diff --git a/test/Makefile b/test/Makefile
index 009e6de0..03282a78 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -5,7 +5,7 @@
 SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 SRC_DIR = $(PWD)/../src
-PROJECT_SOURCES = project.v
+PROJECT_SOURCES = tt_um_JorgeArias8644.v alu_1bit.v alu_8bit.v mux2.v mux4.v xor3a1n.v CLA.v
 
 ifneq ($(GATES),yes)
 
diff --git a/test/tb.v b/test/tb.v
index e4f2f97a..212322b3 100644
--- a/test/tb.v
+++ b/test/tb.v
@@ -24,7 +24,7 @@ module tb ();
   wire [7:0] uio_oe;
 
   // Replace tt_um_example with your module name:
-  tt_um_example user_project (
+  tt_um_JorgeArias8644 user_project (
       .ui_in  (ui_in),    // Dedicated inputs
       .uo_out (uo_out),   // Dedicated outputs
       .uio_in (uio_in),   // IOs: Input path