From 608165d03927533ca95fab6bdcbcf8ca3184077d Mon Sep 17 00:00:00 2001 From: Jorge Marques Date: Mon, 18 Aug 2025 14:56:14 +0200 Subject: [PATCH 1/2] fix: ad4062: coraz7s: Wrong constraints por name The ports have been previously renamed to match the I2C variant. Signed-off-by: Jorge Marques --- .../ad4062_ardz/coraz7s/system_constr.xdc | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/projects/ad4062_ardz/coraz7s/system_constr.xdc b/projects/ad4062_ardz/coraz7s/system_constr.xdc index 0ae77d85c74..9ef3bf57bdb 100644 --- a/projects/ad4062_ardz/coraz7s/system_constr.xdc +++ b/projects/ad4062_ardz/coraz7s/system_constr.xdc @@ -11,14 +11,14 @@ set i3c_clk clk_fpga_0 # Input data driven the peripherals toggles every 4 cycles max (PP) of the capture clock # gets registered by rx_reg -set_multicycle_path -from [get_ports i3c_sda] -to [get_clocks $i3c_clk] -setup 4 -set_multicycle_path -from [get_ports i3c_sda] -to [get_clocks $i3c_clk] -hold 3 +set_multicycle_path -from [get_ports iic_ard_sda] -to [get_clocks $i3c_clk] -setup 4 +set_multicycle_path -from [get_ports iic_ard_sda] -to [get_clocks $i3c_clk] -hold 3 # Output data toggles every 2 cycles max of the capture clock (PP) -set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_sda] -setup 2 -set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_sda] -hold 1 -set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_scl] -setup 2 -set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_scl] -hold 1 +set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports iic_ard_sda] -setup 2 +set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports iic_ard_sda] -hold 1 +set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports iic_ard_scl] -setup 2 +set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports iic_ard_scl] -hold 1 # Notes # tcr/tcf rising/fall time for SCL is 150e06 * 1 / fSCL, at fSCL = 12.5 MHz => 12ns, at fSCL = 6.25 MHz, 24ns. @@ -29,11 +29,11 @@ set tsco_max 12; set tsco_min 8; set trc_dly_max 1; set trc_dly_min 0; -set_input_delay -clock $i3c_clk -max [expr $tsco_max + $trc_dly_max] [get_ports i3c_sda] -set_input_delay -clock $i3c_clk -min [expr $tsco_min + $trc_dly_min] [get_ports i3c_sda] +set_input_delay -clock $i3c_clk -max [expr $tsco_max + $trc_dly_max] [get_ports iic_ard_sda] +set_input_delay -clock $i3c_clk -min [expr $tsco_min + $trc_dly_min] [get_ports iic_ard_sda] set tsu 2; set thd 0; -set_output_delay -clock $i3c_clk -max [expr $trc_dly_max + $tsu] [get_ports i3c_sda] -set_output_delay -clock $i3c_clk -min [expr $trc_dly_min - $thd] [get_ports i3c_sda] -set_output_delay -clock $i3c_clk -max [expr $trc_dly_max + $tsu] [get_ports i3c_scl] -set_output_delay -clock $i3c_clk -min [expr $trc_dly_min - $thd] [get_ports i3c_scl] +set_output_delay -clock $i3c_clk -max [expr $trc_dly_max + $tsu] [get_ports iic_ard_sda] +set_output_delay -clock $i3c_clk -min [expr $trc_dly_min - $thd] [get_ports iic_ard_sda] +set_output_delay -clock $i3c_clk -max [expr $trc_dly_max + $tsu] [get_ports iic_ard_scl] +set_output_delay -clock $i3c_clk -min [expr $trc_dly_min - $thd] [get_ports iic_ard_scl] From 3c432fc8c638bddf17814b8ee7b1f484c4ffd652 Mon Sep 17 00:00:00 2001 From: Jorge Marques Date: Mon, 18 Aug 2025 15:09:20 +0200 Subject: [PATCH 2/2] fix: library/i3c_controller: associate reset_n with s_axi_aclk To solve 'Reset pin is connected to asynchronous reset source', may not solve asynchronous use case, currently unused. Signed-off-by: Jorge Marques --- .../i3c_controller_host_interface_ip.tcl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_ip.tcl b/library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_ip.tcl index cee5d4809fa..dc50aa57457 100644 --- a/library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_ip.tcl +++ b/library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_ip.tcl @@ -97,6 +97,8 @@ adi_set_ports_dependency "offload_trigger" \ set cc [ipx::current_core] +ipx::associate_bus_interfaces -clock s_axi_aclk -reset reset_n $cc + ## ID set_property -dict [list \ "value_validation_type" "range_long" \