Skip to content

Commit 8979778

Browse files
StancaPopStancaPop
committed
cn0577: Initial commit
Signed-off-by: Stanca Pop <[email protected]>
1 parent 483e57f commit 8979778

File tree

12 files changed

+954
-0
lines changed

12 files changed

+954
-0
lines changed

‎testbenches/project/cn0577/Makefile

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
####################################################################################
2+
####################################################################################
3+
## Copyright (C) 2025 Analog Devices, Inc.
4+
####################################################################################
5+
####################################################################################
6+
7+
# Makeincludes
8+
include ../../../scripts/make_tb_path.mk
9+
include $(TB_LIBRARY_PATH)/includes/Makeinclude_common.mk
10+
include $(TB_LIBRARY_PATH)/includes/Makeinclude_dmac.mk
11+
include $(TB_LIBRARY_PATH)/includes/Makeinclude_converter.mk
12+
include $(TB_LIBRARY_PATH)/includes/Makeinclude_pwm_gen.mk
13+
14+
# Remaining test-bench dependencies except test programs
15+
16+
SV_DEPS += cn0577_environment.sv
17+
18+
LIB_DEPS += axi_pwm_gen
19+
LIB_DEPS += axi_dmac
20+
LIB_DEPS += axi_ltc2387
21+
22+
# default test programs
23+
# Format is: <test name>
24+
TP := $(notdir $(basename $(wildcard tests/*.sv)))
25+
26+
# config files should have the following format
27+
# cfg_<param1>_<param2>.tcl
28+
CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl))
29+
30+
# List of tests and configuration combinations that has to be run
31+
# Format is: <configuration>:<test name>
32+
TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(addprefix $(cfg):, $(TP)))
33+
34+
include $(ADI_TB_DIR)/scripts/project-sim.mk
35+
36+
# usage :
37+
#
38+
# run specific test on a specific configuration in gui mode
39+
# make CFG=cfg1 TST=test_program MODE=gui
40+
#
41+
# run all test from a configuration
42+
# make cfg1
43+
44+
####################################################################################
45+
####################################################################################

‎testbenches/project/cn0577/README.md

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
Usage :
2+
3+
Run all tests in batch mode:
4+
5+
make
6+
7+
8+
Run all tests in GUI mode:
9+
10+
make MODE=gui
11+
12+
13+
Run specific test on a specific configuration in gui mode:
14+
15+
make CFG=<name of cfg> TST=<name of test> MODE=gui
16+
17+
18+
Run all test from a configuration:
19+
20+
make <name of cfg>
21+
22+
23+
Where:
24+
25+
* <name of cfg> is a file from the cfgs directory without the tcl extension of format cfg\*
26+
* <name of test> is a file from the tests directory without the tcl extension
27+

‎testbenches/project/cn0577/cfgs/cfg_1lane_16b.tcl

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
global ad_project_params
2+
3+
set ad_project_params(TWOLANES) 0
4+
set ad_project_params(ADC_RES) 16

‎testbenches/project/cn0577/cfgs/cfg_1lane_18b.tcl

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
global ad_project_params
2+
3+
set ad_project_params(TWOLANES) 0
4+
set ad_project_params(ADC_RES) 18

‎testbenches/project/cn0577/cfgs/cfg_2lanes_16b.tcl

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
global ad_project_params
2+
3+
set ad_project_params(TWOLANES) 1
4+
set ad_project_params(ADC_RES) 16

‎testbenches/project/cn0577/cfgs/cfg_2lanes_18b.tcl

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
global ad_project_params
2+
3+
set ad_project_params(TWOLANES) 1
4+
set ad_project_params(ADC_RES) 18

‎testbenches/project/cn0577/cn0577_environment.sv

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,43 @@
1+
// ***************************************************************************
2+
// ***************************************************************************
3+
// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
4+
//
5+
// In this HDL repository, there are many different and unique modules, consisting
6+
// of various HDL (Verilog or VHDL) components. The individual modules are
7+
// developed independently, and may be accompanied by separate and unique license
8+
// terms.
9+
//
10+
// The user should read each of these license terms, and understand the
11+
// freedoms and responsibilities that he or she has by using this source/core.
12+
//
13+
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
14+
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
15+
// A PARTICULAR PURPOSE.
16+
//
17+
// Redistribution and use of source or resulting binaries, with or without modification
18+
// of this file, are permitted under one of the following two license terms:
19+
//
20+
// 1. The GNU General Public License version 2 as published by the
21+
// Free Software Foundation, which can be found in the top level directory
22+
// of this repository (LICENSE_GPL2), and also online at:
23+
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
24+
//
25+
// OR
26+
//
27+
// 2. An ADI specific BSD license, which can be found in the top level directory
28+
// of this repository (LICENSE_ADIBSD), and also on-line at:
29+
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
30+
// This will allow to generate bit files and not release the source code,
31+
// as long as it attaches to an ADI device.
32+
//
33+
// ***************************************************************************
34+
// ***************************************************************************
35+
36+
`include "utils.svh"
37+
38+
package cn0577_environment_pkg;
39+
40+
import logger_pkg::*;
41+
import adi_environment_pkg::*;
42+
43+
endpackage

‎testbenches/project/cn0577/system_bd.tcl

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,62 @@
1+
# ***************************************************************************
2+
# ***************************************************************************
3+
# Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
4+
#
5+
# In this HDL repository, there are many different and unique modules, consisting
6+
# of various HDL (Verilog or VHDL) components. The individual modules are
7+
# developed independently, and may be accompanied by separate and unique license
8+
# terms.
9+
#
10+
# The user should read each of these license terms, and understand the
11+
# freedoms and responsibilities that he or she has by using this source/core.
12+
#
13+
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
14+
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
15+
# A PARTICULAR PURPOSE.
16+
#
17+
# Redistribution and use of source or resulting binaries, with or without modification
18+
# of this file, are permitted under one of the following two license terms:
19+
#
20+
# 1. The GNU General Public License version 2 as published by the
21+
# Free Software Foundation, which can be found in the top level directory
22+
# of this repository (LICENSE_GPL2), and also online at:
23+
# <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
24+
#
25+
# OR
26+
#
27+
# 2. An ADI specific BSD license, which can be found in the top level directory
28+
# of this repository (LICENSE_ADIBSD), and also on-line at:
29+
# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
30+
# This will allow to generate bit files and not release the source code,
31+
# as long as it attaches to an ADI device.
32+
#
33+
# ***************************************************************************
34+
# ***************************************************************************
35+
36+
global ad_project_params
37+
38+
# system level parameters
39+
set TWOLANES $ad_project_params(TWOLANES)
40+
set ADC_RES $ad_project_params(ADC_RES)
41+
42+
adi_project_files [list \
43+
"$ad_hdl_dir/library/common/ad_iobuf.v" \
44+
]
45+
46+
#
47+
# Block design under test
48+
#
49+
50+
source $ad_hdl_dir/projects/cn0577/common/cn0577_bd.tcl
51+
52+
set BA_AXI_LTC2387 0x44A00000
53+
set_property offset $BA_AXI_LTC2387 [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ltc2387}]
54+
adi_sim_add_define "AXI_LTC2387_BA=[format "%d" ${BA_AXI_LTC2387}]"
55+
56+
set BA_DMA 0x44A30000
57+
set_property offset $BA_DMA [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ltc2387_dma}]
58+
adi_sim_add_define "AXI_LTC2387_DMA_BA=[format "%d" ${BA_DMA}]"
59+
60+
set BA_PWM 0x44A60000
61+
set_property offset $BA_PWM [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_pwm_gen}]
62+
adi_sim_add_define "AXI_PWM_GEN_BA=[format "%d" ${BA_PWM}]"

‎testbenches/project/cn0577/system_project.tcl

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,42 @@
1+
source ../../../scripts/adi_sim.tcl
2+
3+
if {$argc < 1} {
4+
puts "Expecting at least one argument that specifies the test configuration"
5+
exit 1
6+
} else {
7+
set cfg_file [lindex $argv 0]
8+
}
9+
10+
# Read common config file
11+
source "cfgs/${cfg_file}"
12+
13+
# Set the project name
14+
set project_name [file rootname $cfg_file]
15+
16+
# Set project params
17+
global ad_project_params
18+
19+
set TWOLANES $ad_project_params(TWOLANES)
20+
set ADC_RES $ad_project_params(ADC_RES)
21+
22+
# Set to use SmartConnect or AXI Interconnect
23+
set use_smartconnect 1
24+
25+
# Create the project
26+
adi_sim_project_xilinx $project_name "xc7z007sclg400-1"
27+
28+
source $ad_tb_dir/library/includes/sp_include_dmac.tcl
29+
source $ad_tb_dir/library/includes/sp_include_pwm_gen.tcl
30+
31+
# Add test files to the project
32+
adi_sim_project_files [list \
33+
"$ad_tb_dir/library/regmaps/adi_regmap_adc_pkg.sv" \
34+
"$ad_tb_dir/library/regmaps/adi_regmap_common_pkg.sv" \
35+
"cn0577_environment.sv" \
36+
"tests/test_program.sv" \
37+
]
38+
39+
#set a default test program
40+
adi_sim_add_define "TEST_PROGRAM=test_program"
41+
42+
adi_sim_generate $project_name

‎testbenches/project/cn0577/system_tb.sv

Lines changed: 152 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,152 @@
1+
// ***************************************************************************
2+
// ***************************************************************************
3+
// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
4+
//
5+
// In this HDL repository, there are many different and unique modules, consisting
6+
// of various HDL (Verilog or VHDL) components. The individual modules are
7+
// developed independently, and may be accompanied by separate and unique license
8+
// terms.
9+
//
10+
// The user should read each of these license terms, and understand the
11+
// freedoms and responsibilities that he or she has by using this source/core.
12+
//
13+
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
14+
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
15+
// A PARTICULAR PURPOSE.
16+
//
17+
// Redistribution and use of source or resulting binaries, with or without modification
18+
// of this file, are permitted under one of the following two license terms:
19+
//
20+
// 1. The GNU General Public License version 2 as published by the
21+
// Free Software Foundation, which can be found in the top level directory
22+
// of this repository (LICENSE_GPL2), and also online at:
23+
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
24+
//
25+
// OR
26+
//
27+
// 2. An ADI specific BSD license, which can be found in the top level directory
28+
// of this repository (LICENSE_ADIBSD), and also on-line at:
29+
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
30+
// This will allow to generate bit files and not release the source code,
31+
// as long as it attaches to an ADI device.
32+
//
33+
// ***************************************************************************
34+
// ***************************************************************************
35+
36+
`timescale 1ns/1ps
37+
38+
`include "utils.svh"
39+
40+
module system_tb();
41+
42+
parameter ID = 0;
43+
parameter FPGA_TECHNOLOGY = 1;
44+
parameter IO_DELAY_GROUP = "adc_if_delay_group";
45+
parameter DELAY_REFCLK_FREQUENCY = 200;
46+
47+
// dco delay compared to the reference clk
48+
localparam DCO_DELAY = 12;
49+
50+
// reg signals
51+
52+
reg ref_clk = 1'b0;
53+
reg dco_init = 1'b0;
54+
reg cnv_out = 1'b0;
55+
reg clk_gate = 1'b0;
56+
reg dco_p;
57+
reg dco_n;
58+
reg da_p = 1'b0;
59+
reg da_n = 1'b0;
60+
reg db_p = 1'b0;
61+
reg db_n = 1'b0;
62+
63+
// dma interface
64+
65+
wire adc_valid;
66+
wire [`ADC_RES-1:0] adc_data;
67+
reg adc_dovf = 1'b0;
68+
69+
// axi interface
70+
71+
reg s_axi_aclk = 1'b0;
72+
reg s_axi_aresetn = 1'b0;
73+
reg s_axi_awvalid = 1'b0;
74+
reg [15:0] s_axi_awaddr = 16'b0;
75+
wire s_axi_awready;
76+
reg s_axi_wvalid = 1'b0;
77+
reg [31:0] s_axi_wdata = 32'b0;
78+
reg [ 3:0] s_axi_wstrb = 4'b0;
79+
wire s_axi_wready;
80+
wire s_axi_bvalid;
81+
wire [ 1:0] s_axi_bresp;
82+
reg s_axi_bready = 1'b0;
83+
reg s_axi_arvalid = 1'b0;
84+
reg [15:0] s_axi_araddr = 1'b0;
85+
wire s_axi_arready;
86+
wire s_axi_rvalid;
87+
wire [ 1:0] s_axi_rresp;
88+
wire [31:0] s_axi_rdata;
89+
reg s_axi_rready = 1'b0;
90+
reg [ 2:0] s_axi_awprot = 3'b0;
91+
reg [ 2:0] s_axi_arprot = 3'b0;
92+
93+
// local wires and registers
94+
95+
wire cnv;
96+
reg dco = 1'b0;
97+
98+
integer cnv_count = 0;
99+
100+
// test bench variables
101+
102+
always #25 ref_clk = ~ref_clk;
103+
//always #2.564 ref_clk = ~ref_clk;
104+
105+
// ---------------------------------------------------------------------------
106+
// Creating a "gate" through which the data clock can run (and only then)
107+
// ---------------------------------------------------------------------------
108+
always @ (*) begin
109+
if (clk_gate == 1'b1) begin
110+
dco_init = ref_clk;
111+
end else begin
112+
dco_init = 1'b0;
113+
end
114+
end
115+
116+
initial begin
117+
s_axi_aresetn <= 1'b0;
118+
repeat(10) @(posedge s_axi_aclk);
119+
s_axi_aresetn <= 1'b1;
120+
end
121+
// Data clocks generation
122+
// ---------------------------------------------------------------------------
123+
124+
always @ (dco_init) begin
125+
dco_p <= #DCO_DELAY dco_init;
126+
dco_n <= #DCO_DELAY ~dco_init;
127+
end
128+
129+
`TEST_PROGRAM test(
130+
.ref_clk (ref_clk),
131+
.clk_gate (clk_gate),
132+
.dco_in (dco_init),
133+
.da_p (da_p),
134+
.da_n (da_n),
135+
.db_p (db_p),
136+
.db_n (db_n),
137+
.cnv (cnv));
138+
139+
test_harness `TH (
140+
.ref_clk (ref_clk),
141+
.sampling_clk (sampling_clk),
142+
.dco_p (dco_p),
143+
.dco_n (dco_n),
144+
.cnv (cnv),
145+
.da_n (da_n),
146+
.da_p (da_p),
147+
.db_n (db_n),
148+
.db_p (db_p),
149+
.clk_gate (clk_gate));
150+
151+
endmodule
152+

0 commit comments

Comments
 (0)