From 897977840651099672618ab0992ab2337c00bca0 Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Thu, 22 May 2025 11:09:11 +0300 Subject: [PATCH] cn0577: Initial commit Signed-off-by: Stanca Pop --- testbenches/project/cn0577/Makefile | 45 ++ testbenches/project/cn0577/README.md | 27 ++ .../project/cn0577/cfgs/cfg_1lane_16b.tcl | 4 + .../project/cn0577/cfgs/cfg_1lane_18b.tcl | 4 + .../project/cn0577/cfgs/cfg_2lanes_16b.tcl | 4 + .../project/cn0577/cfgs/cfg_2lanes_18b.tcl | 4 + .../project/cn0577/cn0577_environment.sv | 43 ++ testbenches/project/cn0577/system_bd.tcl | 62 +++ testbenches/project/cn0577/system_project.tcl | 42 ++ testbenches/project/cn0577/system_tb.sv | 152 +++++++ .../project/cn0577/tests/test_program.sv | 407 ++++++++++++++++++ .../project/cn0577/waves/system_tb_behav.wcfg | 160 +++++++ 12 files changed, 954 insertions(+) create mode 100644 testbenches/project/cn0577/Makefile create mode 100644 testbenches/project/cn0577/README.md create mode 100644 testbenches/project/cn0577/cfgs/cfg_1lane_16b.tcl create mode 100644 testbenches/project/cn0577/cfgs/cfg_1lane_18b.tcl create mode 100644 testbenches/project/cn0577/cfgs/cfg_2lanes_16b.tcl create mode 100644 testbenches/project/cn0577/cfgs/cfg_2lanes_18b.tcl create mode 100644 testbenches/project/cn0577/cn0577_environment.sv create mode 100644 testbenches/project/cn0577/system_bd.tcl create mode 100644 testbenches/project/cn0577/system_project.tcl create mode 100644 testbenches/project/cn0577/system_tb.sv create mode 100644 testbenches/project/cn0577/tests/test_program.sv create mode 100644 testbenches/project/cn0577/waves/system_tb_behav.wcfg diff --git a/testbenches/project/cn0577/Makefile b/testbenches/project/cn0577/Makefile new file mode 100644 index 00000000..3bdb4838 --- /dev/null +++ b/testbenches/project/cn0577/Makefile @@ -0,0 +1,45 @@ +#################################################################################### +#################################################################################### +## Copyright (C) 2025 Analog Devices, Inc. +#################################################################################### +#################################################################################### + +# Makeincludes +include ../../../scripts/make_tb_path.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_common.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_dmac.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_converter.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_pwm_gen.mk + +# Remaining test-bench dependencies except test programs + +SV_DEPS += cn0577_environment.sv + +LIB_DEPS += axi_pwm_gen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_ltc2387 + +# default test programs +# Format is: +TP := $(notdir $(basename $(wildcard tests/*.sv))) + +# config files should have the following format +# cfg__.tcl +CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl)) + +# List of tests and configuration combinations that has to be run +# Format is: : +TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(addprefix $(cfg):, $(TP))) + +include $(ADI_TB_DIR)/scripts/project-sim.mk + +# usage : +# +# run specific test on a specific configuration in gui mode +# make CFG=cfg1 TST=test_program MODE=gui +# +# run all test from a configuration +# make cfg1 + +#################################################################################### +#################################################################################### diff --git a/testbenches/project/cn0577/README.md b/testbenches/project/cn0577/README.md new file mode 100644 index 00000000..f1495cb4 --- /dev/null +++ b/testbenches/project/cn0577/README.md @@ -0,0 +1,27 @@ +Usage : + +Run all tests in batch mode: + + make + + +Run all tests in GUI mode: + + make MODE=gui + + +Run specific test on a specific configuration in gui mode: + + make CFG= TST= MODE=gui + + +Run all test from a configuration: + + make + + +Where: + + * is a file from the cfgs directory without the tcl extension of format cfg\* + * is a file from the tests directory without the tcl extension + diff --git a/testbenches/project/cn0577/cfgs/cfg_1lane_16b.tcl b/testbenches/project/cn0577/cfgs/cfg_1lane_16b.tcl new file mode 100644 index 00000000..d45a948a --- /dev/null +++ b/testbenches/project/cn0577/cfgs/cfg_1lane_16b.tcl @@ -0,0 +1,4 @@ +global ad_project_params + +set ad_project_params(TWOLANES) 0 +set ad_project_params(ADC_RES) 16 diff --git a/testbenches/project/cn0577/cfgs/cfg_1lane_18b.tcl b/testbenches/project/cn0577/cfgs/cfg_1lane_18b.tcl new file mode 100644 index 00000000..e77795d9 --- /dev/null +++ b/testbenches/project/cn0577/cfgs/cfg_1lane_18b.tcl @@ -0,0 +1,4 @@ +global ad_project_params + +set ad_project_params(TWOLANES) 0 +set ad_project_params(ADC_RES) 18 diff --git a/testbenches/project/cn0577/cfgs/cfg_2lanes_16b.tcl b/testbenches/project/cn0577/cfgs/cfg_2lanes_16b.tcl new file mode 100644 index 00000000..cabe5582 --- /dev/null +++ b/testbenches/project/cn0577/cfgs/cfg_2lanes_16b.tcl @@ -0,0 +1,4 @@ +global ad_project_params + +set ad_project_params(TWOLANES) 1 +set ad_project_params(ADC_RES) 16 diff --git a/testbenches/project/cn0577/cfgs/cfg_2lanes_18b.tcl b/testbenches/project/cn0577/cfgs/cfg_2lanes_18b.tcl new file mode 100644 index 00000000..846aa928 --- /dev/null +++ b/testbenches/project/cn0577/cfgs/cfg_2lanes_18b.tcl @@ -0,0 +1,4 @@ +global ad_project_params + +set ad_project_params(TWOLANES) 1 +set ad_project_params(ADC_RES) 18 diff --git a/testbenches/project/cn0577/cn0577_environment.sv b/testbenches/project/cn0577/cn0577_environment.sv new file mode 100644 index 00000000..a804b4e9 --- /dev/null +++ b/testbenches/project/cn0577/cn0577_environment.sv @@ -0,0 +1,43 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" + +package cn0577_environment_pkg; + + import logger_pkg::*; + import adi_environment_pkg::*; + +endpackage diff --git a/testbenches/project/cn0577/system_bd.tcl b/testbenches/project/cn0577/system_bd.tcl new file mode 100644 index 00000000..8b2ccced --- /dev/null +++ b/testbenches/project/cn0577/system_bd.tcl @@ -0,0 +1,62 @@ +# *************************************************************************** +# *************************************************************************** +# Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +# +# In this HDL repository, there are many different and unique modules, consisting +# of various HDL (Verilog or VHDL) components. The individual modules are +# developed independently, and may be accompanied by separate and unique license +# terms. +# +# The user should read each of these license terms, and understand the +# freedoms and responsibilities that he or she has by using this source/core. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. +# +# Redistribution and use of source or resulting binaries, with or without modification +# of this file, are permitted under one of the following two license terms: +# +# 1. The GNU General Public License version 2 as published by the +# Free Software Foundation, which can be found in the top level directory +# of this repository (LICENSE_GPL2), and also online at: +# +# +# OR +# +# 2. An ADI specific BSD license, which can be found in the top level directory +# of this repository (LICENSE_ADIBSD), and also on-line at: +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +# This will allow to generate bit files and not release the source code, +# as long as it attaches to an ADI device. +# +# *************************************************************************** +# *************************************************************************** + +global ad_project_params + +# system level parameters +set TWOLANES $ad_project_params(TWOLANES) +set ADC_RES $ad_project_params(ADC_RES) + +adi_project_files [list \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ +] + +# +# Block design under test +# + +source $ad_hdl_dir/projects/cn0577/common/cn0577_bd.tcl + +set BA_AXI_LTC2387 0x44A00000 +set_property offset $BA_AXI_LTC2387 [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ltc2387}] +adi_sim_add_define "AXI_LTC2387_BA=[format "%d" ${BA_AXI_LTC2387}]" + +set BA_DMA 0x44A30000 +set_property offset $BA_DMA [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ltc2387_dma}] +adi_sim_add_define "AXI_LTC2387_DMA_BA=[format "%d" ${BA_DMA}]" + +set BA_PWM 0x44A60000 +set_property offset $BA_PWM [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_pwm_gen}] +adi_sim_add_define "AXI_PWM_GEN_BA=[format "%d" ${BA_PWM}]" diff --git a/testbenches/project/cn0577/system_project.tcl b/testbenches/project/cn0577/system_project.tcl new file mode 100644 index 00000000..8da4d719 --- /dev/null +++ b/testbenches/project/cn0577/system_project.tcl @@ -0,0 +1,42 @@ +source ../../../scripts/adi_sim.tcl + +if {$argc < 1} { + puts "Expecting at least one argument that specifies the test configuration" + exit 1 +} else { + set cfg_file [lindex $argv 0] +} + +# Read common config file +source "cfgs/${cfg_file}" + +# Set the project name +set project_name [file rootname $cfg_file] + +# Set project params +global ad_project_params + +set TWOLANES $ad_project_params(TWOLANES) +set ADC_RES $ad_project_params(ADC_RES) + +# Set to use SmartConnect or AXI Interconnect +set use_smartconnect 1 + +# Create the project +adi_sim_project_xilinx $project_name "xc7z007sclg400-1" + +source $ad_tb_dir/library/includes/sp_include_dmac.tcl +source $ad_tb_dir/library/includes/sp_include_pwm_gen.tcl + +# Add test files to the project +adi_sim_project_files [list \ + "$ad_tb_dir/library/regmaps/adi_regmap_adc_pkg.sv" \ + "$ad_tb_dir/library/regmaps/adi_regmap_common_pkg.sv" \ + "cn0577_environment.sv" \ + "tests/test_program.sv" \ +] + +#set a default test program +adi_sim_add_define "TEST_PROGRAM=test_program" + +adi_sim_generate $project_name diff --git a/testbenches/project/cn0577/system_tb.sv b/testbenches/project/cn0577/system_tb.sv new file mode 100644 index 00000000..03207211 --- /dev/null +++ b/testbenches/project/cn0577/system_tb.sv @@ -0,0 +1,152 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +`include "utils.svh" + +module system_tb(); + + parameter ID = 0; + parameter FPGA_TECHNOLOGY = 1; + parameter IO_DELAY_GROUP = "adc_if_delay_group"; + parameter DELAY_REFCLK_FREQUENCY = 200; + + // dco delay compared to the reference clk + localparam DCO_DELAY = 12; + + // reg signals + + reg ref_clk = 1'b0; + reg dco_init = 1'b0; + reg cnv_out = 1'b0; + reg clk_gate = 1'b0; + reg dco_p; + reg dco_n; + reg da_p = 1'b0; + reg da_n = 1'b0; + reg db_p = 1'b0; + reg db_n = 1'b0; + + // dma interface + + wire adc_valid; + wire [`ADC_RES-1:0] adc_data; + reg adc_dovf = 1'b0; + + // axi interface + + reg s_axi_aclk = 1'b0; + reg s_axi_aresetn = 1'b0; + reg s_axi_awvalid = 1'b0; + reg [15:0] s_axi_awaddr = 16'b0; + wire s_axi_awready; + reg s_axi_wvalid = 1'b0; + reg [31:0] s_axi_wdata = 32'b0; + reg [ 3:0] s_axi_wstrb = 4'b0; + wire s_axi_wready; + wire s_axi_bvalid; + wire [ 1:0] s_axi_bresp; + reg s_axi_bready = 1'b0; + reg s_axi_arvalid = 1'b0; + reg [15:0] s_axi_araddr = 1'b0; + wire s_axi_arready; + wire s_axi_rvalid; + wire [ 1:0] s_axi_rresp; + wire [31:0] s_axi_rdata; + reg s_axi_rready = 1'b0; + reg [ 2:0] s_axi_awprot = 3'b0; + reg [ 2:0] s_axi_arprot = 3'b0; + + // local wires and registers + + wire cnv; + reg dco = 1'b0; + + integer cnv_count = 0; + + // test bench variables + + always #25 ref_clk = ~ref_clk; + //always #2.564 ref_clk = ~ref_clk; + + // --------------------------------------------------------------------------- + // Creating a "gate" through which the data clock can run (and only then) + // --------------------------------------------------------------------------- + always @ (*) begin + if (clk_gate == 1'b1) begin + dco_init = ref_clk; + end else begin + dco_init = 1'b0; + end + end + + initial begin + s_axi_aresetn <= 1'b0; + repeat(10) @(posedge s_axi_aclk); + s_axi_aresetn <= 1'b1; + end + // Data clocks generation + // --------------------------------------------------------------------------- + + always @ (dco_init) begin + dco_p <= #DCO_DELAY dco_init; + dco_n <= #DCO_DELAY ~dco_init; + end + + `TEST_PROGRAM test( + .ref_clk (ref_clk), + .clk_gate (clk_gate), + .dco_in (dco_init), + .da_p (da_p), + .da_n (da_n), + .db_p (db_p), + .db_n (db_n), + .cnv (cnv)); + + test_harness `TH ( + .ref_clk (ref_clk), + .sampling_clk (sampling_clk), + .dco_p (dco_p), + .dco_n (dco_n), + .cnv (cnv), + .da_n (da_n), + .da_p (da_p), + .db_n (db_n), + .db_p (db_p), + .clk_gate (clk_gate)); + +endmodule + diff --git a/testbenches/project/cn0577/tests/test_program.sv b/testbenches/project/cn0577/tests/test_program.sv new file mode 100644 index 00000000..92c887fe --- /dev/null +++ b/testbenches/project/cn0577/tests/test_program.sv @@ -0,0 +1,407 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" + +import logger_pkg::*; +import test_harness_env_pkg::*; +import adi_regmap_pkg::*; +import adi_regmap_adc_pkg::*; +import adi_regmap_common_pkg::*; +import adi_regmap_dmac_pkg::*; +import adi_regmap_pwm_gen_pkg::*; +import axi_vip_pkg::*; +import axi4stream_vip_pkg::*; +import dmac_api_pkg::*; +import pwm_gen_api_pkg::*; +import cn0577_environment_pkg::*; + +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +localparam NUM_OF_TRANSFERS = 16; + +//--------------------------------------------------------------------------- +// SPI Engine configuration parameters +//--------------------------------------------------------------------------- + +program test_program ( + input ref_clk, + input clk_gate, + input dco_in, + output da_n, + output da_p, + output db_n, + output db_p, + output reg dco_p, + output reg dco_n, + output cnv); + +timeunit 1ns; +timeprecision 1ps; + +typedef enum {DATA_MODE_RANDOM, DATA_MODE_RAMP, DATA_MODE_PATTERN} offload_test_t; + +test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + +// set to active debug messages +localparam bit DEBUG = 1; + +// dco delay compared to the reference clk +localparam DCO_DELAY = 12; + +pwm_gen_api pwm_api; +dmac_api dma_api; + +// dma interface +wire adc_valid; +wire [`ADC_RES-1:0] adc_data; +reg adc_dovf = 1'b0; + +// -------------------------- +// Wrapper function for AXI read verif +// -------------------------- +task axi_read_v( + input [31:0] raddr, + input [31:0] vdata); + + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); +endtask + +task axi_read( + input [31:0] raddr, + output [31:0] data); + + base_env.mng.sequencer.RegRead32(raddr,data); +endtask + +// -------------------------- +// Wrapper function for AXI write +// -------------------------- +task axi_write( + input [31:0] waddr, + input [31:0] wdata); + + base_env.mng.sequencer.RegWrite32(waddr,wdata); +endtask + +// -------------------------- +// Main procedure +// -------------------------- + +initial begin + + //creating environment + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + pwm_api = new( + "AXI PWM GEN API", + base_env.mng.sequencer, + `AXI_PWM_GEN_BA); + + dma_api = new("DMA API", + base_env.mng.sequencer, + `AXI_LTC2387_DMA_BA); + + setLoggerVerbosity(ADI_VERBOSITY_LOW); + + base_env.start(); + base_env.sys_reset(); + + sanity_test(); + + #100 + + data_acquisition_test(); + + base_env.stop(); + + `INFO(("Test Done"), ADI_VERBOSITY_NONE); + $finish(); + +end + +bit [31:0] dma_data_store_arr [(NUM_OF_TRANSFERS) - 1:0]; +bit transfer_status = 0; +bit [31:0] transfer_cnt; + +//--------------------------------------------------------------------------- +// Transfer Counter +//--------------------------------------------------------------------------- + +initial begin + transfer_cnt = 0; + forever begin + @(posedge cnv); + if (transfer_status) begin + transfer_cnt = transfer_cnt + 1; + end + @(negedge cnv); + end +end + +//--------------------------------------------------------------------------- +// Clk_gate shifted copy +//--------------------------------------------------------------------------- + +localparam int N = (`TWOLANES == 0 && `ADC_RES == 16) ? 16 : + (`TWOLANES == 0 && `ADC_RES == 18) ? 18 : + (`TWOLANES == 1 && `ADC_RES == 16) ? 8 : + (`TWOLANES == 1 && `ADC_RES == 18) ? 10 : + -1; // Error case +parameter int num_of_dco = N / 2; + +initial begin + forever begin + @(posedge dco_in, negedge dco_in) begin + #1 + dco_p <= dco_in; + dco_n <= ~dco_in; + end + end + end + +//--------------------------------------------------------------------------- +// Data store +//--------------------------------------------------------------------------- + +reg [`ADC_RES-1:0] data_gen = 'h3a5a5; +reg [`ADC_RES-1:0] data_shift = 'h0; + +reg r_da_p = 1'b0; +reg r_da_n = 1'b0; +reg r_db_p = 1'b0; +reg r_db_n = 1'b0; + +assign da_p = r_da_p; +assign da_n = r_da_n; +assign db_p = r_db_p; +assign db_n = r_db_n; + +// --------------------------------------------------------------------------- +// Output data ready +// --------------------------------------------------------------------------- + +initial begin + forever begin + @ (posedge dco_in, negedge dco_in) begin + if (`TWOLANES == 1) begin + r_da_p = data_shift[`ADC_RES - 1]; + r_da_n = ~data_shift[`ADC_RES - 1]; + r_db_p = data_shift[`ADC_RES - 2]; + r_db_n = ~data_shift[`ADC_RES - 2]; + data_shift = data_shift << 2; + end else begin + r_da_p = data_shift[`ADC_RES - 1]; + r_da_n = ~data_shift[`ADC_RES - 1]; + data_shift = data_shift << 1; + end + end + end +end + +initial begin + forever begin + @ (posedge cnv) begin + data_shift = data_gen; + end + end +end + +// --------------------------------------------------------------------------- +// Generating expected data +// --------------------------------------------------------------------------- + +initial begin + forever begin + @(posedge dco_in); + if (transfer_status) begin + if (`ADC_RES == 16) begin + if (`TWOLANES == 0) begin + if (transfer_cnt[0]) begin + dma_data_store_arr[(transfer_cnt - 1) >> 1][15:0] = data_gen; + end else begin + dma_data_store_arr[(transfer_cnt - 1) >> 1][31:16] = data_gen; + end + end else begin + if (transfer_cnt[0]) begin + dma_data_store_arr[(transfer_cnt - 1) >> 1][15:0] = data_gen; + end else begin + dma_data_store_arr[(transfer_cnt - 1) >> 1][31:16] = data_gen; + end + end + end else if (`ADC_RES == 18) begin + if (`TWOLANES == 0) begin + dma_data_store_arr[(transfer_cnt - 1) >> 1] = data_gen; + end else begin + dma_data_store_arr[(transfer_cnt - 1) >> 1] = data_gen; + end + end + end + @(negedge dco_in); + end +end + +//--------------------------------------------------------------------------- +// Sanity test reg interface +//--------------------------------------------------------------------------- + +task sanity_test(); + axi_write (`AXI_LTC2387_BA + GetAddrs(COMMON_REG_SCRATCH), `SET_COMMON_REG_SCRATCH_SCRATCH(32'hDEADBEEF)); + axi_read_v (`AXI_LTC2387_BA + GetAddrs(COMMON_REG_SCRATCH), `SET_COMMON_REG_SCRATCH_SCRATCH(32'hDEADBEEF)); + `INFO(("Sanity Test Done"), ADI_VERBOSITY_LOW); +endtask + +//--------------------------------------------------------------------------- +// Data Acquisition Test +//--------------------------------------------------------------------------- + +reg [31:0] rdata_reg; +bit [31:0] captured_word_arr [(NUM_OF_TRANSFERS) -1 :0]; +bit [31:0] config_wr_SIMPLE = 'h0; // write request sent result +bit [31:0] config_SIMPLE = 'h0; // channel static data setup + +task data_acquisition_test(); + + // Enable all ADC channels + for (int i = 0; i < 4; i=i+1) begin + axi_write (`AXI_LTC2387_BA + i*'h40 + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(32'h00000001)); + end + + // Configure AXI PWM GEN + pwm_api.reset(); // PWM_GEN reset in regmap (ACTIVE HIGH) + + pwm_api.pulse_period_config( + .channel(8'h00), + .period(32'h1A)); + + pwm_api.pulse_width_config( + .channel(8'h00), + .width(32'h01)); + + pwm_api.pulse_period_config( + .channel(8'h01), + .period(32'h1A)); + + pwm_api.pulse_width_config( + .channel(8'h01), + .width(num_of_dco)); + + pwm_api.pulse_offset_config( + .channel(8'h01), + .offset(32'h03)); + + pwm_api.load_config(); // load AXI_PWM_GEN configuration + pwm_api.start(); + `INFO(("AXI_PWM_GEN started"), ADI_VERBOSITY_LOW); + + // Configure DMA + dma_api.enable_dma(); + + dma_api.set_flags( + .cyclic(1'b0), + .tlast(1'b1), + .partial_reporting_en(1'b1)); + + dma_api.set_lengths(((NUM_OF_TRANSFERS)*4)-1,0); + + dma_api.set_dest_addr(`DDR_BA); + + // Configure AXI_LTC2387 + axi_write (`AXI_LTC2387_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(0)); + #5000 + axi_write (`AXI_LTC2387_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1)); + + @(posedge cnv) + #200 + + transfer_status = 1; + + dma_api.transfer_start(); + + wait(transfer_cnt == 2 * NUM_OF_TRANSFERS ); + + #100 + @(negedge cnv); + @(posedge ref_clk); + transfer_status = 0; + + // Stop pwm gen + pwm_api.reset(); + `INFO(("AXI_PWM_GEN stopped"), ADI_VERBOSITY_LOW); + + // Configure axi_ltc2387 + axi_write(`AXI_LTC2387_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1'b1)); //ADC common core out of reset + axi_write(`AXI_LTC2387_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), `SET_ADC_COMMON_REG_ADC_CONFIG_WR_ADC_CONFIG_WR(32'h00002181)); // set static data setup in device's reg 0x21 + axi_read(`AXI_LTC2387_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), config_SIMPLE); // read last config result + `INFO(("Config_SIMPLE is set up, ADC_CONFIG_WR contains 0x%h",config_SIMPLE), ADI_VERBOSITY_LOW); + axi_write(`AXI_LTC2387_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_CTRL), `SET_ADC_COMMON_REG_ADC_CONFIG_CTRL_ADC_CONFIG_CTRL(32'h00000001)); // send WR request + axi_read(`AXI_LTC2387_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_CTRL), config_wr_SIMPLE); // read last config result + `INFO(("Write request sent, ADC_CONFIG_CTRL contains 0x%h",config_wr_SIMPLE), ADI_VERBOSITY_LOW); + + axi_write(`AXI_LTC2387_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_CTRL), `SET_ADC_COMMON_REG_ADC_CONFIG_CTRL_ADC_CONFIG_CTRL(32'h00000000)); // set default control value (no rd/wr request) + axi_read(`AXI_LTC2387_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_CTRL), config_wr_SIMPLE); // read last config result + `INFO(("ADC_CONFIG_CTRL contains 0x%h",config_wr_SIMPLE), ADI_VERBOSITY_LOW); + + axi_write(`AXI_LTC2387_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), `SET_ADC_COMMON_REG_ADC_CONFIG_WR_ADC_CONFIG_WR(32'h00000000)); // set exit from register mode sequence + axi_write(`AXI_LTC2387_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_CTRL), `SET_ADC_COMMON_REG_ADC_CONFIG_CTRL_ADC_CONFIG_CTRL(32'h00000001)); // send WR request + axi_write(`AXI_LTC2387_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_CTRL), `SET_ADC_COMMON_REG_ADC_CONFIG_CTRL_ADC_CONFIG_CTRL(32'h00000000)); // set default control value (no rd/wr request) + + //set HDL config mode + axi_write(`AXI_LTC2387_BA + GetAddrs(ADC_COMMON_REG_CNTRL_3), 'h100); // set default + + #2000 + for (int i=0; i<=((NUM_OF_TRANSFERS) -1); i=i+1) begin + #1 + captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); + end + + `INFO(("captured_word_arr: %x; dma_data_store_arr %x", captured_word_arr, dma_data_store_arr), ADI_VERBOSITY_LOW); + + if (captured_word_arr != dma_data_store_arr) begin + `ERROR(("Data Acquisition Test FAILED")); + end else begin + `INFO(("Data Acquisition Test PASSED"), ADI_VERBOSITY_LOW); + end + +endtask + +endprogram diff --git a/testbenches/project/cn0577/waves/system_tb_behav.wcfg b/testbenches/project/cn0577/waves/system_tb_behav.wcfg new file mode 100644 index 00000000..8590ac87 --- /dev/null +++ b/testbenches/project/cn0577/waves/system_tb_behav.wcfg @@ -0,0 +1,160 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ref_clk + ref_clk + + + clk_gate + clk_gate + + + dco_in + dco_in + + + dco_p + dco_p + + + da_p + da_p + + + db_p + db_p + + + cnv + cnv + + + data_gen[15:0] + data_gen[15:0] + + + data_shift[15:0] + data_shift[15:0] + + + transfer_status + transfer_status + + + da_p_int_s + da_p_int_s + #FFFF00 + true + + + da_n_int_s + da_n_int_s + + + adc_data_da_p[9:0] + adc_data_da_p[9:0] + + + adc_data_da_n[9:0] + adc_data_da_n[9:0] + + + adc_data_db_p[9:0] + adc_data_db_p[9:0] + + + adc_data_db_n[9:0] + adc_data_db_n[9:0] + + + adc_data_int[17:0] + adc_data_int[17:0] + + + adc_valid + adc_valid + + + adc_data[17:0] + adc_data[17:0] + + + if + label + + + dco + dco + + + dco_p + dco_p + + + da_p + da_p + + + da_p_int_s + da_p_int_s + +