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EclecticGriffinEclecticGriffin
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[repo] Bump rust version and dependencies (#2532)
I've bumped the rust version to `1.88` and also updated the versions of our rust dependencies. As this updates `clippy`, that means a bunch of new lints are active now, so I had to go and correct those as well. The vast majority are format string related. Unfortunately that makes for a bit of a big PR.
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‎Cargo.lock

Lines changed: 624 additions & 482 deletions
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‎Cargo.toml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ categories = ["compilers"]
4545
homepage = "https://calyxir.org"
4646
edition = "2024"
4747
version = "0.7.1"
48-
rust-version = "1.85"
48+
rust-version = "1.88"
4949

5050
[workspace.dependencies]
5151
# Internal crates

‎benches/component-sharing.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ fn cell_share_bench(c: &mut Criterion) {
1717
b.iter_batched(
1818
|| {
1919
let name =
20-
format!("benches/component-sharing/{}.futil", name);
20+
format!("benches/component-sharing/{name}.futil");
2121
let bench = Path::new(&name);
2222
let lib = [PathBuf::from(".")];
2323

‎calyx/backend/src/backend_opt.rs

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -54,8 +54,7 @@ impl FromStr for BackendOpt {
5454
.map(|(name, _)| (*name).to_string())
5555
.join(", ");
5656
Err(format!(
57-
"`{}` is not a valid backend.\nValid backends: {}",
58-
input, backend_str
57+
"`{input}` is not a valid backend.\nValid backends: {backend_str}"
5958
))
6059
}
6160
}

‎calyx/backend/src/firrtl.rs

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -185,7 +185,7 @@ fn emit_primitive_extmodule<F: io::Write>(
185185
param_binding: &Binding,
186186
f: &mut F,
187187
) -> io::Result<()> {
188-
writeln!(f, "{}extmodule {}:", SPACING, curr_module_name)?;
188+
writeln!(f, "{SPACING}extmodule {curr_module_name}:")?;
189189
for port in ports {
190190
let port_borrowed = port.borrow();
191191
emit_port(port_borrowed, false, f)?;
@@ -251,16 +251,16 @@ fn get_guard_string(guard: &ir::Guard<ir::Nothing>) -> String {
251251
ir::Guard::Or(l, r) => {
252252
let l_str = get_guard_string(l.as_ref());
253253
let r_str = get_guard_string(r.as_ref());
254-
format!("or({}, {})", l_str, r_str)
254+
format!("or({l_str}, {r_str})")
255255
}
256256
ir::Guard::And(l, r) => {
257257
let l_str = get_guard_string(l.as_ref());
258258
let r_str = get_guard_string(r.as_ref());
259-
format!("and({}, {})", l_str, r_str)
259+
format!("and({l_str}, {r_str})")
260260
}
261261
ir::Guard::Not(g) => {
262262
let g_str = get_guard_string(g);
263-
format!("not({})", g_str)
263+
format!("not({g_str})")
264264
}
265265
ir::Guard::True => String::from(""),
266266
ir::Guard::CompOp(op, l, r) => {
@@ -274,7 +274,7 @@ fn get_guard_string(guard: &ir::Guard<ir::Nothing>) -> String {
274274
ir::PortComp::Geq => "geq",
275275
ir::PortComp::Leq => "leq",
276276
};
277-
format!("{}({}, {})", op_str, l_str, r_str)
277+
format!("{op_str}({l_str}, {r_str})")
278278
}
279279
ir::Guard::Port(port) => get_port_string(&port.borrow(), false),
280280
ir::Guard::Info(_) => {
@@ -293,7 +293,7 @@ fn get_port_string(port: &calyx_ir::Port, is_dst: bool) -> String {
293293
match parent.prototype {
294294
ir::CellType::Constant { val, width: _ } => {
295295
if !is_dst {
296-
format!("UInt({})", val)
296+
format!("UInt({val})")
297297
} else {
298298
unreachable!()
299299
}

‎calyx/backend/src/mlir.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -229,7 +229,7 @@ impl MlirBackend {
229229
.map(|p| format!("%{}.{}", name, p.borrow().name))
230230
.collect::<Vec<_>>()
231231
.join(", ");
232-
write!(f, "{} = ", all_ports)?;
232+
write!(f, "{all_ports} = ")?;
233233
let supports_attrs =
234234
Self::write_prototype_sig(&cell.prototype, name.as_str(), f)?;
235235
if supports_attrs {
@@ -242,7 +242,7 @@ impl MlirBackend {
242242
.map(|p| format!("i{}", p.borrow().width))
243243
.collect::<Vec<_>>()
244244
.join(", ");
245-
writeln!(f, "{}", all_port_widths)
245+
writeln!(f, "{all_port_widths}")
246246
}
247247

248248
/// Format and write an assignment.

‎calyx/backend/src/resources.rs

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -135,7 +135,7 @@ fn estimated_size(count_map: HashMap<(ir::Id, ir::Binding, bool), u32>) {
135135
};
136136
let externalize_name = |name: ir::Id, is_external: bool| {
137137
if is_external {
138-
format!("external {}", name)
138+
format!("external {name}")
139139
} else {
140140
name.to_string()
141141
}
@@ -275,9 +275,6 @@ fn estimated_size(count_map: HashMap<(ir::Id, ir::Binding, bool), u32>) {
275275
_ => (),
276276
}
277277
}
278-
eprintln!("Estimated size in bit(s): {}", estimated_size);
279-
eprintln!(
280-
"Estimated external size in bit(s): {}",
281-
estimated_external_size
282-
);
278+
eprintln!("Estimated size in bit(s): {estimated_size}");
279+
eprintln!("Estimated external size in bit(s): {estimated_external_size}");
283280
}

‎calyx/backend/src/verilog.rs

Lines changed: 18 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -124,16 +124,14 @@ trait LibraryHandlerTrait {
124124
for dir in library_dirs {
125125
let entries = std::fs::read_dir(&dir).map_err(|e| {
126126
Error::invalid_file(format!(
127-
"Error accessing library directory `{:?}`: {}",
128-
dir, e
127+
"Error accessing library directory `{dir:?}`: {e}"
129128
))
130129
})?;
131130

132131
for entry in entries {
133132
let entry = entry.map_err(|e| {
134133
Error::invalid_file(format!(
135-
"Error reading entry in directory `{:?}`: {}",
136-
dir, e
134+
"Error reading entry in directory `{dir:?}`: {e}"
137135
))
138136
})?;
139137
library_paths.push(entry.path());
@@ -419,8 +417,7 @@ impl Backend for VerilogBackend {
419417
morty::build_syntax_tree(&file_list, false, false, true, false)
420418
.map_err(|err| {
421419
Error::write_error(format!(
422-
"Failed to build syntax tree with Morty: {}",
423-
err
420+
"Failed to build syntax tree with Morty: {err}"
424421
))
425422
})?;
426423
let top_module = ctx.entrypoint.to_string();
@@ -437,7 +434,7 @@ impl Backend for VerilogBackend {
437434
true,
438435
false,
439436
)
440-
.map_err(|err| Error::write_error(format!("{}", err)))?;
437+
.map_err(|err| Error::write_error(format!("{err}")))?;
441438
}
442439
// Rewind to the start of the temporary file so that we can read the content
443440
temp_writer.seek(SeekFrom::Start(0)).map_err(|_| {
@@ -454,12 +451,7 @@ impl Backend for VerilogBackend {
454451
let mut final_writer = file.get_write();
455452
final_writer
456453
.write_all(temp_content.as_bytes())
457-
.map_err(|err| {
458-
io::Error::new(
459-
io::ErrorKind::Other,
460-
format!("Write failed: {}", err),
461-
)
462-
})?;
454+
.map_err(|err| io::Error::other(format!("Write failed: {err}")))?;
463455
Ok(())
464456
}
465457
}
@@ -474,7 +466,7 @@ fn emit_prim_inline<F: io::Write>(
474466
if !prim.params.is_empty() {
475467
writeln!(f, " #(")?;
476468
for (idx, param) in prim.params.iter().enumerate() {
477-
write!(f, " parameter {} = 32", param)?;
469+
write!(f, " parameter {param} = 32")?;
478470
if idx != prim.params.len() - 1 {
479471
writeln!(f, ",")?;
480472
} else {
@@ -582,7 +574,7 @@ fn emit_component<F: io::Write>(
582574
if !synthesis_mode {
583575
memory_read_write(comp)
584576
.into_iter()
585-
.try_for_each(|stmt| writeln!(f, "{}", stmt))?;
577+
.try_for_each(|stmt| writeln!(f, "{stmt}"))?;
586578
}
587579

588580
let cells = comp
@@ -593,7 +585,7 @@ fn emit_component<F: io::Write>(
593585
// structure wire declarations
594586
cells.iter().try_for_each(|(name, width, _)| {
595587
let decl = v::Decl::new_logic(name, *width);
596-
writeln!(f, "{};", decl)
588+
writeln!(f, "{decl};")
597589
})?;
598590

599591
// cell instances
@@ -740,9 +732,7 @@ fn cell_instance(cell: &ir::Cell) -> Option<v::Instance> {
740732
param_binding.iter().for_each(|(name, value)| {
741733
if *value > (i32::MAX as u64) {
742734
panic!(
743-
"Parameter value {} for `{}` cannot be represented using 32 bits",
744-
value,
745-
name
735+
"Parameter value {value} for `{name}` cannot be represented using 32 bits"
746736
)
747737
}
748738
inst.add_param(
@@ -835,7 +825,7 @@ fn emit_fsms<F: io::Write>(
835825
collection.into_iter().enumerate()
836826
{
837827
// string representing the new guard on the assignment
838-
let case_guard = format!("{}_s{state}_out", fsm_id);
828+
let case_guard = format!("{fsm_id}_s{state}_out");
839829
let case_guarded_assign_guard = if assignment.guard.is_true() {
840830
case_guard
841831
} else {
@@ -936,12 +926,12 @@ fn emit_fsm_module<F: io::Write>(
936926
if (reset) begin\n state_reg <= s0;\n end\n\
937927
else begin\n state_reg <= state_next;\n\
938928
end\n end\n";
939-
writeln!(f, "{}", always_comb_header)?;
929+
writeln!(f, "{always_comb_header}")?;
940930

941931
// Begin emitting the FSM's transitions and updates
942932
let case_header = " always @(*) begin\n state_next = s0;\n\
943933
case ( state_reg )";
944-
writeln!(f, "{}", case_header)?;
934+
writeln!(f, "{case_header}")?;
945935
// At each state, write the updates to the state and the outward-facing
946936
// wires to make high / low
947937
for (case, trans) in fsm.borrow().transitions.iter().enumerate() {
@@ -966,7 +956,7 @@ fn emit_fsm_module<F: io::Write>(
966956
// Wrap up the module
967957
let case_footer = " endcase\n end\n\
968958
endmodule\n";
969-
writeln!(f, "{}", case_footer)?;
959+
writeln!(f, "{case_footer}")?;
970960

971961
io::Result::Ok(())
972962
}
@@ -1033,7 +1023,7 @@ fn emit_guard_disjoint_check(
10331023

10341024
// Generated error message
10351025
let ir::Canonical { cell, port } = dst.borrow().canonical();
1036-
let msg = format!("Multiple assignment to port `{}.{}'.", cell, port);
1026+
let msg = format!("Multiple assignment to port `{cell}.{port}'.");
10371027
let err = v::Sequential::new_seqexpr(v::Expr::new_call(
10381028
"$fatal",
10391029
vec![v::Expr::new_int(2), v::Expr::Str(msg)],
@@ -1429,11 +1419,11 @@ fn memory_read_write(comp: &ir::Component) -> Vec<v::Stmt> {
14291419
vec![
14301420
v::Expr::Concat(v::ExprConcat {
14311421
exprs: vec![
1432-
v::Expr::new_str(&format!("/{}.dat", name)),
1422+
v::Expr::new_str(&format!("/{name}.dat")),
14331423
v::Expr::new_ref("DATA"),
14341424
],
14351425
}),
1436-
v::Expr::new_ipath(&format!("{}.{}", name, mem_access_str)),
1426+
v::Expr::new_ipath(&format!("{name}.{mem_access_str}")),
14371427
],
14381428
)));
14391429
});
@@ -1447,11 +1437,11 @@ fn memory_read_write(comp: &ir::Component) -> Vec<v::Stmt> {
14471437
vec![
14481438
v::Expr::Concat(v::ExprConcat {
14491439
exprs: vec![
1450-
v::Expr::new_str(&format!("/{}.out", name)),
1440+
v::Expr::new_str(&format!("/{name}.out")),
14511441
v::Expr::new_ref("DATA"),
14521442
],
14531443
}),
1454-
v::Expr::new_ipath(&format!("{}.{}", name, mem_access_str)),
1444+
v::Expr::new_ipath(&format!("{name}.{mem_access_str}")),
14551445
],
14561446
)));
14571447
});

‎calyx/backend/src/xilinx/control_axi.rs

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -80,13 +80,13 @@ impl ControlInterface for AxiInterface {
8080
) -> Self {
8181
// read channels
8282
let read_address = AxiChannel {
83-
prefix: format!("{}AR", prefix),
83+
prefix: format!("{prefix}AR"),
8484
direction: ChannelDirection::Recv,
8585
state: vec![v::Decl::new_wire("raddr", address_width)],
8686
data_ports: vec![("ADDR".to_string(), address_width)],
8787
};
8888
let read_data = AxiChannel {
89-
prefix: format!("{}R", prefix),
89+
prefix: format!("{prefix}R"),
9090
direction: ChannelDirection::Send,
9191
state: vec![v::Decl::new_reg("rdata", data_width)],
9292
data_ports: vec![
@@ -97,19 +97,19 @@ impl ControlInterface for AxiInterface {
9797

9898
// write channels
9999
let write_address = AxiChannel {
100-
prefix: format!("{}AW", prefix),
100+
prefix: format!("{prefix}AW"),
101101
direction: ChannelDirection::Recv,
102102
state: vec![v::Decl::new_reg("waddr", address_width)],
103103
data_ports: vec![("ADDR".to_string(), address_width)],
104104
};
105105
let write_data = AxiChannel {
106-
prefix: format!("{}W", prefix),
106+
prefix: format!("{prefix}W"),
107107
direction: ChannelDirection::Recv,
108108
state: vec![v::Decl::new_wire("wdata", data_width)],
109109
data_ports: vec![("DATA".to_string(), data_width)],
110110
};
111111
let write_response = AxiChannel {
112-
prefix: format!("{}B", prefix),
112+
prefix: format!("{prefix}B"),
113113
direction: ChannelDirection::Send,
114114
state: vec![],
115115
data_ports: vec![("RESP".to_string(), 2)],
@@ -146,9 +146,9 @@ impl ControlInterface for AxiInterface {
146146
vec![(0..32, "int_timeout", 0..32, Flags::default().write())],
147147
);
148148
for (idx, memory_name) in memories.iter().enumerate() {
149-
let part0_name = format!("{}_0", memory_name);
150-
let part1_name = format!("{}_1", memory_name);
151-
let addr_name = format!("addr_{}", memory_name);
149+
let part0_name = format!("{memory_name}_0");
150+
let part1_name = format!("{memory_name}_1");
151+
let addr_name = format!("addr_{memory_name}");
152152
addr_space.add_address(
153153
0x18 + (idx * 8),
154154
&part0_name,
@@ -257,9 +257,9 @@ impl ControlInterface for AxiInterface {
257257
);
258258

259259
for memory in memories {
260-
let part0_name = format!("{}_0", memory);
261-
let part1_name = format!("{}_1", memory);
262-
let addr_name = format!("addr_{}", memory);
260+
let part0_name = format!("{memory}_0");
261+
let part1_name = format!("{memory}_1");
262+
let addr_name = format!("addr_{memory}");
263263
module.add_stmt(v::Parallel::Assign(
264264
memory.as_str().into(),
265265
addr_name.into(),

‎calyx/backend/src/xilinx/memory_axi.rs

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -39,13 +39,13 @@ impl MemoryInterface for AxiInterface {
3939
];
4040
// read channels
4141
let read_address = AxiChannel {
42-
prefix: format!("{}AR", prefix),
42+
prefix: format!("{prefix}AR"),
4343
direction: ChannelDirection::Send,
4444
state: vec![],
4545
data_ports: addr_data_ports.clone(),
4646
};
4747
let read_data = AxiChannel {
48-
prefix: format!("{}R", prefix),
48+
prefix: format!("{prefix}R"),
4949
direction: ChannelDirection::Recv,
5050
state: vec![],
5151
data_ports: vec![
@@ -58,13 +58,13 @@ impl MemoryInterface for AxiInterface {
5858

5959
// write channels
6060
let write_address = AxiChannel {
61-
prefix: format!("{}AW", prefix),
61+
prefix: format!("{prefix}AW"),
6262
direction: ChannelDirection::Send,
6363
state: vec![],
6464
data_ports: addr_data_ports,
6565
};
6666
let write_data = AxiChannel {
67-
prefix: format!("{}W", prefix),
67+
prefix: format!("{prefix}W"),
6868
direction: ChannelDirection::Send,
6969
state: vec![],
7070
data_ports: vec![
@@ -75,7 +75,7 @@ impl MemoryInterface for AxiInterface {
7575
],
7676
};
7777
let write_response = AxiChannel {
78-
prefix: format!("{}B", prefix),
78+
prefix: format!("{prefix}B"),
7979
direction: ChannelDirection::Recv,
8080
state: vec![],
8181
data_ports: vec![
@@ -342,7 +342,7 @@ fn bram_logic(
342342
let suffix_idx = "Memory_controller_axi_".len();
343343
let suffix = &name[suffix_idx..];
344344
let mut ram_instance =
345-
v::Instance::new("bram", &format!("SINGLE_PORT_BRAM_{}", suffix));
345+
v::Instance::new("bram", &format!("SINGLE_PORT_BRAM_{suffix}"));
346346
ram_instance.connect_ref("ACLK", "ACLK");
347347
ram_instance.connect_ref("ADDR", "bram_addr");
348348
ram_instance.connect_ref("Din", "bram_write_data");

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