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Merge branch 'ml_calc' into gtl_wrapper_axo_v5_sim
2 parents 76322e2 + 3698d02 commit 060b29d

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-- Description:
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-- Instance for ML score calculation.
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-- Version history:
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-- HB 2024-04-19: first design.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.gtl_pkg.all;
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entity ml_calculation_instances is
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generic (
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obj: natural := AXO_SEL;
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model: natural := AXO_MODEL_V3;
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score_width: natural := AXO_SCORE_WIDTH
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);
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port(
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lhc_clk: in std_logic;
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mu: in muon_objects_array;
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eg: in calo_objects_array;
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jet: in calo_objects_array;
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tau: in calo_objects_array;
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ett: in std_logic_vector(MAX_ESUMS_BITS-1 downto 0);
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htt: in std_logic_vector(MAX_ESUMS_BITS-1 downto 0);
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etm: in std_logic_vector(MAX_ESUMS_BITS-1 downto 0);
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htm: in std_logic_vector(MAX_ESUMS_BITS-1 downto 0);
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etmhf: in std_logic_vector(MAX_ESUMS_BITS-1 downto 0);
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htmhf: in std_logic_vector(MAX_ESUMS_BITS-1 downto 0);
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ml_score_o: out std_logic_vector(score_width-1 downto 0)
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);
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end ml_calculation_instances;
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architecture rtl of ml_calculation_instances is
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signal ett_i, htt_i, etm_i, htm_i, etmhf_i, htmhf_i: std_logic_vector(31 downto 0) := X"00000000";
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signal ml_score: std_logic_vector(score_width-1 downto 0);
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signal ap_rst: std_logic := '0';
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signal ap_start: std_logic := '1';
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begin
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ett_i(MAX_ESUMS_BITS-1 downto 0) <= ett;
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htt_i(MAX_ESUMS_BITS-1 downto 0) <= htt;
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etm_i(MAX_ESUMS_BITS-1 downto 0) <= etm;
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htm_i(MAX_ESUMS_BITS-1 downto 0) <= htm;
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etmhf_i(MAX_ESUMS_BITS-1 downto 0) <= etmhf;
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htmhf_i(MAX_ESUMS_BITS-1 downto 0) <= htmhf;
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axo_i: if obj = AXO_SEL generate
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v1_i: if model = AXO_MODEL_V1 generate
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axol1tl_v1_i: entity work.axol1tl_v1
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port map(
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lhc_clk, ap_rst, ap_start,
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open, open, open,
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mu(0),mu(1),mu(2),mu(3),
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mu(4),mu(5),mu(6),mu(7),
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jet(0),jet(1),jet(2),jet(3),
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jet(4),jet(5),jet(6),jet(7),
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jet(8),jet(9),jet(10),jet(11),
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eg(0),eg(1),eg(2),eg(3),
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eg(4),eg(5),eg(6),eg(7),
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eg(8),eg(9),eg(10),eg(11),
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tau(0),tau(1),tau(2),tau(3),
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tau(4),tau(5),tau(6),tau(7),
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tau(8),tau(9),tau(10),tau(11),
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ett_i,htt_i,etm_i,htm_i,etmhf_i,htmhf_i,
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ml_score(score_width-1 downto 0),
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open
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);
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end generate v1_i;
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v3_i: if model = AXO_MODEL_V3 generate
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axol1tl_v3_i: entity work.axol1tl_v3
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port map(
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lhc_clk, ap_rst, ap_start,
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open, open, open,
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mu(0),mu(1),mu(2),mu(3),
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mu(4),mu(5),mu(6),mu(7),
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jet(0),jet(1),jet(2),jet(3),
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jet(4),jet(5),jet(6),jet(7),
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jet(8),jet(9),jet(10),jet(11),
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eg(0),eg(1),eg(2),eg(3),
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eg(4),eg(5),eg(6),eg(7),
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eg(8),eg(9),eg(10),eg(11),
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tau(0),tau(1),tau(2),tau(3),
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tau(4),tau(5),tau(6),tau(7),
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tau(8),tau(9),tau(10),tau(11),
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ett_i,htt_i,etm_i,htm_i,etmhf_i,htmhf_i,
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ml_score(score_width-1 downto 0),
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open
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);
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end generate v3_i;
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end generate axo_i;
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topo_i: if obj = TOPO_SEL generate
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base_v1_i: if model = TOPO_MODEL_BASE_V1 generate
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base_v1_inst_i: entity work.topo_base_v1
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port map(
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lhc_clk, ap_rst, ap_start,
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open, open, open,
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mu(0),mu(1),mu(2),mu(3),
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mu(4),mu(5),mu(6),mu(7),
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jet(0),jet(1),jet(2),jet(3),
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jet(4),jet(5),jet(6),jet(7),
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jet(8),jet(9),jet(10),jet(11),
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eg(0),eg(1),eg(2),eg(3),
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eg(4),eg(5),eg(6),eg(7),
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eg(8),eg(9),eg(10),eg(11),
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tau(0),tau(1),tau(2),tau(3),
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tau(4),tau(5),tau(6),tau(7),
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tau(8),tau(9),tau(10),tau(11),
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ett_i,htt_i,etm_i,htm_i,etmhf_i,htmhf_i,
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ml_score(score_width-1 downto 0),
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open
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);
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end generate base_v1_i;
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end generate topo_i;
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ml_score_o(score_width-1 downto 0) <= ml_score(score_width-1 downto 0);
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end architecture rtl;
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-- Description:
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-- Comparison for ML scores.
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-- Version history:
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-- HB 2024-04-19: first design.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.gtl_pkg.all;
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entity ml_comparison is
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generic (
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threshold: integer := 4150;
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score_width: integer := 18
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);
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port(
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ml_score: in std_logic_vector(score_width-1 downto 0);
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ml_out: out std_logic
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);
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end ml_comparison;
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architecture rtl of ml_comparison is
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begin
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ml_out <= '1' when to_integer(unsigned(ml_score)) >= threshold else '0';
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end architecture rtl;

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