Skip to content

Commit f75ae49

Browse files
herbbergherbberg
authored
Merge pull request #64 from cms-l1-globaltrigger/dev_v1.32.0
dev_v1.32.0 contains new ML calculation instance
2 parents 55c95cd + bc363e3 commit f75ae49

File tree

9 files changed

+234
-9
lines changed

9 files changed

+234
-9
lines changed

‎CHANGELOG.md

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,20 @@ All notable changes to this project will be documented in this file.
44
The format is based on [Keep a Changelog](http://keepachangelog.com/)
55
and this project adheres to [Semantic Versioning](http://semver.org/).
66

7+
## [v1.32.0] - 2025-05-13
8+
### Comment
9+
10+
- added modules for ML calculations and comparisons
11+
12+
### Changed
13+
- source files:
14+
- ../packages/gt_mp7_core_pkg.vhd
15+
- ../packages/gtl_pkg.vhd
16+
- ../payload/gtl/ml_calculation_instances
17+
- ../payload/gtl/ml_comparison
18+
- dep file:
19+
- ../cfg/uGT_algo.dep
20+
721
## [v1.31.2] - 2025-04-14
822
### Comment
923

‎README.md

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,9 +24,9 @@ Current versions:
2424

2525
| entity | version |
2626
|:-:|:-:|
27-
| uGT FW | v1.31.2 |
27+
| uGT FW | v1.32.0 |
2828
| framework | v1.4.2 |
29-
| gt logic | v1.24.2 |
29+
| gt logic | v1.25.0 |
3030
| final decision logic | v1.4.1 |
3131

3232
Following software tool versions used to create L1Menu and menu depended VHDL

‎firmware/cfg/uGT_algo.dep

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,8 @@ src payload/gtl/correlation_conditions.vhd
8080
src payload/gtl/zdc_condition.vhd
8181
src payload/gtl/cicada_condition.vhd
8282
src payload/gtl/calo_comb_multi_condition.vhd
83+
src payload/gtl/ml_calculation_instances.vhd
84+
src payload/gtl/ml_comparison.vhd
8385
#
8486
### modules of BRAMs used for mass over DeltaR
8587
## XCI files of blk_mem_gen for rom_lut_calo_inv_dr_sq and rom_lut_muon_inv_dr_sq moved to 'add_l1menu_blkmem_files.tcl'

‎firmware/hdl/packages/gt_mp7_core_pkg.vhd

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -4,12 +4,12 @@
44
-- actual versions:
55
-- use "FRAME_VERSION" as mp7_ugt release fw version (used for tag name).
66

7-
-- mp7_ugt (=FRAME_VERSION): v1.31.2
7+
-- mp7_ugt (=FRAME_VERSION): v1.32.0
88

99
-- use "GT_VERSION" as mp7_ugt release fw version (used for tag name).
10-
-- gt: v1.31.1
10+
-- gt: v1.32.0
1111
-- frame: v1.4.2 (see frame.vhd)
12-
-- gtl: v1.24.2 (see gtl_module_tpl.vhd)
12+
-- gtl: v1.25.0 (see gtl_module_tpl.vhd)
1313
-- fdl: v1.4.1 (see fdl_module.vhd)
1414

1515
-- HB 2024-09-04: v1.30.0 - Added vivado_fix_cells_tpl.tcl and constraints_fixed_cells.tcl to ../scripts.
@@ -37,6 +37,7 @@
3737
--
3838
-- gtl history:
3939

40+
-- HB 2025-05-12: v1.25.0: Added output ports for AXO score value, moved "algo_pipeline_p" to VHDL Producer template.
4041
-- HB 2025-04-14: v1.24.2: Added AXOL1TL new model v5 payload.
4142
-- HB 2025-03-21: v1.24.1: Added AXOL1TL model v5 payload.
4243
-- HB 2025-01-07: v1.24.0: Implemented AXOL1TL model v5.
@@ -107,8 +108,8 @@ package gt_mp7_core_pkg is
107108
-- ==================================================================================================
108109
-- GT firmware version
109110
constant GT_MAJOR_VERSION : integer range 0 to 255 := 1;
110-
constant GT_MINOR_VERSION : integer range 0 to 255 := 31;
111-
constant GT_REV_VERSION : integer range 0 to 255 := 2;
111+
constant GT_MINOR_VERSION : integer range 0 to 255 := 32;
112+
constant GT_REV_VERSION : integer range 0 to 255 := 0;
112113
constant GT_VERSION : std_logic_vector(31 downto 0) := X"00" &
113114
std_logic_vector(to_unsigned(GT_MAJOR_VERSION, 8)) &
114115
std_logic_vector(to_unsigned(GT_MINOR_VERSION, 8)) &
@@ -119,8 +120,8 @@ package gt_mp7_core_pkg is
119120
constant FRAME_REV_VERSION : integer range 0 to 255 := 2;
120121
-- GTL firmware (fix part) version
121122
constant GTL_FW_MAJOR_VERSION : integer range 0 to 255 := 1;
122-
constant GTL_FW_MINOR_VERSION : integer range 0 to 255 := 24;
123-
constant GTL_FW_REV_VERSION : integer range 0 to 255 := 2;
123+
constant GTL_FW_MINOR_VERSION : integer range 0 to 255 := 25;
124+
constant GTL_FW_REV_VERSION : integer range 0 to 255 := 0;
124125
-- FDL firmware version
125126
constant FDL_FW_MAJOR_VERSION : integer range 0 to 255 := 1;
126127
constant FDL_FW_MINOR_VERSION : integer range 0 to 255 := 4;

‎firmware/hdl/packages/gtl_pkg.vhd

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
-- Package for constant and type definitions of GTL firmware in Global Trigger Upgrade system.
33

44
-- Version history:
5+
-- HB 2025-05-09: added constants for ml_calculation_instances.
56
-- HB 2024-05-10: added COMMON_COND_STAGES for condition with no intermediate pipeline.
67
-- HB 2023-10-10: CICADA definition changed: no bjets.
78
-- HB 2023-10-03: inserted calo anomaly algorithm (CICADA) definitions.
@@ -81,6 +82,16 @@ package gtl_pkg is
8182
constant LINK_FRAMES : natural := 6;
8283
type lword_array is array (0 to LINK_FRAMES-1) of lword;
8384

85+
-- AXO
86+
constant AXO_SCORE_WIDTH: natural := 18;
87+
constant AXO_SEL: natural := 1;
88+
constant TOPO_SEL: natural := 2;
89+
constant AXO_MODEL_V1: natural := 1;
90+
constant AXO_MODEL_V3: natural := 3;
91+
constant AXO_MODEL_V4: natural := 4;
92+
constant AXO_MODEL_V5: natural := 5;
93+
constant TOPO_MODEL_BASE_V1: natural := 100;
94+
8495
-- Fixed pipeline structure
8596
constant BX_PIPELINE_STAGES: natural := 5; -- +/- 2bx pipeline
8697
constant COMMON_COND_STAGES: natural := 2; -- pipeline stages for condition with no intermediate pipeline

‎firmware/hdl/payload/gtl/ml_calculation_instances.vhd

Lines changed: 164 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,164 @@
1+
2+
-- Description:
3+
-- Instance for ML score calculation.
4+
5+
-- Version history:
6+
-- HB 2024-04-19: first design.
7+
8+
library ieee;
9+
use ieee.std_logic_1164.all;
10+
use ieee.numeric_std.all;
11+
12+
use work.gtl_pkg.all;
13+
14+
entity ml_calculation_instances is
15+
generic (
16+
obj: natural := AXO_SEL;
17+
model: natural := AXO_MODEL_V3;
18+
score_width: natural := AXO_SCORE_WIDTH
19+
);
20+
port(
21+
lhc_clk: in std_logic;
22+
mu: in muon_objects_array;
23+
eg: in calo_objects_array;
24+
jet: in calo_objects_array;
25+
tau: in calo_objects_array;
26+
ett: in std_logic_vector(MAX_ESUMS_BITS-1 downto 0);
27+
htt: in std_logic_vector(MAX_ESUMS_BITS-1 downto 0);
28+
etm: in std_logic_vector(MAX_ESUMS_BITS-1 downto 0);
29+
htm: in std_logic_vector(MAX_ESUMS_BITS-1 downto 0);
30+
etmhf: in std_logic_vector(MAX_ESUMS_BITS-1 downto 0);
31+
htmhf: in std_logic_vector(MAX_ESUMS_BITS-1 downto 0);
32+
ml_score_o: out std_logic_vector(score_width-1 downto 0)
33+
);
34+
end ml_calculation_instances;
35+
36+
architecture rtl of ml_calculation_instances is
37+
38+
signal ett_i, htt_i, etm_i, htm_i, etmhf_i, htmhf_i: std_logic_vector(31 downto 0) := X"00000000";
39+
signal ml_score: std_logic_vector(score_width-1 downto 0);
40+
signal ap_rst: std_logic := '0';
41+
signal ap_start: std_logic := '1';
42+
43+
begin
44+
45+
ett_i(MAX_ESUMS_BITS-1 downto 0) <= ett;
46+
htt_i(MAX_ESUMS_BITS-1 downto 0) <= htt;
47+
etm_i(MAX_ESUMS_BITS-1 downto 0) <= etm;
48+
htm_i(MAX_ESUMS_BITS-1 downto 0) <= htm;
49+
etmhf_i(MAX_ESUMS_BITS-1 downto 0) <= etmhf;
50+
htmhf_i(MAX_ESUMS_BITS-1 downto 0) <= htmhf;
51+
52+
axo_i: if obj = AXO_SEL generate
53+
v1_i: if model = AXO_MODEL_V1 generate
54+
axol1tl_v1_i: entity work.axol1tl_v1
55+
port map(
56+
lhc_clk, ap_rst, ap_start,
57+
open, open, open,
58+
mu(0),mu(1),mu(2),mu(3),
59+
mu(4),mu(5),mu(6),mu(7),
60+
jet(0),jet(1),jet(2),jet(3),
61+
jet(4),jet(5),jet(6),jet(7),
62+
jet(8),jet(9),jet(10),jet(11),
63+
eg(0),eg(1),eg(2),eg(3),
64+
eg(4),eg(5),eg(6),eg(7),
65+
eg(8),eg(9),eg(10),eg(11),
66+
tau(0),tau(1),tau(2),tau(3),
67+
tau(4),tau(5),tau(6),tau(7),
68+
tau(8),tau(9),tau(10),tau(11),
69+
ett_i,htt_i,etm_i,htm_i,etmhf_i,htmhf_i,
70+
ml_score(score_width-1 downto 0),
71+
open
72+
);
73+
end generate v1_i;
74+
v3_i: if model = AXO_MODEL_V3 generate
75+
axol1tl_v3_i: entity work.axol1tl_v3
76+
port map(
77+
lhc_clk, ap_rst, ap_start,
78+
open, open, open,
79+
mu(0),mu(1),mu(2),mu(3),
80+
mu(4),mu(5),mu(6),mu(7),
81+
jet(0),jet(1),jet(2),jet(3),
82+
jet(4),jet(5),jet(6),jet(7),
83+
jet(8),jet(9),jet(10),jet(11),
84+
eg(0),eg(1),eg(2),eg(3),
85+
eg(4),eg(5),eg(6),eg(7),
86+
eg(8),eg(9),eg(10),eg(11),
87+
tau(0),tau(1),tau(2),tau(3),
88+
tau(4),tau(5),tau(6),tau(7),
89+
tau(8),tau(9),tau(10),tau(11),
90+
ett_i,htt_i,etm_i,htm_i,etmhf_i,htmhf_i,
91+
ml_score(score_width-1 downto 0),
92+
open
93+
);
94+
end generate v3_i;
95+
v4_i: if model = AXO_MODEL_V4 generate
96+
axol1tl_v4_i: entity work.axol1tl_v4
97+
port map(
98+
lhc_clk, ap_rst, ap_start,
99+
open, open, open,
100+
mu(0),mu(1),mu(2),mu(3),
101+
mu(4),mu(5),mu(6),mu(7),
102+
jet(0),jet(1),jet(2),jet(3),
103+
jet(4),jet(5),jet(6),jet(7),
104+
jet(8),jet(9),jet(10),jet(11),
105+
eg(0),eg(1),eg(2),eg(3),
106+
eg(4),eg(5),eg(6),eg(7),
107+
eg(8),eg(9),eg(10),eg(11),
108+
tau(0),tau(1),tau(2),tau(3),
109+
tau(4),tau(5),tau(6),tau(7),
110+
tau(8),tau(9),tau(10),tau(11),
111+
ett_i,htt_i,etm_i,htm_i,etmhf_i,htmhf_i,
112+
ml_score(score_width-1 downto 0),
113+
open
114+
);
115+
end generate v4_i;
116+
v5_i: if model = AXO_MODEL_V5 generate
117+
axol1tl_v5_i: entity work.axol1tl_v5_da
118+
port map(
119+
lhc_clk, ap_rst, ap_start,
120+
open, open, open,
121+
mu(0),mu(1),mu(2),mu(3),
122+
mu(4),mu(5),mu(6),mu(7),
123+
jet(0),jet(1),jet(2),jet(3),
124+
jet(4),jet(5),jet(6),jet(7),
125+
jet(8),jet(9),jet(10),jet(11),
126+
eg(0),eg(1),eg(2),eg(3),
127+
eg(4),eg(5),eg(6),eg(7),
128+
eg(8),eg(9),eg(10),eg(11),
129+
tau(0),tau(1),tau(2),tau(3),
130+
tau(4),tau(5),tau(6),tau(7),
131+
tau(8),tau(9),tau(10),tau(11),
132+
ett_i,htt_i,etm_i,htm_i,etmhf_i,htmhf_i,
133+
ml_score(score_width-1 downto 0),
134+
open
135+
);
136+
end generate v5_i;
137+
end generate axo_i;
138+
topo_i: if obj = TOPO_SEL generate
139+
base_v1_i: if model = TOPO_MODEL_BASE_V1 generate
140+
base_v1_inst_i: entity work.topo_base_v1
141+
port map(
142+
lhc_clk, ap_rst, ap_start,
143+
open, open, open,
144+
mu(0),mu(1),mu(2),mu(3),
145+
mu(4),mu(5),mu(6),mu(7),
146+
jet(0),jet(1),jet(2),jet(3),
147+
jet(4),jet(5),jet(6),jet(7),
148+
jet(8),jet(9),jet(10),jet(11),
149+
eg(0),eg(1),eg(2),eg(3),
150+
eg(4),eg(5),eg(6),eg(7),
151+
eg(8),eg(9),eg(10),eg(11),
152+
tau(0),tau(1),tau(2),tau(3),
153+
tau(4),tau(5),tau(6),tau(7),
154+
tau(8),tau(9),tau(10),tau(11),
155+
ett_i,htt_i,etm_i,htm_i,etmhf_i,htmhf_i,
156+
ml_score(score_width-1 downto 0),
157+
open
158+
);
159+
end generate base_v1_i;
160+
end generate topo_i;
161+
162+
ml_score_o(score_width-1 downto 0) <= ml_score(score_width-1 downto 0);
163+
164+
end architecture rtl;

‎firmware/hdl/payload/gtl/ml_comparison.vhd

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
2+
-- Description:
3+
-- Comparison for ML scores.
4+
5+
-- Version history:
6+
-- HB 2024-04-19: first design.
7+
8+
library ieee;
9+
use ieee.std_logic_1164.all;
10+
use ieee.numeric_std.all;
11+
12+
use work.gtl_pkg.all;
13+
14+
entity ml_comparison is
15+
generic (
16+
threshold: integer := 4150;
17+
score_width: integer := 18
18+
);
19+
port(
20+
ml_score: in std_logic_vector(score_width-1 downto 0);
21+
ml_out: out std_logic
22+
);
23+
end ml_comparison;
24+
25+
architecture rtl of ml_comparison is
26+
begin
27+
28+
ml_out <= '1' when to_integer(unsigned(ml_score)) >= threshold else '0';
29+
30+
end architecture rtl;

‎firmware/hdl/payload/gtl_module_tpl.vhd

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
-- Global Trigger Logic module.
33

44
-- Version history:
5+
-- HB 2025-05-13: v1.25.0: Added modules for ML calculations and comparisons.
56
-- HB 2025-04-14: v1.24.2: Added AXOL1TL new model v5 payload.
67
-- HB 2025-03-21: v1.24.1: Added AXOL1TL model v5 payload.
78
-- HB 2025-01-07: v1.24.0: Implemented AXOL1TL model v5.

‎firmware/sim/scripts/templates/gtl_fdl_wrapper_tpl_questa.do

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,8 @@ vcom -93 -work work $HDL_DIR/payload/gtl/zdc_condition.vhd
118118
vcom -93 -work work $HDL_DIR/payload/gtl/cicada_condition.vhd
119119
vcom -93 -work work $HDL_DIR/payload/gtl/correlation_conditions.vhd
120120
vcom -93 -work work $HDL_DIR/payload/gtl/calo_comb_multi_condition.vhd
121+
vcom -93 -work work $HDL_DIR/payload/gtl/ml_comparison.vhd
122+
vcom -93 -work work $HDL_DIR/payload/gtl/ml_calculation_instances.vhd
121123
#
122124
#### inserted from anomaly_detection.dep (wrapper in dep file)
123125
{{adt_vhd}}

0 commit comments

Comments
 (0)