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- import os
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- import sys
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- import subprocess
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import importlib .util
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import json
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+ import os
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import shutil
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+ import subprocess
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+ import sys
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from hls4ml .backends import VivadoBackend
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from hls4ml .model .flow import get_flow , register_flow
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- from hls4ml .report import parse_vivado_report , aggregate_graph_reports
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- from hls4ml .utils .simulation_utils import write_verilog_testbench , read_testbench_log , write_testbench_input , prepare_testbench_input , prepare_zero_input
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+ from hls4ml .report import aggregate_graph_reports , parse_vivado_report
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+ from hls4ml .utils .simulation_utils import (
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+ prepare_testbench_input ,
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+ prepare_zero_input ,
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+ read_testbench_log ,
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+ write_testbench_input ,
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+ write_verilog_testbench ,
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+ )
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class VitisBackend (VivadoBackend ):
@@ -81,7 +87,18 @@ def create_initial_config(
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return config
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- def build (self , model , reset = False , csim = True , synth = True , cosim = False , validation = False , export = False , vsynth = False , log_to_stdout = True ):
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+ def build (
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+ self ,
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+ model ,
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+ reset = False ,
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+ csim = True ,
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+ synth = True ,
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+ cosim = False ,
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+ validation = False ,
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+ export = False ,
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+ vsynth = False ,
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+ log_to_stdout = True ,
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+ ):
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if 'linux' in sys .platform :
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found = os .system ('command -v vitis_hls > /dev/null' )
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if found != 0 :
@@ -95,18 +112,13 @@ def build(self, model, reset=False, csim=True, synth=True, cosim=False, validati
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output_dir = model .config .get_output_dir ()
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stdout_log = os .path .join (output_dir , 'build_stdout.log' )
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stderr_log = os .path .join (output_dir , 'build_stderr.log' )
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-
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+
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stdout_target = None if log_to_stdout else open (stdout_log , 'w' )
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stderr_target = None if log_to_stdout else open (stderr_log , 'w' )
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try :
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process = subprocess .Popen (
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- build_command ,
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- shell = True ,
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- cwd = output_dir ,
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- stdout = stdout_target ,
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- stderr = stderr_target ,
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- text = True
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+ build_command , shell = True , cwd = output_dir , stdout = stdout_target , stderr = stderr_target , text = True
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)
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process .communicate ()
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@@ -118,15 +130,16 @@ def build(self, model, reset=False, csim=True, synth=True, cosim=False, validati
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stderr_target .close ()
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return parse_vivado_report (output_dir )
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-
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+
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def build_stitched_design (
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self ,
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stitch_design = True ,
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sim_stitched_design = False ,
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export_stitched_design = False ,
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nn_config = None ,
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graph_reports = None ,
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- simulation_input_data = None ):
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+ simulation_input_data = None ,
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+ ):
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os .makedirs (nn_config ['OutputDir' ], exist_ok = True )
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stitched_design_dir = os .path .join (nn_config ['OutputDir' ], nn_config ['StitchedProjectName' ])
@@ -136,11 +149,11 @@ def build_stitched_design(
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spec = importlib .util .find_spec ('hls4ml' )
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hls4ml_path = os .path .dirname (spec .origin )
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- ip_stitcher_path = os .path .join (hls4ml_path , 'templates/vivado/ip_stitcher.tcl' )
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+ ip_stitcher_path = os .path .join (hls4ml_path , 'templates/vivado/ip_stitcher.tcl' )
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stdout_log = os .path .join (stitched_design_dir , 'stitcher_stdout.log' )
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stderr_log = os .path .join (stitched_design_dir , 'stitcher_stderr.log' )
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nn_config_path = os .path .join (stitched_design_dir , 'nn_config.json' )
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- testbench_path = os .path .join (stitched_design_dir , 'testbench.v' )
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+ testbench_path = os .path .join (stitched_design_dir , 'testbench.v' )
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testbench_log_path = os .path .join (stitched_design_dir , 'testbench_log.csv' )
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try :
@@ -151,8 +164,8 @@ def build_stitched_design(
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if nn_config :
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with open (nn_config_path , "w" ) as file :
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json .dump (nn_config , file , indent = 4 )
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-
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- if ( sim_stitched_design ) :
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+
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+ if sim_stitched_design :
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write_verilog_testbench (nn_config , testbench_path )
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# Produce a testbench input file for every input layer
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for i , layer in enumerate (nn_config ['inputs' ]):
@@ -165,30 +178,33 @@ def build_stitched_design(
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# Handles both single and multi-layer cases. First dim should always be batch size
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data = simulation_input_data [i ]
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input_data_reshaped = prepare_testbench_input (data , layer ['fifo_depth' ], layer ['batch_size' ])
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- write_testbench_input (input_data_reshaped , testbench_input_path , layer ['integer_bits' ], layer ['fractional_bits' ])
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+ write_testbench_input (
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+ input_data_reshaped , testbench_input_path , layer ['integer_bits' ], layer ['fractional_bits' ]
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+ )
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print ('Verilog testbench and its input data were generated.' )
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print ('Running build process of stitched IP...\n ' )
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stitch_command = [
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- 'vivado' , '-mode' , 'batch' , '-nojournal' , '-nolog' , '-notrace' ,
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- '-source' , ip_stitcher_path ,
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+ 'vivado' ,
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+ '-mode' ,
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+ 'batch' ,
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+ '-nojournal' ,
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+ '-nolog' ,
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+ '-notrace' ,
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+ '-source' ,
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+ ip_stitcher_path ,
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'-tclargs' ,
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f'stitch_design={ int (stitch_design )} ' ,
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f'sim_design={ int (sim_stitched_design )} ' ,
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f'export_design={ int (export_stitched_design )} ' ,
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f"stitch_project_name={ nn_config ['StitchedProjectName' ]} " ,
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f"original_project_name={ nn_config ['OriginalProjectName' ]} " ,
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- f'sim_verilog_file=testbench.v'
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+ f'sim_verilog_file=testbench.v' ,
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]
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-
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+
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with open (stdout_log , 'w' ) as stdout_file , open (stderr_log , 'w' ) as stderr_file :
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process = subprocess .Popen (
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- stitch_command ,
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- cwd = stitched_design_dir ,
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- stdout = stdout_file ,
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- stderr = stderr_file ,
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- text = True ,
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- shell = False
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+ stitch_command , cwd = stitched_design_dir , stdout = stdout_file , stderr = stderr_file , text = True , shell = False
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)
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process .communicate ()
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if process .returncode != 0 :
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