Skip to content

Commit eba8ff1

Browse files
committed
Added PLATFORM_TCL support to optionally load a Tcl script called before load_design
Signed-off-by: Jeff Ng <[email protected]>
1 parent cc477d8 commit eba8ff1

File tree

6 files changed

+28
-22
lines changed

6 files changed

+28
-22
lines changed

docs/user/FlowVariables.md

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -133,6 +133,7 @@ configuration file.
133133
| <a name="PLACE_PINS_ARGS"></a>PLACE_PINS_ARGS| Arguments to place_pins| | |
134134
| <a name="PLACE_SITE"></a>PLACE_SITE| Placement site for core cells defined in the technology LEF file.| | |
135135
| <a name="PLATFORM"></a>PLATFORM| Specifies process design kit or technology node to be used.| | |
136+
| <a name="PLATFORM_TCL"></a>PLATFORM_TCL| Specifies a Tcl script with commands to run before loading design.| | |
136137
| <a name="POST_CTS_TCL"></a>POST_CTS_TCL| Specifies a Tcl script with commands to run after CTS is completed.| | |
137138
| <a name="PROCESS"></a>PROCESS| Technology node or process in use.| | |
138139
| <a name="PWR_NETS_VOLTAGES"></a>PWR_NETS_VOLTAGES| Used for IR Drop calculation.| | |
@@ -413,6 +414,7 @@ configuration file.
413414
- [LIB_FILES](#LIB_FILES)
414415
- [MACRO_EXTENSION](#MACRO_EXTENSION)
415416
- [PLATFORM](#PLATFORM)
417+
- [PLATFORM_TCL](#PLATFORM_TCL)
416418
- [PROCESS](#PROCESS)
417419
- [RCX_RULES](#RCX_RULES)
418420
- [RECOVER_POWER](#RECOVER_POWER)

flow/platforms/asap7/config.mk

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,8 @@ ifeq ($(LIB_MODEL),)
77
endif
88
export LIB_DIR ?= $(PLATFORM_DIR)/lib/$(LIB_MODEL)
99

10+
export PLATFORM_TCL = $(PLATFORM_DIR)/liberty_suppressions.tcl
11+
1012
#Library Setup variable
1113
export TECH_LEF = $(PLATFORM_DIR)/lef/asap7_tech_1x_201209.lef
1214

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
# To remove [WARNING STA-1212] from the logs for ASAP7.
2+
# /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz line 13178, timing group from output port.
3+
# Added following suppress_message
4+
log_cmd suppress_message STA 1212

flow/scripts/load.tcl

Lines changed: 14 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3,29 +3,35 @@ source $::env(SCRIPTS_DIR)/util.tcl
33
source $::env(SCRIPTS_DIR)/report_metrics.tcl
44

55
proc load_design {design_file sdc_file} {
6+
# Source platform-related Tcl command (initially for suppressing Liberty
7+
# warnings
8+
if {[env_var_exists_and_non_empty PLATFORM_TCL]} {
9+
log_cmd source $::env(PLATFORM_TCL)
10+
}
11+
612
# Read liberty files
7-
source $::env(SCRIPTS_DIR)/read_liberty.tcl
13+
log_cmd source $::env(SCRIPTS_DIR)/read_liberty.tcl
814

915
# Read design files
1016
set ext [file extension $design_file]
1117
if {$ext == ".v"} {
12-
read_lef $::env(TECH_LEF)
13-
read_lef $::env(SC_LEF)
18+
log_cmd read_lef $::env(TECH_LEF)
19+
log_cmd read_lef $::env(SC_LEF)
1420
if {[env_var_exists_and_non_empty ADDITIONAL_LEFS]} {
1521
foreach lef $::env(ADDITIONAL_LEFS) {
16-
read_lef $lef
22+
log_cmd read_lef $lef
1723
}
1824
}
19-
read_verilog $::env(RESULTS_DIR)/$design_file
20-
link_design $::env(DESIGN_NAME)
25+
log_cmd read_verilog $::env(RESULTS_DIR)/$design_file
26+
log_cmd link_design $::env(DESIGN_NAME)
2127
} elseif {$ext == ".odb"} {
22-
read_db $::env(RESULTS_DIR)/$design_file
28+
log_cmd read_db $::env(RESULTS_DIR)/$design_file
2329
} else {
2430
error "Unrecognized input file $design_file"
2531
}
2632

2733
# Read SDC file
28-
read_sdc $::env(RESULTS_DIR)/$sdc_file
34+
log_cmd read_sdc $::env(RESULTS_DIR)/$sdc_file
2935

3036
if [file exists $::env(PLATFORM_DIR)/derate.tcl] {
3137
log_cmd source $::env(PLATFORM_DIR)/derate.tcl

flow/scripts/read_liberty.tcl

Lines changed: 3 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,29 +1,18 @@
1-
# To remove [WARNING STA-1212] from the logs for ASAP7.
2-
# /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz line 13178, timing group from output port.
3-
# Added following suppress_message
4-
if {[env_var_equals PLATFORM asap7]} {
5-
suppress_message STA 1212
6-
}
7-
81
#Read Liberty
92
if {[env_var_exists_and_non_empty CORNERS]} {
103
# corners
11-
define_corners {*}$::env(CORNERS)
4+
log_cmd define_corners {*}$::env(CORNERS)
125
foreach corner $::env(CORNERS) {
136
set LIBKEY "[string toupper $corner]_LIB_FILES"
147
foreach libFile $::env($LIBKEY) {
15-
read_liberty -corner $corner $libFile
8+
log_cmd read_liberty -corner $corner $libFile
169
}
1710
unset LIBKEY
1811
}
1912
unset corner
2013
} else {
2114
## no corner
2215
foreach libFile $::env(LIB_FILES) {
23-
read_liberty $libFile
16+
log_cmd read_liberty $libFile
2417
}
2518
}
26-
27-
if {[env_var_equals PLATFORM asap7]} {
28-
unsuppress_message STA 1212
29-
}

flow/scripts/variables.yaml

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -146,6 +146,9 @@ LIB_FILES:
146146
A Liberty file of the standard cell library with PVT characterization,
147147
input and output characteristics, timing and power definitions for each
148148
cell.
149+
PLATFORM_TCL:
150+
description: |
151+
Specifies a Tcl script with commands to run before loading design.
149152
DONT_USE_CELLS:
150153
description: |
151154
Dont use cells eases pin access in detailed routing.

0 commit comments

Comments
 (0)