diff --git a/.dockerignore b/.dockerignore index 76a64bc3c1..971b76fa27 100644 --- a/.dockerignore +++ b/.dockerignore @@ -10,6 +10,11 @@ flow/reports flow/objects flow/tech +bazel-bin/ +bazel-obj/ +bazel-OpenROAD-flow-scripts/ +bazel-testlogs/ + # Tar archives flow/*tar.gz flow/run-me*.sh diff --git a/.github/workflows/black.yaml b/.github/workflows/black.yaml index d14d043183..117bbab072 100644 --- a/.github/workflows/black.yaml +++ b/.github/workflows/black.yaml @@ -1,11 +1,9 @@ name: Lint Python on: [push, pull_request] - jobs: lint: - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} steps: - uses: actions/checkout@v3 - uses: psf/black@stable - diff --git a/.github/workflows/github-actions-cron-sync-fork-from-upstream.yml b/.github/workflows/github-actions-cron-sync-fork-from-upstream.yml index 6d5f57424c..e91e0633cc 100644 --- a/.github/workflows/github-actions-cron-sync-fork-from-upstream.yml +++ b/.github/workflows/github-actions-cron-sync-fork-from-upstream.yml @@ -14,7 +14,7 @@ on: jobs: Sync-Branch-From-Upstream: name: Automatic sync 'master' from The-OpenROAD-Project/OpenROAD-flow-scripts - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} # Only allow one action to run at a time. concurrency: sync-branch-from-upstream diff --git a/.github/workflows/github-actions-cron-test-installer.yml b/.github/workflows/github-actions-cron-test-installer.yml index b2564f5db2..2a53fde91a 100644 --- a/.github/workflows/github-actions-cron-test-installer.yml +++ b/.github/workflows/github-actions-cron-test-installer.yml @@ -27,7 +27,7 @@ jobs: fail-fast: false matrix: os: ["ubuntu20.04", "ubuntu22.04"] - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} steps: - name: Check out repository code uses: actions/checkout@v3 diff --git a/.github/workflows/github-actions-cron-update-OR.yml b/.github/workflows/github-actions-cron-update-OR.yml index 6511c5563c..695bd621f0 100644 --- a/.github/workflows/github-actions-cron-update-OR.yml +++ b/.github/workflows/github-actions-cron-update-OR.yml @@ -7,7 +7,7 @@ on: jobs: update: - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} steps: - name: Check out repository code recursively uses: actions/checkout@v3 diff --git a/.github/workflows/github-actions-cron-update-yosys.yml b/.github/workflows/github-actions-cron-update-yosys.yml index b88a39c721..f19a27ebe5 100644 --- a/.github/workflows/github-actions-cron-update-yosys.yml +++ b/.github/workflows/github-actions-cron-update-yosys.yml @@ -8,7 +8,7 @@ on: jobs: update: - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} steps: - name: Check out repository code recursively uses: actions/checkout@v3 diff --git a/.github/workflows/github-actions-cron-util-test.yml b/.github/workflows/github-actions-cron-util-test.yml index b57089329b..dcfda4c78b 100644 --- a/.github/workflows/github-actions-cron-util-test.yml +++ b/.github/workflows/github-actions-cron-util-test.yml @@ -13,11 +13,11 @@ on: # Allows you to run this workflow manually from the Actions tab workflow_dispatch: -jobs: +jobs: testUtilScripts: strategy: fail-fast: false - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} steps: - name: Check out repository code uses: actions/checkout@v3 @@ -33,4 +33,4 @@ jobs: cd flow/test for file in *.py; do python "$file" - done \ No newline at end of file + done diff --git a/.github/workflows/github-actions-lint-tcl.yml b/.github/workflows/github-actions-lint-tcl.yml new file mode 100644 index 0000000000..0399b50831 --- /dev/null +++ b/.github/workflows/github-actions-lint-tcl.yml @@ -0,0 +1,29 @@ +name: Lint Tcl code + +on: + push: + branches: + - master + pull_request: + branches: + - master + +jobs: + build: + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} + steps: + - name: Checkout repository + uses: actions/checkout@v4 + + - name: Install Dependencies + run: | + python3 -m venv venv + venv/bin/pip install tclint==0.4.2 + + - name: Lint + run: | + source venv/bin/activate + tclfmt --version + tclfmt --in-place . + git diff --exit-code + tclint --no-check-style . diff --git a/.github/workflows/github-actions-manual-update-rules.yml b/.github/workflows/github-actions-manual-update-rules.yml index fc10dae30d..cdcf2744e2 100644 --- a/.github/workflows/github-actions-manual-update-rules.yml +++ b/.github/workflows/github-actions-manual-update-rules.yml @@ -9,7 +9,7 @@ on: jobs: update: - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} strategy: fail-fast: false steps: @@ -22,15 +22,17 @@ jobs: python-version: "3.10" - name: Install Python Packages run: | - pip install firebase-admin + python3 -m venv venv + venv/bin/pip install firebase-admin - name: Execute Python Script Update env: CREDS_FILE: ${{ secrets.CREDS_FILE }} API_BASE_URL: ${{ secrets.API_BASE_URL }} run: | + source venv/bin/activate if [[ "${{ github.event.inputs.type }}" == "overwrite" ]]; then python flow/util/updateRules.py --keyFile "${CREDS_FILE}" --apiURL ${API_BASE_URL} --commitSHA $(git rev-parse HEAD) --overwrite - else + else python flow/util/updateRules.py --keyFile "${CREDS_FILE}" --apiURL ${API_BASE_URL} --commitSHA $(git rev-parse HEAD) fi - name: Push updated rules diff --git a/.github/workflows/github-actions-on-delete-cleanup.yml b/.github/workflows/github-actions-on-delete-cleanup.yml index 7596854aad..5dc97769ad 100644 --- a/.github/workflows/github-actions-on-delete-cleanup.yml +++ b/.github/workflows/github-actions-on-delete-cleanup.yml @@ -12,7 +12,7 @@ jobs: Delete-From-Staging: name: Delete branch from staging - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} permissions: # Read-only access so we don't accidentally try to push to *this* repository. diff --git a/.github/workflows/github-actions-on-label-create.yml b/.github/workflows/github-actions-on-label-create.yml index 0befd29908..4e083dac8a 100644 --- a/.github/workflows/github-actions-on-label-create.yml +++ b/.github/workflows/github-actions-on-label-create.yml @@ -12,7 +12,7 @@ env: jobs: Push-To-Staging: name: Push to staging - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} permissions: # Read-only access so we don't accidentally try to push to *this* repository. diff --git a/.github/workflows/github-actions-on-push.yml b/.github/workflows/github-actions-on-push.yml index d95abd04bc..579beea403 100644 --- a/.github/workflows/github-actions-on-push.yml +++ b/.github/workflows/github-actions-on-push.yml @@ -8,12 +8,9 @@ on: jobs: scan: - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} steps: - name: Check out repository code uses: actions/checkout@v2 - name: run security_scan_on_push uses: The-OpenROAD-Project/actions/security_scan_on_push@main - - - diff --git a/.github/workflows/github-actions-publish-docker-images.yml b/.github/workflows/github-actions-publish-docker-images.yml index bf32946e50..476ec3220d 100644 --- a/.github/workflows/github-actions-publish-docker-images.yml +++ b/.github/workflows/github-actions-publish-docker-images.yml @@ -27,7 +27,7 @@ on: jobs: buildCodespaceImage: - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} timeout-minutes: 600 steps: - uses: actions/checkout@v4 @@ -61,7 +61,7 @@ jobs: fail-fast: false matrix: os: [["ubuntu20.04", "ubuntu:20.04"], ["ubuntu22.04", "ubuntu:22.04"]] - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} steps: - name: Check out repository code uses: actions/checkout@v4 diff --git a/.github/workflows/github-actions-update-rules.yml b/.github/workflows/github-actions-update-rules.yml index c728f90df9..3355612ba5 100644 --- a/.github/workflows/github-actions-update-rules.yml +++ b/.github/workflows/github-actions-update-rules.yml @@ -6,7 +6,7 @@ on: jobs: update: - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} strategy: fail-fast: false steps: @@ -24,12 +24,14 @@ jobs: python-version: "3.10" - name: Install Python Packages run: | - pip install firebase-admin + python3 -m venv venv + venv/bin/pip install firebase-admin - name: Execute Python Script Update env: CREDS_FILE: ${{ secrets.CREDS_FILE }} API_BASE_URL: ${{ secrets.API_BASE_URL }} run: | + source ./venv/bin/activate echo ${{ github.event_name }} echo ${{ github.event.client_payload.type }} if [[ "${{ github.event_name }}" == "repository_dispatch" && "${{ github.event.client_payload.type }}" == "overwrite" ]]; then diff --git a/.github/workflows/github-actions-yaml-test.yml b/.github/workflows/github-actions-yaml-test.yml index e9ced92258..704f34ab78 100644 --- a/.github/workflows/github-actions-yaml-test.yml +++ b/.github/workflows/github-actions-yaml-test.yml @@ -7,7 +7,7 @@ jobs: docs-test-job: name: 'Tests for variables.yaml' if: github.event_name == 'pull_request' || github.event_name == 'push' - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} steps: - name: Checkout repository uses: actions/checkout@v4 @@ -23,9 +23,13 @@ jobs: - name: Check if FlowVariables.md is up to date run: | git diff --exit-code docs/user/FlowVariables.md + - name: Install dependencies + run: | + python3 -m venv venv + venv/bin/pip install --quiet yamlfix==1.17.0 - name: Run yamlfix check run: | - pip install --quiet yamlfix==1.17.0 + source venv/bin/activate yamlfix --version set -x yamlfix -c yamlfix.toml flow/scripts/variables.yaml diff --git a/.gitignore b/.gitignore index 5d1922e9b0..37ebf3fa79 100644 --- a/.gitignore +++ b/.gitignore @@ -29,7 +29,6 @@ flow/rc_model.bin flow/*.tif.gz flow/*.def.v - # RePlAce deps *PORT9.dat *POST9.dat @@ -99,4 +98,10 @@ build metadata-base-at.json user.bazelrc -bazel-* +bazel-bin +bazel-out +bazel-OpenROAD-flow-scripts +bazel-testlogs + +# python venv +venv/ diff --git a/.gitmodules b/.gitmodules index bcda953424..ec90369ba8 100644 --- a/.gitmodules +++ b/.gitmodules @@ -4,3 +4,6 @@ [submodule "tools/OpenROAD"] path = tools/OpenROAD url = ../OpenROAD.git +[submodule "tools/yosys-slang"] + path = tools/yosys-slang + url = https://github.com/povik/yosys-slang.git diff --git a/MODULE.bazel b/MODULE.bazel index 7c9706cc88..574d678f5d 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -11,75 +11,36 @@ bazel_dep(name = "bazel-orfs") # To bump version, run: bazelisk run @bazel-orfs//:bump git_override( module_name = "bazel-orfs", - commit = "4a67015d0165e14466b89cc7ce1e92688f393093", + commit = "f8a4b694b37c8f5322323eba9a9ae37f9541ee17", remote = "https://github.com/The-OpenROAD-Project/bazel-orfs.git", ) -bazel_dep(name = "rules_python", version = "0.31.0") +bazel_dep(name = "rules_python", version = "1.2.0") python = use_extension("@rules_python//python/extensions:python.bzl", "python") python.toolchain( ignore_root_user_error = True, - python_version = "3.12", + python_version = "3.13", ) pip = use_extension("@rules_python//python/extensions:pip.bzl", "pip") pip.parse( hub_name = "orfs-pip", - python_version = "3.12", + python_version = "3.13", requirements_lock = "//flow:util/requirements_lock.txt", ) use_repo(pip, "orfs-pip") -# HACK! While we're waiting for OpenROAD to switch to bzlmod -new_local_repository = use_repo_rule("@bazel_tools//tools/build_defs/repo:local.bzl", "new_local_repository") - -new_local_repository( - name = "openroad", - build_file_content = """ -exports_files(["openroad"], -visibility = ["//visibility:public"], -) -filegroup( - name = "all", - data = glob(["openroad.runfiles/**/*"]), - visibility = ["//visibility:public"], -) -""", - path = "tools/OpenROAD/bazel-out/k8-opt/bin", -) - orfs = use_extension("@bazel-orfs//:extension.bzl", "orfs_repositories") # To bump version, run: bazelisk run @bazel-orfs//:bump orfs.default( - # Check out the version you want to test and make any modifications locally: - # - # ./build_openroad.sh --no_init - # - # Comment out "sha256" below, not available for local docker images - # and update "image" to point to the local image. - - # Official image https://hub.docker.com/r/openroad/orfs/tags - image = "docker.io/openroad/orfs:v3.0-2888-g38f93c61", + image = "docker.io/openroad/orfs:v3.0-3273-gedf3d6bf", # Use local files instead of docker image makefile = "//flow:makefile", makefile_yosys = "//flow:makefile_yosys", - # TODO once openroad is switched to MODULE.bazel, use - # local_path_override(module_name = "openroad", path = "../tools/OpenROAD") - # to point to the local openroad Bazel module instead of - # getting the openroad binary from the docker image, supports GUI. - # - # openroad = "@docker_orfs//:openroad", - - # Use locally built OpenROAD while we're waiting for OpenROAD - # to bzlmod, no GUI for now. - # - # cd ../tools/OpenROAD - # bazelisk build -c opt :openroad - openroad = "//flow/test:openroad", pdk = "//flow:asap7", - sha256 = "173581fc6ca74ece349150866ddce96534c5e9d855a25ca8ae509a45fcaefc0d", + sha256 = "f5692c6325ebcf27cc348e033355ec95c82c35ace1af7e72a0d352624ada143e", ) use_repo(orfs, "com_github_nixos_patchelf_download") use_repo(orfs, "docker_orfs") diff --git a/MODULE.bazel.lock b/MODULE.bazel.lock index 2e7263fada..45ece7112e 100644 --- a/MODULE.bazel.lock +++ b/MODULE.bazel.lock @@ -638,7 +638,7 @@ "@@bazel-orfs~//:extension.bzl%orfs_repositories": { "general": { "bzlTransitiveDigest": "opZMguyG+UPmDQ6vhzXe/u0WnKyao2m9IAQt+JWkhcA=", - "usagesDigest": "DOOJ9+vsihVM2cEr/ckxKDoJuGmICP6rKX1uYMN3cd4=", + "usagesDigest": "ZjAOFUXNXojx6a5mgorvg9pXsDXOsJv7KzaZaxOrWXU=", "recordedFileInputs": {}, "recordedDirentsInputs": {}, "envVariables": {}, @@ -658,8 +658,8 @@ "bzlFile": "@@bazel-orfs~//:docker.bzl", "ruleClassName": "docker_pkg", "attributes": { - "image": "docker.io/openroad/orfs:v3.0-2888-g38f93c61", - "sha256": "173581fc6ca74ece349150866ddce96534c5e9d855a25ca8ae509a45fcaefc0d", + "image": "docker.io/openroad/orfs:v3.0-3273-gedf3d6bf", + "sha256": "f5692c6325ebcf27cc348e033355ec95c82c35ace1af7e72a0d352624ada143e", "build_file": "@@bazel-orfs~//:docker.BUILD.bazel", "timeout": 3600, "patch_cmds": [ @@ -674,7 +674,7 @@ "makefile": "@@//flow:makefile", "pdk": "@@//flow:asap7", "makefile_yosys": "@@//flow:makefile_yosys", - "openroad": "@@//flow/test:openroad", + "openroad": "@@bazel-orfs~~orfs_repositories~docker_orfs//:openroad", "yosys": "@@bazel-orfs~~orfs_repositories~docker_orfs//:yosys", "yosys_abc": "@@bazel-orfs~~orfs_repositories~docker_orfs//:yosys-abc" } @@ -941,12 +941,12 @@ }, "@@rules_python~//python/extensions:pip.bzl%pip": { "general": { - "bzlTransitiveDigest": "UVXSWhRHdKjw09doJ4m4mjTHC+BIiApwOePiq04rmBA=", - "usagesDigest": "pH3zwwfC5Cl9+K3uTBlFrrKV8Gno7nf5+n1aL4X3uGU=", + "bzlTransitiveDigest": "wDKx+PsqgAb8Kll8JbxI6+g8BUNJT48gxqvlHp+uPaM=", + "usagesDigest": "Pmo+R+aERo0wl9TIu+O0dXTNmE8JG2ElzftJqGKKsXk=", "recordedFileInputs": { "@@rules_python~//tools/publish/requirements_linux.txt": "d576e0d8542df61396a9b38deeaa183c24135ed5e8e73bb9622f298f2671811e", - "@@bazel-orfs~//requirements_lock_3_13.txt": "fcabafb7192fe8f92d82e7ec8ddd8e3fd6787f8acea3ec694f105ed63821416a", - "@@//flow/util/requirements_lock.txt": "016f788600d492820c9a6ff951c31a26735bcdb24a5a1bc83f68a726c6e4c884", + "@@bazel-orfs~//requirements_lock_3_13.txt": "6d409e2c9f81ceee67c23e6f26b6742b4ee6c32826c7d0591c5c57df72a6a16b", + "@@//flow/util/requirements_lock.txt": "21d4a2f4b126820247f3f9b3554210fc78861c0a367c2b52d87771900b40520c", "@@rules_fuzzing~//fuzzing/requirements.txt": "ab04664be026b632a0d2a2446c4f65982b7654f5b6851d2f9d399a19b7242a5b", "@@rules_python~//tools/publish/requirements_windows.txt": "d18538a3982beab378fd5687f4db33162ee1ece69801f9a451661b1b64286b76", "@@protobuf~//python/requirements.txt": "983be60d3cec4b319dcab6d48aeb3f5b2f7c3350f26b3a9e97486c37967c73c5", @@ -1028,6 +1028,16 @@ "requirement": "packaging==24.2 --hash=sha256:09abb1bccd265c01f4a3aa3f7a7db064b36514d2cba19a2f694fe6150451a759 --hash=sha256:c228a6dc5e932d346bc5739379109d49e8853dd8223571c7c5b55260edc0b97f" } }, + "bazel-orfs-pip_313_pandas": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@bazel-orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "bazel-orfs-pip_313", + "requirement": "pandas==2.3.0 --hash=sha256:034abd6f3db8b9880aaee98f4f5d4dbec7c4829938463ec046517220b2f8574e --hash=sha256:094e271a15b579650ebf4c5155c05dcd2a14fd4fdd72cf4854b2f7ad31ea30be --hash=sha256:14a0cc77b0f089d2d2ffe3007db58f170dae9b9f54e569b299db871a3ab5bf46 --hash=sha256:1a881bc1309f3fce34696d07b00f13335c41f5f5a8770a33b09ebe23261cfc67 --hash=sha256:1d2b33e68d0ce64e26a4acc2e72d747292084f4e8db4c847c6f5f6cbe56ed6d8 --hash=sha256:213cd63c43263dbb522c1f8a7c9d072e25900f6975596f883f4bebd77295d4f3 --hash=sha256:23c2b2dc5213810208ca0b80b8666670eb4660bbfd9d45f58592cc4ddcfd62e1 --hash=sha256:2c7e2fc25f89a49a11599ec1e76821322439d90820108309bf42130d2f36c983 --hash=sha256:2eb4728a18dcd2908c7fccf74a982e241b467d178724545a48d0caf534b38ebf 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--hash=sha256:4721f391ed90541fddacab5acf947aa0d3dc7d27b2e1e8eda2be8970586c3274 --hash=sha256:ff70335d468e7eb6ec65b95b99d3a2836546063f63acc5171de367e834932a81" } }, @@ -3813,11 +3843,14 @@ "matplotlib": "{\"bazel-orfs-pip_313_matplotlib\":[{\"version\":\"3.13\"}]}", "numpy": "{\"bazel-orfs-pip_313_numpy\":[{\"version\":\"3.13\"}]}", "packaging": "{\"bazel-orfs-pip_313_packaging\":[{\"version\":\"3.13\"}]}", + "pandas": "{\"bazel-orfs-pip_313_pandas\":[{\"version\":\"3.13\"}]}", "pillow": "{\"bazel-orfs-pip_313_pillow\":[{\"version\":\"3.13\"}]}", "pyparsing": "{\"bazel-orfs-pip_313_pyparsing\":[{\"version\":\"3.13\"}]}", "python_dateutil": "{\"bazel-orfs-pip_313_python_dateutil\":[{\"version\":\"3.13\"}]}", + "pytz": "{\"bazel-orfs-pip_313_pytz\":[{\"version\":\"3.13\"}]}", "pyyaml": "{\"bazel-orfs-pip_313_pyyaml\":[{\"version\":\"3.13\"}]}", - "six": "{\"bazel-orfs-pip_313_six\":[{\"version\":\"3.13\"}]}" + "six": "{\"bazel-orfs-pip_313_six\":[{\"version\":\"3.13\"}]}", + "tzdata": "{\"bazel-orfs-pip_313_tzdata\":[{\"version\":\"3.13\"}]}" }, "packages": [ "contourpy", @@ -3827,11 +3860,14 @@ "matplotlib", "numpy", "packaging", + "pandas", "pillow", "pyparsing", "python_dateutil", + "pytz", "pyyaml", - "six" + "six", + "tzdata" ], "groups": {} } @@ -3843,18 +3879,18 @@ "repo_name": "orfs-pip", "extra_hub_aliases": {}, "whl_map": { - "contourpy": "{\"orfs-pip_312_contourpy\":[{\"version\":\"3.12\"}]}", - "cycler": "{\"orfs-pip_312_cycler\":[{\"version\":\"3.12\"}]}", - "fonttools": "{\"orfs-pip_312_fonttools\":[{\"version\":\"3.12\"}]}", - "kiwisolver": "{\"orfs-pip_312_kiwisolver\":[{\"version\":\"3.12\"}]}", - "matplotlib": "{\"orfs-pip_312_matplotlib\":[{\"version\":\"3.12\"}]}", - "numpy": "{\"orfs-pip_312_numpy\":[{\"version\":\"3.12\"}]}", - "packaging": "{\"orfs-pip_312_packaging\":[{\"version\":\"3.12\"}]}", - "pillow": "{\"orfs-pip_312_pillow\":[{\"version\":\"3.12\"}]}", - "pyparsing": "{\"orfs-pip_312_pyparsing\":[{\"version\":\"3.12\"}]}", - "python_dateutil": "{\"orfs-pip_312_python_dateutil\":[{\"version\":\"3.12\"}]}", - "pyyaml": "{\"orfs-pip_312_pyyaml\":[{\"version\":\"3.12\"}]}", - "six": "{\"orfs-pip_312_six\":[{\"version\":\"3.12\"}]}" + "contourpy": "{\"orfs-pip_313_contourpy\":[{\"version\":\"3.13\"}]}", + "cycler": "{\"orfs-pip_313_cycler\":[{\"version\":\"3.13\"}]}", + "fonttools": "{\"orfs-pip_313_fonttools\":[{\"version\":\"3.13\"}]}", + "kiwisolver": "{\"orfs-pip_313_kiwisolver\":[{\"version\":\"3.13\"}]}", + "matplotlib": "{\"orfs-pip_313_matplotlib\":[{\"version\":\"3.13\"}]}", + "numpy": "{\"orfs-pip_313_numpy\":[{\"version\":\"3.13\"}]}", + "packaging": "{\"orfs-pip_313_packaging\":[{\"version\":\"3.13\"}]}", + "pillow": "{\"orfs-pip_313_pillow\":[{\"version\":\"3.13\"}]}", + "pyparsing": "{\"orfs-pip_313_pyparsing\":[{\"version\":\"3.13\"}]}", + "python_dateutil": "{\"orfs-pip_313_python_dateutil\":[{\"version\":\"3.13\"}]}", + "pyyaml": "{\"orfs-pip_313_pyyaml\":[{\"version\":\"3.13\"}]}", + "six": "{\"orfs-pip_313_six\":[{\"version\":\"3.13\"}]}" }, "packages": [ "contourpy", diff --git a/README.md b/README.md index 56d3a2a1f7..515be0b597 100644 --- a/README.md +++ b/README.md @@ -46,6 +46,14 @@ timeline ## Tool Installation +There are different ways to install and develop OpenROAD and ORFS, which is the best fit depends use-case, experience and personal taste. + +### Use Bazel, avoid installing anything at all and adapt the flow to your needs in your own repository + +[bazel-orfs](https://github.com/The-OpenROAD-Project/bazel-orfs) provides a seamless, reproducible way to manage dependencies and adapt the flow without requiring manual installations(no Docker images, sudo bash scripts, etc.) + +By leveraging [Bazel](https://bazel.build/)'s robust build system, all dependencies are automatically resolved, versioned, and built in a consistent environment. This eliminates setup complexity, ensures fast incremental builds, and allows for easy customization of the flow, making it an efficient choice for both [beginners](https://github.com/Pinata-Consulting/RegFileStudy) and [advanced](https://github.com/The-OpenROAD-Project/megaboom) users. + ### Docker Based Installation To ease dependency installation issues, ORFS uses docker images. diff --git a/build_openroad.sh b/build_openroad.sh index 604985e306..c4967f9b68 100755 --- a/build_openroad.sh +++ b/build_openroad.sh @@ -21,7 +21,7 @@ OPENROAD_APP_BRANCH="master" INSTALL_PATH="$(pwd)/tools/install" YOSYS_USER_ARGS="" -YOSYS_ARGS="CONFIG=clang" +YOSYS_ARGS="" OPENROAD_APP_USER_ARGS="" OPENROAD_APP_ARGS="" @@ -237,6 +237,10 @@ __local_build() set -u fi + echo "[INFO FLW-0018] Compiling OpenROAD." + eval ${NICE} ./tools/OpenROAD/etc/Build.sh -dir="$DIR/tools/OpenROAD/build" -threads=${PROC} -cmake=\'${OPENROAD_APP_ARGS}\' + ${NICE} cmake --build tools/OpenROAD/build --target install -j "${PROC}" + YOSYS_ABC_PATH=tools/yosys/abc if [[ -d "${YOSYS_ABC_PATH}/.git" ]]; then # update indexes to make sure git diff-index uses correct data @@ -246,9 +250,10 @@ __local_build() echo "[INFO FLW-0017] Compiling Yosys." ${NICE} make install -C tools/yosys -j "${PROC}" ${YOSYS_ARGS} - echo "[INFO FLW-0018] Compiling OpenROAD." - eval ${NICE} ./tools/OpenROAD/etc/Build.sh -dir="$DIR/tools/OpenROAD/build" -threads=${PROC} -cmake=\'${OPENROAD_APP_ARGS}\' - ${NICE} cmake --build tools/OpenROAD/build --target install -j "${PROC}" + echo "[INFO FLW-0030] Compiling yosys-slang." + # CMAKE_FLAGS added to work around yosys-slang#141 (unable to build outside of git checkout) + ${NICE} make install -C tools/yosys-slang -j "${PROC}" YOSYS_PREFIX="${INSTALL_PATH}/yosys/bin/" CMAKE_FLAGS="-DYOSYS_SLANG_REVISION=unknown -DSLANG_REVISION=unknown" + } __update_openroad_app_remote() @@ -340,7 +345,7 @@ __common_setup # Choose install method if [ -z "${LOCAL_BUILD+x}" ] && command -v docker &> /dev/null; then - echo -n "[INFO FLW-0000] Using docker build method." + echo "[INFO FLW-0000] Using docker build method." __docker_build else echo -n "[INFO FLW-0001] Using local build method." diff --git a/dev_env.sh b/dev_env.sh index 61a77e6929..917747caf5 100755 --- a/dev_env.sh +++ b/dev_env.sh @@ -3,7 +3,7 @@ # Set developer paths and environment variables here, # user settings go in ./env.sh function __setpaths() { - local DIR=$(readlink -f "$(dirname "${BASH_SOURCE[0]}")") + local DIR=$(readlink -f "$(dirname "${BASH_SOURCE[0]:-${(%):-%x}}")") [ "$(find $DIR/dependencies -type f -user root)" ] && echo "WARNING! Files set up by sudo found in $DIR" export PATH="$DIR/dependencies/bin:$PATH" export CMAKE_INSTALL_RPATH=$DIR/dependencies/lib:$DIR/dependencies/lib64 diff --git a/docker/Dockerfile.builder b/docker/Dockerfile.builder index b7bcb250bd..69d616f6da 100644 --- a/docker/Dockerfile.builder +++ b/docker/Dockerfile.builder @@ -15,12 +15,23 @@ COPY --link build_openroad.sh build_openroad.sh FROM orfs-base AS orfs-builder-base +# Inject compiler wrapper scripts that append the macros +RUN mkdir -p /usr/local/bin/wrapped-cc && \ + echo '#!/bin/sh' > /usr/local/bin/wrapped-cc/gcc && \ + echo 'exec /usr/bin/gcc -D__TIME__="\"0\"" -D__DATE__="\"0\"" -D__TIMESTAMP__="\"0\"" -Wno-builtin-macro-redefined "$@"' >> /usr/local/bin/wrapped-cc/gcc && \ + chmod +x /usr/local/bin/wrapped-cc/gcc && \ + ln -sf /usr/local/bin/wrapped-cc/gcc /usr/local/bin/wrapped-cc/cc && \ + echo '#!/bin/sh' > /usr/local/bin/wrapped-cc/g++ && \ + echo 'exec /usr/bin/g++ -D__TIME__="\"0\"" -D__DATE__="\"0\"" -D__TIMESTAMP__="\"0\"" -Wno-builtin-macro-redefined "$@"' >> /usr/local/bin/wrapped-cc/g++ && \ + chmod +x /usr/local/bin/wrapped-cc/g++ + +# Prepend wrapper directory to PATH so they override system compilers +ENV PATH="/usr/local/bin/wrapped-cc:$PATH" + COPY --link tools tools ARG numThreads=$(nproc) RUN echo "" > tools/yosys/abc/.gitcommit && \ - env CFLAGS="-D__TIME__=0 -D__DATE__=0 -D__TIMESTAMP__=0 -Wno-builtin-macro-redefined" \ - CXXFLAGS="-D__TIME__=0 -D__DATE__=0 -D__TIMESTAMP__=0 -Wno-builtin-macro-redefined" \ ./build_openroad.sh --no_init --local --threads ${numThreads} FROM orfs-base diff --git a/docker/Dockerfile.dev b/docker/Dockerfile.dev index 53828058f2..a2a822b486 100644 --- a/docker/Dockerfile.dev +++ b/docker/Dockerfile.dev @@ -15,8 +15,18 @@ COPY InstallerOpenROAD.sh \ ARG options="" ARG constantBuildDir="-constant-build-dir" -ENV CFLAGS="-D__TIME__=0 -D__DATE__=0 -D__TIMESTAMP__=0 -Wno-builtin-macro-redefined" -ENV CXXFLAGS="-D__TIME__=0 -D__DATE__=0 -D__TIMESTAMP__=0 -Wno-builtin-macro-redefined" +# add compiler wrapper scripts +# inject the macro definitions during compilation only +RUN mkdir -p /usr/local/bin/wrapped-cc && \ + echo '#!/bin/sh' > /usr/local/bin/wrapped-cc/gcc && \ + echo 'exec /usr/bin/gcc -D__TIME__="\"0\"" -D__DATE__="\"0\"" -D__TIMESTAMP__="\"0\"" -Wno-builtin-macro-redefined "$@"' >> /usr/local/bin/wrapped-cc/gcc && \ + chmod +x /usr/local/bin/wrapped-cc/gcc && \ + ln -sf /usr/local/bin/wrapped-cc/gcc /usr/local/bin/wrapped-cc/cc && \ + echo '#!/bin/sh' > /usr/local/bin/wrapped-cc/g++ && \ + echo 'exec /usr/bin/g++ -D__TIME__="\"0\"" -D__DATE__="\"0\"" -D__TIMESTAMP__="\"0\"" -Wno-builtin-macro-redefined "$@"' >> /usr/local/bin/wrapped-cc/g++ && \ + chmod +x /usr/local/bin/wrapped-cc/g++ + +ENV PATH="/usr/local/bin/wrapped-cc:$PATH" RUN ./DependencyInstaller.sh -base $options $constantBuildDir \ && ./DependencyInstaller.sh -common $options $constantBuildDir \ diff --git a/docs/tutorials/FlowTutorial.md b/docs/tutorials/FlowTutorial.md index 57ea6f223f..4f0c6ff9fc 100644 --- a/docs/tutorials/FlowTutorial.md +++ b/docs/tutorials/FlowTutorial.md @@ -187,15 +187,15 @@ minimum required timing constraint. create_clock -name core_clock -period 17.4 [get_ports {clk_i}] ``` -### Design Input Verilog +### Design Input SystemVerilog -The Verilog input files are located in `./designs/src/ibex/` +The SystemVerilog input files are located in `./designs/src/ibex_sv/` -The design is defined in `ibex_core.v` available -[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex/ibex_core.v). +The design is defined in `ibex_core.sv` available +[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex_sv/ibex_core.sv). Refer to the `ibex` design `README.md` -[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex/README.md). +[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex_sv/README.md). ## Running The Automated RTL-to-GDS Flow diff --git a/docs/user/BuildLocally.md b/docs/user/BuildLocally.md index 573be158a8..857235d288 100644 --- a/docs/user/BuildLocally.md +++ b/docs/user/BuildLocally.md @@ -32,6 +32,7 @@ up the environment. The `make` command runs from RTL-GDSII generation for defaul ``` shell source ./env.sh yosys -help +yosys -m slang -p "slang_version" openroad -help cd flow make diff --git a/docs/user/BuildWithDocker.md b/docs/user/BuildWithDocker.md index 4825ebd5fd..82d532c567 100644 --- a/docs/user/BuildWithDocker.md +++ b/docs/user/BuildWithDocker.md @@ -79,6 +79,7 @@ Then, inside docker: ``` shell source ./env.sh yosys -help +yosys -m slang -p "slang_version" openroad -help cd flow make diff --git a/docs/user/BuildWithPrebuilt.md b/docs/user/BuildWithPrebuilt.md index 1bc4abb05b..8dd74384fc 100644 --- a/docs/user/BuildWithPrebuilt.md +++ b/docs/user/BuildWithPrebuilt.md @@ -63,6 +63,7 @@ export YOSYS_EXE=$(command -v yosys) export LD_LIBRARY_PATH="/bin:$PATH" yosys -help +yosys -m slang -p "slang_version" openroad -help cd flow make diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index e547af1f78..854bceb8d2 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -1,10 +1,48 @@ -# Environment Variables for the OpenROAD Flow Scripts +# Variables for the OpenROAD Flow Scripts - -Environment variables are used in the OpenROAD flow to define various +Variables are used in the OpenROAD flow to define various platform, design and tool specific variables to allow finer control and -user overrides at various flow stages. These are defined in the -`config.mk` file located in the platform and design specific directories. +user overrides at various flow stages. + +These are normally defined in the `config.mk` file located in the platform and design-specific directories, but can also be defined on the command line or via environment variables. For example: + +- Command line: `make PLACE_DENSITY=0.5` +- Environment variable: `export PLACE_DENSITY=0.5` + +This works provided that `config.mk` has defined it as a default value using the `export PLACE_DENSITY?=0.4` syntax. + +The actual value used is determined by the priority rules set by `make`: + +1. **Makefile Definitions**: Variables defined in the `Makefile` or included files are used when they are defined using the no-override `=` operator, `export PLACE_DENSITY=0.4` syntax. The priority within the included files is the `DESIGN_CONFIG` file, then `Makefile` definitions and finally platform(PDK) defined variables. +2. **Command Line**: Variables defined on the command line take the highest priority in overriding defaults. +3. **Environment Variables**: Variables exported in the shell environment are used if not overridden by the command line. +4. **Default Values**: Variables defined with the `?=` operator in the `Makefile` are used only if the variable is not already defined elsewhere. + +## Effects of variables + +The variables for ORFS are not fully independent and can interact in complex ways. Small changes to a combination of variables can have large consequences, such as on macro placement, which can lead to vastly different quality of results. + +Due to the large number of variables, some of which are continuous and require long runtimes, other discrete, it is not feasible to perform an exhaustive end-to-end search for the best combination of variables. + +Instead, the following approaches are used to determine reasonable values, up to a point of diminishing returns: + +- **Experience**: Leveraging domain expertise to set initial values. +- **AI**: Using machine learning techniques to explore variable combinations. +- **Parameter Sweeps**: Testing a smaller subset of variables to identify optimal ranges. + +These values are then set in configuration files and kept under source control alongside the RTL input. + +## Types of variables + +Variables values are set in ORFS scripts or `config.mk` files and are kept in source control together with configuration files and RTL. + +It is an ongoing effort to move variables upwards in the categories below. + +| Category | Definition | User Involvement | Examples | Automation Potential | Notes | +|--------------------|----------------------------------------------------------------------------|----------------------------------------|-----------------------------------------|-----------------------------|-----------------------------------------------------------------------| +| **Trivial** | Automatically determined by tool with near-optimal results. | None (unless debugging) | Buffer sizing, default layers | **High** – can be hidden | Best if invisible; surfaced only in debug or verbose mode. | +| **Easy** | Requires input, but easy to tune using reports or visuals. | Moderate – copy/edit from reports | `PLACE_DENSITY` | **Medium–High** | Smooth response curves, intuitive tuning. | +| **Complex** | Small changes in values may result in large effects. | High – requires multiple runs/sweeps | `CTS_DISTANCE_BUF`, small changes can have large effects on skew and quality of results. Small changes to independent inputs, such as RTL, can invalidate earlier "good values". | **Low–Medium** | Needs scripted sweeps and statistical evaluation. | ## Platform @@ -20,7 +58,7 @@ variable. For OpenROAD Flow Scripts we have the following public platforms: - `nangate45` - `asap7` -## Platform Specific Environment Variables +## Platform Specific Variables The table below lists the complete set of variables used in each of the @@ -50,155 +88,164 @@ configuration file. ## Variables in alphabetic order -| Variable | Description | Default | Deprecated | -| --- | --- | --- | --- | -| ABC_AREA| Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED.| 0| | -| ABC_CLOCK_PERIOD_IN_PS| Clock period to be used by STA during synthesis. Default value read from `constraint.sdc`.| | | -| ABC_DRIVER_CELL| Default driver cell used during ABC synthesis.| | | -| ABC_LOAD_IN_FF| During synthesis set_load value used.| | | -| ABSTRACT_SOURCE| Which .odb file to use to create abstract| | | -| ADDER_MAP_FILE| List of adders treated as a black box by Yosys.| | | -| ADDITIONAL_FILES| Additional files to be added to `make issue` archive.| | | -| ADDITIONAL_GDS| Hardened macro GDS files listed here.| | | -| ADDITIONAL_LEFS| Hardened macro LEF view files listed here. The LEF information of the macros is immutable and used throughout all stages. Stored in the .odb file.| | | -| ADDITIONAL_LIBS| Hardened macro library files listed here. The library information is immutable and used throughout all stages. Not stored in the .odb file.| | | -| BLOCKS| Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile.| | | -| CAP_MARGIN| Specifies a capacitance margin when fixing max capacitance violations. This option allows you to overfix.| | | -| CDL_FILES| Insert additional Circuit Description Language (`.cdl`) netlist files.| | | -| CELL_PAD_IN_SITES_DETAIL_PLACEMENT| Cell padding on both sides in site widths to ease routability in detail placement.| 0| | -| CELL_PAD_IN_SITES_GLOBAL_PLACEMENT| Cell padding on both sides in site widths to ease routability during global placement.| 0| | -| CLKGATE_MAP_FILE| List of cells for gating clock treated as a black box by Yosys.| | | -| CORE_AREA| The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | | -| CORE_ASPECT_RATIO| The core aspect ratio (height / width). This value is ignored if `CORE_UTILIZATION` is undefined.| | | -| CORE_MARGIN| The margin between the core area and die area, specified in microns. Allowed values are either one value for all margins or a set of four values, one for each margin. The order of the four values are: `{bottom top left right}`. This variable is ignored if `CORE_UTILIZATION` is undefined.| | | -| CORE_UTILIZATION| The core utilization percentage (0-100).| | | -| CORNER| PVT corner library selection. Only available for ASAP7 and GF180 PDKs.| | | -| CTS_ARGS| Override `clock_tree_synthesis` arguments.| | | -| CTS_BUF_DISTANCE| Distance (in microns) between buffers.| | | -| CTS_BUF_LIST| List of cells used to construct the clock tree.| | | -| CTS_CLUSTER_DIAMETER| Maximum diameter (in microns) of sink cluster.| 20| | -| CTS_CLUSTER_SIZE| Maximum number of sinks per cluster.| 50| | -| CTS_SNAPSHOT| Creates ODB/SDC files prior to clock net and setup/hold repair.| | | -| DESIGN_NAME| The name of the top-level module of the design.| | | -| DESIGN_NICKNAME| DESIGN_NICKNAME just changes the directory name that ORFS outputs to be DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a different design.| | | -| DETAILED_METRICS| If set, then calls report_metrics prior to repair operations in the CTS and global route stages| 0| | -| DETAILED_ROUTE_ARGS| Add additional arguments for debugging purposes during detail route.| | | -| DETAILED_ROUTE_END_ITERATION| Maximum number of iterations.| 64| | -| DFF_LIB_FILES| Technology mapping liberty files for flip-flops.| | | -| DIE_AREA| The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | | -| DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| | | -| DONT_USE_LIBS| Set liberty files as `dont_use`.| | | -| DPO_MAX_DISPLACEMENT| Specifies how far an instance can be moved when optimizing.| 5 1| | -| ENABLE_DPO| Enable detail placement with improve_placement feature.| 1| | -| EQUIVALENCE_CHECK| Enable running equivalence checks to verify logical correctness of repair_timing.| 0| | -| FASTROUTE_TCL| Specifies a Tcl script with commands to run before FastRoute.| | | -| FILL_CELLS| Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped.| | | -| FILL_CONFIG| JSON rule file for metal fill during chip finishing.| | | -| FLOORPLAN_DEF| Use the DEF file to initialize floorplan.| | | -| FLOW_VARIANT| Flow variant to use, used in the flow variant directory name.| base| | -| GDS_ALLOW_EMPTY| Regular expression of module names of macros that have no .gds file| | | -| GDS_FILES| Path to platform GDS files.| | | -| GENERATE_ARTIFACTS_ON_FAILURE| For instance Bazel needs artifacts (.odb and .rpt files) on a failure to allow the user to save hours on re-running the failed step locally, but when working with a Makefile flow, it is more natural to fail the step and leave the user to manually inspect the logs and artifacts directly via the file system. Set to 1 to change the behavior to generate artifacts upon failure to e.g. do a global route. The exit code will still be non-zero on all other failures that aren't covered by the "useful to inspect the artifacts on failure" use-case. Example: just like detailed routing, a global route that fails with congestion, is not a build failure(as in exit code non-zero), it is a successful(as in zero exit code) global route that produce reports detailing the problem. Detailed route will not proceed, if there is global routing congestion This allows build systems, such as bazel, to create artifacts for global and detailed route, even if the operation had problems, without having know about the semantics between global and detailed route. Considering that global and detailed route can run for a long time and use a lot of memory, this allows inspecting results on a laptop for a build that ran on a server.| 0| | -| GLOBAL_PLACEMENT_ARGS| Use additional tuning parameters during global placement other than default args defined in global_place.tcl.| | | -| GLOBAL_ROUTE_ARGS| Replaces default arguments for global route.| -congestion_iterations 30 -congestion_report_iter_step 5 -verbose| | -| GND_NETS_VOLTAGES| Used for IR Drop calculation.| | | -| GPL_ROUTABILITY_DRIVEN| Specifies whether the placer should use routability driven placement.| 1| | -| GPL_TIMING_DRIVEN| Specifies whether the placer should use timing driven placement.| 1| | -| GUI_TIMING| Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc.| 1| | -| HOLD_SLACK_MARGIN| Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix or underfix (negative value, terminate retiming before 0 or positive slack). floorplan.tcl uses min of HOLD_SLACK_MARGIN and 0 (default hold slack margin). This avoids overrepair in floorplan for hold by default, but allows skipping hold repair using a negative HOLD_SLACK_MARGIN. Exiting timing repair early is useful in exploration where the .sdc has a fixed clock period at the design's target clock period and where HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair (extremely long running times) when exploring different parameter settings. When an ideal clock is used, that is before CTS, a clock insertion delay of 0 is used in timing paths. This creates a mismatch between macros that have a .lib file from after CTS, when the clock is propagated. To mitigate this, OpenSTA will use subtract the clock insertion delay of macros when calculating timing with ideal clock. Provided that min_clock_tree_path and max_clock_tree_path are in the .lib file, which is the case for macros built with OpenROAD. This is less accurate than if OpenROAD had created a placeholder clock tree for timing estimation purposes prior to CTS. There will inevitably be inaccuracies in the timing calculation prior to CTS. Use a slack margin that is low enough, even negative, to avoid overrepair. Inaccuracies in the timing prior to CTS can also lead to underrepair, but there no obvious and simple way to avoid underrapir in these cases. Overrepair can lead to excessive runtimes in repair or too much buffering being added, which can present itself as congestion of hold cells or buffer cells. Another use of SETUP/HOLD_SLACK_MARGIN is design parameter exploration when trying to find the minimum clock period for a design. The SDC_FILE for a design can be quite complicated and instead of modifying the clock period in the SDC_FILE, which can be non-trivial, the clock period can be fixed at the target frequency and the SETUP/HOLD_SLACK_MARGIN can be swept to find a plausible current minimum clock period.| 0| | -| IO_CONSTRAINTS| File path to the IO constraints .tcl file.| | | -| IO_PLACER_H| The metal layer on which to place the I/O pins horizontally (top and bottom of the die).| | | -| IO_PLACER_V| The metal layer on which to place the I/O pins vertically (sides of the die).| | | -| IR_DROP_LAYER| Default metal layer to report IR drop.| | | -| KLAYOUT_TECH_FILE| A mapping from LEF/DEF to GDS using the KLayout tool.| | | -| LATCH_MAP_FILE| List of latches treated as a black box by Yosys.| | | -| LIB_FILES| A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.| | | -| MACRO_BLOCKAGE_HALO| Distance beyond the edges of a macro that will also be covered by the blockage generated for that macro. Note that the default macro blockage halo comes from the largest of the specified MACRO_PLACE_HALO x or y values. This variable overrides that calculation.| | | -| MACRO_EXTENSION| Sets the number of GCells added to the blockages boundaries from macros.| | | -| MACRO_PLACEMENT| Specifies the path of a file on how to place certain macros manually using read_macro_placement.| | | -| MACRO_PLACEMENT_TCL| Specifies the path of a TCL file on how to place certain macros manually.| | | -| MACRO_PLACE_HALO| Horizontal/vertical halo around macros (microns). Used by automatic macro placement.| | | -| MACRO_ROWS_HALO_X| Horizontal distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.| | | -| MACRO_ROWS_HALO_Y| Vertical distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.| | | -| MACRO_WRAPPERS| The wrapper file that replaces existing macros with their wrapped version.| | | -| MAKE_TRACKS| Tcl file that defines add routing tracks to a floorplan.| | | -| MATCH_CELL_FOOTPRINT| Enforce sizing operations to only swap cells that have the same layout boundary.| 0| | -| MAX_ROUTING_LAYER| The highest metal layer name to be used in routing.| | | -| MIN_BUF_CELL_AND_PORTS| Used to insert a buffer cell to pass through wires. Used in synthesis.| | | -| MIN_ROUTING_LAYER| The lowest metal layer name to be used in routing.| | | -| PDN_TCL| File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.| | | -| PLACE_DENSITY| The desired placement density of cells. It reflects how spread the cells would be on the core area. 1.0 = closely dense. 0.0 = widely spread.| | | -| PLACE_DENSITY_LB_ADDON| Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists.| | | -| PLACE_PINS_ARGS| Arguments to place_pins| | | -| PLACE_SITE| Placement site for core cells defined in the technology LEF file.| | | -| PLATFORM| Specifies process design kit or technology node to be used.| | | -| POST_CTS_TCL| Specifies a Tcl script with commands to run after CTS is completed.| | | -| PROCESS| Technology node or process in use.| | | -| PWR_NETS_VOLTAGES| Used for IR Drop calculation.| | | -| RCX_RULES| RC Extraction rules file path.| | | -| RECOVER_POWER| Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].| 0| | -| REMOVE_ABC_BUFFERS| Remove abc buffers from the netlist. If timing repair in floorplanning is taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.| | yes| -| REMOVE_CELLS_FOR_EQY| String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.| | | -| REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| | | -| REPORT_CLOCK_SKEW| Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable.| 1| | -| RESYNTH_AREA_RECOVER| Enable re-synthesis for area reclaim.| 0| | -| RESYNTH_TIMING_RECOVER| Enable re-synthesis for timing optimization.| 0| | -| ROUTING_LAYER_ADJUSTMENT| Adjusts routing layer capacities to manage congestion and improve detailed routing. High values ease detailed routing but risk excessive detours and long global routing times, while low values reduce global routing failure but can complicate detailed routing. The global routing running time normally reduces dramatically (entirely design specific, but going from hours to minutes has been observed) when the value is low (such as 0.10). Sometimes, global routing will succeed with lower values and fail with higher values. Exploring results with different values can help shed light on the problem. Start with a too low value, such as 0.10, and bisect to value that works by doing multiple global routing runs. As a last resort, `make global_route_issue` and using the tools/OpenROAD/etc/deltaDebug.py can be useful to debug global routing errors. If there is something specific that is impossible to route, such as a clock line over a macro, global routing will terminate with DRC errors routes that could have been routed were it not for the specific impossible routes. deltaDebug.py should weed out the possible routes and leave a minimal failing case that pinpoints the problem.| 0.5| | -| RTLMP_AREA_WT| Weight for the area of the current floorplan.| 0.1| | -| RTLMP_ARGS| Overrides all other RTL macro placer arguments.| | | -| RTLMP_BOUNDARY_WT| Weight for the boundary or how far the hard macro clusters are from boundaries.| 50.0| | -| RTLMP_DEAD_SPACE| Specifies the target dead space percentage, which influences the utilization of a cluster.| 0.05| | -| RTLMP_FENCE_LX| Defines the lower left X coordinate for the global fence bounding box in microns.| 0.0| | -| RTLMP_FENCE_LY| Defines the lower left Y coordinate for the global fence bounding box in microns.| 0.0| | -| RTLMP_FENCE_UX| Defines the upper right X coordinate for the global fence bounding box in microns.| 100000000.0| | -| RTLMP_FENCE_UY| Defines the upper right Y coordinate for the global fence bounding box in microns.| 100000000.0| | -| RTLMP_MAX_INST| Maximum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | | -| RTLMP_MAX_LEVEL| Maximum depth of the physical hierarchy tree.| 2| | -| RTLMP_MAX_MACRO| Maximum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | | -| RTLMP_MIN_AR| Specifies the minimum aspect ratio (height/width).| 0.33| | -| RTLMP_MIN_INST| Minimum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | | -| RTLMP_MIN_MACRO| Minimum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | | -| RTLMP_NOTCH_WT| Weight for the notch, or the existence of dead space that cannot be used for placement and routing.| 10.0| | -| RTLMP_OUTLINE_WT| Weight for violating the fixed outline constraint, meaning that all clusters should be placed within the shape of their parent cluster.| 100.0| | -| RTLMP_RPT_DIR| Path to the directory where reports are saved.| | | -| RTLMP_SIGNATURE_NET_THRESHOLD| Minimum number of connections between two clusters to be identified as connected.| 50| | -| RTLMP_WIRELENGTH_WT| Weight for half-perimiter wirelength.| 100.0| | -| RULES_JSON| json files with the metrics baseline regression rules. In the ORFS Makefile, this defaults to $DESIGN_DIR/rules-base.json, but ORFS does not mandate the users source directory layout and this can be placed elsewhere when the user sets up an ORFS config.mk or from bazel-orfs.| | | -| RUN_LOG_NAME_STEM| Stem of the log file name, the log file will be named `$(LOG_DIR)/$(RUN_LOG_NAME_STEM).log`.| run| | -| RUN_SCRIPT| Path to script to run from `make run`, python or tcl script detected by .py or .tcl extension.| | | -| SC_LEF| Path to technology standard cell LEF file.| | | -| SDC_FILE| The path to design constraint (SDC) file.| | | -| SDC_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | | -| SEAL_GDS| Seal macro to place around the design.| | | -| SETUP_SLACK_MARGIN| Specifies a time margin for the slack when fixing setup violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). See HOLD_SLACK_MARGIN for more details.| 0| | -| SET_RC_TCL| Metal & Via RC definition file path.| | | -| SKIP_CTS_REPAIR_TIMING| Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running.| | | -| SKIP_GATE_CLONING| Do not use gate cloning transform to fix timing violations (default: use gate cloning).| | | -| SKIP_INCREMENTAL_REPAIR| Skip incremental repair in global route.| 0| | -| SKIP_LAST_GASP| Do not use last gasp optimization to fix timing violations (default: use gate last gasp).| | | -| SKIP_PIN_SWAP| Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).| | | -| SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| | | -| SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| | | -| SYNTH_ARGS| Optional synthesis variables for yosys.| -flatten| | -| SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| | | -| SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | | -| SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| | -| SYNTH_KEEP_MODULES| Mark modules to keep from getting removed in flattening.| | | -| SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096| | -| SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| 0| | -| SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| | | -| SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| | | -| TAPCELL_TCL| Path to Endcap and Welltie cells file.| | | -| TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| | | -| TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| | | -| TIEHI_CELL_AND_PORT| Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist.| | | -| TIELO_CELL_AND_PORT| Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.| | | -| TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100| | -| USE_FILL| Whether to perform metal density filling.| 0| | -| VERILOG_FILES| The path to the design Verilog files or JSON files providing a description of modules (check `yosys -h write_json` for more details).| | | -| VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| | | -| VERILOG_TOP_PARAMS| Apply toplevel params (if exist).| | | -| YOSYS_FLAGS| Flags to pass to yosys.| -v 3| | +| Variable | Description | Default | +| --- | --- | --- | +| ABC_AREA| Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED.| 0| +| ABC_CLOCK_PERIOD_IN_PS| Clock period to be used by STA during synthesis. Default value read from `constraint.sdc`.| | +| ABC_DRIVER_CELL| Default driver cell used during ABC synthesis.| | +| ABC_LOAD_IN_FF| During synthesis set_load value used.| | +| ABSTRACT_SOURCE| Which .odb file to use to create abstract| | +| ADDER_MAP_FILE| List of adders treated as a black box by Yosys.| | +| ADDITIONAL_FILES| Additional files to be added to `make issue` archive.| | +| ADDITIONAL_GDS| Hardened macro GDS files listed here.| | +| ADDITIONAL_LEFS| Hardened macro LEF view files listed here. The LEF information of the macros is immutable and used throughout all stages. Stored in the .odb file.| | +| ADDITIONAL_LIBS| Hardened macro library files listed here. The library information is immutable and used throughout all stages. Not stored in the .odb file.| | +| BLOCKS| Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile.| | +| CAP_MARGIN| Specifies a capacitance margin when fixing max capacitance violations. This option allows you to overfix.| | +| CDL_FILES| Insert additional Circuit Description Language (`.cdl`) netlist files.| | +| CELL_PAD_IN_SITES_DETAIL_PLACEMENT| Cell padding on both sides in site widths to ease routability in detail placement.| 0| +| CELL_PAD_IN_SITES_GLOBAL_PLACEMENT| Cell padding on both sides in site widths to ease routability during global placement.| 0| +| CLKGATE_MAP_FILE| List of cells for gating clock treated as a black box by Yosys.| | +| CORE_AREA| The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | +| CORE_ASPECT_RATIO| The core aspect ratio (height / width). This value is ignored if `CORE_UTILIZATION` is undefined.| 1.0| +| CORE_MARGIN| The margin between the core area and die area, specified in microns. Allowed values are either one value for all margins or a set of four values, one for each margin. The order of the four values are: `{bottom top left right}`. This variable is ignored if `CORE_UTILIZATION` is undefined.| 1.0| +| CORE_UTILIZATION| The core utilization percentage (0-100).| | +| CORNER| PVT corner library selection. Only available for ASAP7 and GF180 PDKs.| | +| CTS_ARGS| Override `clock_tree_synthesis` arguments.| | +| CTS_BUF_DISTANCE| Distance (in microns) between buffers.| | +| CTS_BUF_LIST| List of cells used to construct the clock tree. Overrides buffer inference.| | +| CTS_CLUSTER_DIAMETER| Maximum diameter (in microns) of sink cluster.| 20| +| CTS_CLUSTER_SIZE| Maximum number of sinks per cluster.| 50| +| CTS_LIB_NAME| Name of the Liberty library to use in selecting the clock buffers.| | +| CTS_SNAPSHOT| Creates ODB/SDC files prior to clock net and setup/hold repair.| | +| DESIGN_NAME| The name of the top-level module of the design.| | +| DESIGN_NICKNAME| DESIGN_NICKNAME just changes the directory name that ORFS outputs to be DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a different design.| | +| DETAILED_METRICS| If set, then calls report_metrics prior to repair operations in the CTS and global route stages| 0| +| DETAILED_ROUTE_ARGS| Add additional arguments for debugging purposes during detail route.| | +| DETAILED_ROUTE_END_ITERATION| Maximum number of iterations.| 64| +| DFF_LIB_FILES| Technology mapping liberty files for flip-flops.| | +| DIE_AREA| The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | +| DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| | +| DONT_USE_LIBS| Set liberty files as `dont_use`.| | +| DPO_MAX_DISPLACEMENT| Specifies how far an instance can be moved when optimizing.| 5 1| +| EARLY_SIZING_CAP_RATIO| Ratio between the input pin capacitance and the output pin load during initial gate sizing.| | +| ENABLE_DPO| Enable detail placement with improve_placement feature.| 1| +| EQUIVALENCE_CHECK| Enable running equivalence checks to verify logical correctness of repair_timing.| 0| +| FASTROUTE_TCL| Specifies a Tcl script with commands to run before FastRoute.| | +| FILL_CELLS| Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped.| | +| FILL_CONFIG| JSON rule file for metal fill during chip finishing.| | +| FLOORPLAN_DEF| Use the DEF file to initialize floorplan.| | +| FLOW_VARIANT| Flow variant to use, used in the flow variant directory name.| base| +| GDS_ALLOW_EMPTY| Regular expression of module names of macros that have no .gds file| | +| GDS_FILES| Path to platform GDS files.| | +| GENERATE_ARTIFACTS_ON_FAILURE| For instance Bazel needs artifacts (.odb and .rpt files) on a failure to allow the user to save hours on re-running the failed step locally, but when working with a Makefile flow, it is more natural to fail the step and leave the user to manually inspect the logs and artifacts directly via the file system. Set to 1 to change the behavior to generate artifacts upon failure to e.g. do a global route. The exit code will still be non-zero on all other failures that aren't covered by the "useful to inspect the artifacts on failure" use-case. Example: just like detailed routing, a global route that fails with congestion, is not a build failure(as in exit code non-zero), it is a successful(as in zero exit code) global route that produce reports detailing the problem. Detailed route will not proceed, if there is global routing congestion This allows build systems, such as bazel, to create artifacts for global and detailed route, even if the operation had problems, without having know about the semantics between global and detailed route. Considering that global and detailed route can run for a long time and use a lot of memory, this allows inspecting results on a laptop for a build that ran on a server.| 0| +| GLOBAL_PLACEMENT_ARGS| Use additional tuning parameters during global placement other than default args defined in global_place.tcl.| | +| GLOBAL_ROUTE_ARGS| Replaces default arguments for global route.| -congestion_iterations 30 -congestion_report_iter_step 5 -verbose| +| GND_NETS_VOLTAGES| Used for IR Drop calculation.| | +| GPL_ROUTABILITY_DRIVEN| Specifies whether the placer should use routability driven placement.| 1| +| GPL_TIMING_DRIVEN| Specifies whether the placer should use timing driven placement.| 1| +| GUI_TIMING| Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc.| 1| +| HOLD_SLACK_MARGIN| Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix or underfix (negative value, terminate retiming before 0 or positive slack). floorplan.tcl uses min of HOLD_SLACK_MARGIN and 0 (default hold slack margin). This avoids overrepair in floorplan for hold by default, but allows skipping hold repair using a negative HOLD_SLACK_MARGIN. Exiting timing repair early is useful in exploration where the .sdc has a fixed clock period at the design's target clock period and where HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair (extremely long running times) when exploring different parameter settings. When an ideal clock is used, that is before CTS, a clock insertion delay of 0 is used in timing paths. This creates a mismatch between macros that have a .lib file from after CTS, when the clock is propagated. To mitigate this, OpenSTA will use subtract the clock insertion delay of macros when calculating timing with ideal clock. Provided that min_clock_tree_path and max_clock_tree_path are in the .lib file, which is the case for macros built with OpenROAD. This is less accurate than if OpenROAD had created a placeholder clock tree for timing estimation purposes prior to CTS. There will inevitably be inaccuracies in the timing calculation prior to CTS. Use a slack margin that is low enough, even negative, to avoid overrepair. Inaccuracies in the timing prior to CTS can also lead to underrepair, but there no obvious and simple way to avoid underrapir in these cases. Overrepair can lead to excessive runtimes in repair or too much buffering being added, which can present itself as congestion of hold cells or buffer cells. Another use of SETUP/HOLD_SLACK_MARGIN is design parameter exploration when trying to find the minimum clock period for a design. The SDC_FILE for a design can be quite complicated and instead of modifying the clock period in the SDC_FILE, which can be non-trivial, the clock period can be fixed at the target frequency and the SETUP/HOLD_SLACK_MARGIN can be swept to find a plausible current minimum clock period.| 0| +| IO_CONSTRAINTS| File path to the IO constraints .tcl file.| | +| IO_PLACER_H| A list of metal layers on which the I/O pins are placed horizontally (top and bottom of the die).| | +| IO_PLACER_V| A list of metal layers on which the I/O pins are placed vertically (sides of the die).| | +| IR_DROP_LAYER| Default metal layer to report IR drop.| | +| KLAYOUT_TECH_FILE| A mapping from LEF/DEF to GDS using the KLayout tool.| | +| LATCH_MAP_FILE| List of latches treated as a black box by Yosys.| | +| LIB_FILES| A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.| | +| MACRO_BLOCKAGE_HALO| Distance beyond the edges of a macro that will also be covered by the blockage generated for that macro. Note that the default macro blockage halo comes from the largest of the specified MACRO_PLACE_HALO x or y values. This variable overrides that calculation.| | +| MACRO_EXTENSION| Sets the number of GCells added to the blockages boundaries from macros.| | +| MACRO_PLACEMENT| Specifies the path of a file on how to place certain macros manually using read_macro_placement.| | +| MACRO_PLACEMENT_TCL| Specifies the path of a TCL file on how to place certain macros manually.| | +| MACRO_PLACE_HALO| Horizontal/vertical halo around macros (microns). Used by automatic macro placement.| | +| MACRO_ROWS_HALO_X| Horizontal distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.| | +| MACRO_ROWS_HALO_Y| Vertical distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.| | +| MACRO_WRAPPERS| The wrapper file that replaces existing macros with their wrapped version.| | +| MAKE_TRACKS| Tcl file that defines add routing tracks to a floorplan.| | +| MATCH_CELL_FOOTPRINT| Enforce sizing operations to only swap cells that have the same layout boundary.| 0| +| MAX_ROUTING_LAYER| The highest metal layer name to be used in routing.| | +| MIN_BUF_CELL_AND_PORTS| Used to insert a buffer cell to pass through wires. Used in synthesis.| | +| MIN_ROUTING_LAYER| The lowest metal layer name to be used in routing.| | +| PDN_TCL| File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.| | +| PLACE_DENSITY| The desired average placement density of cells: 1.0 = dense, 0.0 = widely spread. The intended effort is also communicated by this parameter. Use a low value for faster builds and higher value for better quality of results. If a too low value is used, the placer will not be able to place all cells and a recommended minimum placement density can be found in the logs. A too high value can lead to excessive runtimes, even timeouts and subtle failures in the flow after placement, such as in CTS or global routing when timing repair fails. The default is platform specific.| | +| PLACE_DENSITY_LB_ADDON| Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists.| | +| PLACE_PINS_ARGS| Arguments to place_pins| | +| PLACE_SITE| Placement site for core cells defined in the technology LEF file.| | +| PLATFORM| Specifies process design kit or technology node to be used.| | +| PLATFORM_TCL| Specifies a Tcl script with commands to run before loading design.| | +| POST_CTS_TCL| Specifies a Tcl script with commands to run after CTS is completed.| | +| PRE_GLOBAL_ROUTE_TCL| Specifies a Tcl script with commands to run before global route.| | +| PROCESS| Technology node or process in use.| | +| PWR_NETS_VOLTAGES| Used for IR Drop calculation.| | +| RCX_RULES| RC Extraction rules file path.| | +| RECOVER_POWER| Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].| 0| +| REMOVE_ABC_BUFFERS (deprecated)| Remove abc buffers from the netlist. If timing repair in floorplanning is taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.| | +| REMOVE_CELLS_FOR_EQY| String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.| | +| REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| | +| REPORT_CLOCK_SKEW| Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable.| 1| +| ROUTING_LAYER_ADJUSTMENT| Adjusts routing layer capacities to manage congestion and improve detailed routing. High values ease detailed routing but risk excessive detours and long global routing times, while low values reduce global routing failure but can complicate detailed routing. The global routing running time normally reduces dramatically (entirely design specific, but going from hours to minutes has been observed) when the value is low (such as 0.10). Sometimes, global routing will succeed with lower values and fail with higher values. Exploring results with different values can help shed light on the problem. Start with a too low value, such as 0.10, and bisect to value that works by doing multiple global routing runs. As a last resort, `make global_route_issue` and using the tools/OpenROAD/etc/deltaDebug.py can be useful to debug global routing errors. If there is something specific that is impossible to route, such as a clock line over a macro, global routing will terminate with DRC errors routes that could have been routed were it not for the specific impossible routes. deltaDebug.py should weed out the possible routes and leave a minimal failing case that pinpoints the problem.| 0.5| +| RTLMP_AREA_WT| Weight for the area of the current floorplan.| 0.1| +| RTLMP_ARGS| Overrides all other RTL macro placer arguments.| | +| RTLMP_BOUNDARY_WT| Weight for the boundary or how far the hard macro clusters are from boundaries.| 50.0| +| RTLMP_DEAD_SPACE| Specifies the target dead space percentage, which influences the utilization of a cluster.| 0.05| +| RTLMP_FENCE_LX| Defines the lower left X coordinate for the global fence bounding box in microns.| 0.0| +| RTLMP_FENCE_LY| Defines the lower left Y coordinate for the global fence bounding box in microns.| 0.0| +| RTLMP_FENCE_UX| Defines the upper right X coordinate for the global fence bounding box in microns.| 100000000.0| +| RTLMP_FENCE_UY| Defines the upper right Y coordinate for the global fence bounding box in microns.| 100000000.0| +| RTLMP_MAX_INST| Maximum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | +| RTLMP_MAX_LEVEL| Maximum depth of the physical hierarchy tree.| 2| +| RTLMP_MAX_MACRO| Maximum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | +| RTLMP_MIN_AR| Specifies the minimum aspect ratio (height/width).| 0.33| +| RTLMP_MIN_INST| Minimum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | +| RTLMP_MIN_MACRO| Minimum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | +| RTLMP_NOTCH_WT| Weight for the notch, or the existence of dead space that cannot be used for placement and routing.| 10.0| +| RTLMP_OUTLINE_WT| Weight for violating the fixed outline constraint, meaning that all clusters should be placed within the shape of their parent cluster.| 100.0| +| RTLMP_RPT_DIR| Path to the directory where reports are saved.| | +| RTLMP_SIGNATURE_NET_THRESHOLD| Minimum number of connections between two clusters to be identified as connected.| 50| +| RTLMP_WIRELENGTH_WT| Weight for half-perimiter wirelength.| 100.0| +| RULES_JSON| json files with the metrics baseline regression rules. In the ORFS Makefile, this defaults to $DESIGN_DIR/rules-base.json, but ORFS does not mandate the users source directory layout and this can be placed elsewhere when the user sets up an ORFS config.mk or from bazel-orfs.| | +| RUN_LOG_NAME_STEM| Stem of the log file name, the log file will be named `$(LOG_DIR)/$(RUN_LOG_NAME_STEM).log`.| run| +| RUN_SCRIPT| Path to script to run from `make run`, python or tcl script detected by .py or .tcl extension.| | +| SC_LEF| Path to technology standard cell LEF file.| | +| SDC_FILE| The path to design constraint (SDC) file.| | +| SDC_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | +| SEAL_GDS| Seal macro to place around the design.| | +| SETUP_REPAIR_SEQUENCE| Specifies the sequence of moves to do in repair_timing -setup. This should be a string of move keywords separated by commas such as the default when not used: "unbuffer,sizedown,sizeup,swap,buffer,clone,split".| | +| SETUP_SLACK_MARGIN| Specifies a time margin for the slack when fixing setup violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). See HOLD_SLACK_MARGIN for more details.| 0| +| SET_RC_TCL| Metal & Via RC definition file path.| | +| SKIP_CTS_REPAIR_TIMING| Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running.| | +| SKIP_GATE_CLONING| Do not use gate cloning transform to fix timing violations (default: use gate cloning).| | +| SKIP_INCREMENTAL_REPAIR| Skip incremental repair in global route.| 0| +| SKIP_LAST_GASP| Do not use last gasp optimization to fix timing violations (default: use gate last gasp).| | +| SKIP_PIN_SWAP| Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).| | +| SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| | +| SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| | +| SWAP_ARITH_OPERATORS| Improve timing QoR by swapping ALU and MULT arithmetic operators.| | +| SYNTH_ARGS| Optional synthesis variables for yosys.| | +| SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| | +| SYNTH_CANONICALIZE_TCL| Specifies a Tcl script with commands to run as part of the synth canonicalize step.| | +| SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | +| SYNTH_HDL_FRONTEND| Select an alternative language frontend to ingest the design. Available option is "slang". If the variable is empty, design is read with the Yosys read_verilog command.| | +| SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| +| SYNTH_HIER_SEPARATOR| Separator used for the synthesis flatten stage.| .| +| SYNTH_KEEP_MODULES| Mark modules to keep from getting removed in flattening.| | +| SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096| +| SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| 0| +| SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| | +| SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| | +| TAPCELL_TCL| Path to Endcap and Welltie cells file.| | +| TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| | +| TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| | +| TIEHI_CELL_AND_PORT| Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist.| | +| TIELO_CELL_AND_PORT| Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.| | +| TIE_SEPARATION| Distance separating tie high/low instances from the load.| | +| TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100| +| USE_FILL| Whether to perform metal density filling.| 0| +| VERILOG_DEFINES| Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`| | +| VERILOG_FILES| The path to the design Verilog/SystemVerilog files providing a description of modules.| | +| VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| | +| VERILOG_TOP_PARAMS| Apply toplevel params (if exist).| | +| YOSYS_FLAGS| Flags to pass to yosys.| -v 3| ## synth variables - [ABC_AREA](#ABC_AREA) @@ -211,8 +258,11 @@ configuration file. - [MIN_BUF_CELL_AND_PORTS](#MIN_BUF_CELL_AND_PORTS) - [SDC_FILE](#SDC_FILE) - [SDC_GUT](#SDC_GUT) +- [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS) - [SYNTH_BLACKBOXES](#SYNTH_BLACKBOXES) +- [SYNTH_CANONICALIZE_TCL](#SYNTH_CANONICALIZE_TCL) - [SYNTH_GUT](#SYNTH_GUT) +- [SYNTH_HDL_FRONTEND](#SYNTH_HDL_FRONTEND) - [SYNTH_HIERARCHICAL](#SYNTH_HIERARCHICAL) - [SYNTH_KEEP_MODULES](#SYNTH_KEEP_MODULES) - [SYNTH_MEMORY_MAX_BITS](#SYNTH_MEMORY_MAX_BITS) @@ -221,6 +271,7 @@ configuration file. - [SYNTH_WRAPPED_OPERATORS](#SYNTH_WRAPPED_OPERATORS) - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT) - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT) +- [VERILOG_DEFINES](#VERILOG_DEFINES) - [VERILOG_FILES](#VERILOG_FILES) - [VERILOG_INCLUDE_DIRS](#VERILOG_INCLUDE_DIRS) - [VERILOG_TOP_PARAMS](#VERILOG_TOP_PARAMS) @@ -251,8 +302,6 @@ configuration file. - [PLACE_DENSITY_LB_ADDON](#PLACE_DENSITY_LB_ADDON) - [PLACE_SITE](#PLACE_SITE) - [REMOVE_ABC_BUFFERS](#REMOVE_ABC_BUFFERS) -- [RESYNTH_AREA_RECOVER](#RESYNTH_AREA_RECOVER) -- [RESYNTH_TIMING_RECOVER](#RESYNTH_TIMING_RECOVER) - [RTLMP_AREA_WT](#RTLMP_AREA_WT) - [RTLMP_ARGS](#RTLMP_ARGS) - [RTLMP_BOUNDARY_WT](#RTLMP_BOUNDARY_WT) @@ -272,18 +321,23 @@ configuration file. - [RTLMP_RPT_DIR](#RTLMP_RPT_DIR) - [RTLMP_SIGNATURE_NET_THRESHOLD](#RTLMP_SIGNATURE_NET_THRESHOLD) - [RTLMP_WIRELENGTH_WT](#RTLMP_WIRELENGTH_WT) +- [SETUP_REPAIR_SEQUENCE](#SETUP_REPAIR_SEQUENCE) - [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SKIP_GATE_CLONING](#SKIP_GATE_CLONING) - [SKIP_LAST_GASP](#SKIP_LAST_GASP) - [SKIP_PIN_SWAP](#SKIP_PIN_SWAP) - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) +- [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS) - [TAPCELL_TCL](#TAPCELL_TCL) +- [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT) +- [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT) - [TNS_END_PERCENT](#TNS_END_PERCENT) ## place variables - [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT) - [CELL_PAD_IN_SITES_GLOBAL_PLACEMENT](#CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) +- [EARLY_SIZING_CAP_RATIO](#EARLY_SIZING_CAP_RATIO) - [FLOORPLAN_DEF](#FLOORPLAN_DEF) - [GPL_ROUTABILITY_DRIVEN](#GPL_ROUTABILITY_DRIVEN) - [GPL_TIMING_DRIVEN](#GPL_TIMING_DRIVEN) @@ -298,8 +352,8 @@ configuration file. - [PLACE_PINS_ARGS](#PLACE_PINS_ARGS) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) -- [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT) -- [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT) +- [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS) +- [TIE_SEPARATION](#TIE_SEPARATION) ## cts variables @@ -309,6 +363,7 @@ configuration file. - [CTS_BUF_LIST](#CTS_BUF_LIST) - [CTS_CLUSTER_DIAMETER](#CTS_CLUSTER_DIAMETER) - [CTS_CLUSTER_SIZE](#CTS_CLUSTER_SIZE) +- [CTS_LIB_NAME](#CTS_LIB_NAME) - [CTS_SNAPSHOT](#CTS_SNAPSHOT) - [DETAILED_METRICS](#DETAILED_METRICS) - [EQUIVALENCE_CHECK](#EQUIVALENCE_CHECK) @@ -317,6 +372,7 @@ configuration file. - [POST_CTS_TCL](#POST_CTS_TCL) - [REMOVE_CELLS_FOR_EQY](#REMOVE_CELLS_FOR_EQY) - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) +- [SETUP_REPAIR_SEQUENCE](#SETUP_REPAIR_SEQUENCE) - [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SKIP_CTS_REPAIR_TIMING](#SKIP_CTS_REPAIR_TIMING) - [SKIP_GATE_CLONING](#SKIP_GATE_CLONING) @@ -333,8 +389,10 @@ configuration file. - [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN) - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) +- [PRE_GLOBAL_ROUTE_TCL](#PRE_GLOBAL_ROUTE_TCL) - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) +- [SETUP_REPAIR_SEQUENCE](#SETUP_REPAIR_SEQUENCE) - [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SKIP_GATE_CLONING](#SKIP_GATE_CLONING) - [SKIP_INCREMENTAL_REPAIR](#SKIP_INCREMENTAL_REPAIR) @@ -407,6 +465,7 @@ configuration file. - [LIB_FILES](#LIB_FILES) - [MACRO_EXTENSION](#MACRO_EXTENSION) - [PLATFORM](#PLATFORM) +- [PLATFORM_TCL](#PLATFORM_TCL) - [PROCESS](#PROCESS) - [RCX_RULES](#RCX_RULES) - [RECOVER_POWER](#RECOVER_POWER) @@ -418,6 +477,7 @@ configuration file. - [SET_RC_TCL](#SET_RC_TCL) - [SLEW_MARGIN](#SLEW_MARGIN) - [SYNTH_ARGS](#SYNTH_ARGS) +- [SYNTH_HIER_SEPARATOR](#SYNTH_HIER_SEPARATOR) - [TAP_CELL_NAME](#TAP_CELL_NAME) - [TECH_LEF](#TECH_LEF) - [USE_FILL](#USE_FILL) diff --git a/env.sh b/env.sh index 88021867cb..563c003a81 100755 --- a/env.sh +++ b/env.sh @@ -1,9 +1,9 @@ #!/usr/bin/env bash function __setpaths() { if [[ "$OSTYPE" == "darwin"* ]]; then - DIR="$(dirname $(perl -e 'use Cwd "abs_path";print abs_path(shift)' "${BASH_SOURCE[0]}"))" + DIR="$(dirname $(perl -e 'use Cwd "abs_path";print abs_path(shift)' "${BASH_SOURCE[0]:-${(%):-%x}}"))" else - DIR="$(dirname $(readlink -f "${BASH_SOURCE[0]}"))" + DIR="$(dirname $(readlink -f "${BASH_SOURCE[0]:-${(%):-%x}}"))" fi export OPENROAD=${DIR}/tools/OpenROAD diff --git a/etc/DependencyInstaller.sh b/etc/DependencyInstaller.sh index fba0a1c32a..c0927426d7 100755 --- a/etc/DependencyInstaller.sh +++ b/etc/DependencyInstaller.sh @@ -10,7 +10,7 @@ else fi # package versions -klayoutVersion=0.28.8 +klayoutVersion=0.28.17 verilatorVersion=5.026 _versionCompare() { @@ -94,7 +94,7 @@ _installUbuntuCleanUp() { } _installKlayoutDependenciesUbuntuAarch64() { - echo "Installing Klayout dependancies" + echo "Installing Klayout dependencies" export DEBIAN_FRONTEND=noninteractive apt-get -y update apt-get -y install build-essential \ @@ -116,6 +116,7 @@ _installUbuntuPackages() { help2man \ libfl-dev \ libfl2 \ + libgit2-dev \ libgoogle-perftools-dev \ libqt5multimediawidgets5 \ libqt5opengl5 \ @@ -135,7 +136,9 @@ _installUbuntuPackages() { packages=() # Choose libstdc++ version - if _versionCompare $1 -ge 24.04; then + if _versionCompare $1 -ge 25.04; then + packages+=("libstdc++-15-dev") + elif _versionCompare $1 -ge 24.04; then packages+=("libstdc++-14-dev") elif _versionCompare $1 -ge 22.10; then packages+=("libstdc++-12-dev") @@ -167,9 +170,9 @@ _installUbuntuPackages() { fi else if [[ $1 == 20.04 ]]; then - klayoutChecksum=15a26f74cf396d8a10b7985ed70ab135 + klayoutChecksum=f78d41edf5bcfa5f1990bde1a9307e9e else - klayoutChecksum=db751264399706a23d20455bb7624264 + klayoutChecksum=54748a49e1ab53e14cf5bf95feb2f25a fi wget https://www.klayout.org/downloads/Ubuntu-${1%.*}/klayout_${klayoutVersion}-1_amd64.deb md5sum -c <(echo "${klayoutChecksum} klayout_${klayoutVersion}-1_amd64.deb") || exit 1 @@ -232,7 +235,7 @@ _help() { cat <] # Installs all of OpenROAD's dependencies no # need to run -base or -common. Requires # privileged access. diff --git a/etc/DockerHelper.sh b/etc/DockerHelper.sh index 3eff831853..7d168b2ad0 100755 --- a/etc/DockerHelper.sh +++ b/etc/DockerHelper.sh @@ -33,6 +33,7 @@ usage: $0 [CMD] [OPTIONS] -password=PASSWORD Password to loging at the docker registry. -ci Install CI tools in image -dry-run Do not push images to the repository + -push-latest Push the latest image to the repository -no-constant-build-dir Do not use constant build directory -h -help Show this message and exits @@ -136,10 +137,22 @@ _push() { orfsTag=${org}/orfs:${tag} echo "Renaming docker image: ${builderTag} -> ${orfsTag}" ${DOCKER_CMD} tag ${builderTag} ${orfsTag} + if [[ "${dryRun}" == 1 ]]; then echo "[DRY-RUN] ${DOCKER_CMD} push ${orfsTag}" + if [[ "${pushLatest}" == 1 ]]; then + echo "[DRY-RUN] ${DOCKER_CMD} tag ${orfsTag} \"${org}/orfs:latest\"" + echo "[DRY-RUN] ${DOCKER_CMD} push \"${org}/orfs:latest\"" + fi else ${DOCKER_CMD} push ${orfsTag} + + # Only tag and push as latest if requested + if [[ "${pushLatest}" == 1 ]]; then + ${DOCKER_CMD} tag ${orfsTag} "${org}/orfs:latest" + ${DOCKER_CMD} push "${org}/orfs:latest" + echo "Tagged and pushed ${org}/orfs:latest" + fi fi fi } @@ -174,6 +187,7 @@ numThreads="-1" tag="" options="" dryRun=0 +pushLatest=0 while [ "$#" -gt 0 ]; do case "${1}" in @@ -186,6 +200,9 @@ while [ "$#" -gt 0 ]; do -dry-run ) dryRun=1 ;; + -push-latest ) + pushLatest=1 + ;; -os=* ) os="${1#*=}" ;; diff --git a/flow/.gitignore b/flow/.gitignore index 74da9d6a93..a08f9fc5cb 100644 --- a/flow/.gitignore +++ b/flow/.gitignore @@ -2,5 +2,3 @@ settings.mk vars.sh vars.gdb vars.tcl -user.bazelrc -bazel-* diff --git a/flow/Makefile b/flow/Makefile index c257d8e367..530ff511c4 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -89,23 +89,29 @@ include $(DESIGN_CONFIG) export DESIGN_DIR ?= $(dir $(DESIGN_CONFIG)) -# default value "base" is duplicated from variables.yaml because we need it +# default value "base" for FLOW_VARIANT and "." for WORK_HOME are duplicated +# from variables.yaml and variables.mk because we need it # earlier in the flow for BLOCKS. BLOCKS is a feature specific to the # ORFS Makefile. export FLOW_VARIANT?=base +export WORK_HOME?=. # BLOCKS is a ORFS make flow specific feature. ifneq ($(BLOCKS),) # Normally this comes from variables.yaml, but we need it here to set up these variables # which are part of the DESIGN_CONFIG. BLOCKS is a Makefile specific concept. - $(foreach block,$(BLOCKS),$(eval BLOCK_LEFS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef)) - $(foreach block,$(BLOCKS),$(eval BLOCK_LIBS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lib)) - $(foreach block,$(BLOCKS),$(eval BLOCK_GDS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds)) - $(foreach block,$(BLOCKS),$(eval BLOCK_CDL += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.cdl)) - $(foreach block,$(BLOCKS),$(eval BLOCK_LOG_FOLDERS += ./logs/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/)) + $(foreach block,$(BLOCKS),$(eval BLOCK_LEFS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef)) + $(foreach block,$(BLOCKS),$(eval BLOCK_TYP_LIBS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_typ.lib)) + $(foreach block,$(BLOCKS),$(eval BLOCK_FAST_LIBS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_fast.lib)) + $(foreach block,$(BLOCKS),$(eval BLOCK_SLOW_LIBS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_slow.lib)) + $(foreach block,$(BLOCKS),$(eval BLOCK_GDS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds)) + $(foreach block,$(BLOCKS),$(eval BLOCK_CDL += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.cdl)) + $(foreach block,$(BLOCKS),$(eval BLOCK_LOG_FOLDERS += $(WORK_HOME)/logs/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/)) export ADDITIONAL_LEFS += $(BLOCK_LEFS) - export ADDITIONAL_LIBS += $(BLOCK_LIBS) + export ADDITIONAL_LIBS += $(BLOCK_TYP_LIBS) + export ADDITIONAL_TYP_LIBS += $(BLOCK_TYP_LIBS) + export ADDITIONAL_FAST_LIBS += $(BLOCK_FAST_LIBS) + export ADDITIONAL_SLOW_LIBS += $(BLOCK_SLOW_LIBS) export ADDITIONAL_GDS += $(BLOCK_GDS) - export GDS_FILES += $(BLOCK_GDS) ifneq ($(CDL_FILES),) export CDL_FILES += $(BLOCK_CDL) endif @@ -140,7 +146,7 @@ SHELL := /usr/bin/env bash # location # - default is current install / clone directory ifeq ($(origin FLOW_HOME), undefined) -FLOW_HOME := $(abspath $(dir $(firstword $(MAKEFILE_LIST)))) + FLOW_HOME := $(abspath $(dir $(firstword $(MAKEFILE_LIST)))) endif export FLOW_HOME @@ -168,27 +174,19 @@ endef # Targets to harden Blocks in case of hierarchical flow is triggered .PHONY: build_macros -build_macros: $(BLOCK_LEFS) $(BLOCK_LIBS) +build_macros: $(BLOCK_LEFS) $(BLOCK_TYP_LIBS) -$(foreach block,$(BLOCKS),$(eval $(call GENERATE_ABSTRACT_RULE,./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef,./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lib,$(shell dirname $(DESIGN_CONFIG))/${block}/config.mk))) -$(foreach block,$(BLOCKS),$(eval ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds: ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef)) +$(foreach block,$(BLOCKS),$(eval $(call GENERATE_ABSTRACT_RULE,$(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef,$(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_typ.lib,$(shell dirname $(DESIGN_CONFIG))/${block}/config.mk))) +$(foreach block,$(BLOCKS),$(eval $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds: $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef)) # Utility to print tool version information #------------------------------------------------------------------------------- .PHONY: versions.txt versions.txt: mkdir -p $(OBJECTS_DIR) - @if [ -z "$(YOSYS_EXE)" ]; then \ - echo >> $(OBJECTS_DIR)/$@ "yosys not installed"; \ - else \ - $(YOSYS_EXE) -V > $(OBJECTS_DIR)/$@; \ - fi - @echo openroad `$(OPENROAD_EXE) -version` >> $(OBJECTS_DIR)/$@ - @if [ -z "$(KLAYOUT_CMD)" ]; then \ - echo >> $(OBJECTS_DIR)/$@ "klayout not installed"; \ - else \ - $(KLAYOUT_CMD) -zz -v >> $(OBJECTS_DIR)/$@; \ - fi + @echo "yosys $(if $(YOSYS_EXE),$(shell $(YOSYS_EXE) -V 2>&1),not available)" > $(OBJECTS_DIR)/$@ + @echo "openroad $(if $(OPENROAD_EXE),$(shell $(OPENROAD_EXE) -version 2>&1),not available)" >> $(OBJECTS_DIR)/$@ + @echo "klayout $(if $(KLAYOUT_CMD),$(shell $(KLAYOUT_CMD) -zz -v 2>&1),not available)" >> $(OBJECTS_DIR)/$@ # Pre-process libraries # ============================================================================== @@ -198,10 +196,10 @@ versions.txt: .SECONDEXPANSION: $(DONT_USE_LIBS): $$(filter %$$(@F) %$$(@F).gz,$(LIB_FILES)) @mkdir -p $(OBJECTS_DIR)/lib - $(UTILS_DIR)/preprocessLib.py -i $^ -o $@ + $(PYTHON_EXE) $(UTILS_DIR)/preprocessLib.py -i $^ -o $@ $(OBJECTS_DIR)/lib/merged.lib: $(DONT_USE_LIBS) - $(UTILS_DIR)/mergeLib.pl $(PLATFORM)_merged $(DONT_USE_LIBS) > $@ + $(PYTHON_EXE) $(UTILS_DIR)/merge_lib.py $(PLATFORM)_merged $(DONT_USE_LIBS) > $@ # Pre-process KLayout tech # ============================================================================== @@ -219,7 +217,7 @@ $(OBJECTS_DIR)/klayout.lyt: $(KLAYOUT_TECH_FILE) $(OBJECTS_DIR)/klayout_tech.lef .PHONY: do-klayout do-klayout: ifeq ($(KLAYOUT_ENV_VAR_IN_PATH),valid) - SC_LEF_RELATIVE_PATH="$$\(env('FLOW_HOME')\)/$(shell realpath --relative-to=$(FLOW_HOME) $(SC_LEF))"; \ + SC_LEF_RELATIVE_PATH="$(shell realpath --relative-to=$(RESULTS_DIR) $(SC_LEF))"; \ OTHER_LEFS_RELATIVE_PATHS=$$(echo "$(foreach file, $(OBJECTS_DIR)/klayout_tech.lef $(ADDITIONAL_LEFS),$$(realpath --relative-to=$(RESULTS_DIR) $(file)))"); \ sed 's,.*,'"$$SC_LEF_RELATIVE_PATH"''"$$OTHER_LEFS_RELATIVE_PATHS"',g' $(KLAYOUT_TECH_FILE) > $(OBJECTS_DIR)/klayout.lyt else @@ -260,14 +258,14 @@ synth-report: synth .PHONY: do-synth-report do-synth-report: - ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/synth_metrics.tcl) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys_metrics.log) + ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/synth_metrics.tcl) 2>&1 | tee $(abspath $(LOG_DIR)/1_2_yosys_metrics.log) .PHONY: memory memory: if [ -f $(RESULTS_DIR)/mem_hierarchical.json ]; then \ - python3 $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem_hierarchical.json; \ + $(PYTHON_EXE) $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem_hierarchical.json; \ fi - python3 $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem.json + $(PYTHON_EXE) $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem.json # ============================================================================== @@ -284,24 +282,24 @@ yosys-dependencies: $(YOSYS_DEPENDENCIES) .PHONY: do-yosys do-yosys: $(DONT_USE_SC_LIB) - $(SCRIPTS_DIR)/synth.sh $(SYNTH_SCRIPT) $(LOG_DIR)/1_1_yosys.log + $(SCRIPTS_DIR)/synth.sh $(SYNTH_SCRIPT) $(LOG_DIR)/1_2_yosys.log .PHONY: do-yosys-canonicalize do-yosys-canonicalize: yosys-dependencies $(DONT_USE_SC_LIB) $(SCRIPTS_DIR)/synth.sh $(SCRIPTS_DIR)/synth_canonicalize.tcl $(LOG_DIR)/1_1_yosys_canonicalize.log -$(RESULTS_DIR)/1_synth.rtlil: $(YOSYS_DEPENDENCIES) +$(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil: $(YOSYS_DEPENDENCIES) $(UNSET_AND_MAKE) do-yosys-canonicalize -$(RESULTS_DIR)/1_1_yosys.v: $(RESULTS_DIR)/1_synth.rtlil +$(RESULTS_DIR)/1_2_yosys.v: $(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil $(UNSET_AND_MAKE) do-yosys .PHONY: do-synth do-synth: mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) - cp $(RESULTS_DIR)/1_1_yosys.v $(RESULTS_DIR)/1_synth.v + cp $(RESULTS_DIR)/1_2_yosys.v $(RESULTS_DIR)/1_synth.v -$(RESULTS_DIR)/1_synth.v: $(RESULTS_DIR)/1_1_yosys.v +$(RESULTS_DIR)/1_synth.v: $(RESULTS_DIR)/1_2_yosys.v $(UNSET_AND_MAKE) do-synth .PHONY: clean_synth @@ -543,7 +541,8 @@ clean_cts: route: $(RESULTS_DIR)/5_route.odb \ $(RESULTS_DIR)/5_route.sdc -.PHONY: grt +.PHONY: grt globalroute +globalroute: grt grt: $(RESULTS_DIR)/5_1_grt.odb # ============================================================================== @@ -551,7 +550,7 @@ grt: $(RESULTS_DIR)/5_1_grt.odb # STEP 1: Run global route #------------------------------------------------------------------------------- -$(eval $(call do-step,5_1_grt,$(RESULTS_DIR)/4_cts.odb $(FASTROUTE_TCL) $(PRE_GLOBAL_ROUTE),global_route)) +$(eval $(call do-step,5_1_grt,$(RESULTS_DIR)/4_cts.odb $(FASTROUTE_TCL) $(PRE_GLOBAL_ROUTE_TCL),global_route)) # STEP 2: Run detailed route #------------------------------------------------------------------------------- @@ -613,12 +612,12 @@ finish: $(LOG_DIR)/6_report.log \ .PHONY: elapsed elapsed: - -@$(UTILS_DIR)/genElapsedTime.py -d $(BLOCK_LOG_FOLDERS) $(LOG_DIR) + -@$(PYTHON_EXE) $(UTILS_DIR)/genElapsedTime.py -d $(BLOCK_LOG_FOLDERS) $(LOG_DIR) # Useful when working with macros, see elapsed time for all macros in platform .PHONY: elapsed-all elapsed-all: - @$(UTILS_DIR)/genElapsedTime.py -d $(shell find $(WORK_HOME)/logs/$(PLATFORM)/*/*/ -type d) + @$(PYTHON_EXE) $(UTILS_DIR)/genElapsedTime.py -d $(shell find $(WORK_HOME)/logs/$(PLATFORM)/*/*/ -type d) $(eval $(call do-step,6_1_fill,$(RESULTS_DIR)/5_route.odb $(RESULTS_DIR)/5_route.sdc $(FILL_CONFIG),density_fill)) @@ -765,7 +764,7 @@ clean_all: clean_synth clean_floorplan clean_place clean_cts clean_route clean_f .PHONY: nuke nuke: clean_test clean_issues - rm -rf ./results ./logs ./reports ./objects + rm -rf $(WORK_HOME)/results $(WORK_HOME)/logs $(WORK_HOME)/reports $(WORK_HOME)/objects rm -rf layer_*.mps macrocell.list *best.plt *_pdn.def rm -rf *.rpt *.rpt.old *.def.v pin_dumper.log rm -f $(OBJECTS_DIR)/versions.txt $(OBJECTS_DIR)/copyright.txt dummy.guide diff --git a/flow/designs/asap7/aes-block/config.mk b/flow/designs/asap7/aes-block/config.mk index 616c8ff94e..08e2b12595 100644 --- a/flow/designs/asap7/aes-block/config.mk +++ b/flow/designs/asap7/aes-block/config.mk @@ -11,7 +11,7 @@ export ABC_AREA = 1 export CORE_UTILIZATION = 20 export CORE_ASPECT_RATIO = 1 export CORE_MARGIN = 2 -export PLACE_DENSITY = 0.65 +export PLACE_DENSITY = 0.53 export BLOCKS ?= aes_rcon aes_sbox export SYNTH_HIERARCHICAL = 1 diff --git a/flow/designs/asap7/aes-block/constraint.sdc b/flow/designs/asap7/aes-block/constraint.sdc index 15c31e02f8..8d7d7c5987 100644 --- a/flow/designs/asap7/aes-block/constraint.sdc +++ b/flow/designs/asap7/aes-block/constraint.sdc @@ -1,4 +1,4 @@ -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 475 set clk_io_pct 0.2 @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json index 513fab5283..e9fbea3933 100644 --- a/flow/designs/asap7/aes-block/rules-base.json +++ b/flow/designs/asap7/aes-block/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 2293.17, + "value": 2131.37, "compare": "<=" }, "constraints__clocks__count": { @@ -24,7 +24,7 @@ "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1491, + "value": 1866, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 71923, + "value": 75984, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -118.73, + "value": -243.45, "compare": ">=" }, "finish__design__instance__area": { @@ -60,11 +60,11 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 419, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -21.42, + "value": -43.48, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/aes-mbff/constraint.sdc b/flow/designs/asap7/aes-mbff/constraint.sdc index e45d9100bd..a9b5a65d9c 100644 --- a/flow/designs/asap7/aes-mbff/constraint.sdc +++ b/flow/designs/asap7/aes-mbff/constraint.sdc @@ -1,13 +1,13 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 400 +set clk_period 400 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/aes-mbff/rules-base.json b/flow/designs/asap7/aes-mbff/rules-base.json index a55c9a0b72..5b87e6a78e 100644 --- a/flow/designs/asap7/aes-mbff/rules-base.json +++ b/flow/designs/asap7/aes-mbff/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 1972.31, + "value": 1928.39, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2273, + "value": 2214, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 19686, + "value": 19594, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1712, + "value": 1704, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1712, + "value": 1704, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 89339, + "value": 76679, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -68.71, + "value": -42.46, "compare": ">=" }, "finish__design__instance__area": { - "value": 2359, + "value": 2272, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 856, + "value": 852, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -21.4, + "value": -15.57, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/aes/constraint.sdc b/flow/designs/asap7/aes/constraint.sdc index e45d9100bd..a9b5a65d9c 100644 --- a/flow/designs/asap7/aes/constraint.sdc +++ b/flow/designs/asap7/aes/constraint.sdc @@ -1,13 +1,13 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 400 +set clk_period 400 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/aes/rules-base.json b/flow/designs/asap7/aes/rules-base.json index 47f49f188b..5dfa3fd7a7 100644 --- a/flow/designs/asap7/aes/rules-base.json +++ b/flow/designs/asap7/aes/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 1972.31, + "value": 1928.39, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2273, + "value": 2214, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 19686, + "value": 19594, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1712, + "value": 1704, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1712, + "value": 1704, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 86627, + "value": 74787, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -70.11, + "value": -73.23, "compare": ">=" }, "finish__design__instance__area": { - "value": 2350, + "value": 2278, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 856, + "value": 852, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -19.6, + "value": -13.72, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/aes_lvt/constraint.sdc b/flow/designs/asap7/aes_lvt/constraint.sdc index e45d9100bd..a9b5a65d9c 100644 --- a/flow/designs/asap7/aes_lvt/constraint.sdc +++ b/flow/designs/asap7/aes_lvt/constraint.sdc @@ -1,13 +1,13 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 400 +set clk_period 400 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/aes_lvt/rules-base.json b/flow/designs/asap7/aes_lvt/rules-base.json index 051ab64450..d531c2e47a 100644 --- a/flow/designs/asap7/aes_lvt/rules-base.json +++ b/flow/designs/asap7/aes_lvt/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 77902, + "value": 72549, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,11 +48,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -29.62, + "value": -45.99, "compare": ">=" }, "finish__design__instance__area": { - "value": 2142, + "value": 2103, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -12.43, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/cva6/autotuner.json b/flow/designs/asap7/cva6/autotuner.json new file mode 100644 index 0000000000..a7315e9578 --- /dev/null +++ b/flow/designs/asap7/cva6/autotuner.json @@ -0,0 +1,43 @@ +{ + "_SDC_FILE_PATH": "constraint.sdc", + "_SDC_CLK_PERIOD": { + "type": "float", + "minmax": [ + 1000, + 1300 + ], + "step": 0 + }, + "CORE_UTILIZATION": { + "type": "int", + "minmax": [ + 65, + 75 + ], + "step": 1 + }, + "CORE_MARGIN": { + "type": "float", + "minmax": [ + 1.5, + 2 + ], + "step": 1 + }, + "CTS_CLUSTER_SIZE": { + "type": "int", + "minmax": [ + 40, + 60 + ], + "step": 1 + }, + "CTS_CLUSTER_DIAMETER": { + "type": "int", + "minmax": [ + 15, + 25 + ], + "step": 1 + } +} diff --git a/flow/designs/asap7/cva6/config.mk b/flow/designs/asap7/cva6/config.mk index 913fb21d5b..45b0278e17 100644 --- a/flow/designs/asap7/cva6/config.mk +++ b/flow/designs/asap7/cva6/config.mk @@ -1,179 +1,74 @@ -# -# TODO before enablement: pipe VERILOG_DEFINES through to yosys -# - export PLATFORM = asap7 export DESIGN_NAME = cva6 -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_pkg.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include/config_pkg.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include/cv32a65x_config_pkg.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include/riscv_pkg.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include/ariane_pkg.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/axi/src/axi_pkg.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include/wt_cache_pkg.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include/std_cache_pkg.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include/build_config_pkg.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvxif_example/include/cvxif_instr_pkg.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_pkg.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_pkg.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_cast_multi.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_classifier.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_divsqrt_multi.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_fma_multi.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_fma.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_noncomp.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_opgroup_block.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_opgroup_fmt_slice.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_rounding.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_top.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvxif_compressed_if_driver.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvxif_issue_register_commit_if_driver.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvxif_fu.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvxif_example/instr_decoder.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvxif_example/compressed_instr_decoder.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvxif_example/copro_alu.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/fifo_v3.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/lfsr.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/stream_arbiter.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/stream_mux.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/stream_demux.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/lzc.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/shift_reg.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/unread.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/popcount.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/exp_backoff.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/counter.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/delta_counter.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cva6.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cva6_rvfi_probes.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/alu.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/fpu_wrap.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/branch_unit.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/compressed_decoder.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/macro_decoder.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/controller.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/zcmt_decoder.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/csr_buffer.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/csr_regfile.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/decoder.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/ex_stage.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/instr_realign.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/id_stage.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/issue_read_operands.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/issue_stage.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/load_unit.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/load_store_unit.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/lsu_bypass.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/mult.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/multiplier.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/serdiv.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/perf_counters.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/ariane_regfile_ff.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/scoreboard.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/store_buffer.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/amo_buffer.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/store_unit.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/commit_stage.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/axi_shim.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cva6_accel_first_pass_decoder_stub.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/acc_dispatcher.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cva6_fifo_v3.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/frontend/btb.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/frontend/bht.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/frontend/bht2lvl.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/frontend/ras.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/frontend/instr_scan.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/frontend/instr_queue.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/frontend/frontend.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/wt_dcache_ctrl.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/wt_dcache_mem.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/wt_dcache_missunit.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/wt_dcache_wbuffer.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/wt_dcache.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/cva6_icache.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/wt_cache_subsystem.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/wt_axi_adapter.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/tag_cmp.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/axi_adapter.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/cache_ctrl.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/cva6_icache_axi_wrapper.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/std_cache_subsystem.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/std_nbdcache.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_resp_demux.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_read.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_write.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/cva6_hpdcache_subsystem.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/cva6_hpdcache_if_adapter.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/cva6_hpdcache_wrapper.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/hpdcache_sram_1rw.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/hpdcache_sram_wbyteenable_1rw.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/hpdcache_sram_wmask_1rw.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/pmp/src/pmp.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/pmp/src/pmp_entry.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/pmp/src/pmp_data_if.sv \ - $(PLATFORM_DIR)/verilog/fakeram7_256x32.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/common/local/util/tc_sram_wrapper.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/common/local/util/sram.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/common/local/util/sram_cache.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cva6_mmu/cva6_mmu.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cva6_mmu/cva6_ptw.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cva6_mmu/cva6_tlb.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cva6_mmu/cva6_shared_tlb.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_read_arbiter.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_write_arbiter.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_demux.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_lfsr.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sync_buffer.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fifo_reg.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fxarb.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_rrarb.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_mux.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_decoder.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_1hot_to_binary.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_prio_1hot_encoder.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wmask.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wbyteenable_1rw.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wmask_1rw.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_downsize.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_upsize.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_resize.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_arb.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_amo.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_cmo.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_core_arbiter.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl_pe.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_memctrl.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_miss_handler.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_mshr.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_rtab.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_uncached.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_plru.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_random.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv +# Some files are listed specifically vs. sorted wildcard to control the order +# (makes Verific happy) +export SRC_HOME = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME) +export VERILOG_FILES = $(sort $(wildcard $(SRC_HOME)/common/local/util/*.sv)) \ + $(SRC_HOME)/core/include/config_pkg.sv \ + $(SRC_HOME)/core/include/cv32a65x_config_pkg.sv \ + $(SRC_HOME)/core/include/riscv_pkg.sv \ + $(SRC_HOME)/core/include/ariane_pkg.sv \ + $(SRC_HOME)/core/include/build_config_pkg.sv \ + $(SRC_HOME)/core/include/std_cache_pkg.sv \ + $(SRC_HOME)/core/include/wt_cache_pkg.sv \ + $(sort $(wildcard $(SRC_HOME)/vendor/pulp-platform/common_cells/src/*.sv)) \ + $(SRC_HOME)/core/cvfpu/src/fpnew_pkg.sv \ + $(sort $(wildcard $(SRC_HOME)/vendor/pulp-platform/axi/src/*.sv)) \ + $(SRC_HOME)/core/cvfpu/src/fpnew_cast_multi.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_classifier.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_divsqrt_multi.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_fma.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_fma_multi.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_noncomp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_block.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_fmt_slice.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_rounding.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_top.sv \ + $(sort $(wildcard $(SRC_HOME)/core/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/pmp/src/*.sv)) \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_pkg.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_amo.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_cmo.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_core_arbiter.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl_pe.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_memctrl.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_miss_handler.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_mshr.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_rtab.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_uncached.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_plru.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_random.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_pkg.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_arb.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/common/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/utils/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cva6_mmu/*.sv)) \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv \ + $(SRC_HOME)/core/cvxif_example/include/cvxif_instr_pkg.sv \ + $(sort $(wildcard $(SRC_HOME)/core/frontend/*.sv)) \ + $(SRC_HOME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \ + $(PLATFORM_DIR)/verilog/fakeram7_64x256.sv \ + $(PLATFORM_DIR)/verilog/fakeram7_128x64.sv \ + $(PLATFORM_DIR)/verilog/fakeram7_64x28.sv \ + $(PLATFORM_DIR)/verilog/fakeram7_64x25.sv export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include \ $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/common_cells/include \ @@ -181,20 +76,32 @@ export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include export VERILOG_DEFINES += -D HPDCACHE_ASSERT_OFF -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram7_256x32.lef +export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram7_64x256.lef \ + $(PLATFORM_DIR)/lef/fakeram7_128x64.lef \ + $(PLATFORM_DIR)/lef/fakeram7_64x28.lef \ + $(PLATFORM_DIR)/lef/fakeram7_64x25.lef -export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_256x32.lib +export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x256.lib \ + $(PLATFORM_DIR)/lib/NLDM/fakeram7_128x64.lib \ + $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x28.lib \ + $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x25.lib export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc -export DIE_AREA = 0 0 250 250 -export CORE_AREA = 1.08 1.08 240 240 - -export PLACE_DENSITY = 0.50 +export CORE_UTILIZATION = 70 +export CORE_MARGIN = 2 +export MACRO_PLACE_HALO = 3 3 +export PLACE_DENSITY = 0.73 # a smoketest for this option, there are a # few last gasp iterations export SKIP_LAST_GASP ?= 1 +# For use with SYNTH_HIERARCHICAL +export SYNTH_MINIMUM_KEEP_SIZE ?= 40000 + +export SYNTH_HDL_FRONTEND = slang + +export ASAP7_USE_VT = RVT LVT SLVT -export SYNTH_USE_SLANG = 1 +export CTS_LIB_NAME = asap7sc7p5t_INVBUF_SLVT_FF_nldm_211120 diff --git a/flow/designs/asap7/cva6/constraint.sdc b/flow/designs/asap7/cva6/constraint.sdc index 3c9064541c..724d7f20ea 100644 --- a/flow/designs/asap7/cva6/constraint.sdc +++ b/flow/designs/asap7/cva6/constraint.sdc @@ -3,7 +3,7 @@ set clk_name main_clk set clk_port clk_i set clk_ports_list [list $clk_port] -set clk_period 1300 +set clk_period 1200 set input_delay 0.46 set output_delay 0.11 create_clock [get_ports $clk_port] -name $clk_name -period $clk_period @@ -14,15 +14,23 @@ create_clock [get_ports $clk_port] -name $clk_name -period $clk_period # set_dont_touch i_cache_subsystem/i_cva6_icache/gen_sram[*].data_sram # set_dont_touch i_cache_subsystem/i_cva6_icache/gen_sram[*].tag_sram # #constraint the timing to and from the sram black boxes -# set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] -# set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] -# set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] -# set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] +# set_input_delay -clock main_clk -max $input_delay \ +# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] +# set_input_delay -clock main_clk -max $input_delay \ +# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] +# set_input_delay -clock main_clk -max $input_delay \ +# i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] +# set_input_delay -clock main_clk -max $input_delay \ +# i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] -# set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] -# set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] -# set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] -# set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] +# set_output_delay $output_delay -max -clock main_clk \ +# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] +# set_output_delay $output_delay -max -clock main_clk \ +# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] +# set_output_delay $output_delay -max -clock main_clk \ +# i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] +# set_output_delay $output_delay -max -clock main_clk \ +# i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] set_false_path -to [get_ports {rvfi_probes_o}] diff --git a/flow/designs/asap7/cva6/rules-base.json b/flow/designs/asap7/cva6/rules-base.json index cf5cbd2b4c..203bb993c4 100644 --- a/flow/designs/asap7/cva6/rules-base.json +++ b/flow/designs/asap7/cva6/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 13337.62, + "value": 19725.15, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 15798, + "value": 20690, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 130789, + "value": 136421, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 11373, + "value": 11863, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 11373, + "value": 11863, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1241141, + "value": 1074578, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -181.59, + "value": -139.89, "compare": ">=" }, "finish__design__instance__area": { - "value": 16112, + "value": 20850, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 5686, + "value": 5931, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -18.66, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/ethmac/constraint.sdc b/flow/designs/asap7/ethmac/constraint.sdc index 71e846bd4a..1dd0000a50 100644 --- a/flow/designs/asap7/ethmac/constraint.sdc +++ b/flow/designs/asap7/ethmac/constraint.sdc @@ -3,8 +3,8 @@ set clk_period 1000 set clk_io_pct 0.2 set clk_port [get_ports $top_clk_name] create_clock -name $top_clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs +set non_clock_inputs [all_inputs -no_clocks] +set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs] set tx_clk_name mtx_clk_pad_i @@ -12,7 +12,7 @@ set tx_clk_port [get_ports $tx_clk_name] set tx_clk_period 300 create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port] -set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs +set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs] set rx_clk_name mrx_clk_pad_i @@ -20,12 +20,12 @@ set rx_clk_port [get_ports $rx_clk_name] set rx_clk_period 300 create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port] -set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs +set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs] set_clock_groups -name core_clock -logically_exclusive \ - -group [get_clocks $top_clk_name] \ - -group [get_clocks $tx_clk_name] \ - -group [get_clocks $rx_clk_name] + -group [get_clocks $top_clk_name] \ + -group [get_clocks $tx_clk_name] \ + -group [get_clocks $rx_clk_name] set_max_fanout 10 [current_design] diff --git a/flow/designs/asap7/ethmac/rules-base.json b/flow/designs/asap7/ethmac/rules-base.json index ad4a2c2eca..c6e93e2063 100644 --- a/flow/designs/asap7/ethmac/rules-base.json +++ b/flow/designs/asap7/ethmac/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 9662, + "value": 9343, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 71326, + "value": 71068, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 6202, + "value": 6180, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 6202, + "value": 6180, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 559393, + "value": 232938, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -187.76, + "value": -144.87, "compare": ">=" }, "finish__design__instance__area": { - "value": 10048, + "value": 9507, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 3101, + "value": 3090, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -44.05, + "value": -42.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/ethmac_lvt/constraint.sdc b/flow/designs/asap7/ethmac_lvt/constraint.sdc index c9a876f18f..465d603d0c 100644 --- a/flow/designs/asap7/ethmac_lvt/constraint.sdc +++ b/flow/designs/asap7/ethmac_lvt/constraint.sdc @@ -3,8 +3,8 @@ set clk_period 1000 set clk_io_pct 0.2 set clk_port [get_ports $top_clk_name] create_clock -name $top_clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs +set non_clock_inputs [all_inputs -no_clocks] +set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs] set tx_clk_name mtx_clk_pad_i @@ -12,7 +12,7 @@ set tx_clk_port [get_ports $tx_clk_name] set tx_clk_period 300 create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port] -set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs +set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs] set rx_clk_name mrx_clk_pad_i @@ -20,10 +20,10 @@ set rx_clk_port [get_ports $rx_clk_name] set rx_clk_period 300 create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port] -set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs +set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs] set_clock_groups -name core_clock -logically_exclusive \ - -group [get_clocks $top_clk_name] \ - -group [get_clocks $tx_clk_name] \ - -group [get_clocks $rx_clk_name] + -group [get_clocks $top_clk_name] \ + -group [get_clocks $tx_clk_name] \ + -group [get_clocks $rx_clk_name] diff --git a/flow/designs/asap7/ethmac_lvt/rules-base.json b/flow/designs/asap7/ethmac_lvt/rules-base.json index 2140f3006c..36f0d0a851 100644 --- a/flow/designs/asap7/ethmac_lvt/rules-base.json +++ b/flow/designs/asap7/ethmac_lvt/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 9583, + "value": 8660, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 69566, + "value": 66074, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 6049, + "value": 5746, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 6049, + "value": 5746, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 653875, + "value": 250591, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -90.17, + "value": -55.18, "compare": ">=" }, "finish__design__instance__area": { - "value": 9943, + "value": 8806, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 3025, + "value": 2873, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -22.89, + "value": -22.5, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/gcd-ccs/rules-base.json b/flow/designs/asap7/gcd-ccs/rules-base.json index 8b4b672953..3b2e302854 100644 --- a/flow/designs/asap7/gcd-ccs/rules-base.json +++ b/flow/designs/asap7/gcd-ccs/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 543, + "value": 540, "compare": "<=" }, "detailedplace__design__violations": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1357, + "value": 1224, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -96.02, + "value": -94.0, "compare": ">=" }, "finish__design__instance__area": { - "value": 57, + "value": 56, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 43, + "value": 24, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/asap7/gcd/constraint.sdc b/flow/designs/asap7/gcd/constraint.sdc index b4a21ce6a4..27de11250b 100644 --- a/flow/designs/asap7/gcd/constraint.sdc +++ b/flow/designs/asap7/gcd/constraint.sdc @@ -1,15 +1,15 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 310 +set clk_period 310 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/gcd/rules-base.json b/flow/designs/asap7/gcd/rules-base.json index b335dc0836..b770bcc571 100644 --- a/flow/designs/asap7/gcd/rules-base.json +++ b/flow/designs/asap7/gcd/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1410, + "value": 1271, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -74.47, + "value": -73.56, "compare": ">=" }, "finish__design__instance__area": { - "value": 60, + "value": 59, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 24, + "value": 27, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -33.05, + "value": -32.76, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/ibex/config.mk b/flow/designs/asap7/ibex/config.mk index 585708f775..170af31035 100644 --- a/flow/designs/asap7/ibex/config.mk +++ b/flow/designs/asap7/ibex/config.mk @@ -3,7 +3,13 @@ export PLATFORM = asap7 export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core -export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \ + $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v + +export VERILOG_INCLUDE_DIRS = \ + $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/ + +export SYNTH_HDL_FRONTEND = slang # if FLOW_VARIANT == pos_slack, use an SDC file that has a larger clock # resulting in positive slack diff --git a/flow/designs/asap7/ibex/constraint.sdc b/flow/designs/asap7/ibex/constraint.sdc index a58c555b69..30bb0a2292 100644 --- a/flow/designs/asap7/ibex/constraint.sdc +++ b/flow/designs/asap7/ibex/constraint.sdc @@ -1,4 +1,4 @@ -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 1260 set clk_io_pct 0.2 @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/ibex/constraint_pos_slack.sdc b/flow/designs/asap7/ibex/constraint_pos_slack.sdc index 7d9d39b7c1..d605a5aa8e 100644 --- a/flow/designs/asap7/ibex/constraint_pos_slack.sdc +++ b/flow/designs/asap7/ibex/constraint_pos_slack.sdc @@ -1,4 +1,4 @@ -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 1468 set clk_io_pct 0.2 @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/ibex/rules-base.json b/flow/designs/asap7/ibex/rules-base.json index 7e13390189..ab9f3184ac 100644 --- a/flow/designs/asap7/ibex/rules-base.json +++ b/flow/designs/asap7/ibex/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 2616.39, + "value": 2612.72, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2950, + "value": 2805, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 24427, + "value": 22941, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 2124, + "value": 1995, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 2124, + "value": 1995, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 132532, + "value": 106483, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -108.44, + "value": -75.22, "compare": ">=" }, "finish__design__instance__area": { - "value": 3035, + "value": 2867, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 1062, + "value": 997, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -15.17, + "value": -11.43, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc index 7f2469a084..bd163e05ff 100644 --- a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc +++ b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc @@ -1,6 +1,6 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 900 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc b/flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc index d37e20a0ee..46a528441e 100644 --- a/flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc +++ b/flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc @@ -7,7 +7,7 @@ set_units -time 1.0ps current_design jpeg_encoder create_clock -name "tclk" -period 1000.0 -waveform {0.0 500.0} [get_ports clk] -set_propagated_clock [ all_clocks ] +set_propagated_clock [all_clocks] set_load -pin_load -max 3.0 [get_ports {qnt_cnt[5]}] set_load -pin_load -max 3.0 [get_ports {qnt_cnt[4]}] set_load -pin_load -max 3.0 [get_ports {qnt_cnt[3]}] @@ -36,113 +36,113 @@ set_load -pin_load -max 3.0 [get_ports {amp[1]}] set_load -pin_load -max 3.0 [get_ports {amp[0]}] set_load -pin_load -max 3.0 [get_ports douten] set_max_delay 500 -from [list \ - [get_clocks tclk] ] -to [list \ - [get_ports douten] \ - [get_ports {amp[0]}] \ - [get_ports {amp[1]}] \ - [get_ports {amp[2]}] \ - [get_ports {amp[3]}] \ - [get_ports {amp[4]}] \ - [get_ports {amp[5]}] \ - [get_ports {amp[6]}] \ - [get_ports {amp[7]}] \ - [get_ports {amp[8]}] \ - [get_ports {amp[9]}] \ - [get_ports {amp[10]}] \ - [get_ports {amp[11]}] \ - [get_ports {rlen[0]}] \ - [get_ports {rlen[1]}] \ - [get_ports {rlen[2]}] \ - [get_ports {rlen[3]}] \ - [get_ports {size[0]}] \ - [get_ports {size[1]}] \ - [get_ports {size[2]}] \ - [get_ports {size[3]}] \ - [get_ports {qnt_cnt[0]}] \ - [get_ports {qnt_cnt[1]}] \ - [get_ports {qnt_cnt[2]}] \ - [get_ports {qnt_cnt[3]}] \ - [get_ports {qnt_cnt[4]}] \ - [get_ports {qnt_cnt[5]}] ] + [get_clocks tclk]] -to [list \ + [get_ports douten] \ + [get_ports {amp[0]}] \ + [get_ports {amp[1]}] \ + [get_ports {amp[2]}] \ + [get_ports {amp[3]}] \ + [get_ports {amp[4]}] \ + [get_ports {amp[5]}] \ + [get_ports {amp[6]}] \ + [get_ports {amp[7]}] \ + [get_ports {amp[8]}] \ + [get_ports {amp[9]}] \ + [get_ports {amp[10]}] \ + [get_ports {amp[11]}] \ + [get_ports {rlen[0]}] \ + [get_ports {rlen[1]}] \ + [get_ports {rlen[2]}] \ + [get_ports {rlen[3]}] \ + [get_ports {size[0]}] \ + [get_ports {size[1]}] \ + [get_ports {size[2]}] \ + [get_ports {size[3]}] \ + [get_ports {qnt_cnt[0]}] \ + [get_ports {qnt_cnt[1]}] \ + [get_ports {qnt_cnt[2]}] \ + [get_ports {qnt_cnt[3]}] \ + [get_ports {qnt_cnt[4]}] \ + [get_ports {qnt_cnt[5]}]] set_min_delay 500 \ - -from [list \ - [get_ports ena] \ - [get_ports rst] ] \ - -to [list \ - [get_clocks tclk] ] + -from [list \ + [get_ports ena] \ + [get_ports rst]] \ + -to [list \ + [get_clocks tclk]] group_path -weight 1.000000 -name cg_enable_group_tclk -through [list \ - [get_pins qnr_RC_CG_HIER_INST3/enable] \ - [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ - [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ - [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ - [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ - [get_pins qnr_RC_CG_HIER_INST3/enable] \ - [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ - [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ - [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ - [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ - [get_pins qnr_RC_CG_HIER_INST3/enable] \ - [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ - [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ - [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ - [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ - [get_pins RC_CG_DECLONE_HIER_INST/enable] \ - [get_pins qnr_RC_CG_HIER_INST3/enable] \ - [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ - [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ - [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ - [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ - [get_pins RC_CG_DECLONE_HIER_INST/enable] ] + [get_pins qnr_RC_CG_HIER_INST3/enable] \ + [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ + [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ + [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ + [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ + [get_pins qnr_RC_CG_HIER_INST3/enable] \ + [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ + [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ + [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ + [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ + [get_pins qnr_RC_CG_HIER_INST3/enable] \ + [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ + [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ + [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ + [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ + [get_pins RC_CG_DECLONE_HIER_INST/enable] \ + [get_pins qnr_RC_CG_HIER_INST3/enable] \ + [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ + [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ + [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ + [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ + [get_pins RC_CG_DECLONE_HIER_INST/enable]] set_clock_gating_check -setup 0.0 -set_input_delay 100 -clock tclk [get_ports ena] -set_input_delay 100 -clock tclk [get_ports rst] +set_input_delay 100 -clock tclk [get_ports ena] +set_input_delay 100 -clock tclk [get_ports rst] -set_input_delay 100 -clock tclk [get_ports {qnt_val[0]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[1]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[2]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[3]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[4]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[5]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[6]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[7]}] -set_input_delay 100 -clock tclk [get_ports {din[0]}] -set_input_delay 100 -clock tclk [get_ports {din[1]}] -set_input_delay 100 -clock tclk [get_ports {din[2]}] -set_input_delay 100 -clock tclk [get_ports {din[3]}] -set_input_delay 100 -clock tclk [get_ports {din[4]}] -set_input_delay 100 -clock tclk [get_ports {din[5]}] -set_input_delay 100 -clock tclk [get_ports {din[6]}] -set_input_delay 100 -clock tclk [get_ports {din[7]}] -set_input_delay 100 -clock tclk [get_ports dstrb] -set_output_delay 100 -clock tclk [get_ports douten] -set_output_delay 100 -clock tclk [get_ports {amp[0]}] -set_output_delay 100 -clock tclk [get_ports {amp[1]}] -set_output_delay 100 -clock tclk [get_ports {amp[2]}] -set_output_delay 100 -clock tclk [get_ports {amp[3]}] -set_output_delay 100 -clock tclk [get_ports {amp[4]}] -set_output_delay 100 -clock tclk [get_ports {amp[5]}] -set_output_delay 100 -clock tclk [get_ports {amp[6]}] -set_output_delay 100 -clock tclk [get_ports {amp[7]}] -set_output_delay 100 -clock tclk [get_ports {amp[8]}] -set_output_delay 100 -clock tclk [get_ports {amp[9]}] -set_output_delay 100 -clock tclk [get_ports {amp[10]}] -set_output_delay 100 -clock tclk [get_ports {amp[11]}] -set_output_delay 100 -clock tclk [get_ports {rlen[0]}] -set_output_delay 100 -clock tclk [get_ports {rlen[1]}] -set_output_delay 100 -clock tclk [get_ports {rlen[2]}] -set_output_delay 100 -clock tclk [get_ports {rlen[3]}] -set_output_delay 100 -clock tclk [get_ports {size[0]}] -set_output_delay 100 -clock tclk [get_ports {size[1]}] -set_output_delay 100 -clock tclk [get_ports {size[2]}] -set_output_delay 100 -clock tclk [get_ports {size[3]}] -set_output_delay 100 -clock tclk [get_ports {qnt_cnt[0]}] -set_output_delay 100 -clock tclk [get_ports {qnt_cnt[1]}] -set_output_delay 100 -clock tclk [get_ports {qnt_cnt[2]}] -set_output_delay 100 -clock tclk [get_ports {qnt_cnt[3]}] -set_output_delay 100 -clock tclk [get_ports {qnt_cnt[4]}] -set_output_delay 100 -clock tclk [get_ports {qnt_cnt[5]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[0]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[1]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[2]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[3]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[4]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[5]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[6]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[7]}] +set_input_delay 100 -clock tclk [get_ports {din[0]}] +set_input_delay 100 -clock tclk [get_ports {din[1]}] +set_input_delay 100 -clock tclk [get_ports {din[2]}] +set_input_delay 100 -clock tclk [get_ports {din[3]}] +set_input_delay 100 -clock tclk [get_ports {din[4]}] +set_input_delay 100 -clock tclk [get_ports {din[5]}] +set_input_delay 100 -clock tclk [get_ports {din[6]}] +set_input_delay 100 -clock tclk [get_ports {din[7]}] +set_input_delay 100 -clock tclk [get_ports dstrb] +set_output_delay 100 -clock tclk [get_ports douten] +set_output_delay 100 -clock tclk [get_ports {amp[0]}] +set_output_delay 100 -clock tclk [get_ports {amp[1]}] +set_output_delay 100 -clock tclk [get_ports {amp[2]}] +set_output_delay 100 -clock tclk [get_ports {amp[3]}] +set_output_delay 100 -clock tclk [get_ports {amp[4]}] +set_output_delay 100 -clock tclk [get_ports {amp[5]}] +set_output_delay 100 -clock tclk [get_ports {amp[6]}] +set_output_delay 100 -clock tclk [get_ports {amp[7]}] +set_output_delay 100 -clock tclk [get_ports {amp[8]}] +set_output_delay 100 -clock tclk [get_ports {amp[9]}] +set_output_delay 100 -clock tclk [get_ports {amp[10]}] +set_output_delay 100 -clock tclk [get_ports {amp[11]}] +set_output_delay 100 -clock tclk [get_ports {rlen[0]}] +set_output_delay 100 -clock tclk [get_ports {rlen[1]}] +set_output_delay 100 -clock tclk [get_ports {rlen[2]}] +set_output_delay 100 -clock tclk [get_ports {rlen[3]}] +set_output_delay 100 -clock tclk [get_ports {size[0]}] +set_output_delay 100 -clock tclk [get_ports {size[1]}] +set_output_delay 100 -clock tclk [get_ports {size[2]}] +set_output_delay 100 -clock tclk [get_ports {size[3]}] +set_output_delay 100 -clock tclk [get_ports {qnt_cnt[0]}] +set_output_delay 100 -clock tclk [get_ports {qnt_cnt[1]}] +set_output_delay 100 -clock tclk [get_ports {qnt_cnt[2]}] +set_output_delay 100 -clock tclk [get_ports {qnt_cnt[3]}] +set_output_delay 100 -clock tclk [get_ports {qnt_cnt[4]}] +set_output_delay 100 -clock tclk [get_ports {qnt_cnt[5]}] set_max_fanout 40.000 [current_design] set_max_transition 80.0 [current_design] set_clock_uncertainty -setup 20.0 [get_clocks tclk] diff --git a/flow/designs/asap7/jpeg/rules-base.json b/flow/designs/asap7/jpeg/rules-base.json index 6d4217d2e3..37cf7724de 100644 --- a/flow/designs/asap7/jpeg/rules-base.json +++ b/flow/designs/asap7/jpeg/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 7117.21, + "value": 7008.24, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 7801, + "value": 7287, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 66869, + "value": 63593, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 5815, + "value": 5530, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 5815, + "value": 5530, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 317533, + "value": 181528, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -52,11 +52,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 7973, + "value": 7375, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 2907, + "value": 2765, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/asap7/jpeg_lvt/config.mk b/flow/designs/asap7/jpeg_lvt/config.mk index 975596c3a4..4b77c09e67 100644 --- a/flow/designs/asap7/jpeg_lvt/config.mk +++ b/flow/designs/asap7/jpeg_lvt/config.mk @@ -8,15 +8,6 @@ export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc export ABC_AREA = 1 -export ADDITIONAL_LIBS = $(LIB_DIR)/asap7sc7p5t_AO_LVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_LVT_FF_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_LVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_LVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_LVT_FF_nldm_220123.lib - -export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_L_220121a.gds -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/asap7sc7p5t_28_L_1x_220121a.lef - export CORE_UTILIZATION = 30 export CORE_ASPECT_RATIO = 1 export CORE_MARGIN = 2 @@ -25,3 +16,6 @@ export PLACE_DENSITY = 0.60 export TNS_END_PERCENT = 100 export RECOVER_POWER = 100 +export ASAP7_USE_VT = LVT + + diff --git a/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc index a1f1601f12..d1aa7a70f9 100644 --- a/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc +++ b/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc @@ -1,6 +1,6 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 1100 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/jpeg_lvt/rules-base.json b/flow/designs/asap7/jpeg_lvt/rules-base.json index feb87d0f48..8f6bc56ba2 100644 --- a/flow/designs/asap7/jpeg_lvt/rules-base.json +++ b/flow/designs/asap7/jpeg_lvt/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 7707, + "value": 7477, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 67286, + "value": 66675, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 5851, + "value": 5798, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 5851, + "value": 5798, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 315524, + "value": 187616, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -52,11 +52,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 7778, + "value": 7543, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 2926, + "value": 2899, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/asap7/mock-alu/constraints.sdc b/flow/designs/asap7/mock-alu/constraints.sdc index 2a2d4d2f56..dd93e54e87 100644 --- a/flow/designs/asap7/mock-alu/constraints.sdc +++ b/flow/designs/asap7/mock-alu/constraints.sdc @@ -5,15 +5,15 @@ set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * 0.7] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * 0.7] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] set output_regs [get_cells *io_out_REG*] -if {[llength $output_regs] == 0} { - puts "Error: Could not find *io_out_REG*" - exit 1 +if { [llength $output_regs] == 0 } { + puts "Error: Could not find *io_out_REG*" + exit 1 } diff --git a/flow/designs/asap7/mock-alu/rules-base.json b/flow/designs/asap7/mock-alu/rules-base.json index 656330e652..bbec5f551f 100644 --- a/flow/designs/asap7/mock-alu/rules-base.json +++ b/flow/designs/asap7/mock-alu/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 61395, + "value": 59049, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -515.34, + "value": -506.14, "compare": ">=" }, "finish__design__instance__area": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 148, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/asap7/mock-array/Element/io.tcl b/flow/designs/asap7/mock-array/Element/io.tcl index 07e4edceb6..e0e50243c7 100644 --- a/flow/designs/asap7/mock-array/Element/io.tcl +++ b/flow/designs/asap7/mock-array/Element/io.tcl @@ -1,58 +1,51 @@ # bazel has root of OpenROAD-flow-scripts as working directory foreach prefix {"" flow/} { set f ${prefix}designs/src/mock-array/util.tcl - if {[file exists $f]} { + if { [file exists $f] } { source $f } } set assignments [list \ - top bottom \ - [list [ concat \ - {*}[match_pins io_ins_down.*] \ - {*}[match_pins io_outs_up.*] \ - ] \ - [ concat \ - {*}[match_pins io_outs_down.*] \ - {*}[match_pins io_ins_up.*] \ - ]] \ - left right \ - [list [ concat \ - {*}[match_pins io_ins_right.*] \ - {*}[match_pins io_outs_left.*] \ - ] \ - [ concat \ - {*}[match_pins io_outs_right.*] \ - {*}[match_pins io_ins_left.*] \ - ]] \ - left right \ - [list [ concat \ - {*}[match_pins io_lsbIns_.*] \ - ] \ - [ concat \ - {*}[match_pins io_lsbOuts_.*] \ - ]] -] + top bottom \ + [list [concat \ + {*}[match_pins io_ins_down.*] \ + {*}[match_pins io_outs_up.*]] \ + [concat \ + {*}[match_pins io_outs_down.*] \ + {*}[match_pins io_ins_up.*]]] \ + left right \ + [list [concat \ + {*}[match_pins io_ins_right.*] \ + {*}[match_pins io_outs_left.*]] \ + [concat \ + {*}[match_pins io_outs_right.*] \ + {*}[match_pins io_ins_left.*]]] \ + left right \ + [list [concat \ + {*}[match_pins io_lsbIns_.*]] \ + [concat \ + {*}[match_pins io_lsbOuts_.*]]]] -proc zip {list1 list2} { - set result {} - set length [llength $list1] - set skip [expr [llength $list2] - [llength $list1]] - for {set i 0} {$i < $length} {incr i} { - lappend result [lindex $list2 [expr $skip + $i]] [lindex $list1 $i] - } - return $result +proc zip { list1 list2 } { + set result {} + set length [llength $list1] + set skip [expr [llength $list2] - [llength $list1]] + for { set i 0 } { $i < $length } { incr i } { + lappend result [lindex $list2 [expr $skip + $i]] [lindex $list1 $i] + } + return $result } foreach {direction direction2 names} $assignments { - set mirrored [zip {*}$names] - set_io_pin_constraint -region $direction2:* -pin_names [lindex $names 1] - # Test pins across multiple metal layers; so don't group - # pins as a group of pins must be on a single metal layer. - # - # set_io_pin_constraint -group -order -pin_names [lindex $names 1] - set_io_pin_constraint -mirrored_pins $mirrored + set mirrored [zip {*}$names] + set_io_pin_constraint -region $direction2:* -pin_names [lindex $names 1] + # Test pins across multiple metal layers; so don't group + # pins as a group of pins must be on a single metal layer. + # + # set_io_pin_constraint -group -order -pin_names [lindex $names 1] + set_io_pin_constraint -mirrored_pins $mirrored } set_io_pin_constraint -region top:* -pin_names clock diff --git a/flow/designs/asap7/mock-array/config.mk b/flow/designs/asap7/mock-array/config.mk index 599dc6bed4..6b694315ff 100644 --- a/flow/designs/asap7/mock-array/config.mk +++ b/flow/designs/asap7/mock-array/config.mk @@ -26,6 +26,10 @@ export DIE_AREA = $(shell \ export MACRO_PLACE_HALO = 0 2.16 export RTLMP_BOUNDARY_WT = 0 export RTLMP_FLOW ?= 1 +export RTLMP_MAX_INST = 250 +export RTLMP_MIN_INST = 50 +export RTLMP_MAX_MACRO = 64 +export RTLMP_MIN_MACRO = 8 export BLOCKS ?= Element diff --git a/flow/designs/asap7/mock-array/io.tcl b/flow/designs/asap7/mock-array/io.tcl index 9f1cdde4a5..1bf0ee962b 100644 --- a/flow/designs/asap7/mock-array/io.tcl +++ b/flow/designs/asap7/mock-array/io.tcl @@ -1,35 +1,30 @@ # bazel has root of OpenROAD-flow-scripts as working directory foreach prefix {"" flow/} { set f ${prefix}designs/src/mock-array/util.tcl - if {[file exists $f]} { + if { [file exists $f] } { source $f } } set assignments [list \ - top \ - [ concat \ - {*}[match_pins io_ins_down_.*] \ - {*}[match_pins io_outs_up_.*] \ - ] \ - bottom \ - [ concat \ - {*}[match_pins io_ins_up_.*] \ - {*}[match_pins io_outs_down_.*] \ - ] \ - left \ - [ concat \ - {*}[match_pins io_ins_right_.*] \ - {*}[match_pins io_outs_left_.*] \ - ] \ - right \ - [ concat \ - {*}[match_pins io_ins_left_.*] \ - {*}[match_pins io_outs_right_.*] \ - {*}[match_pins io_lsbs_.*] \ - ] \ -] + top \ + [concat \ + {*}[match_pins io_ins_down_.*] \ + {*}[match_pins io_outs_up_.*]] \ + bottom \ + [concat \ + {*}[match_pins io_ins_up_.*] \ + {*}[match_pins io_outs_down_.*]] \ + left \ + [concat \ + {*}[match_pins io_ins_right_.*] \ + {*}[match_pins io_outs_left_.*]] \ + right \ + [concat \ + {*}[match_pins io_ins_left_.*] \ + {*}[match_pins io_outs_right_.*] \ + {*}[match_pins io_lsbs_.*]]] foreach {direction names} $assignments { - set_io_pin_constraint -region $direction:* -pin_names $names + set_io_pin_constraint -region $direction:* -pin_names $names } diff --git a/flow/designs/asap7/mock-array/macro-placement.tcl b/flow/designs/asap7/mock-array/macro-placement.tcl index 18bd768798..6eed9be902 100644 --- a/flow/designs/asap7/mock-array/macro-placement.tcl +++ b/flow/designs/asap7/mock-array/macro-placement.tcl @@ -15,11 +15,14 @@ set x_offset [expr [$core xMin] + ([$core dx] - (7 * $x_pitch) - [$bbox getDX])/ set y_offset [expr [$core yMin] + ([$core dy] - (7 * $y_pitch) - [$bbox getDY])/2] # Loop through the 8x8 array, add the offset, and invoke place_macro -for {set i 0} {$i < 8} {incr i} { - for {set j 0} {$j < 8} {incr j} { - set macro_name [format "ces_%d_%d" $i $j] - set x_location [expr {$j * $x_pitch + $x_offset}] - set y_location [expr {$i * $y_pitch + $y_offset}] - place_macro -macro_name $macro_name -location [list [expr [ord::dbu_to_microns 1] * $x_location] [expr [ord::dbu_to_microns 1] * $y_location]] -orientation R0 - } +for { set i 0 } { $i < 8 } { incr i } { + for { set j 0 } { $j < 8 } { incr j } { + set macro_name [format "ces_%d_%d" $i $j] + set x_location [expr { $j * $x_pitch + $x_offset }] + set y_location [expr { $i * $y_pitch + $y_offset }] + place_macro -macro_name $macro_name -location \ + [list [expr [ord::dbu_to_microns 1] * $x_location] \ + [expr [ord::dbu_to_microns 1] * $y_location]] \ + -orientation R0 + } } diff --git a/flow/designs/asap7/mock-array/power.tcl b/flow/designs/asap7/mock-array/power.tcl index c53beade09..b132101bd8 100644 --- a/flow/designs/asap7/mock-array/power.tcl +++ b/flow/designs/asap7/mock-array/power.tcl @@ -1,7 +1,7 @@ source $::env(SCRIPTS_DIR)/util.tcl foreach libFile $::env(LIB_FILES) { - if {[lsearch -exact $::env(ADDITIONAL_LIBS) $libFile] == -1} { + if { [lsearch -exact $::env(ADDITIONAL_LIBS) $libFile] == -1 } { read_liberty $libFile } } @@ -14,8 +14,8 @@ log_cmd link_design MockArray log_cmd read_sdc $::env(RESULTS_DIR)/6_final.sdc log_cmd read_spef $::env(RESULTS_DIR)/6_final.spef puts "read_spef for ces_*_* macros" -for {set x 0} {$x < 8} {incr x} { - for {set y 0} {$y < 8} {incr y} { +for { set x 0 } { $x < 8 } { incr x } { + for { set y 0 } { $y < 8 } { incr y } { read_spef -path ces_${x}_${y} results/asap7/mock-array_Element/base/6_final.spef } } @@ -36,7 +36,7 @@ set clock_period [expr [get_property [get_clocks] period] * 1e-12] foreach pin $pins { set activity [get_property $pin activity] set activity_origin [lindex $activity 2] - if {$activity_origin != "vcd"} { + if { $activity_origin != "vcd" } { continue } puts $fp "set_power_activity \ @@ -51,32 +51,32 @@ set no_vcd_activity {} foreach pin $pins { set activity [get_property $pin activity] set activity_origin [lindex $activity 2] - if {$activity_origin == "vcd"} { + if { $activity_origin == "vcd" } { continue } - if {$activity_origin == "constant"} { + if { $activity_origin == "constant" } { continue } - if {$activity_origin == "unknown"} { + if { $activity_origin == "unknown" } { continue } - if {[get_property $pin is_hierarchical]} { + if { [get_property $pin is_hierarchical] } { continue } - if {$activity_origin == "clock"} { + if { $activity_origin == "clock" } { continue } set direction [get_property $pin direction] - if {$direction == "internal"} { + if { $direction == "internal" } { continue } lappend no_vcd_activity "[get_full_name $pin] $activity $direction" - if {[llength $no_vcd_activity] >= 10} { + if { [llength $no_vcd_activity] >= 10 } { break } } -if {[llength $no_vcd_activity] > 0} { +if { [llength $no_vcd_activity] > 0 } { puts "Error: Listing [llength $no_vcd_activity] pins without activity from $vcd_file:" foreach pin $no_vcd_activity { puts $pin @@ -85,8 +85,8 @@ if {[llength $no_vcd_activity] > 0} { } set ces {} -for {set x 0} {$x < 8} {incr x} { - for {set y 0} {$y < 8} {incr y} { +for { set x 0 } { $x < 8 } { incr x } { + for { set y 0 } { $y < 8 } { incr y } { lappend ces ces_${x}_${y} } } @@ -94,7 +94,7 @@ for {set x 0} {$x < 8} {incr x} { puts {report_power -instances [get_cells $ces]} report_power -instances [get_cells $ces] -proc total_power {} { +proc total_power { } { return [lindex [sta::design_power [sta::corners]] 3] } @@ -108,13 +108,14 @@ set total_power_user_activity [total_power] puts "Total power from VCD: $total_power_vcd" puts "Total power from user activity: $total_power_user_activity" -if {$total_power_vcd == $total_power_user_activity} { +if { $total_power_vcd == $total_power_user_activity } { puts "Error: settting user power activity had no effect, expected some loss in accuracy" exit 1 } -if {abs($total_power_vcd - $total_power_user_activity) > 1e-3} { - puts "Error: Total power mismatch between VCD and user activity: $total_power_vcd vs $total_power_user_activity" +if { abs($total_power_vcd - $total_power_user_activity) > 1e-3 } { + puts "Error: Total power mismatch between VCD and user activity: \ + $total_power_vcd vs $total_power_user_activity" exit 1 } diff --git a/flow/designs/asap7/mock-array/rules-base.json b/flow/designs/asap7/mock-array/rules-base.json index daa5093b94..ca0dbc34d6 100644 --- a/flow/designs/asap7/mock-array/rules-base.json +++ b/flow/designs/asap7/mock-array/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 35802.37, + "value": 35273.33, "compare": "<=" }, "constraints__clocks__count": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": 0.0, + "value": -457.76, "compare": ">=" }, "finish__design__instance__area": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 536, + "value": 605, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -10.0, + "value": -111.1, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/mock-cpu/constraint.sdc b/flow/designs/asap7/mock-cpu/constraint.sdc index 15002f21dd..4648916e35 100644 --- a/flow/designs/asap7/mock-cpu/constraint.sdc +++ b/flow/designs/asap7/mock-cpu/constraint.sdc @@ -10,11 +10,13 @@ set clk_period 333 set clk2_period 1000 set clk1_name clk -create_clock -name $clk1_name -period $clk_period -waveform [list 0 [expr $clk_period/2]] [get_ports $clk1_name] +create_clock -name $clk1_name -period $clk_period -waveform \ + [list 0 [expr $clk_period/2]] [get_ports $clk1_name] set_clock_uncertainty 10 [get_clocks $clk1_name] set clk2_name clk_uncore -create_clock -name $clk2_name -period $clk2_period -waveform [list 0 [expr $clk_period/2]] [get_ports $clk2_name] +create_clock -name $clk2_name -period $clk2_period -waveform \ + [list 0 [expr $clk_period/2]] [get_ports $clk2_name] set_clock_uncertainty 10 [get_clocks $clk2_name] set_clock_groups -group $clk1_name -group $clk2_name -asynchronous -allow_paths @@ -31,7 +33,7 @@ set_false_path -to [get_ports *rst_n] set non_clk_inputs {} set clock_ports [list [get_ports $clk1_name] [get_ports $clk2_name]] foreach input [all_inputs] { - if {[lsearch -exact $clock_ports $input] == -1} { + if { [lsearch -exact $clock_ports $input] == -1 } { lappend non_clk_inputs $input } } diff --git a/flow/designs/asap7/mock-cpu/io.tcl b/flow/designs/asap7/mock-cpu/io.tcl index 01693e7da3..ea8b842fc3 100644 --- a/flow/designs/asap7/mock-cpu/io.tcl +++ b/flow/designs/asap7/mock-cpu/io.tcl @@ -1,9 +1,10 @@ # bazel has root of OpenROAD-flow-scripts as working directory foreach prefix {"" flow/} { set f ${prefix}designs/src/mock-array/util.tcl - if {[file exists $f]} { + if { [file exists $f] } { source $f } } -set_io_pin_constraint -order -group -region bottom:* -pin_names [concat [match_pins .*] [match_pins clk input 1]] +set_io_pin_constraint -order -group -region bottom:* \ + -pin_names [concat [match_pins .*] [match_pins clk input 1]] diff --git a/flow/designs/asap7/mock-cpu/rules-base.json b/flow/designs/asap7/mock-cpu/rules-base.json index d299f58c15..4cd178023b 100644 --- a/flow/designs/asap7/mock-cpu/rules-base.json +++ b/flow/designs/asap7/mock-cpu/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 7398, + "value": 7389, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 53867, + "value": 52446, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -52,7 +52,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 7961, + "value": 7638, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 101, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/config.mk b/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/config.mk index ce5a44e06c..3c1a32d84c 100644 --- a/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/config.mk +++ b/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/config.mk @@ -11,6 +11,7 @@ export PLACE_DENSITY = 0.80 # fakeram7 doesn't block off M5, so limit to M4 here. # However, PDN will use M5, so it is still added to blockages. export MAX_ROUTING_LAYER = M4 +export MIN_CLK_ROUTING_LAYER = M2 export PLACE_PINS_ARGS = -min_distance 6 -min_distance_in_tracks export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/riscv32i-mock-sram/fakeram7_256x32/io.tcl diff --git a/flow/designs/asap7/riscv32i-mock-sram/rules-base.json b/flow/designs/asap7/riscv32i-mock-sram/rules-base.json index a661910f66..e38e846845 100644 --- a/flow/designs/asap7/riscv32i-mock-sram/rules-base.json +++ b/flow/designs/asap7/riscv32i-mock-sram/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2269, + "value": 2395, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 127446, + "value": 95161, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,11 +48,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -103.06, + "value": -79.2, "compare": ">=" }, "finish__design__instance__area": { - "value": 2307, + "value": 2464, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -10.0, + "value": -11.73, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/riscv32i/config.mk b/flow/designs/asap7/riscv32i/config.mk index 7775e498c8..60313250f5 100644 --- a/flow/designs/asap7/riscv32i/config.mk +++ b/flow/designs/asap7/riscv32i/config.mk @@ -4,11 +4,6 @@ export PLATFORM = asap7 export SYNTH_HIERARCHICAL ?= 1 -export RTLMP_MIN_INST = 1000 -export RTLMP_MAX_INST = 3500 -export RTLMP_MIN_MACRO = 1 -export RTLMP_MAX_MACRO = 5 - export SYNTH_MINIMUM_KEEP_SIZE ?= 10000 export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/riscv32i/*.v)) diff --git a/flow/designs/asap7/riscv32i/constraint.sdc b/flow/designs/asap7/riscv32i/constraint.sdc index 74dca22a8f..9868986799 100644 --- a/flow/designs/asap7/riscv32i/constraint.sdc +++ b/flow/designs/asap7/riscv32i/constraint.sdc @@ -1,6 +1,6 @@ current_design riscv_top -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 1260 set clk_io_pct 0.125 @@ -9,6 +9,6 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set non_clock_inputs [all_inputs -no_clocks] +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/riscv32i/rules-base.json b/flow/designs/asap7/riscv32i/rules-base.json index abf9096660..ce0d33577c 100644 --- a/flow/designs/asap7/riscv32i/rules-base.json +++ b/flow/designs/asap7/riscv32i/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 3191, + "value": 3109, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 12507, + "value": 11777, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1088, + "value": 1024, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1088, + "value": 1024, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 137800, + "value": 83651, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -113.89, + "value": -44.21, "compare": ">=" }, "finish__design__instance__area": { - "value": 3234, + "value": 3180, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 827, + "value": 512, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -14.39, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/swerv_wrapper/BUILD.bazel b/flow/designs/asap7/swerv_wrapper/BUILD.bazel index e0b7a45eb4..e97eee723b 100644 --- a/flow/designs/asap7/swerv_wrapper/BUILD.bazel +++ b/flow/designs/asap7/swerv_wrapper/BUILD.bazel @@ -100,10 +100,6 @@ orfs_flow( arguments = { "LIB_MODEL": "CCS", "SYNTH_HIERARCHICAL": "1", - "RTLMP_MAX_INST": "30000", - "RTLMP_MIN_INST": "5000", - "RTLMP_MAX_MACRO": "30", - "RTLMP_MIN_MACRO": "4", "DIE_AREA": "0 0 550 600", "CORE_AREA": "5 5 545 595", "PLACE_PINS_ARGS": "-exclude left:* -exclude right:*", diff --git a/flow/designs/asap7/swerv_wrapper/config.mk b/flow/designs/asap7/swerv_wrapper/config.mk index 2e3716df43..2a22c2dde9 100644 --- a/flow/designs/asap7/swerv_wrapper/config.mk +++ b/flow/designs/asap7/swerv_wrapper/config.mk @@ -42,12 +42,6 @@ export SYNTH_KEEP_MODULES ?= \ ram_256x34 -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 30 -export RTLMP_MIN_MACRO = 4 - export LIB_MODEL = CCS export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \ diff --git a/flow/designs/asap7/swerv_wrapper/constraint.sdc b/flow/designs/asap7/swerv_wrapper/constraint.sdc index f679177441..2cae11c882 100644 --- a/flow/designs/asap7/swerv_wrapper/constraint.sdc +++ b/flow/designs/asap7/swerv_wrapper/constraint.sdc @@ -1,15 +1,15 @@ current_design swerv_wrapper -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 2500 +set clk_period 2500 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/swerv_wrapper/rules-base.json b/flow/designs/asap7/swerv_wrapper/rules-base.json index 6f5045049c..e1ce5d7c25 100644 --- a/flow/designs/asap7/swerv_wrapper/rules-base.json +++ b/flow/designs/asap7/swerv_wrapper/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1919981, + "value": 1867701, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 950, + "value": 286, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/asap7/uart/constraint.sdc b/flow/designs/asap7/uart/constraint.sdc index cc49402954..b58ae3408f 100644 --- a/flow/designs/asap7/uart/constraint.sdc +++ b/flow/designs/asap7/uart/constraint.sdc @@ -1,13 +1,13 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 300 +set clk_period 300 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/uart/rules-base.json b/flow/designs/asap7/uart/rules-base.json index 220aa64156..80006ed54c 100644 --- a/flow/designs/asap7/uart/rules-base.json +++ b/flow/designs/asap7/uart/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -24.54, + "value": -20.24, "compare": ">=" }, "finish__design__instance__area": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -13.14, + "value": -11.75, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf12/aes/constraint.sdc b/flow/designs/gf12/aes/constraint.sdc index a930ae4ba7..a820710ab4 100644 --- a/flow/designs/gf12/aes/constraint.sdc +++ b/flow/designs/gf12/aes/constraint.sdc @@ -1,17 +1,17 @@ current_design aes_cipher_top -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 420 +set clk_period 420 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] set_timing_derate -early 0.9500 diff --git a/flow/designs/gf12/ariane/config.mk b/flow/designs/gf12/ariane/config.mk index cfb21ab138..28194633ef 100644 --- a/flow/designs/gf12/ariane/config.mk +++ b/flow/designs/gf12/ariane/config.mk @@ -24,9 +24,6 @@ export PLACE_DENSITY ?= 0.50 export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/io.tcl -# to be removed once gpl is fixed for "corner buffers" issue -export GPL_KEEP_OVERFLOW = 0 - export MACRO_PLACE_HALO = 7 7 export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl diff --git a/flow/designs/gf12/ariane/constraint.sdc b/flow/designs/gf12/ariane/constraint.sdc index 2430c4b71e..d5971e4984 100644 --- a/flow/designs/gf12/ariane/constraint.sdc +++ b/flow/designs/gf12/ariane/constraint.sdc @@ -1,495 +1,495 @@ -create_clock [get_ports clk_i] -name core_clock -period 3400 -waveform {0 850} -set_input_delay -clock core_clock 1000 [get_ports rst_ni] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[63]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[62]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[61]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[60]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[59]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[58]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[57]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[56]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[55]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[54]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[53]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[52]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[51]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[50]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[49]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[48]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[47]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[46]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[45]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[44]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[43]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[42]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[41]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[40]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[39]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[38]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[37]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[36]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[35]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[34]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[33]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[32]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[31]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[30]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[29]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[28]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[27]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[26]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[25]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[24]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[23]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[22]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[21]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[20]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[19]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[18]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[17]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[16]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[15]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[14]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[13]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[12]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[11]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[10]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[9]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[8]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[7]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[6]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[5]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[4]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[3]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[2]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[1]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[0]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[63]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[62]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[61]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[60]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[59]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[58]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[57]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[56]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[55]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[54]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[53]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[52]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[51]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[50]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[49]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[48]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[47]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[46]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[45]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[44]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[43]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[42]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[41]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[40]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[39]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[38]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[37]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[36]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[35]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[34]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[33]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[32]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[31]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[30]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[29]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[28]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[27]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[26]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[25]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[24]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[23]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[22]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[21]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[20]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[19]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[18]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[17]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[16]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[15]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[14]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[13]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[12]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[11]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[10]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[9]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[8]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[7]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[6]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[5]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[4]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[3]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[2]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[1]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[0]}] -set_input_delay -clock core_clock 1000 [get_ports {irq_i[1]}] -set_input_delay -clock core_clock 1000 [get_ports {irq_i[0]}] -set_input_delay -clock core_clock 1000 [get_ports ipi_i] -set_input_delay -clock core_clock 1000 [get_ports time_irq_i] -set_input_delay -clock core_clock 1000 [get_ports debug_req_i] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[81]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[80]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[79]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[78]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[77]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[76]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[75]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[74]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[73]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[72]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[71]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[70]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[69]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[68]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[67]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[66]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[65]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[64]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[63]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[62]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[61]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[60]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[59]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[58]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[57]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[56]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[55]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[54]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[53]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[52]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[51]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[50]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[49]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[48]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[47]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[46]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[45]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[44]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[43]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[42]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[41]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[40]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[39]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[38]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[37]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[36]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[35]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[34]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[33]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[32]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[31]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[30]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[29]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[28]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[27]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[26]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[25]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[24]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[23]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[22]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[21]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[20]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[19]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[18]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[17]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[16]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[15]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[14]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[13]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[12]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[11]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[10]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[9]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[8]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[7]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[6]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[5]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[4]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[3]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[2]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[1]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[0]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[277]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[276]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[275]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[274]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[273]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[272]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[271]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[270]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[269]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[268]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[267]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[266]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[265]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[264]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[263]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[262]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[261]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[260]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[259]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[258]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[257]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[256]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[255]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[254]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[253]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[252]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[251]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[250]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[249]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[248]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[247]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[246]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[245]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[244]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[243]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[242]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[241]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[240]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[239]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[238]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[237]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[236]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[235]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[234]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[233]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[232]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[231]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[230]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[229]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[228]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[227]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[226]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[225]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[224]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[223]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[222]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[221]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[220]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[219]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[218]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[217]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[216]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[215]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[214]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[213]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[212]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[211]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[210]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[209]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[208]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[207]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[206]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[205]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[204]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[203]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[202]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[201]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[200]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[199]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[198]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[197]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[196]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[195]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[194]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[193]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[192]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[191]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[190]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[189]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[188]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[187]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[186]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[185]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[184]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[183]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[182]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[181]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[180]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[179]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[178]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[177]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[176]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[175]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[174]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[173]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[172]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[171]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[170]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[169]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[168]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[167]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[166]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[165]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[164]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[163]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[162]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[161]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[160]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[159]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[158]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[157]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[156]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[155]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[154]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[153]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[152]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[151]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[150]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[149]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[148]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[147]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[146]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[145]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[144]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[143]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[142]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[141]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[140]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[139]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[138]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[137]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[136]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[135]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[134]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[133]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[132]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[131]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[130]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[129]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[128]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[127]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[126]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[125]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[124]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[123]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[122]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[121]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[120]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[119]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[118]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[117]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[116]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[115]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[114]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[113]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[112]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[111]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[110]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[109]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[108]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[107]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[106]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[105]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[104]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[103]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[102]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[101]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[100]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[99]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[98]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[97]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[96]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[95]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[94]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[93]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[92]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[91]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[90]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[89]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[88]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[87]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[86]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[85]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[84]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[83]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[82]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[81]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[80]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[79]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[78]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[77]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[76]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[75]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[74]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[73]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[72]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[71]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[70]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[69]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[68]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[67]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[66]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[65]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[64]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[63]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[62]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[61]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[60]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[59]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[58]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[57]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[56]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[55]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[54]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[53]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[52]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[51]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[50]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[49]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[48]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[47]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[46]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[45]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[44]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[43]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[42]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[41]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[40]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[39]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[38]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[37]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[36]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[35]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[34]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[33]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[32]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[31]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[30]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[29]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[28]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[27]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[26]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[25]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[24]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[23]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[22]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[21]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[20]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[19]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[18]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[17]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[16]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[15]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[14]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[13]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[12]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[11]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[10]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[9]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[8]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[7]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[6]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[5]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[4]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[3]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[2]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[1]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[0]}] +create_clock [get_ports clk_i] -name core_clock -period 3400 -waveform {0 850} +set_input_delay -clock core_clock 1000 [get_ports rst_ni] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[63]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[62]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[61]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[60]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[59]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[58]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[57]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[56]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[55]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[54]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[53]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[52]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[51]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[50]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[49]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[48]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[47]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[46]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[45]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[44]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[43]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[42]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[41]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[40]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[39]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[38]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[37]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[36]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[35]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[34]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[33]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[32]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[31]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[30]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[29]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[28]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[27]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[26]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[25]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[24]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[23]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[22]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[21]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[20]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[19]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[18]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[17]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[16]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[15]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[14]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[13]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[12]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[11]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[10]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[9]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[8]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[7]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[6]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[5]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[4]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[3]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[2]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[1]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[0]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[63]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[62]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[61]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[60]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[59]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[58]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[57]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[56]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[55]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[54]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[53]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[52]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[51]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[50]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[49]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[48]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[47]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[46]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[45]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[44]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[43]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[42]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[41]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[40]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[39]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[38]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[37]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[36]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[35]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[34]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[33]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[32]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[31]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[30]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[29]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[28]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[27]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[26]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[25]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[24]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[23]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[22]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[21]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[20]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[19]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[18]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[17]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[16]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[15]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[14]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[13]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[12]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[11]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[10]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[9]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[8]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[7]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[6]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[5]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[4]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[3]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[2]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[1]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[0]}] +set_input_delay -clock core_clock 1000 [get_ports {irq_i[1]}] +set_input_delay -clock core_clock 1000 [get_ports {irq_i[0]}] +set_input_delay -clock core_clock 1000 [get_ports ipi_i] +set_input_delay -clock core_clock 1000 [get_ports time_irq_i] +set_input_delay -clock core_clock 1000 [get_ports debug_req_i] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[81]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[80]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[79]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[78]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[77]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[76]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[75]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[74]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[73]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[72]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[71]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[70]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[69]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[68]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[67]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[66]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[65]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[64]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[63]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[62]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[61]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[60]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[59]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[58]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[57]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[56]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[55]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[54]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[53]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[52]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[51]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[50]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[49]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[48]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[47]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[46]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[45]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[44]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[43]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[42]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[41]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[40]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[39]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[38]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[37]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[36]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[35]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[34]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[33]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[32]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[31]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[30]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[29]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[28]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[27]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[26]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[25]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[24]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[23]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[22]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[21]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[20]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[19]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[18]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[17]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[16]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[15]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[14]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[13]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[12]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[11]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[10]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[9]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[8]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[7]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[6]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[5]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[4]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[3]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[2]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[1]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[0]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[277]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[276]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[275]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[274]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[273]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[272]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[271]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[270]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[269]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[268]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[267]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[266]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[265]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[264]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[263]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[262]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[261]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[260]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[259]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[258]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[257]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[256]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[255]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[254]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[253]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[252]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[251]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[250]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[249]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[248]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[247]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[246]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[245]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[244]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[243]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[242]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[241]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[240]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[239]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[238]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[237]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[236]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[235]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[234]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[233]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[232]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[231]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[230]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[229]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[228]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[227]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[226]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[225]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[224]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[223]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[222]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[221]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[220]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[219]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[218]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[217]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[216]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[215]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[214]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[213]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[212]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[211]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[210]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[209]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[208]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[207]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[206]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[205]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[204]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[203]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[202]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[201]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[200]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[199]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[198]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[197]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[196]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[195]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[194]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[193]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[192]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[191]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[190]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[189]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[188]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[187]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[186]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[185]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[184]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[183]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[182]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[181]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[180]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[179]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[178]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[177]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[176]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[175]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[174]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[173]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[172]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[171]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[170]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[169]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[168]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[167]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[166]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[165]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[164]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[163]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[162]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[161]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[160]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[159]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[158]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[157]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[156]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[155]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[154]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[153]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[152]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[151]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[150]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[149]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[148]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[147]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[146]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[145]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[144]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[143]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[142]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[141]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[140]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[139]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[138]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[137]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[136]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[135]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[134]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[133]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[132]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[131]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[130]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[129]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[128]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[127]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[126]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[125]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[124]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[123]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[122]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[121]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[120]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[119]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[118]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[117]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[116]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[115]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[114]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[113]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[112]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[111]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[110]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[109]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[108]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[107]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[106]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[105]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[104]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[103]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[102]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[101]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[100]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[99]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[98]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[97]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[96]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[95]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[94]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[93]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[92]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[91]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[90]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[89]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[88]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[87]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[86]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[85]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[84]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[83]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[82]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[81]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[80]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[79]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[78]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[77]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[76]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[75]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[74]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[73]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[72]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[71]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[70]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[69]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[68]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[67]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[66]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[65]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[64]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[63]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[62]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[61]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[60]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[59]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[58]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[57]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[56]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[55]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[54]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[53]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[52]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[51]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[50]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[49]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[48]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[47]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[46]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[45]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[44]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[43]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[42]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[41]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[40]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[39]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[38]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[37]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[36]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[35]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[34]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[33]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[32]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[31]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[30]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[29]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[28]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[27]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[26]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[25]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[24]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[23]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[22]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[21]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[20]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[19]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[18]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[17]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[16]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[15]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[14]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[13]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[12]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[11]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[10]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[9]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[8]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[7]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[6]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[5]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[4]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[3]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[2]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[1]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[0]}] diff --git a/flow/designs/gf12/ariane/constraint_hier.sdc b/flow/designs/gf12/ariane/constraint_hier.sdc index 89c4ae0115..1a22a7607f 100644 --- a/flow/designs/gf12/ariane/constraint_hier.sdc +++ b/flow/designs/gf12/ariane/constraint_hier.sdc @@ -1,495 +1,495 @@ -create_clock [get_ports clk_i] -name core_clock -period 3000 -waveform {0 1500} -set_input_delay -clock core_clock 1500 [get_ports rst_ni] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[63]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[62]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[61]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[60]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[59]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[58]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[57]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[56]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[55]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[54]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[53]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[52]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[51]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[50]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[49]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[48]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[47]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[46]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[45]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[44]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[43]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[42]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[41]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[40]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[39]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[38]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[37]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[36]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[35]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[34]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[33]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[32]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[31]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[30]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[29]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[28]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[27]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[26]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[25]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[24]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[23]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[22]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[21]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[20]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[19]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[18]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[17]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[16]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[15]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[14]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[13]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[12]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[11]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[10]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[9]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[8]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[7]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[6]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[5]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[4]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[3]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[2]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[1]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[0]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[63]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[62]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[61]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[60]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[59]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[58]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[57]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[56]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[55]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[54]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[53]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[52]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[51]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[50]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[49]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[48]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[47]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[46]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[45]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[44]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[43]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[42]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[41]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[40]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[39]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[38]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[37]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[36]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[35]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[34]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[33]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[32]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[31]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[30]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[29]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[28]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[27]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[26]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[25]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[24]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[23]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[22]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[21]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[20]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[19]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[18]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[17]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[16]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[15]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[14]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[13]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[12]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[11]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[10]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[9]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[8]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[7]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[6]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[5]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[4]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[3]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[2]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[1]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[0]}] -set_input_delay -clock core_clock 1500 [get_ports {irq_i[1]}] -set_input_delay -clock core_clock 1500 [get_ports {irq_i[0]}] -set_input_delay -clock core_clock 1500 [get_ports ipi_i] -set_input_delay -clock core_clock 1500 [get_ports time_irq_i] -set_input_delay -clock core_clock 1500 [get_ports debug_req_i] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[81]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[80]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[79]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[78]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[77]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[76]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[75]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[74]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[73]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[72]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[71]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[70]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[69]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[68]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[67]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[66]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[65]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[64]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[63]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[62]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[61]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[60]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[59]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[58]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[57]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[56]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[55]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[54]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[53]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[52]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[51]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[50]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[49]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[48]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[47]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[46]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[45]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[44]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[43]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[42]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[41]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[40]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[39]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[38]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[37]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[36]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[35]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[34]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[33]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[32]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[31]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[30]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[29]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[28]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[27]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[26]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[25]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[24]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[23]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[22]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[21]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[20]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[19]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[18]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[17]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[16]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[15]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[14]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[13]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[12]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[11]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[10]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[9]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[8]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[7]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[6]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[5]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[4]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[3]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[2]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[1]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[0]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[277]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[276]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[275]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[274]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[273]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[272]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[271]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[270]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[269]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[268]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[267]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[266]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[265]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[264]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[263]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[262]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[261]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[260]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[259]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[258]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[257]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[256]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[255]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[254]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[253]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[252]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[251]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[250]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[249]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[248]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[247]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[246]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[245]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[244]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[243]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[242]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[241]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[240]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[239]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[238]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[237]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[236]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[235]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[234]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[233]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[232]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[231]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[230]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[229]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[228]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[227]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[226]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[225]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[224]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[223]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[222]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[221]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[220]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[219]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[218]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[217]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[216]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[215]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[214]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[213]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[212]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[211]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[210]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[209]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[208]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[207]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[206]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[205]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[204]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[203]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[202]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[201]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[200]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[199]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[198]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[197]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[196]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[195]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[194]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[193]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[192]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[191]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[190]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[189]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[188]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[187]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[186]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[185]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[184]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[183]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[182]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[181]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[180]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[179]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[178]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[177]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[176]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[175]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[174]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[173]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[172]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[171]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[170]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[169]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[168]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[167]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[166]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[165]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[164]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[163]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[162]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[161]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[160]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[159]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[158]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[157]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[156]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[155]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[154]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[153]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[152]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[151]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[150]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[149]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[148]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[147]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[146]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[145]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[144]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[143]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[142]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[141]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[140]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[139]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[138]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[137]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[136]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[135]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[134]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[133]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[132]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[131]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[130]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[129]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[128]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[127]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[126]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[125]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[124]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[123]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[122]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[121]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[120]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[119]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[118]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[117]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[116]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[115]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[114]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[113]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[112]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[111]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[110]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[109]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[108]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[107]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[106]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[105]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[104]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[103]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[102]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[101]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[100]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[99]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[98]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[97]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[96]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[95]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[94]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[93]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[92]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[91]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[90]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[89]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[88]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[87]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[86]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[85]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[84]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[83]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[82]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[81]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[80]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[79]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[78]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[77]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[76]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[75]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[74]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[73]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[72]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[71]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[70]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[69]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[68]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[67]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[66]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[65]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[64]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[63]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[62]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[61]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[60]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[59]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[58]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[57]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[56]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[55]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[54]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[53]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[52]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[51]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[50]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[49]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[48]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[47]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[46]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[45]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[44]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[43]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[42]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[41]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[40]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[39]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[38]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[37]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[36]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[35]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[34]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[33]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[32]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[31]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[30]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[29]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[28]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[27]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[26]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[25]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[24]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[23]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[22]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[21]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[20]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[19]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[18]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[17]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[16]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[15]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[14]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[13]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[12]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[11]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[10]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[9]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[8]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[7]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[6]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[5]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[4]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[3]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[2]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[1]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[0]}] +create_clock [get_ports clk_i] -name core_clock -period 3000 -waveform {0 1500} +set_input_delay -clock core_clock 1500 [get_ports rst_ni] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[63]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[62]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[61]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[60]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[59]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[58]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[57]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[56]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[55]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[54]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[53]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[52]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[51]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[50]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[49]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[48]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[47]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[46]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[45]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[44]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[43]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[42]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[41]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[40]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[39]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[38]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[37]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[36]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[35]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[34]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[33]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[32]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[31]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[30]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[29]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[28]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[27]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[26]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[25]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[24]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[23]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[22]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[21]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[20]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[19]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[18]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[17]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[16]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[15]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[14]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[13]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[12]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[11]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[10]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[9]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[8]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[7]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[6]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[5]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[4]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[3]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[2]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[1]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[0]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[63]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[62]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[61]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[60]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[59]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[58]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[57]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[56]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[55]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[54]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[53]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[52]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[51]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[50]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[49]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[48]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[47]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[46]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[45]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[44]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[43]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[42]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[41]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[40]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[39]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[38]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[37]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[36]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[35]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[34]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[33]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[32]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[31]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[30]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[29]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[28]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[27]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[26]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[25]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[24]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[23]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[22]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[21]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[20]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[19]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[18]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[17]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[16]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[15]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[14]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[13]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[12]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[11]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[10]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[9]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[8]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[7]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[6]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[5]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[4]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[3]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[2]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[1]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[0]}] +set_input_delay -clock core_clock 1500 [get_ports {irq_i[1]}] +set_input_delay -clock core_clock 1500 [get_ports {irq_i[0]}] +set_input_delay -clock core_clock 1500 [get_ports ipi_i] +set_input_delay -clock core_clock 1500 [get_ports time_irq_i] +set_input_delay -clock core_clock 1500 [get_ports debug_req_i] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[81]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[80]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[79]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[78]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[77]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[76]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[75]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[74]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[73]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[72]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[71]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[70]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[69]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[68]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[67]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[66]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[65]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[64]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[63]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[62]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[61]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[60]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[59]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[58]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[57]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[56]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[55]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[54]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[53]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[52]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[51]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[50]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[49]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[48]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[47]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[46]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[45]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[44]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[43]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[42]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[41]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[40]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[39]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[38]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[37]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[36]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[35]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[34]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[33]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[32]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[31]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[30]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[29]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[28]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[27]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[26]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[25]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[24]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[23]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[22]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[21]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[20]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[19]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[18]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[17]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[16]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[15]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[14]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[13]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[12]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[11]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[10]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[9]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[8]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[7]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[6]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[5]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[4]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[3]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[2]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[1]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[0]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[277]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[276]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[275]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[274]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[273]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[272]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[271]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[270]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[269]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[268]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[267]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[266]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[265]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[264]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[263]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[262]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[261]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[260]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[259]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[258]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[257]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[256]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[255]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[254]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[253]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[252]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[251]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[250]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[249]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[248]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[247]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[246]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[245]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[244]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[243]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[242]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[241]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[240]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[239]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[238]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[237]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[236]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[235]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[234]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[233]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[232]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[231]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[230]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[229]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[228]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[227]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[226]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[225]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[224]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[223]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[222]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[221]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[220]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[219]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[218]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[217]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[216]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[215]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[214]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[213]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[212]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[211]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[210]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[209]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[208]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[207]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[206]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[205]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[204]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[203]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[202]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[201]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[200]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[199]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[198]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[197]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[196]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[195]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[194]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[193]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[192]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[191]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[190]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[189]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[188]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[187]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[186]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[185]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[184]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[183]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[182]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[181]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[180]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[179]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[178]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[177]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[176]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[175]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[174]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[173]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[172]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[171]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[170]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[169]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[168]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[167]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[166]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[165]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[164]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[163]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[162]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[161]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[160]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[159]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[158]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[157]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[156]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[155]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[154]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[153]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[152]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[151]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[150]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[149]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[148]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[147]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[146]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[145]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[144]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[143]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[142]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[141]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[140]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[139]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[138]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[137]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[136]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[135]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[134]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[133]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[132]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[131]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[130]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[129]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[128]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[127]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[126]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[125]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[124]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[123]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[122]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[121]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[120]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[119]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[118]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[117]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[116]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[115]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[114]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[113]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[112]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[111]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[110]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[109]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[108]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[107]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[106]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[105]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[104]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[103]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[102]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[101]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[100]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[99]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[98]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[97]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[96]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[95]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[94]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[93]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[92]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[91]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[90]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[89]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[88]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[87]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[86]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[85]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[84]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[83]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[82]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[81]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[80]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[79]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[78]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[77]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[76]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[75]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[74]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[73]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[72]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[71]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[70]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[69]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[68]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[67]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[66]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[65]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[64]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[63]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[62]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[61]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[60]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[59]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[58]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[57]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[56]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[55]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[54]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[53]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[52]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[51]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[50]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[49]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[48]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[47]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[46]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[45]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[44]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[43]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[42]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[41]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[40]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[39]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[38]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[37]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[36]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[35]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[34]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[33]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[32]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[31]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[30]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[29]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[28]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[27]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[26]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[25]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[24]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[23]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[22]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[21]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[20]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[19]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[18]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[17]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[16]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[15]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[14]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[13]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[12]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[11]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[10]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[9]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[8]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[7]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[6]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[5]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[4]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[3]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[2]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[1]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[0]}] diff --git a/flow/designs/gf12/ariane/io.tcl b/flow/designs/gf12/ariane/io.tcl index 9a9b44e885..b49abf4c20 100644 --- a/flow/designs/gf12/ariane/io.tcl +++ b/flow/designs/gf12/ariane/io.tcl @@ -1 +1,2 @@ -exclude_io_pin_region -region left:0-150 -region left:450-600 -region right:* -region top:* -region bottom:* +exclude_io_pin_region -region left:0-150 -region left:450-600 -region right:* \ + -region top:* -region bottom:* diff --git a/flow/designs/gf12/ariane/rules-base.json b/flow/designs/gf12/ariane/rules-base.json index 747bfd0115..3c43ec8b2d 100644 --- a/flow/designs/gf12/ariane/rules-base.json +++ b/flow/designs/gf12/ariane/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 226890, + "value": 226083, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,11 +32,11 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 3723168, + "value": 3662425, "compare": "<=" }, "detailedroute__route__drc_errors": { - "value": 0, + "value": 1, "compare": "<=" }, "detailedroute__antenna__violating__nets": { @@ -48,11 +48,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -402.07, + "value": -212.42, "compare": ">=" }, "finish__design__instance__area": { - "value": 228909, + "value": 228519, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -27.26, + "value": -14.79, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf12/ariane133/ariane.sdc b/flow/designs/gf12/ariane133/ariane.sdc index c756ae05a3..4ddcb37965 100644 --- a/flow/designs/gf12/ariane133/ariane.sdc +++ b/flow/designs/gf12/ariane133/ariane.sdc @@ -7,5 +7,5 @@ set_units -time 1ps current_design ariane create_clock -name "core_clock" -period 1300.0 -waveform {0.0 900.0} [get_ports clk_i] -set_clock_gating_check -setup 0.0 +set_clock_gating_check -setup 0.0 set_wire_load_mode "top" diff --git a/flow/designs/gf12/ariane133/io.tcl b/flow/designs/gf12/ariane133/io.tcl index 9dbb9bc470..6ac9789e72 100644 --- a/flow/designs/gf12/ariane133/io.tcl +++ b/flow/designs/gf12/ariane133/io.tcl @@ -1 +1,2 @@ -exclude_io_pin_region -region left:0-200 -region left:500-700 -region right:* -region top:* -region bottom:* +exclude_io_pin_region -region left:0-200 -region left:500-700 -region right:* \ + -region top:* -region bottom:* diff --git a/flow/designs/gf12/bp_quad/rules-base.json b/flow/designs/gf12/bp_quad/rules-base.json index 8839af8226..fc43857901 100644 --- a/flow/designs/gf12/bp_quad/rules-base.json +++ b/flow/designs/gf12/bp_quad/rules-base.json @@ -4,7 +4,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 1729278, + "value": 1652113, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -24,7 +24,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 0, + "value": 33, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -44,11 +44,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -255.36, + "value": -114.98, "compare": ">=" }, "finish__design__instance__area": { - "value": 1765388, + "value": 1688970, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -56,11 +56,11 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 109, + "value": 105, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -16.47, + "value": -10.96, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf12/bp_single/fastroute.tcl b/flow/designs/gf12/bp_single/fastroute.tcl index 91d3b4162f..69e55f9f90 100644 --- a/flow/designs/gf12/bp_single/fastroute.tcl +++ b/flow/designs/gf12/bp_single/fastroute.tcl @@ -3,7 +3,5 @@ set_global_routing_layer_adjustment M3 0.6 set_global_routing_layer_adjustment C4-C5 0.5 set_global_routing_layer_adjustment K1-K4 0.45 -set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) -clock K1-$::env(MAX_ROUTING_LAYER) - -set_macro_extension 1 - +set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) \ + -clock K1-$::env(MAX_ROUTING_LAYER) diff --git a/flow/designs/gf12/bp_single/rules-base.json b/flow/designs/gf12/bp_single/rules-base.json index 9f270fcfe6..561e77cdbd 100644 --- a/flow/designs/gf12/bp_single/rules-base.json +++ b/flow/designs/gf12/bp_single/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 509289, + "value": 491681, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 546190, + "value": 535708, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 47495, + "value": 46583, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 47495, + "value": 46583, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,11 +32,11 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 7863419, + "value": 6200511, "compare": "<=" }, "detailedroute__route__drc_errors": { - "value": 1, + "value": 0, "compare": "<=" }, "detailedroute__antenna__violating__nets": { @@ -48,23 +48,23 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -183.6, + "value": -97.15, "compare": ">=" }, "finish__design__instance__area": { - "value": 519153, + "value": 500408, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 23747, + "value": 23292, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 230, + "value": 740, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -12.6, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf12/ca53/fastroute.tcl b/flow/designs/gf12/ca53/fastroute.tcl index 78b39516da..7b9941dfdb 100644 --- a/flow/designs/gf12/ca53/fastroute.tcl +++ b/flow/designs/gf12/ca53/fastroute.tcl @@ -3,5 +3,4 @@ set_global_routing_layer_adjustment M3 0.5 set_global_routing_layer_adjustment C4-K4 0.5 #set_global_routing_layer_adjustment H1-H2 0.5 -set_routing_layers -signal M2-$::env(MAX_ROUTING_LAYER) -clock K1-$::env(MAX_ROUTING_LAYER) -set_macro_extension 2 +set_routing_layers -signal M2-$::env(MAX_ROUTING_LAYER) -clock K1-$::env(MAX_ROUTING_LAYER) diff --git a/flow/designs/gf12/ca53/io.tcl b/flow/designs/gf12/ca53/io.tcl index 77f5111afc..89e27e2ff6 100644 --- a/flow/designs/gf12/ca53/io.tcl +++ b/flow/designs/gf12/ca53/io.tcl @@ -1 +1,2 @@ -exclude_io_pin_region -region left:0-600 -region left:1350-1400 -region right:* -region top:* -region bottom:* +exclude_io_pin_region -region left:0-600 -region left:1350-1400 -region right:* \ + -region top:* -region bottom:* diff --git a/flow/designs/gf12/coyote/constraint.sdc b/flow/designs/gf12/coyote/constraint.sdc index a27541fdcd..b110ae09d5 100644 --- a/flow/designs/gf12/coyote/constraint.sdc +++ b/flow/designs/gf12/coyote/constraint.sdc @@ -11,813 +11,1616 @@ set_clock_transition 59.0000 [get_clocks {core_clk}] set_clock_uncertainty -setup 200.0000 core_clk set_clock_uncertainty -hold 20.0000 core_clk set_clock_latency -source 0.0000 [get_clocks {core_clk}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {en_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[0]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[10]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[11]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[12]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[13]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[14]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[15]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[16]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[17]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[18]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[19]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[1]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[20]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[21]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[22]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[23]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[24]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[25]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[26]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[27]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[28]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[29]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[2]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[30]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[31]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[32]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[33]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[34]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[35]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[36]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[37]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[38]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[39]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[3]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[40]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[41]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[42]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[43]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[44]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[45]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[46]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[47]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[48]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[49]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[4]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[50]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[51]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[52]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[53]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[54]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[55]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[56]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[57]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[58]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[59]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[5]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[60]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[61]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[62]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[63]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[64]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[65]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[66]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[67]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[68]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[69]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[6]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[70]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[71]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[72]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[73]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[74]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[75]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[76]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[77]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[78]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[79]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[7]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[8]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[9]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_yumi_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {reset_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_ready_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_busy_}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_interrupt_}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[0]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[100]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[101]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[102]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[103]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[104]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[105]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[106]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[107]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[108]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[109]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[10]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[110]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[111]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[112]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[113]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[114]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[115]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[116]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[117]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[118]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[119]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[11]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[120]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[121]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[122]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[12]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[13]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[14]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[15]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[16]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[17]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[18]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[19]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[1]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[20]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[21]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[22]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[23]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[24]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[25]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[26]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[27]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[28]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[29]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[2]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[30]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[31]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[32]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[33]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[34]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[35]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[36]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[37]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[38]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[39]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[3]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[40]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[41]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[42]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[43]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[44]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[45]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[46]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[47]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[48]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[49]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[4]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[50]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[51]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[52]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[53]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[54]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[55]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[56]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[57]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[58]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[59]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[5]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[60]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[61]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[62]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[63]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[64]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[65]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[66]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[67]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[68]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[69]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[6]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[70]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[71]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[72]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[73]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[74]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[75]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[76]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[77]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[78]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[79]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[7]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[80]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[81]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[82]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[83]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[84]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[85]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[86]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[87]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[88]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[89]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[8]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[90]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[91]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[92]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[93]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[94]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[95]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[96]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[97]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[98]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[99]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[9]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_v_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[0]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[10]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[11]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[12]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[13]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[14]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[15]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[16]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[17]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[18]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[19]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[1]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[20]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[21]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[22]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[23]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[24]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[25]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[26]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[27]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[28]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[29]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[2]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[30]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[31]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[32]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[33]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[34]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[35]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[36]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[37]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[38]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[39]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[3]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[40]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[41]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[42]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[43]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[44]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[45]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[46]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[47]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[48]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[49]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[4]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[50]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[51]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[52]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[53]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[54]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[55]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[56]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[57]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[58]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[59]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[5]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[60]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[61]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[62]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[63]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[64]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[65]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[66]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[67]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[68]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[6]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[7]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[8]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[9]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_v_i}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[0]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[10]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[11]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[12]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[13]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[14]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[15]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[16]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[17]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[18]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[19]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[1]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[20]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[21]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[22]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[23]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[24]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[25]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[26]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[27]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[28]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[29]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[2]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[30]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[31]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[32]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[33]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[34]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[35]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[36]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[37]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[38]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[39]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[3]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[40]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[41]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[42]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[43]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[44]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[45]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[46]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[47]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[48]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[49]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[4]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[50]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[51]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[52]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[53]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[54]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[55]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[56]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[57]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[58]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[59]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[5]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[60]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[61]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[62]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[63]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[64]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[65]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[66]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[67]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[68]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[69]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[6]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[70]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[71]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[72]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[73]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[74]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[75]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[76]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[77]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[78]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[79]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[7]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[8]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[9]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_ready_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[0]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[100]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[101]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[102]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[103]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[104]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[105]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[106]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[107]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[108]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[109]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[10]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[110]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[111]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[112]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[113]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[114]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[115]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[116]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[117]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[118]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[119]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[11]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[120]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[121]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[122]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[123]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[124]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[125]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[126]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[127]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[128]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[129]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[12]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[130]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[131]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[132]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[133]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[134]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[135]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[136]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[137]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[138]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[139]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[13]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[140]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[141]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[142]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[143]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[144]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[145]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[146]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[147]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[148]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[149]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[14]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[150]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[151]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[152]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[153]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[154]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[155]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[156]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[157]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[158]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[159]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[15]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[16]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[17]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[18]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[19]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[1]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[20]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[21]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[22]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[23]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[24]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[25]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[26]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[27]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[28]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[29]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[2]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[30]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[31]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[32]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[33]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[34]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[35]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[36]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[37]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[38]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[39]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[3]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[40]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[41]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[42]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[43]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[44]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[45]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[46]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[47]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[48]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[49]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[4]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[50]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[51]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[52]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[53]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[54]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[55]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[56]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[57]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[58]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[59]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[5]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[60]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[61]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[62]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[63]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[64]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[65]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[66]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[67]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[68]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[69]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[6]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[70]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[71]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[72]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[73]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[74]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[75]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[76]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[77]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[78]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[79]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[7]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[80]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[81]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[82]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[83]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[84]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[85]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[86]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[87]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[88]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[89]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[8]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[90]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[91]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[92]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[93]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[94]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[95]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[96]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[97]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[98]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[99]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[9]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_v_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_exception_}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_host_id_}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_s_}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_ready_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[0]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[100]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[101]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[102]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[103]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[104]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[105]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[106]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[107]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[108]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[109]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[10]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[110]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[111]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[112]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[113]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[114]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[115]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[116]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[117]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[118]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[119]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[11]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[120]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[121]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[122]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[123]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[124]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[125]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[126]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[127]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[128]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[129]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[12]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[130]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[131]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[132]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[133]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[134]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[135]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[136]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[137]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[138]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[139]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[13]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[140]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[141]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[142]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[143]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[144]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[145]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[146]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[147]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[148]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[149]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[14]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[150]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[151]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[152]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[153]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[154]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[155]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[156]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[157]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[158]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[159]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[15]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[160]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[161]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[162]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[163]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[164]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[165]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[166]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[167]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[168]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[169]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[16]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[170]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[171]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[172]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[173]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[174]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[175]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[176]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[177]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[178]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[179]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[17]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[180]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[181]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[182]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[183]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[184]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[185]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[186]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[187]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[188]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[189]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[18]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[190]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[191]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[192]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[193]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[194]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[195]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[196]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[197]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[198]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[199]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[19]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[1]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[200]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[201]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[202]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[203]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[204]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[205]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[206]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[207]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[208]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[209]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[20]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[210]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[211]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[212]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[213]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[214]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[215]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[216]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[217]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[218]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[219]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[21]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[220]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[221]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[222]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[223]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[224]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[225]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[226]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[227]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[228]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[229]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[22]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[230]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[231]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[232]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[233]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[234]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[235]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[236]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[237]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[238]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[239]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[23]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[240]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[241]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[242]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[243]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[244]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[245]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[246]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[247]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[248]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[249]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[24]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[250]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[251]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[252]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[25]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[26]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[27]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[28]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[29]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[2]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[30]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[31]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[32]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[33]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[34]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[35]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[36]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[37]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[38]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[39]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[3]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[40]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[41]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[42]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[43]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[44]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[45]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[46]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[47]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[48]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[49]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[4]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[50]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[51]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[52]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[53]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[54]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[55]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[56]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[57]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[58]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[59]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[5]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[60]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[61]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[62]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[63]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[64]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[65]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[66]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[67]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[68]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[69]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[6]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[70]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[71]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[72]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[73]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[74]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[75]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[76]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[77]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[78]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[79]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[7]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[80]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[81]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[82]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[83]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[84]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[85]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[86]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[87]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[88]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[89]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[8]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[90]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[91]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[92]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[93]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[94]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[95]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[96]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[97]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[98]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[99]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[9]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_v_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_ready_o}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem1.macro_mem0}] -set_false_path\ - -to [list [get_ports {rocc_ctrl_o_exception_}]\ - [get_ports {rocc_ctrl_o_host_id_}]\ - [get_ports {rocc_ctrl_o_s_}]] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {en_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[0]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[10]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[11]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[12]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[13]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[14]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[15]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[16]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[17]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[18]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[19]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[1]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[20]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[21]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[22]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[23]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[24]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[25]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[26]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[27]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[28]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[29]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[2]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[30]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[31]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[32]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[33]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[34]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[35]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[36]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[37]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[38]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[39]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[3]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[40]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[41]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[42]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[43]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[44]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[45]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[46]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[47]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[48]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[49]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[4]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[50]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[51]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[52]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[53]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[54]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[55]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[56]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[57]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[58]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[59]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[5]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[60]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[61]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[62]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[63]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[64]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[65]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[66]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[67]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[68]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[69]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[6]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[70]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[71]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[72]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[73]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[74]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[75]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[76]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[77]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[78]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[79]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[7]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[8]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[9]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_yumi_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {reset_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_ready_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_busy_}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_interrupt_}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[0]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[100]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[101]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[102]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[103]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[104]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[105]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[106]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[107]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[108]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[109]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[10]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[110]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[111]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[112]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[113]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[114]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[115]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[116]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[117]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[118]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[119]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[11]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[120]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[121]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[122]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[12]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[13]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[14]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[15]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[16]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[17]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[18]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[19]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[1]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[20]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[21]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[22]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[23]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[24]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[25]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[26]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[27]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[28]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[29]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[2]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[30]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[31]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[32]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[33]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[34]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[35]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[36]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[37]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[38]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[39]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[3]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[40]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[41]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[42]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[43]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[44]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[45]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[46]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[47]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[48]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[49]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[4]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[50]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[51]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[52]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[53]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[54]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[55]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[56]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[57]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[58]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[59]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[5]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[60]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[61]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[62]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[63]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[64]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[65]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[66]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[67]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[68]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[69]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[6]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[70]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[71]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[72]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[73]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[74]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[75]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[76]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[77]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[78]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[79]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[7]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[80]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[81]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[82]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[83]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[84]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[85]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[86]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[87]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[88]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[89]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[8]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[90]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[91]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[92]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[93]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[94]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[95]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[96]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[97]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[98]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[99]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[9]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_v_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[0]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[10]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[11]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[12]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[13]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[14]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[15]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[16]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[17]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[18]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[19]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[1]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[20]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[21]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[22]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[23]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[24]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[25]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[26]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[27]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[28]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[29]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[2]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[30]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[31]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[32]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[33]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[34]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[35]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[36]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[37]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[38]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[39]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[3]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[40]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[41]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[42]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[43]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[44]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[45]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[46]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[47]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[48]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[49]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[4]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[50]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[51]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[52]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[53]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[54]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[55]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[56]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[57]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[58]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[59]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[5]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[60]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[61]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[62]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[63]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[64]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[65]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[66]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[67]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[68]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[6]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[7]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[8]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[9]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_v_i}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[0]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[10]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[11]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[12]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[13]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[14]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[15]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[16]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[17]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[18]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[19]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[1]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[20]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[21]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[22]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[23]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[24]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[25]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[26]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[27]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[28]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[29]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[2]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[30]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[31]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[32]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[33]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[34]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[35]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[36]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[37]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[38]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[39]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[3]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[40]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[41]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[42]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[43]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[44]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[45]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[46]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[47]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[48]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[49]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[4]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[50]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[51]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[52]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[53]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[54]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[55]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[56]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[57]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[58]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[59]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[5]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[60]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[61]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[62]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[63]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[64]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[65]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[66]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[67]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[68]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[69]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[6]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[70]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[71]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[72]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[73]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[74]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[75]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[76]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[77]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[78]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[79]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[7]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[8]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[9]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_ready_o}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_o}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[0]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[100]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[101]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[102]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[103]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[104]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[105]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[106]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[107]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[108]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[109]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[10]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[110]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[111]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[112]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[113]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[114]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[115]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[116]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[117]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[118]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[119]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[11]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[120]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[121]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[122]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[123]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[124]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[125]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[126]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[127]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[128]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[129]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[12]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[130]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[131]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[132]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[133]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[134]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[135]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[136]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[137]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[138]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[139]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[13]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[140]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[141]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[142]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[143]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[144]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[145]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[146]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[147]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[148]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[149]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[14]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[150]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[151]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[152]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[153]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[154]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[155]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[156]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[157]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[158]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[159]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[15]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[16]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[17]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[18]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[19]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[1]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[20]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[21]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[22]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[23]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[24]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[25]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[26]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[27]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[28]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[29]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[2]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[30]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[31]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[32]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[33]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[34]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[35]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[36]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[37]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[38]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[39]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[3]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[40]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[41]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[42]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[43]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[44]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[45]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[46]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[47]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[48]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[49]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[4]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[50]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[51]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[52]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[53]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[54]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[55]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[56]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[57]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[58]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[59]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[5]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[60]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[61]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[62]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[63]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[64]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[65]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[66]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[67]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[68]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[69]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[6]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[70]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[71]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[72]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[73]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[74]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[75]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[76]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[77]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[78]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[79]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[7]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[80]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[81]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[82]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[83]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[84]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[85]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[86]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[87]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[88]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[89]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[8]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[90]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[91]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[92]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[93]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[94]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[95]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[96]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[97]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[98]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[99]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[9]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_v_o}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_exception_}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_host_id_}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_s_}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_ready_o}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[0]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[100]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[101]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[102]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[103]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[104]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[105]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[106]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[107]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[108]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[109]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[10]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[110]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[111]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[112]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[113]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[114]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[115]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[116]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[117]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[118]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[119]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[11]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[120]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[121]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[122]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[123]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[124]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[125]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[126]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[127]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[128]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[129]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[12]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[130]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[131]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[132]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[133]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[134]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[135]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[136]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[137]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[138]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[139]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[13]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[140]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[141]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[142]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[143]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[144]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[145]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[146]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[147]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[148]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[149]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[14]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[150]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[151]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[152]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[153]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[154]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[155]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[156]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[157]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[158]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[159]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[15]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[160]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[161]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[162]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[163]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[164]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[165]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[166]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[167]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[168]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[169]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[16]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[170]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[171]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[172]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[173]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[174]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[175]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[176]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[177]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[178]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[179]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[17]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[180]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[181]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[182]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[183]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[184]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[185]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[186]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[187]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[188]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[189]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[18]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[190]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[191]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[192]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[193]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[194]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[195]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[196]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[197]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[198]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[199]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[19]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[1]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[200]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[201]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[202]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[203]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[204]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[205]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[206]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[207]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[208]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[209]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[20]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[210]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[211]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[212]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[213]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[214]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[215]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[216]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[217]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[218]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[219]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[21]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[220]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[221]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[222]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[223]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[224]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[225]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[226]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[227]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[228]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[229]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[22]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[230]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[231]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[232]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[233]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[234]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[235]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[236]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[237]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[238]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[239]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[23]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[240]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[241]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[242]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[243]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[244]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[245]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[246]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[247]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[248]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[249]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[24]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[250]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[251]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[252]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[25]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[26]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[27]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[28]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[29]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[2]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[30]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[31]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[32]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[33]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[34]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[35]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[36]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[37]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[38]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[39]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[3]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[40]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[41]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[42]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[43]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[44]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[45]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[46]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[47]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[48]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[49]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[4]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[50]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[51]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[52]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[53]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[54]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[55]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[56]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[57]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[58]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[59]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[5]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[60]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[61]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[62]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[63]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[64]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[65]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[66]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[67]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[68]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[69]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[6]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[70]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[71]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[72]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[73]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[74]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[75]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[76]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[77]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[78]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[79]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[7]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[80]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[81]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[82]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[83]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[84]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[85]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[86]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[87]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[88]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[89]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[8]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[90]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[91]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[92]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[93]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[94]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[95]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[96]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[97]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[98]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[99]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[9]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_v_o}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_ready_o}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem1.macro_mem0}] +set_false_path \ + -to [list [get_ports {rocc_ctrl_o_exception_}] \ + [get_ports {rocc_ctrl_o_host_id_}] \ + [get_ports {rocc_ctrl_o_s_}]] ############################################################################### # Environment ############################################################################### diff --git a/flow/designs/gf12/coyote/constraint_hier.sdc b/flow/designs/gf12/coyote/constraint_hier.sdc index 19f548615f..3ca86c77ea 100644 --- a/flow/designs/gf12/coyote/constraint_hier.sdc +++ b/flow/designs/gf12/coyote/constraint_hier.sdc @@ -11,813 +11,1616 @@ set_clock_transition 59.0000 [get_clocks {core_clk}] set_clock_uncertainty -setup 200.0000 core_clk set_clock_uncertainty -hold 20.0000 core_clk set_clock_latency -source 0.0000 [get_clocks {core_clk}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {en_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[0]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[10]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[11]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[12]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[13]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[14]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[15]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[16]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[17]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[18]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[19]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[1]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[20]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[21]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[22]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[23]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[24]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[25]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[26]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[27]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[28]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[29]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[2]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[30]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[31]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[32]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[33]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[34]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[35]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[36]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[37]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[38]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[39]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[3]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[40]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[41]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[42]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[43]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[44]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[45]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[46]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[47]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[48]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[49]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[4]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[50]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[51]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[52]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[53]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[54]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[55]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[56]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[57]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[58]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[59]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[5]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[60]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[61]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[62]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[63]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[64]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[65]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[66]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[67]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[68]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[69]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[6]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[70]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[71]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[72]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[73]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[74]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[75]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[76]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[77]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[78]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[79]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[7]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[8]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[9]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_yumi_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {reset_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_ready_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_busy_}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_interrupt_}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[0]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[100]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[101]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[102]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[103]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[104]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[105]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[106]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[107]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[108]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[109]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[10]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[110]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[111]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[112]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[113]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[114]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[115]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[116]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[117]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[118]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[119]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[11]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[120]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[121]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[122]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[12]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[13]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[14]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[15]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[16]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[17]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[18]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[19]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[1]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[20]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[21]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[22]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[23]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[24]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[25]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[26]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[27]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[28]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[29]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[2]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[30]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[31]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[32]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[33]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[34]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[35]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[36]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[37]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[38]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[39]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[3]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[40]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[41]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[42]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[43]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[44]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[45]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[46]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[47]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[48]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[49]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[4]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[50]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[51]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[52]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[53]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[54]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[55]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[56]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[57]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[58]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[59]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[5]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[60]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[61]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[62]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[63]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[64]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[65]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[66]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[67]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[68]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[69]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[6]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[70]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[71]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[72]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[73]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[74]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[75]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[76]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[77]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[78]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[79]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[7]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[80]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[81]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[82]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[83]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[84]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[85]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[86]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[87]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[88]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[89]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[8]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[90]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[91]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[92]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[93]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[94]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[95]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[96]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[97]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[98]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[99]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[9]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_v_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[0]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[10]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[11]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[12]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[13]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[14]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[15]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[16]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[17]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[18]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[19]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[1]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[20]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[21]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[22]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[23]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[24]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[25]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[26]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[27]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[28]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[29]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[2]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[30]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[31]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[32]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[33]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[34]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[35]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[36]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[37]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[38]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[39]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[3]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[40]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[41]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[42]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[43]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[44]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[45]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[46]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[47]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[48]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[49]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[4]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[50]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[51]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[52]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[53]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[54]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[55]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[56]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[57]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[58]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[59]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[5]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[60]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[61]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[62]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[63]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[64]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[65]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[66]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[67]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[68]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[6]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[7]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[8]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[9]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_v_i}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[0]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[10]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[11]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[12]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[13]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[14]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[15]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[16]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[17]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[18]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[19]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[1]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[20]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[21]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[22]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[23]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[24]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[25]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[26]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[27]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[28]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[29]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[2]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[30]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[31]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[32]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[33]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[34]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[35]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[36]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[37]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[38]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[39]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[3]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[40]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[41]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[42]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[43]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[44]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[45]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[46]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[47]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[48]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[49]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[4]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[50]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[51]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[52]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[53]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[54]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[55]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[56]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[57]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[58]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[59]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[5]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[60]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[61]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[62]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[63]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[64]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[65]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[66]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[67]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[68]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[69]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[6]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[70]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[71]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[72]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[73]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[74]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[75]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[76]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[77]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[78]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[79]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[7]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[8]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[9]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_ready_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[0]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[100]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[101]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[102]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[103]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[104]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[105]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[106]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[107]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[108]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[109]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[10]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[110]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[111]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[112]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[113]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[114]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[115]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[116]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[117]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[118]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[119]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[11]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[120]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[121]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[122]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[123]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[124]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[125]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[126]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[127]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[128]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[129]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[12]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[130]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[131]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[132]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[133]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[134]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[135]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[136]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[137]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[138]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[139]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[13]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[140]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[141]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[142]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[143]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[144]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[145]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[146]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[147]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[148]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[149]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[14]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[150]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[151]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[152]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[153]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[154]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[155]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[156]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[157]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[158]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[159]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[15]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[16]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[17]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[18]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[19]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[1]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[20]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[21]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[22]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[23]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[24]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[25]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[26]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[27]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[28]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[29]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[2]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[30]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[31]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[32]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[33]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[34]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[35]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[36]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[37]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[38]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[39]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[3]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[40]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[41]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[42]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[43]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[44]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[45]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[46]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[47]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[48]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[49]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[4]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[50]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[51]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[52]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[53]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[54]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[55]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[56]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[57]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[58]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[59]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[5]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[60]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[61]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[62]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[63]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[64]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[65]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[66]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[67]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[68]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[69]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[6]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[70]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[71]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[72]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[73]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[74]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[75]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[76]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[77]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[78]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[79]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[7]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[80]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[81]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[82]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[83]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[84]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[85]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[86]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[87]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[88]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[89]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[8]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[90]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[91]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[92]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[93]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[94]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[95]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[96]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[97]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[98]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[99]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[9]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_v_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_exception_}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_host_id_}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_s_}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_ready_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[0]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[100]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[101]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[102]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[103]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[104]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[105]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[106]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[107]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[108]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[109]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[10]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[110]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[111]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[112]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[113]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[114]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[115]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[116]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[117]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[118]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[119]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[11]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[120]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[121]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[122]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[123]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[124]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[125]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[126]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[127]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[128]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[129]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[12]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[130]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[131]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[132]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[133]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[134]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[135]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[136]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[137]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[138]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[139]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[13]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[140]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[141]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[142]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[143]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[144]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[145]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[146]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[147]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[148]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[149]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[14]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[150]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[151]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[152]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[153]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[154]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[155]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[156]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[157]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[158]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[159]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[15]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[160]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[161]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[162]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[163]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[164]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[165]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[166]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[167]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[168]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[169]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[16]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[170]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[171]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[172]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[173]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[174]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[175]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[176]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[177]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[178]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[179]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[17]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[180]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[181]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[182]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[183]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[184]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[185]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[186]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[187]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[188]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[189]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[18]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[190]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[191]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[192]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[193]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[194]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[195]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[196]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[197]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[198]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[199]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[19]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[1]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[200]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[201]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[202]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[203]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[204]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[205]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[206]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[207]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[208]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[209]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[20]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[210]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[211]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[212]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[213]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[214]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[215]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[216]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[217]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[218]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[219]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[21]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[220]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[221]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[222]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[223]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[224]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[225]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[226]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[227]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[228]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[229]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[22]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[230]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[231]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[232]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[233]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[234]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[235]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[236]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[237]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[238]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[239]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[23]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[240]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[241]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[242]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[243]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[244]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[245]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[246]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[247]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[248]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[249]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[24]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[250]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[251]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[252]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[25]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[26]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[27]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[28]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[29]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[2]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[30]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[31]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[32]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[33]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[34]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[35]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[36]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[37]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[38]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[39]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[3]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[40]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[41]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[42]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[43]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[44]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[45]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[46]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[47]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[48]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[49]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[4]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[50]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[51]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[52]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[53]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[54]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[55]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[56]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[57]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[58]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[59]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[5]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[60]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[61]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[62]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[63]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[64]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[65]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[66]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[67]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[68]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[69]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[6]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[70]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[71]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[72]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[73]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[74]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[75]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[76]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[77]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[78]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[79]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[7]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[80]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[81]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[82]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[83]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[84]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[85]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[86]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[87]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[88]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[89]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[8]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[90]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[91]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[92]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[93]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[94]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[95]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[96]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[97]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[98]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[99]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[9]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_v_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_ready_o}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}] -set_false_path\ - -to [list [get_ports {rocc_ctrl_o_exception_}]\ - [get_ports {rocc_ctrl_o_host_id_}]\ - [get_ports {rocc_ctrl_o_s_}]] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {en_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[0]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[10]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[11]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[12]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[13]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[14]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[15]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[16]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[17]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[18]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[19]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[1]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[20]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[21]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[22]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[23]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[24]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[25]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[26]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[27]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[28]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[29]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[2]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[30]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[31]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[32]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[33]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[34]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[35]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[36]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[37]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[38]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[39]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[3]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[40]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[41]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[42]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[43]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[44]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[45]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[46]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[47]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[48]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[49]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[4]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[50]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[51]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[52]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[53]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[54]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[55]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[56]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[57]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[58]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[59]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[5]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[60]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[61]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[62]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[63]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[64]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[65]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[66]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[67]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[68]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[69]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[6]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[70]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[71]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[72]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[73]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[74]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[75]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[76]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[77]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[78]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[79]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[7]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[8]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[9]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_yumi_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {reset_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_ready_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_busy_}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_interrupt_}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[0]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[100]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[101]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[102]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[103]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[104]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[105]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[106]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[107]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[108]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[109]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[10]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[110]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[111]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[112]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[113]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[114]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[115]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[116]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[117]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[118]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[119]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[11]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[120]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[121]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[122]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[12]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[13]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[14]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[15]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[16]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[17]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[18]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[19]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[1]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[20]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[21]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[22]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[23]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[24]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[25]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[26]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[27]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[28]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[29]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[2]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[30]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[31]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[32]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[33]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[34]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[35]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[36]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[37]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[38]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[39]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[3]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[40]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[41]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[42]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[43]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[44]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[45]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[46]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[47]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[48]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[49]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[4]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[50]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[51]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[52]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[53]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[54]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[55]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[56]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[57]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[58]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[59]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[5]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[60]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[61]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[62]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[63]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[64]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[65]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[66]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[67]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[68]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[69]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[6]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[70]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[71]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[72]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[73]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[74]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[75]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[76]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[77]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[78]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[79]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[7]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[80]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[81]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[82]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[83]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[84]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[85]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[86]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[87]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[88]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[89]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[8]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[90]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[91]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[92]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[93]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[94]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[95]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[96]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[97]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[98]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[99]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[9]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_v_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[0]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[10]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[11]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[12]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[13]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[14]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[15]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[16]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[17]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[18]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[19]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[1]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[20]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[21]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[22]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[23]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[24]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[25]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[26]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[27]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[28]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[29]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[2]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[30]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[31]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[32]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[33]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[34]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[35]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[36]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[37]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[38]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[39]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[3]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[40]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[41]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[42]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[43]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[44]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[45]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[46]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[47]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[48]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[49]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[4]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[50]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[51]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[52]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[53]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[54]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[55]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[56]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[57]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[58]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[59]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[5]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[60]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[61]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[62]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[63]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[64]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[65]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[66]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[67]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[68]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[6]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[7]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[8]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[9]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_v_i}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[0]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[10]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[11]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[12]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[13]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[14]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[15]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[16]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[17]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[18]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[19]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[1]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[20]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[21]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[22]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[23]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[24]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[25]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[26]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[27]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[28]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[29]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[2]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[30]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[31]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[32]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[33]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[34]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[35]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[36]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[37]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[38]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[39]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[3]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[40]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[41]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[42]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[43]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[44]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[45]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[46]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[47]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[48]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[49]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[4]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[50]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[51]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[52]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[53]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[54]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[55]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[56]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[57]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[58]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[59]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[5]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[60]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[61]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[62]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[63]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[64]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[65]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[66]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[67]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[68]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[69]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[6]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[70]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[71]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[72]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[73]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[74]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[75]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[76]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[77]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[78]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[79]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[7]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[8]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[9]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_ready_o}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_o}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[0]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[100]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[101]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[102]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[103]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[104]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[105]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[106]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[107]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[108]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[109]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[10]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[110]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[111]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[112]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[113]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[114]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[115]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[116]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[117]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[118]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[119]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[11]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[120]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[121]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[122]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[123]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[124]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[125]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[126]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[127]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[128]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[129]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[12]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[130]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[131]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[132]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[133]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[134]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[135]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[136]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[137]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[138]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[139]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[13]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[140]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[141]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[142]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[143]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[144]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[145]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[146]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[147]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[148]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[149]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[14]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[150]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[151]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[152]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[153]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[154]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[155]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[156]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[157]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[158]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[159]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[15]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[16]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[17]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[18]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[19]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[1]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[20]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[21]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[22]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[23]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[24]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[25]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[26]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[27]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[28]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[29]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[2]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[30]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[31]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[32]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[33]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[34]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[35]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[36]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[37]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[38]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[39]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[3]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[40]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[41]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[42]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[43]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[44]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[45]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[46]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[47]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[48]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[49]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[4]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[50]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[51]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[52]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[53]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[54]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[55]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[56]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[57]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[58]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[59]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[5]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[60]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[61]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[62]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[63]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[64]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[65]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[66]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[67]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[68]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[69]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[6]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[70]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[71]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[72]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[73]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[74]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[75]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[76]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[77]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[78]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[79]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[7]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[80]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[81]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[82]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[83]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[84]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[85]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[86]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[87]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[88]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[89]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[8]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[90]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[91]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[92]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[93]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[94]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[95]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[96]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[97]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[98]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[99]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[9]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_v_o}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_exception_}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_host_id_}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_s_}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_ready_o}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[0]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[100]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[101]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[102]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[103]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[104]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[105]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[106]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[107]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[108]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[109]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[10]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[110]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[111]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[112]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[113]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[114]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[115]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[116]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[117]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[118]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[119]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[11]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[120]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[121]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[122]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[123]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[124]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[125]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[126]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[127]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[128]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[129]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[12]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[130]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[131]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[132]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[133]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[134]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[135]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[136]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[137]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[138]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[139]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[13]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[140]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[141]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[142]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[143]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[144]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[145]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[146]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[147]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[148]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[149]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[14]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[150]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[151]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[152]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[153]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[154]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[155]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[156]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[157]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[158]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[159]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[15]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[160]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[161]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[162]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[163]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[164]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[165]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[166]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[167]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[168]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[169]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[16]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[170]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[171]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[172]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[173]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[174]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[175]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[176]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[177]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[178]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[179]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[17]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[180]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[181]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[182]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[183]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[184]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[185]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[186]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[187]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[188]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[189]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[18]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[190]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[191]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[192]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[193]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[194]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[195]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[196]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[197]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[198]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[199]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[19]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[1]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[200]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[201]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[202]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[203]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[204]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[205]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[206]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[207]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[208]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[209]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[20]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[210]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[211]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[212]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[213]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[214]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[215]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[216]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[217]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[218]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[219]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[21]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[220]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[221]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[222]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[223]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[224]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[225]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[226]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[227]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[228]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[229]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[22]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[230]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[231]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[232]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[233]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[234]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[235]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[236]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[237]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[238]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[239]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[23]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[240]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[241]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[242]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[243]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[244]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[245]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[246]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[247]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[248]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[249]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[24]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[250]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[251]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[252]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[25]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[26]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[27]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[28]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[29]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[2]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[30]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[31]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[32]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[33]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[34]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[35]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[36]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[37]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[38]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[39]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[3]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[40]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[41]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[42]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[43]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[44]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[45]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[46]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[47]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[48]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[49]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[4]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[50]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[51]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[52]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[53]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[54]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[55]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[56]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[57]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[58]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[59]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[5]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[60]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[61]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[62]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[63]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[64]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[65]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[66]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[67]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[68]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[69]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[6]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[70]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[71]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[72]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[73]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[74]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[75]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[76]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[77]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[78]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[79]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[7]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[80]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[81]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[82]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[83]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[84]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[85]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[86]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[87]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[88]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[89]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[8]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[90]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[91]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[92]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[93]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[94]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[95]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[96]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[97]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[98]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[99]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[9]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_v_o}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_ready_o}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}] +set_false_path \ + -to [list [get_ports {rocc_ctrl_o_exception_}] \ + [get_ports {rocc_ctrl_o_host_id_}] \ + [get_ports {rocc_ctrl_o_s_}]] ############################################################################### # Environment ############################################################################### diff --git a/flow/designs/gf12/coyote/io.tcl b/flow/designs/gf12/coyote/io.tcl index 39d22dc7cf..0154d2704c 100644 --- a/flow/designs/gf12/coyote/io.tcl +++ b/flow/designs/gf12/coyote/io.tcl @@ -1 +1,2 @@ -exclude_io_pin_region -region left:* -region right:* -region top:* -region bottom:0-20 -region bottom:450-750 \ No newline at end of file +exclude_io_pin_region -region left:* -region right:* -region top:* \ + -region bottom:0-20 -region bottom:450-750 diff --git a/flow/designs/gf12/coyote/rules-base.json b/flow/designs/gf12/coyote/rules-base.json index 6c4fc6394a..8359e8a556 100644 --- a/flow/designs/gf12/coyote/rules-base.json +++ b/flow/designs/gf12/coyote/rules-base.json @@ -32,11 +32,11 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 5770855, + "value": 5678019, "compare": "<=" }, "detailedroute__route__drc_errors": { - "value": 0, + "value": 1, "compare": "<=" }, "detailedroute__antenna__violating__nets": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 100, + "value": 266, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/gf12/gcd/constraint.sdc b/flow/designs/gf12/gcd/constraint.sdc index e1df1eb91a..d7ee23ad0a 100644 --- a/flow/designs/gf12/gcd/constraint.sdc +++ b/flow/designs/gf12/gcd/constraint.sdc @@ -1,17 +1,17 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 280 +set clk_period 280 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] # set_timing_derate -early 0.9500 diff --git a/flow/designs/gf12/ibex/config.mk b/flow/designs/gf12/ibex/config.mk index c94bfc69e1..78f928de7f 100644 --- a/flow/designs/gf12/ibex/config.mk +++ b/flow/designs/gf12/ibex/config.mk @@ -2,46 +2,13 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = gf12 +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \ + $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v - +export VERILOG_INCLUDE_DIRS = \ + $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/ +export SYNTH_HDL_FRONTEND = slang export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc diff --git a/flow/designs/gf12/ibex/constraint.sdc b/flow/designs/gf12/ibex/constraint.sdc index 1684b897b5..85d691d76e 100644 --- a/flow/designs/gf12/ibex/constraint.sdc +++ b/flow/designs/gf12/ibex/constraint.sdc @@ -1,17 +1,17 @@ current_design ibex_core -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i -set clk_period 1020 +set clk_period 1020 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] set_timing_derate -early 0.9500 diff --git a/flow/designs/gf12/jpeg/constraint.sdc b/flow/designs/gf12/jpeg/constraint.sdc index 86761946c6..9e32a57bf1 100644 --- a/flow/designs/gf12/jpeg/constraint.sdc +++ b/flow/designs/gf12/jpeg/constraint.sdc @@ -1,17 +1,17 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 770 +set clk_period 770 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] set_timing_derate -early 0.9500 diff --git a/flow/designs/gf12/swerv_wrapper/config.mk b/flow/designs/gf12/swerv_wrapper/config.mk index 0acf902085..2ed5601613 100644 --- a/flow/designs/gf12/swerv_wrapper/config.mk +++ b/flow/designs/gf12/swerv_wrapper/config.mk @@ -4,12 +4,6 @@ export PLATFORM = gf12 export SYNTH_MINIMUM_KEEP_SIZE ?= 10000 export SYNTH_HIERARCHICAL = 1 -# RTL_MP Settings -export RTLMP_MAX_INST = 25000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 12 -export RTLMP_MIN_MACRO = 4 - export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \ $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc diff --git a/flow/designs/gf12/swerv_wrapper/constraint.sdc b/flow/designs/gf12/swerv_wrapper/constraint.sdc index a7296dd71c..186b5121f8 100644 --- a/flow/designs/gf12/swerv_wrapper/constraint.sdc +++ b/flow/designs/gf12/swerv_wrapper/constraint.sdc @@ -8,11 +8,11 @@ current_design swerv_wrapper ############################################################################### create_clock -name core_clock -period 1500.0 -waveform {0.0000 750.0} [get_ports {clk}] set_clock_uncertainty -setup 70.0000 core_clock -set_clock_uncertainty -hold 70.0000 core_clock +set_clock_uncertainty -hold 70.0000 core_clock #set_propagated_clock [get_clocks {core_clock}] create_clock -name jtag_clock -period 1500 -waveform {0.0000 750.0} [get_ports {jtag_tck}] set_clock_uncertainty -setup 70.0000 jtag_clock -set_clock_uncertainty -hold 70.0000 jtag_clock +set_clock_uncertainty -hold 70.0000 jtag_clock #set_propagated_clock [get_clocks {jtag_clock}] # There is sync logic between jtag and core_clock @@ -25,7 +25,7 @@ set_clock_uncertainty -hold 70.0000 jtag_clock # Design Rules ############################################################################### set clock_ports "jtag_tck clk" -set jtag_ports "jtag_id* jtag_tdi jtag_tms jtag_trst_n" +set jtag_ports "jtag_id* jtag_tdi jtag_tms jtag_trst_n" #set input_not_jtag_ports [remove_from_collection [all_inputs] "$jtag_ports $clock_ports"] set input_not_jtag_ports [list] foreach input [all_inputs] { @@ -40,9 +40,9 @@ foreach input [all_inputs] { lappend input_not_jtag_ports $input } } -set_input_delay 375 -clock jtag_clock $jtag_ports +set_input_delay 375 -clock jtag_clock $jtag_ports set_output_delay 375 -clock jtag_clock [get_ports "jtag_tdo"] -set_input_delay 750 -clock core_clock $input_not_jtag_ports +set_input_delay 750 -clock core_clock $input_not_jtag_ports set ports_list [list] foreach output [all_outputs] { set addFlag 1 @@ -63,5 +63,3 @@ set_driving_cell -lib_cell BUFH_X2N_A9PP84TR_C14 [all_inputs] foreach input [all_inputs] { set_load 0 $input } - - diff --git a/flow/designs/gf12/swerv_wrapper/io.tcl b/flow/designs/gf12/swerv_wrapper/io.tcl index fc3731672b..0545c0cca8 100644 --- a/flow/designs/gf12/swerv_wrapper/io.tcl +++ b/flow/designs/gf12/swerv_wrapper/io.tcl @@ -1 +1,2 @@ -exclude_io_pin_region -region left:* -region right:* -region top:* -region bottom:0-10 -region bottom:400-700 +exclude_io_pin_region -region left:* -region right:* -region top:* \ + -region bottom:0-10 -region bottom:400-700 diff --git a/flow/designs/gf12/swerv_wrapper/rules-base.json b/flow/designs/gf12/swerv_wrapper/rules-base.json index 41042fe3ee..eccdad7d0f 100644 --- a/flow/designs/gf12/swerv_wrapper/rules-base.json +++ b/flow/designs/gf12/swerv_wrapper/rules-base.json @@ -24,7 +24,7 @@ "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 13650, + "value": 11303, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 2668710, + "value": 2311628, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 521, + "value": 755, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/gf12/tinyRocket/constraint.sdc b/flow/designs/gf12/tinyRocket/constraint.sdc index e5604adf91..79e26f0bee 100644 --- a/flow/designs/gf12/tinyRocket/constraint.sdc +++ b/flow/designs/gf12/tinyRocket/constraint.sdc @@ -1,13 +1,13 @@ -set clk_name core_clock +set clk_name core_clock set clk_port_name clock -set clk_period 800 +set clk_period 800 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/aes-hybrid/rules-base.json b/flow/designs/gf180/aes-hybrid/rules-base.json index 2699ea70df..1478ea051c 100644 --- a/flow/designs/gf180/aes-hybrid/rules-base.json +++ b/flow/designs/gf180/aes-hybrid/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 21061, + "value": 26088, "compare": "<=" }, "detailedplace__design__violations": { @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 0, + "value": 84, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1815251, + "value": 1799784, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,15 +44,15 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 9, + "value": 8, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.3, + "value": -1.43, "compare": ">=" }, "finish__design__instance__area": { - "value": 685668, + "value": 803898, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -39.5, + "value": -37.4, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf180/aes/constraint.sdc b/flow/designs/gf180/aes/constraint.sdc index 2e7189ca5f..9efd6867db 100644 --- a/flow/designs/gf180/aes/constraint.sdc +++ b/flow/designs/gf180/aes/constraint.sdc @@ -1,19 +1,18 @@ current_design aes_cipher_top -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 3 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] set_timing_derate -early 0.9500 set_timing_derate -late 1.0500 - diff --git a/flow/designs/gf180/aes/rules-base.json b/flow/designs/gf180/aes/rules-base.json index 2b3dc898b8..9de3ce5b90 100644 --- a/flow/designs/gf180/aes/rules-base.json +++ b/flow/designs/gf180/aes/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 21792, + "value": 25876, "compare": "<=" }, "detailedplace__design__violations": { @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 0, + "value": 72, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1512295, + "value": 1477421, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,11 +48,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.12, + "value": -1.25, "compare": ">=" }, "finish__design__instance__area": { - "value": 762481, + "value": 905336, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { diff --git a/flow/designs/gf180/ibex/config.mk b/flow/designs/gf180/ibex/config.mk index ebeeadf520..ed5fd3dd6e 100644 --- a/flow/designs/gf180/ibex/config.mk +++ b/flow/designs/gf180/ibex/config.mk @@ -2,43 +2,13 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = gf180 -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \ + $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v + +export VERILOG_INCLUDE_DIRS = \ + $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/ + +export SYNTH_HDL_FRONTEND = slang export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc diff --git a/flow/designs/gf180/ibex/constraint.sdc b/flow/designs/gf180/ibex/constraint.sdc index e6e7f6257a..24711119f1 100644 --- a/flow/designs/gf180/ibex/constraint.sdc +++ b/flow/designs/gf180/ibex/constraint.sdc @@ -1,6 +1,6 @@ current_design ibex_core -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 10.0 set clk_io_pct 0.2 @@ -9,8 +9,8 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] set_false_path -from [get_ports {rst_ni}] diff --git a/flow/designs/gf180/ibex/rules-base.json b/flow/designs/gf180/ibex/rules-base.json index 9e38f16d6d..1614e8fcee 100644 --- a/flow/designs/gf180/ibex/rules-base.json +++ b/flow/designs/gf180/ibex/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 738423.39, + "value": 731295.7, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 845748, + "value": 813057, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 17828, + "value": 16937, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1550, + "value": 1473, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1550, + "value": 1473, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 0, + "value": 38, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1753283, + "value": 1544585, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.58, + "value": -0.77, "compare": ">=" }, "finish__design__instance__area": { - "value": 899459, + "value": 985974, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 1013, + "value": 736, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -21.3, + "value": -14.05, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf180/jpeg/constraint.sdc b/flow/designs/gf180/jpeg/constraint.sdc index d123c56533..42d6b4abf9 100644 --- a/flow/designs/gf180/jpeg/constraint.sdc +++ b/flow/designs/gf180/jpeg/constraint.sdc @@ -1,6 +1,6 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 7.5 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/jpeg/io.tcl b/flow/designs/gf180/jpeg/io.tcl index e023ab42b4..0c81b1f9fa 100644 --- a/flow/designs/gf180/jpeg/io.tcl +++ b/flow/designs/gf180/jpeg/io.tcl @@ -1 +1 @@ -exclude_io_pin_region -region top:* -region bottom:* \ No newline at end of file +exclude_io_pin_region -region top:* -region bottom:* diff --git a/flow/designs/gf180/jpeg/rules-base.json b/flow/designs/gf180/jpeg/rules-base.json index f9a5a19c70..f3d7b6a752 100644 --- a/flow/designs/gf180/jpeg/rules-base.json +++ b/flow/designs/gf180/jpeg/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 2163344.49, + "value": 2161429.49, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2383064, + "value": 2362986, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 54888, + "value": 53818, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 4773, + "value": 4680, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 4773, + "value": 4680, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 15, + "value": 0, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 4344677, + "value": 2973166, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 9, + "value": 10, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.08, + "value": 0.0, "compare": ">=" }, "finish__design__instance__area": { - "value": 2438978, + "value": 2695462, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 2386, + "value": 2340, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/gf180/riscv32i/constraint.sdc b/flow/designs/gf180/riscv32i/constraint.sdc index 26f4484628..3b2184da75 100644 --- a/flow/designs/gf180/riscv32i/constraint.sdc +++ b/flow/designs/gf180/riscv32i/constraint.sdc @@ -1,12 +1,12 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 10.0 +set clk_period 10.0 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set non_clock_inputs [all_inputs -no_clocks] +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/riscv32i/rules-base.json b/flow/designs/gf180/riscv32i/rules-base.json index 7cc69d5b09..02bc390fc2 100644 --- a/flow/designs/gf180/riscv32i/rules-base.json +++ b/flow/designs/gf180/riscv32i/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 414808, + "value": 383765, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 8511, + "value": 8224, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 740, + "value": 715, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 740, + "value": 715, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 0, + "value": 2, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 891236, + "value": 739817, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.45, + "value": -1.04, "compare": ">=" }, "finish__design__instance__area": { - "value": 435127, + "value": 475387, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 370, + "value": 358, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl b/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl index c89b0808dd..c431fbff0f 100644 --- a/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl +++ b/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl @@ -18,14 +18,16 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} #################################### # standard cell grid #################################### -define_pdn_grid -name {block} -voltage_domains {CORE} +define_pdn_grid -name {block} -voltage_domains {CORE} add_pdn_stripe -grid {block} -layer {Metal1} -width {0.900} -pitch {5.040} -offset {0} -followpins -add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} -offset {22.4} +add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} \ + -offset {22.4} add_pdn_stripe -grid {block} -layer {Metal5} -width {4.480} -pitch {89.6} -offset {44.8} add_pdn_connect -grid {block} -layers {Metal1 Metal4} add_pdn_connect -grid {block} -layers {Metal4 Metal5} #################################### # Block grids #################################### -define_pdn_grid -macro -cells uart_rx -halo "2.0 2.0 2.0 2.0" -voltage_domains {CORE} -name BlocksGrid +define_pdn_grid -macro -cells uart_rx -halo "2.0 2.0 2.0 2.0" -voltage_domains {CORE} \ + -name BlocksGrid add_pdn_connect -grid {BlocksGrid} -layers {Metal4 Metal5} diff --git a/flow/designs/gf180/uart-blocks/constraint.sdc b/flow/designs/gf180/uart-blocks/constraint.sdc index e921f859f9..e4bcee59d1 100644 --- a/flow/designs/gf180/uart-blocks/constraint.sdc +++ b/flow/designs/gf180/uart-blocks/constraint.sdc @@ -1,4 +1,4 @@ -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 6 set clk_io_pct 0.2 @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/uart-blocks/rules-base.json b/flow/designs/gf180/uart-blocks/rules-base.json index eaea660e58..e54080e043 100644 --- a/flow/designs/gf180/uart-blocks/rules-base.json +++ b/flow/designs/gf180/uart-blocks/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 731, + "value": 726, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 64, + "value": 63, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 64, + "value": 63, "compare": "<=" }, "globalroute__antenna_diodes_count": { diff --git a/flow/designs/gf180/uart-blocks/tapcell.tcl b/flow/designs/gf180/uart-blocks/tapcell.tcl index b3d1bf1303..aa4a9daa9d 100644 --- a/flow/designs/gf180/uart-blocks/tapcell.tcl +++ b/flow/designs/gf180/uart-blocks/tapcell.tcl @@ -1,8 +1,7 @@ - tapcell \ - -endcap_cpp "12" \ - -distance 100 \ - -tapcell_master $::env(TIE_CELL) \ - -endcap_master $::env(ENDCAP_CELL) \ - -halo_width_x $::env(MACRO_ROWS_HALO_X) \ - -halo_width_y $::env(MACRO_ROWS_HALO_Y) - +tapcell \ + -endcap_cpp "12" \ + -distance 100 \ + -tapcell_master $::env(TIE_CELL) \ + -endcap_master $::env(ENDCAP_CELL) \ + -halo_width_x $::env(MACRO_ROWS_HALO_X) \ + -halo_width_y $::env(MACRO_ROWS_HALO_Y) diff --git a/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc b/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc index ffe2329cf5..e4bcee59d1 100644 --- a/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc +++ b/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc @@ -1,13 +1,13 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 6 +set clk_period 6 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl b/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl index f5185790be..ac80ec7d83 100644 --- a/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl +++ b/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl @@ -18,7 +18,9 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} #################################### # standard cell grid #################################### -define_pdn_grid -name {block} -voltage_domains {CORE} -add_pdn_stripe -grid {block} -layer {Metal1} -width {0.900} -pitch {5.040} -offset {0} -followpins -add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} -offset {22.4} +define_pdn_grid -name {block} -voltage_domains {CORE} +add_pdn_stripe -grid {block} -layer {Metal1} -width {0.900} -pitch {5.040} -offset {0} \ + -followpins +add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} \ + -offset {22.4} add_pdn_connect -grid {block} -layers {Metal1 Metal4} diff --git a/flow/designs/harness.mk b/flow/designs/harness.mk deleted file mode 100644 index 39db272b06..0000000000 --- a/flow/designs/harness.mk +++ /dev/null @@ -1,22 +0,0 @@ -export DESIGN_NAME ?= SPECIFY_DESIGN_NAME -export PLATFORM = nangate45 - -export VERILOG_FILES = ./designs/src/harness/*.v -export SDC_FILE = ./designs/src/harness/design.sdc - -export MERGED_LEF = $(PLATFORM_DIR)/NangateOpenCellLibrary.mod.lef -export LIB_FILES = $(PLATFORM_DIR)/NangateOpenCellLibrary_typical.lib -export GDS_FILES = $(sort $(wildcard $(PLATFORM_DIR)/gds/*)) - -# Automatically pick a reasonable area and utilization - -# Core utilization in % -export CORE_UTILIZATION = 10.0 -# Core height / core width -export CORE_ASPECT_RATIO = 1.0 -# Core margin in um -export CORE_MARGIN = 2.0 - -# Start with 250MHz for nangate45, relatively conservative -export CLOCK_PERIOD = 4 -export CLOCK_PORT = clock diff --git a/flow/designs/ihp-sg13g2/aes/constraint.sdc b/flow/designs/ihp-sg13g2/aes/constraint.sdc index ec67329fda..f0b3b99355 100644 --- a/flow/designs/ihp-sg13g2/aes/constraint.sdc +++ b/flow/designs/ihp-sg13g2/aes/constraint.sdc @@ -1,16 +1,15 @@ current_design aes_cipher_top -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 4.5 +set clk_period 4.5 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] - diff --git a/flow/designs/ihp-sg13g2/aes/rules-base.json b/flow/designs/ihp-sg13g2/aes/rules-base.json index 4027a1c50a..8d1832de8c 100644 --- a/flow/designs/ihp-sg13g2/aes/rules-base.json +++ b/flow/designs/ihp-sg13g2/aes/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 210460, + "value": 229478, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 19280, + "value": 18986, "compare": "<=" }, "detailedplace__design__violations": { @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 282, + "value": 6, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -40,11 +40,11 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 39, + "value": 0, "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 5, + "value": 39, "compare": "<=" }, "finish__timing__setup__ws": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 841, + "value": 826, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/ihp-sg13g2/gcd/constraint.sdc b/flow/designs/ihp-sg13g2/gcd/constraint.sdc index 0e975c114d..0c1e6d1d5b 100644 --- a/flow/designs/ihp-sg13g2/gcd/constraint.sdc +++ b/flow/designs/ihp-sg13g2/gcd/constraint.sdc @@ -1,6 +1,6 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk set clk_period 2.6 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/gcd/rules-base.json b/flow/designs/ihp-sg13g2/gcd/rules-base.json index 61cbba865c..e8f4653148 100644 --- a/flow/designs/ihp-sg13g2/gcd/rules-base.json +++ b/flow/designs/ihp-sg13g2/gcd/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 505, + "value": 494, "compare": "<=" }, "detailedplace__design__violations": { @@ -48,11 +48,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.16, + "value": 0.0, "compare": ">=" }, "finish__design__instance__area": { - "value": 27357, + "value": 27303, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/config.mk b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/config.mk new file mode 100644 index 0000000000..68feb648f2 --- /dev/null +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/config.mk @@ -0,0 +1,20 @@ +export DESIGN_NAME = I2cDeviceCtrl +export TOP_DESIGN_NICKNAME = i2c-gpio-expander +export DESIGN_NICKNAME = ${TOP_DESIGN_NICKNAME}_${DESIGN_NAME} +export PLATFORM = ihp-sg13g2 + +export VERILOG_FILES = $(DESIGN_HOME)/$(PLATFORM)/${TOP_DESIGN_NICKNAME}/I2cGpioExpander.v \ + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(TOP_DESIGN_NICKNAME)/${DESIGN_NAME}/constraint.sdc + +export DIE_AREA = 0.0 0.0 147.84 147.42 +export CORE_AREA = 18.72 18.9 128.64 128.52 + +export MAX_ROUTING_LAYER = TopMetal2 + +export TNS_END_PERCENT = 100 +export PLACE_DENSITY = 0.75 + +export CORNERS = slow typ fast + +export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(TOP_DESIGN_NICKNAME)/${DESIGN_NAME}/pdn.tcl diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/constraint.sdc b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/constraint.sdc new file mode 100644 index 0000000000..95787b8df0 --- /dev/null +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/constraint.sdc @@ -0,0 +1,22 @@ +current_design I2cDeviceCtrl/I2cDeviceCtrl +set_units -time ns -resistance kOhm -capacitance pF -voltage V -current uA +set_max_fanout 8 [current_design] +set_max_capacitance 0.5 [current_design] +set_max_transition 3 [current_design] +set_max_area 0 + +create_clock [get_ports clock] -name clock -period 20.0 -waveform {0 10.0} +set_ideal_network [get_ports clock] +set_clock_uncertainty 0.15 [get_clocks clock] +set_clock_transition 0.25 [get_clocks clock] +set input_delay_value_clock 4.0 +set output_delay_value_clock 4.0 +set clk_indx_clock [lsearch [all_inputs] [get_port clock]] +set all_inputs_wo_clk_rst_clock [lreplace [all_inputs] $clk_indx_clock $clk_indx_clock ""] +set_input_delay $input_delay_value_clock -clock [get_clocks clock] $all_inputs_wo_clk_rst_clock +set_output_delay $output_delay_value_clock -clock [get_clocks clock] [all_outputs] + +set_load -pin_load 5 [all_inputs] +set_load -pin_load 5 [all_outputs] +set_timing_derate -early 0.95 +set_timing_derate -late 1.05 diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl new file mode 100644 index 0000000000..aa6f2f142a --- /dev/null +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl @@ -0,0 +1,38 @@ +# standard cells +add_global_connection -net {VDD} -pin_pattern {^VDD$} -power +add_global_connection -net {VDD} -pin_pattern {^VDDPE$} +add_global_connection -net {VDD} -pin_pattern {^VDDCE$} +add_global_connection -net {VSS} -pin_pattern {^VSS$} -ground +add_global_connection -net {VSS} -pin_pattern {^VSSE$} + +# macros +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VDD!} -power +add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VSS!} -ground +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power +add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground + +# padframe core power pins +add_global_connection -net {VDD} -pin_pattern {^vdd$} -power +add_global_connection -net {VSS} -pin_pattern {^vss$} -ground + +# padframe io power pins +add_global_connection -net {IOVDD} -pin_pattern {^iovdd$} -power +add_global_connection -net {IOVSS} -pin_pattern {^iovss$} -ground + +global_connect + +# core voltage domain +set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} + +# stdcell grid +define_pdn_grid -name {grid} -voltage_domains {CORE} +add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} \ + -followpins -extend_to_core_ring +add_pdn_ring -grid {grid} -layers {Metal3 Metal4} -widths {3.0} -spacings {2.0} \ + -core_offsets {4.5} -connect_to_pads +add_pdn_stripe -grid {grid} -layer {Metal3} -width {1.840} -pitch {75.6} -offset {37.8} \ + -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {Metal4} -width {1.840} -pitch {75.6} -offset {37.8} \ + -extend_to_core_ring +add_pdn_connect -grid {grid} -layers {Metal1 Metal3} +add_pdn_connect -grid {grid} -layers {Metal3 Metal4} diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk b/flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk index de8d933f03..f46620b481 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk @@ -3,18 +3,22 @@ export DESIGN_NICKNAME = i2c-gpio-expander export PLATFORM = ihp-sg13g2 export VERILOG_FILES = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).v \ - $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/I2cGpioExpander.v + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/I2cGpioExpander.v export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export SEAL_GDS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sealring.gds.gz export DIE_AREA = 0.0 0.0 1050.0 1050.0 -export CORE_AREA = 425.28 427.16 631.2 630.24 +export CORE_AREA = 351.36 351.54 699.84 699.3 export MAX_ROUTING_LAYER = TopMetal2 export TNS_END_PERCENT = 100 export PLACE_DENSITY = 0.75 +export CORNERS = slow fast + export FOOTPRINT_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/pad.tcl export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/pdn.tcl + +export BLOCKS = I2cDeviceCtrl diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc b/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc index 02aff71773..b66bcf5e1c 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc @@ -10,45 +10,45 @@ create_clock [get_pins sg13g2_IOPad_io_clock/p2c] -name clk_core -period 20.0 -w set_clock_uncertainty 0.15 [get_clocks clk_core] set_clock_transition 0.25 [get_clocks clk_core] -set clock_ports [get_ports { - io_clock_PAD +set clock_ports [get_ports { + io_clock_PAD }] set_driving_cell -lib_cell sg13g2_IOPadIn -pin pad $clock_ports -set clk_core_inout_16mA_ports [get_ports { - io_gpio_0_PAD - io_gpio_1_PAD - io_gpio_2_PAD - io_gpio_3_PAD - io_gpio_4_PAD - io_gpio_5_PAD - io_gpio_6_PAD - io_gpio_7_PAD -}] +set clk_core_inout_16mA_ports [get_ports { + io_gpio_0_PAD + io_gpio_1_PAD + io_gpio_2_PAD + io_gpio_3_PAD + io_gpio_4_PAD + io_gpio_5_PAD + io_gpio_6_PAD + io_gpio_7_PAD +}] set_driving_cell -lib_cell sg13g2_IOPadInOut16mA -pin pad $clk_core_inout_16mA_ports set_input_delay 8 -clock clk_core $clk_core_inout_16mA_ports set_output_delay 8 -clock clk_core $clk_core_inout_16mA_ports -set clk_core_inout_4mA_ports [get_ports { - io_i2c_scl_PAD - io_i2c_sda_PAD -}] +set clk_core_inout_4mA_ports [get_ports { + io_i2c_scl_PAD + io_i2c_sda_PAD +}] set_driving_cell -lib_cell sg13g2_IOPadInOut4mA -pin pad $clk_core_inout_4mA_ports set_input_delay 8 -clock clk_core $clk_core_inout_4mA_ports set_output_delay 8 -clock clk_core $clk_core_inout_4mA_ports -set clk_core_input_ports [get_ports { - io_reset_PAD - io_address_0_PAD - io_address_1_PAD - io_address_2_PAD -}] +set clk_core_input_ports [get_ports { + io_reset_PAD + io_address_0_PAD + io_address_1_PAD + io_address_2_PAD +}] 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+} \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl index 5ed1a981fa..049987ebe2 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl @@ -2,82 +2,180 @@ set IO_LENGTH 180 set IO_WIDTH 80 set BONDPAD_SIZE 70 set SEALRING_OFFSET 70 +set IO_OFFSET [expr { $BONDPAD_SIZE + $SEALRING_OFFSET }] -proc calc_horizontal_pad_location {index total} { - global IO_LENGTH - global IO_WIDTH - global BONDPAD_SIZE - global SEALRING_OFFSET +proc calc_horizontal_pad_location { index total IO_LENGTH IO_WIDTH BONDPAD_SIZE SEALRING_OFFSET } { + set DIE_WIDTH [expr { [lindex $::env(DIE_AREA) 2] - [lindex $::env(DIE_AREA) 0] }] + set PAD_OFFSET [expr { $IO_LENGTH + $BONDPAD_SIZE + $SEALRING_OFFSET }] + set PAD_AREA_WIDTH [expr { $DIE_WIDTH - ($PAD_OFFSET * 2) }] + set HORIZONTAL_PAD_DISTANCE [expr { ($PAD_AREA_WIDTH / $total) - $IO_WIDTH }] - set DIE_WIDTH [expr {[lindex $::env(DIE_AREA) 2] - [lindex $::env(DIE_AREA) 0]}] - set PAD_OFFSET [expr {$IO_LENGTH + $BONDPAD_SIZE + $SEALRING_OFFSET}] - set PAD_AREA_WIDTH [expr {$DIE_WIDTH - ($PAD_OFFSET * 2)}] - set HORIZONTAL_PAD_DISTANCE [expr {($PAD_AREA_WIDTH / $total) - $IO_WIDTH}] - - return [expr {$PAD_OFFSET + (($IO_WIDTH + $HORIZONTAL_PAD_DISTANCE) * $index) + ($HORIZONTAL_PAD_DISTANCE / 2)}] + return [expr { + $PAD_OFFSET + (($IO_WIDTH + $HORIZONTAL_PAD_DISTANCE) * $index) + + ($HORIZONTAL_PAD_DISTANCE / 2) + }] } -proc calc_vertical_pad_location {index total} { - global IO_LENGTH - global IO_WIDTH - global BONDPAD_SIZE - global SEALRING_OFFSET - - set DIE_HEIGHT [expr {[lindex $::env(DIE_AREA) 3] - [lindex $::env(DIE_AREA) 1]}] - set PAD_OFFSET [expr {$IO_LENGTH + $BONDPAD_SIZE + $SEALRING_OFFSET}] - set PAD_AREA_HEIGHT [expr {$DIE_HEIGHT - ($PAD_OFFSET * 2)}] - set VERTICAL_PAD_DISTANCE [expr {($PAD_AREA_HEIGHT / $total) - $IO_WIDTH}] +proc calc_vertical_pad_location { index total IO_LENGTH IO_WIDTH BONDPAD_SIZE SEALRING_OFFSET } { + set DIE_HEIGHT [expr { [lindex $::env(DIE_AREA) 3] - [lindex $::env(DIE_AREA) 1] }] + set PAD_OFFSET [expr { $IO_LENGTH + $BONDPAD_SIZE + $SEALRING_OFFSET }] + set PAD_AREA_HEIGHT [expr { $DIE_HEIGHT - ($PAD_OFFSET * 2) }] + set VERTICAL_PAD_DISTANCE [expr { ($PAD_AREA_HEIGHT / $total) - $IO_WIDTH }] - return [expr {$PAD_OFFSET + (($IO_WIDTH + $VERTICAL_PAD_DISTANCE) * $index) + ($VERTICAL_PAD_DISTANCE / 2)}] + return [expr { + $PAD_OFFSET + (($IO_WIDTH + $VERTICAL_PAD_DISTANCE) * $index) + + ($VERTICAL_PAD_DISTANCE / 2) + }] } make_fake_io_site -name IOLibSite -width 1 -height $IO_LENGTH make_fake_io_site -name IOLibCSite -width $IO_LENGTH -height $IO_LENGTH -set IO_OFFSET [expr {$BONDPAD_SIZE + $SEALRING_OFFSET}] +set IO_OFFSET [expr { $BONDPAD_SIZE + $SEALRING_OFFSET }] # Create IO Rows make_io_sites \ - -horizontal_site IOLibSite \ - -vertical_site IOLibSite \ - -corner_site IOLibCSite \ - -offset $IO_OFFSET + -horizontal_site IOLibSite \ + -vertical_site IOLibSite \ + -corner_site IOLibCSite \ + -offset $IO_OFFSET -# Place Pads\n# IO pin io_clock -place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 0 5] {sg13g2_IOPad_io_clock} -master sg13g2_IOPadIn +# Place Pads +# IO pin io_clock +place_pad \ + -row IO_SOUTH \ + -location [calc_horizontal_pad_location \ + 0 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_clock} \ + -master sg13g2_IOPadIn # IO pin io_reset -place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 1 5] {sg13g2_IOPad_io_reset} -master sg13g2_IOPadIn +place_pad \ + -row IO_SOUTH \ + -location [calc_horizontal_pad_location \ + 1 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_reset} \ + -master sg13g2_IOPadIn # IO pin io_i2c_scl -place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 2 5] {sg13g2_IOPad_io_i2c_scl} -master sg13g2_IOPadInOut4mA +place_pad \ + -row IO_SOUTH \ + -location [calc_horizontal_pad_location \ + 2 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_i2c_scl} \ + -master sg13g2_IOPadInOut4mA # IO pin io_i2c_sda -place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 3 5] {sg13g2_IOPad_io_i2c_sda} -master sg13g2_IOPadInOut4mA +place_pad \ + -row IO_SOUTH \ + -location [calc_horizontal_pad_location \ + 3 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_i2c_sda} \ + -master sg13g2_IOPadInOut4mA # IO pin io_i2c_interrupt -place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 4 5] {sg13g2_IOPad_io_i2c_interrupt} -master sg13g2_IOPadOut4mA -place_pad -row IO_EAST -location [calc_vertical_pad_location 0 5] {sg13g2_IOPadVdd_east_0} -master sg13g2_IOPadVdd -place_pad -row IO_EAST -location [calc_vertical_pad_location 1 5] {sg13g2_IOPadVss_east_1} -master sg13g2_IOPadVss +place_pad \ + -row IO_SOUTH \ + -location [calc_horizontal_pad_location \ + 4 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_i2c_interrupt} \ + -master sg13g2_IOPadOut4mA +place_pad \ + -row IO_EAST \ + -location [calc_vertical_pad_location \ + 0 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPadVdd_east_0} \ + -master sg13g2_IOPadVdd +place_pad \ + -row IO_EAST \ + -location [calc_vertical_pad_location \ + 1 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPadVss_east_1} \ + -master sg13g2_IOPadVss # IO pin io_address_0 -place_pad -row IO_EAST -location [calc_vertical_pad_location 2 5] {sg13g2_IOPad_io_address_0} -master sg13g2_IOPadIn +place_pad \ + -row IO_EAST \ + -location [calc_vertical_pad_location \ + 2 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_address_0} \ + -master sg13g2_IOPadIn # IO pin io_address_1 -place_pad -row IO_EAST -location [calc_vertical_pad_location 3 5] {sg13g2_IOPad_io_address_1} -master sg13g2_IOPadIn +place_pad \ + -row IO_EAST \ + -location [calc_vertical_pad_location \ + 3 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_address_1} \ + -master sg13g2_IOPadIn # IO pin io_address_2 -place_pad -row IO_EAST -location [calc_vertical_pad_location 4 5] {sg13g2_IOPad_io_address_2} -master sg13g2_IOPadIn +place_pad \ + -row IO_EAST \ + -location [calc_vertical_pad_location \ + 4 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_address_2} \ + -master sg13g2_IOPadIn # IO pin io_gpio_0 -place_pad -row IO_NORTH -location [calc_horizontal_pad_location 0 5] {sg13g2_IOPad_io_gpio_0} -master sg13g2_IOPadInOut16mA +place_pad \ + -row IO_NORTH \ + -location [calc_horizontal_pad_location \ + 0 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_0} \ + -master sg13g2_IOPadInOut16mA # IO pin io_gpio_1 -place_pad -row IO_NORTH -location [calc_horizontal_pad_location 1 5] {sg13g2_IOPad_io_gpio_1} -master sg13g2_IOPadInOut16mA +place_pad \ + -row IO_NORTH \ + -location [calc_horizontal_pad_location \ + 1 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_1} \ + -master sg13g2_IOPadInOut16mA # IO pin io_gpio_2 -place_pad -row IO_NORTH -location [calc_horizontal_pad_location 2 5] {sg13g2_IOPad_io_gpio_2} -master sg13g2_IOPadInOut16mA +place_pad \ + -row IO_NORTH \ + -location [calc_horizontal_pad_location \ + 2 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_2} \ + -master sg13g2_IOPadInOut16mA # IO pin io_gpio_3 -place_pad -row IO_NORTH -location [calc_horizontal_pad_location 3 5] {sg13g2_IOPad_io_gpio_3} -master sg13g2_IOPadInOut16mA +place_pad \ + -row IO_NORTH \ + -location [calc_horizontal_pad_location \ + 3 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_3} \ + -master sg13g2_IOPadInOut16mA # IO pin io_gpio_4 -place_pad -row IO_NORTH -location [calc_horizontal_pad_location 4 5] {sg13g2_IOPad_io_gpio_4} -master sg13g2_IOPadInOut16mA +place_pad \ + -row IO_NORTH \ + -location [calc_horizontal_pad_location \ + 4 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_4} \ + -master sg13g2_IOPadInOut16mA # IO pin io_gpio_5 -place_pad -row IO_WEST -location [calc_vertical_pad_location 0 5] {sg13g2_IOPad_io_gpio_5} -master sg13g2_IOPadInOut16mA +place_pad \ + -row IO_WEST \ + -location [calc_vertical_pad_location \ + 0 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_5} \ + -master sg13g2_IOPadInOut16mA # IO pin io_gpio_6 -place_pad -row IO_WEST -location [calc_vertical_pad_location 1 5] {sg13g2_IOPad_io_gpio_6} -master sg13g2_IOPadInOut16mA +place_pad \ + -row IO_WEST \ + -location [calc_vertical_pad_location \ + 1 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_6} \ + -master sg13g2_IOPadInOut16mA # IO pin io_gpio_7 -place_pad -row IO_WEST -location [calc_vertical_pad_location 2 5] {sg13g2_IOPad_io_gpio_7} -master sg13g2_IOPadInOut16mA -place_pad -row IO_WEST -location [calc_vertical_pad_location 3 5] {sg13g2_IOPadIOVss_west_3} -master sg13g2_IOPadIOVss -place_pad -row IO_WEST -location [calc_vertical_pad_location 4 5] {sg13g2_IOPadIOVdd_west_4} -master sg13g2_IOPadIOVdd +place_pad \ + -row IO_WEST \ + -location [calc_vertical_pad_location \ + 2 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_7} \ + -master sg13g2_IOPadInOut16mA +place_pad \ + -row IO_WEST \ + -location [calc_vertical_pad_location \ + 3 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPadIOVss_west_3} \ + -master sg13g2_IOPadIOVss +place_pad \ + -row IO_WEST \ + -location [calc_vertical_pad_location \ + 4 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPadIOVdd_west_4} \ + -master sg13g2_IOPadIOVdd # Place Corner Cells and Filler place_corners sg13g2_Corner diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl index 0534bb5bde..6e80d2f55e 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl @@ -1,12 +1,16 @@ - -# stdcell power pins +# standard cells add_global_connection -net {VDD} -pin_pattern {^VDD$} -power add_global_connection -net {VDD} -pin_pattern {^VDDPE$} add_global_connection -net {VDD} -pin_pattern {^VDDCE$} - add_global_connection -net {VSS} -pin_pattern {^VSS$} -ground add_global_connection -net {VSS} -pin_pattern {^VSSE$} +# macros +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VDD!} -power +add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VSS!} -ground +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power +add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground + # padframe core power pins add_global_connection -net {VDD} -pin_pattern {^vdd$} -power add_global_connection -net {VSS} -pin_pattern {^vss$} -ground @@ -22,43 +26,21 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} # stdcell grid define_pdn_grid -name {grid} -voltage_domains {CORE} -add_pdn_ring \ - -grid {grid} \ - -layers {Metal5 TopMetal1} \ - -widths {30.0} \ - -spacings {5.0} \ - -core_offsets {4.5} \ - -connect_to_pads -add_pdn_stripe \ - -grid {grid} \ - -layer {Metal1} \ - -width {0.44} \ - -pitch {7.56} \ - -offset {0} \ - -followpins \ - -extend_to_core_ring -add_pdn_stripe \ - -grid {grid} \ - -layer {Metal5} \ - -width {2.200} \ - -pitch {75.6} \ - -offset {13.600} \ - -extend_to_core_ring -add_pdn_stripe \ - -grid {grid} \ - -layer {TopMetal1} \ - -width {2.200} \ - -pitch {75.6} \ - -offset {13.600} \ - -extend_to_core_ring -add_pdn_stripe \ - -grid {grid} \ - -layer {TopMetal2} \ - -width {2.200} \ - -pitch {75.6} \ - -offset {13.600} \ - -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} \ + -followpins -extend_to_core_ring +add_pdn_ring -grid {grid} -layers {Metal5 TopMetal1} -widths {8.0} -spacings {5.0} \ + -core_offsets {4.5} -connect_to_pads +add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {37.8} \ + -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {2.200} -pitch {75.6} -offset {37.8} \ + -extend_to_core_ring add_pdn_connect -grid {grid} -layers {Metal1 Metal5} add_pdn_connect -grid {grid} -layers {Metal5 TopMetal1} add_pdn_connect -grid {grid} -layers {Metal5 TopMetal2} add_pdn_connect -grid {grid} -layers {TopMetal1 TopMetal2} + +define_pdn_grid \ + -name {CORE_macro_grid_1} -voltage_domains {CORE} \ + -macro -cells {I2cDeviceCtrl} -grid_over_boundary +add_pdn_connect -grid {CORE_macro_grid_1} -layers {Metal3 TopMetal1} +add_pdn_connect -grid {CORE_macro_grid_1} -layers {Metal4 TopMetal1} diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json index c1f8f21746..e848ab6240 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 23061, + "value": 39158, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 1601, + "value": 965, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 139, + "value": 84, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 139, + "value": 84, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 14, + "value": 18, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 49751, + "value": 39121, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -40,11 +40,11 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 1, + "value": 0, "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 5, + "value": 22, "compare": "<=" }, "finish__timing__setup__ws": { @@ -52,11 +52,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 44306, + "value": 135868, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 70, + "value": 42, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/ihp-sg13g2/ibex/config.mk b/flow/designs/ihp-sg13g2/ibex/config.mk index 8565d7e0b5..2ec1ac66f8 100644 --- a/flow/designs/ihp-sg13g2/ibex/config.mk +++ b/flow/designs/ihp-sg13g2/ibex/config.mk @@ -2,43 +2,13 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = ihp-sg13g2 -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \ + $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v + +export VERILOG_INCLUDE_DIRS = \ + $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/ + +export SYNTH_HDL_FRONTEND = slang export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc diff --git a/flow/designs/ihp-sg13g2/ibex/constraint.sdc b/flow/designs/ihp-sg13g2/ibex/constraint.sdc index a4faf836eb..fed426995f 100644 --- a/flow/designs/ihp-sg13g2/ibex/constraint.sdc +++ b/flow/designs/ihp-sg13g2/ibex/constraint.sdc @@ -1,6 +1,6 @@ current_design ibex_core -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 10.0 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/ibex/constraint_doe.sdc b/flow/designs/ihp-sg13g2/ibex/constraint_doe.sdc index e169d10114..31ddde31d7 100644 --- a/flow/designs/ihp-sg13g2/ibex/constraint_doe.sdc +++ b/flow/designs/ihp-sg13g2/ibex/constraint_doe.sdc @@ -1,5 +1,5 @@ set uncertainty 1.0 -set io_delay 7.0 +set io_delay 7.0 set clock_port clk_i @@ -11,5 +11,5 @@ create_clock -name core_clock -period 15.0 -waveform {0.0000 7.5} [get_ports {cl set_clock_uncertainty $uncertainty [all_clocks] # -set_input_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_inputs] -set_output_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_outputs] +set_input_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_inputs] +set_output_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_outputs] diff --git a/flow/designs/ihp-sg13g2/ibex/rules-base.json b/flow/designs/ihp-sg13g2/ibex/rules-base.json index 734d6b9ff4..5b12a715ff 100644 --- a/flow/designs/ihp-sg13g2/ibex/rules-base.json +++ b/flow/designs/ihp-sg13g2/ibex/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 305593, + "value": 365471, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 1215, + "value": 21, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1304850, + "value": 1072557, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -40,23 +40,23 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 48, + "value": 0, "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 5, + "value": 32, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.55, + "value": -0.17, "compare": ">=" }, "finish__design__instance__area": { - "value": 646738, + "value": 645302, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 1056, + "value": 906, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/ihp-sg13g2/jpeg/config.mk b/flow/designs/ihp-sg13g2/jpeg/config.mk index a1cfef88a4..24bb3852d5 100644 --- a/flow/designs/ihp-sg13g2/jpeg/config.mk +++ b/flow/designs/ihp-sg13g2/jpeg/config.mk @@ -6,8 +6,8 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/* export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc -export CORE_UTILIZATION = 55 -export PLACE_DENSITY_LB_ADDON = 0.20 +export CORE_UTILIZATION = 50 +export PLACE_DENSITY_LB_ADDON = 0.15 export TNS_END_PERCENT = 100 export REMOVE_ABC_BUFFERS = 1 diff --git a/flow/designs/ihp-sg13g2/jpeg/constraint.sdc b/flow/designs/ihp-sg13g2/jpeg/constraint.sdc index 879a3ef4b4..0ca3cc5b3d 100644 --- a/flow/designs/ihp-sg13g2/jpeg/constraint.sdc +++ b/flow/designs/ihp-sg13g2/jpeg/constraint.sdc @@ -1,15 +1,15 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 8.0 +set clk_period 8.0 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/jpeg/rules-base.json b/flow/designs/ihp-sg13g2/jpeg/rules-base.json index 8ce13b60b2..115f3ccc12 100644 --- a/flow/designs/ihp-sg13g2/jpeg/rules-base.json +++ b/flow/designs/ihp-sg13g2/jpeg/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 1512439.93, + "value": 1507968.61, "compare": "<=" }, "constraints__clocks__count": { @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 88060, + "value": 86736, "compare": "<=" }, "detailedplace__design__violations": { @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 1714, + "value": 12, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 3188482, + "value": 3140459, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -40,23 +40,23 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 110, + "value": 0, "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 5, + "value": 134, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -2.18, + "value": 0.0, "compare": ">=" }, "finish__design__instance__area": { - "value": 2610834, + "value": 2605152, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 3829, + "value": 3771, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -30.54, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc b/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc index 72adf7e57f..5b0a6f1b4e 100644 --- a/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc +++ b/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc @@ -1,4 +1,4 @@ -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 6.0 set clk_io_pct 0.2 @@ -9,10 +9,10 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [list] foreach input [all_inputs] { - if {$clk_port != $input} { - lappend $non_clock_inputs $input - } + if { $clk_port != $input } { + lappend $non_clock_inputs $input + } } -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/riscv32i/rules-base.json b/flow/designs/ihp-sg13g2/riscv32i/rules-base.json index 90b3c7852c..1559d3db81 100644 --- a/flow/designs/ihp-sg13g2/riscv32i/rules-base.json +++ b/flow/designs/ihp-sg13g2/riscv32i/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 177178, + "value": 170435, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 362, + "value": 0, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 770173, + "value": 511850, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -40,15 +40,15 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 20, + "value": 0, "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 5, + "value": 12, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.65, + "value": 0.0, "compare": ">=" }, "finish__design__instance__area": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 523, + "value": 478, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -18.36, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/spi/constraint.sdc b/flow/designs/ihp-sg13g2/spi/constraint.sdc index 5c7d8643e9..956369e4b8 100644 --- a/flow/designs/ihp-sg13g2/spi/constraint.sdc +++ b/flow/designs/ihp-sg13g2/spi/constraint.sdc @@ -1,6 +1,6 @@ current_design spi -set clk_name core_clock +set clk_name core_clock set clk_port_name clk set clk_period 0.9 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/spi/rules-base.json b/flow/designs/ihp-sg13g2/spi/rules-base.json index d51052ebb0..48f784b4d5 100644 --- a/flow/designs/ihp-sg13g2/spi/rules-base.json +++ b/flow/designs/ihp-sg13g2/spi/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 4391, + "value": 4888, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.3, + "value": -0.09, "compare": ">=" }, "finish__design__instance__area": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 20, + "value": 10, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -21.65, + "value": -15.68, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/intel16/aes/config.mk b/flow/designs/intel16/aes/config.mk deleted file mode 100644 index 6bbdea6e2d..0000000000 --- a/flow/designs/intel16/aes/config.mk +++ /dev/null @@ -1,18 +0,0 @@ -DESIGN_PDK_HOME := $(realpath $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) - -export DESIGN_NICKNAME = aes -export DESIGN_NAME = aes_cipher_top -export PLATFORM = intel16 - -export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = $(DESIGN_DIR)/constraint.sdc - -# These values must be multiples of placement site -# x=0.19 y=1.4 -export DIE_AREA = 0 0 250 250 -export CORE_AREA = 1.26 1.89 248 248 - - -export PLACE_DENSITY = uniform -#export SKIP_PIN_SWAP = 1 -export SKIP_GATE_CLONING = 1 diff --git a/flow/designs/intel16/aes/constraint.sdc b/flow/designs/intel16/aes/constraint.sdc deleted file mode 100644 index b90ac2d10e..0000000000 --- a/flow/designs/intel16/aes/constraint.sdc +++ /dev/null @@ -1,8 +0,0 @@ -set clk_name clk -set clk_period 2100 -# -create_clock -name $clk_name -period $clk_period [get_ports clk] -# -set_input_delay [expr $clk_period * 0.2] -clock $clk_name [all_inputs] -set_output_delay [expr $clk_period * 0.2] -clock $clk_name [all_outputs] - diff --git a/flow/designs/intel16/aes/rules-base.json b/flow/designs/intel16/aes/rules-base.json deleted file mode 100644 index aa912f3841..0000000000 --- a/flow/designs/intel16/aes/rules-base.json +++ /dev/null @@ -1,70 +0,0 @@ -{ - "synth__design__instance__area__stdcell": { - "value": 5582.34, - "compare": "<=" - }, - "constraints__clocks__count": { - "value": 1, - "compare": "==" - }, - "placeopt__design__instance__area": { - "value": 10618, - "compare": "<=" - }, - "placeopt__design__instance__count__stdcell": { - "value": 12985, - "compare": "<=" - }, - "detailedplace__design__violations": { - "value": 0, - "compare": "==" - }, - "cts__design__instance__count__setup_buffer": { - "value": 1159, - "compare": "<=" - }, - "cts__design__instance__count__hold_buffer": { - "value": 1129, - "compare": "<=" - }, - "globalroute__antenna_diodes_count": { - "value": 0, - "compare": "<=" - }, - "detailedroute__route__wirelength": { - "value": 319217, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { - "value": 0, - "compare": "<=" - }, - "detailedroute__antenna__violating__nets": { - "value": 0, - "compare": "<=" - }, - "detailedroute__antenna_diodes_count": { - "value": 5, - "compare": "<=" - }, - "finish__timing__setup__ws": { - "value": -125.35, - "compare": ">=" - }, - "finish__design__instance__area": { - "value": 10974, - "compare": "<=" - }, - "finish__timing__drv__setup_violation_count": { - "value": 565, - "compare": "<=" - }, - "finish__timing__drv__hold_violation_count": { - "value": 100, - "compare": "<=" - }, - "finish__timing__wns_percent_delay": { - "value": -10.0, - "compare": ">=" - } -} \ No newline at end of file diff --git a/flow/designs/intel16/gcd/config.mk b/flow/designs/intel16/gcd/config.mk deleted file mode 100644 index 6d857dfbd6..0000000000 --- a/flow/designs/intel16/gcd/config.mk +++ /dev/null @@ -1,15 +0,0 @@ -export DESIGN_NAME = gcd -export PLATFORM = intel16 - -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc -export ABC_AREA = 1 - -# Adders degrade GCD -export ADDER_MAP_FILE := - -export CORE_UTILIZATION = 30 -export CORE_ASPECT_RATIO = 1 -export CORE_MARGIN = 1 - -export PLACE_DENSITY = uniform diff --git a/flow/designs/intel16/ibex/config.mk b/flow/designs/intel16/ibex/config.mk deleted file mode 100644 index 86fa2349a7..0000000000 --- a/flow/designs/intel16/ibex/config.mk +++ /dev/null @@ -1,15 +0,0 @@ -DESIGN_PDK_HOME := $(realpath $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) - -export DESIGN_NICKNAME = ibex -export DESIGN_NAME = ibex_core -export PLATFORM = intel16 - -export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = $(DESIGN_DIR)/constraint.sdc - -export CORE_UTILIZATION = 30 -export CORE_ASPECT_RATIO = 1 -export CORE_MARGIN = 2 - -export PLACE_DENSITY = uniform -export SKIP_PIN_SWAP = 1 diff --git a/flow/designs/intel16/ibex/constraint.sdc b/flow/designs/intel16/ibex/constraint.sdc deleted file mode 100644 index 51ad46d500..0000000000 --- a/flow/designs/intel16/ibex/constraint.sdc +++ /dev/null @@ -1,8 +0,0 @@ -current_design ibex_core -set clk_name core_clock -set clk_period 3200 -# -create_clock -name $clk_name -period $clk_period [get_ports {clk_i}] -# -set_input_delay [expr $clk_period * 0.2] -clock $clk_name [all_inputs] -set_output_delay [expr $clk_period * 0.2] -clock $clk_name [all_outputs] diff --git a/flow/designs/intel16/ibex/rules-base.json b/flow/designs/intel16/ibex/rules-base.json deleted file mode 100644 index ccbf9c7d87..0000000000 --- a/flow/designs/intel16/ibex/rules-base.json +++ /dev/null @@ -1,70 +0,0 @@ -{ - "synth__design__instance__area__stdcell": { - "value": 9265.72, - "compare": "<=" - }, - "constraints__clocks__count": { - "value": 1, - "compare": "==" - }, - "placeopt__design__instance__area": { - "value": 13342, - "compare": "<=" - }, - "placeopt__design__instance__count__stdcell": { - "value": 17697, - "compare": "<=" - }, - "detailedplace__design__violations": { - "value": 0, - "compare": "==" - }, - "cts__design__instance__count__setup_buffer": { - "value": 1539, - "compare": "<=" - }, - "cts__design__instance__count__hold_buffer": { - "value": 1539, - "compare": "<=" - }, - "globalroute__antenna_diodes_count": { - "value": 0, - "compare": "<=" - }, - "detailedroute__route__wirelength": { - "value": 284142, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { - "value": 0, - "compare": "<=" - }, - "detailedroute__antenna__violating__nets": { - "value": 0, - "compare": "<=" - }, - "detailedroute__antenna_diodes_count": { - "value": 5, - "compare": "<=" - }, - "finish__timing__setup__ws": { - "value": -1438.04, - "compare": ">=" - }, - "finish__design__instance__area": { - "value": 14676, - "compare": "<=" - }, - "finish__timing__drv__setup_violation_count": { - "value": 2345, - "compare": "<=" - }, - "finish__timing__drv__hold_violation_count": { - "value": 100, - "compare": "<=" - }, - "finish__timing__wns_percent_delay": { - "value": -45.91, - "compare": ">=" - } -} \ No newline at end of file diff --git a/flow/designs/intel16/jpeg/config.mk b/flow/designs/intel16/jpeg/config.mk deleted file mode 100644 index 02f2c58949..0000000000 --- a/flow/designs/intel16/jpeg/config.mk +++ /dev/null @@ -1,15 +0,0 @@ -DESIGN_PDK_HOME := $(realpath $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) - -export DESIGN_NICKNAME = jpeg -export DESIGN_NAME = jpeg_encoder -export PLATFORM = intel16 - -export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = $(DESIGN_DIR)/constraint.sdc - -export CORE_UTILIZATION = 20 -export CORE_ASPECT_RATIO = 1 -export CORE_MARGIN = 2 - -export PLACE_DENSITY = uniform diff --git a/flow/designs/intel16/jpeg/constraint.sdc b/flow/designs/intel16/jpeg/constraint.sdc deleted file mode 100644 index 6200dad94c..0000000000 --- a/flow/designs/intel16/jpeg/constraint.sdc +++ /dev/null @@ -1,10 +0,0 @@ -current_design jpeg_encoder -set clk_name clk -set clk_period 4400 -############################################################################### -# Timing Constraints -############################################################################### -create_clock -name $clk_name -period $clk_period [get_ports {clk}] -# -set_input_delay [expr $clk_period * 0.2] -clock $clk_name [all_inputs] -set_output_delay [expr $clk_period * 0.2] -clock $clk_name [all_outputs] diff --git a/flow/designs/intel16/jpeg/rules-base.json b/flow/designs/intel16/jpeg/rules-base.json deleted file mode 100644 index 350e1a2d75..0000000000 --- a/flow/designs/intel16/jpeg/rules-base.json +++ /dev/null @@ -1,70 +0,0 @@ -{ - "synth__design__instance__area__stdcell": { - "value": 27937.52, - "compare": "<=" - }, - "constraints__clocks__count": { - "value": 1, - "compare": "==" - }, - "placeopt__design__instance__area": { - "value": 46486, - "compare": "<=" - }, - "placeopt__design__instance__count__stdcell": { - "value": 57337, - "compare": "<=" - }, - "detailedplace__design__violations": { - "value": 0, - "compare": "==" - }, - "cts__design__instance__count__setup_buffer": { - "value": 4986, - "compare": "<=" - }, - "cts__design__instance__count__hold_buffer": { - "value": 4986, - "compare": "<=" - }, - "globalroute__antenna_diodes_count": { - "value": 0, - "compare": "<=" - }, - "detailedroute__route__wirelength": { - "value": 1477016, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { - "value": 0, - "compare": "<=" - }, - "detailedroute__antenna__violating__nets": { - "value": 0, - "compare": "<=" - }, - "detailedroute__antenna_diodes_count": { - "value": 5, - "compare": "<=" - }, - "finish__timing__setup__ws": { - "value": -531.17, - "compare": ">=" - }, - "finish__design__instance__area": { - "value": 47945, - "compare": "<=" - }, - "finish__timing__drv__setup_violation_count": { - "value": 2493, - "compare": "<=" - }, - "finish__timing__drv__hold_violation_count": { - "value": 100, - "compare": "<=" - }, - "finish__timing__wns_percent_delay": { - "value": -10.0, - "compare": ">=" - } -} \ No newline at end of file diff --git a/flow/designs/nangate45/aes/config.mk b/flow/designs/nangate45/aes/config.mk index f653445292..7008a46a9f 100644 --- a/flow/designs/nangate45/aes/config.mk +++ b/flow/designs/nangate45/aes/config.mk @@ -11,3 +11,5 @@ export PLACE_DENSITY_LB_ADDON = 0.20 export TNS_END_PERCENT = 100 export REMOVE_CELLS_FOR_EQY = TAPCELL* +# workaround for high congestion in post-grt repair +export SKIP_INCREMENTAL_REPAIR = 1 diff --git a/flow/designs/nangate45/aes/constraint.sdc b/flow/designs/nangate45/aes/constraint.sdc index 6bf0879d5b..95f709e341 100644 --- a/flow/designs/nangate45/aes/constraint.sdc +++ b/flow/designs/nangate45/aes/constraint.sdc @@ -1,15 +1,15 @@ current_design aes_cipher_top -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 0.82 +set clk_period 0.82 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/aes/rules-base.json b/flow/designs/nangate45/aes/rules-base.json index 2c0aede758..65c5fac049 100644 --- a/flow/designs/nangate45/aes/rules-base.json +++ b/flow/designs/nangate45/aes/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 27558, + "value": 26514, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 351027, + "value": 298800, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,11 +48,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.14, + "value": -0.06, "compare": ">=" }, "finish__design__instance__area": { - "value": 30793, + "value": 27064, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -21.31, + "value": -13.22, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/ariane133/config.mk b/flow/designs/nangate45/ariane133/config.mk index 39617c5063..1de1c20457 100644 --- a/flow/designs/nangate45/ariane133/config.mk +++ b/flow/designs/nangate45/ariane133/config.mk @@ -4,12 +4,6 @@ export PLATFORM = nangate45 export SYNTH_HIERARCHICAL = 1 -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 16 -export RTLMP_MIN_MACRO = 4 - export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \ $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v diff --git a/flow/designs/nangate45/ariane133/io.tcl b/flow/designs/nangate45/ariane133/io.tcl index 11444dfcea..cf94350a6c 100644 --- a/flow/designs/nangate45/ariane133/io.tcl +++ b/flow/designs/nangate45/ariane133/io.tcl @@ -1 +1,2 @@ -exclude_io_pin_region -region left:0-500 -region left:1000-1500: -region right:* -region top:* -region bottom:* +exclude_io_pin_region -region left:0-500 -region left:1000-1500: -region right:* \ + -region top:* -region bottom:* diff --git a/flow/designs/nangate45/ariane133/rules-base.json b/flow/designs/nangate45/ariane133/rules-base.json index 199ee80fd2..00369c0887 100644 --- a/flow/designs/nangate45/ariane133/rules-base.json +++ b/flow/designs/nangate45/ariane133/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 872735, + "value": 871517, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 9590764, + "value": 8921456, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.26, + "value": -0.22, "compare": ">=" }, "finish__design__instance__area": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -11.66, + "value": -10.68, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/ariane136/config.mk b/flow/designs/nangate45/ariane136/config.mk index 50b014480b..2832239861 100644 --- a/flow/designs/nangate45/ariane136/config.mk +++ b/flow/designs/nangate45/ariane136/config.mk @@ -5,10 +5,6 @@ export PLATFORM = nangate45 export SYNTH_HIERARCHICAL = 1 # RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 16 -export RTLMP_MIN_MACRO = 4 export RTLMP_SIGNATURE_NET_THRESHOLD = 30 export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \ diff --git a/flow/designs/nangate45/ariane136/constraint.sdc b/flow/designs/nangate45/ariane136/constraint.sdc index e0f4e320df..34dd047647 100644 --- a/flow/designs/nangate45/ariane136/constraint.sdc +++ b/flow/designs/nangate45/ariane136/constraint.sdc @@ -1,496 +1,496 @@ -create_clock [get_ports clk_i] -name core_clock -period 6 -waveform {0 3} -set_input_delay -clock core_clock 0 [get_ports clk_i] -set_input_delay -clock core_clock 0 [get_ports rst_ni] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[63]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[62]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[61]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[60]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[59]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[58]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[57]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[56]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[55]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[54]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[53]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[52]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[51]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[50]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[49]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[48]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[47]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[46]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[45]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[44]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[43]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[42]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[41]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[40]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[39]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[38]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[37]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[36]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[35]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[34]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[33]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[32]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[31]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[30]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[29]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[28]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[27]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[26]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[25]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[24]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[23]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[22]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[21]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[20]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[19]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[18]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[17]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[16]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[15]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[14]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[13]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[12]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[11]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[10]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[9]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[8]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[7]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[6]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[5]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[4]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[3]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[2]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[1]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[0]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[63]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[62]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[61]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[60]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[59]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[58]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[57]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[56]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[55]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[54]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[53]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[52]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[51]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[50]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[49]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[48]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[47]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[46]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[45]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[44]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[43]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[42]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[41]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[40]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[39]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[38]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[37]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[36]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[35]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[34]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[33]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[32]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[31]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[30]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[29]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[28]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[27]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[26]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[25]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[24]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[23]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[22]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[21]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[20]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[19]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[18]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[17]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[16]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[15]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[14]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[13]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[12]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[11]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[10]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[9]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[8]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[7]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[6]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[5]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[4]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[3]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[2]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[1]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[0]}] -set_input_delay -clock core_clock 0 [get_ports {irq_i[1]}] -set_input_delay -clock core_clock 0 [get_ports {irq_i[0]}] -set_input_delay -clock core_clock 0 [get_ports ipi_i] -set_input_delay -clock core_clock 0 [get_ports time_irq_i] -set_input_delay -clock core_clock 0 [get_ports debug_req_i] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[81]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[80]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[79]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[78]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[77]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[76]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[75]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[74]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[73]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[72]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[71]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[70]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[69]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[68]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[67]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[66]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[65]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[64]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[63]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[62]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[61]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[60]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[59]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[58]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[57]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[56]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[55]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[54]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[53]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[52]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[51]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[50]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[49]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[48]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[47]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[46]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[45]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[44]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[43]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[42]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[41]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[40]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[39]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[38]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[37]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[36]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[35]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[34]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[33]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[32]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[31]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[30]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[29]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[28]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[27]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[26]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[25]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[24]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[23]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[22]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[21]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[20]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[19]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[18]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[17]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[16]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[15]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[14]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[13]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[12]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[11]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[10]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[9]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[8]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[7]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[6]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[5]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[4]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[3]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[2]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[1]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[0]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[277]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[276]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[275]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[274]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[273]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[272]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[271]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[270]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[269]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[268]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[267]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[266]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[265]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[264]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[263]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[262]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[261]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[260]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[259]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[258]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[257]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[256]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[255]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[254]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[253]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[252]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[251]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[250]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[249]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[248]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[247]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[246]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[245]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[244]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[243]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[242]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[241]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[240]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[239]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[238]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[237]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[236]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[235]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[234]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[233]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[232]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[231]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[230]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[229]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[228]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[227]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[226]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[225]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[224]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[223]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[222]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[221]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[220]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[219]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[218]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[217]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[216]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[215]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[214]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[213]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[212]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[211]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[210]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[209]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[208]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[207]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[206]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[205]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[204]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[203]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[202]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[201]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[200]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[199]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[198]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[197]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[196]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[195]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[194]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[193]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[192]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[191]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[190]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[189]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[188]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[187]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[186]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[185]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[184]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[183]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[182]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[181]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[180]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[179]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[178]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[177]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[176]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[175]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[174]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[173]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[172]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[171]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[170]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[169]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[168]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[167]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[166]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[165]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[164]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[163]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[162]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[161]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[160]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[159]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[158]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[157]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[156]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[155]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[154]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[153]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[152]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[151]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[150]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[149]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[148]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[147]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[146]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[145]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[144]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[143]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[142]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[141]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[140]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[139]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[138]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[137]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[136]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[135]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[134]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[133]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[132]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[131]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[130]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[129]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[128]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[127]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[126]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[125]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[124]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[123]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[122]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[121]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[120]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[119]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[118]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[117]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[116]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[115]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[114]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[113]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[112]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[111]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[110]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[109]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[108]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[107]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[106]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[105]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[104]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[103]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[102]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[101]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[100]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[99]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[98]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[97]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[96]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[95]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[94]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[93]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[92]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[91]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[90]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[89]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[88]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[87]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[86]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[85]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[84]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[83]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[82]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[81]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[80]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[79]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[78]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[77]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[76]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[75]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[74]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[73]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[72]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[71]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[70]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[69]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[68]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[67]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[66]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[65]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[64]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[63]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[62]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[61]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[60]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[59]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[58]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[57]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[56]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[55]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[54]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[53]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[52]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[51]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[50]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[49]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[48]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[47]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[46]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[45]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[44]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[43]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[42]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[41]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[40]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[39]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[38]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[37]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[36]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[35]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[34]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[33]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[32]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[31]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[30]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[29]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[28]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[27]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[26]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[25]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[24]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[23]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[22]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[21]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[20]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[19]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[18]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[17]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[16]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[15]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[14]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[13]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[12]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[11]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[10]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[9]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[8]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[7]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[6]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[5]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[4]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[3]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[2]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[1]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[0]}] +create_clock [get_ports clk_i] -name core_clock -period 6 -waveform {0 3} +set_input_delay -clock core_clock 0 [get_ports clk_i] +set_input_delay -clock core_clock 0 [get_ports rst_ni] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[63]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[62]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[61]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[60]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[59]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[58]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[57]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[56]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[55]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[54]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[53]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[52]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[51]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[50]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[49]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[48]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[47]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[46]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[45]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[44]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[43]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[42]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[41]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[40]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[39]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[38]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[37]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[36]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[35]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[34]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[33]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[32]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[31]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[30]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[29]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[28]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[27]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[26]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[25]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[24]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[23]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[22]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[21]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[20]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[19]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[18]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[17]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[16]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[15]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[14]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[13]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[12]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[11]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[10]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[9]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[8]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[7]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[6]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[5]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[4]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[3]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[2]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[1]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[0]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[63]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[62]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[61]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[60]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[59]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[58]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[57]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[56]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[55]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[54]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[53]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[52]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[51]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[50]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[49]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[48]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[47]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[46]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[45]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[44]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[43]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[42]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[41]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[40]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[39]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[38]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[37]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[36]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[35]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[34]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[33]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[32]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[31]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[30]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[29]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[28]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[27]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[26]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[25]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[24]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[23]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[22]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[21]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[20]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[19]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[18]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[17]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[16]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[15]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[14]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[13]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[12]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[11]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[10]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[9]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[8]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[7]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[6]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[5]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[4]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[3]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[2]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[1]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[0]}] +set_input_delay -clock core_clock 0 [get_ports {irq_i[1]}] +set_input_delay -clock core_clock 0 [get_ports {irq_i[0]}] +set_input_delay -clock core_clock 0 [get_ports ipi_i] +set_input_delay -clock core_clock 0 [get_ports time_irq_i] +set_input_delay -clock core_clock 0 [get_ports debug_req_i] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[81]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[80]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[79]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[78]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[77]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[76]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[75]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[74]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[73]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[72]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[71]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[70]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[69]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[68]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[67]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[66]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[65]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[64]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[63]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[62]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[61]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[60]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[59]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[58]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[57]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[56]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[55]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[54]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[53]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[52]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[51]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[50]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[49]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[48]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[47]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[46]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[45]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[44]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[43]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[42]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[41]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[40]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[39]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[38]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[37]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[36]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[35]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[34]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[33]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[32]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[31]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[30]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[29]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[28]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[27]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[26]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[25]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[24]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[23]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[22]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[21]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[20]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[19]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[18]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[17]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[16]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[15]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[14]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[13]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[12]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[11]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[10]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[9]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[8]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[7]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[6]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[5]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[4]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[3]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[2]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[1]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[0]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[277]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[276]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[275]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[274]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[273]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[272]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[271]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[270]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[269]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[268]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[267]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[266]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[265]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[264]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[263]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[262]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[261]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[260]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[259]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[258]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[257]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[256]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[255]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[254]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[253]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[252]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[251]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[250]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[249]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[248]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[247]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[246]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[245]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[244]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[243]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[242]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[241]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[240]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[239]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[238]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[237]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[236]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[235]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[234]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[233]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[232]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[231]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[230]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[229]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[228]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[227]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[226]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[225]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[224]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[223]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[222]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[221]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[220]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[219]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[218]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[217]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[216]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[215]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[214]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[213]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[212]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[211]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[210]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[209]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[208]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[207]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[206]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[205]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[204]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[203]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[202]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[201]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[200]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[199]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[198]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[197]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[196]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[195]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[194]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[193]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[192]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[191]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[190]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[189]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[188]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[187]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[186]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[185]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[184]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[183]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[182]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[181]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[180]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[179]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[178]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[177]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[176]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[175]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[174]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[173]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[172]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[171]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[170]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[169]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[168]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[167]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[166]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[165]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[164]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[163]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[162]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[161]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[160]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[159]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[158]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[157]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[156]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[155]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[154]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[153]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[152]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[151]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[150]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[149]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[148]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[147]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[146]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[145]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[144]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[143]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[142]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[141]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[140]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[139]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[138]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[137]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[136]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[135]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[134]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[133]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[132]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[131]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[130]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[129]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[128]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[127]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[126]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[125]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[124]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[123]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[122]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[121]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[120]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[119]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[118]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[117]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[116]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[115]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[114]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[113]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[112]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[111]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[110]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[109]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[108]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[107]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[106]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[105]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[104]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[103]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[102]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[101]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[100]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[99]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[98]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[97]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[96]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[95]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[94]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[93]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[92]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[91]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[90]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[89]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[88]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[87]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[86]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[85]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[84]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[83]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[82]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[81]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[80]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[79]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[78]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[77]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[76]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[75]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[74]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[73]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[72]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[71]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[70]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[69]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[68]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[67]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[66]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[65]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[64]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[63]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[62]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[61]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[60]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[59]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[58]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[57]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[56]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[55]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[54]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[53]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[52]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[51]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[50]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[49]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[48]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[47]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[46]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[45]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[44]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[43]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[42]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[41]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[40]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[39]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[38]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[37]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[36]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[35]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[34]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[33]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[32]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[31]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[30]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[29]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[28]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[27]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[26]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[25]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[24]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[23]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[22]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[21]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[20]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[19]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[18]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[17]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[16]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[15]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[14]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[13]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[12]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[11]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[10]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[9]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[8]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[7]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[6]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[5]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[4]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[3]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[2]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[1]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[0]}] diff --git a/flow/designs/nangate45/ariane136/io.tcl b/flow/designs/nangate45/ariane136/io.tcl index 11444dfcea..4de8dc3e2a 100644 --- a/flow/designs/nangate45/ariane136/io.tcl +++ b/flow/designs/nangate45/ariane136/io.tcl @@ -1 +1,6 @@ -exclude_io_pin_region -region left:0-500 -region left:1000-1500: -region right:* -region top:* -region bottom:* +exclude_io_pin_region \ + -region left:0-500 \ + -region left:1000-1500: \ + -region right:* \ + -region top:* \ + -region bottom:* diff --git a/flow/designs/nangate45/ariane136/rules-base.json b/flow/designs/nangate45/ariane136/rules-base.json index 3b363296ad..d692880787 100644 --- a/flow/designs/nangate45/ariane136/rules-base.json +++ b/flow/designs/nangate45/ariane136/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 897767, + "value": 889812, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 9221377, + "value": 8032745, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -52,7 +52,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 904162, + "value": 902506, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 299, + "value": 292, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/nangate45/black_parrot/config.mk b/flow/designs/nangate45/black_parrot/config.mk index 9f823b5b74..bdf35d8289 100644 --- a/flow/designs/nangate45/black_parrot/config.mk +++ b/flow/designs/nangate45/black_parrot/config.mk @@ -4,11 +4,6 @@ export PLATFORM = nangate45 export SYNTH_HIERARCHICAL = 1 # -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 12 -export RTLMP_MIN_MACRO = 4 export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v diff --git a/flow/designs/nangate45/black_parrot/constraint.sdc b/flow/designs/nangate45/black_parrot/constraint.sdc index d6a53ebbd8..a5514ffe49 100644 --- a/flow/designs/nangate45/black_parrot/constraint.sdc +++ b/flow/designs/nangate45/black_parrot/constraint.sdc @@ -1,4 +1,4 @@ -set clk_name CLK +set clk_name CLK set clk_port_name clk_i set clk_period 6.0 set clk_io_pct 0.2 @@ -9,2397 +9,2397 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set_input_delay -clock CLK -max 3.42 [get_ports reset_i] -set_input_delay -clock CLK -min $min_arrival [get_ports reset_i] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_cmd_yumi_i[0]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_yumi_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_yumi_i[0]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_yumi_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[54]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[54]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[53]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[53]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[52]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[52]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[51]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[51]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[50]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[50]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[49]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[49]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[48]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[48]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[47]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[47]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[46]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[46]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[45]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[45]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[44]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[44]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[43]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[43]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[42]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[42]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[41]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[41]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[40]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[40]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[39]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[39]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[38]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[38]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[37]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[37]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[36]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[36]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[35]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[35]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[34]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[34]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[33]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[33]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[32]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[32]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[31]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[31]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[30]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[30]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[29]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[29]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[28]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[28]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[27]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[27]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[26]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[26]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[25]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[25]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[24]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[24]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[23]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[23]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[22]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[22]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[21]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[21]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[20]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[20]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[19]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[19]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[18]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[18]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[17]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[17]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[16]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[16]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[15]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[15]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[14]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[14]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[13]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[13]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[12]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[12]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[11]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[11]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[10]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[10]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[9]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[9]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[8]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[8]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[7]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[7]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[6]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[6]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[5]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[5]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[4]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[4]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[3]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[3]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[2]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[2]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[1]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[1]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[0]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_v_i[0]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_v_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[538]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[538]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[537]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[537]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[536]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[536]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[535]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[535]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[534]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[534]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[533]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[533]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[532]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[532]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[531]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[531]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[530]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[530]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[529]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[529]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[528]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[528]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[527]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[527]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[526]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[526]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[525]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[525]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[524]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[524]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[523]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[523]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[522]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[522]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[521]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[521]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[520]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[520]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[519]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[519]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[518]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[518]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[517]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[517]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[516]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[516]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[515]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[515]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[514]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[514]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[513]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[513]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[512]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[512]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[511]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[511]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[510]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[510]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[509]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[509]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[508]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[508]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[507]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[507]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[506]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[506]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[505]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[505]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[504]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[504]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[503]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[503]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[502]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[502]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[501]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[501]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[500]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[500]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[499]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[499]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[498]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[498]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[497]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[497]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[496]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[496]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[495]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[495]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[494]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[494]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[493]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[493]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[492]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[492]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[491]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[491]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[490]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[490]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[489]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[489]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[488]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[488]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[487]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[487]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[486]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[486]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[485]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[485]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[484]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[484]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[483]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[483]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[482]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[482]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[481]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[481]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[480]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[480]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[479]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[479]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[478]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[478]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[477]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[477]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[476]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[476]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[475]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[475]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[474]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[474]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[473]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[473]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[472]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[472]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[471]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[471]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[470]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[470]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[469]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[469]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[468]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[468]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[467]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[467]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[466]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[466]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[465]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[465]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[464]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[464]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[463]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[463]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[462]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[462]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[461]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[461]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[460]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[460]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[459]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[459]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[458]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[458]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[457]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[457]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[456]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[456]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[455]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[455]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[454]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[454]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[453]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[453]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[452]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[452]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[451]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[451]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[450]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[450]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[449]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[449]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[448]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[448]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[447]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[447]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[446]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[446]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[445]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[445]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[444]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[444]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[443]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[443]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[442]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[442]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[441]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[441]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[440]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[440]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[439]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[439]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[438]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[438]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[437]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[437]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[436]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[436]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[435]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[435]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[434]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[434]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[433]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[433]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[432]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[432]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[431]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[431]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[430]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[430]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[429]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[429]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[428]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[428]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[427]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[427]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[426]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[426]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[425]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[425]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[424]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[424]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[423]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[423]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[422]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[422]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[421]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[421]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[420]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[420]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[419]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[419]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[418]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[418]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[417]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[417]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[416]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[416]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[415]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[415]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[414]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[414]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[413]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[413]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[412]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[412]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[411]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[411]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[410]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[410]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[409]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[409]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[408]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[408]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[407]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[407]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[406]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[406]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[405]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[405]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[404]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[404]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[403]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[403]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[402]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[402]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[401]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[401]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[400]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[400]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[399]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[399]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[398]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[398]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[397]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[397]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[396]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[396]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[395]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[395]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[394]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[394]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[393]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[393]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[392]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[392]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[391]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[391]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[390]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[390]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[389]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[389]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[388]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[388]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[387]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[387]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[386]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[386]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[385]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[385]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[384]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[384]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[383]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[383]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[382]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[382]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[381]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[381]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[380]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[380]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[379]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[379]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[378]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[378]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[377]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[377]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[376]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[376]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[375]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[375]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[374]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[374]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[373]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[373]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[372]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[372]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[371]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[371]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[370]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[370]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[369]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[369]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[368]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[368]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[367]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[367]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[366]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[366]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[365]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[365]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[364]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[364]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[363]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[363]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[362]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[362]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[361]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[361]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[360]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[360]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[359]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[359]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[358]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[358]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[357]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[357]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[356]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[356]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[355]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[355]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[354]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[354]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[353]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[353]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[352]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[352]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[351]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[351]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[350]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[350]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[349]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[349]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[348]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[348]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[347]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[347]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[346]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[346]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[345]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[345]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[344]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[344]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[343]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[343]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[342]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[342]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[341]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[341]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[340]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[340]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[339]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[339]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[338]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[338]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[337]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[337]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[336]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[336]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[335]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[335]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[334]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[334]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[333]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[333]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[332]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[332]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[331]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[331]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[330]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[330]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[329]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[329]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[328]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[328]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[327]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[327]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[326]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[326]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[325]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[325]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[324]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[324]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[323]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[323]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[322]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[322]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[321]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[321]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[320]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[320]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[319]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[319]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[318]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[318]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[317]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[317]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[316]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[316]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[315]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[315]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[314]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[314]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[313]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[313]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[312]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[312]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[311]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[311]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[310]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[310]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[309]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[309]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[308]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[308]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[307]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[307]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[306]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[306]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[305]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[305]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[304]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[304]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[303]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[303]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[302]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[302]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[301]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[301]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[300]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[300]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[299]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[299]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[298]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[298]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[297]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[297]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[296]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[296]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[295]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[295]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[294]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[294]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[293]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[293]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[292]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[292]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[291]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[291]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[290]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[290]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[289]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[289]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[288]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[288]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[287]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[287]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[286]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[286]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[285]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[285]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[284]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[284]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[283]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[283]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[282]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[282]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[281]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[281]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[280]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[280]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[279]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[279]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[278]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[278]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[277]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[277]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[276]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[276]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[275]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[275]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[274]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[274]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[273]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[273]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[272]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[272]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[271]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[271]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[270]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[270]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[269]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[269]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[268]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[268]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[267]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[267]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[266]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[266]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[265]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[265]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[264]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[264]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[263]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[263]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[262]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[262]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[261]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[261]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[260]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[260]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[259]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[259]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[258]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[258]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[257]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[257]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[256]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[256]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[255]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[255]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[254]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[254]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[253]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[253]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[252]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[252]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[251]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[251]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[250]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[250]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[249]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[249]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[248]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[248]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[247]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[247]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[246]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[246]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[245]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[245]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[244]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[244]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[243]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[243]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[242]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[242]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[241]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[241]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[240]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[240]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[239]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[239]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[238]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[238]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[237]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[237]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[236]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[236]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[235]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[235]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[234]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[234]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[233]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[233]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[232]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[232]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[231]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[231]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[230]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[230]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[229]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[229]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[228]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[228]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[227]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[227]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[226]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[226]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[225]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[225]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[224]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[224]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[223]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[223]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[222]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[222]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[221]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[221]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[220]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[220]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[219]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[219]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[218]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[218]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[217]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[217]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[216]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[216]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[215]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[215]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[214]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[214]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[213]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[213]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[212]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[212]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[211]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[211]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[210]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[210]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[209]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[209]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[208]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[208]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[207]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[207]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[206]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[206]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[205]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[205]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[204]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[204]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[203]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[203]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[202]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[202]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[201]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[201]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[200]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[200]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[199]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[199]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[198]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[198]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[197]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[197]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[196]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[196]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[195]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[195]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[194]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[194]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[193]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[193]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[192]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[192]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[191]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[191]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[190]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[190]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[189]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[189]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[188]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[188]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[187]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[187]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[186]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[186]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[185]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[185]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[184]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[184]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[183]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[183]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[182]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[182]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[181]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[181]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[180]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[180]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[179]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[179]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[178]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[178]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[177]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[177]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[176]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[176]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[175]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[175]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[174]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[174]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[173]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[173]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[172]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[172]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[171]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[171]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[170]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[170]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[169]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[169]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[168]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[168]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[167]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[167]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[166]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[166]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[165]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[165]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[164]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[164]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[163]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[163]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[162]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[162]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[161]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[161]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[160]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[160]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[159]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[159]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[158]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[158]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[157]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[157]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[156]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[156]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[155]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[155]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[154]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[154]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[153]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[153]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[152]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[152]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[151]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[151]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[150]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[150]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[149]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[149]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[148]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[148]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[147]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[147]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[146]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[146]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[145]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[145]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[144]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[144]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[143]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[143]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[142]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[142]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[141]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[141]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[140]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[140]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[139]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[139]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[138]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[138]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[137]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[137]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[136]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[136]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[135]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[135]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[134]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[134]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[133]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[133]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[132]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[132]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[131]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[131]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[130]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[130]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[129]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[129]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[128]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[128]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[127]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[127]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[126]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[126]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[125]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[125]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[124]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[124]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[123]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[123]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[122]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[122]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[121]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[121]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[120]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[120]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[119]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[119]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[118]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[118]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[117]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[117]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[116]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[116]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[115]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[115]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[114]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[114]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[113]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[113]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[112]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[112]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[111]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[111]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[110]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[110]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[109]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[109]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[108]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[108]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[107]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[107]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[106]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[106]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[105]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[105]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[104]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[104]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[103]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[103]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[102]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[102]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[101]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[101]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[100]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[100]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[99]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[99]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[98]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[98]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[97]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[97]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[96]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[96]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[95]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[95]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[94]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[94]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[93]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[93]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[92]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[92]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[91]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[91]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[90]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[90]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[89]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[89]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[88]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[88]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[87]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[87]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[86]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[86]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[85]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[85]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[84]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[84]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[83]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[83]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[82]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[82]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[81]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[81]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[80]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[80]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[79]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[79]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[78]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[78]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[77]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[77]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[76]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[76]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[75]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[75]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[74]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[74]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[73]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[73]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[72]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[72]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[71]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[71]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[70]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[70]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[69]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[69]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[68]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[68]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[67]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[67]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[66]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[66]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[65]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[65]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[64]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[64]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[63]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[63]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[62]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[62]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[61]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[61]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[60]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[60]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[59]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[59]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[58]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[58]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[57]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[57]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[56]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[56]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[55]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[55]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[54]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[54]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[53]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[53]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[52]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[52]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[51]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[51]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[50]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[50]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[49]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[49]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[48]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[48]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[47]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[47]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[46]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[46]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[45]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[45]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[44]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[44]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[43]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[43]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[42]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[42]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[41]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[41]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[40]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[40]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[39]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[39]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[38]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[38]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[37]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[37]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[36]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[36]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[35]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[35]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[34]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[34]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[33]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[33]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[32]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[32]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[31]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[31]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[30]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[30]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[29]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[29]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[28]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[28]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[27]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[27]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[26]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[26]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[25]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[25]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[24]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[24]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[23]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[23]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[22]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[22]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[21]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[21]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[20]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[20]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[19]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[19]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[18]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[18]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[17]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[17]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[16]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[16]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[15]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[15]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[14]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[14]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[13]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[13]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[12]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[12]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[11]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[11]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[10]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[10]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[9]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[9]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[8]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[8]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[7]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[7]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[6]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[6]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[5]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[5]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[4]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[4]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[3]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[3]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[2]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[2]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[1]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[1]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[0]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_v_i[0]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_v_i[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[26]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[26]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[25]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[25]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[24]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[24]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[23]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[23]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[22]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[22]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[21]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[21]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[20]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[20]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[19]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[19]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[18]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[18]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[17]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[17]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[16]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[16]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[15]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[15]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[14]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[14]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[13]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[13]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[12]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[12]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[11]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[11]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[10]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[10]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[9]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[9]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[8]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[8]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[7]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[7]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[6]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[6]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[5]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[5]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[4]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[4]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[3]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[3]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[2]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[2]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[1]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[1]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[0]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_v_o[0]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_v_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[566]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[566]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[565]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[565]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[564]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[564]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[563]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[563]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[562]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[562]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[561]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[561]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[560]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[560]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[559]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[559]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[558]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[558]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[557]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[557]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[556]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[556]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[555]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[555]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[554]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[554]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[553]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[553]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[552]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[552]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[551]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[551]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[550]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[550]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[549]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[549]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[548]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[548]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[547]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[547]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[546]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[546]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[545]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[545]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[544]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[544]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[543]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[543]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[542]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[542]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[541]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[541]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[540]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[540]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[539]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[539]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[538]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[538]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[537]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[537]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[536]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[536]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[535]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[535]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[534]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[534]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[533]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[533]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[532]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[532]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[531]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[531]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[530]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[530]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[529]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[529]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[528]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[528]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[527]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[527]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[526]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[526]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[525]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[525]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[524]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[524]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[523]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[523]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[522]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[522]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[521]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[521]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[520]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[520]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[519]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[519]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[518]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[518]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[517]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[517]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[516]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[516]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[515]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[515]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[514]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[514]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[513]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[513]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[512]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[512]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[511]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[511]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[510]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[510]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[509]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[509]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[508]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[508]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[507]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[507]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[506]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[506]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[505]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[505]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[504]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[504]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[503]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[503]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[502]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[502]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[501]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[501]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[500]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[500]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[499]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[499]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[498]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[498]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[497]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[497]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[496]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[496]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[495]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[495]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[494]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[494]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[493]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[493]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[492]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[492]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[491]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[491]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[490]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[490]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[489]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[489]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[488]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[488]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[487]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[487]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[486]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[486]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[485]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[485]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[484]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[484]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[483]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[483]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[482]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[482]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[481]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[481]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[480]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[480]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[479]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[479]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[478]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[478]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[477]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[477]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[476]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[476]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[475]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[475]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[474]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[474]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[473]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[473]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[472]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[472]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[471]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[471]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[470]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[470]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[469]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[469]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[468]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[468]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[467]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[467]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[466]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[466]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[465]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[465]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[464]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[464]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[463]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[463]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[462]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[462]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[461]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[461]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[460]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[460]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[459]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[459]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[458]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[458]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[457]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[457]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[456]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[456]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[455]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[455]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[454]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[454]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[453]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[453]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[452]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[452]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[451]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[451]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[450]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[450]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[449]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[449]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[448]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[448]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[447]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[447]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[446]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[446]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[445]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[445]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[444]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[444]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[443]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[443]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[442]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[442]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[441]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[441]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[440]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[440]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[439]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[439]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[438]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[438]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[437]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[437]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[436]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[436]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[435]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[435]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[434]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[434]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[433]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[433]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[432]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[432]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[431]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[431]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[430]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[430]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[429]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[429]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[428]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[428]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[427]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[427]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[426]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[426]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[425]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[425]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[424]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[424]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[423]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[423]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[422]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[422]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[421]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[421]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[420]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[420]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[419]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[419]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[418]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[418]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[417]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[417]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[416]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[416]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[415]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[415]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[414]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[414]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[413]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[413]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[412]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[412]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[411]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[411]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[410]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[410]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[409]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[409]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[408]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[408]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[407]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[407]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[406]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[406]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[405]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[405]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[404]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[404]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[403]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[403]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[402]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[402]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[401]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[401]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[400]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[400]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[399]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[399]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[398]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[398]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[397]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[397]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[396]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[396]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[395]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[395]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[394]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[394]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[393]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[393]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[392]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[392]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[391]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[391]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[390]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[390]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[389]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[389]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[388]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[388]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[387]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[387]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[386]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[386]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[385]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[385]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[384]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[384]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[383]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[383]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[382]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[382]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[381]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[381]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[380]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[380]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[379]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[379]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[378]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[378]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[377]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[377]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[376]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[376]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[375]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[375]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[374]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[374]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[373]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[373]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[372]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[372]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[371]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[371]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[370]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[370]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[369]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[369]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[368]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[368]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[367]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[367]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[366]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[366]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[365]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[365]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[364]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[364]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[363]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[363]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[362]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[362]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[361]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[361]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[360]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[360]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[359]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[359]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[358]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[358]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[357]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[357]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[356]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[356]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[355]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[355]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[354]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[354]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[353]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[353]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[352]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[352]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[351]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[351]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[350]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[350]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[349]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[349]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[348]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[348]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[347]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[347]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[346]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[346]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[345]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[345]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[344]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[344]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[343]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[343]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[342]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[342]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[341]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[341]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[340]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[340]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[339]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[339]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[338]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[338]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[337]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[337]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[336]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[336]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[335]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[335]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[334]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[334]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[333]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[333]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[332]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[332]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[331]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[331]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[330]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[330]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[329]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[329]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[328]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[328]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[327]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[327]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[326]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[326]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[325]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[325]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[324]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[324]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[323]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[323]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[322]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[322]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[321]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[321]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[320]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[320]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[319]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[319]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[318]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[318]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[317]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[317]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[316]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[316]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[315]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[315]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[314]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[314]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[313]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[313]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[312]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[312]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[311]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[311]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[310]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[310]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[309]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[309]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[308]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[308]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[307]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[307]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[306]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[306]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[305]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[305]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[304]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[304]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[303]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[303]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[302]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[302]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[301]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[301]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[300]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[300]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[299]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[299]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[298]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[298]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[297]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[297]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[296]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[296]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[295]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[295]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[294]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[294]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[293]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[293]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[292]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[292]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[291]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[291]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[290]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[290]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[289]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[289]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[288]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[288]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[287]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[287]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[286]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[286]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[285]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[285]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[284]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[284]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[283]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[283]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[282]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[282]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[281]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[281]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[280]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[280]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[279]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[279]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[278]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[278]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[277]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[277]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[276]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[276]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[275]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[275]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[274]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[274]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[273]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[273]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[272]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[272]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[271]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[271]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[270]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[270]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[269]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[269]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[268]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[268]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[267]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[267]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[266]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[266]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[265]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[265]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[264]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[264]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[263]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[263]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[262]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[262]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[261]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[261]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[260]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[260]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[259]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[259]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[258]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[258]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[257]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[257]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[256]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[256]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[255]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[255]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[254]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[254]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[253]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[253]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[252]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[252]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[251]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[251]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[250]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[250]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[249]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[249]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[248]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[248]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[247]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[247]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[246]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[246]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[245]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[245]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[244]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[244]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[243]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[243]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[242]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[242]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[241]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[241]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[240]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[240]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[239]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[239]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[238]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[238]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[237]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[237]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[236]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[236]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[235]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[235]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[234]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[234]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[233]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[233]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[232]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[232]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[231]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[231]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[230]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[230]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[229]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[229]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[228]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[228]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[227]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[227]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[226]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[226]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[225]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[225]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[224]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[224]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[223]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[223]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[222]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[222]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[221]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[221]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[220]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[220]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[219]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[219]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[218]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[218]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[217]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[217]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[216]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[216]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[215]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[215]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[214]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[214]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[213]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[213]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[212]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[212]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[211]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[211]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[210]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[210]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[209]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[209]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[208]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[208]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[207]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[207]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[206]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[206]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[205]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[205]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[204]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[204]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[203]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[203]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[202]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[202]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[201]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[201]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[200]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[200]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[199]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[199]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[198]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[198]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[197]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[197]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[196]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[196]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[195]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[195]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[194]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[194]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[193]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[193]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[192]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[192]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[191]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[191]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[190]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[190]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[189]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[189]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[188]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[188]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[187]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[187]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[186]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[186]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[185]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[185]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[184]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[184]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[183]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[183]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[182]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[182]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[181]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[181]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[180]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[180]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[179]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[179]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[178]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[178]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[177]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[177]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[176]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[176]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[175]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[175]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[174]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[174]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[173]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[173]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[172]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[172]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[171]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[171]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[170]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[170]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[169]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[169]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[168]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[168]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[167]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[167]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[166]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[166]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[165]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[165]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[164]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[164]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[163]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[163]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[162]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[162]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[161]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[161]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[160]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[160]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[159]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[159]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[158]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[158]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[157]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[157]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[156]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[156]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[155]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[155]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[154]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[154]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[153]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[153]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[152]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[152]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[151]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[151]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[150]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[150]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[149]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[149]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[148]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[148]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[147]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[147]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[146]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[146]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[145]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[145]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[144]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[144]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[143]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[143]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[142]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[142]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[141]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[141]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[140]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[140]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[139]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[139]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[138]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[138]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[137]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[137]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[136]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[136]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[135]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[135]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[134]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[134]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[133]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[133]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[132]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[132]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[131]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[131]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[130]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[130]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[129]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[129]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[128]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[128]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[127]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[127]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[126]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[126]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[125]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[125]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[124]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[124]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[123]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[123]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[122]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[122]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[121]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[121]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[120]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[120]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[119]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[119]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[118]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[118]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[117]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[117]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[116]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[116]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[115]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[115]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[114]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[114]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[113]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[113]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[112]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[112]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[111]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[111]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[110]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[110]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[109]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[109]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[108]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[108]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[107]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[107]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[106]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[106]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[105]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[105]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[104]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[104]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[103]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[103]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[102]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[102]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[101]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[101]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[100]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[100]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[99]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[99]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[98]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[98]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[97]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[97]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[96]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[96]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[95]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[95]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[94]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[94]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[93]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[93]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[92]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[92]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[91]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[91]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[90]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[90]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[89]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[89]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[88]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[88]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[87]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[87]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[86]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[86]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[85]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[85]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[84]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[84]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[83]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[83]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[82]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[82]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[81]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[81]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[80]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[80]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[79]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[79]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[78]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[78]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[77]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[77]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[76]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[76]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[75]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[75]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[74]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[74]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[73]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[73]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[72]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[72]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[71]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[71]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[70]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[70]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[69]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[69]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[68]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[68]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[67]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[67]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[66]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[66]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[65]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[65]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[64]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[64]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[63]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[63]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[62]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[62]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[61]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[61]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[60]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[60]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[59]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[59]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[58]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[58]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[57]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[57]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[56]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[56]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[55]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[55]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[54]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[54]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[53]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[53]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[52]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[52]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[51]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[51]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[50]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[50]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[49]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[49]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[48]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[48]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[47]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[47]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[46]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[46]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[45]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[45]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[44]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[44]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[43]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[43]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[42]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[42]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[41]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[41]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[40]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[40]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[39]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[39]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[38]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[38]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[37]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[37]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[36]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[36]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[35]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[35]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[34]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[34]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[33]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[33]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[32]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[32]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[31]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[31]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[30]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[30]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[29]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[29]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[28]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[28]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[27]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[27]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[26]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[26]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[25]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[25]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[24]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[24]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[23]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[23]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[22]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[22]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[21]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[21]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[20]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[20]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[19]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[19]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[18]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[18]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[17]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[17]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[16]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[16]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[15]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[15]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[14]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[14]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[13]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[13]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[12]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[12]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[11]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[11]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[10]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[10]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[9]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[9]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[8]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[8]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[7]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[7]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[6]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[6]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[5]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[5]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[4]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[4]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[3]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[3]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[2]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[2]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[1]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[1]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[0]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_v_o[0]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_v_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_resp_ready_o[0]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_resp_ready_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_ready_o[0]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_ready_o[0]}] +set_input_delay -clock CLK -max 3.42 [get_ports reset_i] +set_input_delay -clock CLK -min $min_arrival [get_ports reset_i] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_cmd_yumi_i[0]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_yumi_i[0]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_yumi_i[0]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_yumi_i[0]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[54]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[54]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[53]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[53]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[52]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[52]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[51]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[51]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[50]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[50]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[49]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[49]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[48]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[48]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[47]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[47]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[46]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[46]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[45]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[45]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[44]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[44]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[43]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[43]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[42]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[42]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[41]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[41]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[40]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[40]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[39]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[39]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[38]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[38]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[37]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[37]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[36]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[36]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[35]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[35]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[34]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[34]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[33]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[33]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[32]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[32]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[31]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[31]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[30]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[30]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[29]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[29]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[28]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[28]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[27]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[27]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[26]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[26]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[25]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[25]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[24]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[24]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[23]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[23]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[22]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[22]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[21]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[21]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[20]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[20]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[19]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[19]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[18]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[18]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[17]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[17]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[16]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[16]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[15]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[15]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[14]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[14]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[13]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[13]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[12]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[12]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[11]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[11]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[10]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[10]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[9]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[9]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[8]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[8]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[7]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[7]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[6]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[6]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[5]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[5]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[4]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[4]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[3]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[3]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[2]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[2]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[1]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[1]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[0]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[0]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_v_i[0]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_v_i[0]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[538]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[538]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[537]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[537]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[536]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[536]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[535]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[535]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[534]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[534]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[533]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[533]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[532]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[532]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[531]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[531]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[530]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[530]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[529]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[529]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[528]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[528]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[527]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[527]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[526]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[526]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[525]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[525]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[524]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[524]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[523]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[523]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[522]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[522]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[521]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[521]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[520]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[520]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[519]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[519]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[518]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[518]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[517]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[517]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[516]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[516]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[515]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[515]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[514]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[514]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[513]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[513]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[512]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[512]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[511]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[511]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[510]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[510]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[509]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[509]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[508]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[508]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[507]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[507]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[506]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[506]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[505]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[505]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[504]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[504]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[503]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[503]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[502]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[502]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[501]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[501]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[500]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[500]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[499]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[499]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[498]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[498]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[497]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[497]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[496]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[496]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[495]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[495]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[494]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[494]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[493]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[493]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[492]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[492]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[491]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[491]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[490]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[490]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[489]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[489]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[488]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[488]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[487]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[487]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[486]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[486]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[485]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[485]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[484]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[484]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[483]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[483]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[482]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[482]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[481]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[481]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[480]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[480]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[479]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[479]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[478]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[478]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[477]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[477]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[476]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[476]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[475]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[475]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[474]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[474]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[473]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[473]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[472]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[472]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[471]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[471]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[470]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[470]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[469]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[469]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[468]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[468]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[467]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[467]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[466]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[466]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[465]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[465]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[464]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[464]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[463]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[463]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[462]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[462]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[461]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[461]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[460]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[460]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[459]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[459]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[458]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[458]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[457]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[457]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[456]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[456]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[455]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[455]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[454]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[454]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[453]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[453]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[452]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[452]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[451]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[451]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[450]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[450]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[449]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[449]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[448]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[448]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[447]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[447]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[446]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[446]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[445]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[445]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[444]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[444]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[443]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[443]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[442]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[442]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[441]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[441]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[440]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[440]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[439]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[439]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[438]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[438]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[437]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[437]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[436]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[436]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[435]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[435]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[434]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[434]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[433]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[433]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[432]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[432]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[431]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[431]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[430]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[430]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[429]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[429]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[428]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[428]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[427]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[427]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[426]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[426]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[425]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[425]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[424]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[424]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[423]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[423]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[422]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[422]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[421]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[421]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[420]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[420]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[419]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[419]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[418]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[418]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[417]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[417]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[416]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[416]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[415]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[415]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[414]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[414]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[413]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[413]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[412]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[412]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[411]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[411]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[410]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[410]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[409]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[409]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[408]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[408]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[407]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[407]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[406]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[406]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[405]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[405]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[404]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[404]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[403]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[403]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[402]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[402]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[401]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[401]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[400]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[400]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[399]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[399]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[398]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[398]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[397]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[397]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[396]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[396]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[395]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[395]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[394]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[394]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[393]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[393]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[392]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[392]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[391]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[391]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[390]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[390]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[389]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[389]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[388]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[388]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[387]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[387]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[386]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[386]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[385]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[385]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[384]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[384]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[383]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[383]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[382]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[382]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[381]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[381]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[380]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[380]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[379]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[379]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[378]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[378]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[377]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[377]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[376]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[376]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[375]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[375]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[374]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[374]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[373]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[373]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[372]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[372]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[371]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[371]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[370]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[370]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[369]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[369]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[368]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[368]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[367]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[367]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[366]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[366]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[365]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[365]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[364]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[364]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[363]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[363]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[362]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[362]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[361]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[361]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[360]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[360]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[359]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[359]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[358]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[358]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[357]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[357]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[356]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[356]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[355]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[355]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[354]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[354]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[353]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[353]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[352]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[352]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[351]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[351]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[350]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[350]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[349]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[349]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[348]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[348]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[347]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[347]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[346]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[346]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[345]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[345]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[344]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[344]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[343]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[343]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[342]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[342]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[341]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[341]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[340]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[340]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[339]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[339]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[338]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[338]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[337]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[337]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[336]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[336]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[335]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[335]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[334]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[334]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[333]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[333]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[332]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[332]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[331]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[331]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[330]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[330]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[329]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[329]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[328]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[328]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[327]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[327]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[326]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[326]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[325]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[325]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[324]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[324]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[323]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[323]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[322]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[322]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[321]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[321]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[320]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[320]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[319]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[319]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[318]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[318]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[317]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[317]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[316]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[316]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[315]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[315]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[314]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[314]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[313]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[313]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[312]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[312]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[311]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[311]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[310]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[310]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[309]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[309]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[308]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[308]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[307]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[307]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[306]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[306]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[305]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[305]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[304]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[304]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[303]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[303]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[302]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[302]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[301]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[301]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[300]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[300]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[299]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[299]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[298]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[298]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[297]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[297]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[296]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[296]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[295]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[295]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[294]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[294]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[293]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[293]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[292]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[292]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[291]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[291]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[290]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[290]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[289]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[289]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[288]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[288]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[287]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[287]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[286]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[286]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[285]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[285]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[284]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[284]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[283]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[283]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[282]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[282]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[281]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[281]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[280]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[280]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[279]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[279]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[278]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[278]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[277]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[277]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[276]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[276]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[275]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[275]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[274]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[274]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[273]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[273]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[272]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[272]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[271]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[271]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[270]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[270]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[269]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[269]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[268]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[268]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[267]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[267]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[266]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[266]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[265]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[265]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[264]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[264]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[263]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[263]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[262]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[262]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[261]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[261]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[260]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[260]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[259]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[259]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[258]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[258]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[257]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[257]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[256]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[256]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[255]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[255]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[254]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[254]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[253]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[253]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[252]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[252]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[251]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[251]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[250]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[250]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[249]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[249]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[248]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[248]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[247]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[247]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[246]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[246]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[245]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[245]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[244]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[244]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[243]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[243]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[242]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[242]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[241]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[241]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[240]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[240]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[239]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[239]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[238]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[238]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[237]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[237]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[236]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[236]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[235]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[235]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[234]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[234]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[233]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[233]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[232]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[232]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[231]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[231]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[230]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[230]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[229]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[229]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[228]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[228]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[227]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[227]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[226]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[226]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[225]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[225]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[224]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[224]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[223]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[223]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[222]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[222]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[221]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[221]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[220]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[220]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[219]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[219]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[218]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[218]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[217]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[217]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[216]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[216]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[215]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[215]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[214]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[214]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[213]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[213]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[212]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[212]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[211]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[211]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[210]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[210]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[209]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[209]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[208]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[208]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[207]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[207]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[206]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[206]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[205]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[205]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[204]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[204]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[203]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[203]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[202]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[202]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[201]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[201]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[200]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[200]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[199]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[199]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[198]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[198]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[197]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[197]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[196]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[196]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[195]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[195]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[194]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[194]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[193]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[193]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[192]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[192]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[191]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[191]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[190]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[190]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[189]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[189]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[188]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[188]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[187]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[187]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[186]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[186]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[185]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[185]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[184]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[184]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[183]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[183]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[182]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[182]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[181]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[181]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[180]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[180]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[179]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[179]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[178]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[178]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[177]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[177]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[176]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[176]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[175]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[175]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[174]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[174]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[173]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[173]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[172]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[172]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[171]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[171]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[170]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[170]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[169]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[169]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[168]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[168]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[167]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[167]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[166]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[166]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[165]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[165]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[164]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[164]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[163]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[163]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[162]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[162]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[161]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[161]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[160]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[160]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[159]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[159]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[158]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[158]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[157]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[157]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[156]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[156]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[155]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[155]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[154]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[154]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[153]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[153]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[152]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[152]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[151]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[151]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[150]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[150]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[149]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[149]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[148]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[148]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[147]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[147]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[146]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[146]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[145]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[145]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[144]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[144]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[143]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[143]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[142]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[142]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[141]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[141]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[140]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[140]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[139]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[139]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[138]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[138]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[137]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[137]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[136]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[136]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[135]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[135]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[134]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[134]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[133]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[133]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[132]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[132]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[131]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[131]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[130]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[130]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[129]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[129]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[128]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[128]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[127]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[127]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[126]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[126]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[125]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[125]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[124]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[124]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[123]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[123]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[122]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[122]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[121]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[121]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[120]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[120]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[119]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[119]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[118]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[118]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[117]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[117]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[116]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[116]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[115]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[115]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[114]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[114]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[113]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[113]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[112]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[112]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[111]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[111]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[110]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[110]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[109]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[109]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[108]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[108]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[107]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[107]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[106]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[106]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[105]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[105]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[104]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[104]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[103]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[103]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[102]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[102]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[101]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[101]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[100]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[100]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[99]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[99]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[98]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[98]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[97]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[97]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[96]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[96]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[95]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[95]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[94]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[94]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[93]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[93]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[92]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[92]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[91]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[91]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[90]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[90]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[89]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[89]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[88]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[88]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[87]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[87]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[86]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[86]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[85]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[85]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[84]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[84]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[83]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[83]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[82]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[82]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[81]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[81]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[80]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[80]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[79]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[79]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[78]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[78]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[77]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[77]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[76]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[76]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[75]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[75]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[74]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[74]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[73]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[73]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[72]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[72]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[71]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[71]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[70]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[70]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[69]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[69]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[68]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[68]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[67]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[67]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[66]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[66]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[65]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[65]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[64]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[64]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[63]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[63]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[62]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[62]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[61]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[61]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[60]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[60]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[59]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[59]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[58]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[58]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[57]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[57]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[56]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[56]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[55]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[55]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[54]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[54]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[53]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[53]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[52]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[52]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[51]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[51]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[50]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[50]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[49]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[49]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[48]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[48]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[47]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[47]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[46]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[46]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[45]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[45]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[44]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[44]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[43]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[43]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[42]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[42]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[41]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[41]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[40]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[40]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[39]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[39]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[38]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[38]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[37]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[37]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[36]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[36]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[35]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[35]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[34]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[34]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[33]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[33]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[32]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[32]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[31]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[31]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[30]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[30]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[29]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[29]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[28]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[28]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[27]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[27]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[26]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[26]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[25]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[25]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[24]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[24]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[23]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[23]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[22]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[22]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[21]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[21]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[20]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[20]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[19]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[19]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[18]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[18]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[17]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[17]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[16]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[16]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[15]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[15]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[14]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[14]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[13]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[13]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[12]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[12]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[11]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[11]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[10]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[10]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[9]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[9]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[8]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[8]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[7]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[7]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[6]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[6]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[5]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[5]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[4]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[4]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[3]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[3]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[2]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[2]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[1]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[1]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[0]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[0]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_v_i[0]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_v_i[0]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[26]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[26]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[25]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[25]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[24]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[24]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[23]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[23]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[22]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[22]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[21]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[21]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[20]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[20]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[19]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[19]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[18]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[18]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[17]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[17]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[16]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[16]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[15]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[15]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[14]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[14]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[13]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[13]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[12]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[12]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[11]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[11]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[10]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[10]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[9]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[9]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[8]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[8]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[7]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[7]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[6]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[6]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[5]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[5]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[4]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[4]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[3]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[3]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[2]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[2]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[1]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[1]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[0]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[0]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_v_o[0]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_v_o[0]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[566]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[566]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[565]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[565]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[564]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[564]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[563]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[563]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[562]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[562]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[561]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[561]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[560]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[560]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[559]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[559]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[558]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[558]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[557]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[557]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[556]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[556]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[555]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[555]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[554]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[554]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[553]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[553]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[552]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[552]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[551]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[551]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[550]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[550]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[549]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[549]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[548]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[548]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[547]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[547]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[546]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[546]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[545]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[545]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[544]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[544]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[543]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[543]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[542]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[542]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[541]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[541]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[540]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[540]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[539]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[539]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[538]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[538]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[537]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[537]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[536]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[536]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[535]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[535]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[534]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[534]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[533]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[533]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[532]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[532]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[531]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[531]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[530]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[530]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[529]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[529]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[528]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[528]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[527]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[527]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[526]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[526]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[525]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[525]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[524]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[524]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[523]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[523]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[522]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[522]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[521]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[521]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[520]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[520]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[519]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[519]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[518]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[518]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[517]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[517]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[516]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[516]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[515]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[515]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[514]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[514]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[513]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[513]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[512]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[512]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[511]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[511]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[510]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[510]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[509]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[509]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[508]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[508]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[507]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[507]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[506]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[506]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[505]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[505]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[504]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[504]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[503]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[503]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[502]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[502]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[501]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[501]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[500]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[500]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[499]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[499]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[498]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[498]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[497]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[497]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[496]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[496]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[495]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[495]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[494]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[494]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[493]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[493]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[492]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[492]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[491]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[491]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[490]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[490]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[489]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[489]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[488]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[488]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[487]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[487]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[486]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[486]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[485]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[485]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[484]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[484]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[483]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[483]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[482]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[482]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[481]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[481]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[480]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[480]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[479]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[479]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[478]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[478]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[477]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[477]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[476]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[476]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[475]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[475]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[474]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[474]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[473]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[473]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[472]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[472]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[471]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[471]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[470]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[470]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[469]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[469]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[468]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[468]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[467]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[467]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[466]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[466]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[465]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[465]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[464]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[464]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[463]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[463]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[462]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[462]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[461]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[461]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[460]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[460]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[459]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[459]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[458]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[458]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[457]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[457]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[456]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[456]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[455]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[455]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[454]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[454]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[453]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[453]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[452]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[452]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[451]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[451]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[450]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[450]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[449]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[449]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[448]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[448]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[447]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[447]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[446]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[446]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[445]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[445]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[444]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[444]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[443]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[443]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[442]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[442]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[441]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[441]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[440]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[440]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[439]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[439]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[438]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[438]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[437]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[437]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[436]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[436]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[435]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[435]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[434]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[434]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[433]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[433]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[432]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[432]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[431]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[431]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[430]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[430]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[429]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[429]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[428]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[428]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[427]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[427]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[426]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[426]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[425]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[425]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[424]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[424]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[423]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[423]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[422]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[422]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[421]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[421]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[420]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[420]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[419]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[419]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[418]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[418]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[417]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[417]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[416]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[416]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[415]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[415]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[414]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[414]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[413]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[413]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[412]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[412]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[411]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[411]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[410]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[410]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[409]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[409]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[408]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[408]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[407]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[407]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[406]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[406]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[405]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[405]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[404]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[404]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[403]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[403]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[402]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[402]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[401]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[401]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[400]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[400]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[399]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[399]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[398]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[398]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[397]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[397]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[396]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[396]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[395]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[395]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[394]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[394]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[393]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[393]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[392]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[392]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[391]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[391]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[390]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[390]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[389]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[389]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[388]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[388]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[387]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[387]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[386]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[386]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[385]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[385]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[384]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[384]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[383]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[383]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[382]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[382]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[381]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[381]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[380]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[380]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[379]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[379]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[378]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[378]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[377]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[377]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[376]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[376]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[375]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[375]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[374]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[374]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[373]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[373]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[372]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[372]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[371]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[371]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[370]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[370]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[369]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[369]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[368]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[368]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[367]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[367]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[366]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[366]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[365]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[365]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[364]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[364]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[363]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[363]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[362]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[362]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[361]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[361]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[360]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[360]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[359]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[359]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[358]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[358]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[357]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[357]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[356]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[356]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[355]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[355]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[354]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[354]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[353]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[353]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[352]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[352]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[351]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[351]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[350]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[350]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[349]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[349]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[348]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[348]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[347]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[347]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[346]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[346]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[345]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[345]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[344]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[344]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[343]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[343]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[342]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[342]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[341]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[341]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[340]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[340]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[339]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[339]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[338]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[338]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[337]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[337]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[336]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[336]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[335]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[335]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[334]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[334]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[333]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[333]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[332]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[332]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[331]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[331]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[330]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[330]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[329]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[329]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[328]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[328]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[327]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[327]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[326]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[326]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[325]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[325]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[324]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[324]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[323]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[323]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[322]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[322]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[321]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[321]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[320]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[320]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[319]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[319]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[318]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[318]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[317]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[317]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[316]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[316]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[315]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[315]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[314]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[314]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[313]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[313]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[312]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[312]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[311]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[311]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[310]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[310]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[309]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[309]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[308]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[308]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[307]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[307]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[306]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[306]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[305]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[305]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[304]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[304]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[303]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[303]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[302]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[302]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[301]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[301]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[300]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[300]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[299]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[299]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[298]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[298]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[297]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[297]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[296]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[296]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[295]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[295]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[294]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[294]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[293]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[293]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[292]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[292]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[291]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[291]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[290]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[290]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[289]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[289]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[288]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[288]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[287]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[287]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[286]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[286]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[285]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[285]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[284]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[284]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[283]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[283]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[282]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[282]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[281]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[281]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[280]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[280]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[279]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[279]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[278]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[278]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[277]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[277]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[276]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[276]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[275]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[275]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[274]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[274]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[273]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[273]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[272]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[272]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[271]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[271]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[270]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[270]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[269]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[269]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[268]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[268]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[267]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[267]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[266]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[266]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[265]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[265]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[264]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[264]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[263]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[263]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[262]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[262]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[261]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[261]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[260]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[260]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[259]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[259]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[258]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[258]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[257]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[257]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[256]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[256]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[255]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[255]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[254]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[254]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[253]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[253]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[252]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[252]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[251]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[251]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[250]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[250]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[249]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[249]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[248]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[248]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[247]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[247]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[246]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[246]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[245]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[245]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[244]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[244]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[243]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[243]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[242]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[242]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[241]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[241]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[240]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[240]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[239]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[239]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[238]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[238]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[237]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[237]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[236]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[236]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[235]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[235]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[234]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[234]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[233]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[233]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[232]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[232]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[231]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[231]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[230]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[230]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[229]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[229]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[228]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[228]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[227]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[227]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[226]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[226]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[225]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[225]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[224]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[224]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[223]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[223]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[222]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[222]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[221]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[221]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[220]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[220]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[219]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[219]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[218]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[218]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[217]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[217]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[216]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[216]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[215]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[215]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[214]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[214]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[213]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[213]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[212]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[212]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[211]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[211]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[210]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[210]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[209]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[209]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[208]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[208]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[207]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[207]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[206]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[206]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[205]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[205]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[204]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[204]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[203]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[203]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[202]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[202]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[201]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[201]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[200]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[200]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[199]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[199]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[198]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[198]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[197]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[197]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[196]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[196]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[195]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[195]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[194]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[194]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[193]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[193]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[192]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[192]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[191]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[191]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[190]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[190]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[189]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[189]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[188]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[188]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[187]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[187]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[186]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[186]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[185]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[185]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[184]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[184]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[183]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[183]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[182]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[182]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[181]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[181]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[180]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[180]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[179]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[179]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[178]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[178]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[177]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[177]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[176]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[176]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[175]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[175]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[174]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[174]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[173]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[173]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[172]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[172]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[171]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[171]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[170]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[170]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[169]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[169]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[168]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[168]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[167]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[167]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[166]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[166]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[165]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[165]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[164]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[164]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[163]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[163]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[162]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[162]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[161]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[161]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[160]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[160]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[159]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[159]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[158]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[158]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[157]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[157]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[156]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[156]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[155]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[155]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[154]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[154]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[153]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[153]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[152]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[152]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[151]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[151]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[150]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[150]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[149]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[149]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[148]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[148]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[147]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[147]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[146]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[146]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[145]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[145]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[144]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[144]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[143]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[143]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[142]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[142]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[141]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[141]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[140]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[140]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[139]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[139]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[138]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[138]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[137]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[137]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[136]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[136]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[135]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[135]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[134]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[134]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[133]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[133]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[132]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[132]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[131]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[131]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[130]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[130]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[129]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[129]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[128]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[128]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[127]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[127]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[126]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[126]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[125]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[125]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[124]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[124]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[123]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[123]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[122]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[122]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[121]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[121]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[120]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[120]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[119]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[119]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[118]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[118]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[117]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[117]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[116]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[116]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[115]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[115]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[114]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[114]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[113]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[113]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[112]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[112]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[111]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[111]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[110]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[110]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[109]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[109]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[108]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[108]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[107]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[107]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[106]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[106]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[105]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[105]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[104]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[104]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[103]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[103]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[102]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[102]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[101]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[101]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[100]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[100]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[99]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[99]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[98]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[98]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[97]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[97]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[96]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[96]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[95]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[95]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[94]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[94]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[93]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[93]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[92]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[92]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[91]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[91]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[90]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[90]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[89]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[89]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[88]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[88]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[87]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[87]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[86]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[86]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[85]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[85]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[84]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[84]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[83]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[83]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[82]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[82]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[81]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[81]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[80]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[80]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[79]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[79]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[78]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[78]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[77]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[77]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[76]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[76]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[75]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[75]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[74]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[74]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[73]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[73]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[72]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[72]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[71]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[71]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[70]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[70]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[69]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[69]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[68]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[68]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[67]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[67]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[66]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[66]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[65]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[65]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[64]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[64]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[63]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[63]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[62]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[62]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[61]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[61]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[60]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[60]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[59]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[59]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[58]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[58]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[57]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[57]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[56]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[56]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[55]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[55]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[54]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[54]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[53]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[53]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[52]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[52]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[51]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[51]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[50]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[50]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[49]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[49]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[48]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[48]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[47]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[47]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[46]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[46]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[45]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[45]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[44]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[44]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[43]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[43]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[42]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[42]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[41]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[41]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[40]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[40]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[39]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[39]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[38]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[38]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[37]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[37]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[36]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[36]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[35]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[35]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[34]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[34]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[33]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[33]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[32]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[32]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[31]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[31]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[30]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[30]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[29]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[29]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[28]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[28]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[27]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[27]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[26]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[26]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[25]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[25]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[24]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[24]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[23]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[23]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[22]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[22]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[21]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[21]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[20]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[20]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[19]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[19]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[18]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[18]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[17]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[17]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[16]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[16]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[15]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[15]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[14]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[14]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[13]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[13]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[12]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[12]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[11]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[11]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[10]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[10]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[9]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[9]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[8]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[8]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[7]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[7]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[6]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[6]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[5]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[5]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[4]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[4]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[3]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[3]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[2]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[2]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[1]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[1]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[0]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[0]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_v_o[0]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_v_o[0]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_resp_ready_o[0]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_resp_ready_o[0]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_ready_o[0]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_ready_o[0]}] diff --git a/flow/designs/nangate45/black_parrot/io.tcl b/flow/designs/nangate45/black_parrot/io.tcl index 0204afcc11..9df7874f57 100644 --- a/flow/designs/nangate45/black_parrot/io.tcl +++ b/flow/designs/nangate45/black_parrot/io.tcl @@ -1 +1,2 @@ -exclude_io_pin_region -region left:* -region right:* -region top:* -region bottom:0-100 -region bottom:1200-1350 +exclude_io_pin_region -region left:* -region right:* -region top:* \ + -region bottom:0-100 -region bottom:1200-1350 diff --git a/flow/designs/nangate45/black_parrot/rules-base.json b/flow/designs/nangate45/black_parrot/rules-base.json index 6a7a83aedf..2ff95a60b1 100644 --- a/flow/designs/nangate45/black_parrot/rules-base.json +++ b/flow/designs/nangate45/black_parrot/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 778508.16, + "value": 778458.91, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 857876, + "value": 816555, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 299688, + "value": 280905, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 26060, + "value": 24426, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 26060, + "value": 24426, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 10420028, + "value": 7165555, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,19 +48,19 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -3.63, + "value": -3.58, "compare": ">=" }, "finish__design__instance__area": { - "value": 870913, + "value": 832384, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 13030, + "value": 12213, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 429, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/nangate45/bp_be_top/constraint.sdc b/flow/designs/nangate45/bp_be_top/constraint.sdc index 632222055a..3df6fe408f 100644 --- a/flow/designs/nangate45/bp_be_top/constraint.sdc +++ b/flow/designs/nangate45/bp_be_top/constraint.sdc @@ -1,6058 +1,6057 @@ - -create_clock [get_ports clk_i] -name CLK -period 2.6 -waveform {0 1.3} -set_input_delay -clock CLK -max 0.6 [get_ports reset_i] -set_input_delay -clock CLK -min 0.6 [get_ports reset_i] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[133]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[133]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[132]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[132]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[131]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[131]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[130]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[130]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[129]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[129]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[128]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[128]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[127]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[127]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[126]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[126]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[125]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[125]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[124]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[124]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[123]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[123]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[122]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[122]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[121]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[121]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[120]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[120]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[119]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[119]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[118]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[118]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[117]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[117]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[116]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[116]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[115]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[115]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[114]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[114]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[113]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[113]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[112]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[112]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[111]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[111]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[110]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[110]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[109]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[109]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[108]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[108]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[107]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[107]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[106]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[106]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[105]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[105]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[104]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[104]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[103]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[103]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[102]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[102]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[101]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[101]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[100]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[100]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[99]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[99]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[98]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[98]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[97]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[97]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[96]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[96]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[95]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[95]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[94]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[94]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[93]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[93]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[92]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[92]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[91]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[91]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[90]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[90]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[89]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[89]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[88]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[88]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[87]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[87]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[86]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[86]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[85]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[85]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[84]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[84]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[83]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[83]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[82]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[82]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[81]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[81]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[80]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[80]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[79]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[79]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[78]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[78]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[77]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[77]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[76]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[76]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[75]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[75]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[74]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[74]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[73]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[73]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[72]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[72]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[71]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[71]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[70]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[70]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[69]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[69]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[68]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[68]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[67]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[67]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[66]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[66]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[65]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[65]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[64]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[64]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[63]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[63]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[62]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[62]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[61]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[61]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[60]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[60]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[59]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[59]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[58]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[58]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[57]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[57]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[56]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[56]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[55]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[55]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[54]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[54]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[53]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[53]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[52]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[52]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[51]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[51]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[50]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[50]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[49]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[49]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[48]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[48]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[47]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[47]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[46]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[46]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[45]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[45]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[44]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[44]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[43]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[43]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[42]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[42]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[41]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[41]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[40]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[40]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[39]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[39]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[38]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[38]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[37]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[37]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[36]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[36]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[35]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[34]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[33]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[32]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[31]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[30]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[29]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[28]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[27]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[26]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[25]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[24]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[23]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[22]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[21]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[20]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[19]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[18]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[17]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[16]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[15]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[14]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[13]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[12]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[11]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[10]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[9]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[8]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[7]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[6]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[5]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[4]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[3]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[0]}] -set_input_delay -clock CLK -max 0.6 [get_ports fe_queue_v_i] -set_input_delay -clock CLK -min 0.6 [get_ports fe_queue_v_i] -set_input_delay -clock CLK -max 0.6 [get_ports fe_cmd_ready_i] -set_input_delay -clock CLK -min 0.6 [get_ports fe_cmd_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports lce_req_ready_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_req_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports lce_resp_ready_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_resp_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports lce_data_resp_ready_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_data_resp_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[35]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[34]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[33]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[32]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[31]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[30]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[29]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[28]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[27]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[26]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[25]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[24]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[23]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[22]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[21]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[20]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[19]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[18]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[17]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[16]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[15]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[14]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[13]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[12]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[11]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[10]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[9]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[8]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[7]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[6]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[5]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[4]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[3]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[0]}] -set_input_delay -clock CLK -max 0.6 [get_ports lce_cmd_v_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_cmd_v_i] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[539]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[539]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[538]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[538]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[537]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[537]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[536]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[536]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[535]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[535]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[534]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[534]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[533]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[533]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[532]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[532]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[531]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[531]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[530]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[530]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[529]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[529]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[528]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[528]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[527]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[527]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[526]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[526]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[525]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[525]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[524]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[524]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[523]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[523]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[522]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[522]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[521]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[521]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[520]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[520]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[519]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[519]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[518]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[518]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[517]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[517]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[516]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[516]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[515]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[515]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[514]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[514]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[513]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[513]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[512]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[512]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[511]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[511]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[510]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[510]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[509]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[509]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[508]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[508]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[507]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[507]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[506]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[506]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[505]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[505]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[504]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[504]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[503]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[503]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[502]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[502]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[501]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[501]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[500]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[500]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[499]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[499]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[498]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[498]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[497]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[497]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[496]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[496]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[495]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[495]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[494]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[494]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[493]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[493]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[492]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[492]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[491]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[491]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[490]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[490]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[489]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[489]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[488]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[488]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[487]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[487]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[486]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[486]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[485]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[485]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[484]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[484]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[483]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[483]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[482]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[482]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[481]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[481]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[480]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[480]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[479]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[479]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[478]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[478]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[477]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[477]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[476]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[476]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[475]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[475]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[474]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[474]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[473]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[473]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[472]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[472]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[471]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[471]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[470]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[470]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[469]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[469]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[468]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[468]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[467]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[467]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[466]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[466]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[465]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[465]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[464]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[464]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[463]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[463]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[462]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[462]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[461]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[461]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[460]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[460]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[459]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[459]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[458]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[458]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[457]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[457]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[456]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[456]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[455]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[455]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[454]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[454]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[453]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[453]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[452]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[452]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[451]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[451]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[450]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[450]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[449]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[449]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[448]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[448]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[447]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[447]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[446]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[446]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[445]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[445]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[444]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[444]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[443]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[443]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[442]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[442]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[441]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[441]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[440]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[440]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[439]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[439]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[438]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[438]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[437]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[437]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[436]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[436]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[435]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[435]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[434]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[434]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[433]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[433]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[432]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[432]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[431]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[431]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[430]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[430]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[429]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[429]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[428]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[428]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[427]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[427]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[426]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[426]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[425]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[425]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[424]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[424]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[423]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[423]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[422]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[422]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[421]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[421]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[420]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[420]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[419]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[419]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[418]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[418]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[417]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[417]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[416]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[416]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[415]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[415]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[414]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[414]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[413]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[413]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[412]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[412]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[411]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[411]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[410]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[410]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[409]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[409]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[408]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[408]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[407]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[407]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[406]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[406]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[405]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[405]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[404]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[404]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[403]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[403]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[402]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[402]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[401]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[401]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[400]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[400]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[399]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[399]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[398]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[398]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[397]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[397]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[396]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[396]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[395]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[395]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[394]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[394]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[393]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[393]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[392]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[392]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[391]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[391]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[390]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[390]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[389]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[389]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[388]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[388]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[387]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[387]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[386]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[386]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[385]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[385]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[384]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[384]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[383]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[383]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[382]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[382]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[381]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[381]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[380]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[380]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[379]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[379]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[378]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[378]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[377]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[377]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[376]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[376]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[375]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[375]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[374]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[374]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[373]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[373]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[372]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[372]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[371]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[371]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[370]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[370]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[369]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[369]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[368]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[368]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[367]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[367]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[366]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[366]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[365]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[365]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[364]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[364]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[363]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[363]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[362]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[362]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[361]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[361]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[360]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[360]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[359]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[359]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[358]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[358]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[357]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[357]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[356]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[356]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[355]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[355]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[354]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[354]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[353]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[353]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[352]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[352]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[351]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[351]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[350]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[350]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[349]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[349]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[348]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[348]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[347]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[347]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[346]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[346]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[345]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[345]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[344]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[344]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[343]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[343]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[342]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[342]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[341]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[341]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[340]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[340]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[339]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[339]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[338]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[338]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[337]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[337]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[336]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[336]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[335]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[335]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[334]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[334]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[333]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[333]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[332]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[332]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[331]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[331]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[330]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[330]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[329]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[329]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[328]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[328]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[327]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[327]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[326]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[326]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[325]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[325]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[324]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[324]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[323]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[323]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[322]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[322]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[321]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[321]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[320]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[320]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[319]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[319]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[318]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[318]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[317]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[317]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[316]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[316]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[315]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[315]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[314]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[314]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[313]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[313]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[312]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[312]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[311]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[311]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[310]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[310]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[309]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[309]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[308]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[308]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[307]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[307]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[306]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[306]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[305]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[305]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[304]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[304]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[303]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[303]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[302]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[302]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[301]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[301]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[300]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[300]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[299]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[299]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[298]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[298]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[297]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[297]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[296]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[296]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[295]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[295]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[294]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[294]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[293]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[293]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[292]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[292]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[291]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[291]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[290]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[290]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[289]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[289]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[288]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[288]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[287]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[287]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[286]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[286]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[285]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[285]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[284]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[284]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[283]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[283]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[282]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[282]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[281]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[281]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[280]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[280]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[279]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[279]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[278]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[278]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[277]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[277]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[276]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[276]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[275]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[275]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[274]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[274]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[273]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[273]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[272]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[272]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[271]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[271]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[270]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[270]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[269]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[269]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[268]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[268]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[267]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[267]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[266]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[266]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[265]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[265]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[264]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[264]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[263]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[263]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[262]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[262]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[261]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[261]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[260]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[260]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[259]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[259]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[258]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[258]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[257]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[257]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[256]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[256]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[255]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[255]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[254]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[254]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[253]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[253]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[252]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[252]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[251]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[251]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[250]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[250]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[249]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[249]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[248]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[248]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[247]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[247]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[246]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[246]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[245]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[245]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[244]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[244]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[243]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[243]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[242]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[242]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[241]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[241]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[240]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[240]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[239]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[239]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[238]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[238]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[237]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[237]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[236]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[236]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[235]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[235]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[234]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[234]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[233]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[233]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[232]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[232]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[231]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[231]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[230]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[230]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[229]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[229]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[228]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[228]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[227]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[227]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[226]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[226]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[225]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[225]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[224]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[224]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[223]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[223]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[222]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[222]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[221]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[221]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[220]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[220]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[219]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[219]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[218]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[218]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[217]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[217]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[216]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[216]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[215]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[215]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[214]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[214]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[213]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[213]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[212]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[212]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[211]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[211]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[210]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[210]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[209]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[209]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[208]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[208]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[207]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[207]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[206]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[206]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[205]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[205]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[204]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[204]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[203]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[203]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[202]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[202]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[201]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[201]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[200]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[200]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[199]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[199]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[198]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[198]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[197]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[197]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[196]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[196]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[195]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[195]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[194]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[194]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[193]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[193]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[192]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[192]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[191]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[191]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[190]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[190]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[189]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[189]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[188]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[188]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[187]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[187]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[186]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[186]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[185]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[185]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[184]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[184]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[183]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[183]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[182]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[182]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[181]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[181]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[180]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[180]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[179]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[179]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[178]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[178]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[177]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[177]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[176]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[176]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[175]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[175]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[174]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[174]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[173]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[173]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[172]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[172]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[171]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[171]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[170]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[170]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[169]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[169]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[168]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[168]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[167]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[167]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[166]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[166]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[165]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[165]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[164]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[164]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[163]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[163]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[162]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[162]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[161]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[161]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[160]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[160]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[159]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[159]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[158]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[158]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[157]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[157]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[156]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[156]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[155]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[155]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[154]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[154]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[153]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[153]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[152]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[152]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[151]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[151]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[150]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[150]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[149]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[149]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[148]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[148]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[147]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[147]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[146]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[146]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[145]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[145]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[144]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[144]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[143]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[143]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[142]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[142]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[141]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[141]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[140]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[140]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[139]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[139]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[138]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[138]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[137]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[137]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[136]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[136]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[135]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[135]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[134]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[134]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[133]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[133]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[132]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[132]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[131]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[131]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[130]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[130]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[129]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[129]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[128]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[128]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[127]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[127]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[126]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[126]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[125]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[125]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[124]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[124]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[123]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[123]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[122]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[122]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[121]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[121]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[120]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[120]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[119]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[119]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[118]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[118]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[117]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[117]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[116]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[116]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[115]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[115]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[114]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[114]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[113]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[113]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[112]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[112]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[111]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[111]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[110]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[110]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[109]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[109]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[108]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[108]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[107]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[107]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[106]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[106]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[105]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[105]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[104]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[104]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[103]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[103]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[102]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[102]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[101]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[101]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[100]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[100]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[99]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[99]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[98]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[98]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[97]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[97]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[96]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[96]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[95]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[95]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[94]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[94]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[93]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[93]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[92]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[92]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[91]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[91]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[90]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[90]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[89]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[89]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[88]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[88]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[87]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[87]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[86]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[86]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[85]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[85]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[84]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[84]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[83]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[83]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[82]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[82]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[81]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[81]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[80]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[80]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[79]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[79]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[78]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[78]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[77]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[77]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[76]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[76]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[75]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[75]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[74]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[74]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[73]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[73]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[72]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[72]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[71]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[71]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[70]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[70]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[69]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[69]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[68]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[68]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[67]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[67]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[66]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[66]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[65]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[65]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[64]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[64]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[63]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[63]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[62]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[62]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[61]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[61]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[60]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[60]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[59]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[59]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[58]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[58]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[57]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[57]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[56]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[56]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[55]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[55]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[54]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[54]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[53]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[53]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[52]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[52]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[51]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[51]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[50]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[50]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[49]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[49]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[48]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[48]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[47]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[47]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[46]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[46]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[45]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[45]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[44]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[44]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[43]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[43]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[42]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[42]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[41]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[41]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[40]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[40]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[39]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[39]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[38]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[38]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[37]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[37]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[36]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[36]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[35]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[34]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[33]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[32]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[31]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[30]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[29]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[28]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[27]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[26]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[25]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[24]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[23]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[22]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[21]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[20]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[19]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[18]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[17]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[16]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[15]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[14]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[13]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[12]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[11]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[10]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[9]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[8]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[7]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[6]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[5]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[4]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[3]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[0]}] -set_input_delay -clock CLK -max 0.6 [get_ports lce_data_cmd_v_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_data_cmd_v_i] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[538]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[538]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[537]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[537]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[536]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[536]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[535]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[535]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[534]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[534]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[533]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[533]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[532]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[532]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[531]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[531]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[530]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[530]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[529]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[529]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[528]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[528]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[527]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[527]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[526]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[526]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[525]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[525]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[524]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[524]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[523]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[523]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[522]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[522]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[521]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[521]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[520]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[520]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[519]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[519]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[518]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[518]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[517]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[517]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[516]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[516]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[515]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[515]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[514]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[514]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[513]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[513]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[512]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[512]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[511]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[511]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[510]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[510]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[509]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[509]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[508]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[508]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[507]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[507]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[506]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[506]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[505]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[505]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[504]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[504]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[503]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[503]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[502]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[502]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[501]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[501]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[500]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[500]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[499]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[499]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[498]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[498]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[497]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[497]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[496]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[496]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[495]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[495]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[494]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[494]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[493]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[493]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[492]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[492]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[491]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[491]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[490]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[490]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[489]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[489]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[488]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[488]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[487]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[487]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[486]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[486]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[485]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[485]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[484]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[484]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[483]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[483]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[482]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[482]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[481]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[481]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[480]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[480]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[479]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[479]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[478]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[478]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[477]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[477]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[476]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[476]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[475]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[475]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[474]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[474]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[473]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[473]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[472]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[472]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[471]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[471]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[470]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[470]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[469]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[469]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[468]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[468]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[467]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[467]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[466]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[466]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[465]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[465]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[464]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[464]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[463]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[463]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[462]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[462]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[461]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[461]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[460]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[460]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[459]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[459]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[458]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[458]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[457]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[457]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[456]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[456]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[455]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[455]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[454]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[454]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[453]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[453]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[452]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[452]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[451]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[451]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[450]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[450]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[449]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[449]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[448]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[448]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[447]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[447]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[446]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[446]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[445]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[445]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[444]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[444]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[443]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[443]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[442]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[442]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[441]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[441]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[440]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[440]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[439]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[439]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[438]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[438]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[437]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[437]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[436]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[436]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[435]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[435]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[434]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[434]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[433]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[433]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[432]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[432]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[431]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[431]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[430]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[430]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[429]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[429]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[428]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[428]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[427]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[427]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[426]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[426]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[425]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[425]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[424]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[424]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[423]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[423]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[422]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[422]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[421]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[421]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[420]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[420]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[419]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[419]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[418]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[418]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[417]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[417]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[416]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[416]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[415]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[415]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[414]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[414]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[413]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[413]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[412]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[412]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[411]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[411]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[410]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[410]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[409]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[409]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[408]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[408]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[407]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[407]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[406]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[406]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[405]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[405]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[404]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[404]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[403]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[403]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[402]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[402]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[401]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[401]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[400]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[400]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[399]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[399]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[398]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[398]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[397]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[397]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[396]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[396]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[395]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[395]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[394]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[394]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[393]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[393]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[392]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[392]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[391]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[391]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[390]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[390]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[389]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[389]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[388]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[388]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[387]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[387]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[386]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[386]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[385]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[385]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[384]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[384]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[383]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[383]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[382]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[382]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[381]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[381]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[380]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[380]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[379]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[379]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[378]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[378]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[377]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[377]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[376]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[376]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[375]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[375]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[374]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[374]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[373]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[373]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[372]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[372]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[371]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[371]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[370]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[370]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[369]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[369]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[368]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[368]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[367]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[367]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[366]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[366]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[365]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[365]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[364]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[364]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[363]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[363]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[362]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[362]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[361]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[361]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[360]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[360]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[359]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[359]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[358]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[358]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[357]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[357]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[356]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[356]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[355]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[355]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[354]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[354]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[353]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[353]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[352]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[352]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[351]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[351]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[350]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[350]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[349]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[349]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[348]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[348]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[347]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[347]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[346]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[346]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[345]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[345]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[344]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[344]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[343]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[343]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[342]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[342]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[341]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[341]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[340]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[340]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[339]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[339]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[338]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[338]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[337]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[337]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[336]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[336]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[335]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[335]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[334]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[334]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[333]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[333]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[332]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[332]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[331]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[331]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[330]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[330]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[329]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[329]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[328]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[328]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[327]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[327]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[326]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[326]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[325]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[325]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[324]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[324]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[323]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[323]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[322]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[322]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[321]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[321]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[320]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[320]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[319]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[319]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[318]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[318]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[317]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[317]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[316]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[316]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[315]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[315]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[314]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[314]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[313]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[313]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[312]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[312]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[311]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[311]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[310]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[310]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[309]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[309]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[308]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[308]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[307]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[307]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[306]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[306]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[305]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[305]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[304]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[304]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[303]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[303]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[302]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[302]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[301]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[301]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[300]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[300]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[299]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[299]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[298]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[298]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[297]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[297]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[296]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[296]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[295]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[295]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[294]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[294]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[293]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[293]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[292]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[292]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[291]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[291]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[290]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[290]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[289]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[289]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[288]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[288]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[287]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[287]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[286]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[286]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[285]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[285]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[284]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[284]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[283]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[283]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[282]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[282]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[281]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[281]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[280]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[280]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[279]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[279]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[278]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[278]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[277]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[277]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[276]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[276]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[275]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[275]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[274]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[274]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[273]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[273]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[272]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[272]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[271]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[271]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[270]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[270]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[269]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[269]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[268]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[268]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[267]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[267]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[266]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[266]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[265]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[265]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[264]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[264]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[263]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[263]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[262]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[262]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[261]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[261]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[260]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[260]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[259]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[259]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[258]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[258]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[257]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[257]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[256]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[256]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[255]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[255]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[254]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[254]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[253]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[253]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[252]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[252]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[251]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[251]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[250]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[250]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[249]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[249]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[248]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[248]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[247]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[247]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[246]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[246]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[245]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[245]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[244]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[244]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[243]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[243]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[242]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[242]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[241]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[241]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[240]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[240]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[239]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[239]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[238]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[238]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[237]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[237]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[236]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[236]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[235]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[235]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[234]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[234]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[233]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[233]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[232]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[232]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[231]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[231]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[230]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[230]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[229]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[229]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[228]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[228]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[227]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[227]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[226]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[226]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[225]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[225]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[224]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[224]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[223]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[223]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[222]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[222]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[221]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[221]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[220]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[220]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[219]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[219]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[218]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[218]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[217]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[217]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[216]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[216]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[215]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[215]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[214]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[214]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[213]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[213]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[212]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[212]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[211]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[211]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[210]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[210]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[209]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[209]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[208]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[208]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[207]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[207]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[206]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[206]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[205]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[205]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[204]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[204]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[203]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[203]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[202]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[202]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[201]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[201]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[200]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[200]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[199]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[199]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[198]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[198]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[197]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[197]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[196]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[196]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[195]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[195]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[194]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[194]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[193]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[193]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[192]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[192]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[191]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[191]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[190]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[190]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[189]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[189]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[188]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[188]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[187]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[187]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[186]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[186]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[185]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[185]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[184]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[184]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[183]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[183]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[182]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[182]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[181]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[181]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[180]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[180]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[179]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[179]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[178]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[178]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[177]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[177]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[176]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[176]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[175]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[175]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[174]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[174]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[173]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[173]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[172]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[172]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[171]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[171]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[170]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[170]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[169]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[169]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[168]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[168]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[167]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[167]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[166]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[166]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[165]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[165]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[164]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[164]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[163]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[163]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[162]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[162]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[161]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[161]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[160]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[160]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[159]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[159]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[158]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[158]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[157]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[157]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[156]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[156]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[155]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[155]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[154]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[154]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[153]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[153]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[152]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[152]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[151]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[151]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[150]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[150]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[149]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[149]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[148]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[148]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[147]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[147]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[146]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[146]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[145]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[145]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[144]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[144]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[143]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[143]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[142]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[142]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[141]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[141]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[140]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[140]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[139]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[139]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[138]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[138]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[137]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[137]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[136]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[136]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[135]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[135]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[134]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[134]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[133]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[133]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[132]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[132]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[131]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[131]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[130]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[130]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[129]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[129]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[128]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[128]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[127]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[127]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[126]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[126]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[125]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[125]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[124]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[124]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[123]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[123]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[122]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[122]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[121]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[121]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[120]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[120]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[119]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[119]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[118]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[118]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[117]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[117]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[116]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[116]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[115]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[115]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[114]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[114]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[113]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[113]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[112]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[112]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[111]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[111]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[110]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[110]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[109]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[109]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[108]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[108]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[107]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[107]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[106]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[106]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[105]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[105]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[104]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[104]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[103]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[103]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[102]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[102]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[101]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[101]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[100]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[100]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[99]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[99]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[98]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[98]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[97]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[97]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[96]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[96]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[95]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[95]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[94]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[94]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[93]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[93]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[92]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[92]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[91]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[91]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[90]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[90]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[89]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[89]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[88]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[88]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[87]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[87]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[86]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[86]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[85]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[85]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[84]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[84]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[83]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[83]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[82]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[82]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[81]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[81]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[80]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[80]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[79]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[79]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[78]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[78]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[77]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[77]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[76]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[76]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[75]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[75]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[74]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[74]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[73]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[73]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[72]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[72]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[71]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[71]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[70]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[70]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[69]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[69]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[68]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[68]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[67]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[67]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[66]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[66]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[65]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[65]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[64]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[64]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[63]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[63]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[62]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[62]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[61]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[61]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[60]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[60]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[59]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[59]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[58]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[58]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[57]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[57]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[56]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[56]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[55]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[55]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[54]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[54]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[53]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[53]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[52]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[52]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[51]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[51]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[50]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[50]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[49]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[49]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[48]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[48]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[47]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[47]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[46]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[46]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[45]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[45]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[44]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[44]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[43]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[43]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[42]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[42]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[41]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[41]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[40]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[40]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[39]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[39]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[38]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[38]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[37]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[37]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[36]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[36]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[35]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[34]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[33]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[32]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[31]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[30]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[29]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[28]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[27]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[26]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[25]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[24]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[23]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[22]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[21]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[20]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[19]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[18]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[17]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[16]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[15]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[14]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[13]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[12]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[11]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[10]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[9]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[8]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[7]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[6]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[5]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[4]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[3]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[0]}] -set_input_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_v_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_v_i] -set_input_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_ready_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_ready_o] -set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_ready_o] -set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_clr_o] -set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_clr_o] -set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_dequeue_o] -set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_dequeue_o] -set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_rollback_o] -set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_rollback_o] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[108]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[107]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[106]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[105]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[104]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[103]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[102]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[101]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[100]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[99]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[98]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[97]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[96]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[95]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[94]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[93]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[92]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[91]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[90]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[89]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[88]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[87]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[86]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[85]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[84]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[83]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[82]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[81]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[80]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[79]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[78]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[77]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[76]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[75]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[74]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[73]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[72]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[71]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[70]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[69]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[68]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[67]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[66]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[65]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[64]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports fe_cmd_v_o] -set_output_delay -clock CLK -min 0.6 [get_ports fe_cmd_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports lce_req_v_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_req_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports lce_resp_v_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_resp_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[536]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[536]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[535]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[535]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[534]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[534]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[533]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[533]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[532]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[532]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[531]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[531]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[530]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[530]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[529]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[529]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[528]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[528]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[527]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[527]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[526]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[526]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[525]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[525]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[524]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[524]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[523]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[523]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[522]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[522]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[521]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[521]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[520]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[520]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[519]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[519]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[518]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[518]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[517]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[517]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[516]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[516]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[515]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[515]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[514]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[514]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[513]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[513]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[512]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[512]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[511]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[511]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[510]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[510]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[509]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[509]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[508]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[508]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[507]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[507]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[506]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[506]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[505]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[505]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[504]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[504]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[503]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[503]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[502]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[502]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[501]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[501]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[500]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[500]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[499]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[499]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[498]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[498]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[497]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[497]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[496]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[496]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[495]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[495]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[494]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[494]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[493]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[493]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[492]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[492]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[491]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[491]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[490]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[490]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[489]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[489]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[488]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[488]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[487]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[487]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[486]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[486]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[485]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[485]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[484]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[484]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[483]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[483]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[482]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[482]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[481]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[481]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[480]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[480]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[479]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[479]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[478]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[478]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[477]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[477]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[476]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[476]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[475]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[475]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[474]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[474]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[473]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[473]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[472]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[472]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[471]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[471]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[470]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[470]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[469]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[469]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[468]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[468]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[467]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[467]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[466]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[466]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[465]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[465]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[464]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[464]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[463]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[463]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[462]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[462]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[461]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[461]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[460]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[460]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[459]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[459]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[458]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[458]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[457]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[457]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[456]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[456]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[455]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[455]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[454]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[454]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[453]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[453]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[452]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[452]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[451]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[451]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[450]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[450]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[449]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[449]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[448]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[448]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[447]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[447]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[446]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[446]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[445]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[445]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[444]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[444]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[443]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[443]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[442]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[442]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[441]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[441]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[440]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[440]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[439]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[439]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[438]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[438]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[437]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[437]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[436]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[436]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[435]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[435]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[434]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[434]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[433]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[433]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[432]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[432]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[431]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[431]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[430]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[430]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[429]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[429]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[428]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[428]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[427]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[427]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[426]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[426]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[425]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[425]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[424]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[424]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[423]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[423]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[422]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[422]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[421]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[421]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[420]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[420]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[419]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[419]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[418]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[418]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[417]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[417]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[416]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[416]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[415]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[415]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[414]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[414]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[413]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[413]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[412]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[412]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[411]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[411]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[410]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[410]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[409]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[409]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[408]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[408]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[407]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[407]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[406]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[406]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[405]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[405]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[404]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[404]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[403]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[403]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[402]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[402]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[401]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[401]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[400]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[400]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[399]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[399]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[398]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[398]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[397]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[397]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[396]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[396]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[395]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[395]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[394]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[394]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[393]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[393]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[392]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[392]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[391]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[391]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[390]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[390]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[389]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[389]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[388]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[388]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[387]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[387]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[386]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[386]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[385]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[385]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[384]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[384]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[383]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[383]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[382]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[382]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[381]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[381]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[380]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[380]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[379]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[379]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[378]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[378]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[377]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[377]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[376]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[376]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[375]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[375]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[374]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[374]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[373]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[373]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[372]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[372]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[371]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[371]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[370]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[370]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[369]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[369]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[368]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[368]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[367]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[367]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[366]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[366]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[365]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[365]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[364]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[364]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[363]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[363]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[362]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[362]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[361]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[361]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[360]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[360]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[359]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[359]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[358]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[358]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[357]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[357]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[356]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[356]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[355]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[355]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[354]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[354]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[353]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[353]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[352]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[352]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[351]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[351]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[350]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[350]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[349]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[349]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[348]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[348]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[347]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[347]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[346]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[346]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[345]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[345]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[344]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[344]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[343]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[343]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[342]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[342]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[341]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[341]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[340]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[340]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[339]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[339]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[338]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[338]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[337]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[337]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[336]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[336]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[335]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[335]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[334]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[334]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[333]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[333]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[332]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[332]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[331]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[331]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[330]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[330]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[329]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[329]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[328]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[328]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[327]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[327]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[326]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[326]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[325]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[325]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[324]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[324]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[323]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[323]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[322]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[322]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[321]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[321]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[320]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[320]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[319]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[319]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[318]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[318]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[317]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[317]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[316]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[316]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[315]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[315]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[314]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[314]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[313]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[313]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[312]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[312]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[311]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[311]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[310]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[310]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[309]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[309]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[308]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[308]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[307]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[307]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[306]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[306]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[305]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[305]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[304]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[304]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[303]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[303]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[302]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[302]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[301]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[301]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[300]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[300]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[299]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[299]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[298]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[298]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[297]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[297]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[296]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[296]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[295]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[295]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[294]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[294]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[293]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[293]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[292]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[292]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[291]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[291]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[290]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[290]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[289]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[289]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[288]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[288]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[287]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[287]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[286]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[286]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[285]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[285]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[284]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[284]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[283]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[283]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[282]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[282]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[281]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[281]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[280]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[280]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[279]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[279]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[278]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[278]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[277]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[277]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[276]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[276]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[275]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[275]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[274]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[274]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[273]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[273]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[272]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[272]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[271]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[271]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[270]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[270]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[269]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[269]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[268]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[268]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[267]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[267]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[266]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[266]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[265]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[265]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[264]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[264]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[263]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[263]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[262]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[262]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[261]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[261]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[260]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[260]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[259]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[259]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[258]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[258]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[257]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[257]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[256]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[256]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[255]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[255]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[254]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[254]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[253]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[253]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[252]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[252]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[251]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[251]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[250]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[250]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[249]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[249]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[248]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[248]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[247]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[247]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[246]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[246]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[245]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[245]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[244]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[244]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[243]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[243]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[242]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[242]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[241]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[241]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[240]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[240]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[239]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[239]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[238]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[238]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[237]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[237]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[236]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[236]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[235]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[235]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[234]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[234]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[233]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[233]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[232]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[232]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[231]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[231]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[230]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[230]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[229]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[229]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[228]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[228]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[227]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[227]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[226]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[226]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[225]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[225]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[224]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[224]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[223]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[223]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[222]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[222]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[221]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[221]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[220]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[220]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[219]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[219]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[218]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[218]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[217]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[217]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[216]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[216]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[215]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[215]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[214]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[214]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[213]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[213]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[212]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[212]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[211]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[211]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[210]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[210]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[209]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[209]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[208]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[208]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[207]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[207]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[206]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[206]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[205]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[205]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[204]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[204]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[203]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[203]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[202]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[202]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[201]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[201]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[200]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[200]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[199]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[199]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[198]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[198]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[197]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[197]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[196]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[196]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[195]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[195]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[194]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[194]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[193]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[193]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[192]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[192]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[191]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[191]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[190]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[190]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[189]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[189]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[188]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[188]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[187]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[187]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[186]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[186]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[185]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[185]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[184]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[184]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[183]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[183]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[182]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[182]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[181]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[181]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[180]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[180]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[179]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[179]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[178]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[178]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[177]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[177]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[176]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[176]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[175]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[175]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[174]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[174]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[173]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[173]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[172]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[172]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[171]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[171]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[170]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[170]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[169]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[169]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[168]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[168]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[167]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[167]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[166]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[166]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[165]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[165]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[164]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[164]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[163]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[163]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[162]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[162]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[161]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[161]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[160]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[160]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[159]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[159]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[158]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[158]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[157]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[157]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[156]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[156]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[155]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[155]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[154]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[154]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[153]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[153]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[152]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[152]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[151]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[151]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[150]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[150]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[149]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[149]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[148]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[148]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[147]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[147]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[146]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[146]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[145]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[145]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[144]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[144]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[143]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[143]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[142]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[142]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[141]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[141]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[140]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[140]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[139]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[139]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[138]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[138]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[137]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[137]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[136]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[136]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[135]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[135]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[134]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[134]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[133]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[133]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[132]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[132]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[131]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[131]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[130]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[130]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[129]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[129]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[128]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[128]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[127]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[127]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[126]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[126]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[125]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[125]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[124]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[124]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[123]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[123]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[122]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[122]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[121]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[121]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[120]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[120]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[119]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[119]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[118]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[118]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[117]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[117]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[116]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[116]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[115]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[115]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[114]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[114]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[113]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[113]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[112]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[112]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[111]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[111]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[110]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[110]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[109]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[109]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[108]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[107]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[106]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[105]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[104]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[103]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[102]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[101]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[100]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[99]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[98]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[97]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[96]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[95]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[94]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[93]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[92]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[91]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[90]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[89]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[88]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[87]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[86]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[85]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[84]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[83]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[82]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[81]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[80]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[79]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[78]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[77]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[76]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[75]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[74]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[73]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[72]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[71]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[70]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[69]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[68]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[67]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[66]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[65]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[64]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports lce_data_resp_v_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_data_resp_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports lce_cmd_ready_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_cmd_ready_o] -set_output_delay -clock CLK -max 0.6 [get_ports lce_data_cmd_ready_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_data_cmd_ready_o] -set_output_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_ready_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_ready_o] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[538]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[538]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[537]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[537]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[536]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[536]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[535]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[535]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[534]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[534]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[533]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[533]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[532]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[532]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[531]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[531]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[530]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[530]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[529]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[529]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[528]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[528]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[527]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[527]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[526]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[526]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[525]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[525]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[524]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[524]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[523]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[523]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[522]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[522]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[521]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[521]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[520]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[520]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[519]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[519]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[518]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[518]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[517]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[517]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[516]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[516]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[515]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[515]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[514]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[514]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[513]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[513]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[512]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[512]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[511]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[511]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[510]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[510]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[509]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[509]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[508]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[508]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[507]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[507]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[506]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[506]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[505]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[505]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[504]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[504]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[503]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[503]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[502]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[502]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[501]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[501]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[500]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[500]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[499]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[499]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[498]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[498]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[497]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[497]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[496]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[496]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[495]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[495]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[494]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[494]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[493]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[493]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[492]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[492]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[491]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[491]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[490]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[490]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[489]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[489]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[488]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[488]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[487]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[487]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[486]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[486]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[485]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[485]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[484]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[484]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[483]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[483]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[482]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[482]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[481]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[481]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[480]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[480]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[479]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[479]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[478]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[478]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[477]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[477]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[476]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[476]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[475]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[475]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[474]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[474]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[473]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[473]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[472]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[472]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[471]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[471]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[470]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[470]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[469]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[469]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[468]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[468]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[467]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[467]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[466]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[466]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[465]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[465]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[464]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[464]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[463]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[463]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[462]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[462]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[461]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[461]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[460]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[460]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[459]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[459]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[458]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[458]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[457]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[457]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[456]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[456]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[455]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[455]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[454]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[454]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[453]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[453]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[452]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[452]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[451]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[451]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[450]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[450]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[449]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[449]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[448]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[448]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[447]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[447]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[446]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[446]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[445]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[445]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[444]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[444]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[443]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[443]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[442]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[442]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[441]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[441]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[440]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[440]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[439]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[439]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[438]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[438]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[437]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[437]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[436]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[436]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[435]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[435]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[434]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[434]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[433]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[433]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[432]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[432]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[431]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[431]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[430]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[430]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[429]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[429]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[428]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[428]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[427]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[427]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[426]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[426]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[425]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[425]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[424]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[424]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[423]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[423]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[422]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[422]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[421]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[421]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[420]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[420]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[419]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[419]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[418]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[418]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[417]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[417]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[416]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[416]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[415]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[415]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[414]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[414]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[413]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[413]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[412]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[412]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[411]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[411]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[410]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[410]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[409]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[409]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[408]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[408]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[407]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[407]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[406]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[406]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[405]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[405]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[404]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[404]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[403]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[403]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[402]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[402]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[401]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[401]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[400]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[400]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[399]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[399]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[398]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[398]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[397]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[397]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[396]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[396]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[395]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[395]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[394]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[394]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[393]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[393]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[392]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[392]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[391]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[391]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[390]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[390]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[389]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[389]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[388]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[388]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[387]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[387]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[386]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[386]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[385]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[385]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[384]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[384]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[383]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[383]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[382]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[382]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[381]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[381]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[380]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[380]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[379]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[379]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[378]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[378]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[377]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[377]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[376]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[376]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[375]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[375]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[374]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[374]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[373]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[373]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[372]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[372]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[371]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[371]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[370]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[370]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[369]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[369]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[368]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[368]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[367]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[367]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[366]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[366]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[365]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[365]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[364]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[364]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[363]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[363]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[362]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[362]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[361]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[361]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[360]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[360]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[359]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[359]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[358]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[358]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[357]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[357]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[356]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[356]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[355]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[355]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[354]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[354]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[353]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[353]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[352]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[352]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[351]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[351]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[350]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[350]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[349]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[349]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[348]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[348]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[347]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[347]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[346]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[346]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[345]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[345]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[344]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[344]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[343]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[343]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[342]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[342]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[341]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[341]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[340]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[340]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[339]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[339]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[338]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[338]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[337]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[337]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[336]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[336]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[335]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[335]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[334]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[334]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[333]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[333]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[332]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[332]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[331]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[331]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[330]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[330]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[329]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[329]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[328]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[328]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[327]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[327]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[326]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[326]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[325]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[325]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[324]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[324]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[323]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[323]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[322]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[322]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[321]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[321]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[320]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[320]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[319]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[319]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[318]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[318]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[317]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[317]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[316]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[316]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[315]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[315]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[314]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[314]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[313]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[313]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[312]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[312]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[311]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[311]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[310]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[310]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[309]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[309]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[308]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[308]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[307]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[307]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[306]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[306]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[305]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[305]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[304]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[304]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[303]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[303]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[302]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[302]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[301]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[301]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[300]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[300]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[299]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[299]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[298]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[298]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[297]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[297]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[296]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[296]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[295]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[295]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[294]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[294]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[293]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[293]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[292]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[292]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[291]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[291]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[290]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[290]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[289]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[289]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[288]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[288]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[287]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[287]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[286]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[286]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[285]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[285]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[284]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[284]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[283]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[283]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[282]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[282]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[281]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[281]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[280]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[280]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[279]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[279]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[278]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[278]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[277]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[277]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[276]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[276]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[275]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[275]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[274]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[274]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[273]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[273]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[272]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[272]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[271]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[271]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[270]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[270]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[269]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[269]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[268]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[268]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[267]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[267]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[266]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[266]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[265]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[265]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[264]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[264]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[263]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[263]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[262]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[262]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[261]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[261]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[260]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[260]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[259]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[259]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[258]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[258]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[257]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[257]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[256]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[256]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[255]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[255]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[254]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[254]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[253]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[253]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[252]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[252]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[251]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[251]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[250]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[250]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[249]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[249]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[248]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[248]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[247]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[247]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[246]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[246]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[245]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[245]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[244]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[244]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[243]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[243]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[242]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[242]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[241]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[241]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[240]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[240]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[239]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[239]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[238]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[238]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[237]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[237]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[236]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[236]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[235]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[235]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[234]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[234]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[233]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[233]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[232]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[232]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[231]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[231]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[230]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[230]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[229]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[229]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[228]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[228]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[227]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[227]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[226]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[226]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[225]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[225]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[224]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[224]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[223]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[223]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[222]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[222]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[221]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[221]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[220]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[220]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[219]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[219]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[218]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[218]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[217]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[217]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[216]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[216]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[215]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[215]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[214]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[214]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[213]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[213]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[212]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[212]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[211]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[211]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[210]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[210]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[209]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[209]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[208]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[208]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[207]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[207]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[206]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[206]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[205]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[205]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[204]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[204]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[203]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[203]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[202]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[202]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[201]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[201]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[200]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[200]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[199]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[199]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[198]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[198]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[197]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[197]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[196]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[196]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[195]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[195]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[194]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[194]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[193]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[193]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[192]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[192]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[191]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[191]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[190]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[190]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[189]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[189]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[188]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[188]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[187]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[187]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[186]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[186]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[185]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[185]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[184]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[184]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[183]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[183]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[182]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[182]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[181]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[181]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[180]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[180]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[179]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[179]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[178]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[178]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[177]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[177]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[176]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[176]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[175]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[175]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[174]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[174]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[173]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[173]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[172]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[172]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[171]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[171]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[170]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[170]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[169]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[169]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[168]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[168]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[167]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[167]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[166]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[166]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[165]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[165]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[164]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[164]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[163]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[163]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[162]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[162]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[161]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[161]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[160]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[160]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[159]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[159]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[158]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[158]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[157]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[157]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[156]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[156]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[155]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[155]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[154]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[154]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[153]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[153]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[152]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[152]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[151]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[151]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[150]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[150]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[149]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[149]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[148]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[148]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[147]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[147]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[146]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[146]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[145]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[145]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[144]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[144]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[143]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[143]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[142]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[142]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[141]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[141]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[140]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[140]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[139]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[139]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[138]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[138]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[137]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[137]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[136]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[136]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[135]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[135]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[134]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[134]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[133]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[133]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[132]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[132]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[131]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[131]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[130]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[130]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[129]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[129]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[128]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[128]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[127]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[127]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[126]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[126]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[125]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[125]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[124]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[124]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[123]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[123]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[122]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[122]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[121]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[121]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[120]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[120]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[119]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[119]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[118]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[118]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[117]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[117]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[116]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[116]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[115]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[115]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[114]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[114]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[113]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[113]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[112]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[112]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[111]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[111]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[110]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[110]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[109]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[109]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[108]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[107]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[106]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[105]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[104]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[103]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[102]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[101]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[100]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[99]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[98]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[97]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[96]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[95]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[94]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[93]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[92]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[91]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[90]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[89]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[88]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[87]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[86]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[85]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[84]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[83]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[82]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[81]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[80]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[79]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[78]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[77]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[76]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[75]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[74]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[73]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[72]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[71]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[70]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[69]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[68]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[67]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[66]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[65]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[64]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_v_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[377]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[377]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[376]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[376]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[375]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[375]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[374]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[374]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[373]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[373]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[372]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[372]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[371]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[371]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[370]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[370]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[369]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[369]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[368]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[368]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[367]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[367]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[366]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[366]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[365]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[365]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[364]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[364]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[363]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[363]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[362]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[362]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[361]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[361]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[360]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[360]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[359]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[359]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[358]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[358]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[357]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[357]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[356]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[356]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[355]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[355]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[354]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[354]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[353]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[353]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[352]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[352]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[351]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[351]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[350]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[350]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[349]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[349]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[348]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[348]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[347]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[347]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[346]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[346]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[345]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[345]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[344]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[344]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[343]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[343]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[342]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[342]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[341]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[341]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[340]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[340]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[339]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[339]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[338]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[338]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[337]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[337]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[336]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[336]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[335]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[335]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[334]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[334]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[333]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[333]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[332]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[332]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[331]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[331]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[330]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[330]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[329]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[329]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[328]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[328]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[327]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[327]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[326]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[326]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[325]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[325]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[324]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[324]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[323]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[323]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[322]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[322]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[321]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[321]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[320]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[320]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[319]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[319]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[318]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[318]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[317]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[317]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[316]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[316]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[315]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[315]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[314]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[314]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[313]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[313]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[312]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[312]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[311]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[311]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[310]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[310]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[309]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[309]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[308]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[308]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[307]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[307]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[306]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[306]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[305]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[305]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[304]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[304]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[303]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[303]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[302]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[302]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[301]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[301]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[300]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[300]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[299]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[299]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[298]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[298]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[297]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[297]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[296]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[296]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[295]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[295]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[294]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[294]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[293]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[293]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[292]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[292]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[291]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[291]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[290]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[290]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[289]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[289]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[288]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[288]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[287]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[287]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[286]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[286]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[285]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[285]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[284]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[284]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[283]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[283]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[282]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[282]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[281]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[281]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[280]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[280]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[279]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[279]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[278]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[278]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[277]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[277]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[276]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[276]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[275]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[275]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[274]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[274]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[273]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[273]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[272]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[272]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[271]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[271]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[270]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[270]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[269]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[269]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[268]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[268]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[267]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[267]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[266]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[266]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[265]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[265]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[264]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[264]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[263]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[263]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[262]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[262]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[261]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[261]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[260]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[260]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[259]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[259]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[258]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[258]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[257]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[257]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[256]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[256]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[255]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[255]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[254]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[254]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[253]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[253]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[252]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[252]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[251]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[251]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[250]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[250]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[249]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[249]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[248]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[248]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[247]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[247]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[246]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[246]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[245]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[245]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[244]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[244]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[243]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[243]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[242]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[242]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[241]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[241]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[240]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[240]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[239]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[239]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[238]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[238]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[237]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[237]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[236]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[236]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[235]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[235]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[234]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[234]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[233]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[233]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[232]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[232]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[231]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[231]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[230]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[230]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[229]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[229]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[228]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[228]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[227]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[227]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[226]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[226]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[225]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[225]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[224]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[224]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[223]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[223]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[222]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[222]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[221]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[221]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[220]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[220]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[219]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[219]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[218]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[218]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[217]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[217]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[216]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[216]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[215]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[215]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[214]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[214]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[213]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[213]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[212]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[212]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[211]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[211]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[210]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[210]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[209]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[209]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[208]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[208]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[207]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[207]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[206]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[206]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[205]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[205]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[204]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[204]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[203]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[203]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[202]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[202]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[201]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[201]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[200]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[200]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[199]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[199]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[198]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[198]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[197]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[197]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[196]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[196]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[195]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[195]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[194]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[194]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[193]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[193]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[192]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[192]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[191]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[191]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[190]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[190]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[189]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[189]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[188]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[188]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[187]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[187]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[186]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[186]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[185]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[185]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[184]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[184]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[183]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[183]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[182]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[182]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[181]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[181]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[180]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[180]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[179]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[179]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[178]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[178]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[177]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[177]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[176]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[176]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[175]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[175]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[174]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[174]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[173]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[173]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[172]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[172]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[171]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[171]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[170]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[170]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[169]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[169]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[168]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[168]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[167]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[167]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[166]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[166]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[165]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[165]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[164]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[164]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[163]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[163]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[162]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[162]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[161]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[161]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[160]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[160]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[159]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[159]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[158]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[158]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[157]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[157]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[156]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[156]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[155]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[155]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[154]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[154]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[153]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[153]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[152]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[152]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[151]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[151]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[150]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[150]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[149]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[149]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[148]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[148]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[147]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[147]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[146]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[146]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[145]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[145]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[144]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[144]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[143]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[143]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[142]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[142]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[141]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[141]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[140]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[140]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[139]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[139]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[138]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[138]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[137]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[137]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[136]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[136]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[135]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[135]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[134]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[134]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[133]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[133]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[132]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[132]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[131]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[131]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[130]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[130]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[129]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[129]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[128]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[128]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[127]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[127]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[126]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[126]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[125]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[125]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[124]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[124]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[123]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[123]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[122]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[122]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[121]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[121]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[120]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[120]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[119]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[119]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[118]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[118]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[117]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[117]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[116]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[116]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[115]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[115]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[114]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[114]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[113]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[113]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[112]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[112]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[111]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[111]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[110]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[110]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[109]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[109]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[108]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[107]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[106]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[105]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[104]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[103]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[102]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[101]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[100]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[99]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[98]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[97]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[96]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[95]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[94]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[93]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[92]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[91]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[90]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[89]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[88]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[87]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[86]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[85]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[84]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[83]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[82]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[81]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[80]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[79]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[78]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[77]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[76]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[75]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[74]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[73]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[72]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[71]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[70]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[69]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[68]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[67]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[66]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[65]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[64]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[127]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[127]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[126]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[126]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[125]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[125]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[124]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[124]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[123]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[123]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[122]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[122]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[121]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[121]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[120]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[120]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[119]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[119]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[118]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[118]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[117]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[117]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[116]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[116]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[115]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[115]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[114]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[114]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[113]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[113]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[112]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[112]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[111]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[111]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[110]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[110]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[109]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[109]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[108]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[107]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[106]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[105]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[104]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[103]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[102]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[101]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[100]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[99]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[98]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[97]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[96]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[95]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[94]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[93]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[92]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[91]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[90]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[89]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[88]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[87]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[86]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[85]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[84]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[83]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[82]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[81]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[80]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[79]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[78]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[77]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[76]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[75]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[74]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[73]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[72]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[71]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[70]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[69]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[68]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[67]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[66]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[65]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[64]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[0]}] +create_clock [get_ports clk_i] -name CLK -period 2.6 -waveform {0 1.3} +set_input_delay -clock CLK -max 0.6 [get_ports reset_i] +set_input_delay -clock CLK -min 0.6 [get_ports reset_i] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[133]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[133]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[132]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[132]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[131]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[131]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[130]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[130]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[129]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[129]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[128]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[128]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[127]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[127]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[126]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[126]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[125]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[125]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[124]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[124]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[123]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[123]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[122]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[122]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[121]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[121]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[120]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[120]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[119]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[119]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[118]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[118]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[117]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[117]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[116]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[116]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[115]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[115]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[114]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[114]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[113]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[113]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[112]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[112]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[111]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[111]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[110]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[110]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[109]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[109]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[108]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[108]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[107]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[107]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[106]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[106]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[105]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[105]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[104]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[104]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[103]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[103]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[102]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[102]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[101]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[101]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[100]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[100]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[99]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[99]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[98]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[98]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[97]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[97]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[96]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[96]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[95]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[95]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[94]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[94]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[93]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[93]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[92]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[92]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[91]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[91]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[90]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[90]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[89]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[89]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[88]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[88]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[87]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[87]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[86]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[86]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[85]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[85]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[84]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[84]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[83]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[83]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[82]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[82]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[81]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[81]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[80]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[80]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[79]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[79]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[78]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[78]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[77]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[77]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[76]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[76]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[75]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[75]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[74]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[74]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[73]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[73]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[72]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[72]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[71]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[71]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[70]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[70]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[69]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[69]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[68]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[68]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[67]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[67]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[66]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[66]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[65]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[65]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[64]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[64]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[63]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[63]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[62]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[62]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[61]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[61]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[60]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[60]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[59]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[59]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[58]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[58]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[57]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[57]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[56]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[56]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[55]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[55]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[54]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[54]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[53]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[53]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[52]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[52]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[51]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[51]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[50]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[50]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[49]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[49]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[48]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[48]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[47]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[47]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[46]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[46]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[45]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[45]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[44]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[44]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[43]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[43]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[42]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[42]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[41]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[41]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[40]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[40]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[39]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[39]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[38]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[38]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[37]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[37]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[36]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[36]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[35]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[34]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[33]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[32]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[31]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[30]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[29]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[28]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[27]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[26]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[25]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[24]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[23]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[22]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[21]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[20]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[19]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[18]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[17]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[16]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[15]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[14]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[13]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[12]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[11]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[10]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[9]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[8]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[7]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[6]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[5]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[4]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[3]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[2]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[1]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[0]}] +set_input_delay -clock CLK -max 0.6 [get_ports fe_queue_v_i] +set_input_delay -clock CLK -min 0.6 [get_ports fe_queue_v_i] +set_input_delay -clock CLK -max 0.6 [get_ports fe_cmd_ready_i] +set_input_delay -clock CLK -min 0.6 [get_ports fe_cmd_ready_i] +set_input_delay -clock CLK -max 0.6 [get_ports lce_req_ready_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_req_ready_i] +set_input_delay -clock CLK -max 0.6 [get_ports lce_resp_ready_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_resp_ready_i] +set_input_delay -clock CLK -max 0.6 [get_ports lce_data_resp_ready_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_data_resp_ready_i] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[35]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[34]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[33]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[32]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[31]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[30]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[29]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[28]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[27]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[26]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[25]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[24]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[23]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[22]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[21]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[20]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[19]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[18]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[17]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[16]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[15]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[14]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[13]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[12]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[11]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[10]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[9]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[8]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[7]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[6]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[5]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[4]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[3]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[2]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[1]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[0]}] +set_input_delay -clock CLK -max 0.6 [get_ports lce_cmd_v_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_cmd_v_i] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[539]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[539]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[538]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[538]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[537]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[537]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[536]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[536]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[535]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[535]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[534]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[534]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[533]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[533]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[532]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[532]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[531]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[531]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[530]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[530]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[529]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[529]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[528]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[528]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[527]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[527]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[526]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[526]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[525]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[525]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[524]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[524]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[523]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[523]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[522]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[522]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[521]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[521]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[520]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[520]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[519]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[519]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[518]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[518]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[517]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[517]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[516]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[516]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[515]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[515]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[514]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[514]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[513]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[513]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[512]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[512]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[511]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[511]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[510]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[510]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[509]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[509]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[508]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[508]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[507]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[507]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[506]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[506]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[505]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[505]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[504]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[504]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[503]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[503]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[502]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[502]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[501]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[501]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[500]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[500]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[499]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[499]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[498]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[498]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[497]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[497]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[496]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[496]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[495]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[495]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[494]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[494]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[493]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[493]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[492]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[492]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[491]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[491]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[490]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[490]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[489]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[489]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[488]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[488]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[487]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[487]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[486]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[486]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[485]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[485]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[484]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[484]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[483]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[483]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[482]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[482]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[481]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[481]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[480]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[480]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[479]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[479]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[478]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[478]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[477]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[477]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[476]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[476]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[475]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[475]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[474]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[474]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[473]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[473]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[472]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[472]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[471]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[471]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[470]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[470]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[469]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[469]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[468]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[468]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[467]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[467]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[466]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[466]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[465]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[465]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[464]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[464]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[463]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[463]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[462]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[462]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[461]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[461]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[460]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[460]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[459]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[459]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[458]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[458]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[457]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[457]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[456]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[456]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[455]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[455]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[454]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[454]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[453]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[453]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[452]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[452]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[451]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[451]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[450]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[450]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[449]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[449]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[448]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[448]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[447]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[447]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[446]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[446]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[445]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[445]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[444]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[444]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[443]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[443]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[442]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[442]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[441]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[441]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[440]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[440]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[439]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[439]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[438]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[438]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[437]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[437]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[436]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[436]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[435]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[435]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[434]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[434]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[433]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[433]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[432]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[432]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[431]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[431]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[430]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[430]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[429]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[429]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[428]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[428]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[427]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[427]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[426]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[426]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[425]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[425]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[424]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[424]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[423]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[423]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[422]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[422]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[421]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[421]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[420]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[420]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[419]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[419]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[418]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[418]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[417]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[417]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[416]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[416]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[415]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[415]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[414]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[414]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[413]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[413]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[412]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[412]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[411]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[411]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[410]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[410]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[409]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[409]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[408]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[408]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[407]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[407]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[406]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[406]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[405]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[405]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[404]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[404]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[403]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[403]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[402]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[402]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[401]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[401]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[400]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[400]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[399]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[399]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[398]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[398]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[397]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[397]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[396]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[396]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[395]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[395]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[394]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[394]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[393]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[393]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[392]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[392]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[391]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[391]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[390]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[390]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[389]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[389]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[388]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[388]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[387]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[387]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[386]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[386]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[385]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[385]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[384]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[384]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[383]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[383]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[382]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[382]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[381]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[381]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[380]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[380]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[379]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[379]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[378]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[378]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[377]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[377]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[376]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[376]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[375]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[375]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[374]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[374]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[373]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[373]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[372]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[372]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[371]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[371]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[370]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[370]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[369]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[369]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[368]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[368]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[367]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[367]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[366]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[366]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[365]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[365]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[364]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[364]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[363]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[363]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[362]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[362]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[361]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[361]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[360]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[360]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[359]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[359]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[358]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[358]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[357]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[357]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[356]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[356]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[355]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[355]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[354]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[354]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[353]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[353]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[352]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[352]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[351]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[351]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[350]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[350]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[349]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[349]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[348]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[348]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[347]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[347]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[346]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[346]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[345]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[345]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[344]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[344]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[343]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[343]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[342]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[342]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[341]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[341]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[340]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[340]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[339]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[339]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[338]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[338]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[337]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[337]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[336]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[336]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[335]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[335]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[334]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[334]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[333]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[333]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[332]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[332]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[331]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[331]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[330]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[330]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[329]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[329]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[328]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[328]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[327]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[327]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[326]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[326]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[325]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[325]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[324]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[324]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[323]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[323]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[322]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[322]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[321]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[321]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[320]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[320]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[319]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[319]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[318]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[318]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[317]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[317]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[316]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[316]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[315]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[315]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[314]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[314]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[313]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[313]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[312]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[312]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[311]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[311]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[310]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[310]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[309]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[309]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[308]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[308]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[307]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[307]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[306]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[306]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[305]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[305]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[304]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[304]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[303]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[303]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[302]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[302]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[301]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[301]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[300]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[300]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[299]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[299]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[298]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[298]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[297]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[297]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[296]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[296]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[295]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[295]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[294]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[294]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[293]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[293]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[292]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[292]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[291]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[291]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[290]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[290]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[289]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[289]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[288]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[288]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[287]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[287]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[286]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[286]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[285]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[285]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[284]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[284]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[283]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[283]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[282]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[282]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[281]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[281]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[280]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[280]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[279]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[279]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[278]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[278]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[277]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[277]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[276]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[276]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[275]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[275]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[274]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[274]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[273]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[273]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[272]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[272]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[271]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[271]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[270]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[270]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[269]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[269]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[268]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[268]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[267]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[267]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[266]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[266]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[265]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[265]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[264]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[264]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[263]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[263]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[262]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[262]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[261]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[261]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[260]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[260]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[259]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[259]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[258]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[258]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[257]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[257]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[256]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[256]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[255]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[255]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[254]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[254]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[253]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[253]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[252]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[252]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[251]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[251]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[250]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[250]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[249]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[249]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[248]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[248]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[247]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[247]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[246]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[246]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[245]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[245]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[244]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[244]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[243]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[243]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[242]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[242]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[241]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[241]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[240]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[240]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[239]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[239]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[238]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[238]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[237]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[237]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[236]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[236]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[235]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[235]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[234]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[234]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[233]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[233]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[232]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[232]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[231]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[231]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[230]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[230]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[229]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[229]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[228]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[228]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[227]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[227]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[226]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[226]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[225]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[225]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[224]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[224]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[223]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[223]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[222]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[222]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[221]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[221]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[220]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[220]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[219]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[219]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[218]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[218]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[217]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[217]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[216]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[216]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[215]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[215]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[214]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[214]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[213]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[213]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[212]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[212]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[211]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[211]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[210]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[210]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[209]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[209]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[208]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[208]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[207]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[207]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[206]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[206]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[205]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[205]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[204]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[204]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[203]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[203]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[202]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[202]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[201]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[201]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[200]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[200]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[199]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[199]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[198]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[198]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[197]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[197]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[196]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[196]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[195]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[195]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[194]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[194]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[193]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[193]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[192]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[192]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[191]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[191]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[190]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[190]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[189]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[189]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[188]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[188]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[187]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[187]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[186]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[186]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[185]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[185]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[184]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[184]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[183]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[183]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[182]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[182]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[181]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[181]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[180]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[180]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[179]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[179]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[178]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[178]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[177]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[177]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[176]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[176]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[175]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[175]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[174]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[174]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[173]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[173]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[172]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[172]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[171]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[171]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[170]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[170]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[169]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[169]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[168]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[168]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[167]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[167]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[166]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[166]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[165]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[165]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[164]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[164]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[163]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[163]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[162]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[162]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[161]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[161]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[160]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[160]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[159]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[159]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[158]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[158]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[157]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[157]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[156]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[156]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[155]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[155]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[154]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[154]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[153]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[153]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[152]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[152]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[151]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[151]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[150]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[150]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[149]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[149]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[148]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[148]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[147]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[147]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[146]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[146]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[145]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[145]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[144]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[144]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[143]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[143]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[142]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[142]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[141]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[141]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[140]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[140]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[139]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[139]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[138]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[138]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[137]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[137]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[136]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[136]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[135]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[135]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[134]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[134]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[133]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[133]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[132]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[132]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[131]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[131]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[130]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[130]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[129]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[129]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[128]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[128]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[127]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[127]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[126]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[126]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[125]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[125]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[124]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[124]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[123]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[123]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[122]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[122]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[121]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[121]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[120]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[120]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[119]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[119]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[118]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[118]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[117]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[117]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[116]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[116]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[115]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[115]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[114]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[114]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[113]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[113]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[112]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[112]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[111]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[111]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[110]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[110]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[109]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[109]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[108]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[108]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[107]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[107]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[106]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[106]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[105]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[105]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[104]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[104]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[103]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[103]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[102]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[102]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[101]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[101]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[100]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[100]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[99]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[99]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[98]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[98]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[97]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[97]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[96]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[96]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[95]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[95]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[94]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[94]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[93]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[93]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[92]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[92]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[91]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[91]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[90]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[90]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[89]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[89]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[88]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[88]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[87]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[87]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[86]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[86]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[85]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[85]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[84]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[84]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[83]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[83]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[82]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[82]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[81]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[81]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[80]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[80]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[79]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[79]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[78]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[78]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[77]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[77]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[76]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[76]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[75]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[75]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[74]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[74]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[73]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[73]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[72]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[72]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[71]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[71]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[70]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[70]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[69]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[69]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[68]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[68]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[67]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[67]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[66]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[66]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[65]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[65]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[64]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[64]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[63]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[63]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[62]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[62]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[61]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[61]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[60]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[60]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[59]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[59]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[58]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[58]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[57]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[57]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[56]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[56]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[55]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[55]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[54]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[54]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[53]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[53]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[52]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[52]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[51]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[51]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[50]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[50]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[49]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[49]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[48]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[48]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[47]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[47]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[46]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[46]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[45]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[45]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[44]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[44]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[43]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[43]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[42]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[42]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[41]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[41]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[40]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[40]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[39]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[39]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[38]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[38]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[37]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[37]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[36]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[36]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[35]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[34]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[33]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[32]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[31]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[30]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[29]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[28]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[27]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[26]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[25]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[24]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[23]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[22]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[21]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[20]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[19]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[18]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[17]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[16]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[15]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[14]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[13]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[12]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[11]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[10]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[9]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[8]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[7]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[6]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[5]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[4]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[3]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[2]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[1]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[0]}] +set_input_delay -clock CLK -max 0.6 [get_ports lce_data_cmd_v_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_data_cmd_v_i] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[538]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[538]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[537]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[537]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[536]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[536]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[535]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[535]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[534]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[534]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[533]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[533]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[532]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[532]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[531]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[531]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[530]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[530]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[529]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[529]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[528]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[528]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[527]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[527]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[526]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[526]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[525]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[525]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[524]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[524]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[523]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[523]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[522]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[522]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[521]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[521]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[520]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[520]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[519]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[519]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[518]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[518]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[517]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[517]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[516]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[516]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[515]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[515]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[514]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[514]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[513]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[513]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[512]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[512]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[511]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[511]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[510]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[510]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[509]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[509]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[508]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[508]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[507]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[507]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[506]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[506]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[505]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[505]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[504]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[504]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[503]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[503]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[502]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[502]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[501]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[501]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[500]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[500]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[499]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[499]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[498]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[498]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[497]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[497]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[496]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[496]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[495]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[495]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[494]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[494]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[493]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[493]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[492]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[492]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[491]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[491]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[490]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[490]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[489]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[489]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[488]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[488]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[487]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[487]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[486]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[486]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[485]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[485]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[484]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[484]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[483]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[483]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[482]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[482]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[481]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[481]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[480]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[480]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[479]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[479]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[478]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[478]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[477]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[477]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[476]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[476]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[475]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[475]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[474]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[474]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[473]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[473]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[472]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[472]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[471]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[471]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[470]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[470]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[469]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[469]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[468]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[468]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[467]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[467]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[466]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[466]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[465]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[465]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[464]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[464]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[463]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[463]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[462]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[462]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[461]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[461]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[460]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[460]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[459]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[459]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[458]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[458]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[457]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[457]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[456]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[456]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[455]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[455]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[454]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[454]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[453]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[453]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[452]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[452]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[451]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[451]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[450]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[450]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[449]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[449]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[448]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[448]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[447]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[447]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[446]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[446]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[445]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[445]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[444]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[444]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[443]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[443]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[442]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[442]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[441]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[441]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[440]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[440]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[439]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[439]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[438]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[438]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[437]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[437]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[436]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[436]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[435]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[435]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[434]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[434]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[433]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[433]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[432]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[432]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[431]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[431]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[430]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[430]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[429]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[429]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[428]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[428]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[427]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[427]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[426]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[426]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[425]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[425]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[424]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[424]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[423]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[423]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[422]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[422]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[421]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[421]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[420]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[420]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[419]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[419]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[418]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[418]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[417]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[417]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[416]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[416]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[415]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[415]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[414]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[414]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[413]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[413]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[412]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[412]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[411]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[411]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[410]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[410]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[409]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[409]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[408]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[408]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[407]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[407]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[406]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[406]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[405]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[405]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[404]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[404]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[403]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[403]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[402]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[402]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[401]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[401]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[400]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[400]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[399]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[399]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[398]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[398]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[397]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[397]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[396]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[396]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[395]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[395]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[394]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[394]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[393]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[393]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[392]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[392]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[391]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[391]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[390]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[390]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[389]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[389]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[388]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[388]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[387]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[387]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[386]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[386]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[385]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[385]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[384]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[384]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[383]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[383]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[382]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[382]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[381]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[381]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[380]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[380]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[379]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[379]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[378]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[378]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[377]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[377]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[376]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[376]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[375]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[375]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[374]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[374]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[373]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[373]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[372]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[372]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[371]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[371]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[370]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[370]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[369]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[369]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[368]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[368]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[367]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[367]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[366]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[366]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[365]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[365]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[364]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[364]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[363]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[363]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[362]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[362]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[361]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[361]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[360]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[360]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[359]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[359]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[358]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[358]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[357]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[357]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[356]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[356]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[355]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[355]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[354]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[354]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[353]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[353]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[352]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[352]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[351]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[351]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[350]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[350]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[349]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[349]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[348]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[348]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[347]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[347]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[346]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[346]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[345]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[345]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[344]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[344]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[343]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[343]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[342]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[342]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[341]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[341]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[340]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[340]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[339]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[339]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[338]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[338]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[337]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[337]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[336]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[336]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[335]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[335]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[334]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[334]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[333]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[333]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[332]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[332]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[331]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[331]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[330]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[330]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[329]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[329]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[328]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[328]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[327]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[327]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[326]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[326]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[325]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[325]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[324]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[324]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[323]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[323]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[322]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[322]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[321]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[321]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[320]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[320]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[319]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[319]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[318]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[318]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[317]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[317]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[316]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[316]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[315]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[315]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[314]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[314]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[313]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[313]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[312]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[312]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[311]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[311]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[310]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[310]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[309]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[309]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[308]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[308]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[307]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[307]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[306]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[306]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[305]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[305]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[304]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[304]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[303]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[303]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[302]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[302]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[301]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[301]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[300]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[300]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[299]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[299]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[298]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[298]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[297]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[297]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[296]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[296]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[295]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[295]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[294]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[294]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[293]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[293]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[292]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[292]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[291]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[291]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[290]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[290]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[289]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[289]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[288]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[288]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[287]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[287]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[286]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[286]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[285]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[285]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[284]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[284]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[283]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[283]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[282]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[282]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[281]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[281]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[280]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[280]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[279]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[279]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[278]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[278]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[277]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[277]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[276]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[276]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[275]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[275]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[274]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[274]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[273]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[273]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[272]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[272]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[271]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[271]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[270]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[270]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[269]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[269]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[268]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[268]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[267]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[267]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[266]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[266]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[265]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[265]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[264]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[264]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[263]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[263]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[262]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[262]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[261]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[261]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[260]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[260]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[259]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[259]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[258]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[258]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[257]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[257]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[256]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[256]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[255]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[255]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[254]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[254]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[253]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[253]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[252]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[252]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[251]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[251]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[250]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[250]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[249]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[249]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[248]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[248]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[247]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[247]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[246]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[246]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[245]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[245]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[244]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[244]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[243]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[243]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[242]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[242]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[241]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[241]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[240]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[240]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[239]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[239]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[238]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[238]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[237]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[237]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[236]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[236]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[235]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[235]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[234]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[234]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[233]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[233]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[232]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[232]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[231]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[231]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[230]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[230]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[229]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[229]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[228]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[228]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[227]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[227]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[226]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[226]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[225]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[225]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[224]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[224]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[223]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[223]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[222]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[222]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[221]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[221]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[220]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[220]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[219]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[219]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[218]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[218]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[217]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[217]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[216]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[216]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[215]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[215]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[214]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[214]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[213]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[213]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[212]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[212]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[211]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[211]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[210]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[210]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[209]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[209]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[208]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[208]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[207]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[207]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[206]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[206]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[205]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[205]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[204]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[204]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[203]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[203]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[202]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[202]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[201]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[201]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[200]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[200]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[199]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[199]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[198]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[198]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[197]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[197]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[196]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[196]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[195]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[195]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[194]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[194]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[193]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[193]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[192]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[192]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[191]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[191]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[190]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[190]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[189]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[189]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[188]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[188]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[187]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[187]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[186]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[186]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[185]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[185]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[184]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[184]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[183]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[183]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[182]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[182]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[181]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[181]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[180]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[180]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[179]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[179]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[178]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[178]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[177]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[177]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[176]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[176]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[175]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[175]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[174]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[174]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[173]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[173]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[172]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[172]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[171]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[171]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[170]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[170]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[169]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[169]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[168]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[168]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[167]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[167]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[166]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[166]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[165]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[165]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[164]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[164]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[163]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[163]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[162]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[162]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[161]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[161]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[160]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[160]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[159]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[159]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[158]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[158]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[157]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[157]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[156]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[156]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[155]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[155]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[154]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[154]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[153]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[153]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[152]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[152]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[151]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[151]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[150]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[150]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[149]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[149]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[148]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[148]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[147]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[147]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[146]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[146]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[145]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[145]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[144]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[144]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[143]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[143]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[142]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[142]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[141]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[141]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[140]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[140]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[139]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[139]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[138]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[138]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[137]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[137]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[136]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[136]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[135]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[135]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[134]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[134]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[133]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[133]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[132]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[132]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[131]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[131]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[130]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[130]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[129]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[129]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[128]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[128]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[127]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[127]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[126]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[126]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[125]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[125]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[124]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[124]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[123]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[123]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[122]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[122]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[121]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[121]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[120]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[120]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[119]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[119]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[118]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[118]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[117]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[117]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[116]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[116]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[115]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[115]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[114]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[114]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[113]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[113]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[112]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[112]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[111]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[111]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[110]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[110]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[109]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[109]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[108]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[108]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[107]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[107]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[106]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[106]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[105]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[105]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[104]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[104]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[103]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[103]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[102]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[102]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[101]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[101]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[100]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[100]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[99]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[99]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[98]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[98]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[97]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[97]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[96]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[96]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[95]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[95]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[94]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[94]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[93]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[93]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[92]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[92]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[91]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[91]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[90]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[90]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[89]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[89]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[88]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[88]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[87]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[87]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[86]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[86]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[85]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[85]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[84]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[84]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[83]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[83]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[82]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[82]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[81]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[81]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[80]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[80]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[79]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[79]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[78]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[78]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[77]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[77]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[76]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[76]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[75]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[75]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[74]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[74]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[73]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[73]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[72]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[72]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[71]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[71]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[70]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[70]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[69]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[69]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[68]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[68]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[67]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[67]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[66]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[66]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[65]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[65]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[64]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[64]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[63]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[63]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[62]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[62]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[61]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[61]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[60]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[60]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[59]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[59]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[58]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[58]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[57]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[57]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[56]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[56]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[55]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[55]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[54]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[54]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[53]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[53]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[52]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[52]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[51]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[51]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[50]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[50]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[49]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[49]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[48]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[48]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[47]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[47]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[46]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[46]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[45]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[45]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[44]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[44]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[43]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[43]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[42]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[42]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[41]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[41]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[40]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[40]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[39]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[39]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[38]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[38]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[37]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[37]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[36]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[36]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[35]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[34]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[33]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[32]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[31]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[30]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[29]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[28]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[27]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[26]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[25]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[24]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[23]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[22]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[21]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[20]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[19]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[18]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[17]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[16]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[15]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[14]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[13]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[12]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[11]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[10]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[9]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[8]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[7]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[6]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[5]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[4]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[3]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[2]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[1]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[0]}] +set_input_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_v_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_v_i] +set_input_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_ready_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_ready_i] +set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[2]}] +set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[1]}] +set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_ready_o] +set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_ready_o] +set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_clr_o] +set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_clr_o] +set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_dequeue_o] +set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_dequeue_o] +set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_rollback_o] +set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_rollback_o] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[108]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[108]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[107]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[107]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[106]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[106]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[105]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[105]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[104]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[104]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[103]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[103]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[102]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[102]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[101]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[101]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[100]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[100]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[99]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[99]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[98]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[98]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[97]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[97]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[96]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[96]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[95]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[95]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[94]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[94]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[93]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[93]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[92]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[92]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[91]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[91]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[90]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[90]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[89]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[89]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[88]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[88]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[87]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[87]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[86]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[86]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[85]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[85]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[84]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[84]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[83]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[83]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[82]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[82]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[81]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[81]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[80]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[80]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[79]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[79]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[78]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[78]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[77]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[77]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[76]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[76]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[75]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[75]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[74]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[74]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[73]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[73]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[72]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[72]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[71]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[71]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[70]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[70]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[69]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[69]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[68]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[68]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[67]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[67]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[66]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[66]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[65]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[65]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[64]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[64]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[63]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[62]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[61]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[60]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[59]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[58]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[57]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[56]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[55]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[54]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[53]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[52]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[51]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[50]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[49]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[48]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[47]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[46]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[45]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[44]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[43]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[42]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[41]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[40]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[39]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[38]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[37]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[36]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[35]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[34]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[33]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[32]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[31]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[30]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[29]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[28]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[27]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[26]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports fe_cmd_v_o] +set_output_delay -clock CLK -min 0.6 [get_ports fe_cmd_v_o] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[29]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[28]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[27]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[26]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports lce_req_v_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_req_v_o] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports lce_resp_v_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_resp_v_o] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[536]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[536]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[535]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[535]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[534]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[534]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[533]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[533]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[532]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[532]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[531]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[531]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[530]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[530]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[529]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[529]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[528]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[528]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[527]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[527]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[526]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[526]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[525]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[525]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[524]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[524]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[523]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[523]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[522]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[522]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[521]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[521]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[520]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[520]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[519]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[519]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[518]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[518]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[517]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[517]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[516]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[516]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[515]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[515]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[514]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[514]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[513]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[513]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[512]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[512]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[511]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[511]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[510]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[510]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[509]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[509]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[508]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[508]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[507]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[507]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[506]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[506]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[505]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[505]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[504]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[504]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[503]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[503]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[502]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[502]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[501]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[501]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[500]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[500]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[499]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[499]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[498]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[498]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[497]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[497]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[496]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[496]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[495]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[495]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[494]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[494]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[493]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[493]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[492]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[492]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[491]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[491]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[490]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[490]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[489]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[489]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[488]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[488]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[487]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[487]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[486]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[486]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[485]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[485]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[484]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[484]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[483]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[483]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[482]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[482]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[481]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[481]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[480]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[480]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[479]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[479]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[478]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[478]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[477]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[477]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[476]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[476]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[475]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[475]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[474]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[474]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[473]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[473]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[472]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[472]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[471]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[471]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[470]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[470]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[469]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[469]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[468]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[468]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[467]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[467]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[466]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[466]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[465]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[465]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[464]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[464]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[463]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[463]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[462]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[462]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[461]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[461]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[460]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[460]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[459]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[459]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[458]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[458]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[457]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[457]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[456]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[456]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[455]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[455]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[454]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[454]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[453]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[453]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[452]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[452]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[451]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[451]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[450]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[450]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[449]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[449]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[448]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[448]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[447]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[447]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[446]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[446]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[445]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[445]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[444]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[444]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[443]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[443]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[442]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[442]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[441]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[441]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[440]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[440]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[439]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[439]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[438]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[438]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[437]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[437]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[436]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[436]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[435]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[435]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[434]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[434]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[433]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[433]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[432]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[432]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[431]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[431]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[430]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[430]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[429]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[429]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[428]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[428]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[427]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[427]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[426]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[426]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[425]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[425]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[424]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[424]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[423]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[423]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[422]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[422]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[421]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[421]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[420]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[420]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[419]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[419]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[418]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[418]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[417]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[417]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[416]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[416]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[415]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[415]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[414]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[414]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[413]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[413]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[412]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[412]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[411]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[411]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[410]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[410]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[409]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[409]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[408]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[408]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[407]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[407]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[406]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[406]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[405]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[405]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[404]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[404]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[403]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[403]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[402]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[402]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[401]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[401]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[400]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[400]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[399]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[399]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[398]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[398]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[397]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[397]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[396]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[396]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[395]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[395]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[394]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[394]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[393]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[393]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[392]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[392]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[391]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[391]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[390]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[390]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[389]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[389]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[388]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[388]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[387]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[387]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[386]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[386]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[385]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[385]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[384]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[384]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[383]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[383]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[382]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[382]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[381]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[381]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[380]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[380]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[379]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[379]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[378]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[378]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[377]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[377]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[376]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[376]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[375]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[375]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[374]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[374]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[373]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[373]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[372]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[372]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[371]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[371]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[370]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[370]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[369]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[369]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[368]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[368]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[367]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[367]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[366]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[366]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[365]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[365]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[364]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[364]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[363]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[363]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[362]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[362]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[361]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[361]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[360]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[360]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[359]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[359]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[358]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[358]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[357]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[357]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[356]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[356]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[355]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[355]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[354]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[354]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[353]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[353]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[352]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[352]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[351]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[351]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[350]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[350]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[349]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[349]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[348]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[348]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[347]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[347]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[346]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[346]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[345]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[345]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[344]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[344]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[343]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[343]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[342]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[342]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[341]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[341]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[340]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[340]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[339]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[339]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[338]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[338]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[337]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[337]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[336]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[336]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[335]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[335]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[334]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[334]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[333]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[333]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[332]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[332]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[331]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[331]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[330]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[330]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[329]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[329]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[328]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[328]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[327]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[327]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[326]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[326]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[325]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[325]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[324]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[324]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[323]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[323]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[322]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[322]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[321]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[321]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[320]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[320]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[319]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[319]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[318]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[318]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[317]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[317]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[316]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[316]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[315]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[315]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[314]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[314]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[313]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[313]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[312]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[312]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[311]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[311]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[310]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[310]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[309]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[309]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[308]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[308]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[307]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[307]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[306]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[306]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[305]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[305]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[304]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[304]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[303]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[303]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[302]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[302]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[301]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[301]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[300]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[300]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[299]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[299]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[298]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[298]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[297]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[297]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[296]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[296]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[295]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[295]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[294]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[294]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[293]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[293]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[292]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[292]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[291]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[291]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[290]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[290]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[289]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[289]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[288]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[288]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[287]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[287]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[286]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[286]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[285]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[285]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[284]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[284]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[283]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[283]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[282]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[282]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[281]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[281]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[280]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[280]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[279]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[279]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[278]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[278]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[277]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[277]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[276]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[276]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[275]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[275]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[274]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[274]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[273]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[273]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[272]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[272]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[271]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[271]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[270]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[270]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[269]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[269]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[268]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[268]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[267]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[267]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[266]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[266]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[265]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[265]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[264]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[264]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[263]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[263]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[262]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[262]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[261]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[261]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[260]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[260]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[259]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[259]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[258]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[258]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[257]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[257]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[256]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[256]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[255]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[255]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[254]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[254]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[253]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[253]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[252]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[252]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[251]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[251]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[250]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[250]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[249]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[249]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[248]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[248]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[247]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[247]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[246]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[246]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[245]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[245]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[244]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[244]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[243]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[243]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[242]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[242]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[241]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[241]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[240]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[240]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[239]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[239]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[238]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[238]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[237]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[237]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[236]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[236]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[235]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[235]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[234]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[234]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[233]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[233]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[232]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[232]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[231]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[231]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[230]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[230]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[229]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[229]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[228]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[228]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[227]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[227]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[226]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[226]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[225]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[225]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[224]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[224]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[223]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[223]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[222]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[222]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[221]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[221]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[220]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[220]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[219]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[219]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[218]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[218]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[217]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[217]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[216]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[216]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[215]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[215]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[214]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[214]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[213]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[213]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[212]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[212]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[211]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[211]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[210]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[210]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[209]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[209]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[208]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[208]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[207]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[207]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[206]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[206]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[205]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[205]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[204]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[204]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[203]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[203]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[202]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[202]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[201]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[201]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[200]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[200]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[199]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[199]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[198]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[198]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[197]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[197]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[196]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[196]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[195]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[195]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[194]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[194]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[193]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[193]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[192]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[192]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[191]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[191]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[190]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[190]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[189]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[189]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[188]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[188]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[187]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[187]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[186]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[186]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[185]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[185]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[184]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[184]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[183]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[183]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[182]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[182]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[181]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[181]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[180]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[180]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[179]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[179]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[178]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[178]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[177]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[177]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[176]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[176]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[175]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[175]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[174]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[174]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[173]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[173]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[172]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[172]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[171]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[171]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[170]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[170]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[169]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[169]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[168]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[168]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[167]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[167]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[166]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[166]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[165]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[165]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[164]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[164]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[163]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[163]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[162]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[162]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[161]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[161]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[160]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[160]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[159]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[159]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[158]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[158]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[157]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[157]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[156]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[156]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[155]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[155]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[154]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[154]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[153]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[153]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[152]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[152]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[151]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[151]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[150]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[150]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[149]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[149]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[148]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[148]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[147]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[147]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[146]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[146]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[145]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[145]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[144]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[144]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[143]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[143]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[142]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[142]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[141]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[141]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[140]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[140]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[139]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[139]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[138]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[138]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[137]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[137]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[136]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[136]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[135]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[135]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[134]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[134]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[133]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[133]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[132]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[132]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[131]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[131]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[130]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[130]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[129]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[129]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[128]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[128]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[127]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[127]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[126]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[126]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[125]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[125]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[124]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[124]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[123]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[123]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[122]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[122]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[121]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[121]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[120]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[120]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[119]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[119]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[118]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[118]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[117]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[117]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[116]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[116]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[115]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[115]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[114]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[114]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[113]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[113]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[112]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[112]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[111]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[111]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[110]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[110]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[109]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[109]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[108]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[108]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[107]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[107]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[106]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[106]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[105]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[105]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[104]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[104]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[103]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[103]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[102]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[102]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[101]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[101]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[100]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[100]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[99]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[99]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[98]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[98]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[97]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[97]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[96]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[96]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[95]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[95]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[94]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[94]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[93]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[93]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[92]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[92]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[91]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[91]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[90]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[90]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[89]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[89]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[88]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[88]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[87]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[87]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[86]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[86]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[85]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[85]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[84]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[84]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[83]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[83]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[82]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[82]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[81]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[81]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[80]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[80]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[79]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[79]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[78]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[78]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[77]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[77]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[76]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[76]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[75]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[75]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[74]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[74]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[73]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[73]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[72]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[72]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[71]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[71]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[70]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[70]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[69]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[69]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[68]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[68]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[67]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[67]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[66]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[66]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[65]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[65]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[64]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[64]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[63]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[62]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[61]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[60]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[59]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[58]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[57]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[56]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[55]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[54]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[53]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[52]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[51]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[50]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[49]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[48]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[47]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[46]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[45]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[44]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[43]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[42]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[41]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[40]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[39]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[38]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[37]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[36]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[35]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[34]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[33]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[32]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[31]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[30]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[29]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[28]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[27]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[26]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports lce_data_resp_v_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_data_resp_v_o] +set_output_delay -clock CLK -max 0.6 [get_ports lce_cmd_ready_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_cmd_ready_o] +set_output_delay -clock CLK -max 0.6 [get_ports lce_data_cmd_ready_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_data_cmd_ready_o] +set_output_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_ready_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_ready_o] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[538]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[538]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[537]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[537]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[536]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[536]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[535]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[535]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[534]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[534]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[533]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[533]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[532]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[532]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[531]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[531]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[530]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[530]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[529]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[529]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[528]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[528]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[527]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[527]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[526]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[526]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[525]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[525]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[524]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[524]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[523]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[523]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[522]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[522]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[521]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[521]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[520]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[520]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[519]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[519]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[518]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[518]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[517]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[517]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[516]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[516]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[515]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[515]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[514]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[514]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[513]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[513]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[512]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[512]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[511]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[511]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[510]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[510]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[509]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[509]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[508]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[508]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[507]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[507]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[506]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[506]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[505]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[505]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[504]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[504]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[503]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[503]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[502]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[502]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[501]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[501]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[500]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[500]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[499]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[499]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[498]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[498]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[497]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[497]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[496]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[496]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[495]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[495]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[494]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[494]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[493]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[493]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[492]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[492]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[491]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[491]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[490]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[490]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[489]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[489]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[488]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[488]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[487]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[487]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[486]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[486]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[485]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[485]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[484]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[484]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[483]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[483]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[482]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[482]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[481]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[481]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[480]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[480]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[479]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[479]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[478]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[478]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[477]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[477]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[476]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[476]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[475]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[475]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[474]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[474]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[473]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[473]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[472]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[472]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[471]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[471]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[470]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[470]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[469]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[469]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[468]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[468]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[467]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[467]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[466]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[466]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[465]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[465]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[464]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[464]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[463]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[463]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[462]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[462]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[461]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[461]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[460]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[460]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[459]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[459]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[458]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[458]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[457]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[457]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[456]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[456]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[455]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[455]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[454]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[454]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[453]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[453]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[452]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[452]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[451]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[451]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[450]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[450]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[449]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[449]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[448]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[448]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[447]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[447]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[446]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[446]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[445]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[445]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[444]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[444]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[443]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[443]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[442]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[442]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[441]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[441]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[440]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[440]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[439]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[439]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[438]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[438]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[437]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[437]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[436]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[436]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[435]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[435]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[434]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[434]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[433]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[433]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[432]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[432]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[431]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[431]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[430]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[430]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[429]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[429]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[428]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[428]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[427]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[427]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[426]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[426]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[425]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[425]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[424]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[424]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[423]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[423]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[422]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[422]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[421]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[421]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[420]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[420]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[419]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[419]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[418]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[418]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[417]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[417]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[416]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[416]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[415]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[415]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[414]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[414]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[413]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[413]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[412]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[412]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[411]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[411]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[410]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[410]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[409]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[409]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[408]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[408]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[407]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[407]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[406]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[406]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[405]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[405]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[404]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[404]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[403]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[403]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[402]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[402]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[401]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[401]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[400]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[400]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[399]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[399]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[398]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[398]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[397]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[397]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[396]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[396]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[395]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[395]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[394]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[394]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[393]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[393]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[392]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[392]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[391]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[391]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[390]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[390]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[389]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[389]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[388]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[388]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[387]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[387]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[386]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[386]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[385]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[385]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[384]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[384]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[383]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[383]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[382]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[382]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[381]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[381]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[380]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[380]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[379]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[379]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[378]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[378]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[377]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[377]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[376]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[376]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[375]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[375]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[374]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[374]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[373]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[373]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[372]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[372]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[371]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[371]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[370]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[370]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[369]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[369]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[368]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[368]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[367]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[367]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[366]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[366]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[365]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[365]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[364]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[364]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[363]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[363]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[362]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[362]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[361]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[361]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[360]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[360]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[359]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[359]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[358]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[358]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[357]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[357]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[356]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[356]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[355]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[355]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[354]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[354]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[353]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[353]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[352]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[352]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[351]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[351]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[350]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[350]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[349]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[349]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[348]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[348]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[347]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[347]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[346]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[346]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[345]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[345]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[344]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[344]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[343]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[343]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[342]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[342]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[341]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[341]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[340]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[340]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[339]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[339]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[338]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[338]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[337]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[337]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[336]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[336]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[335]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[335]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[334]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[334]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[333]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[333]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[332]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[332]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[331]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[331]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[330]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[330]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[329]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[329]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[328]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[328]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[327]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[327]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[326]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[326]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[325]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[325]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[324]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[324]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[323]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[323]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[322]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[322]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[321]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[321]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[320]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[320]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[319]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[319]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[318]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[318]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[317]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[317]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[316]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[316]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[315]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[315]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[314]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[314]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[313]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[313]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[312]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[312]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[311]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[311]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[310]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[310]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[309]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[309]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[308]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[308]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[307]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[307]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[306]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[306]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[305]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[305]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[304]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[304]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[303]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[303]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[302]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[302]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[301]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[301]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[300]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[300]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[299]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[299]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[298]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[298]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[297]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[297]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[296]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[296]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[295]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[295]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[294]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[294]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[293]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[293]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[292]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[292]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[291]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[291]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[290]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[290]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[289]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[289]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[288]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[288]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[287]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[287]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[286]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[286]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[285]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[285]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[284]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[284]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[283]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[283]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[282]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[282]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[281]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[281]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[280]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[280]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[279]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[279]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[278]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[278]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[277]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[277]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[276]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[276]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[275]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[275]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[274]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[274]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[273]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[273]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[272]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[272]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[271]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[271]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[270]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[270]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[269]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[269]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[268]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[268]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[267]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[267]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[266]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[266]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[265]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[265]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[264]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[264]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[263]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[263]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[262]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[262]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[261]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[261]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[260]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[260]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[259]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[259]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[258]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[258]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[257]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[257]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[256]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[256]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[255]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[255]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[254]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[254]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[253]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[253]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[252]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[252]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[251]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[251]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[250]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[250]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[249]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[249]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[248]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[248]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[247]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[247]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[246]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[246]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[245]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[245]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[244]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[244]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[243]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[243]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[242]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[242]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[241]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[241]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[240]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[240]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[239]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[239]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[238]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[238]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[237]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[237]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[236]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[236]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[235]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[235]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[234]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[234]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[233]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[233]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[232]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[232]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[231]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[231]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[230]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[230]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[229]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[229]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[228]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[228]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[227]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[227]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[226]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[226]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[225]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[225]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[224]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[224]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[223]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[223]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[222]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[222]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[221]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[221]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[220]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[220]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[219]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[219]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[218]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[218]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[217]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[217]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[216]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[216]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[215]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[215]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[214]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[214]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[213]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[213]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[212]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[212]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[211]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[211]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[210]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[210]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[209]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[209]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[208]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[208]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[207]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[207]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[206]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[206]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[205]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[205]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[204]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[204]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[203]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[203]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[202]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[202]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[201]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[201]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[200]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[200]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[199]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[199]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[198]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[198]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[197]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[197]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[196]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[196]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[195]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[195]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[194]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[194]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[193]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[193]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[192]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[192]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[191]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[191]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[190]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[190]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[189]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[189]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[188]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[188]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[187]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[187]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[186]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[186]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[185]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[185]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[184]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[184]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[183]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[183]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[182]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[182]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[181]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[181]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[180]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[180]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[179]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[179]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[178]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[178]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[177]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[177]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[176]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[176]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[175]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[175]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[174]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[174]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[173]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[173]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[172]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[172]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[171]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[171]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[170]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[170]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[169]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[169]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[168]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[168]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[167]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[167]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[166]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[166]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[165]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[165]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[164]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[164]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[163]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[163]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[162]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[162]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[161]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[161]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[160]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[160]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[159]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[159]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[158]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[158]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[157]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[157]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[156]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[156]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[155]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[155]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[154]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[154]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[153]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[153]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[152]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[152]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[151]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[151]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[150]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[150]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[149]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[149]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[148]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[148]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[147]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[147]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[146]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[146]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[145]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[145]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[144]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[144]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[143]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[143]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[142]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[142]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[141]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[141]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[140]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[140]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[139]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[139]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[138]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[138]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[137]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[137]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[136]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[136]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[135]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[135]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[134]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[134]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[133]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[133]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[132]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[132]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[131]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[131]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[130]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[130]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[129]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[129]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[128]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[128]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[127]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[127]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[126]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[126]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[125]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[125]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[124]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[124]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[123]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[123]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[122]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[122]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[121]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[121]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[120]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[120]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[119]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[119]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[118]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[118]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[117]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[117]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[116]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[116]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[115]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[115]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[114]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[114]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[113]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[113]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[112]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[112]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[111]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[111]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[110]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[110]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[109]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[109]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[108]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[108]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[107]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[107]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[106]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[106]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[105]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[105]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[104]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[104]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[103]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[103]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[102]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[102]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[101]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[101]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[100]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[100]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[99]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[99]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[98]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[98]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[97]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[97]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[96]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[96]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[95]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[95]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[94]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[94]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[93]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[93]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[92]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[92]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[91]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[91]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[90]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[90]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[89]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[89]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[88]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[88]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[87]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[87]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[86]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[86]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[85]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[85]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[84]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[84]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[83]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[83]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[82]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[82]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[81]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[81]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[80]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[80]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[79]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[79]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[78]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[78]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[77]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[77]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[76]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[76]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[75]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[75]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[74]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[74]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[73]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[73]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[72]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[72]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[71]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[71]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[70]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[70]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[69]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[69]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[68]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[68]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[67]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[67]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[66]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[66]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[65]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[65]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[64]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[64]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[63]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[62]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[61]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[60]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[59]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[58]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[57]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[56]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[55]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[54]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[53]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[52]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[51]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[50]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[49]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[48]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[47]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[46]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[45]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[44]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[43]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[42]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[41]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[40]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[39]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[38]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[37]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[36]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[35]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[34]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[33]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[32]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[31]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[30]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[29]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[28]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[27]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[26]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_v_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_v_o] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[377]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[377]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[376]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[376]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[375]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[375]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[374]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[374]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[373]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[373]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[372]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[372]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[371]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[371]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[370]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[370]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[369]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[369]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[368]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[368]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[367]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[367]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[366]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[366]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[365]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[365]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[364]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[364]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[363]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[363]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[362]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[362]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[361]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[361]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[360]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[360]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[359]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[359]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[358]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[358]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[357]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[357]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[356]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[356]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[355]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[355]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[354]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[354]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[353]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[353]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[352]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[352]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[351]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[351]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[350]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[350]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[349]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[349]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[348]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[348]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[347]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[347]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[346]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[346]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[345]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[345]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[344]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[344]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[343]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[343]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[342]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[342]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[341]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[341]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[340]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[340]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[339]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[339]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[338]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[338]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[337]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[337]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[336]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[336]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[335]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[335]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[334]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[334]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[333]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[333]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[332]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[332]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[331]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[331]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[330]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[330]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[329]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[329]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[328]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[328]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[327]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[327]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[326]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[326]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[325]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[325]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[324]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[324]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[323]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[323]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[322]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[322]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[321]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[321]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[320]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[320]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[319]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[319]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[318]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[318]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[317]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[317]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[316]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[316]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[315]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[315]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[314]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[314]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[313]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[313]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[312]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[312]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[311]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[311]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[310]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[310]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[309]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[309]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[308]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[308]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[307]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[307]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[306]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[306]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[305]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[305]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[304]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[304]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[303]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[303]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[302]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[302]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[301]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[301]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[300]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[300]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[299]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[299]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[298]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[298]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[297]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[297]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[296]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[296]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[295]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[295]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[294]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[294]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[293]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[293]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[292]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[292]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[291]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[291]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[290]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[290]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[289]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[289]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[288]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[288]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[287]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[287]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[286]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[286]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[285]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[285]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[284]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[284]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[283]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[283]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[282]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[282]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[281]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[281]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[280]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[280]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[279]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[279]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[278]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[278]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[277]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[277]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[276]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[276]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[275]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[275]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[274]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[274]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[273]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[273]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[272]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[272]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[271]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[271]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[270]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[270]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[269]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[269]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[268]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[268]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[267]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[267]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[266]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[266]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[265]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[265]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[264]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[264]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[263]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[263]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[262]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[262]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[261]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[261]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[260]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[260]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[259]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[259]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[258]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[258]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[257]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[257]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[256]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[256]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[255]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[255]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[254]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[254]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[253]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[253]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[252]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[252]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[251]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[251]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[250]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[250]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[249]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[249]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[248]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[248]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[247]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[247]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[246]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[246]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[245]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[245]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[244]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[244]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[243]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[243]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[242]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[242]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[241]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[241]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[240]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[240]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[239]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[239]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[238]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[238]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[237]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[237]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[236]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[236]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[235]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[235]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[234]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[234]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[233]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[233]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[232]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[232]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[231]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[231]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[230]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[230]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[229]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[229]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[228]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[228]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[227]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[227]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[226]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[226]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[225]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[225]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[224]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[224]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[223]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[223]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[222]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[222]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[221]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[221]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[220]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[220]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[219]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[219]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[218]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[218]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[217]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[217]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[216]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[216]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[215]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[215]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[214]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[214]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[213]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[213]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[212]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[212]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[211]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[211]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[210]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[210]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[209]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[209]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[208]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[208]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[207]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[207]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[206]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[206]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[205]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[205]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[204]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[204]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[203]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[203]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[202]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[202]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[201]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[201]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[200]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[200]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[199]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[199]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[198]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[198]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[197]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[197]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[196]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[196]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[195]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[195]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[194]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[194]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[193]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[193]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[192]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[192]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[191]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[191]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[190]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[190]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[189]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[189]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[188]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[188]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[187]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[187]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[186]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[186]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[185]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[185]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[184]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[184]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[183]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[183]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[182]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[182]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[181]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[181]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[180]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[180]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[179]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[179]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[178]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[178]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[177]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[177]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[176]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[176]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[175]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[175]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[174]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[174]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[173]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[173]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[172]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[172]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[171]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[171]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[170]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[170]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[169]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[169]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[168]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[168]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[167]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[167]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[166]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[166]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[165]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[165]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[164]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[164]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[163]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[163]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[162]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[162]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[161]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[161]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[160]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[160]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[159]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[159]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[158]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[158]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[157]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[157]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[156]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[156]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[155]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[155]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[154]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[154]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[153]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[153]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[152]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[152]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[151]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[151]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[150]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[150]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[149]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[149]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[148]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[148]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[147]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[147]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[146]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[146]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[145]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[145]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[144]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[144]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[143]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[143]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[142]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[142]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[141]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[141]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[140]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[140]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[139]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[139]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[138]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[138]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[137]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[137]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[136]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[136]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[135]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[135]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[134]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[134]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[133]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[133]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[132]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[132]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[131]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[131]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[130]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[130]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[129]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[129]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[128]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[128]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[127]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[127]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[126]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[126]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[125]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[125]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[124]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[124]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[123]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[123]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[122]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[122]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[121]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[121]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[120]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[120]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[119]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[119]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[118]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[118]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[117]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[117]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[116]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[116]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[115]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[115]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[114]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[114]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[113]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[113]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[112]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[112]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[111]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[111]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[110]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[110]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[109]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[109]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[108]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[108]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[107]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[107]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[106]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[106]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[105]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[105]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[104]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[104]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[103]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[103]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[102]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[102]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[101]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[101]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[100]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[100]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[99]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[99]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[98]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[98]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[97]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[97]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[96]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[96]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[95]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[95]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[94]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[94]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[93]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[93]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[92]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[92]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[91]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[91]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[90]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[90]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[89]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[89]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[88]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[88]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[87]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[87]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[86]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[86]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[85]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[85]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[84]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[84]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[83]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[83]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[82]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[82]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[81]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[81]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[80]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[80]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[79]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[79]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[78]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[78]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[77]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[77]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[76]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[76]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[75]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[75]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[74]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[74]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[73]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[73]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[72]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[72]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[71]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[71]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[70]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[70]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[69]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[69]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[68]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[68]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[67]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[67]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[66]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[66]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[65]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[65]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[64]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[64]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[63]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[62]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[61]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[60]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[59]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[58]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[57]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[56]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[55]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[54]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[53]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[52]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[51]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[50]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[49]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[48]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[47]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[46]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[45]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[44]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[43]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[42]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[41]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[40]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[39]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[38]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[37]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[36]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[35]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[34]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[33]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[32]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[31]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[30]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[29]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[28]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[27]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[26]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[127]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[127]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[126]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[126]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[125]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[125]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[124]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[124]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[123]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[123]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[122]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[122]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[121]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[121]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[120]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[120]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[119]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[119]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[118]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[118]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[117]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[117]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[116]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[116]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[115]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[115]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[114]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[114]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[113]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[113]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[112]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[112]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[111]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[111]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[110]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[110]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[109]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[109]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[108]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[108]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[107]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[107]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[106]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[106]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[105]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[105]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[104]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[104]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[103]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[103]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[102]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[102]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[101]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[101]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[100]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[100]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[99]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[99]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[98]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[98]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[97]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[97]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[96]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[96]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[95]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[95]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[94]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[94]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[93]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[93]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[92]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[92]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[91]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[91]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[90]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[90]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[89]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[89]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[88]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[88]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[87]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[87]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[86]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[86]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[85]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[85]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[84]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[84]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[83]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[83]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[82]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[82]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[81]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[81]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[80]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[80]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[79]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[79]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[78]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[78]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[77]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[77]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[76]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[76]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[75]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[75]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[74]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[74]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[73]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[73]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[72]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[72]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[71]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[71]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[70]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[70]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[69]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[69]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[68]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[68]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[67]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[67]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[66]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[66]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[65]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[65]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[64]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[64]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[63]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[62]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[61]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[60]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[59]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[58]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[57]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[56]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[55]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[54]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[53]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[52]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[51]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[50]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[49]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[48]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[47]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[46]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[45]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[44]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[43]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[42]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[41]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[40]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[39]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[38]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[37]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[36]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[35]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[34]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[33]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[32]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[31]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[30]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[29]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[28]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[27]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[26]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[0]}] diff --git a/flow/designs/nangate45/bp_be_top/io.tcl b/flow/designs/nangate45/bp_be_top/io.tcl index b3bbef4631..713f1d0db0 100644 --- a/flow/designs/nangate45/bp_be_top/io.tcl +++ b/flow/designs/nangate45/bp_be_top/io.tcl @@ -1 +1 @@ -exclude_io_pin_region -region left:500-800 -region right:500-800 -region top:* \ No newline at end of file +exclude_io_pin_region -region left:500-800 -region right:500-800 -region top:* diff --git a/flow/designs/nangate45/bp_be_top/rules-base.json b/flow/designs/nangate45/bp_be_top/rules-base.json index 7db8d96863..f886e74244 100644 --- a/flow/designs/nangate45/bp_be_top/rules-base.json +++ b/flow/designs/nangate45/bp_be_top/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 298541, + "value": 288926, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 63823, + "value": 62588, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 5550, + "value": 5442, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 5550, + "value": 5442, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.76, + "value": -0.35, "compare": ">=" }, "finish__design__instance__area": { - "value": 302367, + "value": 290373, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 2775, + "value": 2721, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -33.25, + "value": -22.31, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/bp_fe_top/config.mk b/flow/designs/nangate45/bp_fe_top/config.mk index 3af39f39c3..249771d43d 100644 --- a/flow/designs/nangate45/bp_fe_top/config.mk +++ b/flow/designs/nangate45/bp_fe_top/config.mk @@ -4,11 +4,6 @@ export PLATFORM = nangate45 export SYNTH_HIERARCHICAL = 1 # -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 12 -export RTLMP_MIN_MACRO = 4 export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v @@ -29,8 +24,10 @@ export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io.tcl export MACRO_PLACE_HALO = 10 10 -export PLACE_DENSITY_LB_ADDON = 0.10 -export PLACE_DENSITY_MAX_POST_HOLD = 0.12 +export PLACE_DENSITY_LB_ADDON = 0.11 +export PLACE_DENSITY_MAX_POST_HOLD = 0.13 export TNS_END_PERCENT = 100 export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl + +export GPL_KEEP_OVERFLOW = 0 diff --git a/flow/designs/nangate45/bp_fe_top/constraint.sdc b/flow/designs/nangate45/bp_fe_top/constraint.sdc index b2d5405cf1..7428491fbe 100644 --- a/flow/designs/nangate45/bp_fe_top/constraint.sdc +++ b/flow/designs/nangate45/bp_fe_top/constraint.sdc @@ -1,4 +1,3 @@ - set clk_period 1.8 create_clock [get_ports clk_i] -name CLK -period $clk_period set io_delay [expr $clk_period * .2] diff --git a/flow/designs/nangate45/bp_fe_top/io.tcl b/flow/designs/nangate45/bp_fe_top/io.tcl index 8e24fc28ea..82d99e921d 100644 --- a/flow/designs/nangate45/bp_fe_top/io.tcl +++ b/flow/designs/nangate45/bp_fe_top/io.tcl @@ -1 +1 @@ -exclude_io_pin_region -region left:400-700 -region right:400-700 -region top:* \ No newline at end of file +exclude_io_pin_region -region left:400-700 -region right:400-700 -region top:* diff --git a/flow/designs/nangate45/bp_fe_top/rules-base.json b/flow/designs/nangate45/bp_fe_top/rules-base.json index d1aee0a272..8ae464c9af 100644 --- a/flow/designs/nangate45/bp_fe_top/rules-base.json +++ b/flow/designs/nangate45/bp_fe_top/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 261584, + "value": 252534, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 40888, + "value": 39729, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 3556, + "value": 3455, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 3556, + "value": 3455, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 2111490, + "value": 2081448, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,19 +48,19 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.12, + "value": -0.21, "compare": ">=" }, "finish__design__instance__area": { - "value": 263398, + "value": 254470, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 1778, + "value": 1727, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 2500, + "value": 860, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/nangate45/bp_multi_top/config.mk b/flow/designs/nangate45/bp_multi_top/config.mk index 685d4564cf..e05d37d2e5 100644 --- a/flow/designs/nangate45/bp_multi_top/config.mk +++ b/flow/designs/nangate45/bp_multi_top/config.mk @@ -4,11 +4,6 @@ export PLATFORM = nangate45 export SYNTH_HIERARCHICAL = 1 # -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 12 -export RTLMP_MIN_MACRO = 4 export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v diff --git a/flow/designs/nangate45/bp_multi_top/constraint.sdc b/flow/designs/nangate45/bp_multi_top/constraint.sdc index f9be728c02..24d87fe369 100644 --- a/flow/designs/nangate45/bp_multi_top/constraint.sdc +++ b/flow/designs/nangate45/bp_multi_top/constraint.sdc @@ -1,2906 +1,2905 @@ - -create_clock [get_ports clk_i] -name CLK -period 4.8 -waveform {0 2.4} -set_input_delay -clock CLK -max 1.8 [get_ports reset_i] -set_input_delay -clock CLK -min 0.6 [get_ports reset_i] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[95]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[95]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[94]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[94]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[93]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[93]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[92]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[92]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[91]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[91]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[90]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[90]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[89]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[89]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[88]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[88]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[87]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[87]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[86]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[86]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[85]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[85]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[84]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[84]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[83]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[83]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[82]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[82]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[81]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[81]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[80]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[80]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[79]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[79]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[78]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[78]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[77]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[77]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[76]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[76]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[75]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[75]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[74]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[74]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[73]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[73]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[72]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[72]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[71]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[71]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[70]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[70]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[69]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[69]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[68]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[68]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[67]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[67]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[66]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[66]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[65]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[65]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[64]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[64]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[63]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[63]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[62]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[62]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[61]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[61]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[60]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[60]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[59]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[59]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[58]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[58]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[57]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[57]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[56]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[56]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[55]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[55]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[54]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[54]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[53]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[53]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[52]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[52]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[51]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[51]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[50]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[50]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[49]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[49]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[48]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[48]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[47]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[47]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[46]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[46]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[45]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[45]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[44]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[44]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[43]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[43]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[42]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[42]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[41]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[41]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[40]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[40]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[39]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[39]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[38]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[38]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[37]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[37]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[36]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[36]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[35]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[34]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[33]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[32]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[31]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[30]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[29]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[28]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[27]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[26]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[25]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[24]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[23]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[22]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[21]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[20]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[19]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[18]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[17]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[16]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[15]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[14]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[13]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[12]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[11]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[10]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[9]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[8]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[7]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[6]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[5]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[4]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[3]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[2]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[1]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[57]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[57]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[56]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[56]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[55]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[55]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[54]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[54]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[53]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[53]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[52]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[52]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[51]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[51]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[50]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[50]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[49]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[49]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[48]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[48]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[47]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[47]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[46]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[46]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[45]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[45]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[44]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[44]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[43]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[43]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[42]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[42]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[41]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[41]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[40]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[40]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[39]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[39]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[38]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[38]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[37]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[37]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[36]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[36]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[35]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[34]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[33]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[32]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[31]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[30]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[29]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[28]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[27]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[26]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[25]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[24]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[23]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[22]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[21]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[20]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[19]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[18]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[17]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[16]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[15]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[14]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[13]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[12]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[11]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[10]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[9]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[8]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[7]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[6]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[5]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[4]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[3]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[2]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[1]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_v_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_v_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[541]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[541]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[540]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[540]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[539]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[539]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[538]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[538]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[537]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[537]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[536]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[536]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[535]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[535]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[534]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[534]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[533]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[533]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[532]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[532]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[531]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[531]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[530]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[530]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[529]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[529]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[528]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[528]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[527]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[527]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[526]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[526]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[525]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[525]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[524]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[524]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[523]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[523]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[522]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[522]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[521]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[521]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[520]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[520]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[519]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[519]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[518]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[518]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[517]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[517]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[516]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[516]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[515]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[515]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[514]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[514]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[513]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[513]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[512]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[512]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[511]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[511]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[510]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[510]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[509]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[509]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[508]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[508]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[507]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[507]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[506]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[506]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[505]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[505]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[504]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[504]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[503]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[503]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[502]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[502]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[501]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[501]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[500]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[500]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[499]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[499]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[498]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[498]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[497]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[497]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[496]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[496]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[495]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[495]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[494]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[494]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[493]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[493]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[492]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[492]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[491]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[491]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[490]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[490]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[489]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[489]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[488]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[488]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[487]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[487]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[486]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[486]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[485]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[485]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[484]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[484]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[483]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[483]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[482]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[482]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[481]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[481]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[480]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[480]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[479]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[479]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[478]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[478]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[477]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[477]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[476]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[476]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[475]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[475]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[474]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[474]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[473]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[473]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[472]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[472]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[471]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[471]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[470]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[470]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[469]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[469]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[468]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[468]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[467]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[467]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[466]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[466]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[465]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[465]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[464]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[464]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[463]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[463]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[462]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[462]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[461]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[461]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[460]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[460]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[459]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[459]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[458]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[458]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[457]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[457]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[456]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[456]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[455]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[455]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[454]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[454]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[453]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[453]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[452]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[452]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[451]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[451]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[450]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[450]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[449]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[449]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[448]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[448]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[447]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[447]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[446]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[446]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[445]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[445]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[444]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[444]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[443]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[443]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[442]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[442]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[441]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[441]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[440]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[440]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[439]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[439]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[438]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[438]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[437]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[437]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[436]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[436]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[435]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[435]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[434]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[434]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[433]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[433]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[432]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[432]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[431]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[431]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[430]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[430]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[429]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[429]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[428]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[428]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[427]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[427]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[426]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[426]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[425]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[425]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[424]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[424]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[423]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[423]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[422]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[422]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[421]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[421]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[420]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[420]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[419]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[419]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[418]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[418]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[417]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[417]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[416]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[416]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[415]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[415]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[414]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[414]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[413]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[413]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[412]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[412]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[411]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[411]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[410]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[410]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[409]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[409]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[408]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[408]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[407]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[407]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[406]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[406]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[405]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[405]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[404]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[404]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[403]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[403]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[402]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[402]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[401]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[401]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[400]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[400]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[399]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[399]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[398]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[398]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[397]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[397]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[396]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[396]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[395]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[395]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[394]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[394]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[393]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[393]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[392]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[392]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[391]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[391]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[390]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[390]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[389]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[389]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[388]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[388]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[387]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[387]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[386]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[386]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[385]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[385]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[384]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[384]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[383]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[383]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[382]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[382]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[381]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[381]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[380]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[380]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[379]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[379]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[378]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[378]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[377]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[377]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[376]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[376]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[375]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[375]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[374]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[374]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[373]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[373]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[372]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[372]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[371]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[371]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[370]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[370]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[369]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[369]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[368]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[368]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[367]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[367]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[366]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[366]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[365]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[365]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[364]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[364]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[363]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[363]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[362]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[362]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[361]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[361]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[360]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[360]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[359]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[359]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[358]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[358]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[357]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[357]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[356]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[356]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[355]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[355]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[354]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[354]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[353]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[353]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[352]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[352]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[351]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[351]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[350]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[350]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[349]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[349]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[348]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[348]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[347]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[347]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[346]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[346]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[345]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[345]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[344]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[344]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[343]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[343]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[342]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[342]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[341]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[341]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[340]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[340]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[339]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[339]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[338]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[338]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[337]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[337]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[336]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[336]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[335]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[335]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[334]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[334]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[333]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[333]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[332]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[332]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[331]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[331]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[330]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[330]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[329]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[329]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[328]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[328]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[327]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[327]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[326]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[326]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[325]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[325]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[324]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[324]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[323]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[323]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[322]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[322]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[321]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[321]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[320]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[320]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[319]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[319]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[318]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[318]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[317]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[317]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[316]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[316]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[315]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[315]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[314]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[314]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[313]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[313]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[312]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[312]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[311]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[311]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[310]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[310]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[309]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[309]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[308]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[308]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[307]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[307]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[306]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[306]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[305]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[305]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[304]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[304]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[303]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[303]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[302]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[302]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[301]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[301]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[300]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[300]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[299]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[299]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[298]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[298]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[297]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[297]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[296]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[296]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[295]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[295]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[294]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[294]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[293]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[293]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[292]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[292]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[291]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[291]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[290]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[290]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[289]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[289]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[288]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[288]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[287]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[287]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[286]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[286]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[285]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[285]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[284]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[284]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[283]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[283]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[282]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[282]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[281]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[281]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[280]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[280]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[279]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[279]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[278]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[278]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[277]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[277]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[276]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[276]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[275]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[275]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[274]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[274]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[273]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[273]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[272]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[272]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[271]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[271]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[270]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[270]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[269]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[269]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[268]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[268]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[267]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[267]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[266]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[266]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[265]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[265]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[264]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[264]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[263]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[263]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[262]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[262]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[261]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[261]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[260]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[260]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[259]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[259]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[258]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[258]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[257]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[257]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[256]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[256]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[255]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[255]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[254]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[254]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[253]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[253]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[252]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[252]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[251]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[251]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[250]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[250]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[249]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[249]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[248]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[248]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[247]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[247]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[246]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[246]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[245]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[245]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[244]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[244]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[243]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[243]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[242]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[242]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[241]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[241]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[240]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[240]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[239]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[239]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[238]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[238]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[237]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[237]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[236]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[236]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[235]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[235]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[234]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[234]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[233]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[233]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[232]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[232]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[231]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[231]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[230]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[230]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[229]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[229]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[228]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[228]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[227]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[227]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[226]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[226]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[225]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[225]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[224]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[224]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[223]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[223]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[222]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[222]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[221]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[221]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[220]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[220]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[219]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[219]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[218]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[218]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[217]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[217]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[216]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[216]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[215]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[215]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[214]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[214]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[213]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[213]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[212]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[212]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[211]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[211]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[210]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[210]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[209]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[209]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[208]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[208]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[207]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[207]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[206]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[206]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[205]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[205]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[204]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[204]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[203]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[203]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[202]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[202]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[201]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[201]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[200]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[200]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[199]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[199]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[198]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[198]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[197]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[197]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[196]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[196]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[195]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[195]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[194]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[194]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[193]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[193]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[192]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[192]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[191]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[191]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[190]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[190]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[189]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[189]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[188]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[188]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[187]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[187]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[186]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[186]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[185]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[185]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[184]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[184]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[183]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[183]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[182]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[182]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[181]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[181]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[180]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[180]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[179]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[179]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[178]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[178]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[177]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[177]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[176]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[176]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[175]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[175]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[174]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[174]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[173]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[173]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[172]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[172]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[171]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[171]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[170]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[170]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[169]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[169]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[168]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[168]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[167]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[167]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[166]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[166]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[165]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[165]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[164]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[164]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[163]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[163]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[162]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[162]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[161]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[161]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[160]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[160]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[159]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[159]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[158]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[158]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[157]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[157]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[156]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[156]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[155]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[155]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[154]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[154]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[153]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[153]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[152]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[152]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[151]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[151]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[150]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[150]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[149]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[149]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[148]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[148]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[147]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[147]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[146]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[146]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[145]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[145]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[144]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[144]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[143]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[143]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[142]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[142]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[141]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[141]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[140]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[140]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[139]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[139]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[138]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[138]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[137]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[137]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[136]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[136]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[135]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[135]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[134]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[134]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[133]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[133]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[132]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[132]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[131]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[131]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[130]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[130]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[129]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[129]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[128]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[128]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[127]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[127]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[126]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[126]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[125]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[125]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[124]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[124]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[123]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[123]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[122]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[122]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[121]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[121]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[120]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[120]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[119]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[119]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[118]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[118]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[117]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[117]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[116]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[116]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[115]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[115]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[114]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[114]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[113]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[113]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[112]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[112]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[111]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[111]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[110]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[110]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[109]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[109]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[108]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[108]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[107]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[107]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[106]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[106]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[105]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[105]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[104]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[104]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[103]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[103]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[102]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[102]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[101]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[101]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[100]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[100]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[99]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[99]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[98]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[98]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[97]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[97]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[96]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[96]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[95]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[95]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[94]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[94]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[93]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[93]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[92]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[92]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[91]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[91]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[90]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[90]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[89]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[89]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[88]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[88]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[87]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[87]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[86]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[86]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[85]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[85]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[84]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[84]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[83]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[83]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[82]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[82]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[81]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[81]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[80]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[80]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[79]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[79]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[78]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[78]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[77]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[77]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[76]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[76]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[75]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[75]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[74]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[74]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[73]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[73]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[72]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[72]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[71]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[71]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[70]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[70]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[69]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[69]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[68]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[68]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[67]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[67]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[66]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[66]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[65]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[65]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[64]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[64]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[63]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[63]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[62]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[62]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[61]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[61]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[60]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[60]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[59]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[59]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[58]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[58]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[57]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[57]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[56]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[56]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[55]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[55]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[54]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[54]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[53]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[53]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[52]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[52]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[51]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[51]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[50]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[50]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[49]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[49]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[48]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[48]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[47]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[47]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[46]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[46]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[45]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[45]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[44]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[44]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[43]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[43]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[42]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[42]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[41]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[41]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[40]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[40]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[39]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[39]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[38]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[38]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[37]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[37]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[36]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[36]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[35]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[34]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[33]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[32]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[31]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[30]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[29]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[28]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[27]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[26]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[25]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[24]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[23]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[22]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[21]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[20]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[19]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[18]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[17]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[16]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[15]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[14]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[13]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[12]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[11]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[10]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[9]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[8]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[7]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[6]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[5]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[4]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[3]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[2]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[1]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_v_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_v_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_cmd_yumi_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_cmd_yumi_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_yumi_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_yumi_i[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_resp_ready_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_resp_ready_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_ready_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_ready_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[29]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[28]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[27]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[26]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[25]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[24]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[23]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[22]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[21]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[20]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[19]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[18]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[17]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[16]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[15]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[14]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[13]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[12]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[11]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[10]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[9]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[8]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_v_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_v_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[569]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[569]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[568]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[568]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[567]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[567]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[566]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[566]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[565]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[565]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[564]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[564]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[563]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[563]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[562]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[562]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[561]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[561]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[560]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[560]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[559]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[559]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[558]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[558]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[557]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[557]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[556]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[556]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[555]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[555]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[554]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[554]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[553]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[553]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[552]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[552]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[551]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[551]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[550]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[550]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[549]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[549]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[548]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[548]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[547]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[547]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[546]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[546]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[545]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[545]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[544]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[544]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[543]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[543]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[542]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[542]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[541]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[541]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[540]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[540]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[539]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[539]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[538]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[538]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[537]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[537]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[536]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[536]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[535]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[535]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[534]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[534]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[533]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[533]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[532]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[532]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[531]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[531]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[530]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[530]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[529]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[529]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[528]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[528]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[527]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[527]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[526]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[526]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[525]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[525]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[524]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[524]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[523]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[523]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[522]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[522]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[521]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[521]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[520]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[520]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[519]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[519]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[518]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[518]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[517]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[517]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[516]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[516]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[515]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[515]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[514]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[514]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[513]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[513]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[512]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[512]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[511]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[511]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[510]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[510]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[509]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[509]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[508]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[508]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[507]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[507]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[506]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[506]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[505]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[505]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[504]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[504]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[503]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[503]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[502]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[502]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[501]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[501]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[500]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[500]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[499]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[499]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[498]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[498]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[497]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[497]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[496]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[496]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[495]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[495]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[494]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[494]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[493]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[493]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[492]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[492]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[491]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[491]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[490]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[490]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[489]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[489]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[488]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[488]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[487]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[487]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[486]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[486]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[485]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[485]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[484]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[484]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[483]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[483]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[482]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[482]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[481]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[481]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[480]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[480]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[479]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[479]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[478]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[478]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[477]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[477]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[476]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[476]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[475]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[475]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[474]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[474]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[473]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[473]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[472]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[472]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[471]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[471]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[470]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[470]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[469]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[469]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[468]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[468]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[467]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[467]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[466]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[466]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[465]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[465]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[464]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[464]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[463]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[463]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[462]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[462]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[461]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[461]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[460]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[460]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[459]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[459]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[458]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[458]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[457]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[457]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[456]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[456]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[455]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[455]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[454]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[454]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[453]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[453]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[452]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[452]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[451]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[451]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[450]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[450]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[449]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[449]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[448]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[448]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[447]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[447]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[446]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[446]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[445]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[445]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[444]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[444]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[443]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[443]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[442]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[442]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[441]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[441]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[440]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[440]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[439]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[439]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[438]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[438]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[437]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[437]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[436]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[436]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[435]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[435]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[434]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[434]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[433]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[433]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[432]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[432]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[431]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[431]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[430]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[430]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[429]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[429]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[428]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[428]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[427]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[427]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[426]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[426]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[425]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[425]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[424]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[424]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[423]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[423]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[422]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[422]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[421]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[421]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[420]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[420]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[419]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[419]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[418]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[418]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[417]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[417]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[416]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[416]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[415]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[415]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[414]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[414]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[413]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[413]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[412]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[412]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[411]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[411]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[410]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[410]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[409]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[409]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[408]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[408]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[407]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[407]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[406]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[406]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[405]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[405]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[404]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[404]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[403]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[403]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[402]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[402]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[401]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[401]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[400]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[400]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[399]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[399]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[398]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[398]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[397]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[397]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[396]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[396]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[395]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[395]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[394]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[394]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[393]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[393]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[392]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[392]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[391]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[391]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[390]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[390]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[389]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[389]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[388]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[388]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[387]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[387]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[386]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[386]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[385]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[385]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[384]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[384]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[383]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[383]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[382]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[382]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[381]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[381]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[380]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[380]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[379]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[379]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[378]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[378]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[377]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[377]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[376]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[376]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[375]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[375]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[374]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[374]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[373]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[373]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[372]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[372]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[371]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[371]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[370]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[370]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[369]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[369]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[368]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[368]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[367]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[367]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[366]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[366]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[365]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[365]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[364]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[364]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[363]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[363]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[362]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[362]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[361]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[361]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[360]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[360]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[359]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[359]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[358]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[358]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[357]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[357]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[356]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[356]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[355]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[355]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[354]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[354]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[353]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[353]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[352]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[352]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[351]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[351]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[350]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[350]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[349]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[349]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[348]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[348]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[347]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[347]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[346]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[346]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[345]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[345]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[344]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[344]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[343]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[343]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[342]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[342]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[341]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[341]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[340]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[340]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[339]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[339]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[338]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[338]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[337]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[337]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[336]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[336]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[335]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[335]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[334]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[334]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[333]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[333]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[332]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[332]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[331]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[331]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[330]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[330]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[329]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[329]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[328]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[328]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[327]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[327]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[326]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[326]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[325]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[325]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[324]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[324]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[323]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[323]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[322]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[322]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[321]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[321]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[320]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[320]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[319]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[319]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[318]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[318]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[317]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[317]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[316]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[316]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[315]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[315]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[314]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[314]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[313]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[313]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[312]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[312]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[311]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[311]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[310]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[310]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[309]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[309]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[308]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[308]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[307]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[307]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[306]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[306]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[305]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[305]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[304]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[304]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[303]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[303]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[302]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[302]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[301]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[301]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[300]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[300]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[299]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[299]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[298]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[298]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[297]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[297]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[296]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[296]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[295]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[295]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[294]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[294]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[293]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[293]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[292]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[292]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[291]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[291]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[290]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[290]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[289]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[289]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[288]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[288]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[287]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[287]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[286]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[286]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[285]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[285]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[284]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[284]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[283]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[283]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[282]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[282]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[281]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[281]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[280]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[280]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[279]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[279]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[278]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[278]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[277]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[277]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[276]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[276]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[275]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[275]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[274]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[274]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[273]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[273]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[272]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[272]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[271]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[271]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[270]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[270]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[269]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[269]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[268]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[268]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[267]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[267]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[266]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[266]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[265]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[265]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[264]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[264]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[263]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[263]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[262]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[262]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[261]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[261]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[260]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[260]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[259]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[259]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[258]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[258]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[257]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[257]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[256]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[256]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[255]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[255]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[254]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[254]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[253]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[253]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[252]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[252]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[251]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[251]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[250]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[250]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[249]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[249]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[248]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[248]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[247]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[247]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[246]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[246]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[245]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[245]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[244]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[244]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[243]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[243]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[242]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[242]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[241]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[241]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[240]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[240]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[239]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[239]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[238]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[238]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[237]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[237]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[236]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[236]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[235]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[235]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[234]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[234]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[233]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[233]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[232]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[232]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[231]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[231]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[230]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[230]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[229]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[229]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[228]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[228]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[227]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[227]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[226]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[226]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[225]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[225]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[224]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[224]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[223]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[223]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[222]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[222]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[221]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[221]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[220]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[220]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[219]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[219]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[218]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[218]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[217]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[217]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[216]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[216]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[215]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[215]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[214]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[214]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[213]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[213]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[212]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[212]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[211]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[211]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[210]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[210]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[209]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[209]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[208]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[208]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[207]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[207]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[206]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[206]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[205]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[205]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[204]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[204]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[203]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[203]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[202]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[202]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[201]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[201]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[200]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[200]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[199]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[199]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[198]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[198]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[197]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[197]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[196]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[196]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[195]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[195]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[194]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[194]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[193]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[193]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[192]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[192]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[191]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[191]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[190]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[190]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[189]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[189]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[188]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[188]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[187]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[187]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[186]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[186]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[185]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[185]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[184]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[184]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[183]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[183]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[182]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[182]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[181]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[181]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[180]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[180]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[179]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[179]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[178]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[178]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[177]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[177]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[176]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[176]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[175]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[175]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[174]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[174]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[173]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[173]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[172]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[172]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[171]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[171]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[170]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[170]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[169]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[169]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[168]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[168]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[167]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[167]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[166]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[166]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[165]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[165]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[164]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[164]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[163]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[163]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[162]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[162]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[161]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[161]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[160]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[160]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[159]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[159]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[158]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[158]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[157]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[157]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[156]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[156]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[155]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[155]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[154]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[154]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[153]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[153]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[152]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[152]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[151]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[151]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[150]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[150]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[149]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[149]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[148]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[148]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[147]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[147]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[146]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[146]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[145]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[145]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[144]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[144]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[143]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[143]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[142]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[142]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[141]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[141]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[140]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[140]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[139]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[139]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[138]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[138]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[137]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[137]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[136]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[136]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[135]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[135]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[134]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[134]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[133]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[133]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[132]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[132]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[131]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[131]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[130]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[130]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[129]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[129]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[128]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[128]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[127]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[127]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[126]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[126]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[125]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[125]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[124]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[124]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[123]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[123]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[122]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[122]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[121]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[121]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[120]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[120]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[119]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[119]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[118]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[118]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[117]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[117]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[116]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[116]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[115]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[115]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[114]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[114]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[113]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[113]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[112]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[112]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[111]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[111]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[110]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[110]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[109]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[109]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[108]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[108]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[107]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[107]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[106]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[106]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[105]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[105]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[104]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[104]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[103]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[103]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[102]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[102]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[101]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[101]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[100]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[100]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[99]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[99]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[98]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[98]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[97]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[97]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[96]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[96]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[95]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[95]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[94]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[94]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[93]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[93]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[92]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[92]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[91]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[91]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[90]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[90]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[89]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[89]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[88]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[88]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[87]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[87]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[86]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[86]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[85]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[85]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[84]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[84]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[83]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[83]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[82]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[82]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[81]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[81]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[80]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[80]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[79]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[79]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[78]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[78]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[77]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[77]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[76]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[76]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[75]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[75]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[74]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[74]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[73]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[73]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[72]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[72]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[71]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[71]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[70]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[70]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[69]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[69]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[68]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[68]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[67]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[67]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[66]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[66]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[65]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[65]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[64]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[64]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[63]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[62]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[61]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[60]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[59]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[58]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[57]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[56]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[55]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[54]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[53]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[52]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[51]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[50]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[49]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[48]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[47]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[46]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[45]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[44]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[43]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[42]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[41]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[40]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[39]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[38]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[37]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[36]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[35]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[34]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[33]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[32]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[31]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[30]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[29]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[28]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[27]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[26]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[25]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[24]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[23]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[22]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[21]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[20]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[19]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[18]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[17]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[16]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[15]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[14]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[13]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[12]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[11]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[10]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[9]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[8]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_v_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_v_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_w_v_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_w_v_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_w_v_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_w_v_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[63]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[62]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[61]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[60]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[59]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[58]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[57]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[56]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[55]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[54]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[53]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[52]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[51]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[50]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[49]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[48]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[47]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[46]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[45]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[44]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[43]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[42]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[41]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[40]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[39]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[38]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[37]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[36]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[35]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[34]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[33]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[32]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[31]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[30]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[29]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[28]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[27]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[26]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[25]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[24]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[23]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[22]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[21]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[20]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[19]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[18]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[17]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[16]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[15]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[14]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[13]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[12]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[11]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[10]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[9]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[8]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[63]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[62]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[61]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[60]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[59]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[58]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[57]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[56]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[55]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[54]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[53]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[52]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[51]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[50]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[49]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[48]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[47]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[46]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[45]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[44]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[43]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[42]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[41]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[40]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[39]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[38]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[37]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[36]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[35]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[34]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[33]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[32]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[31]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[30]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[29]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[28]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[27]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[26]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[25]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[24]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[23]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[22]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[21]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[20]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[19]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[18]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[17]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[16]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[15]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[14]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[13]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[12]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[11]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[10]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[9]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[8]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[0]}] +create_clock [get_ports clk_i] -name CLK -period 4.8 -waveform {0 2.4} +set_input_delay -clock CLK -max 1.8 [get_ports reset_i] +set_input_delay -clock CLK -min 0.6 [get_ports reset_i] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[95]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[95]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[94]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[94]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[93]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[93]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[92]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[92]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[91]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[91]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[90]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[90]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[89]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[89]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[88]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[88]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[87]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[87]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[86]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[86]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[85]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[85]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[84]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[84]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[83]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[83]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[82]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[82]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[81]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[81]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[80]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[80]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[79]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[79]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[78]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[78]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[77]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[77]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[76]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[76]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[75]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[75]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[74]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[74]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[73]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[73]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[72]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[72]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[71]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[71]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[70]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[70]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[69]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[69]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[68]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[68]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[67]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[67]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[66]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[66]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[65]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[65]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[64]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[64]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[63]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[63]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[62]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[62]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[61]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[61]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[60]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[60]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[59]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[59]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[58]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[58]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[57]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[57]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[56]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[56]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[55]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[55]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[54]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[54]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[53]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[53]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[52]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[52]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[51]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[51]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[50]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[50]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[49]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[49]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[48]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[48]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[47]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[47]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[46]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[46]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[45]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[45]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[44]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[44]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[43]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[43]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[42]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[42]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[41]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[41]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[40]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[40]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[39]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[39]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[38]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[38]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[37]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[37]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[36]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[36]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[35]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[34]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[33]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[32]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[31]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[30]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[29]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[28]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[27]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[26]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[25]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[24]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[23]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[22]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[21]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[20]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[19]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[18]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[17]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[16]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[15]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[14]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[13]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[12]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[11]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[10]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[9]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[8]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[7]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[6]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[5]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[4]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[3]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[2]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[1]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[0]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[57]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[57]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[56]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[56]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[55]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[55]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[54]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[54]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[53]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[53]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[52]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[52]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[51]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[51]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[50]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[50]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[49]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[49]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[48]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[48]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[47]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[47]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[46]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[46]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[45]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[45]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[44]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[44]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[43]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[43]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[42]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[42]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[41]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[41]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[40]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[40]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[39]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[39]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[38]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[38]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[37]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[37]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[36]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[36]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[35]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[34]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[33]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[32]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[31]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[30]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[29]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[28]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[27]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[26]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[25]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[24]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[23]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[22]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[21]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[20]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[19]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[18]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[17]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[16]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[15]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[14]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[13]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[12]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[11]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[10]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[9]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[8]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[7]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[6]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[5]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[4]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[3]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[2]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[1]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[0]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_v_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_v_i[0]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[541]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[541]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[540]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[540]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[539]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[539]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[538]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[538]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[537]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[537]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[536]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[536]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[535]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[535]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[534]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[534]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[533]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[533]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[532]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[532]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[531]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[531]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[530]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[530]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[529]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[529]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[528]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[528]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[527]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[527]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[526]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[526]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[525]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[525]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[524]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[524]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[523]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[523]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[522]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[522]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[521]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[521]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[520]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[520]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[519]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[519]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[518]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[518]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[517]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[517]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[516]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[516]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[515]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[515]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[514]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[514]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[513]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[513]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[512]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[512]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[511]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[511]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[510]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[510]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[509]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[509]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[508]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[508]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[507]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[507]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[506]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[506]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[505]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[505]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[504]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[504]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[503]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[503]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[502]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[502]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[501]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[501]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[500]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[500]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[499]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[499]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[498]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[498]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[497]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[497]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[496]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[496]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[495]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[495]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[494]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[494]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[493]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[493]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[492]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[492]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[491]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[491]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[490]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[490]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[489]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[489]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[488]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[488]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[487]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[487]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[486]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[486]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[485]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[485]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[484]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[484]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[483]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[483]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[482]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[482]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[481]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[481]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[480]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[480]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[479]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[479]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[478]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[478]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[477]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[477]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[476]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[476]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[475]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[475]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[474]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[474]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[473]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[473]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[472]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[472]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[471]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[471]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[470]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[470]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[469]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[469]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[468]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[468]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[467]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[467]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[466]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[466]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[465]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[465]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[464]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[464]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[463]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[463]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[462]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[462]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[461]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[461]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[460]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[460]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[459]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[459]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[458]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[458]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[457]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[457]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[456]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[456]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[455]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[455]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[454]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[454]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[453]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[453]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[452]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[452]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[451]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[451]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[450]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[450]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[449]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[449]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[448]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[448]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[447]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[447]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[446]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[446]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[445]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[445]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[444]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[444]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[443]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[443]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[442]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[442]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[441]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[441]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[440]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[440]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[439]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[439]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[438]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[438]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[437]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[437]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[436]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[436]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[435]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[435]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[434]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[434]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[433]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[433]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[432]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[432]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[431]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[431]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[430]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[430]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[429]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[429]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[428]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[428]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[427]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[427]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[426]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[426]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[425]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[425]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[424]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[424]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[423]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[423]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[422]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[422]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[421]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[421]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[420]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[420]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[419]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[419]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[418]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[418]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[417]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[417]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[416]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[416]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[415]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[415]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[414]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[414]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[413]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[413]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[412]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[412]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[411]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[411]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[410]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[410]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[409]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[409]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[408]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[408]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[407]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[407]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[406]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[406]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[405]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[405]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[404]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[404]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[403]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[403]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[402]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[402]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[401]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[401]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[400]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[400]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[399]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[399]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[398]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[398]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[397]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[397]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[396]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[396]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[395]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[395]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[394]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[394]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[393]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[393]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[392]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[392]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[391]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[391]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[390]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[390]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[389]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[389]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[388]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[388]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[387]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[387]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[386]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[386]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[385]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[385]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[384]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[384]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[383]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[383]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[382]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[382]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[381]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[381]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[380]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[380]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[379]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[379]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[378]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[378]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[377]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[377]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[376]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[376]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[375]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[375]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[374]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[374]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[373]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[373]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[372]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[372]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[371]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[371]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[370]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[370]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[369]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[369]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[368]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[368]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[367]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[367]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[366]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[366]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[365]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[365]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[364]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[364]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[363]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[363]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[362]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[362]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[361]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[361]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[360]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[360]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[359]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[359]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[358]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[358]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[357]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[357]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[356]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[356]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[355]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[355]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[354]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[354]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[353]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[353]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[352]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[352]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[351]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[351]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[350]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[350]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[349]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[349]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[348]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[348]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[347]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[347]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[346]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[346]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[345]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[345]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[344]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[344]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[343]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[343]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[342]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[342]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[341]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[341]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[340]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[340]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[339]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[339]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[338]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[338]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[337]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[337]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[336]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[336]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[335]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[335]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[334]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[334]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[333]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[333]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[332]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[332]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[331]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[331]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[330]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[330]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[329]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[329]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[328]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[328]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[327]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[327]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[326]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[326]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[325]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[325]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[324]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[324]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[323]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[323]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[322]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[322]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[321]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[321]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[320]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[320]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[319]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[319]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[318]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[318]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[317]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[317]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[316]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[316]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[315]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[315]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[314]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[314]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[313]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[313]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[312]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[312]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[311]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[311]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[310]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[310]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[309]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[309]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[308]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[308]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[307]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[307]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[306]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[306]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[305]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[305]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[304]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[304]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[303]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[303]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[302]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[302]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[301]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[301]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[300]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[300]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[299]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[299]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[298]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[298]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[297]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[297]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[296]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[296]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[295]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[295]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[294]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[294]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[293]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[293]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[292]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[292]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[291]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[291]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[290]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[290]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[289]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[289]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[288]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[288]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[287]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[287]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[286]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[286]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[285]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[285]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[284]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[284]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[283]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[283]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[282]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[282]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[281]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[281]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[280]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[280]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[279]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[279]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[278]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[278]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[277]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[277]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[276]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[276]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[275]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[275]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[274]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[274]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[273]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[273]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[272]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[272]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[271]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[271]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[270]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[270]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[269]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[269]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[268]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[268]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[267]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[267]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[266]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[266]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[265]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[265]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[264]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[264]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[263]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[263]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[262]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[262]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[261]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[261]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[260]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[260]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[259]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[259]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[258]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[258]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[257]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[257]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[256]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[256]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[255]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[255]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[254]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[254]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[253]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[253]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[252]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[252]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[251]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[251]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[250]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[250]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[249]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[249]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[248]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[248]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[247]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[247]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[246]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[246]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[245]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[245]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[244]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[244]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[243]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[243]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[242]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[242]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[241]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[241]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[240]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[240]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[239]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[239]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[238]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[238]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[237]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[237]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[236]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[236]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[235]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[235]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[234]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[234]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[233]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[233]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[232]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[232]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[231]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[231]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[230]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[230]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[229]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[229]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[228]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[228]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[227]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[227]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[226]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[226]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[225]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[225]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[224]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[224]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[223]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[223]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[222]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[222]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[221]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[221]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[220]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[220]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[219]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[219]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[218]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[218]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[217]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[217]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[216]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[216]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[215]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[215]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[214]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[214]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[213]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[213]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[212]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[212]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[211]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[211]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[210]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[210]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[209]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[209]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[208]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[208]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[207]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[207]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[206]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[206]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[205]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[205]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[204]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[204]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[203]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[203]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[202]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[202]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[201]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[201]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[200]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[200]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[199]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[199]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[198]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[198]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[197]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[197]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[196]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[196]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[195]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[195]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[194]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[194]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[193]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[193]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[192]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[192]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[191]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[191]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[190]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[190]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[189]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[189]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[188]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[188]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[187]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[187]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[186]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[186]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[185]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[185]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[184]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[184]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[183]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[183]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[182]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[182]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[181]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[181]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[180]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[180]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[179]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[179]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[178]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[178]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[177]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[177]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[176]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[176]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[175]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[175]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[174]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[174]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[173]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[173]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[172]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[172]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[171]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[171]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[170]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[170]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[169]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[169]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[168]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[168]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[167]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[167]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[166]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[166]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[165]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[165]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[164]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[164]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[163]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[163]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[162]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[162]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[161]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[161]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[160]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[160]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[159]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[159]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[158]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[158]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[157]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[157]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[156]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[156]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[155]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[155]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[154]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[154]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[153]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[153]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[152]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[152]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[151]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[151]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[150]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[150]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[149]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[149]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[148]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[148]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[147]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[147]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[146]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[146]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[145]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[145]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[144]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[144]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[143]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[143]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[142]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[142]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[141]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[141]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[140]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[140]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[139]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[139]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[138]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[138]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[137]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[137]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[136]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[136]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[135]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[135]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[134]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[134]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[133]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[133]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[132]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[132]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[131]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[131]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[130]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[130]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[129]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[129]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[128]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[128]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[127]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[127]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[126]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[126]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[125]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[125]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[124]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[124]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[123]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[123]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[122]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[122]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[121]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[121]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[120]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[120]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[119]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[119]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[118]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[118]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[117]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[117]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[116]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[116]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[115]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[115]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[114]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[114]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[113]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[113]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[112]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[112]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[111]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[111]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[110]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[110]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[109]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[109]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[108]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[108]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[107]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[107]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[106]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[106]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[105]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[105]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[104]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[104]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[103]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[103]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[102]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[102]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[101]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[101]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[100]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[100]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[99]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[99]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[98]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[98]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[97]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[97]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[96]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[96]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[95]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[95]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[94]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[94]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[93]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[93]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[92]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[92]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[91]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[91]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[90]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[90]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[89]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[89]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[88]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[88]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[87]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[87]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[86]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[86]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[85]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[85]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[84]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[84]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[83]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[83]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[82]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[82]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[81]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[81]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[80]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[80]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[79]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[79]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[78]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[78]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[77]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[77]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[76]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[76]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[75]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[75]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[74]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[74]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[73]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[73]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[72]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[72]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[71]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[71]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[70]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[70]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[69]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[69]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[68]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[68]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[67]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[67]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[66]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[66]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[65]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[65]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[64]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[64]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[63]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[63]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[62]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[62]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[61]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[61]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[60]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[60]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[59]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[59]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[58]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[58]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[57]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[57]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[56]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[56]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[55]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[55]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[54]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[54]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[53]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[53]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[52]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[52]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[51]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[51]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[50]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[50]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[49]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[49]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[48]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[48]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[47]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[47]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[46]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[46]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[45]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[45]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[44]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[44]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[43]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[43]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[42]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[42]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[41]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[41]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[40]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[40]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[39]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[39]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[38]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[38]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[37]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[37]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[36]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[36]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[35]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[34]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[33]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[32]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[31]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[30]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[29]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[28]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[27]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[26]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[25]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[24]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[23]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[22]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[21]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[20]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[19]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[18]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[17]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[16]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[15]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[14]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[13]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[12]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[11]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[10]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[9]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[8]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[7]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[6]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[5]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[4]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[3]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[2]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[1]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[0]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_v_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_v_i[0]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_cmd_yumi_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_cmd_yumi_i[0]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_yumi_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_yumi_i[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[7]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[6]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[5]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[4]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_resp_ready_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_resp_ready_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_ready_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_ready_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[29]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[28]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[27]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[26]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[25]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[24]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[23]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[22]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[21]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[20]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[19]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[18]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[17]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[16]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[15]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[14]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[13]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[12]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[11]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[10]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[9]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[8]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[7]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[6]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[5]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[4]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_v_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_v_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[569]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[569]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[568]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[568]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[567]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[567]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[566]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[566]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[565]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[565]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[564]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[564]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[563]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[563]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[562]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[562]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[561]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[561]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[560]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[560]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[559]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[559]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[558]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[558]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[557]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[557]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[556]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[556]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[555]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[555]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[554]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[554]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[553]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[553]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[552]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[552]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[551]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[551]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[550]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[550]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[549]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[549]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[548]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[548]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[547]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[547]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[546]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[546]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[545]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[545]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[544]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[544]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[543]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[543]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[542]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[542]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[541]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[541]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[540]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[540]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[539]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[539]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[538]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[538]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[537]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[537]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[536]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[536]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[535]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[535]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[534]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[534]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[533]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[533]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[532]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[532]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[531]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[531]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[530]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[530]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[529]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[529]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[528]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[528]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[527]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[527]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[526]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[526]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[525]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[525]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[524]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[524]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[523]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[523]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[522]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[522]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[521]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[521]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[520]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[520]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[519]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[519]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[518]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[518]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[517]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[517]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[516]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[516]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[515]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[515]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[514]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[514]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[513]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[513]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[512]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[512]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[511]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[511]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[510]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[510]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[509]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[509]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[508]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[508]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[507]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[507]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[506]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[506]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[505]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[505]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[504]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[504]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[503]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[503]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[502]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[502]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[501]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[501]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[500]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[500]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[499]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[499]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[498]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[498]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[497]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[497]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[496]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[496]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[495]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[495]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[494]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[494]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[493]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[493]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[492]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[492]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[491]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[491]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[490]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[490]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[489]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[489]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[488]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[488]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[487]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[487]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[486]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[486]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[485]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[485]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[484]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[484]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[483]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[483]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[482]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[482]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[481]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[481]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[480]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[480]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[479]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[479]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[478]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[478]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[477]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[477]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[476]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[476]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[475]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[475]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[474]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[474]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[473]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[473]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[472]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[472]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[471]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[471]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[470]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[470]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[469]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[469]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[468]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[468]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[467]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[467]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[466]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[466]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[465]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[465]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[464]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[464]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[463]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[463]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[462]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[462]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[461]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[461]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[460]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[460]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[459]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[459]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[458]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[458]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[457]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[457]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[456]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[456]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[455]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[455]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[454]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[454]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[453]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[453]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[452]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[452]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[451]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[451]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[450]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[450]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[449]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[449]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[448]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[448]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[447]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[447]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[446]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[446]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[445]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[445]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[444]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[444]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[443]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[443]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[442]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[442]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[441]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[441]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[440]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[440]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[439]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[439]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[438]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[438]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[437]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[437]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[436]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[436]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[435]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[435]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[434]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[434]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[433]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[433]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[432]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[432]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[431]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[431]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[430]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[430]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[429]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[429]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[428]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[428]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[427]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[427]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[426]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[426]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[425]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[425]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[424]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[424]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[423]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[423]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[422]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[422]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[421]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[421]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[420]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[420]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[419]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[419]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[418]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[418]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[417]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[417]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[416]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[416]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[415]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[415]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[414]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[414]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[413]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[413]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[412]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[412]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[411]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[411]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[410]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[410]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[409]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[409]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[408]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[408]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[407]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[407]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[406]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[406]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[405]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[405]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[404]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[404]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[403]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[403]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[402]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[402]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[401]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[401]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[400]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[400]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[399]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[399]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[398]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[398]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[397]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[397]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[396]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[396]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[395]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[395]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[394]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[394]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[393]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[393]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[392]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[392]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[391]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[391]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[390]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[390]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[389]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[389]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[388]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[388]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[387]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[387]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[386]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[386]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[385]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[385]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[384]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[384]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[383]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[383]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[382]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[382]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[381]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[381]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[380]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[380]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[379]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[379]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[378]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[378]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[377]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[377]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[376]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[376]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[375]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[375]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[374]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[374]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[373]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[373]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[372]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[372]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[371]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[371]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[370]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[370]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[369]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[369]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[368]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[368]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[367]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[367]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[366]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[366]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[365]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[365]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[364]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[364]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[363]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[363]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[362]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[362]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[361]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[361]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[360]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[360]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[359]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[359]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[358]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[358]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[357]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[357]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[356]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[356]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[355]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[355]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[354]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[354]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[353]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[353]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[352]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[352]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[351]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[351]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[350]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[350]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[349]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[349]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[348]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[348]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[347]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[347]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[346]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[346]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[345]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[345]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[344]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[344]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[343]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[343]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[342]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[342]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[341]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[341]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[340]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[340]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[339]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[339]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[338]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[338]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[337]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[337]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[336]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[336]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[335]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[335]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[334]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[334]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[333]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[333]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[332]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[332]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[331]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[331]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[330]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[330]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[329]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[329]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[328]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[328]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[327]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[327]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[326]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[326]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[325]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[325]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[324]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[324]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[323]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[323]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[322]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[322]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[321]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[321]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[320]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[320]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[319]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[319]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[318]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[318]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[317]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[317]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[316]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[316]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[315]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[315]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[314]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[314]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[313]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[313]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[312]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[312]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[311]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[311]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[310]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[310]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[309]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[309]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[308]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[308]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[307]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[307]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[306]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[306]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[305]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[305]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[304]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[304]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[303]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[303]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[302]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[302]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[301]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[301]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[300]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[300]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[299]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[299]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[298]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[298]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[297]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[297]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[296]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[296]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[295]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[295]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[294]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[294]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[293]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[293]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[292]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[292]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[291]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[291]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[290]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[290]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[289]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[289]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[288]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[288]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[287]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[287]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[286]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[286]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[285]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[285]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[284]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[284]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[283]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[283]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[282]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[282]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[281]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[281]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[280]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[280]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[279]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[279]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[278]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[278]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[277]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[277]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[276]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[276]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[275]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[275]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[274]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[274]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[273]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[273]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[272]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[272]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[271]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[271]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[270]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[270]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[269]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[269]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[268]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[268]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[267]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[267]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[266]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[266]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[265]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[265]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[264]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[264]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[263]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[263]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[262]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[262]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[261]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[261]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[260]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[260]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[259]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[259]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[258]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[258]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[257]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[257]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[256]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[256]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[255]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[255]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[254]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[254]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[253]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[253]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[252]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[252]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[251]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[251]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[250]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[250]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[249]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[249]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[248]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[248]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[247]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[247]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[246]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[246]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[245]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[245]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[244]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[244]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[243]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[243]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[242]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[242]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[241]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[241]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[240]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[240]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[239]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[239]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[238]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[238]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[237]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[237]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[236]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[236]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[235]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[235]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[234]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[234]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[233]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[233]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[232]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[232]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[231]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[231]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[230]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[230]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[229]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[229]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[228]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[228]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[227]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[227]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[226]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[226]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[225]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[225]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[224]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[224]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[223]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[223]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[222]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[222]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[221]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[221]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[220]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[220]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[219]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[219]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[218]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[218]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[217]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[217]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[216]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[216]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[215]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[215]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[214]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[214]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[213]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[213]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[212]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[212]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[211]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[211]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[210]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[210]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[209]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[209]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[208]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[208]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[207]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[207]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[206]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[206]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[205]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[205]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[204]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[204]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[203]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[203]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[202]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[202]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[201]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[201]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[200]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[200]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[199]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[199]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[198]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[198]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[197]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[197]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[196]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[196]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[195]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[195]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[194]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[194]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[193]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[193]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[192]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[192]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[191]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[191]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[190]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[190]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[189]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[189]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[188]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[188]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[187]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[187]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[186]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[186]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[185]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[185]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[184]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[184]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[183]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[183]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[182]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[182]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[181]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[181]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[180]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[180]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[179]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[179]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[178]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[178]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[177]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[177]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[176]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[176]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[175]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[175]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[174]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[174]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[173]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[173]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[172]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[172]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[171]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[171]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[170]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[170]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[169]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[169]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[168]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[168]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[167]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[167]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[166]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[166]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[165]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[165]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[164]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[164]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[163]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[163]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[162]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[162]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[161]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[161]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[160]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[160]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[159]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[159]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[158]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[158]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[157]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[157]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[156]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[156]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[155]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[155]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[154]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[154]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[153]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[153]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[152]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[152]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[151]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[151]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[150]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[150]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[149]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[149]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[148]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[148]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[147]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[147]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[146]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[146]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[145]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[145]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[144]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[144]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[143]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[143]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[142]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[142]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[141]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[141]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[140]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[140]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[139]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[139]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[138]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[138]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[137]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[137]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[136]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[136]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[135]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[135]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[134]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[134]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[133]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[133]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[132]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[132]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[131]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[131]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[130]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[130]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[129]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[129]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[128]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[128]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[127]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[127]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[126]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[126]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[125]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[125]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[124]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[124]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[123]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[123]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[122]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[122]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[121]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[121]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[120]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[120]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[119]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[119]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[118]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[118]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[117]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[117]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[116]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[116]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[115]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[115]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[114]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[114]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[113]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[113]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[112]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[112]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[111]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[111]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[110]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[110]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[109]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[109]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[108]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[108]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[107]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[107]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[106]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[106]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[105]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[105]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[104]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[104]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[103]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[103]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[102]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[102]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[101]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[101]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[100]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[100]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[99]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[99]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[98]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[98]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[97]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[97]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[96]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[96]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[95]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[95]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[94]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[94]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[93]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[93]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[92]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[92]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[91]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[91]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[90]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[90]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[89]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[89]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[88]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[88]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[87]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[87]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[86]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[86]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[85]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[85]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[84]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[84]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[83]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[83]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[82]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[82]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[81]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[81]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[80]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[80]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[79]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[79]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[78]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[78]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[77]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[77]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[76]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[76]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[75]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[75]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[74]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[74]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[73]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[73]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[72]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[72]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[71]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[71]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[70]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[70]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[69]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[69]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[68]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[68]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[67]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[67]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[66]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[66]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[65]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[65]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[64]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[64]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[63]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[62]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[61]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[60]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[59]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[58]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[57]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[56]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[55]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[54]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[53]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[52]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[51]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[50]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[49]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[48]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[47]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[46]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[45]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[44]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[43]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[42]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[41]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[40]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[39]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[38]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[37]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[36]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[35]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[34]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[33]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[32]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[31]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[30]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[29]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[28]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[27]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[26]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[25]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[24]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[23]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[22]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[21]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[20]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[19]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[18]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[17]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[16]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[15]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[14]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[13]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[12]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[11]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[10]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[9]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[8]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[7]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[6]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[5]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[4]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_v_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_v_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_w_v_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_w_v_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[4]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_w_v_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_w_v_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[63]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[62]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[61]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[60]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[59]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[58]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[57]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[56]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[55]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[54]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[53]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[52]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[51]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[50]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[49]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[48]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[47]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[46]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[45]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[44]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[43]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[42]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[41]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[40]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[39]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[38]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[37]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[36]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[35]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[34]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[33]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[32]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[31]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[30]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[29]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[28]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[27]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[26]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[25]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[24]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[23]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[22]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[21]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[20]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[19]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[18]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[17]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[16]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[15]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[14]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[13]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[12]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[11]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[10]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[9]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[8]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[7]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[6]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[5]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[4]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[63]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[62]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[61]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[60]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[59]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[58]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[57]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[56]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[55]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[54]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[53]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[52]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[51]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[50]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[49]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[48]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[47]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[46]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[45]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[44]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[43]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[42]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[41]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[40]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[39]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[38]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[37]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[36]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[35]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[34]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[33]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[32]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[31]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[30]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[29]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[28]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[27]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[26]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[25]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[24]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[23]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[22]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[21]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[20]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[19]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[18]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[17]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[16]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[15]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[14]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[13]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[12]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[11]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[10]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[9]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[8]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[7]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[6]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[5]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[4]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[0]}] diff --git a/flow/designs/nangate45/bp_multi_top/io.tcl b/flow/designs/nangate45/bp_multi_top/io.tcl index b2bdd9fce6..46c1375a1d 100644 --- a/flow/designs/nangate45/bp_multi_top/io.tcl +++ b/flow/designs/nangate45/bp_multi_top/io.tcl @@ -1 +1 @@ -exclude_io_pin_region -region left:100-1100 -region right:100-1100 -region top:* \ No newline at end of file +exclude_io_pin_region -region left:100-1100 -region right:100-1100 -region top:* diff --git a/flow/designs/nangate45/bp_multi_top/rules-base.json b/flow/designs/nangate45/bp_multi_top/rules-base.json index 4db33fb5f6..0f31b3dbc0 100644 --- a/flow/designs/nangate45/bp_multi_top/rules-base.json +++ b/flow/designs/nangate45/bp_multi_top/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 622260, + "value": 607245, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 150268, + "value": 143977, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 13067, + "value": 12520, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 13067, + "value": 12520, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 4890576, + "value": 4291357, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,19 +48,19 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -4.36, + "value": -4.2, "compare": ">=" }, "finish__design__instance__area": { - "value": 629703, + "value": 616495, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 6533, + "value": 6260, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 1026, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/nangate45/bp_quad/bsg_chip.sdc b/flow/designs/nangate45/bp_quad/bsg_chip.sdc index 69ce39fe4b..d89a844195 100644 --- a/flow/designs/nangate45/bp_quad/bsg_chip.sdc +++ b/flow/designs/nangate45/bp_quad/bsg_chip.sdc @@ -17,132 +17,131 @@ set mx_delay2 [expr ${l_clk_p2}*0.28] set mn_delay1 [expr ${l_clk_p1}*0.02] -set_units -time ps -resistance kOhm -capacitance fF -power mW -voltage V \ --current uA -create_clock [get_ports p_bsg_tag_clk_i] -name tag_clk -period $l_clk_p2 -waveform $wv3 -set_clock_uncertainty -hold $clk_uncertainty [get_clocks tag_clk] -create_clock [get_ports p_clk_A_i] -name bp_clk -period $clk_period -waveform $wv1 -set_clock_uncertainty $clk_uncertainty [get_clocks bp_clk] -create_clock [get_ports p_clk_B_i] -name io_master_clk -period $clk_period -waveform $wv1 -set_clock_uncertainty $clk_uncertainty [get_clocks io_master_clk] -create_clock [get_ports p_clk_C_i] -name router_clk -period $clk_period -waveform $wv1 -set_clock_uncertainty $clk_uncertainty [get_clocks router_clk] -create_clock [get_ports p_ci_clk_i] -name sdi_a_clk -period $l_clk_p1 -waveform $wv2 -set_clock_uncertainty $clk_uncertainty [get_clocks sdi_a_clk] -create_clock [get_ports p_ci2_tkn_i] -name sdo_a_tkn_clk -period $l_clk_p1 -waveform $wv2 -set_clock_uncertainty $clk_uncertainty [get_clocks sdo_a_tkn_clk] -create_clock [get_ports p_co_clk_i] -name sdi_b_clk -period $l_clk_p1 -waveform $wv2 -set_clock_uncertainty $clk_uncertainty [get_clocks sdi_b_clk] -create_clock [get_ports p_co2_tkn_i] -name sdo_b_tkn_clk -period $l_clk_p1 -waveform $wv2 -set_clock_uncertainty $clk_uncertainty [get_clocks sdo_b_tkn_clk] +set_units -time ps -resistance kOhm -capacitance fF -power mW -voltage V \ + -current uA +create_clock [get_ports p_bsg_tag_clk_i] -name tag_clk -period $l_clk_p2 -waveform $wv3 +set_clock_uncertainty -hold $clk_uncertainty [get_clocks tag_clk] +create_clock [get_ports p_clk_A_i] -name bp_clk -period $clk_period -waveform $wv1 +set_clock_uncertainty $clk_uncertainty [get_clocks bp_clk] +create_clock [get_ports p_clk_B_i] -name io_master_clk -period $clk_period -waveform $wv1 +set_clock_uncertainty $clk_uncertainty [get_clocks io_master_clk] +create_clock [get_ports p_clk_C_i] -name router_clk -period $clk_period -waveform $wv1 +set_clock_uncertainty $clk_uncertainty [get_clocks router_clk] +create_clock [get_ports p_ci_clk_i] -name sdi_a_clk -period $l_clk_p1 -waveform $wv2 +set_clock_uncertainty $clk_uncertainty [get_clocks sdi_a_clk] +create_clock [get_ports p_ci2_tkn_i] -name sdo_a_tkn_clk -period $l_clk_p1 -waveform $wv2 +set_clock_uncertainty $clk_uncertainty [get_clocks sdo_a_tkn_clk] +create_clock [get_ports p_co_clk_i] -name sdi_b_clk -period $l_clk_p1 -waveform $wv2 +set_clock_uncertainty $clk_uncertainty [get_clocks sdi_b_clk] +create_clock [get_ports p_co2_tkn_i] -name sdo_b_tkn_clk -period $l_clk_p1 -waveform $wv2 +set_clock_uncertainty $clk_uncertainty [get_clocks sdo_b_tkn_clk] # -set_multicycle_path 0 -hold -to [list [get_ports p_ci2_clk_o] [get_ports \ -p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o] \ -[get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports \ -p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]] -set_multicycle_path 1 -setup -to [list [get_ports p_ci2_clk_o] [get_ports \ -p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o] \ -[get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports \ -p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]] -set_multicycle_path 0 -hold -to [list [get_ports p_co2_clk_o] [get_ports \ -p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o] \ -[get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports \ -p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]] -set_multicycle_path 1 -setup -to [list [get_ports p_co2_clk_o] [get_ports \ -p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o] \ -[get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports \ -p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]] -set_false_path -from [get_clocks router_clk] -to [get_clocks bp_clk] -set_false_path -from [get_clocks tag_clk] -to [get_clocks bp_clk] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_clk_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_clk_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_clk_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_clk_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_clk_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_clk_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_clk_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_clk_i] -set_input_delay -clock tag_clk $mx_delay2 [get_ports p_bsg_tag_data_i] -set_input_delay -clock tag_clk $mx_delay2 [get_ports p_bsg_tag_en_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_v_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_v_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_v_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_v_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_0_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_0_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_0_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_0_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_1_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_1_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_1_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_1_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_2_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_2_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_2_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_2_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_3_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_3_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_3_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_3_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_4_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_4_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_4_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_4_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_5_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_5_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_5_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_5_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_6_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_6_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_6_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_6_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_7_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_7_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_7_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_7_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_8_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_8_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_8_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_8_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_v_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_v_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_v_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_v_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_0_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_0_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_0_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_0_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_1_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_1_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_1_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_1_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_2_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_2_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_2_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_2_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_3_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_3_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_3_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_3_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_4_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_4_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_4_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_4_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_5_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_5_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_5_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_5_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_6_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_6_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_6_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_6_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_7_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_7_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_7_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_7_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_8_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_8_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_8_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_8_i] -set_timing_derate -early -cell_delay 0.97 [get_cells \ -{bp_processor/cc/y_0__x_0__tile_node/tile/core/fe/mem/icache/tag_mem/macro_bmem/db1_wb_0__bank/macro_mem}] +set_multicycle_path 0 -hold -to [list [get_ports p_ci2_clk_o] [get_ports \ + p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o] \ + [get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports \ + p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]] +set_multicycle_path 1 -setup -to [list [get_ports p_ci2_clk_o] [get_ports \ + p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o] \ + [get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports \ + p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]] +set_multicycle_path 0 -hold -to [list [get_ports p_co2_clk_o] [get_ports \ + p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o] \ + [get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports \ + p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]] +set_multicycle_path 1 -setup -to [list [get_ports p_co2_clk_o] [get_ports \ + p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o] \ + [get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports \ + p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]] +set_false_path -from [get_clocks router_clk] -to [get_clocks bp_clk] +set_false_path -from [get_clocks tag_clk] -to [get_clocks bp_clk] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_clk_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_clk_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_clk_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_clk_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_clk_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_clk_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_clk_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_clk_i] +set_input_delay -clock tag_clk $mx_delay2 [get_ports p_bsg_tag_data_i] +set_input_delay -clock tag_clk $mx_delay2 [get_ports p_bsg_tag_en_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_v_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_v_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_v_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_v_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_0_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_0_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_0_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_0_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_1_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_1_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_1_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_1_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_2_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_2_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_2_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_2_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_3_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_3_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_3_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_3_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_4_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_4_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_4_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_4_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_5_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_5_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_5_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_5_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_6_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_6_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_6_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_6_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_7_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_7_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_7_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_7_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_8_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_8_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_8_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_8_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_v_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_v_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_v_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_v_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_0_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_0_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_0_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_0_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_1_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_1_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_1_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_1_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_2_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_2_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_2_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_2_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_3_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_3_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_3_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_3_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_4_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_4_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_4_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_4_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_5_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_5_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_5_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_5_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_6_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_6_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_6_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_6_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_7_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_7_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_7_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_7_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_8_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_8_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_8_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_8_i] +set_timing_derate -early -cell_delay 0.97 [get_cells {bp_processor/cc/y_0__x_0__tile_node/tile/core/fe/mem/icache/tag_mem/macro_bmem/db1_wb_0__bank/macro_mem}] ;# tclint-disable-line line-length diff --git a/flow/designs/nangate45/bp_quad/io.tcl b/flow/designs/nangate45/bp_quad/io.tcl index c368ed9bf9..41bce8db56 100644 --- a/flow/designs/nangate45/bp_quad/io.tcl +++ b/flow/designs/nangate45/bp_quad/io.tcl @@ -1 +1,2 @@ -exclude_io_pin_region -region left:* -region right:* -region top:* -region bottom:0-1000 -region bottom:2400-3600 \ No newline at end of file +exclude_io_pin_region -region left:* -region right:* -region top:* \ + -region bottom:0-1000 -region bottom:2400-3600 diff --git a/flow/designs/nangate45/dynamic_node/rules-base.json b/flow/designs/nangate45/dynamic_node/rules-base.json index 186181dc5f..bdc31d60f5 100644 --- a/flow/designs/nangate45/dynamic_node/rules-base.json +++ b/flow/designs/nangate45/dynamic_node/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 25608.42, + "value": 25515.12, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 28233, + "value": 27551, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 13598, + "value": 12798, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1182, + "value": 1113, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1182, + "value": 1113, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 261214, + "value": 354277, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.51, + "value": -0.49, "compare": ">=" }, "finish__design__instance__area": { - "value": 29582, + "value": 28843, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 591, + "value": 556, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -33.08, + "value": -31.32, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/gcd/constraint.sdc b/flow/designs/nangate45/gcd/constraint.sdc index 57be8eb9c6..c6d4b902be 100644 --- a/flow/designs/nangate45/gcd/constraint.sdc +++ b/flow/designs/nangate45/gcd/constraint.sdc @@ -1,15 +1,15 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 0.46 +set clk_period 0.46 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/gcd/rules-base.json b/flow/designs/nangate45/gcd/rules-base.json index 6bea6c6d38..0e91d99a8e 100644 --- a/flow/designs/nangate45/gcd/rules-base.json +++ b/flow/designs/nangate45/gcd/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 747, + "value": 743, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 5670, + "value": 5050, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.07, + "value": -0.08, "compare": ">=" }, "finish__design__instance__area": { - "value": 909, + "value": 898, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 35, + "value": 46, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/nangate45/ibex/config.mk b/flow/designs/nangate45/ibex/config.mk index 8d6843f00e..3ead834dba 100644 --- a/flow/designs/nangate45/ibex/config.mk +++ b/flow/designs/nangate45/ibex/config.mk @@ -2,48 +2,13 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = nangate45 +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \ + $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v +export VERILOG_INCLUDE_DIRS = \ + $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/ -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v - - - +export SYNTH_HDL_FRONTEND = slang export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc diff --git a/flow/designs/nangate45/ibex/constraint.sdc b/flow/designs/nangate45/ibex/constraint.sdc index 625bba41ec..38667319ac 100644 --- a/flow/designs/nangate45/ibex/constraint.sdc +++ b/flow/designs/nangate45/ibex/constraint.sdc @@ -1,6 +1,6 @@ current_design ibex_core -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 2.2 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/ibex/rules-base.json b/flow/designs/nangate45/ibex/rules-base.json index 00e8486948..966130b95e 100644 --- a/flow/designs/nangate45/ibex/rules-base.json +++ b/flow/designs/nangate45/ibex/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 36863, + "value": 35998, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 18834, + "value": 17800, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1638, + "value": 1548, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1638, + "value": 1548, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 363762, + "value": 325819, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.26, + "value": -0.14, "compare": ">=" }, "finish__design__instance__area": { - "value": 39536, + "value": 37049, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 832, + "value": 774, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -18.58, + "value": -11.47, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/jpeg/constraint.sdc b/flow/designs/nangate45/jpeg/constraint.sdc index af18e2d682..7c97d6490a 100644 --- a/flow/designs/nangate45/jpeg/constraint.sdc +++ b/flow/designs/nangate45/jpeg/constraint.sdc @@ -1,6 +1,6 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 1.2 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/jpeg/rules-base.json b/flow/designs/nangate45/jpeg/rules-base.json index 78373adb41..ffa598e023 100644 --- a/flow/designs/nangate45/jpeg/rules-base.json +++ b/flow/designs/nangate45/jpeg/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 103107.27, + "value": 103045.48, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 110453, + "value": 104372, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 71206, + "value": 69094, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 6192, + "value": 6008, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 6192, + "value": 6008, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1209350, + "value": 687679, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.07, + "value": -0.05, "compare": ">=" }, "finish__design__instance__area": { - "value": 112296, + "value": 106338, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 3096, + "value": 3004, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/nangate45/mempool_group/config.mk b/flow/designs/nangate45/mempool_group/config.mk index b31c76de8f..115c2012c5 100644 --- a/flow/designs/nangate45/mempool_group/config.mk +++ b/flow/designs/nangate45/mempool_group/config.mk @@ -77,4 +77,4 @@ export CORE_AREA = 10 12 1090 1090 export MACRO_PLACE_HALO = 10 10 -export SYNTH_USE_SLANG = 1 +export SYNTH_HDL_FRONTEND = slang diff --git a/flow/designs/nangate45/mempool_group/mempool_group.sdc b/flow/designs/nangate45/mempool_group/mempool_group.sdc index 87e865fbac..a6efdf815b 100755 --- a/flow/designs/nangate45/mempool_group/mempool_group.sdc +++ b/flow/designs/nangate45/mempool_group/mempool_group.sdc @@ -11,8 +11,10 @@ set clock_port_mempool_tile clk_i create_clock -name clk_i -period $clock_cycle [get_ports $clock_port_mempool_tile] set_clock_uncertainty $uncertainty [all_clocks] -set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==in && is_on_clock_network==false"] -set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==out && is_on_clock_network==false"] +set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay \ + [get_ports * -filter "direction==in && is_on_clock_network==false"] +set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay \ + [get_ports * -filter "direction==out && is_on_clock_network==false"] set_max_transition $maxTransition -clock_path [get_clocks clk_i] set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i] #set_propagated_clock [get_clocks clk_i] @@ -29,30 +31,37 @@ set_case_analysis 0 [get_ports scan_enable_i] set_max_fanout $maxFanout [current_design] - # False path some of the quasi-static signals. #set_false_path -from tile_id_i # TCDM Master -set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter { name =~ tcdm_master_.*req_.*_i}] -set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter { name =~ tcdm_master_*req_*_o}] +set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i \ + [get_ports -filter { name =~ tcdm_master_.*req_.*_i}] +set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i \ + [get_ports -filter { name =~ tcdm_master_*req_*_o}] -set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_master_*resp_*_i}] -set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_master_*resp_*_o}] +set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i \ + [get_ports -filter {name =~ tcdm_master_*resp_*_i}] +set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i \ + [get_ports -filter {name =~ tcdm_master_*resp_*_o}] # TCDM Slave -#set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*req_*_i}] -set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*req_*_o}] +#set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i \ +# [get_ports -filter {name =~ tcdm_slave_*req_*_i}] +set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i \ + [get_ports -filter {name =~ tcdm_slave_*req_*_o}] -set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*resp_*_i}] -set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*resp_*_o}] +set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i \ + [get_ports -filter {name =~ tcdm_slave_*resp_*_i}] +set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i \ + [get_ports -filter {name =~ tcdm_slave_*resp_*_o}] # Refill port -#set_input_delay [expr 0.50*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ refill_*_i}] +#set_input_delay [expr 0.50*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ refill_*_i}] #set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ refill_*_o}] # Reset -set_input_delay [expr 0.30*$clock_cycle] -clock vclk_i rst_ni +set_input_delay [expr 0.30*$clock_cycle] -clock vclk_i rst_ni # Critical range # Depending on the synthesis tool used, this can be helpful. diff --git a/flow/designs/intel16/gcd/rules-base.json b/flow/designs/nangate45/mempool_group/rules-base.json similarity index 83% rename from flow/designs/intel16/gcd/rules-base.json rename to flow/designs/nangate45/mempool_group/rules-base.json index 2d3637f04f..62e44a2c7e 100644 --- a/flow/designs/intel16/gcd/rules-base.json +++ b/flow/designs/nangate45/mempool_group/rules-base.json @@ -1,18 +1,18 @@ { "synth__design__instance__area__stdcell": { - "value": 191.22, + "value": 271098.37, "compare": "<=" }, "constraints__clocks__count": { - "value": 1, + "value": 2, "compare": "==" }, "placeopt__design__instance__area": { - "value": 253, + "value": 322046, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 500, + "value": 163160, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 44, + "value": 11373, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 32, + "value": 11373, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 2730, + "value": 4942626, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": 0.0, + "value": -2.34, "compare": ">=" }, "finish__design__instance__area": { - "value": 343, + "value": 331160, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 16, + "value": 7210, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -10.0, + "value": -109.23, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/swerv/constraint.sdc b/flow/designs/nangate45/swerv/constraint.sdc index 9fd406be5e..ccaab11ddf 100644 --- a/flow/designs/nangate45/swerv/constraint.sdc +++ b/flow/designs/nangate45/swerv/constraint.sdc @@ -1,6 +1,6 @@ current_design swerv -set clk_name core_clock +set clk_name core_clock set clk_port_name clk set clk_period 2.0 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/swerv/rules-base.json b/flow/designs/nangate45/swerv/rules-base.json index 6ccf6a6364..26b84e8c90 100644 --- a/flow/designs/nangate45/swerv/rules-base.json +++ b/flow/designs/nangate45/swerv/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 213238, + "value": 201974, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 106074, + "value": 99342, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 9224, + "value": 8638, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 9224, + "value": 8638, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 3342843, + "value": 3900533, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,23 +48,23 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.37, + "value": -0.27, "compare": ">=" }, "finish__design__instance__area": { - "value": 218848, + "value": 206802, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 4612, + "value": 4319, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 281, + "value": 1165, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -22.51, + "value": -21.98, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/swerv_wrapper/config.mk b/flow/designs/nangate45/swerv_wrapper/config.mk index 921ac64a5a..2ce3c88234 100644 --- a/flow/designs/nangate45/swerv_wrapper/config.mk +++ b/flow/designs/nangate45/swerv_wrapper/config.mk @@ -1,12 +1,6 @@ export DESIGN_NAME = swerv_wrapper export PLATFORM = nangate45 -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 12 -export RTLMP_MIN_MACRO = 4 - export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \ $(DESIGN_HOME)/$(PLATFORM)/swerv/macros.v export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/constraint.sdc @@ -25,9 +19,7 @@ export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io.tcl export MACRO_PLACE_HALO = 10 10 -export PLACE_DENSITY_LB_ADDON = 0.10 +export PLACE_DENSITY_LB_ADDON = 0.08 export TNS_END_PERCENT = 100 export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl - -export GPL_KEEP_OVERFLOW = 0 diff --git a/flow/designs/nangate45/swerv_wrapper/constraint.sdc b/flow/designs/nangate45/swerv_wrapper/constraint.sdc index 308fd50a14..f7c9f08b64 100644 --- a/flow/designs/nangate45/swerv_wrapper/constraint.sdc +++ b/flow/designs/nangate45/swerv_wrapper/constraint.sdc @@ -1,6 +1,6 @@ current_design swerv_wrapper -set clk_name core_clock +set clk_name core_clock set clk_port_name clk set clk_period 2.0 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/swerv_wrapper/fastroute.tcl b/flow/designs/nangate45/swerv_wrapper/fastroute.tcl index 8f1d5e070a..1086052539 100644 --- a/flow/designs/nangate45/swerv_wrapper/fastroute.tcl +++ b/flow/designs/nangate45/swerv_wrapper/fastroute.tcl @@ -1,4 +1,4 @@ -set_global_routing_layer_adjustment metal2-metal3 0.25 -set_global_routing_layer_adjustment metal4-$::env(MAX_ROUTING_LAYER) 0.15 +set_global_routing_layer_adjustment metal2-metal3 0.20 +set_global_routing_layer_adjustment metal4-$::env(MAX_ROUTING_LAYER) 0.10 set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) diff --git a/flow/designs/nangate45/swerv_wrapper/io.tcl b/flow/designs/nangate45/swerv_wrapper/io.tcl index 5a3c212330..74f327933a 100644 --- a/flow/designs/nangate45/swerv_wrapper/io.tcl +++ b/flow/designs/nangate45/swerv_wrapper/io.tcl @@ -1 +1,2 @@ -exclude_io_pin_region -region left:* -region right:* -region top:* -region bottom:0-200 -region bottom:1000-1100 +exclude_io_pin_region -region left:* -region right:* -region top:* \ + -region bottom:0-200 -region bottom:1000-1100 diff --git a/flow/designs/nangate45/swerv_wrapper/rules-base.json b/flow/designs/nangate45/swerv_wrapper/rules-base.json index 62caa0a74b..4d68fe18d5 100644 --- a/flow/designs/nangate45/swerv_wrapper/rules-base.json +++ b/flow/designs/nangate45/swerv_wrapper/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 755961, + "value": 755158, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 115300, + "value": 113069, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 10026, + "value": 9832, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 10026, + "value": 9832, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 6208106, + "value": 5365759, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,23 +48,23 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.54, + "value": -0.32, "compare": ">=" }, "finish__design__instance__area": { - "value": 763103, + "value": 762884, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 5013, + "value": 4916, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 678, + "value": 656, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -21.69, + "value": -19.88, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/tinyRocket/rules-base.json b/flow/designs/nangate45/tinyRocket/rules-base.json index e0e394095c..c4e298e189 100644 --- a/flow/designs/nangate45/tinyRocket/rules-base.json +++ b/flow/designs/nangate45/tinyRocket/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 66186, + "value": 64635, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 833444, + "value": 822134, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,11 +48,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.31, + "value": -0.13, "compare": ">=" }, "finish__design__instance__area": { - "value": 68441, + "value": 67327, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -27.52, + "value": -15.79, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/rapidus2hp/README.md b/flow/designs/rapidus2hp/README.md new file mode 100644 index 0000000000..b95ec56e72 --- /dev/null +++ b/flow/designs/rapidus2hp/README.md @@ -0,0 +1,14 @@ +# Rapidus Environment Setup + +## Clone Rapidus Repo from Private GH + +The ORFS-specific files for the Rapidus platform are stored separately in the private rapidus repo. Clone out the repo into a separate directory and then set PLATFORM_HOME to point to it: + +``` +cd rapidus_platform_dir_goes_here +git clone http://github.com/The-OpenROAD-Project-private/rapidus +export PLATFORM_HOME=`pwd`/rapidus_platform_dir_goes_here +``` + +For more information, check out (http://github.com/The-OpenROAD-Project-private/rapidus) + diff --git a/flow/designs/rapidus2hp/cva6/autotuner.json b/flow/designs/rapidus2hp/cva6/autotuner.json new file mode 100644 index 0000000000..734b7d6808 --- /dev/null +++ b/flow/designs/rapidus2hp/cva6/autotuner.json @@ -0,0 +1,51 @@ +{ + "_SDC_FILE_PATH": "constraint.sdc", + "_SDC_CLK_PERIOD": { + "type": "float", + "minmax": [ + 990, + 1250 + ], + "step": 0 + }, + "CORE_UTILIZATION": { + "type": "int", + "minmax": [ + 40, + 60 + ], + "step": 1 + }, + "CTS_BUF_DISTANCE": { + "type": "int", + "minmax": [ + 25, + 50 + ], + "step": 1 + }, + "CTS_CLUSTER_SIZE": { + "type": "int", + "minmax": [ + 30, + 60 + ], + "step": 1 + }, + "CTS_CLUSTER_DIAMETER": { + "type": "int", + "minmax": [ + 15, + 25 + ], + "step": 1 + }, + "CORE_MARGIN": { + "type": "float", + "minmax": [ + 1.8, + 2.1 + ], + "step": 0 + } +} diff --git a/flow/designs/rapidus2hp/cva6/canonicalize.tcl b/flow/designs/rapidus2hp/cva6/canonicalize.tcl new file mode 100644 index 0000000000..d9f81be71f --- /dev/null +++ b/flow/designs/rapidus2hp/cva6/canonicalize.tcl @@ -0,0 +1,4 @@ +# Remove rvfi_probes_o interface since it's not in the baseline and contributes +# 4k ports and connections (many of which are buffers tied to tie cells) + +delete cva6/o:rvfi_probes_o* diff --git a/flow/designs/rapidus2hp/cva6/config.mk b/flow/designs/rapidus2hp/cva6/config.mk new file mode 100644 index 0000000000..ce52828b2c --- /dev/null +++ b/flow/designs/rapidus2hp/cva6/config.mk @@ -0,0 +1,125 @@ +export PLATFORM = rapidus2hp + +export DESIGN_NAME = cva6 + +# Some files are listed specifically vs. sorted wilcard to control the order (makes Verific happy) +export SRC_HOME = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME) +export VERILOG_FILES = $(sort $(wildcard $(SRC_HOME)/common/local/util/*.sv)) \ + $(SRC_HOME)/core/include/config_pkg.sv \ + $(SRC_HOME)/core/include/cv32a65x_config_pkg.sv \ + $(SRC_HOME)/core/include/riscv_pkg.sv \ + $(SRC_HOME)/core/include/ariane_pkg.sv \ + $(SRC_HOME)/core/include/build_config_pkg.sv \ + $(SRC_HOME)/core/include/std_cache_pkg.sv \ + $(SRC_HOME)/core/include/wt_cache_pkg.sv \ + $(sort $(wildcard $(SRC_HOME)/vendor/pulp-platform/common_cells/src/*.sv)) \ + $(SRC_HOME)/core/cvfpu/src/fpnew_pkg.sv \ + $(sort $(wildcard $(SRC_HOME)/vendor/pulp-platform/axi/src/*.sv)) \ + $(SRC_HOME)/core/cvfpu/src/fpnew_cast_multi.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_classifier.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_divsqrt_multi.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_fma.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_fma_multi.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_noncomp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_block.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_fmt_slice.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_rounding.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_top.sv \ + $(sort $(wildcard $(SRC_HOME)/core/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/pmp/src/*.sv)) \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_pkg.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_amo.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_cmo.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_core_arbiter.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl_pe.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_memctrl.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_miss_handler.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_mshr.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_rtab.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_uncached.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_plru.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_random.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_pkg.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_arb.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/common/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/utils/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cva6_mmu/*.sv)) \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv \ + $(SRC_HOME)/core/cvxif_example/include/cvxif_instr_pkg.sv \ + $(sort $(wildcard $(SRC_HOME)/core/frontend/*.sv)) \ + $(SRC_HOME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \ + $(PLATFORM_DIR)/ram/verilog/fakeram7_64x256_shim.sv \ + $(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p64x256m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv \ + $(PLATFORM_DIR)/ram/verilog/fakeram7_128x64_shim.sv \ + $(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p128x64m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv \ + $(PLATFORM_DIR)/ram/verilog/fakeram7_64x28_shim.sv \ + $(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p64x28m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv \ + $(PLATFORM_DIR)/ram/verilog/fakeram7_64x25_shim.sv \ + $(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p64x25m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv + +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/common_cells/include \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/include + +export VERILOG_DEFINES += -D HPDCACHE_ASSERT_OFF + +export ADDITIONAL_LEFS = $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x256m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \ + $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p128x64m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \ + $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x28m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \ + $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x25m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef + +export ADDITIONAL_LIBS += $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x256m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \ + $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p128x64m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \ + $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x28m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \ + $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x25m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc + +# Must be defined before the ifeq's +export SYNTH_HDL_FRONTEND = slang +export SYNTH_HIERARCHICAL = 1 + +ifeq ($(SYNTH_HDL_FRONTEND),verific) + # Reduce utilization for verific since it runs into issues with DPL not being + # able to place instances or with one-site gap/overlap issues + export CORE_UTILIZATION = 45 +else + # Reduce the amount of resizing done between GPL and DPL + export EARLY_SIZING_CAP_RATIO = 6 + export CORE_UTILIZATION = 55 +endif + +export CORE_MARGIN = 2 +export MACRO_PLACE_HALO = 2 2 + +export PLACE_DENSITY = 0.65 + +export ENABLE_DPO = 0 + +# a smoketest for this option, there are a +# few last gasp iterations +export SKIP_LAST_GASP ?= 1 + +# For use with SYNTH_HIERARCHICAL +export SYNTH_MINIMUM_KEEP_SIZE ?= 40000 + +#export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io_constraints.tcl + +# Remove rvfi_probes_o interface +export SYNTH_CANONICALIZE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/canonicalize.tcl diff --git a/flow/designs/rapidus2hp/cva6/constraint.sdc b/flow/designs/rapidus2hp/cva6/constraint.sdc new file mode 100644 index 0000000000..f263502816 --- /dev/null +++ b/flow/designs/rapidus2hp/cva6/constraint.sdc @@ -0,0 +1,9 @@ +# Derived from cva6_synth.tcl and Makefiles + +set clk_name main_clk +set clk_port clk_i +set clk_ports_list [list $clk_port] +set clk_period 1380 +set input_delay 0.46 +set output_delay 0.11 +create_clock [get_ports $clk_port] -name $clk_name -period $clk_period diff --git a/flow/designs/rapidus2hp/cva6/io_constraints.tcl b/flow/designs/rapidus2hp/cva6/io_constraints.tcl new file mode 100644 index 0000000000..44c48e5927 --- /dev/null +++ b/flow/designs/rapidus2hp/cva6/io_constraints.tcl @@ -0,0 +1,34 @@ +# left (bottom to top) +set_io_pin_constraint -group -order -region left:4.09-40.70 -pin_names {cvxif_req_o[*]} +set_io_pin_constraint -group -order -region left:40.85-90.13 -pin_names {noc_req_o[*]} + +# right (bottom to top) +# The intervals have been expanded based on pin placer feedback +set_io_pin_constraint -group -order -region right:5.25-45.34 -pin_names {noc_resp_i[*]} +set_io_pin_constraint -group -order -region right:45.62-93.07 -pin_names {cvxif_resp_i[*]} +set_io_pin_constraint -group -order -region right:93.32-93.73 \ + -pin_names { + debug_req_i time_irq_i ipi_i + } +set_io_pin_constraint -group -order -region right:94.01-94.28 -pin_names {irq_i[*]} +set_io_pin_constraint -group -order -region right:94.51-102.01 -pin_names {hart_id_i[*]} +set_io_pin_constraint -group -order -region right:102.25-109.74 -pin_names {boot_addr_i[*]} +set_io_pin_constraint -group -order -region right:109.99-110.25 -pin_names {rst_ni clk_i} + +# The rvfi_probes_o pins don't exist in reference design implementation +# put a third of them on the top, a third on the bottom, and let the placer +# decide where to put the remaining third +set num_rvfi_probes_ports 4295 +set third_rvfi_probes_ports [expr $num_rvfi_probes_ports / 3] +set top_group {} +for { set i 0 } { $i < $third_rvfi_probes_ports } { incr i } { + lappend top_group "rvfi_probes_o\[$i\]" +} +set bottom_group {} +for { } { $i < $third_rvfi_probes_ports * 2 } { incr i } { + lappend bottom_group "rvfi_probes_o\[$i\]" +} + + +set_io_pin_constraint -group -order -region bottom:* -pin_names $top_group +set_io_pin_constraint -group -order -region top:* -pin_names $bottom_group diff --git a/flow/designs/rapidus2hp/cva6/opt_constraint.sdc b/flow/designs/rapidus2hp/cva6/opt_constraint.sdc new file mode 100644 index 0000000000..b0692f6387 --- /dev/null +++ b/flow/designs/rapidus2hp/cva6/opt_constraint.sdc @@ -0,0 +1,9 @@ +# Derived from cva6_synth.tcl and Makefiles + +set clk_name main_clk +set clk_port clk_i +set clk_ports_list [list $clk_port] +set clk_period 1013.87619516354 +set input_delay 0.46 +set output_delay 0.11 +create_clock [get_ports $clk_port] -name $clk_name -period $clk_period diff --git a/flow/designs/rapidus2hp/ethmac/config.mk b/flow/designs/rapidus2hp/ethmac/config.mk new file mode 100644 index 0000000000..b3507b64a9 --- /dev/null +++ b/flow/designs/rapidus2hp/ethmac/config.mk @@ -0,0 +1,12 @@ +export PLATFORM = rapidus2hp + +export DESIGN_NAME = ethmac + +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export ABC_AREA = 1 + +export CORE_UTILIZATION = 45 +export CORE_ASPECT_RATIO = 1 +export CORE_MARGIN = 0.75 +export PLACE_DENSITY = 0.70 diff --git a/flow/designs/rapidus2hp/ethmac/constraint.sdc b/flow/designs/rapidus2hp/ethmac/constraint.sdc new file mode 100644 index 0000000000..50e470ebba --- /dev/null +++ b/flow/designs/rapidus2hp/ethmac/constraint.sdc @@ -0,0 +1,39 @@ +set top_clk_name wb_clk_i +set clk_period 875 +set clk_io_pct 0.2 +set clk_port [get_ports $top_clk_name] +create_clock -name $top_clk_name -period $clk_period $clk_port +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $top_clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $top_clk_name \ + [all_outputs] + +set tx_clk_name mtx_clk_pad_i +set tx_clk_port [get_ports $tx_clk_name] +set tx_clk_period 300 +create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port +set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] \ + $tx_clk_port] +set_input_delay [expr { $tx_clk_period * $clk_io_pct }] -clock $tx_clk_name \ + $mtx_non_clock_inputs +set_output_delay [expr { $tx_clk_period * $clk_io_pct }] -clock $tx_clk_name \ + [all_outputs] + +set rx_clk_name mrx_clk_pad_i +set rx_clk_port [get_ports $rx_clk_name] +set rx_clk_period 300 +create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port +set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] \ + $rx_clk_port] +set_input_delay [expr { $rx_clk_period * $clk_io_pct }] -clock $rx_clk_name \ + $mrx_non_clock_inputs +set_output_delay [expr { $rx_clk_period * $clk_io_pct }] -clock $rx_clk_name \ + [all_outputs] + +set_clock_groups -name core_clock -logically_exclusive \ + -group [get_clocks $top_clk_name] \ + -group [get_clocks $tx_clk_name] \ + -group [get_clocks $rx_clk_name] + +set_max_fanout 10 [current_design] diff --git a/flow/designs/rapidus2hp/gcd/autotuner.json b/flow/designs/rapidus2hp/gcd/autotuner.json new file mode 100644 index 0000000000..e622bbf82d --- /dev/null +++ b/flow/designs/rapidus2hp/gcd/autotuner.json @@ -0,0 +1,35 @@ +{ + "_SDC_FILE_PATH": "constraint.sdc", + "_SDC_CLK_PERIOD": { + "type": "float", + "minmax": [ + 180, + 300 + ], + "step": 0 + }, + "CORE_UTILIZATION": { + "type": "float", + "minmax": [ + 21, + 60 + ], + "step": 0 + }, + "CTS_CLUSTER_SIZE": { + "type": "int", + "minmax": [ + 10, + 200 + ], + "step": 1 + }, + "CTS_CLUSTER_DIAMETER": { + "type": "int", + "minmax": [ + 20, + 400 + ], + "step": 1 + } +} diff --git a/flow/designs/rapidus2hp/gcd/config.mk b/flow/designs/rapidus2hp/gcd/config.mk new file mode 100644 index 0000000000..0dae84d592 --- /dev/null +++ b/flow/designs/rapidus2hp/gcd/config.mk @@ -0,0 +1,10 @@ +export DESIGN_NICKNAME = gcd +export DESIGN_NAME = gcd +export PLATFORM = rapidus2hp + +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc + +export CORE_UTILIZATION = 30 +export CORE_MARGIN = .75 +export PLACE_DENSITY = 0.42 diff --git a/flow/designs/intel16/gcd/constraint.sdc b/flow/designs/rapidus2hp/gcd/constraint.sdc similarity index 52% rename from flow/designs/intel16/gcd/constraint.sdc rename to flow/designs/rapidus2hp/gcd/constraint.sdc index 727b5bffb3..3eb0db2391 100644 --- a/flow/designs/intel16/gcd/constraint.sdc +++ b/flow/designs/rapidus2hp/gcd/constraint.sdc @@ -1,8 +1,8 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 1200 +set clk_period 185 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -11,5 +11,7 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + [all_outputs] diff --git a/flow/designs/rapidus2hp/hercules_is_int/config.mk b/flow/designs/rapidus2hp/hercules_is_int/config.mk new file mode 100644 index 0000000000..a9486b6323 --- /dev/null +++ b/flow/designs/rapidus2hp/hercules_is_int/config.mk @@ -0,0 +1,37 @@ +export PLATFORM = rapidus2hp + +export DESIGN_NAME = hercules_is_int + +export SRC_HOME = /platforms/Rapidus/designs/hercules_is_int +export VERILOG_FILES = $(sort $(wildcard $(SRC_HOME)/hercules_issue/verilog/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/shared/verilog/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/models/cells/generic/*.sv)) + +export VERILOG_INCLUDE_DIRS = $(SRC_HOME)/hercules_issue/verilog \ + $(SRC_HOME)/shared/verilog \ + $(SRC_HOME)/models/cells/generic + +export VERILOG_DEFINES += + +export ADDITIONAL_LEFS = +export ADDITIONAL_LIBS += + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/prects.sdc + +# Must be defined before the ifeq's +export SYNTH_HDL_FRONTEND = slang +export SYNTH_HIERARCHICAL ?= 0 + +export CORE_UTILIZATION = 35 + +export CORE_MARGIN = 2 +export MACRO_PLACE_HALO = 2 2 + +export PLACE_DENSITY = 0.58 + +# a smoketest for this option, there are a +# few last gasp iterations +export SKIP_LAST_GASP ?= 1 + +# For use with SYNTH_HIERARCHICAL +export SYNTH_MINIMUM_KEEP_SIZE ?= 40000 diff --git a/flow/designs/rapidus2hp/hercules_is_int/prects.sdc b/flow/designs/rapidus2hp/hercules_is_int/prects.sdc new file mode 100644 index 0000000000..934de6be54 --- /dev/null +++ b/flow/designs/rapidus2hp/hercules_is_int/prects.sdc @@ -0,0 +1,12 @@ +#set sdc_version 2.1 +set sdc_version 1.4 +current_design hercules_is_int + +set clk_period 250 + +set_max_fanout 32 [current_design] +set_load 10 [all_outputs] +set_max_capacitance 10 [all_inputs] + +create_clock -name "clk" -add -period $clk_period \ + -waveform [list 0.0 [expr { 0.5 * $clk_period }]] [get_ports clk] diff --git a/flow/designs/rapidus2hp/ibex/config.mk b/flow/designs/rapidus2hp/ibex/config.mk new file mode 100644 index 0000000000..f29c39a686 --- /dev/null +++ b/flow/designs/rapidus2hp/ibex/config.mk @@ -0,0 +1,29 @@ +export PLATFORM = rapidus2hp + +export DESIGN_NICKNAME = ibex +export DESIGN_NAME = ibex_core + +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \ + $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v + +export VERILOG_INCLUDE_DIRS = \ + $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/ + +export SYNTH_HDL_FRONTEND = slang + +# if FLOW_VARIANT == pos_slack, use an SDC file that has a larger clock +# resulting in positive slack +ifeq ($(FLOW_VARIANT),pos_slack) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_pos_slack.sdc +else +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +endif + +export CORE_UTILIZATION = 45 +export CORE_ASPECT_RATIO = 1 +export CORE_MARGIN = 0.75 +export PLACE_DENSITY_LB_ADDON = 0.20 + +export ENABLE_DPO = 0 + +export TNS_END_PERCENT = 100 diff --git a/flow/designs/rapidus2hp/ibex/constraint.sdc b/flow/designs/rapidus2hp/ibex/constraint.sdc new file mode 100644 index 0000000000..1465ae6069 --- /dev/null +++ b/flow/designs/rapidus2hp/ibex/constraint.sdc @@ -0,0 +1,15 @@ +set clk_name core_clock +set clk_port_name clk_i +set clk_period 790 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + [all_outputs] diff --git a/flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc b/flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc new file mode 100644 index 0000000000..d714d428ae --- /dev/null +++ b/flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc @@ -0,0 +1,15 @@ +set clk_name core_clock +set clk_port_name clk_i +set clk_period 1468 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + [all_outputs] diff --git a/flow/designs/rapidus2hp/jpeg/config.mk b/flow/designs/rapidus2hp/jpeg/config.mk new file mode 100644 index 0000000000..6996f9da0e --- /dev/null +++ b/flow/designs/rapidus2hp/jpeg/config.mk @@ -0,0 +1,16 @@ +export PLATFORM = rapidus2hp + +export DESIGN_NAME = jpeg_encoder +export DESIGN_NICKNAME = jpeg + +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc +export ABC_AREA = 1 + +export CORE_UTILIZATION = 35 +export CORE_ASPECT_RATIO = 1 +export CORE_MARGIN = 0.75 +export PLACE_DENSITY = 0.62 + +export TNS_END_PERCENT = 100 diff --git a/flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc b/flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc new file mode 100644 index 0000000000..9f0d6c6a9b --- /dev/null +++ b/flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc @@ -0,0 +1,17 @@ +current_design jpeg_encoder + +set clk_name clk +set clk_port_name clk +set clk_period 425 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + [all_outputs] diff --git a/flow/designs/sky130hd/aes/constraint.sdc b/flow/designs/sky130hd/aes/constraint.sdc index 7fa2a489d8..f0b3b99355 100644 --- a/flow/designs/sky130hd/aes/constraint.sdc +++ b/flow/designs/sky130hd/aes/constraint.sdc @@ -1,15 +1,15 @@ current_design aes_cipher_top -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 4.5 +set clk_period 4.5 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/aes/fastroute.tcl b/flow/designs/sky130hd/aes/fastroute.tcl index 66eb939e6f..80e4274ee2 100644 --- a/flow/designs/sky130hd/aes/fastroute.tcl +++ b/flow/designs/sky130hd/aes/fastroute.tcl @@ -2,4 +2,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/designs/sky130hd/aes/rules-base.json b/flow/designs/sky130hd/aes/rules-base.json index 332c723138..32771e8a71 100644 --- a/flow/designs/sky130hd/aes/rules-base.json +++ b/flow/designs/sky130hd/aes/rules-base.json @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 180, + "value": 148, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 677310, + "value": 783010, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,11 +44,11 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 40, + "value": 16, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.26, + "value": -0.1, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/sky130hd/chameleon/constraint.sdc b/flow/designs/sky130hd/chameleon/constraint.sdc index 6dcc28d927..d3a0d6df47 100644 --- a/flow/designs/sky130hd/chameleon/constraint.sdc +++ b/flow/designs/sky130hd/chameleon/constraint.sdc @@ -1,13 +1,13 @@ -set clk_name core_clock -set clk_port_name HCLK -set clk_period 7.0 +set clk_name core_clock +set clk_port_name HCLK +set clk_period 7.0 set clk_io_pct 0.1 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/chameleon/rules-base.json b/flow/designs/sky130hd/chameleon/rules-base.json index e183d8c443..de98b6d05b 100644 --- a/flow/designs/sky130hd/chameleon/rules-base.json +++ b/flow/designs/sky130hd/chameleon/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 69796, + "value": 69712, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,15 +20,15 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 6069, + "value": 6062, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 6069, + "value": 6062, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 200, + "value": 196, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 189, + "value": 174, "compare": "<=" }, "finish__timing__setup__ws": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 3035, + "value": 3031, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/sky130hd/gcd/constraint.sdc b/flow/designs/sky130hd/gcd/constraint.sdc index 7177c71e7b..fadfedd028 100644 --- a/flow/designs/sky130hd/gcd/constraint.sdc +++ b/flow/designs/sky130hd/gcd/constraint.sdc @@ -1,6 +1,6 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk set clk_period 1.1 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/gcd/rules-base.json b/flow/designs/sky130hd/gcd/rules-base.json index 9251d64a1e..a574f06862 100644 --- a/flow/designs/sky130hd/gcd/rules-base.json +++ b/flow/designs/sky130hd/gcd/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 481, + "value": 581, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,7 +20,7 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 65, + "value": 62, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 9752, + "value": 11675, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 76, + "value": 86, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/sky130hd/ibex/BUILD.bazel b/flow/designs/sky130hd/ibex/BUILD.bazel index 2e20d2d980..08f7adc3e6 100644 --- a/flow/designs/sky130hd/ibex/BUILD.bazel +++ b/flow/designs/sky130hd/ibex/BUILD.bazel @@ -5,9 +5,13 @@ orfs_flow( arguments = { "ADDER_MAP_FILE": "", "CORE_UTILIZATION": "45", - "PLACE_DENSITY_LB_ADDON": "0.2", + "PLACE_DENSITY_LB_ADDON": "0.25", "TNS_END_PERCENT": "100", "REMOVE_ABC_BUFFERS": "1", + "SYNTH_HDL_FRONTEND": "slang", + "VERILOG_INCLUDE_DIRS": "flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl", + "CTS_CLUSTER_SIZE": "20", + "CTS_CLUSTER_DIAMETER": "50", }, pdk = "@docker_orfs//:sky130hd", sources = { @@ -15,5 +19,5 @@ orfs_flow( "FASTROUTE_TCL": ["fastroute.tcl"], }, top = "ibex_core", - verilog_files = ["//flow/designs/src/ibex:verilog"], + verilog_files = ["//flow/designs/src/ibex_sv:verilog"], ) diff --git a/flow/designs/sky130hd/ibex/config.mk b/flow/designs/sky130hd/ibex/config.mk index 3ebfcab5d5..5f03b5aae7 100644 --- a/flow/designs/sky130hd/ibex/config.mk +++ b/flow/designs/sky130hd/ibex/config.mk @@ -2,43 +2,13 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = sky130hd -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \ + $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v + +export VERILOG_INCLUDE_DIRS = \ + $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/ + +export SYNTH_HDL_FRONTEND = slang export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc @@ -46,7 +16,7 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint. export ADDER_MAP_FILE := export CORE_UTILIZATION = 45 -export PLACE_DENSITY_LB_ADDON = 0.2 +export PLACE_DENSITY_LB_ADDON = 0.25 export TNS_END_PERCENT = 100 export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl diff --git a/flow/designs/sky130hd/ibex/constraint.sdc b/flow/designs/sky130hd/ibex/constraint.sdc index a4faf836eb..fed426995f 100644 --- a/flow/designs/sky130hd/ibex/constraint.sdc +++ b/flow/designs/sky130hd/ibex/constraint.sdc @@ -1,6 +1,6 @@ current_design ibex_core -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 10.0 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/ibex/constraint_doe.sdc b/flow/designs/sky130hd/ibex/constraint_doe.sdc index e169d10114..31ddde31d7 100644 --- a/flow/designs/sky130hd/ibex/constraint_doe.sdc +++ b/flow/designs/sky130hd/ibex/constraint_doe.sdc @@ -1,5 +1,5 @@ set uncertainty 1.0 -set io_delay 7.0 +set io_delay 7.0 set clock_port clk_i @@ -11,5 +11,5 @@ create_clock -name core_clock -period 15.0 -waveform {0.0000 7.5} [get_ports {cl set_clock_uncertainty $uncertainty [all_clocks] # -set_input_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_inputs] -set_output_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_outputs] +set_input_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_inputs] +set_output_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_outputs] diff --git a/flow/designs/sky130hd/ibex/fastroute.tcl b/flow/designs/sky130hd/ibex/fastroute.tcl index 24af379c99..76f9321967 100644 --- a/flow/designs/sky130hd/ibex/fastroute.tcl +++ b/flow/designs/sky130hd/ibex/fastroute.tcl @@ -2,4 +2,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/designs/sky130hd/ibex/rules-base.json b/flow/designs/sky130hd/ibex/rules-base.json index 19ca204614..c90e9cb8fd 100644 --- a/flow/designs/sky130hd/ibex/rules-base.json +++ b/flow/designs/sky130hd/ibex/rules-base.json @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 64, + "value": 128, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 808993, + "value": 801898, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,15 +44,15 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 70, + "value": 64, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.45, + "value": -0.98, "compare": ">=" }, "finish__design__instance__area": { - "value": 205228, + "value": 204569, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -19.68, + "value": -16.91, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/sky130hd/jpeg/config.mk b/flow/designs/sky130hd/jpeg/config.mk index dced6f2bca..995fbeda5f 100644 --- a/flow/designs/sky130hd/jpeg/config.mk +++ b/flow/designs/sky130hd/jpeg/config.mk @@ -13,3 +13,6 @@ export TNS_END_PERCENT = 100 export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl export REMOVE_ABC_BUFFERS = 1 + +# workaround for density growing to 0.91 from adjustments on TD/RD iterations +export GPL_ROUTABILITY_DRIVEN = 0 diff --git a/flow/designs/sky130hd/jpeg/constraint.sdc b/flow/designs/sky130hd/jpeg/constraint.sdc index 28aa0cc7ca..5d9b007f0e 100644 --- a/flow/designs/sky130hd/jpeg/constraint.sdc +++ b/flow/designs/sky130hd/jpeg/constraint.sdc @@ -1,6 +1,6 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 5.5 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/jpeg/fastroute.tcl b/flow/designs/sky130hd/jpeg/fastroute.tcl index 80a2ca181e..e795f5e820 100644 --- a/flow/designs/sky130hd/jpeg/fastroute.tcl +++ b/flow/designs/sky130hd/jpeg/fastroute.tcl @@ -2,4 +2,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/designs/sky130hd/jpeg/rules-base.json b/flow/designs/sky130hd/jpeg/rules-base.json index c269c038e1..780a6ec5bd 100644 --- a/flow/designs/sky130hd/jpeg/rules-base.json +++ b/flow/designs/sky130hd/jpeg/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 410, + "value": 220, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -44,11 +44,11 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 94, + "value": 81, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.47, + "value": -0.25, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/sky130hd/microwatt/config.mk b/flow/designs/sky130hd/microwatt/config.mk index 1b0edab7bf..589df7a899 100644 --- a/flow/designs/sky130hd/microwatt/config.mk +++ b/flow/designs/sky130hd/microwatt/config.mk @@ -8,10 +8,8 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/* export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc -export DIE_AREA = 0 0 2920 3520 -export CORE_AREA = 10 10 2910 3510 - -export PLACE_DENSITY ?= 0.2 +export DIE_AREA = 0 0 3020 3610 +export CORE_AREA = 10 10 3010 3600 export microwatt_DIR = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME) @@ -33,11 +31,16 @@ export MACRO_BLOCKAGE_HALO = 151 # There's less space due to the adapted blockage halos, so GPL requires a # higher density in order to run. -export PLACE_DENSITY = 0.21 +export PLACE_DENSITY = 0.2 + +# Extra effort to ease routing: avoid very tall std cell clusters in MPL. +export RTLMP_MIN_AR = 0.40 # CTS tuning export CTS_BUF_DISTANCE = 600 export SKIP_GATE_CLONING = 1 +export CTS_CLUSTER_SIZE = 10 +export CTS_CLUSTER_DIAMETER = 50 export SETUP_SLACK_MARGIN = 0.2 diff --git a/flow/designs/sky130hd/microwatt/constraint.sdc b/flow/designs/sky130hd/microwatt/constraint.sdc index cc9dbbe523..55170d5f75 100644 --- a/flow/designs/sky130hd/microwatt/constraint.sdc +++ b/flow/designs/sky130hd/microwatt/constraint.sdc @@ -49,13 +49,17 @@ set jtag_clk_port [get_ports $jtag_clk_port_name] create_clock -name $jtag_clk_name -period $jtag_clk_period $jtag_clk_port set_clock_groups -name group1 -logically_exclusive \ - -group [get_clocks $jtag_clk_name]\ - -group [get_clocks $clk_name] - -set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] -clock $jtag_clk_name [get_ports jtag_tdi] -set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] -clock $jtag_clk_name [get_ports jtag_tms] -set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] -clock $jtag_clk_name [get_ports jtag_trst] -set_output_delay [expr $jtag_clk_period * $jtag_clk_io_pct] -clock $jtag_clk_name [get_ports jtag_tdo] + -group [get_clocks $jtag_clk_name] \ + -group [get_clocks $clk_name] + +set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] \ + -clock $jtag_clk_name [get_ports jtag_tdi] +set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] \ + -clock $jtag_clk_name [get_ports jtag_tms] +set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] \ + -clock $jtag_clk_name [get_ports jtag_trst] +set_output_delay [expr $jtag_clk_period * $jtag_clk_io_pct] \ + -clock $jtag_clk_name [get_ports jtag_tdo] set_max_fanout 10 [current_design] diff --git a/flow/designs/sky130hd/microwatt/fastroute.tcl b/flow/designs/sky130hd/microwatt/fastroute.tcl index b39791ca0e..e1ea87c701 100644 --- a/flow/designs/sky130hd/microwatt/fastroute.tcl +++ b/flow/designs/sky130hd/microwatt/fastroute.tcl @@ -2,4 +2,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/designs/sky130hd/microwatt/rules-base.json b/flow/designs/sky130hd/microwatt/rules-base.json index 327fa7a3d0..4b1d9fe871 100644 --- a/flow/designs/sky130hd/microwatt/rules-base.json +++ b/flow/designs/sky130hd/microwatt/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 5627882, + "value": 5621142, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 3810, + "value": 4257, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 9717698, + "value": 10026505, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -40,15 +40,15 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 5, + "value": 3, "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 2793, + "value": 1618, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -3.56, + "value": -3.13, "compare": ">=" }, "finish__design__instance__area": { @@ -60,11 +60,11 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 106, + "value": 262, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -21.23, + "value": -17.68, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/sky130hd/riscv32i/constraint.sdc b/flow/designs/sky130hd/riscv32i/constraint.sdc index 70a1fcf751..5b0a6f1b4e 100644 --- a/flow/designs/sky130hd/riscv32i/constraint.sdc +++ b/flow/designs/sky130hd/riscv32i/constraint.sdc @@ -1,6 +1,6 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 6.0 +set clk_period 6.0 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -9,10 +9,10 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [list] foreach input [all_inputs] { - if {$clk_port != $input} { - lappend $non_clock_inputs $input - } + if { $clk_port != $input } { + lappend $non_clock_inputs $input + } } -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/riscv32i/rules-base.json b/flow/designs/sky130hd/riscv32i/rules-base.json index acd2cf3665..ac2c4c89f9 100644 --- a/flow/designs/sky130hd/riscv32i/rules-base.json +++ b/flow/designs/sky130hd/riscv32i/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 70856.21, + "value": 70778.51, "compare": "<=" }, "constraints__clocks__count": { @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 83236, + "value": 81702, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 28, + "value": 20, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 309557, + "value": 301382, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,15 +44,15 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 21, + "value": 18, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.36, + "value": -1.17, "compare": ">=" }, "finish__design__instance__area": { - "value": 90213, + "value": 94909, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -30.94, + "value": -28.53, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/sky130hs/aes/constraint.sdc b/flow/designs/sky130hs/aes/constraint.sdc index 09f157ee3d..5878fa7782 100644 --- a/flow/designs/sky130hs/aes/constraint.sdc +++ b/flow/designs/sky130hs/aes/constraint.sdc @@ -1,6 +1,6 @@ current_design aes_cipher_top -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 3.1 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/aes/rules-base.json b/flow/designs/sky130hs/aes/rules-base.json index e6c5b80408..27ade127bb 100644 --- a/flow/designs/sky130hs/aes/rules-base.json +++ b/flow/designs/sky130hs/aes/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 177040, + "value": 176428, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 53, + "value": 182, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 737983, + "value": 722796, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,15 +44,15 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 45, + "value": 54, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.47, + "value": -0.18, "compare": ">=" }, "finish__design__instance__area": { - "value": 193310, + "value": 184400, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { diff --git a/flow/designs/sky130hs/gcd/constraint.sdc b/flow/designs/sky130hs/gcd/constraint.sdc index f347111b34..ed93d8a1eb 100644 --- a/flow/designs/sky130hs/gcd/constraint.sdc +++ b/flow/designs/sky130hs/gcd/constraint.sdc @@ -1,15 +1,15 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 2.2 +set clk_period 2.2 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/gcd/rules-base.json b/flow/designs/sky130hs/gcd/rules-base.json index 6e33b6ad11..f8939b236d 100644 --- a/flow/designs/sky130hs/gcd/rules-base.json +++ b/flow/designs/sky130hs/gcd/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 5424, + "value": 5423, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 631, + "value": 622, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 55, + "value": 54, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 55, + "value": 54, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 10496, + "value": 12530, "compare": "<=" }, "detailedroute__route__drc_errors": { diff --git a/flow/designs/sky130hs/ibex/config.mk b/flow/designs/sky130hs/ibex/config.mk index 3235138721..bb2959edd3 100644 --- a/flow/designs/sky130hs/ibex/config.mk +++ b/flow/designs/sky130hs/ibex/config.mk @@ -2,43 +2,14 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = sky130hs -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \ + $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v + +export VERILOG_INCLUDE_DIRS = \ + $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/ + +export SYNTH_HDL_FRONTEND = slang + export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 45 diff --git a/flow/designs/sky130hs/ibex/constraint.sdc b/flow/designs/sky130hs/ibex/constraint.sdc index 72bc0ce1a3..9927412616 100644 --- a/flow/designs/sky130hs/ibex/constraint.sdc +++ b/flow/designs/sky130hs/ibex/constraint.sdc @@ -1,6 +1,6 @@ current_design ibex_core -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 9.0 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/ibex/rules-base.json b/flow/designs/sky130hs/ibex/rules-base.json index 9f59b31015..87b458d33b 100644 --- a/flow/designs/sky130hs/ibex/rules-base.json +++ b/flow/designs/sky130hs/ibex/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 262420, + "value": 261133, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 19444, + "value": 19436, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1691, + "value": 1690, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1691, + "value": 1690, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 30, + "value": 130, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 787855, + "value": 908310, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,11 +44,11 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 38, + "value": 33, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.46, + "value": -0.19, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/sky130hs/jpeg/constraint.sdc b/flow/designs/sky130hs/jpeg/constraint.sdc index d9420273eb..4c40fe5a3f 100644 --- a/flow/designs/sky130hs/jpeg/constraint.sdc +++ b/flow/designs/sky130hs/jpeg/constraint.sdc @@ -1,6 +1,6 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 6.0 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/jpeg/rules-base.json b/flow/designs/sky130hs/jpeg/rules-base.json index ac0c8a220e..6bbaa98dba 100644 --- a/flow/designs/sky130hs/jpeg/rules-base.json +++ b/flow/designs/sky130hs/jpeg/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 654669.88, + "value": 653350.08, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 750737, + "value": 723127, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 63909, + "value": 63375, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 5557, + "value": 5511, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 5557, + "value": 5511, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 910, + "value": 166, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 2481556, + "value": 1619030, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -40,11 +40,11 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 3, + "value": 1, "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 810, + "value": 102, "compare": "<=" }, "finish__timing__setup__ws": { @@ -52,11 +52,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 779230, + "value": 760037, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 2779, + "value": 2755, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/sky130hs/riscv32i/constraint.sdc b/flow/designs/sky130hs/riscv32i/constraint.sdc index 4be7147ef9..a598e70954 100644 --- a/flow/designs/sky130hs/riscv32i/constraint.sdc +++ b/flow/designs/sky130hs/riscv32i/constraint.sdc @@ -1,4 +1,4 @@ -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 5.2 set clk_io_pct 0.2 @@ -9,10 +9,10 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [list] foreach input [all_inputs] { - if {$clk_port != $input} { - lappend $non_clock_inputs $input - } + if { $clk_port != $input } { + lappend $non_clock_inputs $input + } } -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/riscv32i/rules-base.json b/flow/designs/sky130hs/riscv32i/rules-base.json index 4a291e2f74..60e391e6ae 100644 --- a/flow/designs/sky130hs/riscv32i/rules-base.json +++ b/flow/designs/sky130hs/riscv32i/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 118571, + "value": 116710, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 7591, + "value": 7538, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 660, + "value": 656, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 660, + "value": 656, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 3, + "value": 26, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 347505, + "value": 369598, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 14, + "value": 16, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.32, + "value": -0.21, "compare": ">=" }, "finish__design__instance__area": { - "value": 124092, + "value": 134164, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 330, + "value": 328, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/src/cva6/README.md b/flow/designs/src/cva6/README.md index 0726796f5c..cd27453e1c 100644 --- a/flow/designs/src/cva6/README.md +++ b/flow/designs/src/cva6/README.md @@ -1 +1,3 @@ Extracted from https://github.com/openhwgroup/cva6 + +Based on commit 3a389af with some changes for the RAMs diff --git a/flow/designs/src/cva6/common/local/util/sram_cache.sv b/flow/designs/src/cva6/common/local/util/sram_cache.sv index f4ac1f3c5a..799c63afcd 100644 --- a/flow/designs/src/cva6/common/local/util/sram_cache.sv +++ b/flow/designs/src/cva6/common/local/util/sram_cache.sv @@ -52,7 +52,7 @@ module sram_cache #( rdata_o = rdata_user[DATA_AND_USER_WIDTH-1:DATA_WIDTH]; ruser_o = rdata_user[USER_WIDTH-1:0]; end - fakeram7_256x32 i_tc_sram_wrapper( + fakeram7_64x256 i_tc_sram_wrapper( .clk ( clk_i ), .ce_in ( req_i ), .we_in ( we_i ), @@ -91,7 +91,7 @@ module sram_cache #( rdata_o = rdata_user; ruser_o = '0; end - fakeram7_256x32 i_tc_sram_wrapper( + fakeram7_64x25 i_tc_sram_wrapper( .clk ( clk_i ), .ce_in ( req_i ), .we_in ( we_i ), diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv index 1948dd1c26..d078555ac4 100644 --- a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv @@ -39,7 +39,7 @@ module hpdcache_sram output logic [DATA_SIZE-1:0] rdata ); - fakeram7_256x32 ram_i ( + fakeram7_64x28 ram_i ( .clk(clk), .ce_in(cs), .we_in(we), diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv index 23a09d136c..d0cf76a389 100644 --- a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv @@ -39,7 +39,7 @@ module hpdcache_sram_wbyteenable input logic [DATA_SIZE/8-1:0] wbyteenable, output logic [DATA_SIZE-1:0] rdata ); - fakeram7_256x32 ram_i ( + fakeram7_128x64 ram_i ( .clk (clk), .ce_in(cs), .we_in(we), diff --git a/flow/designs/src/cva6/core/cvxif_example/cvxif_example_coprocessor.sv b/flow/designs/src/cva6/core/cvxif_example/cvxif_example_coprocessor.sv deleted file mode 100644 index 614b17e850..0000000000 --- a/flow/designs/src/cva6/core/cvxif_example/cvxif_example_coprocessor.sv +++ /dev/null @@ -1,152 +0,0 @@ -// Copyright 2024 Thales DIS France SAS -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -// You may obtain a copy of the License at https://solderpad.org/licenses/ -// -// Original Author: Guillaume Chauvon - -module cvxif_example_coprocessor - import cvxif_instr_pkg::*; -#( - // CVXIF Types - parameter int unsigned NrRgprPorts = 2, - parameter int unsigned XLEN = 32, - parameter type readregflags_t = logic, - parameter type writeregflags_t = logic, - parameter type id_t = logic, - parameter type hartid_t = logic, - parameter type x_compressed_req_t = logic, - parameter type x_compressed_resp_t = logic, - parameter type x_issue_req_t = logic, - parameter type x_issue_resp_t = logic, - parameter type x_register_t = logic, - parameter type x_commit_t = logic, - parameter type x_result_t = logic, - parameter type cvxif_req_t = logic, - parameter type cvxif_resp_t = logic, - localparam type registers_t = logic [NrRgprPorts-1:0][XLEN-1:0] -) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input cvxif_req_t cvxif_req_i, - output cvxif_resp_t cvxif_resp_o -); - - // Compressed interface signals - x_compressed_req_t compressed_req; - x_compressed_resp_t compressed_resp; - logic compressed_valid, compressed_ready; - // Issue interface signals - x_issue_req_t issue_req; - x_issue_resp_t issue_resp; - logic issue_valid, issue_ready; - - // Register interface signals - x_register_t register; - logic register_valid; - - // Decoder and alu signals - registers_t registers; - opcode_t opcode; - hartid_t issue_hartid, hartid; - id_t issue_id, id; - logic [4:0] issue_rd, rd; - logic [XLEN-1:0] result; - logic we; - - // Issue and Register interface - // Mandatory when X_ISSUE_REGISTER_SPLIT = 0 - assign cvxif_resp_o.compressed_ready = compressed_ready; - assign cvxif_resp_o.compressed_resp = compressed_resp; - assign cvxif_resp_o.issue_ready = issue_ready; - assign cvxif_resp_o.issue_resp = issue_resp; - assign cvxif_resp_o.register_ready = cvxif_resp_o.issue_ready; - - assign compressed_req = cvxif_req_i.compressed_req; - assign compressed_valid = cvxif_req_i.compressed_valid; - assign issue_req = cvxif_req_i.issue_req; - assign issue_valid = cvxif_req_i.issue_valid; - assign register = cvxif_req_i.register; - assign register_valid = cvxif_req_i.register_valid; - - compressed_instr_decoder #( - .copro_compressed_resp_t(cvxif_instr_pkg::copro_compressed_resp_t), - .NbInstr(cvxif_instr_pkg::NbCompInstr), - .CoproInstr(cvxif_instr_pkg::CoproCompInstr), - .x_compressed_req_t(x_compressed_req_t), - .x_compressed_resp_t(x_compressed_resp_t) - ) compressed_instr_decoder_i ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .compressed_valid_i(compressed_valid), - .compressed_req_i (compressed_req), - .compressed_ready_o(compressed_ready), - .compressed_resp_o (compressed_resp) - ); - - instr_decoder #( - .copro_issue_resp_t (cvxif_instr_pkg::copro_issue_resp_t), - .opcode_t (cvxif_instr_pkg::opcode_t), - .NbInstr (cvxif_instr_pkg::NbInstr), - .CoproInstr(cvxif_instr_pkg::CoproInstr), - .NrRgprPorts(NrRgprPorts), - .hartid_t (hartid_t), - .id_t (id_t), - .x_issue_req_t (x_issue_req_t), - .x_issue_resp_t (x_issue_resp_t), - .x_register_t (x_register_t), - .registers_t (registers_t) - ) instr_decoder_i ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .issue_valid_i (issue_valid), - .issue_req_i (issue_req), - .issue_ready_o (issue_ready), - .issue_resp_o (issue_resp), - .register_valid_i(register_valid), - .register_i (register), - .registers_o (registers), - .opcode_o (opcode), - .hartid_o (issue_hartid), - .id_o (issue_id), - .rd_o (issue_rd) - ); - - logic alu_valid; - // Result interface - copro_alu #( - .NrRgprPorts(NrRgprPorts), - .XLEN(XLEN), - .hartid_t(hartid_t), - .id_t(id_t), - .registers_t(registers_t) - ) i_copro_alu ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .registers_i(registers), - .opcode_i (opcode), - .hartid_i (issue_hartid), - .id_i (issue_id), - .rd_i (issue_rd), - .hartid_o (hartid), - .id_o (id), - .result_o (result), - .valid_o (alu_valid), - .rd_o (rd), - .we_o (we) - ); - - always_comb begin - cvxif_resp_o.result_valid = alu_valid; //TODO Should wait for ready from CPU - cvxif_resp_o.result.hartid = hartid; - cvxif_resp_o.result.id = id; - cvxif_resp_o.result.data = result; - cvxif_resp_o.result.rd = rd; - cvxif_resp_o.result.we = we; - end - - - -endmodule diff --git a/flow/designs/src/harness/.gitignore b/flow/designs/src/harness/.gitignore deleted file mode 100644 index 7f2238d06e..0000000000 --- a/flow/designs/src/harness/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -*.v -*.fir -*.json -*.v diff --git a/flow/designs/src/harness/design.sdc b/flow/designs/src/harness/design.sdc deleted file mode 100644 index b0fe5c6ab4..0000000000 --- a/flow/designs/src/harness/design.sdc +++ /dev/null @@ -1,12 +0,0 @@ -################################################################### - -# Created by write_sdc on Mon Jun 17 07:26:34 2019 - -################################################################### -set sdc_version 2.0 - -set_units -time ns -resistance kOhm -capacitance pF -voltage V -current mA -# Start with 250MHz for nangate45, relatively conservative -create_clock [get_ports clock] -period 4 -waveform {0 2} -set_clock_uncertainty 0 [get_clocks clock] -set_input_delay -clock clock -max 0 [get_ports clock] diff --git a/flow/designs/src/ibex/BUILD.bazel b/flow/designs/src/ibex/BUILD.bazel deleted file mode 100644 index 1639cf0a3b..0000000000 --- a/flow/designs/src/ibex/BUILD.bazel +++ /dev/null @@ -1,5 +0,0 @@ -filegroup( - name = "verilog", - srcs = glob(include = ["*.v"]), - visibility = ["//visibility:public"], -) diff --git a/flow/designs/src/ibex/ibex_alu.v b/flow/designs/src/ibex/ibex_alu.v deleted file mode 100644 index 1c008c800e..0000000000 --- a/flow/designs/src/ibex/ibex_alu.v +++ /dev/null @@ -1,729 +0,0 @@ -module ibex_alu ( - operator_i, - operand_a_i, - operand_b_i, - instr_first_cycle_i, - multdiv_operand_a_i, - multdiv_operand_b_i, - multdiv_sel_i, - imd_val_q_i, - imd_val_d_o, - imd_val_we_o, - adder_result_o, - adder_result_ext_o, - result_o, - comparison_result_o, - is_equal_result_o -); - localparam integer ibex_pkg_RV32BNone = 0; - parameter integer RV32B = ibex_pkg_RV32BNone; - input wire [5:0] operator_i; - input wire [31:0] operand_a_i; - input wire [31:0] operand_b_i; - input wire instr_first_cycle_i; - input wire [32:0] multdiv_operand_a_i; - input wire [32:0] multdiv_operand_b_i; - input wire multdiv_sel_i; - input wire [63:0] imd_val_q_i; - output reg [63:0] imd_val_d_o; - output reg [1:0] imd_val_we_o; - output wire [31:0] adder_result_o; - output wire [33:0] adder_result_ext_o; - output reg [31:0] result_o; - output wire comparison_result_o; - output wire is_equal_result_o; - wire [31:0] operand_a_rev; - wire [32:0] operand_b_neg; - generate - genvar k; - for (k = 0; k < 32; k = k + 1) begin : gen_rev_operand_a - assign operand_a_rev[k] = operand_a_i[31 - k]; - end - endgenerate - reg adder_op_b_negate; - wire [32:0] adder_in_a; - reg [32:0] adder_in_b; - wire [31:0] adder_result; - localparam [5:0] ibex_pkg_ALU_EQ = 23; - localparam [5:0] ibex_pkg_ALU_GE = 21; - localparam [5:0] ibex_pkg_ALU_GEU = 22; - localparam [5:0] ibex_pkg_ALU_LT = 19; - localparam [5:0] ibex_pkg_ALU_LTU = 20; - localparam [5:0] ibex_pkg_ALU_MAX = 27; - localparam [5:0] ibex_pkg_ALU_MAXU = 28; - localparam [5:0] ibex_pkg_ALU_MIN = 25; - localparam [5:0] ibex_pkg_ALU_MINU = 26; - localparam [5:0] ibex_pkg_ALU_NE = 24; - localparam [5:0] ibex_pkg_ALU_SLT = 37; - localparam [5:0] ibex_pkg_ALU_SLTU = 38; - localparam [5:0] ibex_pkg_ALU_SUB = 1; - always @(*) begin - adder_op_b_negate = 1'b0; - case (operator_i) - ibex_pkg_ALU_SUB, ibex_pkg_ALU_EQ, ibex_pkg_ALU_NE, ibex_pkg_ALU_GE, ibex_pkg_ALU_GEU, ibex_pkg_ALU_LT, ibex_pkg_ALU_LTU, ibex_pkg_ALU_SLT, ibex_pkg_ALU_SLTU, ibex_pkg_ALU_MIN, ibex_pkg_ALU_MINU, ibex_pkg_ALU_MAX, ibex_pkg_ALU_MAXU: adder_op_b_negate = 1'b1; - default: - ; - endcase - end - assign adder_in_a = (multdiv_sel_i ? multdiv_operand_a_i : {operand_a_i, 1'b1}); - assign operand_b_neg = {operand_b_i, 1'b0} ^ {33 {1'b1}}; - always @(*) - case (1'b1) - multdiv_sel_i: adder_in_b = multdiv_operand_b_i; - adder_op_b_negate: adder_in_b = operand_b_neg; - default: adder_in_b = {operand_b_i, 1'b0}; - endcase - assign adder_result_ext_o = $unsigned(adder_in_a) + $unsigned(adder_in_b); - assign adder_result = adder_result_ext_o[32:1]; - assign adder_result_o = adder_result; - wire is_equal; - reg is_greater_equal; - reg cmp_signed; - always @(*) - case (operator_i) - ibex_pkg_ALU_GE, ibex_pkg_ALU_LT, ibex_pkg_ALU_SLT, ibex_pkg_ALU_MIN, ibex_pkg_ALU_MAX: cmp_signed = 1'b1; - default: cmp_signed = 1'b0; - endcase - assign is_equal = adder_result == 32'b00000000000000000000000000000000; - assign is_equal_result_o = is_equal; - always @(*) - if ((operand_a_i[31] ^ operand_b_i[31]) == 1'b0) - is_greater_equal = adder_result[31] == 1'b0; - else - is_greater_equal = operand_a_i[31] ^ cmp_signed; - reg cmp_result; - always @(*) - case (operator_i) - ibex_pkg_ALU_EQ: cmp_result = is_equal; - ibex_pkg_ALU_NE: cmp_result = ~is_equal; - ibex_pkg_ALU_GE, ibex_pkg_ALU_GEU, ibex_pkg_ALU_MAX, ibex_pkg_ALU_MAXU: cmp_result = is_greater_equal; - ibex_pkg_ALU_LT, ibex_pkg_ALU_LTU, ibex_pkg_ALU_MIN, ibex_pkg_ALU_MINU, ibex_pkg_ALU_SLT, ibex_pkg_ALU_SLTU: cmp_result = ~is_greater_equal; - default: cmp_result = is_equal; - endcase - assign comparison_result_o = cmp_result; - reg shift_left; - wire shift_ones; - wire shift_arith; - wire shift_funnel; - wire shift_sbmode; - reg [5:0] shift_amt; - wire [5:0] shift_amt_compl; - reg [31:0] shift_operand; - reg [32:0] shift_result_ext; - reg unused_shift_result_ext; - reg [31:0] shift_result; - reg [31:0] shift_result_rev; - wire bfp_op; - wire [4:0] bfp_len; - wire [4:0] bfp_off; - wire [31:0] bfp_mask; - wire [31:0] bfp_mask_rev; - wire [31:0] bfp_result; - localparam [5:0] ibex_pkg_ALU_BFP = 49; - assign bfp_op = (RV32B != ibex_pkg_RV32BNone ? operator_i == ibex_pkg_ALU_BFP : 1'b0); - assign bfp_len = {~(|operand_b_i[27:24]), operand_b_i[27:24]}; - assign bfp_off = operand_b_i[20:16]; - assign bfp_mask = (RV32B != ibex_pkg_RV32BNone ? ~(32'hffffffff << bfp_len) : {32 {1'sb0}}); - generate - genvar i; - for (i = 0; i < 32; i = i + 1) begin : gen_rev_bfp_mask - assign bfp_mask_rev[i] = bfp_mask[31 - i]; - end - endgenerate - assign bfp_result = (RV32B != ibex_pkg_RV32BNone ? (~shift_result & operand_a_i) | ((operand_b_i & bfp_mask) << bfp_off) : {32 {1'sb0}}); - wire [1:1] sv2v_tmp_86907; - assign sv2v_tmp_86907 = operand_b_i[5] & shift_funnel; - always @(*) shift_amt[5] = sv2v_tmp_86907; - assign shift_amt_compl = 32 - operand_b_i[4:0]; - always @(*) - if (bfp_op) - shift_amt[4:0] = bfp_off; - else - shift_amt[4:0] = (instr_first_cycle_i ? (operand_b_i[5] && shift_funnel ? shift_amt_compl[4:0] : operand_b_i[4:0]) : (operand_b_i[5] && shift_funnel ? operand_b_i[4:0] : shift_amt_compl[4:0])); - localparam [5:0] ibex_pkg_ALU_SBCLR = 44; - localparam [5:0] ibex_pkg_ALU_SBINV = 45; - localparam [5:0] ibex_pkg_ALU_SBSET = 43; - assign shift_sbmode = (RV32B != ibex_pkg_RV32BNone ? ((operator_i == ibex_pkg_ALU_SBSET) | (operator_i == ibex_pkg_ALU_SBCLR)) | (operator_i == ibex_pkg_ALU_SBINV) : 1'b0); - localparam [5:0] ibex_pkg_ALU_FSL = 41; - localparam [5:0] ibex_pkg_ALU_FSR = 42; - localparam [5:0] ibex_pkg_ALU_ROL = 14; - localparam [5:0] ibex_pkg_ALU_ROR = 13; - localparam [5:0] ibex_pkg_ALU_SLL = 10; - localparam [5:0] ibex_pkg_ALU_SLO = 12; - always @(*) begin - case (operator_i) - ibex_pkg_ALU_SLL: shift_left = 1'b1; - ibex_pkg_ALU_SLO, ibex_pkg_ALU_BFP: shift_left = (RV32B != ibex_pkg_RV32BNone ? 1'b1 : 1'b0); - ibex_pkg_ALU_ROL: shift_left = (RV32B != ibex_pkg_RV32BNone ? instr_first_cycle_i : 0); - ibex_pkg_ALU_ROR: shift_left = (RV32B != ibex_pkg_RV32BNone ? ~instr_first_cycle_i : 0); - ibex_pkg_ALU_FSL: shift_left = (RV32B != ibex_pkg_RV32BNone ? (shift_amt[5] ? ~instr_first_cycle_i : instr_first_cycle_i) : 1'b0); - ibex_pkg_ALU_FSR: shift_left = (RV32B != ibex_pkg_RV32BNone ? (shift_amt[5] ? instr_first_cycle_i : ~instr_first_cycle_i) : 1'b0); - default: shift_left = 1'b0; - endcase - if (shift_sbmode) - shift_left = 1'b1; - end - localparam [5:0] ibex_pkg_ALU_SRA = 8; - assign shift_arith = operator_i == ibex_pkg_ALU_SRA; - localparam [5:0] ibex_pkg_ALU_SRO = 11; - assign shift_ones = (RV32B != ibex_pkg_RV32BNone ? (operator_i == ibex_pkg_ALU_SLO) | (operator_i == ibex_pkg_ALU_SRO) : 1'b0); - assign shift_funnel = (RV32B != ibex_pkg_RV32BNone ? (operator_i == ibex_pkg_ALU_FSL) | (operator_i == ibex_pkg_ALU_FSR) : 1'b0); - always @(*) begin - if (RV32B == ibex_pkg_RV32BNone) - shift_operand = (shift_left ? operand_a_rev : operand_a_i); - else - case (1'b1) - bfp_op: shift_operand = bfp_mask_rev; - shift_sbmode: shift_operand = 32'h80000000; - default: shift_operand = (shift_left ? operand_a_rev : operand_a_i); - endcase - shift_result_ext = $unsigned($signed({shift_ones | (shift_arith & shift_operand[31]), shift_operand}) >>> shift_amt[4:0]); - shift_result = shift_result_ext[31:0]; - unused_shift_result_ext = shift_result_ext[32]; - begin : sv2v_autoblock_6 - reg [31:0] i; - for (i = 0; i < 32; i = i + 1) - shift_result_rev[i] = shift_result[31 - i]; - end - shift_result = (shift_left ? shift_result_rev : shift_result); - end - wire bwlogic_or; - wire bwlogic_and; - wire [31:0] bwlogic_operand_b; - wire [31:0] bwlogic_or_result; - wire [31:0] bwlogic_and_result; - wire [31:0] bwlogic_xor_result; - reg [31:0] bwlogic_result; - reg bwlogic_op_b_negate; - localparam [5:0] ibex_pkg_ALU_ANDN = 7; - localparam [5:0] ibex_pkg_ALU_CMIX = 40; - localparam [5:0] ibex_pkg_ALU_ORN = 6; - localparam [5:0] ibex_pkg_ALU_XNOR = 5; - always @(*) - case (operator_i) - ibex_pkg_ALU_XNOR, ibex_pkg_ALU_ORN, ibex_pkg_ALU_ANDN: bwlogic_op_b_negate = (RV32B != ibex_pkg_RV32BNone ? 1'b1 : 1'b0); - ibex_pkg_ALU_CMIX: bwlogic_op_b_negate = (RV32B != ibex_pkg_RV32BNone ? ~instr_first_cycle_i : 1'b0); - default: bwlogic_op_b_negate = 1'b0; - endcase - assign bwlogic_operand_b = (bwlogic_op_b_negate ? operand_b_neg[32:1] : operand_b_i); - assign bwlogic_or_result = operand_a_i | bwlogic_operand_b; - assign bwlogic_and_result = operand_a_i & bwlogic_operand_b; - assign bwlogic_xor_result = operand_a_i ^ bwlogic_operand_b; - localparam [5:0] ibex_pkg_ALU_OR = 3; - assign bwlogic_or = (operator_i == ibex_pkg_ALU_OR) | (operator_i == ibex_pkg_ALU_ORN); - localparam [5:0] ibex_pkg_ALU_AND = 4; - assign bwlogic_and = (operator_i == ibex_pkg_ALU_AND) | (operator_i == ibex_pkg_ALU_ANDN); - always @(*) - case (1'b1) - bwlogic_or: bwlogic_result = bwlogic_or_result; - bwlogic_and: bwlogic_result = bwlogic_and_result; - default: bwlogic_result = bwlogic_xor_result; - endcase - wire [5:0] bitcnt_result; - wire [31:0] minmax_result; - reg [31:0] pack_result; - wire [31:0] sext_result; - reg [31:0] singlebit_result; - reg [31:0] rev_result; - reg [31:0] shuffle_result; - reg [31:0] butterfly_result; - reg [31:0] invbutterfly_result; - reg [31:0] clmul_result; - reg [31:0] multicycle_result; - localparam [5:0] ibex_pkg_ALU_BDEP = 48; - localparam [5:0] ibex_pkg_ALU_BEXT = 47; - localparam [5:0] ibex_pkg_ALU_CLMULH = 52; - localparam [5:0] ibex_pkg_ALU_CLMULR = 51; - localparam [5:0] ibex_pkg_ALU_CLZ = 34; - localparam [5:0] ibex_pkg_ALU_CMOV = 39; - localparam [5:0] ibex_pkg_ALU_CRC32C_B = 54; - localparam [5:0] ibex_pkg_ALU_CRC32C_H = 56; - localparam [5:0] ibex_pkg_ALU_CRC32C_W = 58; - localparam [5:0] ibex_pkg_ALU_CRC32_B = 53; - localparam [5:0] ibex_pkg_ALU_CRC32_H = 55; - localparam [5:0] ibex_pkg_ALU_CRC32_W = 57; - localparam [5:0] ibex_pkg_ALU_CTZ = 35; - localparam [5:0] ibex_pkg_ALU_GORC = 16; - localparam [5:0] ibex_pkg_ALU_PACKH = 31; - localparam [5:0] ibex_pkg_ALU_PACKU = 30; - localparam [5:0] ibex_pkg_ALU_SEXTB = 32; - localparam [5:0] ibex_pkg_ALU_UNSHFL = 18; - localparam integer ibex_pkg_RV32BFull = 2; - generate - if (RV32B != ibex_pkg_RV32BNone) begin : g_alu_rvb - wire zbe_op; - wire bitcnt_ctz; - wire bitcnt_clz; - wire bitcnt_cz; - reg [31:0] bitcnt_bits; - wire [31:0] bitcnt_mask_op; - reg [31:0] bitcnt_bit_mask; - reg [191:0] bitcnt_partial; - wire [31:0] bitcnt_partial_lsb_d; - wire [31:0] bitcnt_partial_msb_d; - assign bitcnt_ctz = operator_i == ibex_pkg_ALU_CTZ; - assign bitcnt_clz = operator_i == ibex_pkg_ALU_CLZ; - assign bitcnt_cz = bitcnt_ctz | bitcnt_clz; - assign bitcnt_result = bitcnt_partial[0+:6]; - assign bitcnt_mask_op = (bitcnt_clz ? operand_a_rev : operand_a_i); - always @(*) begin - bitcnt_bit_mask = bitcnt_mask_op; - bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 1); - bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 2); - bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 4); - bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 8); - bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 16); - bitcnt_bit_mask = ~bitcnt_bit_mask; - end - assign zbe_op = (operator_i == ibex_pkg_ALU_BEXT) | (operator_i == ibex_pkg_ALU_BDEP); - always @(*) - case (1'b1) - zbe_op: bitcnt_bits = operand_b_i; - bitcnt_cz: bitcnt_bits = bitcnt_bit_mask & ~bitcnt_mask_op; - default: bitcnt_bits = operand_a_i; - endcase - always @(*) begin - bitcnt_partial = {32 {6'b000000}}; - begin : sv2v_autoblock_7 - reg [31:0] i; - for (i = 1; i < 32; i = i + 2) - bitcnt_partial[(31 - i) * 6+:6] = {5'h00, bitcnt_bits[i]} + {5'h00, bitcnt_bits[i - 1]}; - end - begin : sv2v_autoblock_8 - reg [31:0] i; - for (i = 3; i < 32; i = i + 4) - bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(33 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6]; - end - begin : sv2v_autoblock_9 - reg [31:0] i; - for (i = 7; i < 32; i = i + 8) - bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(35 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6]; - end - begin : sv2v_autoblock_10 - reg [31:0] i; - for (i = 15; i < 32; i = i + 16) - bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(39 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6]; - end - bitcnt_partial[0+:6] = bitcnt_partial[96+:6] + bitcnt_partial[0+:6]; - bitcnt_partial[48+:6] = bitcnt_partial[96+:6] + bitcnt_partial[48+:6]; - begin : sv2v_autoblock_11 - reg [31:0] i; - for (i = 11; i < 32; i = i + 8) - bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(35 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6]; - end - begin : sv2v_autoblock_12 - reg [31:0] i; - for (i = 5; i < 32; i = i + 4) - bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(33 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6]; - end - bitcnt_partial[186+:6] = {5'h00, bitcnt_bits[0]}; - begin : sv2v_autoblock_13 - reg [31:0] i; - for (i = 2; i < 32; i = i + 2) - bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(32 - i) * 6+:6] + {5'h00, bitcnt_bits[i]}; - end - end - assign minmax_result = (cmp_result ? operand_a_i : operand_b_i); - wire packu; - wire packh; - assign packu = operator_i == ibex_pkg_ALU_PACKU; - assign packh = operator_i == ibex_pkg_ALU_PACKH; - always @(*) - case (1'b1) - packu: pack_result = {operand_b_i[31:16], operand_a_i[31:16]}; - packh: pack_result = {16'h0000, operand_b_i[7:0], operand_a_i[7:0]}; - default: pack_result = {operand_b_i[15:0], operand_a_i[15:0]}; - endcase - assign sext_result = (operator_i == ibex_pkg_ALU_SEXTB ? {{24 {operand_a_i[7]}}, operand_a_i[7:0]} : {{16 {operand_a_i[15]}}, operand_a_i[15:0]}); - always @(*) - case (operator_i) - ibex_pkg_ALU_SBSET: singlebit_result = operand_a_i | shift_result; - ibex_pkg_ALU_SBCLR: singlebit_result = operand_a_i & ~shift_result; - ibex_pkg_ALU_SBINV: singlebit_result = operand_a_i ^ shift_result; - default: singlebit_result = {31'h00000000, shift_result[0]}; - endcase - wire [4:0] zbp_shift_amt; - wire gorc_op; - assign gorc_op = operator_i == ibex_pkg_ALU_GORC; - assign zbp_shift_amt[2:0] = (RV32B == ibex_pkg_RV32BFull ? shift_amt[2:0] : {3 {&shift_amt[2:0]}}); - assign zbp_shift_amt[4:3] = (RV32B == ibex_pkg_RV32BFull ? shift_amt[4:3] : {2 {&shift_amt[4:3]}}); - always @(*) begin - rev_result = operand_a_i; - if (zbp_shift_amt[0]) - rev_result = ((gorc_op ? rev_result : 32'h00000000) | ((rev_result & 32'h55555555) << 1)) | ((rev_result & 32'haaaaaaaa) >> 1); - if (zbp_shift_amt[1]) - rev_result = ((gorc_op ? rev_result : 32'h00000000) | ((rev_result & 32'h33333333) << 2)) | ((rev_result & 32'hcccccccc) >> 2); - if (zbp_shift_amt[2]) - rev_result = ((gorc_op ? rev_result : 32'h00000000) | ((rev_result & 32'h0f0f0f0f) << 4)) | ((rev_result & 32'hf0f0f0f0) >> 4); - if (zbp_shift_amt[3]) - rev_result = ((gorc_op & (RV32B == ibex_pkg_RV32BFull) ? rev_result : 32'h00000000) | ((rev_result & 32'h00ff00ff) << 8)) | ((rev_result & 32'hff00ff00) >> 8); - if (zbp_shift_amt[4]) - rev_result = ((gorc_op & (RV32B == ibex_pkg_RV32BFull) ? rev_result : 32'h00000000) | ((rev_result & 32'h0000ffff) << 16)) | ((rev_result & 32'hffff0000) >> 16); - end - wire crc_hmode; - wire crc_bmode; - wire [31:0] clmul_result_rev; - if (RV32B == ibex_pkg_RV32BFull) begin : gen_alu_rvb_full - localparam [127:0] SHUFFLE_MASK_L = {32'h00ff0000, 32'h0f000f00, 32'h30303030, 32'h44444444}; - localparam [127:0] SHUFFLE_MASK_R = {32'h0000ff00, 32'h00f000f0, 32'h0c0c0c0c, 32'h22222222}; - localparam [127:0] FLIP_MASK_L = {32'h22001100, 32'h00440000, 32'h44110000, 32'h11000000}; - localparam [127:0] FLIP_MASK_R = {32'h00880044, 32'h00002200, 32'h00008822, 32'h00000088}; - wire [31:0] SHUFFLE_MASK_NOT [0:3]; - for (i = 0; i < 4; i = i + 1) begin : gen_shuffle_mask_not - assign SHUFFLE_MASK_NOT[i] = ~(SHUFFLE_MASK_L[(3 - i) * 32+:32] | SHUFFLE_MASK_R[(3 - i) * 32+:32]); - end - wire shuffle_flip; - assign shuffle_flip = operator_i == ibex_pkg_ALU_UNSHFL; - reg [3:0] shuffle_mode; - always @(*) begin - shuffle_result = operand_a_i; - if (shuffle_flip) begin - shuffle_mode[3] = shift_amt[0]; - shuffle_mode[2] = shift_amt[1]; - shuffle_mode[1] = shift_amt[2]; - shuffle_mode[0] = shift_amt[3]; - end - else - shuffle_mode = shift_amt[3:0]; - if (shuffle_flip) - shuffle_result = ((((((((shuffle_result & 32'h88224411) | ((shuffle_result << 6) & FLIP_MASK_L[96+:32])) | ((shuffle_result >> 6) & FLIP_MASK_R[96+:32])) | ((shuffle_result << 9) & FLIP_MASK_L[64+:32])) | ((shuffle_result >> 9) & FLIP_MASK_R[64+:32])) | ((shuffle_result << 15) & FLIP_MASK_L[32+:32])) | ((shuffle_result >> 15) & FLIP_MASK_R[32+:32])) | ((shuffle_result << 21) & FLIP_MASK_L[0+:32])) | ((shuffle_result >> 21) & FLIP_MASK_R[0+:32]); - if (shuffle_mode[3]) - shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[0]) | (((shuffle_result << 8) & SHUFFLE_MASK_L[96+:32]) | ((shuffle_result >> 8) & SHUFFLE_MASK_R[96+:32])); - if (shuffle_mode[2]) - shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[1]) | (((shuffle_result << 4) & SHUFFLE_MASK_L[64+:32]) | ((shuffle_result >> 4) & SHUFFLE_MASK_R[64+:32])); - if (shuffle_mode[1]) - shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[2]) | (((shuffle_result << 2) & SHUFFLE_MASK_L[32+:32]) | ((shuffle_result >> 2) & SHUFFLE_MASK_R[32+:32])); - if (shuffle_mode[0]) - shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[3]) | (((shuffle_result << 1) & SHUFFLE_MASK_L[0+:32]) | ((shuffle_result >> 1) & SHUFFLE_MASK_R[0+:32])); - if (shuffle_flip) - shuffle_result = ((((((((shuffle_result & 32'h88224411) | ((shuffle_result << 6) & FLIP_MASK_L[96+:32])) | ((shuffle_result >> 6) & FLIP_MASK_R[96+:32])) | ((shuffle_result << 9) & FLIP_MASK_L[64+:32])) | ((shuffle_result >> 9) & FLIP_MASK_R[64+:32])) | ((shuffle_result << 15) & FLIP_MASK_L[32+:32])) | ((shuffle_result >> 15) & FLIP_MASK_R[32+:32])) | ((shuffle_result << 21) & FLIP_MASK_L[0+:32])) | ((shuffle_result >> 21) & FLIP_MASK_R[0+:32]); - end - reg [191:0] bitcnt_partial_q; - for (i = 0; i < 32; i = i + 1) begin : gen_bitcnt_reg_in_lsb - assign bitcnt_partial_lsb_d[i] = bitcnt_partial[(31 - i) * 6]; - end - for (i = 0; i < 16; i = i + 1) begin : gen_bitcnt_reg_in_b1 - assign bitcnt_partial_msb_d[i] = bitcnt_partial[((31 - ((2 * i) + 1)) * 6) + 1]; - end - for (i = 0; i < 8; i = i + 1) begin : gen_bitcnt_reg_in_b2 - assign bitcnt_partial_msb_d[16 + i] = bitcnt_partial[((31 - ((4 * i) + 3)) * 6) + 2]; - end - for (i = 0; i < 4; i = i + 1) begin : gen_bitcnt_reg_in_b3 - assign bitcnt_partial_msb_d[24 + i] = bitcnt_partial[((31 - ((8 * i) + 7)) * 6) + 3]; - end - for (i = 0; i < 2; i = i + 1) begin : gen_bitcnt_reg_in_b4 - assign bitcnt_partial_msb_d[28 + i] = bitcnt_partial[((31 - ((16 * i) + 15)) * 6) + 4]; - end - assign bitcnt_partial_msb_d[30] = bitcnt_partial[5]; - assign bitcnt_partial_msb_d[31] = 1'b0; - always @(*) begin - bitcnt_partial_q = {32 {6'b000000}}; - begin : sv2v_autoblock_14 - reg [31:0] i; - for (i = 0; i < 32; i = i + 1) - begin : gen_bitcnt_reg_out_lsb - bitcnt_partial_q[(31 - i) * 6] = imd_val_q_i[32 + i]; - end - end - begin : sv2v_autoblock_15 - reg [31:0] i; - for (i = 0; i < 16; i = i + 1) - begin : gen_bitcnt_reg_out_b1 - bitcnt_partial_q[((31 - ((2 * i) + 1)) * 6) + 1] = imd_val_q_i[i]; - end - end - begin : sv2v_autoblock_16 - reg [31:0] i; - for (i = 0; i < 8; i = i + 1) - begin : gen_bitcnt_reg_out_b2 - bitcnt_partial_q[((31 - ((4 * i) + 3)) * 6) + 2] = imd_val_q_i[16 + i]; - end - end - begin : sv2v_autoblock_17 - reg [31:0] i; - for (i = 0; i < 4; i = i + 1) - begin : gen_bitcnt_reg_out_b3 - bitcnt_partial_q[((31 - ((8 * i) + 7)) * 6) + 3] = imd_val_q_i[24 + i]; - end - end - begin : sv2v_autoblock_18 - reg [31:0] i; - for (i = 0; i < 2; i = i + 1) - begin : gen_bitcnt_reg_out_b4 - bitcnt_partial_q[((31 - ((16 * i) + 15)) * 6) + 4] = imd_val_q_i[28 + i]; - end - end - bitcnt_partial_q[5] = imd_val_q_i[30]; - end - wire [31:0] butterfly_mask_l [0:4]; - wire [31:0] butterfly_mask_r [0:4]; - wire [31:0] butterfly_mask_not [0:4]; - wire [31:0] lrotc_stage [0:4]; - genvar stg; - for (stg = 0; stg < 5; stg = stg + 1) begin : gen_butterfly_ctrl_stage - genvar seg; - for (seg = 0; seg < (2 ** stg); seg = seg + 1) begin : gen_butterfly_ctrl - assign lrotc_stage[stg][((2 * (16 >> stg)) * (seg + 1)) - 1:(2 * (16 >> stg)) * seg] = {{16 >> stg {1'b0}}, {16 >> stg {1'b1}}} << bitcnt_partial_q[((32 - ((16 >> stg) * ((2 * seg) + 1))) * 6) + ($clog2(16 >> stg) >= 0 ? $clog2(16 >> stg) : ($clog2(16 >> stg) + ($clog2(16 >> stg) >= 0 ? $clog2(16 >> stg) + 1 : 1 - $clog2(16 >> stg))) - 1)-:($clog2(16 >> stg) >= 0 ? $clog2(16 >> stg) + 1 : 1 - $clog2(16 >> stg))]; - assign butterfly_mask_l[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)] = ~lrotc_stage[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)]; - assign butterfly_mask_r[stg][((16 >> stg) * ((2 * seg) + 1)) - 1:(16 >> stg) * (2 * seg)] = ~lrotc_stage[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)]; - assign butterfly_mask_l[stg][((16 >> stg) * ((2 * seg) + 1)) - 1:(16 >> stg) * (2 * seg)] = {((((16 >> stg) * ((2 * seg) + 1)) - 1) >= ((16 >> stg) * (2 * seg)) ? ((((16 >> stg) * ((2 * seg) + 1)) - 1) - ((16 >> stg) * (2 * seg))) + 1 : (((16 >> stg) * (2 * seg)) - (((16 >> stg) * ((2 * seg) + 1)) - 1)) + 1) {1'sb0}}; - assign butterfly_mask_r[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)] = {((((16 >> stg) * ((2 * seg) + 2)) - 1) >= ((16 >> stg) * ((2 * seg) + 1)) ? ((((16 >> stg) * ((2 * seg) + 2)) - 1) - ((16 >> stg) * ((2 * seg) + 1))) + 1 : (((16 >> stg) * ((2 * seg) + 1)) - (((16 >> stg) * ((2 * seg) + 2)) - 1)) + 1) {1'sb0}}; - end - end - for (stg = 0; stg < 5; stg = stg + 1) begin : gen_butterfly_not - assign butterfly_mask_not[stg] = ~(butterfly_mask_l[stg] | butterfly_mask_r[stg]); - end - always @(*) begin - butterfly_result = operand_a_i; - butterfly_result = ((butterfly_result & butterfly_mask_not[0]) | ((butterfly_result & butterfly_mask_l[0]) >> 16)) | ((butterfly_result & butterfly_mask_r[0]) << 16); - butterfly_result = ((butterfly_result & butterfly_mask_not[1]) | ((butterfly_result & butterfly_mask_l[1]) >> 8)) | ((butterfly_result & butterfly_mask_r[1]) << 8); - butterfly_result = ((butterfly_result & butterfly_mask_not[2]) | ((butterfly_result & butterfly_mask_l[2]) >> 4)) | ((butterfly_result & butterfly_mask_r[2]) << 4); - butterfly_result = ((butterfly_result & butterfly_mask_not[3]) | ((butterfly_result & butterfly_mask_l[3]) >> 2)) | ((butterfly_result & butterfly_mask_r[3]) << 2); - butterfly_result = ((butterfly_result & butterfly_mask_not[4]) | ((butterfly_result & butterfly_mask_l[4]) >> 1)) | ((butterfly_result & butterfly_mask_r[4]) << 1); - butterfly_result = butterfly_result & operand_b_i; - end - always @(*) begin - invbutterfly_result = operand_a_i & operand_b_i; - invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[4]) | ((invbutterfly_result & butterfly_mask_l[4]) >> 1)) | ((invbutterfly_result & butterfly_mask_r[4]) << 1); - invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[3]) | ((invbutterfly_result & butterfly_mask_l[3]) >> 2)) | ((invbutterfly_result & butterfly_mask_r[3]) << 2); - invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[2]) | ((invbutterfly_result & butterfly_mask_l[2]) >> 4)) | ((invbutterfly_result & butterfly_mask_r[2]) << 4); - invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[1]) | ((invbutterfly_result & butterfly_mask_l[1]) >> 8)) | ((invbutterfly_result & butterfly_mask_r[1]) << 8); - invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[0]) | ((invbutterfly_result & butterfly_mask_l[0]) >> 16)) | ((invbutterfly_result & butterfly_mask_r[0]) << 16); - end - wire clmul_rmode; - wire clmul_hmode; - reg [31:0] clmul_op_a; - reg [31:0] clmul_op_b; - wire [31:0] operand_b_rev; - wire [31:0] clmul_and_stage [0:31]; - wire [31:0] clmul_xor_stage1 [0:15]; - wire [31:0] clmul_xor_stage2 [0:7]; - wire [31:0] clmul_xor_stage3 [0:3]; - wire [31:0] clmul_xor_stage4 [0:1]; - wire [31:0] clmul_result_raw; - for (i = 0; i < 32; i = i + 1) begin : gen_rev_operand_b - assign operand_b_rev[i] = operand_b_i[31 - i]; - end - assign clmul_rmode = operator_i == ibex_pkg_ALU_CLMULR; - assign clmul_hmode = operator_i == ibex_pkg_ALU_CLMULH; - localparam [31:0] CRC32_POLYNOMIAL = 32'h04c11db7; - localparam [31:0] CRC32_MU_REV = 32'hf7011641; - localparam [31:0] CRC32C_POLYNOMIAL = 32'h1edc6f41; - localparam [31:0] CRC32C_MU_REV = 32'hdea713f1; - wire crc_op; - wire crc_cpoly; - reg [31:0] crc_operand; - wire [31:0] crc_poly; - wire [31:0] crc_mu_rev; - assign crc_op = (((((operator_i == ibex_pkg_ALU_CRC32C_W) | (operator_i == ibex_pkg_ALU_CRC32_W)) | (operator_i == ibex_pkg_ALU_CRC32C_H)) | (operator_i == ibex_pkg_ALU_CRC32_H)) | (operator_i == ibex_pkg_ALU_CRC32C_B)) | (operator_i == ibex_pkg_ALU_CRC32_B); - assign crc_cpoly = ((operator_i == ibex_pkg_ALU_CRC32C_W) | (operator_i == ibex_pkg_ALU_CRC32C_H)) | (operator_i == ibex_pkg_ALU_CRC32C_B); - assign crc_hmode = (operator_i == ibex_pkg_ALU_CRC32_H) | (operator_i == ibex_pkg_ALU_CRC32C_H); - assign crc_bmode = (operator_i == ibex_pkg_ALU_CRC32_B) | (operator_i == ibex_pkg_ALU_CRC32C_B); - assign crc_poly = (crc_cpoly ? CRC32C_POLYNOMIAL : CRC32_POLYNOMIAL); - assign crc_mu_rev = (crc_cpoly ? CRC32C_MU_REV : CRC32_MU_REV); - always @(*) - case (1'b1) - crc_bmode: crc_operand = {operand_a_i[7:0], 24'h000000}; - crc_hmode: crc_operand = {operand_a_i[15:0], 16'h0000}; - default: crc_operand = operand_a_i; - endcase - always @(*) - if (crc_op) begin - clmul_op_a = (instr_first_cycle_i ? crc_operand : imd_val_q_i[32+:32]); - clmul_op_b = (instr_first_cycle_i ? crc_mu_rev : crc_poly); - end - else begin - clmul_op_a = (clmul_rmode | clmul_hmode ? operand_a_rev : operand_a_i); - clmul_op_b = (clmul_rmode | clmul_hmode ? operand_b_rev : operand_b_i); - end - for (i = 0; i < 32; i = i + 1) begin : gen_clmul_and_op - assign clmul_and_stage[i] = (clmul_op_b[i] ? clmul_op_a << i : {32 {1'sb0}}); - end - for (i = 0; i < 16; i = i + 1) begin : gen_clmul_xor_op_l1 - assign clmul_xor_stage1[i] = clmul_and_stage[2 * i] ^ clmul_and_stage[(2 * i) + 1]; - end - for (i = 0; i < 8; i = i + 1) begin : gen_clmul_xor_op_l2 - assign clmul_xor_stage2[i] = clmul_xor_stage1[2 * i] ^ clmul_xor_stage1[(2 * i) + 1]; - end - for (i = 0; i < 4; i = i + 1) begin : gen_clmul_xor_op_l3 - assign clmul_xor_stage3[i] = clmul_xor_stage2[2 * i] ^ clmul_xor_stage2[(2 * i) + 1]; - end - for (i = 0; i < 2; i = i + 1) begin : gen_clmul_xor_op_l4 - assign clmul_xor_stage4[i] = clmul_xor_stage3[2 * i] ^ clmul_xor_stage3[(2 * i) + 1]; - end - assign clmul_result_raw = clmul_xor_stage4[0] ^ clmul_xor_stage4[1]; - for (i = 0; i < 32; i = i + 1) begin : gen_rev_clmul_result - assign clmul_result_rev[i] = clmul_result_raw[31 - i]; - end - always @(*) - case (1'b1) - clmul_rmode: clmul_result = clmul_result_rev; - clmul_hmode: clmul_result = {1'b0, clmul_result_rev[31:1]}; - default: clmul_result = clmul_result_raw; - endcase - end - else begin : gen_alu_rvb_notfull - wire [31:0] unused_imd_val_q_1; - assign unused_imd_val_q_1 = imd_val_q_i[0+:32]; - wire [32:1] sv2v_tmp_8C42B; - assign sv2v_tmp_8C42B = {32 {1'sb0}}; - always @(*) shuffle_result = sv2v_tmp_8C42B; - wire [32:1] sv2v_tmp_B0AD4; - assign sv2v_tmp_B0AD4 = {32 {1'sb0}}; - always @(*) butterfly_result = sv2v_tmp_B0AD4; - wire [32:1] sv2v_tmp_AFC2C; - assign sv2v_tmp_AFC2C = {32 {1'sb0}}; - always @(*) invbutterfly_result = sv2v_tmp_AFC2C; - wire [32:1] sv2v_tmp_3A741; - assign sv2v_tmp_3A741 = {32 {1'sb0}}; - always @(*) clmul_result = sv2v_tmp_3A741; - assign bitcnt_partial_lsb_d = {32 {1'sb0}}; - assign bitcnt_partial_msb_d = {32 {1'sb0}}; - assign clmul_result_rev = {32 {1'sb0}}; - assign crc_bmode = 1'b0; - assign crc_hmode = 1'b0; - end - always @(*) - case (operator_i) - ibex_pkg_ALU_CMOV: begin - multicycle_result = (operand_b_i == 32'h00000000 ? operand_a_i : imd_val_q_i[32+:32]); - imd_val_d_o = {operand_a_i, 32'h00000000}; - if (instr_first_cycle_i) - imd_val_we_o = 2'b01; - else - imd_val_we_o = 2'b00; - end - ibex_pkg_ALU_CMIX: begin - multicycle_result = imd_val_q_i[32+:32] | bwlogic_and_result; - imd_val_d_o = {bwlogic_and_result, 32'h00000000}; - if (instr_first_cycle_i) - imd_val_we_o = 2'b01; - else - imd_val_we_o = 2'b00; - end - ibex_pkg_ALU_FSR, ibex_pkg_ALU_FSL, ibex_pkg_ALU_ROL, ibex_pkg_ALU_ROR: begin - if (shift_amt[4:0] == 5'h00) - multicycle_result = (shift_amt[5] ? operand_a_i : imd_val_q_i[32+:32]); - else - multicycle_result = imd_val_q_i[32+:32] | shift_result; - imd_val_d_o = {shift_result, 32'h00000000}; - if (instr_first_cycle_i) - imd_val_we_o = 2'b01; - else - imd_val_we_o = 2'b00; - end - ibex_pkg_ALU_CRC32_W, ibex_pkg_ALU_CRC32C_W, ibex_pkg_ALU_CRC32_H, ibex_pkg_ALU_CRC32C_H, ibex_pkg_ALU_CRC32_B, ibex_pkg_ALU_CRC32C_B: - if (RV32B == ibex_pkg_RV32BFull) begin - case (1'b1) - crc_bmode: multicycle_result = clmul_result_rev ^ (operand_a_i >> 8); - crc_hmode: multicycle_result = clmul_result_rev ^ (operand_a_i >> 16); - default: multicycle_result = clmul_result_rev; - endcase - imd_val_d_o = {clmul_result_rev, 32'h00000000}; - if (instr_first_cycle_i) - imd_val_we_o = 2'b01; - else - imd_val_we_o = 2'b00; - end - else begin - imd_val_d_o = {operand_a_i, 32'h00000000}; - imd_val_we_o = 2'b00; - multicycle_result = {32 {1'sb0}}; - end - ibex_pkg_ALU_BEXT, ibex_pkg_ALU_BDEP: - if (RV32B == ibex_pkg_RV32BFull) begin - multicycle_result = (operator_i == ibex_pkg_ALU_BDEP ? butterfly_result : invbutterfly_result); - imd_val_d_o = {bitcnt_partial_lsb_d, bitcnt_partial_msb_d}; - if (instr_first_cycle_i) - imd_val_we_o = 2'b11; - else - imd_val_we_o = 2'b00; - end - else begin - imd_val_d_o = {operand_a_i, 32'h00000000}; - imd_val_we_o = 2'b00; - multicycle_result = {32 {1'sb0}}; - end - default: begin - imd_val_d_o = {operand_a_i, 32'h00000000}; - imd_val_we_o = 2'b00; - multicycle_result = {32 {1'sb0}}; - end - endcase - end - else begin : g_no_alu_rvb - wire [63:0] unused_imd_val_q; - assign unused_imd_val_q = imd_val_q_i; - wire [31:0] unused_butterfly_result; - assign unused_butterfly_result = butterfly_result; - wire [31:0] unused_invbutterfly_result; - assign unused_invbutterfly_result = invbutterfly_result; - assign bitcnt_result = {6 {1'sb0}}; - assign minmax_result = {32 {1'sb0}}; - wire [32:1] sv2v_tmp_68181; - assign sv2v_tmp_68181 = {32 {1'sb0}}; - always @(*) pack_result = sv2v_tmp_68181; - assign sext_result = {32 {1'sb0}}; - wire [32:1] sv2v_tmp_D756E; - assign sv2v_tmp_D756E = {32 {1'sb0}}; - always @(*) singlebit_result = sv2v_tmp_D756E; - wire [32:1] sv2v_tmp_BAAB3; - assign sv2v_tmp_BAAB3 = {32 {1'sb0}}; - always @(*) rev_result = sv2v_tmp_BAAB3; - wire [32:1] sv2v_tmp_8C42B; - assign sv2v_tmp_8C42B = {32 {1'sb0}}; - always @(*) shuffle_result = sv2v_tmp_8C42B; - wire [32:1] sv2v_tmp_B0AD4; - assign sv2v_tmp_B0AD4 = {32 {1'sb0}}; - always @(*) butterfly_result = sv2v_tmp_B0AD4; - wire [32:1] sv2v_tmp_AFC2C; - assign sv2v_tmp_AFC2C = {32 {1'sb0}}; - always @(*) invbutterfly_result = sv2v_tmp_AFC2C; - wire [32:1] sv2v_tmp_3A741; - assign sv2v_tmp_3A741 = {32 {1'sb0}}; - always @(*) clmul_result = sv2v_tmp_3A741; - wire [32:1] sv2v_tmp_172E8; - assign sv2v_tmp_172E8 = {32 {1'sb0}}; - always @(*) multicycle_result = sv2v_tmp_172E8; - wire [64:1] sv2v_tmp_CAB3F; - assign sv2v_tmp_CAB3F = {2 {32'b00000000000000000000000000000000}}; - always @(*) imd_val_d_o = sv2v_tmp_CAB3F; - wire [2:1] sv2v_tmp_B65CC; - assign sv2v_tmp_B65CC = {2 {1'b0}}; - always @(*) imd_val_we_o = sv2v_tmp_B65CC; - end - endgenerate - localparam [5:0] ibex_pkg_ALU_ADD = 0; - localparam [5:0] ibex_pkg_ALU_CLMUL = 50; - localparam [5:0] ibex_pkg_ALU_GREV = 15; - localparam [5:0] ibex_pkg_ALU_PACK = 29; - localparam [5:0] ibex_pkg_ALU_PCNT = 36; - localparam [5:0] ibex_pkg_ALU_SBEXT = 46; - localparam [5:0] ibex_pkg_ALU_SEXTH = 33; - localparam [5:0] ibex_pkg_ALU_SHFL = 17; - localparam [5:0] ibex_pkg_ALU_SRL = 9; - localparam [5:0] ibex_pkg_ALU_XOR = 2; - always @(*) begin - result_o = {32 {1'sb0}}; - case (operator_i) - ibex_pkg_ALU_XOR, ibex_pkg_ALU_XNOR, ibex_pkg_ALU_OR, ibex_pkg_ALU_ORN, ibex_pkg_ALU_AND, ibex_pkg_ALU_ANDN: result_o = bwlogic_result; - ibex_pkg_ALU_ADD, ibex_pkg_ALU_SUB: result_o = adder_result; - ibex_pkg_ALU_SLL, ibex_pkg_ALU_SRL, ibex_pkg_ALU_SRA, ibex_pkg_ALU_SLO, ibex_pkg_ALU_SRO: result_o = shift_result; - ibex_pkg_ALU_SHFL, ibex_pkg_ALU_UNSHFL: result_o = shuffle_result; - ibex_pkg_ALU_EQ, ibex_pkg_ALU_NE, ibex_pkg_ALU_GE, ibex_pkg_ALU_GEU, ibex_pkg_ALU_LT, ibex_pkg_ALU_LTU, ibex_pkg_ALU_SLT, ibex_pkg_ALU_SLTU: result_o = {31'h00000000, cmp_result}; - ibex_pkg_ALU_MIN, ibex_pkg_ALU_MAX, ibex_pkg_ALU_MINU, ibex_pkg_ALU_MAXU: result_o = minmax_result; - ibex_pkg_ALU_CLZ, ibex_pkg_ALU_CTZ, ibex_pkg_ALU_PCNT: result_o = {26'h0000000, bitcnt_result}; - ibex_pkg_ALU_PACK, ibex_pkg_ALU_PACKH, ibex_pkg_ALU_PACKU: result_o = pack_result; - ibex_pkg_ALU_SEXTB, ibex_pkg_ALU_SEXTH: result_o = sext_result; - ibex_pkg_ALU_CMIX, ibex_pkg_ALU_CMOV, ibex_pkg_ALU_FSL, ibex_pkg_ALU_FSR, ibex_pkg_ALU_ROL, ibex_pkg_ALU_ROR, ibex_pkg_ALU_CRC32_W, ibex_pkg_ALU_CRC32C_W, ibex_pkg_ALU_CRC32_H, ibex_pkg_ALU_CRC32C_H, ibex_pkg_ALU_CRC32_B, ibex_pkg_ALU_CRC32C_B, ibex_pkg_ALU_BEXT, ibex_pkg_ALU_BDEP: result_o = multicycle_result; - ibex_pkg_ALU_SBSET, ibex_pkg_ALU_SBCLR, ibex_pkg_ALU_SBINV, ibex_pkg_ALU_SBEXT: result_o = singlebit_result; - ibex_pkg_ALU_GREV, ibex_pkg_ALU_GORC: result_o = rev_result; - ibex_pkg_ALU_BFP: result_o = bfp_result; - ibex_pkg_ALU_CLMUL, ibex_pkg_ALU_CLMULR, ibex_pkg_ALU_CLMULH: result_o = clmul_result; - default: - ; - endcase - end - wire unused_shift_amt_compl; - assign unused_shift_amt_compl = shift_amt_compl[5]; -endmodule diff --git a/flow/designs/src/ibex/ibex_branch_predict.v b/flow/designs/src/ibex/ibex_branch_predict.v deleted file mode 100644 index 1a54f2e099..0000000000 --- a/flow/designs/src/ibex/ibex_branch_predict.v +++ /dev/null @@ -1,53 +0,0 @@ -module ibex_branch_predict ( - clk_i, - rst_ni, - fetch_rdata_i, - fetch_pc_i, - fetch_valid_i, - predict_branch_taken_o, - predict_branch_pc_o -); - input wire clk_i; - input wire rst_ni; - input wire [31:0] fetch_rdata_i; - input wire [31:0] fetch_pc_i; - input wire fetch_valid_i; - output wire predict_branch_taken_o; - output wire [31:0] predict_branch_pc_o; - wire [31:0] imm_j_type; - wire [31:0] imm_b_type; - wire [31:0] imm_cj_type; - wire [31:0] imm_cb_type; - reg [31:0] branch_imm; - wire [31:0] instr; - wire instr_j; - wire instr_b; - wire instr_cj; - wire instr_cb; - wire instr_b_taken; - assign instr = fetch_rdata_i; - assign imm_j_type = {{12 {instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0}; - assign imm_b_type = {{19 {instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0}; - assign imm_cj_type = {{20 {instr[12]}}, instr[12], instr[8], instr[10:9], instr[6], instr[7], instr[2], instr[11], instr[5:3], 1'b0}; - assign imm_cb_type = {{23 {instr[12]}}, instr[12], instr[6:5], instr[2], instr[11:10], instr[4:3], 1'b0}; - localparam [6:0] ibex_pkg_OPCODE_BRANCH = 7'h63; - assign instr_b = instr[6:0] == ibex_pkg_OPCODE_BRANCH; - localparam [6:0] ibex_pkg_OPCODE_JAL = 7'h6f; - assign instr_j = instr[6:0] == ibex_pkg_OPCODE_JAL; - assign instr_cb = (instr[1:0] == 2'b01) & ((instr[15:13] == 3'b110) | (instr[15:13] == 3'b111)); - assign instr_cj = (instr[1:0] == 2'b01) & ((instr[15:13] == 3'b101) | (instr[15:13] == 3'b001)); - always @(*) begin - branch_imm = imm_b_type; - case (1'b1) - instr_j: branch_imm = imm_j_type; - instr_b: branch_imm = imm_b_type; - instr_cj: branch_imm = imm_cj_type; - instr_cb: branch_imm = imm_cb_type; - default: - ; - endcase - end - assign instr_b_taken = (instr_b & imm_b_type[31]) | (instr_cb & imm_cb_type[31]); - assign predict_branch_taken_o = fetch_valid_i & ((instr_j | instr_cj) | instr_b_taken); - assign predict_branch_pc_o = fetch_pc_i + branch_imm; -endmodule diff --git a/flow/designs/src/ibex/ibex_compressed_decoder.v b/flow/designs/src/ibex/ibex_compressed_decoder.v deleted file mode 100644 index 1321aa0948..0000000000 --- a/flow/designs/src/ibex/ibex_compressed_decoder.v +++ /dev/null @@ -1,115 +0,0 @@ -module ibex_compressed_decoder ( - clk_i, - rst_ni, - valid_i, - instr_i, - instr_o, - is_compressed_o, - illegal_instr_o -); - input wire clk_i; - input wire rst_ni; - input wire valid_i; - input wire [31:0] instr_i; - output reg [31:0] instr_o; - output wire is_compressed_o; - output reg illegal_instr_o; - wire unused_valid; - assign unused_valid = valid_i; - localparam [6:0] ibex_pkg_OPCODE_BRANCH = 7'h63; - localparam [6:0] ibex_pkg_OPCODE_JAL = 7'h6f; - localparam [6:0] ibex_pkg_OPCODE_JALR = 7'h67; - localparam [6:0] ibex_pkg_OPCODE_LOAD = 7'h03; - localparam [6:0] ibex_pkg_OPCODE_LUI = 7'h37; - localparam [6:0] ibex_pkg_OPCODE_OP = 7'h33; - localparam [6:0] ibex_pkg_OPCODE_OP_IMM = 7'h13; - localparam [6:0] ibex_pkg_OPCODE_STORE = 7'h23; - always @(*) begin - instr_o = instr_i; - illegal_instr_o = 1'b0; - case (instr_i[1:0]) - 2'b00: - case (instr_i[15:13]) - 3'b000: begin - instr_o = {2'b00, instr_i[10:7], instr_i[12:11], instr_i[5], instr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], {ibex_pkg_OPCODE_OP_IMM}}; - if (instr_i[12:5] == 8'b00000000) - illegal_instr_o = 1'b1; - end - 3'b010: instr_o = {5'b00000, instr_i[5], instr_i[12:10], instr_i[6], 2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], {ibex_pkg_OPCODE_LOAD}}; - 3'b110: instr_o = {5'b00000, instr_i[5], instr_i[12], 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6], 2'b00, {ibex_pkg_OPCODE_STORE}}; - 3'b001, 3'b011, 3'b100, 3'b101, 3'b111: illegal_instr_o = 1'b1; - default: illegal_instr_o = 1'b1; - endcase - 2'b01: - case (instr_i[15:13]) - 3'b000: instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], instr_i[11:7], 3'b000, instr_i[11:7], {ibex_pkg_OPCODE_OP_IMM}}; - 3'b001, 3'b101: instr_o = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6], instr_i[7], instr_i[2], instr_i[11], instr_i[5:3], {9 {instr_i[12]}}, 4'b0000, ~instr_i[15], {ibex_pkg_OPCODE_JAL}}; - 3'b010: instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b00000, 3'b000, instr_i[11:7], {ibex_pkg_OPCODE_OP_IMM}}; - 3'b011: begin - instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], {ibex_pkg_OPCODE_LUI}}; - if (instr_i[11:7] == 5'h02) - instr_o = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2], instr_i[6], 4'b0000, 5'h02, 3'b000, 5'h02, {ibex_pkg_OPCODE_OP_IMM}}; - if ({instr_i[12], instr_i[6:2]} == 6'b000000) - illegal_instr_o = 1'b1; - end - 3'b100: - case (instr_i[11:10]) - 2'b00, 2'b01: begin - instr_o = {1'b0, instr_i[10], 5'b00000, instr_i[6:2], 2'b01, instr_i[9:7], 3'b101, 2'b01, instr_i[9:7], {ibex_pkg_OPCODE_OP_IMM}}; - if (instr_i[12] == 1'b1) - illegal_instr_o = 1'b1; - end - 2'b10: instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], {ibex_pkg_OPCODE_OP_IMM}}; - 2'b11: - case ({instr_i[12], instr_i[6:5]}) - 3'b000: instr_o = {2'b01, 5'b00000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[9:7], {ibex_pkg_OPCODE_OP}}; - 3'b001: instr_o = {7'b0000000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b100, 2'b01, instr_i[9:7], {ibex_pkg_OPCODE_OP}}; - 3'b010: instr_o = {7'b0000000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b110, 2'b01, instr_i[9:7], {ibex_pkg_OPCODE_OP}}; - 3'b011: instr_o = {7'b0000000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], {ibex_pkg_OPCODE_OP}}; - 3'b100, 3'b101, 3'b110, 3'b111: illegal_instr_o = 1'b1; - default: illegal_instr_o = 1'b1; - endcase - default: illegal_instr_o = 1'b1; - endcase - 3'b110, 3'b111: instr_o = {{4 {instr_i[12]}}, instr_i[6:5], instr_i[2], 5'b00000, 2'b01, instr_i[9:7], 2'b00, instr_i[13], instr_i[11:10], instr_i[4:3], instr_i[12], {ibex_pkg_OPCODE_BRANCH}}; - default: illegal_instr_o = 1'b1; - endcase - 2'b10: - case (instr_i[15:13]) - 3'b000: begin - instr_o = {7'b0000000, instr_i[6:2], instr_i[11:7], 3'b001, instr_i[11:7], {ibex_pkg_OPCODE_OP_IMM}}; - if (instr_i[12] == 1'b1) - illegal_instr_o = 1'b1; - end - 3'b010: begin - instr_o = {4'b0000, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02, 3'b010, instr_i[11:7], ibex_pkg_OPCODE_LOAD}; - if (instr_i[11:7] == 5'b00000) - illegal_instr_o = 1'b1; - end - 3'b100: - if (instr_i[12] == 1'b0) begin - if (instr_i[6:2] != 5'b00000) - instr_o = {7'b0000000, instr_i[6:2], 5'b00000, 3'b000, instr_i[11:7], {ibex_pkg_OPCODE_OP}}; - else begin - instr_o = {12'b000000000000, instr_i[11:7], 3'b000, 5'b00000, {ibex_pkg_OPCODE_JALR}}; - if (instr_i[11:7] == 5'b00000) - illegal_instr_o = 1'b1; - end - end - else if (instr_i[6:2] != 5'b00000) - instr_o = {7'b0000000, instr_i[6:2], instr_i[11:7], 3'b000, instr_i[11:7], {ibex_pkg_OPCODE_OP}}; - else if (instr_i[11:7] == 5'b00000) - instr_o = 32'h00100073; - else - instr_o = {12'b000000000000, instr_i[11:7], 3'b000, 5'b00001, {ibex_pkg_OPCODE_JALR}}; - 3'b110: instr_o = {4'b0000, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010, instr_i[11:9], 2'b00, {ibex_pkg_OPCODE_STORE}}; - 3'b001, 3'b011, 3'b101, 3'b111: illegal_instr_o = 1'b1; - default: illegal_instr_o = 1'b1; - endcase - 2'b11: - ; - default: illegal_instr_o = 1'b1; - endcase - end - assign is_compressed_o = instr_i[1:0] != 2'b11; -endmodule diff --git a/flow/designs/src/ibex/ibex_controller.v b/flow/designs/src/ibex/ibex_controller.v deleted file mode 100644 index 6b4388e039..0000000000 --- a/flow/designs/src/ibex/ibex_controller.v +++ /dev/null @@ -1,579 +0,0 @@ -module ibex_controller ( - clk_i, - rst_ni, - ctrl_busy_o, - illegal_insn_i, - ecall_insn_i, - mret_insn_i, - dret_insn_i, - wfi_insn_i, - ebrk_insn_i, - csr_pipe_flush_i, - instr_valid_i, - instr_i, - instr_compressed_i, - instr_is_compressed_i, - instr_bp_taken_i, - instr_fetch_err_i, - instr_fetch_err_plus2_i, - pc_id_i, - instr_valid_clear_o, - id_in_ready_o, - controller_run_o, - instr_req_o, - pc_set_o, - pc_set_spec_o, - pc_mux_o, - nt_branch_mispredict_o, - exc_pc_mux_o, - exc_cause_o, - lsu_addr_last_i, - load_err_i, - store_err_i, - wb_exception_o, - branch_set_i, - branch_set_spec_i, - branch_not_set_i, - jump_set_i, - csr_mstatus_mie_i, - irq_pending_i, - irqs_i, - irq_nm_i, - nmi_mode_o, - debug_req_i, - debug_cause_o, - debug_csr_save_o, - debug_mode_o, - debug_single_step_i, - debug_ebreakm_i, - debug_ebreaku_i, - trigger_match_i, - csr_save_if_o, - csr_save_id_o, - csr_save_wb_o, - csr_restore_mret_id_o, - csr_restore_dret_id_o, - csr_save_cause_o, - csr_mtval_o, - priv_mode_i, - csr_mstatus_tw_i, - stall_id_i, - stall_wb_i, - flush_id_o, - ready_wb_i, - perf_jump_o, - perf_tbranch_o -); - parameter [0:0] WritebackStage = 0; - parameter [0:0] BranchPredictor = 0; - input wire clk_i; - input wire rst_ni; - output reg ctrl_busy_o; - input wire illegal_insn_i; - input wire ecall_insn_i; - input wire mret_insn_i; - input wire dret_insn_i; - input wire wfi_insn_i; - input wire ebrk_insn_i; - input wire csr_pipe_flush_i; - input wire instr_valid_i; - input wire [31:0] instr_i; - input wire [15:0] instr_compressed_i; - input wire instr_is_compressed_i; - input wire instr_bp_taken_i; - input wire instr_fetch_err_i; - input wire instr_fetch_err_plus2_i; - input wire [31:0] pc_id_i; - output wire instr_valid_clear_o; - output wire id_in_ready_o; - output reg controller_run_o; - output reg instr_req_o; - output reg pc_set_o; - output reg pc_set_spec_o; - output reg [2:0] pc_mux_o; - output reg nt_branch_mispredict_o; - output reg [1:0] exc_pc_mux_o; - output reg [5:0] exc_cause_o; - input wire [31:0] lsu_addr_last_i; - input wire load_err_i; - input wire store_err_i; - output wire wb_exception_o; - input wire branch_set_i; - input wire branch_set_spec_i; - input wire branch_not_set_i; - input wire jump_set_i; - input wire csr_mstatus_mie_i; - input wire irq_pending_i; - input wire [17:0] irqs_i; - input wire irq_nm_i; - output wire nmi_mode_o; - input wire debug_req_i; - output reg [2:0] debug_cause_o; - output reg debug_csr_save_o; - output wire debug_mode_o; - input wire debug_single_step_i; - input wire debug_ebreakm_i; - input wire debug_ebreaku_i; - input wire trigger_match_i; - output reg csr_save_if_o; - output reg csr_save_id_o; - output reg csr_save_wb_o; - output reg csr_restore_mret_id_o; - output reg csr_restore_dret_id_o; - output reg csr_save_cause_o; - output reg [31:0] csr_mtval_o; - input wire [1:0] priv_mode_i; - input wire csr_mstatus_tw_i; - input wire stall_id_i; - input wire stall_wb_i; - output wire flush_id_o; - input wire ready_wb_i; - output reg perf_jump_o; - output reg perf_tbranch_o; - reg [3:0] ctrl_fsm_cs; - reg [3:0] ctrl_fsm_ns; - reg nmi_mode_q; - reg nmi_mode_d; - reg debug_mode_q; - reg debug_mode_d; - reg load_err_q; - wire load_err_d; - reg store_err_q; - wire store_err_d; - reg exc_req_q; - wire exc_req_d; - reg illegal_insn_q; - wire illegal_insn_d; - reg instr_fetch_err_prio; - reg illegal_insn_prio; - reg ecall_insn_prio; - reg ebrk_insn_prio; - reg store_err_prio; - reg load_err_prio; - wire stall; - reg halt_if; - reg retain_id; - reg flush_id; - wire illegal_dret; - wire illegal_umode; - wire exc_req_lsu; - wire special_req_all; - wire special_req_branch; - wire enter_debug_mode; - wire ebreak_into_debug; - wire handle_irq; - reg [3:0] mfip_id; - wire unused_irq_timer; - wire ecall_insn; - wire mret_insn; - wire dret_insn; - wire wfi_insn; - wire ebrk_insn; - wire csr_pipe_flush; - wire instr_fetch_err; - assign load_err_d = load_err_i; - assign store_err_d = store_err_i; - assign ecall_insn = ecall_insn_i & instr_valid_i; - assign mret_insn = mret_insn_i & instr_valid_i; - assign dret_insn = dret_insn_i & instr_valid_i; - assign wfi_insn = wfi_insn_i & instr_valid_i; - assign ebrk_insn = ebrk_insn_i & instr_valid_i; - assign csr_pipe_flush = csr_pipe_flush_i & instr_valid_i; - assign instr_fetch_err = instr_fetch_err_i & instr_valid_i; - assign illegal_dret = dret_insn & ~debug_mode_q; - localparam [1:0] ibex_pkg_PRIV_LVL_M = 2'b11; - assign illegal_umode = (priv_mode_i != ibex_pkg_PRIV_LVL_M) & (mret_insn | (csr_mstatus_tw_i & wfi_insn)); - localparam [3:0] FLUSH = 6; - assign illegal_insn_d = ((illegal_insn_i | illegal_dret) | illegal_umode) & (ctrl_fsm_cs != FLUSH); - assign exc_req_d = (((ecall_insn | ebrk_insn) | illegal_insn_d) | instr_fetch_err) & (ctrl_fsm_cs != FLUSH); - assign exc_req_lsu = store_err_i | load_err_i; - assign special_req_all = ((((mret_insn | dret_insn) | wfi_insn) | csr_pipe_flush) | exc_req_d) | exc_req_lsu; - assign special_req_branch = instr_fetch_err & (ctrl_fsm_cs != FLUSH); - generate - if (WritebackStage) begin : g_wb_exceptions - always @(*) begin - instr_fetch_err_prio = 0; - illegal_insn_prio = 0; - ecall_insn_prio = 0; - ebrk_insn_prio = 0; - store_err_prio = 0; - load_err_prio = 0; - if (store_err_q) - store_err_prio = 1'b1; - else if (load_err_q) - load_err_prio = 1'b1; - else if (instr_fetch_err) - instr_fetch_err_prio = 1'b1; - else if (illegal_insn_q) - illegal_insn_prio = 1'b1; - else if (ecall_insn) - ecall_insn_prio = 1'b1; - else if (ebrk_insn) - ebrk_insn_prio = 1'b1; - end - assign wb_exception_o = ((load_err_q | store_err_q) | load_err_i) | store_err_i; - end - else begin : g_no_wb_exceptions - always @(*) begin - instr_fetch_err_prio = 0; - illegal_insn_prio = 0; - ecall_insn_prio = 0; - ebrk_insn_prio = 0; - store_err_prio = 0; - load_err_prio = 0; - if (instr_fetch_err) - instr_fetch_err_prio = 1'b1; - else if (illegal_insn_q) - illegal_insn_prio = 1'b1; - else if (ecall_insn) - ecall_insn_prio = 1'b1; - else if (ebrk_insn) - ebrk_insn_prio = 1'b1; - else if (store_err_q) - store_err_prio = 1'b1; - else if (load_err_q) - load_err_prio = 1'b1; - end - assign wb_exception_o = 1'b0; - end - endgenerate - assign enter_debug_mode = ((debug_req_i | (debug_single_step_i & instr_valid_i)) | trigger_match_i) & ~debug_mode_q; - localparam [1:0] ibex_pkg_PRIV_LVL_U = 2'b00; - assign ebreak_into_debug = (priv_mode_i == ibex_pkg_PRIV_LVL_M ? debug_ebreakm_i : (priv_mode_i == ibex_pkg_PRIV_LVL_U ? debug_ebreaku_i : 1'b0)); - assign handle_irq = (~debug_mode_q & ~nmi_mode_q) & (irq_nm_i | (irq_pending_i & csr_mstatus_mie_i)); - always @(*) begin : gen_mfip_id - if (irqs_i[14]) - mfip_id = 4'd14; - else if (irqs_i[13]) - mfip_id = 4'd13; - else if (irqs_i[12]) - mfip_id = 4'd12; - else if (irqs_i[11]) - mfip_id = 4'd11; - else if (irqs_i[10]) - mfip_id = 4'd10; - else if (irqs_i[9]) - mfip_id = 4'd9; - else if (irqs_i[8]) - mfip_id = 4'd8; - else if (irqs_i[7]) - mfip_id = 4'd7; - else if (irqs_i[6]) - mfip_id = 4'd6; - else if (irqs_i[5]) - mfip_id = 4'd5; - else if (irqs_i[4]) - mfip_id = 4'd4; - else if (irqs_i[3]) - mfip_id = 4'd3; - else if (irqs_i[2]) - mfip_id = 4'd2; - else if (irqs_i[1]) - mfip_id = 4'd1; - else - mfip_id = 4'd0; - end - assign unused_irq_timer = irqs_i[16]; - localparam [3:0] BOOT_SET = 1; - localparam [3:0] DBG_TAKEN_ID = 9; - localparam [3:0] DBG_TAKEN_IF = 8; - localparam [3:0] DECODE = 5; - localparam [3:0] FIRST_FETCH = 4; - localparam [3:0] IRQ_TAKEN = 7; - localparam [3:0] RESET = 0; - localparam [3:0] SLEEP = 3; - localparam [3:0] WAIT_SLEEP = 2; - localparam [2:0] ibex_pkg_DBG_CAUSE_EBREAK = 3'h1; - localparam [2:0] ibex_pkg_DBG_CAUSE_HALTREQ = 3'h3; - localparam [2:0] ibex_pkg_DBG_CAUSE_STEP = 3'h4; - localparam [2:0] ibex_pkg_DBG_CAUSE_TRIGGER = 3'h2; - localparam [5:0] ibex_pkg_EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3}; - localparam [5:0] ibex_pkg_EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}; - localparam [5:0] ibex_pkg_EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8}; - localparam [5:0] ibex_pkg_EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2}; - localparam [5:0] ibex_pkg_EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0}; - localparam [5:0] ibex_pkg_EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1}; - localparam [5:0] ibex_pkg_EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}; - localparam [5:0] ibex_pkg_EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}; - localparam [5:0] ibex_pkg_EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3}; - localparam [5:0] ibex_pkg_EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7}; - localparam [5:0] ibex_pkg_EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5}; - localparam [5:0] ibex_pkg_EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7}; - localparam [1:0] ibex_pkg_EXC_PC_DBD = 2; - localparam [1:0] ibex_pkg_EXC_PC_DBG_EXC = 3; - localparam [1:0] ibex_pkg_EXC_PC_EXC = 0; - localparam [1:0] ibex_pkg_EXC_PC_IRQ = 1; - localparam [2:0] ibex_pkg_PC_BOOT = 0; - localparam [2:0] ibex_pkg_PC_DRET = 4; - localparam [2:0] ibex_pkg_PC_ERET = 3; - localparam [2:0] ibex_pkg_PC_EXC = 2; - localparam [2:0] ibex_pkg_PC_JUMP = 1; - function automatic [5:0] sv2v_cast_6; - input reg [5:0] inp; - sv2v_cast_6 = inp; - endfunction - always @(*) begin - instr_req_o = 1'b1; - csr_save_if_o = 1'b0; - csr_save_id_o = 1'b0; - csr_save_wb_o = 1'b0; - csr_restore_mret_id_o = 1'b0; - csr_restore_dret_id_o = 1'b0; - csr_save_cause_o = 1'b0; - csr_mtval_o = {32 {1'sb0}}; - pc_mux_o = ibex_pkg_PC_BOOT; - pc_set_o = 1'b0; - pc_set_spec_o = 1'b0; - nt_branch_mispredict_o = 1'b0; - exc_pc_mux_o = ibex_pkg_EXC_PC_IRQ; - exc_cause_o = ibex_pkg_EXC_CAUSE_INSN_ADDR_MISA; - ctrl_fsm_ns = ctrl_fsm_cs; - ctrl_busy_o = 1'b1; - halt_if = 1'b0; - retain_id = 1'b0; - flush_id = 1'b0; - debug_csr_save_o = 1'b0; - debug_cause_o = ibex_pkg_DBG_CAUSE_EBREAK; - debug_mode_d = debug_mode_q; - nmi_mode_d = nmi_mode_q; - perf_tbranch_o = 1'b0; - perf_jump_o = 1'b0; - controller_run_o = 1'b0; - case (ctrl_fsm_cs) - RESET: begin - instr_req_o = 1'b0; - pc_mux_o = ibex_pkg_PC_BOOT; - pc_set_o = 1'b1; - pc_set_spec_o = 1'b1; - ctrl_fsm_ns = BOOT_SET; - end - BOOT_SET: begin - instr_req_o = 1'b1; - pc_mux_o = ibex_pkg_PC_BOOT; - pc_set_o = 1'b1; - pc_set_spec_o = 1'b1; - ctrl_fsm_ns = FIRST_FETCH; - end - WAIT_SLEEP: begin - ctrl_busy_o = 1'b0; - instr_req_o = 1'b0; - halt_if = 1'b1; - flush_id = 1'b1; - ctrl_fsm_ns = SLEEP; - end - SLEEP: begin - instr_req_o = 1'b0; - halt_if = 1'b1; - flush_id = 1'b1; - if ((((irq_nm_i || irq_pending_i) || debug_req_i) || debug_mode_q) || debug_single_step_i) - ctrl_fsm_ns = FIRST_FETCH; - else - ctrl_busy_o = 1'b0; - end - FIRST_FETCH: begin - if (id_in_ready_o) - ctrl_fsm_ns = DECODE; - if (handle_irq) begin - ctrl_fsm_ns = IRQ_TAKEN; - halt_if = 1'b1; - end - if (enter_debug_mode) begin - ctrl_fsm_ns = DBG_TAKEN_IF; - halt_if = 1'b1; - end - end - DECODE: begin - controller_run_o = 1'b1; - pc_mux_o = ibex_pkg_PC_JUMP; - if (special_req_all) begin - retain_id = 1'b1; - if (ready_wb_i | wb_exception_o) - ctrl_fsm_ns = FLUSH; - end - if (!special_req_branch) begin - if (branch_set_i || jump_set_i) begin - pc_set_o = (BranchPredictor ? ~instr_bp_taken_i : 1'b1); - perf_tbranch_o = branch_set_i; - perf_jump_o = jump_set_i; - end - if (BranchPredictor) - if (instr_bp_taken_i & branch_not_set_i) - nt_branch_mispredict_o = 1'b1; - end - if ((branch_set_spec_i || jump_set_i) && !special_req_branch) - pc_set_spec_o = (BranchPredictor ? ~instr_bp_taken_i : 1'b1); - if ((enter_debug_mode || handle_irq) && stall) - halt_if = 1'b1; - if (!stall && !special_req_all) - if (enter_debug_mode) begin - ctrl_fsm_ns = DBG_TAKEN_IF; - halt_if = 1'b1; - end - else if (handle_irq) begin - ctrl_fsm_ns = IRQ_TAKEN; - halt_if = 1'b1; - end - end - IRQ_TAKEN: begin - pc_mux_o = ibex_pkg_PC_EXC; - exc_pc_mux_o = ibex_pkg_EXC_PC_IRQ; - if (handle_irq) begin - pc_set_o = 1'b1; - pc_set_spec_o = 1'b1; - csr_save_if_o = 1'b1; - csr_save_cause_o = 1'b1; - if (irq_nm_i && !nmi_mode_q) begin - exc_cause_o = ibex_pkg_EXC_CAUSE_IRQ_NM; - nmi_mode_d = 1'b1; - end - else if (irqs_i[14-:15] != 15'b000000000000000) - exc_cause_o = sv2v_cast_6({2'b11, mfip_id}); - else if (irqs_i[15]) - exc_cause_o = ibex_pkg_EXC_CAUSE_IRQ_EXTERNAL_M; - else if (irqs_i[17]) - exc_cause_o = ibex_pkg_EXC_CAUSE_IRQ_SOFTWARE_M; - else - exc_cause_o = ibex_pkg_EXC_CAUSE_IRQ_TIMER_M; - end - ctrl_fsm_ns = DECODE; - end - DBG_TAKEN_IF: begin - pc_mux_o = ibex_pkg_PC_EXC; - exc_pc_mux_o = ibex_pkg_EXC_PC_DBD; - if ((debug_single_step_i || debug_req_i) || trigger_match_i) begin - flush_id = 1'b1; - pc_set_o = 1'b1; - pc_set_spec_o = 1'b1; - csr_save_if_o = 1'b1; - debug_csr_save_o = 1'b1; - csr_save_cause_o = 1'b1; - if (trigger_match_i) - debug_cause_o = ibex_pkg_DBG_CAUSE_TRIGGER; - else if (debug_single_step_i) - debug_cause_o = ibex_pkg_DBG_CAUSE_STEP; - else - debug_cause_o = ibex_pkg_DBG_CAUSE_HALTREQ; - debug_mode_d = 1'b1; - end - ctrl_fsm_ns = DECODE; - end - DBG_TAKEN_ID: begin - flush_id = 1'b1; - pc_mux_o = ibex_pkg_PC_EXC; - pc_set_o = 1'b1; - pc_set_spec_o = 1'b1; - exc_pc_mux_o = ibex_pkg_EXC_PC_DBD; - if (ebreak_into_debug && !debug_mode_q) begin - csr_save_cause_o = 1'b1; - csr_save_id_o = 1'b1; - debug_csr_save_o = 1'b1; - debug_cause_o = ibex_pkg_DBG_CAUSE_EBREAK; - end - debug_mode_d = 1'b1; - ctrl_fsm_ns = DECODE; - end - FLUSH: begin - halt_if = 1'b1; - flush_id = 1'b1; - ctrl_fsm_ns = DECODE; - if ((exc_req_q || store_err_q) || load_err_q) begin - pc_set_o = 1'b1; - pc_set_spec_o = 1'b1; - pc_mux_o = ibex_pkg_PC_EXC; - exc_pc_mux_o = (debug_mode_q ? ibex_pkg_EXC_PC_DBG_EXC : ibex_pkg_EXC_PC_EXC); - if (WritebackStage) begin : g_writeback_mepc_save - csr_save_id_o = ~(store_err_q | load_err_q); - csr_save_wb_o = store_err_q | load_err_q; - end - else begin : g_no_writeback_mepc_save - csr_save_id_o = 1'b0; - end - csr_save_cause_o = 1'b1; - case (1'b1) - instr_fetch_err_prio: begin - exc_cause_o = ibex_pkg_EXC_CAUSE_INSTR_ACCESS_FAULT; - csr_mtval_o = (instr_fetch_err_plus2_i ? pc_id_i + 32'd2 : pc_id_i); - end - illegal_insn_prio: begin - exc_cause_o = ibex_pkg_EXC_CAUSE_ILLEGAL_INSN; - csr_mtval_o = (instr_is_compressed_i ? {16'b0000000000000000, instr_compressed_i} : instr_i); - end - ecall_insn_prio: exc_cause_o = (priv_mode_i == ibex_pkg_PRIV_LVL_M ? ibex_pkg_EXC_CAUSE_ECALL_MMODE : ibex_pkg_EXC_CAUSE_ECALL_UMODE); - ebrk_insn_prio: - if (debug_mode_q | ebreak_into_debug) begin - pc_set_o = 1'b0; - pc_set_spec_o = 1'b0; - csr_save_id_o = 1'b0; - csr_save_cause_o = 1'b0; - ctrl_fsm_ns = DBG_TAKEN_ID; - flush_id = 1'b0; - end - else - exc_cause_o = ibex_pkg_EXC_CAUSE_BREAKPOINT; - store_err_prio: begin - exc_cause_o = ibex_pkg_EXC_CAUSE_STORE_ACCESS_FAULT; - csr_mtval_o = lsu_addr_last_i; - end - load_err_prio: begin - exc_cause_o = ibex_pkg_EXC_CAUSE_LOAD_ACCESS_FAULT; - csr_mtval_o = lsu_addr_last_i; - end - default: - ; - endcase - end - else if (mret_insn) begin - pc_mux_o = ibex_pkg_PC_ERET; - pc_set_o = 1'b1; - pc_set_spec_o = 1'b1; - csr_restore_mret_id_o = 1'b1; - if (nmi_mode_q) - nmi_mode_d = 1'b0; - end - else if (dret_insn) begin - pc_mux_o = ibex_pkg_PC_DRET; - pc_set_o = 1'b1; - pc_set_spec_o = 1'b1; - debug_mode_d = 1'b0; - csr_restore_dret_id_o = 1'b1; - end - else if (wfi_insn) - ctrl_fsm_ns = WAIT_SLEEP; - else if (csr_pipe_flush && handle_irq) - ctrl_fsm_ns = IRQ_TAKEN; - if (enter_debug_mode && !(ebrk_insn_prio && ebreak_into_debug)) - ctrl_fsm_ns = DBG_TAKEN_IF; - end - default: begin - instr_req_o = 1'b0; - ctrl_fsm_ns = RESET; - end - endcase - end - assign flush_id_o = flush_id; - assign debug_mode_o = debug_mode_q; - assign nmi_mode_o = nmi_mode_q; - assign stall = stall_id_i | stall_wb_i; - assign id_in_ready_o = (~stall & ~halt_if) & ~retain_id; - assign instr_valid_clear_o = ~(stall | retain_id) | flush_id; - always @(posedge clk_i or negedge rst_ni) begin : update_regs - if (!rst_ni) begin - ctrl_fsm_cs <= RESET; - nmi_mode_q <= 1'b0; - debug_mode_q <= 1'b0; - load_err_q <= 1'b0; - store_err_q <= 1'b0; - exc_req_q <= 1'b0; - illegal_insn_q <= 1'b0; - end - else begin - ctrl_fsm_cs <= ctrl_fsm_ns; - nmi_mode_q <= nmi_mode_d; - debug_mode_q <= debug_mode_d; - load_err_q <= load_err_d; - store_err_q <= store_err_d; - exc_req_q <= exc_req_d; - illegal_insn_q <= illegal_insn_d; - end - end -endmodule diff --git a/flow/designs/src/ibex/ibex_core.v b/flow/designs/src/ibex/ibex_core.v deleted file mode 100644 index 79d926cca0..0000000000 --- a/flow/designs/src/ibex/ibex_core.v +++ /dev/null @@ -1,782 +0,0 @@ -module ibex_core ( - clk_i, - rst_ni, - test_en_i, - hart_id_i, - boot_addr_i, - instr_req_o, - instr_gnt_i, - instr_rvalid_i, - instr_addr_o, - instr_rdata_i, - instr_err_i, - data_req_o, - data_gnt_i, - data_rvalid_i, - data_we_o, - data_be_o, - data_addr_o, - data_wdata_o, - data_rdata_i, - data_err_i, - irq_software_i, - irq_timer_i, - irq_external_i, - irq_fast_i, - irq_nm_i, - debug_req_i, - fetch_enable_i, - alert_minor_o, - alert_major_o, - core_sleep_o -); - parameter [0:0] PMPEnable = 1'b0; - parameter [31:0] PMPGranularity = 0; - parameter [31:0] PMPNumRegions = 4; - parameter [31:0] MHPMCounterNum = 0; - parameter [31:0] MHPMCounterWidth = 40; - parameter [0:0] RV32E = 1'b0; - localparam integer ibex_pkg_RV32MFast = 2; - parameter integer RV32M = ibex_pkg_RV32MFast; - localparam integer ibex_pkg_RV32BNone = 0; - parameter integer RV32B = ibex_pkg_RV32BNone; - localparam integer ibex_pkg_RegFileFF = 0; - parameter integer RegFile = ibex_pkg_RegFileFF; - parameter [0:0] BranchTargetALU = 1'b0; - parameter [0:0] WritebackStage = 1'b0; - parameter [0:0] ICache = 1'b0; - parameter [0:0] ICacheECC = 1'b0; - parameter [0:0] BranchPredictor = 1'b0; - parameter [0:0] DbgTriggerEn = 1'b0; - parameter [31:0] DbgHwBreakNum = 1; - parameter [0:0] SecureIbex = 1'b0; - parameter [31:0] DmHaltAddr = 32'h1a110800; - parameter [31:0] DmExceptionAddr = 32'h1a110808; - input wire clk_i; - input wire rst_ni; - input wire test_en_i; - input wire [31:0] hart_id_i; - input wire [31:0] boot_addr_i; - output wire instr_req_o; - input wire instr_gnt_i; - input wire instr_rvalid_i; - output wire [31:0] instr_addr_o; - input wire [31:0] instr_rdata_i; - input wire instr_err_i; - output wire data_req_o; - input wire data_gnt_i; - input wire data_rvalid_i; - output wire data_we_o; - output wire [3:0] data_be_o; - output wire [31:0] data_addr_o; - output wire [31:0] data_wdata_o; - input wire [31:0] data_rdata_i; - input wire data_err_i; - input wire irq_software_i; - input wire irq_timer_i; - input wire irq_external_i; - input wire [14:0] irq_fast_i; - input wire irq_nm_i; - input wire debug_req_i; - input wire fetch_enable_i; - output wire alert_minor_o; - output wire alert_major_o; - output wire core_sleep_o; - localparam [31:0] PMP_NUM_CHAN = 2; - localparam [0:0] DataIndTiming = SecureIbex; - localparam [0:0] DummyInstructions = SecureIbex; - localparam [0:0] PCIncrCheck = SecureIbex; - localparam [0:0] ShadowCSR = SecureIbex; - localparam [0:0] SpecBranch = PMPEnable & (PMPNumRegions == 16); - localparam [0:0] RegFileECC = SecureIbex; - localparam [31:0] RegFileDataWidth = (RegFileECC ? 39 : 32); - wire dummy_instr_id; - wire instr_valid_id; - wire instr_new_id; - wire [31:0] instr_rdata_id; - wire [31:0] instr_rdata_alu_id; - wire [15:0] instr_rdata_c_id; - wire instr_is_compressed_id; - wire instr_perf_count_id; - wire instr_bp_taken_id; - wire instr_fetch_err; - wire instr_fetch_err_plus2; - wire illegal_c_insn_id; - wire [31:0] pc_if; - wire [31:0] pc_id; - wire [31:0] pc_wb; - wire [67:0] imd_val_d_ex; - wire [67:0] imd_val_q_ex; - wire [1:0] imd_val_we_ex; - wire data_ind_timing; - wire dummy_instr_en; - wire [2:0] dummy_instr_mask; - wire dummy_instr_seed_en; - wire [31:0] dummy_instr_seed; - wire icache_enable; - wire icache_inval; - wire pc_mismatch_alert; - wire csr_shadow_err; - wire instr_first_cycle_id; - wire instr_valid_clear; - wire pc_set; - wire pc_set_spec; - wire nt_branch_mispredict; - wire [2:0] pc_mux_id; - wire [1:0] exc_pc_mux_id; - wire [5:0] exc_cause; - wire lsu_load_err; - wire lsu_store_err; - wire lsu_addr_incr_req; - wire [31:0] lsu_addr_last; - wire [31:0] branch_target_ex; - wire branch_decision; - wire ctrl_busy; - wire if_busy; - wire lsu_busy; - wire core_busy_d; - reg core_busy_q; - wire [4:0] rf_raddr_a; - wire [31:0] rf_rdata_a; - wire [4:0] rf_raddr_b; - wire [31:0] rf_rdata_b; - wire rf_ren_a; - wire rf_ren_b; - wire [4:0] rf_waddr_wb; - wire [31:0] rf_wdata_wb; - wire [31:0] rf_wdata_fwd_wb; - wire [31:0] rf_wdata_lsu; - wire rf_we_wb; - wire rf_we_lsu; - wire [4:0] rf_waddr_id; - wire [31:0] rf_wdata_id; - wire rf_we_id; - wire rf_rd_a_wb_match; - wire rf_rd_b_wb_match; - wire [5:0] alu_operator_ex; - wire [31:0] alu_operand_a_ex; - wire [31:0] alu_operand_b_ex; - wire [31:0] bt_a_operand; - wire [31:0] bt_b_operand; - wire [31:0] alu_adder_result_ex; - wire [31:0] result_ex; - wire mult_en_ex; - wire div_en_ex; - wire mult_sel_ex; - wire div_sel_ex; - wire [1:0] multdiv_operator_ex; - wire [1:0] multdiv_signed_mode_ex; - wire [31:0] multdiv_operand_a_ex; - wire [31:0] multdiv_operand_b_ex; - wire multdiv_ready_id; - wire csr_access; - wire [1:0] csr_op; - wire csr_op_en; - wire [11:0] csr_addr; - wire [31:0] csr_rdata; - wire [31:0] csr_wdata; - wire illegal_csr_insn_id; - wire lsu_we; - wire [1:0] lsu_type; - wire lsu_sign_ext; - wire lsu_req; - wire [31:0] lsu_wdata; - wire lsu_req_done; - wire id_in_ready; - wire ex_valid; - wire lsu_resp_valid; - wire lsu_resp_err; - wire instr_req_int; - wire en_wb; - wire [1:0] instr_type_wb; - wire ready_wb; - wire rf_write_wb; - wire outstanding_load_wb; - wire outstanding_store_wb; - wire irq_pending; - wire nmi_mode; - wire [17:0] irqs; - wire csr_mstatus_mie; - wire [31:0] csr_mepc; - wire [31:0] csr_depc; - wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 34) + (((PMPNumRegions - 1) * 34) - 1) : (PMPNumRegions * 34) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 34 : 0)] csr_pmp_addr; - wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 6) + (((PMPNumRegions - 1) * 6) - 1) : (PMPNumRegions * 6) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 6 : 0)] csr_pmp_cfg; - wire [0:PMP_NUM_CHAN - 1] pmp_req_err; - wire instr_req_out; - wire data_req_out; - wire csr_save_if; - wire csr_save_id; - wire csr_save_wb; - wire csr_restore_mret_id; - wire csr_restore_dret_id; - wire csr_save_cause; - wire csr_mtvec_init; - wire [31:0] csr_mtvec; - wire [31:0] csr_mtval; - wire csr_mstatus_tw; - wire [1:0] priv_mode_id; - wire [1:0] priv_mode_if; - wire [1:0] priv_mode_lsu; - wire debug_mode; - wire [2:0] debug_cause; - wire debug_csr_save; - wire debug_single_step; - wire debug_ebreakm; - wire debug_ebreaku; - wire trigger_match; - wire instr_id_done; - wire instr_done_wb; - wire perf_instr_ret_wb; - wire perf_instr_ret_compressed_wb; - wire perf_iside_wait; - wire perf_dside_wait; - wire perf_mul_wait; - wire perf_div_wait; - wire perf_jump; - wire perf_branch; - wire perf_tbranch; - wire perf_load; - wire perf_store; - wire illegal_insn_id; - wire unused_illegal_insn_id; - wire clk; - wire clock_en; - assign core_busy_d = (ctrl_busy | if_busy) | lsu_busy; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - core_busy_q <= 1'b0; - else - core_busy_q <= core_busy_d; - reg fetch_enable_q; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - fetch_enable_q <= 1'b0; - else if (fetch_enable_i) - fetch_enable_q <= 1'b1; - assign clock_en = fetch_enable_q & (((core_busy_q | debug_req_i) | irq_pending) | irq_nm_i); - assign core_sleep_o = ~clock_en; - prim_clock_gating core_clock_gate_i( - .clk_i(clk_i), - .en_i(clock_en), - .test_en_i(test_en_i), - .clk_o(clk) - ); - localparam [31:0] ibex_pkg_PMP_I = 0; - ibex_if_stage #( - .DmHaltAddr(DmHaltAddr), - .DmExceptionAddr(DmExceptionAddr), - .DummyInstructions(DummyInstructions), - .ICache(ICache), - .ICacheECC(ICacheECC), - .PCIncrCheck(PCIncrCheck), - .BranchPredictor(BranchPredictor) - ) if_stage_i( - .clk_i(clk), - .rst_ni(rst_ni), - .boot_addr_i(boot_addr_i), - .req_i(instr_req_int), - .instr_req_o(instr_req_out), - .instr_addr_o(instr_addr_o), - .instr_gnt_i(instr_gnt_i), - .instr_rvalid_i(instr_rvalid_i), - .instr_rdata_i(instr_rdata_i), - .instr_err_i(instr_err_i), - .instr_pmp_err_i(pmp_req_err[ibex_pkg_PMP_I]), - .instr_valid_id_o(instr_valid_id), - .instr_new_id_o(instr_new_id), - .instr_rdata_id_o(instr_rdata_id), - .instr_rdata_alu_id_o(instr_rdata_alu_id), - .instr_rdata_c_id_o(instr_rdata_c_id), - .instr_is_compressed_id_o(instr_is_compressed_id), - .instr_bp_taken_o(instr_bp_taken_id), - .instr_fetch_err_o(instr_fetch_err), - .instr_fetch_err_plus2_o(instr_fetch_err_plus2), - .illegal_c_insn_id_o(illegal_c_insn_id), - .dummy_instr_id_o(dummy_instr_id), - .pc_if_o(pc_if), - .pc_id_o(pc_id), - .instr_valid_clear_i(instr_valid_clear), - .pc_set_i(pc_set), - .pc_set_spec_i(pc_set_spec), - .pc_mux_i(pc_mux_id), - .nt_branch_mispredict_i(nt_branch_mispredict), - .exc_pc_mux_i(exc_pc_mux_id), - .exc_cause(exc_cause), - .dummy_instr_en_i(dummy_instr_en), - .dummy_instr_mask_i(dummy_instr_mask), - .dummy_instr_seed_en_i(dummy_instr_seed_en), - .dummy_instr_seed_i(dummy_instr_seed), - .icache_enable_i(icache_enable), - .icache_inval_i(icache_inval), - .branch_target_ex_i(branch_target_ex), - .csr_mepc_i(csr_mepc), - .csr_depc_i(csr_depc), - .csr_mtvec_i(csr_mtvec), - .csr_mtvec_init_o(csr_mtvec_init), - .id_in_ready_i(id_in_ready), - .pc_mismatch_alert_o(pc_mismatch_alert), - .if_busy_o(if_busy) - ); - assign perf_iside_wait = id_in_ready & ~instr_valid_id; - assign instr_req_o = instr_req_out & ~pmp_req_err[ibex_pkg_PMP_I]; - ibex_id_stage #( - .RV32E(RV32E), - .RV32M(RV32M), - .RV32B(RV32B), - .BranchTargetALU(BranchTargetALU), - .DataIndTiming(DataIndTiming), - .SpecBranch(SpecBranch), - .WritebackStage(WritebackStage), - .BranchPredictor(BranchPredictor) - ) id_stage_i( - .clk_i(clk), - .rst_ni(rst_ni), - .ctrl_busy_o(ctrl_busy), - .illegal_insn_o(illegal_insn_id), - .instr_valid_i(instr_valid_id), - .instr_rdata_i(instr_rdata_id), - .instr_rdata_alu_i(instr_rdata_alu_id), - .instr_rdata_c_i(instr_rdata_c_id), - .instr_is_compressed_i(instr_is_compressed_id), - .instr_bp_taken_i(instr_bp_taken_id), - .branch_decision_i(branch_decision), - .instr_first_cycle_id_o(instr_first_cycle_id), - .instr_valid_clear_o(instr_valid_clear), - .id_in_ready_o(id_in_ready), - .instr_req_o(instr_req_int), - .pc_set_o(pc_set), - .pc_set_spec_o(pc_set_spec), - .pc_mux_o(pc_mux_id), - .nt_branch_mispredict_o(nt_branch_mispredict), - .exc_pc_mux_o(exc_pc_mux_id), - .exc_cause_o(exc_cause), - .icache_inval_o(icache_inval), - .instr_fetch_err_i(instr_fetch_err), - .instr_fetch_err_plus2_i(instr_fetch_err_plus2), - .illegal_c_insn_i(illegal_c_insn_id), - .pc_id_i(pc_id), - .ex_valid_i(ex_valid), - .lsu_resp_valid_i(lsu_resp_valid), - .alu_operator_ex_o(alu_operator_ex), - .alu_operand_a_ex_o(alu_operand_a_ex), - .alu_operand_b_ex_o(alu_operand_b_ex), - .imd_val_q_ex_o(imd_val_q_ex), - .imd_val_d_ex_i(imd_val_d_ex), - .imd_val_we_ex_i(imd_val_we_ex), - .bt_a_operand_o(bt_a_operand), - .bt_b_operand_o(bt_b_operand), - .mult_en_ex_o(mult_en_ex), - .div_en_ex_o(div_en_ex), - .mult_sel_ex_o(mult_sel_ex), - .div_sel_ex_o(div_sel_ex), - .multdiv_operator_ex_o(multdiv_operator_ex), - .multdiv_signed_mode_ex_o(multdiv_signed_mode_ex), - .multdiv_operand_a_ex_o(multdiv_operand_a_ex), - .multdiv_operand_b_ex_o(multdiv_operand_b_ex), - .multdiv_ready_id_o(multdiv_ready_id), - .csr_access_o(csr_access), - .csr_op_o(csr_op), - .csr_op_en_o(csr_op_en), - .csr_save_if_o(csr_save_if), - .csr_save_id_o(csr_save_id), - .csr_save_wb_o(csr_save_wb), - .csr_restore_mret_id_o(csr_restore_mret_id), - .csr_restore_dret_id_o(csr_restore_dret_id), - .csr_save_cause_o(csr_save_cause), - .csr_mtval_o(csr_mtval), - .priv_mode_i(priv_mode_id), - .csr_mstatus_tw_i(csr_mstatus_tw), - .illegal_csr_insn_i(illegal_csr_insn_id), - .data_ind_timing_i(data_ind_timing), - .lsu_req_o(lsu_req), - .lsu_we_o(lsu_we), - .lsu_type_o(lsu_type), - .lsu_sign_ext_o(lsu_sign_ext), - .lsu_wdata_o(lsu_wdata), - .lsu_req_done_i(lsu_req_done), - .lsu_addr_incr_req_i(lsu_addr_incr_req), - .lsu_addr_last_i(lsu_addr_last), - .lsu_load_err_i(lsu_load_err), - .lsu_store_err_i(lsu_store_err), - .csr_mstatus_mie_i(csr_mstatus_mie), - .irq_pending_i(irq_pending), - .irqs_i(irqs), - .irq_nm_i(irq_nm_i), - .nmi_mode_o(nmi_mode), - .debug_mode_o(debug_mode), - .debug_cause_o(debug_cause), - .debug_csr_save_o(debug_csr_save), - .debug_req_i(debug_req_i), - .debug_single_step_i(debug_single_step), - .debug_ebreakm_i(debug_ebreakm), - .debug_ebreaku_i(debug_ebreaku), - .trigger_match_i(trigger_match), - .result_ex_i(result_ex), - .csr_rdata_i(csr_rdata), - .rf_raddr_a_o(rf_raddr_a), - .rf_rdata_a_i(rf_rdata_a), - .rf_raddr_b_o(rf_raddr_b), - .rf_rdata_b_i(rf_rdata_b), - .rf_ren_a_o(rf_ren_a), - .rf_ren_b_o(rf_ren_b), - .rf_waddr_id_o(rf_waddr_id), - .rf_wdata_id_o(rf_wdata_id), - .rf_we_id_o(rf_we_id), - .rf_rd_a_wb_match_o(rf_rd_a_wb_match), - .rf_rd_b_wb_match_o(rf_rd_b_wb_match), - .rf_waddr_wb_i(rf_waddr_wb), - .rf_wdata_fwd_wb_i(rf_wdata_fwd_wb), - .rf_write_wb_i(rf_write_wb), - .en_wb_o(en_wb), - .instr_type_wb_o(instr_type_wb), - .instr_perf_count_id_o(instr_perf_count_id), - .ready_wb_i(ready_wb), - .outstanding_load_wb_i(outstanding_load_wb), - .outstanding_store_wb_i(outstanding_store_wb), - .perf_jump_o(perf_jump), - .perf_branch_o(perf_branch), - .perf_tbranch_o(perf_tbranch), - .perf_dside_wait_o(perf_dside_wait), - .perf_mul_wait_o(perf_mul_wait), - .perf_div_wait_o(perf_div_wait), - .instr_id_done_o(instr_id_done) - ); - assign unused_illegal_insn_id = illegal_insn_id; - ibex_ex_block #( - .RV32M(RV32M), - .RV32B(RV32B), - .BranchTargetALU(BranchTargetALU) - ) ex_block_i( - .clk_i(clk), - .rst_ni(rst_ni), - .alu_operator_i(alu_operator_ex), - .alu_operand_a_i(alu_operand_a_ex), - .alu_operand_b_i(alu_operand_b_ex), - .alu_instr_first_cycle_i(instr_first_cycle_id), - .bt_a_operand_i(bt_a_operand), - .bt_b_operand_i(bt_b_operand), - .multdiv_operator_i(multdiv_operator_ex), - .mult_en_i(mult_en_ex), - .div_en_i(div_en_ex), - .mult_sel_i(mult_sel_ex), - .div_sel_i(div_sel_ex), - .multdiv_signed_mode_i(multdiv_signed_mode_ex), - .multdiv_operand_a_i(multdiv_operand_a_ex), - .multdiv_operand_b_i(multdiv_operand_b_ex), - .multdiv_ready_id_i(multdiv_ready_id), - .data_ind_timing_i(data_ind_timing), - .imd_val_we_o(imd_val_we_ex), - .imd_val_d_o(imd_val_d_ex), - .imd_val_q_i(imd_val_q_ex), - .alu_adder_result_ex_o(alu_adder_result_ex), - .result_ex_o(result_ex), - .branch_target_o(branch_target_ex), - .branch_decision_o(branch_decision), - .ex_valid_o(ex_valid) - ); - localparam [31:0] ibex_pkg_PMP_D = 1; - assign data_req_o = data_req_out & ~pmp_req_err[ibex_pkg_PMP_D]; - assign lsu_resp_err = lsu_load_err | lsu_store_err; - ibex_load_store_unit load_store_unit_i( - .clk_i(clk), - .rst_ni(rst_ni), - .data_req_o(data_req_out), - .data_gnt_i(data_gnt_i), - .data_rvalid_i(data_rvalid_i), - .data_err_i(data_err_i), - .data_pmp_err_i(pmp_req_err[ibex_pkg_PMP_D]), - .data_addr_o(data_addr_o), - .data_we_o(data_we_o), - .data_be_o(data_be_o), - .data_wdata_o(data_wdata_o), - .data_rdata_i(data_rdata_i), - .lsu_we_i(lsu_we), - .lsu_type_i(lsu_type), - .lsu_wdata_i(lsu_wdata), - .lsu_sign_ext_i(lsu_sign_ext), - .lsu_rdata_o(rf_wdata_lsu), - .lsu_rdata_valid_o(rf_we_lsu), - .lsu_req_i(lsu_req), - .lsu_req_done_o(lsu_req_done), - .adder_result_ex_i(alu_adder_result_ex), - .addr_incr_req_o(lsu_addr_incr_req), - .addr_last_o(lsu_addr_last), - .lsu_resp_valid_o(lsu_resp_valid), - .load_err_o(lsu_load_err), - .store_err_o(lsu_store_err), - .busy_o(lsu_busy), - .perf_load_o(perf_load), - .perf_store_o(perf_store) - ); - ibex_wb_stage #(.WritebackStage(WritebackStage)) wb_stage_i( - .clk_i(clk), - .rst_ni(rst_ni), - .en_wb_i(en_wb), - .instr_type_wb_i(instr_type_wb), - .pc_id_i(pc_id), - .instr_is_compressed_id_i(instr_is_compressed_id), - .instr_perf_count_id_i(instr_perf_count_id), - .ready_wb_o(ready_wb), - .rf_write_wb_o(rf_write_wb), - .outstanding_load_wb_o(outstanding_load_wb), - .outstanding_store_wb_o(outstanding_store_wb), - .pc_wb_o(pc_wb), - .perf_instr_ret_wb_o(perf_instr_ret_wb), - .perf_instr_ret_compressed_wb_o(perf_instr_ret_compressed_wb), - .rf_waddr_id_i(rf_waddr_id), - .rf_wdata_id_i(rf_wdata_id), - .rf_we_id_i(rf_we_id), - .rf_wdata_lsu_i(rf_wdata_lsu), - .rf_we_lsu_i(rf_we_lsu), - .rf_wdata_fwd_wb_o(rf_wdata_fwd_wb), - .rf_waddr_wb_o(rf_waddr_wb), - .rf_wdata_wb_o(rf_wdata_wb), - .rf_we_wb_o(rf_we_wb), - .lsu_resp_valid_i(lsu_resp_valid), - .lsu_resp_err_i(lsu_resp_err), - .instr_done_wb_o(instr_done_wb) - ); - wire [RegFileDataWidth - 1:0] rf_wdata_wb_ecc; - wire [RegFileDataWidth - 1:0] rf_rdata_a_ecc; - wire [RegFileDataWidth - 1:0] rf_rdata_b_ecc; - wire rf_ecc_err_comb; - generate - if (RegFileECC) begin : gen_regfile_ecc - wire [1:0] rf_ecc_err_a; - wire [1:0] rf_ecc_err_b; - wire rf_ecc_err_a_id; - wire rf_ecc_err_b_id; - prim_secded_39_32_enc regfile_ecc_enc( - .in(rf_wdata_wb), - .out(rf_wdata_wb_ecc) - ); - prim_secded_39_32_dec regfile_ecc_dec_a( - .in(rf_rdata_a_ecc), - .d_o(), - .syndrome_o(), - .err_o(rf_ecc_err_a) - ); - prim_secded_39_32_dec regfile_ecc_dec_b( - .in(rf_rdata_b_ecc), - .d_o(), - .syndrome_o(), - .err_o(rf_ecc_err_b) - ); - assign rf_rdata_a = rf_rdata_a_ecc[31:0]; - assign rf_rdata_b = rf_rdata_b_ecc[31:0]; - assign rf_ecc_err_a_id = (|rf_ecc_err_a & rf_ren_a) & ~rf_rd_a_wb_match; - assign rf_ecc_err_b_id = (|rf_ecc_err_b & rf_ren_b) & ~rf_rd_b_wb_match; - assign rf_ecc_err_comb = instr_valid_id & (rf_ecc_err_a_id | rf_ecc_err_b_id); - end - else begin : gen_no_regfile_ecc - wire unused_rf_ren_a; - wire unused_rf_ren_b; - wire unused_rf_rd_a_wb_match; - wire unused_rf_rd_b_wb_match; - assign unused_rf_ren_a = rf_ren_a; - assign unused_rf_ren_b = rf_ren_b; - assign unused_rf_rd_a_wb_match = rf_rd_a_wb_match; - assign unused_rf_rd_b_wb_match = rf_rd_b_wb_match; - assign rf_wdata_wb_ecc = rf_wdata_wb; - assign rf_rdata_a = rf_rdata_a_ecc; - assign rf_rdata_b = rf_rdata_b_ecc; - assign rf_ecc_err_comb = 1'b0; - end - endgenerate - localparam integer ibex_pkg_RegFileFPGA = 1; - localparam integer ibex_pkg_RegFileLatch = 2; - generate - if (RegFile == ibex_pkg_RegFileFF) begin : gen_regfile_ff - ibex_register_file_ff #( - .RV32E(RV32E), - .DataWidth(RegFileDataWidth), - .DummyInstructions(DummyInstructions) - ) register_file_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .test_en_i(test_en_i), - .dummy_instr_id_i(dummy_instr_id), - .raddr_a_i(rf_raddr_a), - .rdata_a_o(rf_rdata_a_ecc), - .raddr_b_i(rf_raddr_b), - .rdata_b_o(rf_rdata_b_ecc), - .waddr_a_i(rf_waddr_wb), - .wdata_a_i(rf_wdata_wb_ecc), - .we_a_i(rf_we_wb) - ); - end - else if (RegFile == ibex_pkg_RegFileFPGA) begin : gen_regfile_fpga - ibex_register_file_fpga #( - .RV32E(RV32E), - .DataWidth(RegFileDataWidth), - .DummyInstructions(DummyInstructions) - ) register_file_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .test_en_i(test_en_i), - .dummy_instr_id_i(dummy_instr_id), - .raddr_a_i(rf_raddr_a), - .rdata_a_o(rf_rdata_a_ecc), - .raddr_b_i(rf_raddr_b), - .rdata_b_o(rf_rdata_b_ecc), - .waddr_a_i(rf_waddr_wb), - .wdata_a_i(rf_wdata_wb_ecc), - .we_a_i(rf_we_wb) - ); - end - else if (RegFile == ibex_pkg_RegFileLatch) begin : gen_regfile_latch - ibex_register_file_latch #( - .RV32E(RV32E), - .DataWidth(RegFileDataWidth), - .DummyInstructions(DummyInstructions) - ) register_file_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .test_en_i(test_en_i), - .dummy_instr_id_i(dummy_instr_id), - .raddr_a_i(rf_raddr_a), - .rdata_a_o(rf_rdata_a_ecc), - .raddr_b_i(rf_raddr_b), - .rdata_b_o(rf_rdata_b_ecc), - .waddr_a_i(rf_waddr_wb), - .wdata_a_i(rf_wdata_wb_ecc), - .we_a_i(rf_we_wb) - ); - end - endgenerate - assign alert_minor_o = 1'b0; - assign alert_major_o = (rf_ecc_err_comb | pc_mismatch_alert) | csr_shadow_err; - assign csr_wdata = alu_operand_a_ex; - function automatic [11:0] sv2v_cast_12; - input reg [11:0] inp; - sv2v_cast_12 = inp; - endfunction - assign csr_addr = sv2v_cast_12((csr_access ? alu_operand_b_ex[11:0] : 12'b000000000000)); - ibex_cs_registers #( - .DbgTriggerEn(DbgTriggerEn), - .DbgHwBreakNum(DbgHwBreakNum), - .DataIndTiming(DataIndTiming), - .DummyInstructions(DummyInstructions), - .ShadowCSR(ShadowCSR), - .ICache(ICache), - .MHPMCounterNum(MHPMCounterNum), - .MHPMCounterWidth(MHPMCounterWidth), - .PMPEnable(PMPEnable), - .PMPGranularity(PMPGranularity), - .PMPNumRegions(PMPNumRegions), - .RV32E(RV32E), - .RV32M(RV32M) - ) cs_registers_i( - .clk_i(clk), - .rst_ni(rst_ni), - .hart_id_i(hart_id_i), - .priv_mode_id_o(priv_mode_id), - .priv_mode_if_o(priv_mode_if), - .priv_mode_lsu_o(priv_mode_lsu), - .csr_mtvec_o(csr_mtvec), - .csr_mtvec_init_i(csr_mtvec_init), - .boot_addr_i(boot_addr_i), - .csr_access_i(csr_access), - .csr_addr_i(csr_addr), - .csr_wdata_i(csr_wdata), - .csr_op_i(csr_op), - .csr_op_en_i(csr_op_en), - .csr_rdata_o(csr_rdata), - .irq_software_i(irq_software_i), - .irq_timer_i(irq_timer_i), - .irq_external_i(irq_external_i), - .irq_fast_i(irq_fast_i), - .nmi_mode_i(nmi_mode), - .irq_pending_o(irq_pending), - .irqs_o(irqs), - .csr_mstatus_mie_o(csr_mstatus_mie), - .csr_mstatus_tw_o(csr_mstatus_tw), - .csr_mepc_o(csr_mepc), - .csr_pmp_cfg_o(csr_pmp_cfg), - .csr_pmp_addr_o(csr_pmp_addr), - .csr_depc_o(csr_depc), - .debug_mode_i(debug_mode), - .debug_cause_i(debug_cause), - .debug_csr_save_i(debug_csr_save), - .debug_single_step_o(debug_single_step), - .debug_ebreakm_o(debug_ebreakm), - .debug_ebreaku_o(debug_ebreaku), - .trigger_match_o(trigger_match), - .pc_if_i(pc_if), - .pc_id_i(pc_id), - .pc_wb_i(pc_wb), - .data_ind_timing_o(data_ind_timing), - .dummy_instr_en_o(dummy_instr_en), - .dummy_instr_mask_o(dummy_instr_mask), - .dummy_instr_seed_en_o(dummy_instr_seed_en), - .dummy_instr_seed_o(dummy_instr_seed), - .icache_enable_o(icache_enable), - .csr_shadow_err_o(csr_shadow_err), - .csr_save_if_i(csr_save_if), - .csr_save_id_i(csr_save_id), - .csr_save_wb_i(csr_save_wb), - .csr_restore_mret_i(csr_restore_mret_id), - .csr_restore_dret_i(csr_restore_dret_id), - .csr_save_cause_i(csr_save_cause), - .csr_mcause_i(exc_cause), - .csr_mtval_i(csr_mtval), - .illegal_csr_insn_o(illegal_csr_insn_id), - .instr_ret_i(perf_instr_ret_wb), - .instr_ret_compressed_i(perf_instr_ret_compressed_wb), - .iside_wait_i(perf_iside_wait), - .jump_i(perf_jump), - .branch_i(perf_branch), - .branch_taken_i(perf_tbranch), - .mem_load_i(perf_load), - .mem_store_i(perf_store), - .dside_wait_i(perf_dside_wait), - .mul_wait_i(perf_mul_wait), - .div_wait_i(perf_div_wait) - ); - localparam [1:0] ibex_pkg_PMP_ACC_EXEC = 2'b00; - localparam [1:0] ibex_pkg_PMP_ACC_READ = 2'b10; - localparam [1:0] ibex_pkg_PMP_ACC_WRITE = 2'b01; - generate - if (PMPEnable) begin : g_pmp - wire [(0 >= (PMP_NUM_CHAN - 1) ? ((2 - PMP_NUM_CHAN) * 34) + (((PMP_NUM_CHAN - 1) * 34) - 1) : (PMP_NUM_CHAN * 34) - 1):(0 >= (PMP_NUM_CHAN - 1) ? (PMP_NUM_CHAN - 1) * 34 : 0)] pmp_req_addr; - wire [(0 >= (PMP_NUM_CHAN - 1) ? ((2 - PMP_NUM_CHAN) * 2) + (((PMP_NUM_CHAN - 1) * 2) - 1) : (PMP_NUM_CHAN * 2) - 1):(0 >= (PMP_NUM_CHAN - 1) ? (PMP_NUM_CHAN - 1) * 2 : 0)] pmp_req_type; - wire [(0 >= (PMP_NUM_CHAN - 1) ? ((2 - PMP_NUM_CHAN) * 2) + (((PMP_NUM_CHAN - 1) * 2) - 1) : (PMP_NUM_CHAN * 2) - 1):(0 >= (PMP_NUM_CHAN - 1) ? (PMP_NUM_CHAN - 1) * 2 : 0)] pmp_priv_lvl; - assign pmp_req_addr[(0 >= (PMP_NUM_CHAN - 1) ? ibex_pkg_PMP_I : (PMP_NUM_CHAN - 1) - ibex_pkg_PMP_I) * 34+:34] = {2'b00, instr_addr_o[31:0]}; - assign pmp_req_type[(0 >= (PMP_NUM_CHAN - 1) ? ibex_pkg_PMP_I : (PMP_NUM_CHAN - 1) - ibex_pkg_PMP_I) * 2+:2] = ibex_pkg_PMP_ACC_EXEC; - assign pmp_priv_lvl[(0 >= (PMP_NUM_CHAN - 1) ? ibex_pkg_PMP_I : (PMP_NUM_CHAN - 1) - ibex_pkg_PMP_I) * 2+:2] = priv_mode_if; - assign pmp_req_addr[(0 >= (PMP_NUM_CHAN - 1) ? ibex_pkg_PMP_D : (PMP_NUM_CHAN - 1) - ibex_pkg_PMP_D) * 34+:34] = {2'b00, data_addr_o[31:0]}; - assign pmp_req_type[(0 >= (PMP_NUM_CHAN - 1) ? ibex_pkg_PMP_D : (PMP_NUM_CHAN - 1) - ibex_pkg_PMP_D) * 2+:2] = (data_we_o ? ibex_pkg_PMP_ACC_WRITE : ibex_pkg_PMP_ACC_READ); - assign pmp_priv_lvl[(0 >= (PMP_NUM_CHAN - 1) ? ibex_pkg_PMP_D : (PMP_NUM_CHAN - 1) - ibex_pkg_PMP_D) * 2+:2] = priv_mode_lsu; - ibex_pmp #( - .PMPGranularity(PMPGranularity), - .PMPNumChan(PMP_NUM_CHAN), - .PMPNumRegions(PMPNumRegions) - ) pmp_i( - .clk_i(clk), - .rst_ni(rst_ni), - .csr_pmp_cfg_i(csr_pmp_cfg), - .csr_pmp_addr_i(csr_pmp_addr), - .priv_mode_i(pmp_priv_lvl), - .pmp_req_addr_i(pmp_req_addr), - .pmp_req_type_i(pmp_req_type), - .pmp_req_err_o(pmp_req_err) - ); - end - else begin : g_no_pmp - wire [1:0] unused_priv_lvl_if; - wire [1:0] unused_priv_lvl_ls; - wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 34) + (((PMPNumRegions - 1) * 34) - 1) : (PMPNumRegions * 34) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 34 : 0)] unused_csr_pmp_addr; - wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 6) + (((PMPNumRegions - 1) * 6) - 1) : (PMPNumRegions * 6) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 6 : 0)] unused_csr_pmp_cfg; - assign unused_priv_lvl_if = priv_mode_if; - assign unused_priv_lvl_ls = priv_mode_lsu; - assign unused_csr_pmp_addr = csr_pmp_addr; - assign unused_csr_pmp_cfg = csr_pmp_cfg; - assign pmp_req_err[ibex_pkg_PMP_I] = 1'b0; - assign pmp_req_err[ibex_pkg_PMP_D] = 1'b0; - end - endgenerate - wire unused_instr_new_id; - wire unused_instr_done_wb; - assign unused_instr_new_id = instr_new_id; - assign unused_instr_done_wb = instr_done_wb; -endmodule diff --git a/flow/designs/src/ibex/ibex_counter.v b/flow/designs/src/ibex/ibex_counter.v deleted file mode 100644 index 081590ebf1..0000000000 --- a/flow/designs/src/ibex/ibex_counter.v +++ /dev/null @@ -1,57 +0,0 @@ -module ibex_counter ( - clk_i, - rst_ni, - counter_inc_i, - counterh_we_i, - counter_we_i, - counter_val_i, - counter_val_o -); - parameter signed [31:0] CounterWidth = 32; - input wire clk_i; - input wire rst_ni; - input wire counter_inc_i; - input wire counterh_we_i; - input wire counter_we_i; - input wire [31:0] counter_val_i; - output wire [63:0] counter_val_o; - wire [63:0] counter; - reg [CounterWidth - 1:0] counter_upd; - reg [63:0] counter_load; - reg we; - reg [CounterWidth - 1:0] counter_d; - always @(*) begin - we = counter_we_i | counterh_we_i; - counter_load[63:32] = counter[63:32]; - counter_load[31:0] = counter_val_i; - if (counterh_we_i) begin - counter_load[63:32] = counter_val_i; - counter_load[31:0] = counter[31:0]; - end - counter_upd = counter[CounterWidth - 1:0] + {{CounterWidth - 1 {1'b0}}, 1'b1}; - if (we) - counter_d = counter_load[CounterWidth - 1:0]; - else if (counter_inc_i) - counter_d = counter_upd[CounterWidth - 1:0]; - else - counter_d = counter[CounterWidth - 1:0]; - end - reg [CounterWidth - 1:0] counter_q; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - counter_q <= {CounterWidth {1'sb0}}; - else - counter_q <= counter_d; - generate - if (CounterWidth < 64) begin : g_counter_narrow - wire [63:CounterWidth] unused_counter_load; - assign counter[CounterWidth - 1:0] = counter_q; - assign counter[63:CounterWidth] = {(63 >= CounterWidth ? 64 - CounterWidth : CounterWidth - 62) {1'sb0}}; - assign unused_counter_load = counter_load[63:CounterWidth]; - end - else begin : g_counter_full - assign counter = counter_q; - end - endgenerate - assign counter_val_o = counter; -endmodule diff --git a/flow/designs/src/ibex/ibex_cs_registers.v b/flow/designs/src/ibex/ibex_cs_registers.v deleted file mode 100644 index 5e7000abd6..0000000000 --- a/flow/designs/src/ibex/ibex_cs_registers.v +++ /dev/null @@ -1,1191 +0,0 @@ -module ibex_cs_registers ( - clk_i, - rst_ni, - hart_id_i, - priv_mode_id_o, - priv_mode_if_o, - priv_mode_lsu_o, - csr_mstatus_tw_o, - csr_mtvec_o, - csr_mtvec_init_i, - boot_addr_i, - csr_access_i, - csr_addr_i, - csr_wdata_i, - csr_op_i, - csr_op_en_i, - csr_rdata_o, - irq_software_i, - irq_timer_i, - irq_external_i, - irq_fast_i, - nmi_mode_i, - irq_pending_o, - irqs_o, - csr_mstatus_mie_o, - csr_mepc_o, - csr_pmp_cfg_o, - csr_pmp_addr_o, - debug_mode_i, - debug_cause_i, - debug_csr_save_i, - csr_depc_o, - debug_single_step_o, - debug_ebreakm_o, - debug_ebreaku_o, - trigger_match_o, - pc_if_i, - pc_id_i, - pc_wb_i, - data_ind_timing_o, - dummy_instr_en_o, - dummy_instr_mask_o, - dummy_instr_seed_en_o, - dummy_instr_seed_o, - icache_enable_o, - csr_shadow_err_o, - csr_save_if_i, - csr_save_id_i, - csr_save_wb_i, - csr_restore_mret_i, - csr_restore_dret_i, - csr_save_cause_i, - csr_mcause_i, - csr_mtval_i, - illegal_csr_insn_o, - instr_ret_i, - instr_ret_compressed_i, - iside_wait_i, - jump_i, - branch_i, - branch_taken_i, - mem_load_i, - mem_store_i, - dside_wait_i, - mul_wait_i, - div_wait_i -); - parameter [0:0] DbgTriggerEn = 0; - parameter [31:0] DbgHwBreakNum = 1; - parameter [0:0] DataIndTiming = 1'b0; - parameter [0:0] DummyInstructions = 1'b0; - parameter [0:0] ShadowCSR = 1'b0; - parameter [0:0] ICache = 1'b0; - parameter [31:0] MHPMCounterNum = 10; - parameter [31:0] MHPMCounterWidth = 40; - parameter [0:0] PMPEnable = 0; - parameter [31:0] PMPGranularity = 0; - parameter [31:0] PMPNumRegions = 4; - parameter [0:0] RV32E = 0; - localparam integer ibex_pkg_RV32MFast = 2; - parameter integer RV32M = ibex_pkg_RV32MFast; - input wire clk_i; - input wire rst_ni; - input wire [31:0] hart_id_i; - output wire [1:0] priv_mode_id_o; - output wire [1:0] priv_mode_if_o; - output wire [1:0] priv_mode_lsu_o; - output wire csr_mstatus_tw_o; - output wire [31:0] csr_mtvec_o; - input wire csr_mtvec_init_i; - input wire [31:0] boot_addr_i; - input wire csr_access_i; - input wire [11:0] csr_addr_i; - input wire [31:0] csr_wdata_i; - input wire [1:0] csr_op_i; - input csr_op_en_i; - output wire [31:0] csr_rdata_o; - input wire irq_software_i; - input wire irq_timer_i; - input wire irq_external_i; - input wire [14:0] irq_fast_i; - input wire nmi_mode_i; - output wire irq_pending_o; - output wire [17:0] irqs_o; - output wire csr_mstatus_mie_o; - output wire [31:0] csr_mepc_o; - output wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 6) + (((PMPNumRegions - 1) * 6) - 1) : (PMPNumRegions * 6) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 6 : 0)] csr_pmp_cfg_o; - output wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 34) + (((PMPNumRegions - 1) * 34) - 1) : (PMPNumRegions * 34) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 34 : 0)] csr_pmp_addr_o; - input wire debug_mode_i; - input wire [2:0] debug_cause_i; - input wire debug_csr_save_i; - output wire [31:0] csr_depc_o; - output wire debug_single_step_o; - output wire debug_ebreakm_o; - output wire debug_ebreaku_o; - output wire trigger_match_o; - input wire [31:0] pc_if_i; - input wire [31:0] pc_id_i; - input wire [31:0] pc_wb_i; - output wire data_ind_timing_o; - output wire dummy_instr_en_o; - output wire [2:0] dummy_instr_mask_o; - output wire dummy_instr_seed_en_o; - output wire [31:0] dummy_instr_seed_o; - output wire icache_enable_o; - output wire csr_shadow_err_o; - input wire csr_save_if_i; - input wire csr_save_id_i; - input wire csr_save_wb_i; - input wire csr_restore_mret_i; - input wire csr_restore_dret_i; - input wire csr_save_cause_i; - input wire [5:0] csr_mcause_i; - input wire [31:0] csr_mtval_i; - output wire illegal_csr_insn_o; - input wire instr_ret_i; - input wire instr_ret_compressed_i; - input wire iside_wait_i; - input wire jump_i; - input wire branch_i; - input wire branch_taken_i; - input wire mem_load_i; - input wire mem_store_i; - input wire dside_wait_i; - input wire mul_wait_i; - input wire div_wait_i; - localparam integer ibex_pkg_RV32MNone = 0; - localparam [31:0] RV32MEnabled = (RV32M == ibex_pkg_RV32MNone ? 0 : 1); - localparam [31:0] PMPAddrWidth = (PMPGranularity > 0 ? 33 - PMPGranularity : 32); - localparam [1:0] ibex_pkg_CSR_MISA_MXL = 2'd1; - function automatic [31:0] sv2v_cast_32; - input reg [31:0] inp; - sv2v_cast_32 = inp; - endfunction - localparam [31:0] MISA_VALUE = ((((((((((0 | 4) | 0) | (sv2v_cast_32(RV32E) << 4)) | 0) | (sv2v_cast_32(!RV32E) << 8)) | (RV32MEnabled << 12)) | 0) | 0) | 1048576) | 0) | (sv2v_cast_32(ibex_pkg_CSR_MISA_MXL) << 30); - reg [31:0] exception_pc; - reg [1:0] priv_lvl_q; - reg [1:0] priv_lvl_d; - wire [5:0] mstatus_q; - reg [5:0] mstatus_d; - wire mstatus_err; - reg mstatus_en; - wire [17:0] mie_q; - wire [17:0] mie_d; - reg mie_en; - wire [31:0] mscratch_q; - reg mscratch_en; - wire [31:0] mepc_q; - reg [31:0] mepc_d; - reg mepc_en; - wire [5:0] mcause_q; - reg [5:0] mcause_d; - reg mcause_en; - wire [31:0] mtval_q; - reg [31:0] mtval_d; - reg mtval_en; - wire [31:0] mtvec_q; - reg [31:0] mtvec_d; - wire mtvec_err; - reg mtvec_en; - wire [17:0] mip; - wire [31:0] dcsr_q; - reg [31:0] dcsr_d; - reg dcsr_en; - wire [31:0] depc_q; - reg [31:0] depc_d; - reg depc_en; - wire [31:0] dscratch0_q; - wire [31:0] dscratch1_q; - reg dscratch0_en; - reg dscratch1_en; - wire [2:0] mstack_q; - reg [2:0] mstack_d; - reg mstack_en; - wire [31:0] mstack_epc_q; - reg [31:0] mstack_epc_d; - wire [5:0] mstack_cause_q; - reg [5:0] mstack_cause_d; - localparam [31:0] ibex_pkg_PMP_MAX_REGIONS = 16; - reg [31:0] pmp_addr_rdata [0:ibex_pkg_PMP_MAX_REGIONS - 1]; - localparam [31:0] ibex_pkg_PMP_CFG_W = 8; - wire [ibex_pkg_PMP_CFG_W - 1:0] pmp_cfg_rdata [0:ibex_pkg_PMP_MAX_REGIONS - 1]; - wire pmp_csr_err; - wire [31:0] mcountinhibit; - reg [MHPMCounterNum + 2:0] mcountinhibit_d; - reg [MHPMCounterNum + 2:0] mcountinhibit_q; - reg mcountinhibit_we; - wire [63:0] mhpmcounter [0:31]; - reg [31:0] mhpmcounter_we; - reg [31:0] mhpmcounterh_we; - reg [31:0] mhpmcounter_incr; - reg [31:0] mhpmevent [0:31]; - wire [4:0] mhpmcounter_idx; - wire unused_mhpmcounter_we_1; - wire unused_mhpmcounterh_we_1; - wire unused_mhpmcounter_incr_1; - wire [31:0] tselect_rdata; - wire [31:0] tmatch_control_rdata; - wire [31:0] tmatch_value_rdata; - wire [5:0] cpuctrl_q; - wire [5:0] cpuctrl_d; - wire [5:0] cpuctrl_wdata; - reg cpuctrl_we; - wire cpuctrl_err; - reg [31:0] csr_wdata_int; - reg [31:0] csr_rdata_int; - wire csr_we_int; - wire csr_wreq; - reg illegal_csr; - wire illegal_csr_priv; - wire illegal_csr_write; - wire [7:0] unused_boot_addr; - wire [2:0] unused_csr_addr; - assign unused_boot_addr = boot_addr_i[7:0]; - wire [11:0] csr_addr; - assign csr_addr = {csr_addr_i}; - assign unused_csr_addr = csr_addr[7:5]; - assign mhpmcounter_idx = csr_addr[4:0]; - assign illegal_csr_priv = csr_addr[9:8] > {priv_lvl_q}; - assign illegal_csr_write = (csr_addr[11:10] == 2'b11) && csr_wreq; - assign illegal_csr_insn_o = csr_access_i & ((illegal_csr | illegal_csr_write) | illegal_csr_priv); - assign mip[17] = irq_software_i; - assign mip[16] = irq_timer_i; - assign mip[15] = irq_external_i; - assign mip[14-:15] = irq_fast_i; - localparam [31:0] ibex_pkg_CSR_MEIX_BIT = 11; - localparam [31:0] ibex_pkg_CSR_MFIX_BIT_HIGH = 30; - localparam [31:0] ibex_pkg_CSR_MFIX_BIT_LOW = 16; - localparam [31:0] ibex_pkg_CSR_MSIX_BIT = 3; - localparam [31:0] ibex_pkg_CSR_MSTATUS_MIE_BIT = 3; - localparam [31:0] ibex_pkg_CSR_MSTATUS_MPIE_BIT = 7; - localparam [31:0] ibex_pkg_CSR_MSTATUS_MPP_BIT_HIGH = 12; - localparam [31:0] ibex_pkg_CSR_MSTATUS_MPP_BIT_LOW = 11; - localparam [31:0] ibex_pkg_CSR_MSTATUS_MPRV_BIT = 17; - localparam [31:0] ibex_pkg_CSR_MSTATUS_TW_BIT = 21; - localparam [31:0] ibex_pkg_CSR_MTIX_BIT = 7; - localparam [11:0] ibex_pkg_CSR_CPUCTRL = 12'h7c0; - localparam [11:0] ibex_pkg_CSR_DCSR = 12'h7b0; - localparam [11:0] ibex_pkg_CSR_DPC = 12'h7b1; - localparam [11:0] ibex_pkg_CSR_DSCRATCH0 = 12'h7b2; - localparam [11:0] ibex_pkg_CSR_DSCRATCH1 = 12'h7b3; - localparam [11:0] ibex_pkg_CSR_MCAUSE = 12'h342; - localparam [11:0] ibex_pkg_CSR_MCONTEXT = 12'h7a8; - localparam [11:0] ibex_pkg_CSR_MCOUNTINHIBIT = 12'h320; - localparam [11:0] ibex_pkg_CSR_MCYCLE = 12'hb00; - localparam [11:0] ibex_pkg_CSR_MCYCLEH = 12'hb80; - localparam [11:0] ibex_pkg_CSR_MEPC = 12'h341; - localparam [11:0] ibex_pkg_CSR_MHARTID = 12'hf14; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER10 = 12'hb0a; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER10H = 12'hb8a; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER11 = 12'hb0b; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER11H = 12'hb8b; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER12 = 12'hb0c; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER12H = 12'hb8c; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER13 = 12'hb0d; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER13H = 12'hb8d; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER14 = 12'hb0e; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER14H = 12'hb8e; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER15 = 12'hb0f; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER15H = 12'hb8f; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER16 = 12'hb10; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER16H = 12'hb90; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER17 = 12'hb11; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER17H = 12'hb91; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER18 = 12'hb12; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER18H = 12'hb92; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER19 = 12'hb13; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER19H = 12'hb93; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER20 = 12'hb14; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER20H = 12'hb94; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER21 = 12'hb15; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER21H = 12'hb95; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER22 = 12'hb16; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER22H = 12'hb96; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER23 = 12'hb17; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER23H = 12'hb97; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER24 = 12'hb18; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER24H = 12'hb98; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER25 = 12'hb19; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER25H = 12'hb99; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER26 = 12'hb1a; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER26H = 12'hb9a; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER27 = 12'hb1b; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER27H = 12'hb9b; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER28 = 12'hb1c; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER28H = 12'hb9c; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER29 = 12'hb1d; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER29H = 12'hb9d; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER3 = 12'hb03; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER30 = 12'hb1e; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER30H = 12'hb9e; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER31 = 12'hb1f; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER31H = 12'hb9f; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER3H = 12'hb83; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER4 = 12'hb04; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER4H = 12'hb84; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER5 = 12'hb05; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER5H = 12'hb85; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER6 = 12'hb06; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER6H = 12'hb86; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER7 = 12'hb07; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER7H = 12'hb87; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER8 = 12'hb08; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER8H = 12'hb88; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER9 = 12'hb09; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER9H = 12'hb89; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT10 = 12'h32a; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT11 = 12'h32b; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT12 = 12'h32c; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT13 = 12'h32d; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT14 = 12'h32e; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT15 = 12'h32f; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT16 = 12'h330; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT17 = 12'h331; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT18 = 12'h332; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT19 = 12'h333; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT20 = 12'h334; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT21 = 12'h335; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT22 = 12'h336; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT23 = 12'h337; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT24 = 12'h338; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT25 = 12'h339; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT26 = 12'h33a; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT27 = 12'h33b; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT28 = 12'h33c; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT29 = 12'h33d; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT3 = 12'h323; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT30 = 12'h33e; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT31 = 12'h33f; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT4 = 12'h324; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT5 = 12'h325; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT6 = 12'h326; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT7 = 12'h327; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT8 = 12'h328; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT9 = 12'h329; - localparam [11:0] ibex_pkg_CSR_MIE = 12'h304; - localparam [11:0] ibex_pkg_CSR_MINSTRET = 12'hb02; - localparam [11:0] ibex_pkg_CSR_MINSTRETH = 12'hb82; - localparam [11:0] ibex_pkg_CSR_MIP = 12'h344; - localparam [11:0] ibex_pkg_CSR_MISA = 12'h301; - localparam [11:0] ibex_pkg_CSR_MSCRATCH = 12'h340; - localparam [11:0] ibex_pkg_CSR_MSTATUS = 12'h300; - localparam [11:0] ibex_pkg_CSR_MTVAL = 12'h343; - localparam [11:0] ibex_pkg_CSR_MTVEC = 12'h305; - localparam [11:0] ibex_pkg_CSR_PMPADDR0 = 12'h3b0; - localparam [11:0] ibex_pkg_CSR_PMPADDR1 = 12'h3b1; - localparam [11:0] ibex_pkg_CSR_PMPADDR10 = 12'h3ba; - localparam [11:0] ibex_pkg_CSR_PMPADDR11 = 12'h3bb; - localparam [11:0] ibex_pkg_CSR_PMPADDR12 = 12'h3bc; - localparam [11:0] ibex_pkg_CSR_PMPADDR13 = 12'h3bd; - localparam [11:0] ibex_pkg_CSR_PMPADDR14 = 12'h3be; - localparam [11:0] ibex_pkg_CSR_PMPADDR15 = 12'h3bf; - localparam [11:0] ibex_pkg_CSR_PMPADDR2 = 12'h3b2; - localparam [11:0] ibex_pkg_CSR_PMPADDR3 = 12'h3b3; - localparam [11:0] ibex_pkg_CSR_PMPADDR4 = 12'h3b4; - localparam [11:0] ibex_pkg_CSR_PMPADDR5 = 12'h3b5; - localparam [11:0] ibex_pkg_CSR_PMPADDR6 = 12'h3b6; - localparam [11:0] ibex_pkg_CSR_PMPADDR7 = 12'h3b7; - localparam [11:0] ibex_pkg_CSR_PMPADDR8 = 12'h3b8; - localparam [11:0] ibex_pkg_CSR_PMPADDR9 = 12'h3b9; - localparam [11:0] ibex_pkg_CSR_PMPCFG0 = 12'h3a0; - localparam [11:0] ibex_pkg_CSR_PMPCFG1 = 12'h3a1; - localparam [11:0] ibex_pkg_CSR_PMPCFG2 = 12'h3a2; - localparam [11:0] ibex_pkg_CSR_PMPCFG3 = 12'h3a3; - localparam [11:0] ibex_pkg_CSR_SCONTEXT = 12'h7aa; - localparam [11:0] ibex_pkg_CSR_SECURESEED = 12'h7c1; - localparam [11:0] ibex_pkg_CSR_TDATA1 = 12'h7a1; - localparam [11:0] ibex_pkg_CSR_TDATA2 = 12'h7a2; - localparam [11:0] ibex_pkg_CSR_TDATA3 = 12'h7a3; - localparam [11:0] ibex_pkg_CSR_TSELECT = 12'h7a0; - always @(*) begin - csr_rdata_int = {32 {1'sb0}}; - illegal_csr = 1'b0; - case (csr_addr_i) - ibex_pkg_CSR_MHARTID: csr_rdata_int = hart_id_i; - ibex_pkg_CSR_MSTATUS: begin - csr_rdata_int = {32 {1'sb0}}; - csr_rdata_int[ibex_pkg_CSR_MSTATUS_MIE_BIT] = mstatus_q[5]; - csr_rdata_int[ibex_pkg_CSR_MSTATUS_MPIE_BIT] = mstatus_q[4]; - csr_rdata_int[ibex_pkg_CSR_MSTATUS_MPP_BIT_HIGH:ibex_pkg_CSR_MSTATUS_MPP_BIT_LOW] = mstatus_q[3-:2]; - csr_rdata_int[ibex_pkg_CSR_MSTATUS_MPRV_BIT] = mstatus_q[1]; - csr_rdata_int[ibex_pkg_CSR_MSTATUS_TW_BIT] = mstatus_q[0]; - end - ibex_pkg_CSR_MISA: csr_rdata_int = MISA_VALUE; - ibex_pkg_CSR_MIE: begin - csr_rdata_int = {32 {1'sb0}}; - csr_rdata_int[ibex_pkg_CSR_MSIX_BIT] = mie_q[17]; - csr_rdata_int[ibex_pkg_CSR_MTIX_BIT] = mie_q[16]; - csr_rdata_int[ibex_pkg_CSR_MEIX_BIT] = mie_q[15]; - csr_rdata_int[ibex_pkg_CSR_MFIX_BIT_HIGH:ibex_pkg_CSR_MFIX_BIT_LOW] = mie_q[14-:15]; - end - ibex_pkg_CSR_MSCRATCH: csr_rdata_int = mscratch_q; - ibex_pkg_CSR_MTVEC: csr_rdata_int = mtvec_q; - ibex_pkg_CSR_MEPC: csr_rdata_int = mepc_q; - ibex_pkg_CSR_MCAUSE: csr_rdata_int = {mcause_q[5], 26'b00000000000000000000000000, mcause_q[4:0]}; - ibex_pkg_CSR_MTVAL: csr_rdata_int = mtval_q; - ibex_pkg_CSR_MIP: begin - csr_rdata_int = {32 {1'sb0}}; - csr_rdata_int[ibex_pkg_CSR_MSIX_BIT] = mip[17]; - csr_rdata_int[ibex_pkg_CSR_MTIX_BIT] = mip[16]; - csr_rdata_int[ibex_pkg_CSR_MEIX_BIT] = mip[15]; - csr_rdata_int[ibex_pkg_CSR_MFIX_BIT_HIGH:ibex_pkg_CSR_MFIX_BIT_LOW] = mip[14-:15]; - end - ibex_pkg_CSR_PMPCFG0: csr_rdata_int = {pmp_cfg_rdata[3], pmp_cfg_rdata[2], pmp_cfg_rdata[1], pmp_cfg_rdata[0]}; - ibex_pkg_CSR_PMPCFG1: csr_rdata_int = {pmp_cfg_rdata[7], pmp_cfg_rdata[6], pmp_cfg_rdata[5], pmp_cfg_rdata[4]}; - ibex_pkg_CSR_PMPCFG2: csr_rdata_int = {pmp_cfg_rdata[11], pmp_cfg_rdata[10], pmp_cfg_rdata[9], pmp_cfg_rdata[8]}; - ibex_pkg_CSR_PMPCFG3: csr_rdata_int = {pmp_cfg_rdata[15], pmp_cfg_rdata[14], pmp_cfg_rdata[13], pmp_cfg_rdata[12]}; - ibex_pkg_CSR_PMPADDR0: csr_rdata_int = pmp_addr_rdata[0]; - ibex_pkg_CSR_PMPADDR1: csr_rdata_int = pmp_addr_rdata[1]; - ibex_pkg_CSR_PMPADDR2: csr_rdata_int = pmp_addr_rdata[2]; - ibex_pkg_CSR_PMPADDR3: csr_rdata_int = pmp_addr_rdata[3]; - ibex_pkg_CSR_PMPADDR4: csr_rdata_int = pmp_addr_rdata[4]; - ibex_pkg_CSR_PMPADDR5: csr_rdata_int = pmp_addr_rdata[5]; - ibex_pkg_CSR_PMPADDR6: csr_rdata_int = pmp_addr_rdata[6]; - ibex_pkg_CSR_PMPADDR7: csr_rdata_int = pmp_addr_rdata[7]; - ibex_pkg_CSR_PMPADDR8: csr_rdata_int = pmp_addr_rdata[8]; - ibex_pkg_CSR_PMPADDR9: csr_rdata_int = pmp_addr_rdata[9]; - ibex_pkg_CSR_PMPADDR10: csr_rdata_int = pmp_addr_rdata[10]; - ibex_pkg_CSR_PMPADDR11: csr_rdata_int = pmp_addr_rdata[11]; - ibex_pkg_CSR_PMPADDR12: csr_rdata_int = pmp_addr_rdata[12]; - ibex_pkg_CSR_PMPADDR13: csr_rdata_int = pmp_addr_rdata[13]; - ibex_pkg_CSR_PMPADDR14: csr_rdata_int = pmp_addr_rdata[14]; - ibex_pkg_CSR_PMPADDR15: csr_rdata_int = pmp_addr_rdata[15]; - ibex_pkg_CSR_DCSR: begin - csr_rdata_int = dcsr_q; - illegal_csr = ~debug_mode_i; - end - ibex_pkg_CSR_DPC: begin - csr_rdata_int = depc_q; - illegal_csr = ~debug_mode_i; - end - ibex_pkg_CSR_DSCRATCH0: begin - csr_rdata_int = dscratch0_q; - illegal_csr = ~debug_mode_i; - end - ibex_pkg_CSR_DSCRATCH1: begin - csr_rdata_int = dscratch1_q; - illegal_csr = ~debug_mode_i; - end - ibex_pkg_CSR_MCOUNTINHIBIT: csr_rdata_int = mcountinhibit; - ibex_pkg_CSR_MHPMEVENT3, ibex_pkg_CSR_MHPMEVENT4, ibex_pkg_CSR_MHPMEVENT5, ibex_pkg_CSR_MHPMEVENT6, ibex_pkg_CSR_MHPMEVENT7, ibex_pkg_CSR_MHPMEVENT8, ibex_pkg_CSR_MHPMEVENT9, ibex_pkg_CSR_MHPMEVENT10, ibex_pkg_CSR_MHPMEVENT11, ibex_pkg_CSR_MHPMEVENT12, ibex_pkg_CSR_MHPMEVENT13, ibex_pkg_CSR_MHPMEVENT14, ibex_pkg_CSR_MHPMEVENT15, ibex_pkg_CSR_MHPMEVENT16, ibex_pkg_CSR_MHPMEVENT17, ibex_pkg_CSR_MHPMEVENT18, ibex_pkg_CSR_MHPMEVENT19, ibex_pkg_CSR_MHPMEVENT20, ibex_pkg_CSR_MHPMEVENT21, ibex_pkg_CSR_MHPMEVENT22, ibex_pkg_CSR_MHPMEVENT23, ibex_pkg_CSR_MHPMEVENT24, ibex_pkg_CSR_MHPMEVENT25, ibex_pkg_CSR_MHPMEVENT26, ibex_pkg_CSR_MHPMEVENT27, ibex_pkg_CSR_MHPMEVENT28, ibex_pkg_CSR_MHPMEVENT29, ibex_pkg_CSR_MHPMEVENT30, ibex_pkg_CSR_MHPMEVENT31: csr_rdata_int = mhpmevent[mhpmcounter_idx]; - ibex_pkg_CSR_MCYCLE, ibex_pkg_CSR_MINSTRET, ibex_pkg_CSR_MHPMCOUNTER3, ibex_pkg_CSR_MHPMCOUNTER4, ibex_pkg_CSR_MHPMCOUNTER5, ibex_pkg_CSR_MHPMCOUNTER6, ibex_pkg_CSR_MHPMCOUNTER7, ibex_pkg_CSR_MHPMCOUNTER8, ibex_pkg_CSR_MHPMCOUNTER9, ibex_pkg_CSR_MHPMCOUNTER10, ibex_pkg_CSR_MHPMCOUNTER11, ibex_pkg_CSR_MHPMCOUNTER12, ibex_pkg_CSR_MHPMCOUNTER13, ibex_pkg_CSR_MHPMCOUNTER14, ibex_pkg_CSR_MHPMCOUNTER15, ibex_pkg_CSR_MHPMCOUNTER16, ibex_pkg_CSR_MHPMCOUNTER17, ibex_pkg_CSR_MHPMCOUNTER18, ibex_pkg_CSR_MHPMCOUNTER19, ibex_pkg_CSR_MHPMCOUNTER20, ibex_pkg_CSR_MHPMCOUNTER21, ibex_pkg_CSR_MHPMCOUNTER22, ibex_pkg_CSR_MHPMCOUNTER23, ibex_pkg_CSR_MHPMCOUNTER24, ibex_pkg_CSR_MHPMCOUNTER25, ibex_pkg_CSR_MHPMCOUNTER26, ibex_pkg_CSR_MHPMCOUNTER27, ibex_pkg_CSR_MHPMCOUNTER28, ibex_pkg_CSR_MHPMCOUNTER29, ibex_pkg_CSR_MHPMCOUNTER30, ibex_pkg_CSR_MHPMCOUNTER31: csr_rdata_int = mhpmcounter[mhpmcounter_idx][31:0]; - ibex_pkg_CSR_MCYCLEH, ibex_pkg_CSR_MINSTRETH, ibex_pkg_CSR_MHPMCOUNTER3H, ibex_pkg_CSR_MHPMCOUNTER4H, ibex_pkg_CSR_MHPMCOUNTER5H, ibex_pkg_CSR_MHPMCOUNTER6H, ibex_pkg_CSR_MHPMCOUNTER7H, ibex_pkg_CSR_MHPMCOUNTER8H, ibex_pkg_CSR_MHPMCOUNTER9H, ibex_pkg_CSR_MHPMCOUNTER10H, ibex_pkg_CSR_MHPMCOUNTER11H, ibex_pkg_CSR_MHPMCOUNTER12H, ibex_pkg_CSR_MHPMCOUNTER13H, ibex_pkg_CSR_MHPMCOUNTER14H, ibex_pkg_CSR_MHPMCOUNTER15H, ibex_pkg_CSR_MHPMCOUNTER16H, ibex_pkg_CSR_MHPMCOUNTER17H, ibex_pkg_CSR_MHPMCOUNTER18H, ibex_pkg_CSR_MHPMCOUNTER19H, ibex_pkg_CSR_MHPMCOUNTER20H, ibex_pkg_CSR_MHPMCOUNTER21H, ibex_pkg_CSR_MHPMCOUNTER22H, ibex_pkg_CSR_MHPMCOUNTER23H, ibex_pkg_CSR_MHPMCOUNTER24H, ibex_pkg_CSR_MHPMCOUNTER25H, ibex_pkg_CSR_MHPMCOUNTER26H, ibex_pkg_CSR_MHPMCOUNTER27H, ibex_pkg_CSR_MHPMCOUNTER28H, ibex_pkg_CSR_MHPMCOUNTER29H, ibex_pkg_CSR_MHPMCOUNTER30H, ibex_pkg_CSR_MHPMCOUNTER31H: csr_rdata_int = mhpmcounter[mhpmcounter_idx][63:32]; - ibex_pkg_CSR_TSELECT: begin - csr_rdata_int = tselect_rdata; - illegal_csr = ~DbgTriggerEn; - end - ibex_pkg_CSR_TDATA1: begin - csr_rdata_int = tmatch_control_rdata; - illegal_csr = ~DbgTriggerEn; - end - ibex_pkg_CSR_TDATA2: begin - csr_rdata_int = tmatch_value_rdata; - illegal_csr = ~DbgTriggerEn; - end - ibex_pkg_CSR_TDATA3: begin - csr_rdata_int = {32 {1'sb0}}; - illegal_csr = ~DbgTriggerEn; - end - ibex_pkg_CSR_MCONTEXT: begin - csr_rdata_int = {32 {1'sb0}}; - illegal_csr = ~DbgTriggerEn; - end - ibex_pkg_CSR_SCONTEXT: begin - csr_rdata_int = {32 {1'sb0}}; - illegal_csr = ~DbgTriggerEn; - end - ibex_pkg_CSR_CPUCTRL: csr_rdata_int = {{26 {1'b0}}, cpuctrl_q}; - ibex_pkg_CSR_SECURESEED: csr_rdata_int = {32 {1'sb0}}; - default: illegal_csr = 1'b1; - endcase - end - localparam [1:0] ibex_pkg_PRIV_LVL_M = 2'b11; - localparam [1:0] ibex_pkg_PRIV_LVL_U = 2'b00; - localparam [3:0] ibex_pkg_XDEBUGVER_STD = 4'd4; - function automatic [1:0] sv2v_cast_2; - input reg [1:0] inp; - sv2v_cast_2 = inp; - endfunction - always @(*) begin - exception_pc = pc_id_i; - priv_lvl_d = priv_lvl_q; - mstatus_en = 1'b0; - mstatus_d = mstatus_q; - mie_en = 1'b0; - mscratch_en = 1'b0; - mepc_en = 1'b0; - mepc_d = {csr_wdata_int[31:1], 1'b0}; - mcause_en = 1'b0; - mcause_d = {csr_wdata_int[31], csr_wdata_int[4:0]}; - mtval_en = 1'b0; - mtval_d = csr_wdata_int; - mtvec_en = csr_mtvec_init_i; - mtvec_d = (csr_mtvec_init_i ? {boot_addr_i[31:8], 6'b000000, 2'b01} : {csr_wdata_int[31:8], 6'b000000, 2'b01}); - dcsr_en = 1'b0; - dcsr_d = dcsr_q; - depc_d = {csr_wdata_int[31:1], 1'b0}; - depc_en = 1'b0; - dscratch0_en = 1'b0; - dscratch1_en = 1'b0; - mstack_en = 1'b0; - mstack_d[2] = mstatus_q[4]; - mstack_d[1-:2] = mstatus_q[3-:2]; - mstack_epc_d = mepc_q; - mstack_cause_d = mcause_q; - mcountinhibit_we = 1'b0; - mhpmcounter_we = {32 {1'sb0}}; - mhpmcounterh_we = {32 {1'sb0}}; - cpuctrl_we = 1'b0; - if (csr_we_int) - case (csr_addr_i) - ibex_pkg_CSR_MSTATUS: begin - mstatus_en = 1'b1; - mstatus_d = {csr_wdata_int[ibex_pkg_CSR_MSTATUS_MIE_BIT], csr_wdata_int[ibex_pkg_CSR_MSTATUS_MPIE_BIT], sv2v_cast_2(csr_wdata_int[ibex_pkg_CSR_MSTATUS_MPP_BIT_HIGH:ibex_pkg_CSR_MSTATUS_MPP_BIT_LOW]), csr_wdata_int[ibex_pkg_CSR_MSTATUS_MPRV_BIT], csr_wdata_int[ibex_pkg_CSR_MSTATUS_TW_BIT]}; - if ((mstatus_d[3-:2] != ibex_pkg_PRIV_LVL_M) && (mstatus_d[3-:2] != ibex_pkg_PRIV_LVL_U)) - mstatus_d[3-:2] = ibex_pkg_PRIV_LVL_M; - end - ibex_pkg_CSR_MIE: mie_en = 1'b1; - ibex_pkg_CSR_MSCRATCH: mscratch_en = 1'b1; - ibex_pkg_CSR_MEPC: mepc_en = 1'b1; - ibex_pkg_CSR_MCAUSE: mcause_en = 1'b1; - ibex_pkg_CSR_MTVAL: mtval_en = 1'b1; - ibex_pkg_CSR_MTVEC: mtvec_en = 1'b1; - ibex_pkg_CSR_DCSR: begin - dcsr_d = csr_wdata_int; - dcsr_d[31-:4] = ibex_pkg_XDEBUGVER_STD; - if ((dcsr_d[1-:2] != ibex_pkg_PRIV_LVL_M) && (dcsr_d[1-:2] != ibex_pkg_PRIV_LVL_U)) - dcsr_d[1-:2] = ibex_pkg_PRIV_LVL_M; - dcsr_d[8-:3] = dcsr_q[8-:3]; - dcsr_d[3] = 1'b0; - dcsr_d[4] = 1'b0; - dcsr_d[10] = 1'b0; - dcsr_d[9] = 1'b0; - dcsr_d[5] = 1'b0; - dcsr_d[14] = 1'b0; - dcsr_d[27-:12] = 12'h000; - dcsr_en = 1'b1; - end - ibex_pkg_CSR_DPC: depc_en = 1'b1; - ibex_pkg_CSR_DSCRATCH0: dscratch0_en = 1'b1; - ibex_pkg_CSR_DSCRATCH1: dscratch1_en = 1'b1; - ibex_pkg_CSR_MCOUNTINHIBIT: mcountinhibit_we = 1'b1; - ibex_pkg_CSR_MCYCLE, ibex_pkg_CSR_MINSTRET, ibex_pkg_CSR_MHPMCOUNTER3, ibex_pkg_CSR_MHPMCOUNTER4, ibex_pkg_CSR_MHPMCOUNTER5, ibex_pkg_CSR_MHPMCOUNTER6, ibex_pkg_CSR_MHPMCOUNTER7, ibex_pkg_CSR_MHPMCOUNTER8, ibex_pkg_CSR_MHPMCOUNTER9, ibex_pkg_CSR_MHPMCOUNTER10, ibex_pkg_CSR_MHPMCOUNTER11, ibex_pkg_CSR_MHPMCOUNTER12, ibex_pkg_CSR_MHPMCOUNTER13, ibex_pkg_CSR_MHPMCOUNTER14, ibex_pkg_CSR_MHPMCOUNTER15, ibex_pkg_CSR_MHPMCOUNTER16, ibex_pkg_CSR_MHPMCOUNTER17, ibex_pkg_CSR_MHPMCOUNTER18, ibex_pkg_CSR_MHPMCOUNTER19, ibex_pkg_CSR_MHPMCOUNTER20, ibex_pkg_CSR_MHPMCOUNTER21, ibex_pkg_CSR_MHPMCOUNTER22, ibex_pkg_CSR_MHPMCOUNTER23, ibex_pkg_CSR_MHPMCOUNTER24, ibex_pkg_CSR_MHPMCOUNTER25, ibex_pkg_CSR_MHPMCOUNTER26, ibex_pkg_CSR_MHPMCOUNTER27, ibex_pkg_CSR_MHPMCOUNTER28, ibex_pkg_CSR_MHPMCOUNTER29, ibex_pkg_CSR_MHPMCOUNTER30, ibex_pkg_CSR_MHPMCOUNTER31: mhpmcounter_we[mhpmcounter_idx] = 1'b1; - ibex_pkg_CSR_MCYCLEH, ibex_pkg_CSR_MINSTRETH, ibex_pkg_CSR_MHPMCOUNTER3H, ibex_pkg_CSR_MHPMCOUNTER4H, ibex_pkg_CSR_MHPMCOUNTER5H, ibex_pkg_CSR_MHPMCOUNTER6H, ibex_pkg_CSR_MHPMCOUNTER7H, ibex_pkg_CSR_MHPMCOUNTER8H, ibex_pkg_CSR_MHPMCOUNTER9H, ibex_pkg_CSR_MHPMCOUNTER10H, ibex_pkg_CSR_MHPMCOUNTER11H, ibex_pkg_CSR_MHPMCOUNTER12H, ibex_pkg_CSR_MHPMCOUNTER13H, ibex_pkg_CSR_MHPMCOUNTER14H, ibex_pkg_CSR_MHPMCOUNTER15H, ibex_pkg_CSR_MHPMCOUNTER16H, ibex_pkg_CSR_MHPMCOUNTER17H, ibex_pkg_CSR_MHPMCOUNTER18H, ibex_pkg_CSR_MHPMCOUNTER19H, ibex_pkg_CSR_MHPMCOUNTER20H, ibex_pkg_CSR_MHPMCOUNTER21H, ibex_pkg_CSR_MHPMCOUNTER22H, ibex_pkg_CSR_MHPMCOUNTER23H, ibex_pkg_CSR_MHPMCOUNTER24H, ibex_pkg_CSR_MHPMCOUNTER25H, ibex_pkg_CSR_MHPMCOUNTER26H, ibex_pkg_CSR_MHPMCOUNTER27H, ibex_pkg_CSR_MHPMCOUNTER28H, ibex_pkg_CSR_MHPMCOUNTER29H, ibex_pkg_CSR_MHPMCOUNTER30H, ibex_pkg_CSR_MHPMCOUNTER31H: mhpmcounterh_we[mhpmcounter_idx] = 1'b1; - ibex_pkg_CSR_CPUCTRL: cpuctrl_we = 1'b1; - default: - ; - endcase - case (1'b1) - csr_save_cause_i: begin - case (1'b1) - csr_save_if_i: exception_pc = pc_if_i; - csr_save_id_i: exception_pc = pc_id_i; - csr_save_wb_i: exception_pc = pc_wb_i; - default: - ; - endcase - priv_lvl_d = ibex_pkg_PRIV_LVL_M; - if (debug_csr_save_i) begin - dcsr_d[1-:2] = priv_lvl_q; - dcsr_d[8-:3] = debug_cause_i; - dcsr_en = 1'b1; - depc_d = exception_pc; - depc_en = 1'b1; - end - else if (!debug_mode_i) begin - mtval_en = 1'b1; - mtval_d = csr_mtval_i; - mstatus_en = 1'b1; - mstatus_d[5] = 1'b0; - mstatus_d[4] = mstatus_q[5]; - mstatus_d[3-:2] = priv_lvl_q; - mepc_en = 1'b1; - mepc_d = exception_pc; - mcause_en = 1'b1; - mcause_d = {csr_mcause_i}; - mstack_en = 1'b1; - end - end - csr_restore_dret_i: priv_lvl_d = dcsr_q[1-:2]; - csr_restore_mret_i: begin - priv_lvl_d = mstatus_q[3-:2]; - mstatus_en = 1'b1; - mstatus_d[5] = mstatus_q[4]; - if (nmi_mode_i) begin - mstatus_d[4] = mstack_q[2]; - mstatus_d[3-:2] = mstack_q[1-:2]; - mepc_en = 1'b1; - mepc_d = mstack_epc_q; - mcause_en = 1'b1; - mcause_d = mstack_cause_q; - end - else begin - mstatus_d[4] = 1'b1; - mstatus_d[3-:2] = ibex_pkg_PRIV_LVL_U; - end - end - default: - ; - endcase - end - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - priv_lvl_q <= ibex_pkg_PRIV_LVL_M; - else - priv_lvl_q <= priv_lvl_d; - assign priv_mode_id_o = priv_lvl_q; - assign priv_mode_if_o = priv_lvl_d; - assign priv_mode_lsu_o = (mstatus_q[1] ? mstatus_q[3-:2] : priv_lvl_q); - localparam [1:0] ibex_pkg_CSR_OP_CLEAR = 3; - localparam [1:0] ibex_pkg_CSR_OP_READ = 0; - localparam [1:0] ibex_pkg_CSR_OP_SET = 2; - localparam [1:0] ibex_pkg_CSR_OP_WRITE = 1; - always @(*) - case (csr_op_i) - ibex_pkg_CSR_OP_WRITE: csr_wdata_int = csr_wdata_i; - ibex_pkg_CSR_OP_SET: csr_wdata_int = csr_wdata_i | csr_rdata_o; - ibex_pkg_CSR_OP_CLEAR: csr_wdata_int = ~csr_wdata_i & csr_rdata_o; - ibex_pkg_CSR_OP_READ: csr_wdata_int = csr_wdata_i; - default: csr_wdata_int = csr_wdata_i; - endcase - assign csr_wreq = csr_op_en_i & |{csr_op_i == ibex_pkg_CSR_OP_WRITE, csr_op_i == ibex_pkg_CSR_OP_SET, csr_op_i == ibex_pkg_CSR_OP_CLEAR}; - assign csr_we_int = csr_wreq & ~illegal_csr_insn_o; - assign csr_rdata_o = csr_rdata_int; - assign csr_mepc_o = mepc_q; - assign csr_depc_o = depc_q; - assign csr_mtvec_o = mtvec_q; - assign csr_mstatus_mie_o = mstatus_q[5]; - assign csr_mstatus_tw_o = mstatus_q[0]; - assign debug_single_step_o = dcsr_q[2]; - assign debug_ebreakm_o = dcsr_q[15]; - assign debug_ebreaku_o = dcsr_q[12]; - assign irqs_o = mip & mie_q; - assign irq_pending_o = |irqs_o; - localparam [5:0] MSTATUS_RST_VAL = {1'b0, 1'b1, ibex_pkg_PRIV_LVL_U, 1'b0, 1'b0}; - ibex_csr #( - .Width(6), - .ShadowCopy(ShadowCSR), - .ResetValue({MSTATUS_RST_VAL}) - ) u_mstatus_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i({mstatus_d}), - .wr_en_i(mstatus_en), - .rd_data_o(mstatus_q), - .rd_error_o(mstatus_err) - ); - ibex_csr #( - .Width(32), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_mepc_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(mepc_d), - .wr_en_i(mepc_en), - .rd_data_o(mepc_q), - .rd_error_o() - ); - assign mie_d[17] = csr_wdata_int[ibex_pkg_CSR_MSIX_BIT]; - assign mie_d[16] = csr_wdata_int[ibex_pkg_CSR_MTIX_BIT]; - assign mie_d[15] = csr_wdata_int[ibex_pkg_CSR_MEIX_BIT]; - assign mie_d[14-:15] = csr_wdata_int[ibex_pkg_CSR_MFIX_BIT_HIGH:ibex_pkg_CSR_MFIX_BIT_LOW]; - ibex_csr #( - .Width(18), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_mie_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i({mie_d}), - .wr_en_i(mie_en), - .rd_data_o(mie_q), - .rd_error_o() - ); - ibex_csr #( - .Width(32), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_mscratch_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(csr_wdata_int), - .wr_en_i(mscratch_en), - .rd_data_o(mscratch_q), - .rd_error_o() - ); - ibex_csr #( - .Width(6), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_mcause_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(mcause_d), - .wr_en_i(mcause_en), - .rd_data_o(mcause_q), - .rd_error_o() - ); - ibex_csr #( - .Width(32), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_mtval_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(mtval_d), - .wr_en_i(mtval_en), - .rd_data_o(mtval_q), - .rd_error_o() - ); - ibex_csr #( - .Width(32), - .ShadowCopy(ShadowCSR), - .ResetValue(32'd1) - ) u_mtvec_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(mtvec_d), - .wr_en_i(mtvec_en), - .rd_data_o(mtvec_q), - .rd_error_o(mtvec_err) - ); - localparam [2:0] ibex_pkg_DBG_CAUSE_NONE = 3'h0; - localparam [31:0] DCSR_RESET_VAL = {ibex_pkg_XDEBUGVER_STD, 12'b000000000000, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, ibex_pkg_DBG_CAUSE_NONE, 1'b0, 1'b0, 1'b0, 1'b0, ibex_pkg_PRIV_LVL_M}; - ibex_csr #( - .Width(32), - .ShadowCopy(1'b0), - .ResetValue({DCSR_RESET_VAL}) - ) u_dcsr_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i({dcsr_d}), - .wr_en_i(dcsr_en), - .rd_data_o(dcsr_q), - .rd_error_o() - ); - ibex_csr #( - .Width(32), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_depc_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(depc_d), - .wr_en_i(depc_en), - .rd_data_o(depc_q), - .rd_error_o() - ); - ibex_csr #( - .Width(32), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_dscratch0_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(csr_wdata_int), - .wr_en_i(dscratch0_en), - .rd_data_o(dscratch0_q), - .rd_error_o() - ); - ibex_csr #( - .Width(32), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_dscratch1_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(csr_wdata_int), - .wr_en_i(dscratch1_en), - .rd_data_o(dscratch1_q), - .rd_error_o() - ); - localparam [2:0] MSTACK_RESET_VAL = {1'b1, ibex_pkg_PRIV_LVL_U}; - ibex_csr #( - .Width(3), - .ShadowCopy(1'b0), - .ResetValue({MSTACK_RESET_VAL}) - ) u_mstack_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i({mstack_d}), - .wr_en_i(mstack_en), - .rd_data_o(mstack_q), - .rd_error_o() - ); - ibex_csr #( - .Width(32), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_mstack_epc_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(mstack_epc_d), - .wr_en_i(mstack_en), - .rd_data_o(mstack_epc_q), - .rd_error_o() - ); - ibex_csr #( - .Width(6), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_mstack_cause_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(mstack_cause_d), - .wr_en_i(mstack_en), - .rd_data_o(mstack_cause_q), - .rd_error_o() - ); - localparam [11:0] ibex_pkg_CSR_OFF_PMP_ADDR = 12'h3b0; - localparam [11:0] ibex_pkg_CSR_OFF_PMP_CFG = 12'h3a0; - localparam [1:0] ibex_pkg_PMP_MODE_NA4 = 2'b10; - localparam [1:0] ibex_pkg_PMP_MODE_NAPOT = 2'b11; - localparam [1:0] ibex_pkg_PMP_MODE_OFF = 2'b00; - localparam [1:0] ibex_pkg_PMP_MODE_TOR = 2'b01; - generate - if (PMPEnable) begin : g_pmp_registers - wire [5:0] pmp_cfg [0:PMPNumRegions - 1]; - reg [5:0] pmp_cfg_wdata [0:PMPNumRegions - 1]; - wire [PMPAddrWidth - 1:0] pmp_addr [0:PMPNumRegions - 1]; - wire [PMPNumRegions - 1:0] pmp_cfg_we; - wire [PMPNumRegions - 1:0] pmp_cfg_err; - wire [PMPNumRegions - 1:0] pmp_addr_we; - wire [PMPNumRegions - 1:0] pmp_addr_err; - genvar i; - for (i = 0; i < ibex_pkg_PMP_MAX_REGIONS; i = i + 1) begin : g_exp_rd_data - if (i < PMPNumRegions) begin : g_implemented_regions - assign pmp_cfg_rdata[i] = {pmp_cfg[i][5], 2'b00, pmp_cfg[i][4-:2], pmp_cfg[i][2], pmp_cfg[i][1], pmp_cfg[i][0]}; - if (PMPGranularity == 0) begin : g_pmp_g0 - wire [PMPAddrWidth:1] sv2v_tmp_D3A6A; - assign sv2v_tmp_D3A6A = pmp_addr[i]; - always @(*) pmp_addr_rdata[i] = sv2v_tmp_D3A6A; - end - else if (PMPGranularity == 1) begin : g_pmp_g1 - always @(*) begin - pmp_addr_rdata[i] = pmp_addr[i]; - if ((pmp_cfg[i][4-:2] == ibex_pkg_PMP_MODE_OFF) || (pmp_cfg[i][4-:2] == ibex_pkg_PMP_MODE_TOR)) - pmp_addr_rdata[i][PMPGranularity - 1:0] = {PMPGranularity {1'sb0}}; - end - end - else begin : g_pmp_g2 - always @(*) begin - pmp_addr_rdata[i] = {pmp_addr[i], {PMPGranularity - 1 {1'b1}}}; - if ((pmp_cfg[i][4-:2] == ibex_pkg_PMP_MODE_OFF) || (pmp_cfg[i][4-:2] == ibex_pkg_PMP_MODE_TOR)) - pmp_addr_rdata[i][PMPGranularity - 1:0] = {PMPGranularity {1'sb0}}; - end - end - end - else begin : g_other_regions - assign pmp_cfg_rdata[i] = {ibex_pkg_PMP_CFG_W {1'sb0}}; - wire [32:1] sv2v_tmp_313D8; - assign sv2v_tmp_313D8 = {32 {1'sb0}}; - always @(*) pmp_addr_rdata[i] = sv2v_tmp_313D8; - end - end - for (i = 0; i < PMPNumRegions; i = i + 1) begin : g_pmp_csrs - assign pmp_cfg_we[i] = (csr_we_int & ~pmp_cfg[i][5]) & (csr_addr == (ibex_pkg_CSR_OFF_PMP_CFG + (i[11:0] >> 2))); - wire [1:1] sv2v_tmp_12AC7; - assign sv2v_tmp_12AC7 = csr_wdata_int[((i % 4) * ibex_pkg_PMP_CFG_W) + 7]; - always @(*) pmp_cfg_wdata[i][5] = sv2v_tmp_12AC7; - always @(*) - case (csr_wdata_int[((i % 4) * ibex_pkg_PMP_CFG_W) + 3+:2]) - 2'b00: pmp_cfg_wdata[i][4-:2] = ibex_pkg_PMP_MODE_OFF; - 2'b01: pmp_cfg_wdata[i][4-:2] = ibex_pkg_PMP_MODE_TOR; - 2'b10: pmp_cfg_wdata[i][4-:2] = (PMPGranularity == 0 ? ibex_pkg_PMP_MODE_NA4 : ibex_pkg_PMP_MODE_OFF); - 2'b11: pmp_cfg_wdata[i][4-:2] = ibex_pkg_PMP_MODE_NAPOT; - default: pmp_cfg_wdata[i][4-:2] = ibex_pkg_PMP_MODE_OFF; - endcase - wire [1:1] sv2v_tmp_B1072; - assign sv2v_tmp_B1072 = csr_wdata_int[((i % 4) * ibex_pkg_PMP_CFG_W) + 2]; - always @(*) pmp_cfg_wdata[i][2] = sv2v_tmp_B1072; - wire [1:1] sv2v_tmp_CFE62; - assign sv2v_tmp_CFE62 = &csr_wdata_int[(i % 4) * ibex_pkg_PMP_CFG_W+:2]; - always @(*) pmp_cfg_wdata[i][1] = sv2v_tmp_CFE62; - wire [1:1] sv2v_tmp_FD795; - assign sv2v_tmp_FD795 = csr_wdata_int[(i % 4) * ibex_pkg_PMP_CFG_W]; - always @(*) pmp_cfg_wdata[i][0] = sv2v_tmp_FD795; - ibex_csr #( - .Width(6), - .ShadowCopy(ShadowCSR), - .ResetValue('0) - ) u_pmp_cfg_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i({pmp_cfg_wdata[i]}), - .wr_en_i(pmp_cfg_we[i]), - .rd_data_o(pmp_cfg[i]), - .rd_error_o(pmp_cfg_err[i]) - ); - if (i < (PMPNumRegions - 1)) begin : g_lower - assign pmp_addr_we[i] = ((csr_we_int & ~pmp_cfg[i][5]) & (~pmp_cfg[i + 1][5] | (pmp_cfg[i + 1][4-:2] != ibex_pkg_PMP_MODE_TOR))) & (csr_addr == (ibex_pkg_CSR_OFF_PMP_ADDR + i[11:0])); - end - else begin : g_upper - assign pmp_addr_we[i] = (csr_we_int & ~pmp_cfg[i][5]) & (csr_addr == (ibex_pkg_CSR_OFF_PMP_ADDR + i[11:0])); - end - ibex_csr #( - .Width(PMPAddrWidth), - .ShadowCopy(ShadowCSR), - .ResetValue('0) - ) u_pmp_addr_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(csr_wdata_int[31-:PMPAddrWidth]), - .wr_en_i(pmp_addr_we[i]), - .rd_data_o(pmp_addr[i]), - .rd_error_o(pmp_addr_err[i]) - ); - assign csr_pmp_cfg_o[(0 >= (PMPNumRegions - 1) ? i : (PMPNumRegions - 1) - i) * 6+:6] = pmp_cfg[i]; - assign csr_pmp_addr_o[(0 >= (PMPNumRegions - 1) ? i : (PMPNumRegions - 1) - i) * 34+:34] = {pmp_addr_rdata[i], 2'b00}; - end - assign pmp_csr_err = |pmp_cfg_err | |pmp_addr_err; - end - else begin : g_no_pmp_tieoffs - genvar i; - for (i = 0; i < ibex_pkg_PMP_MAX_REGIONS; i = i + 1) begin : g_rdata - wire [32:1] sv2v_tmp_313D8; - assign sv2v_tmp_313D8 = {32 {1'sb0}}; - always @(*) pmp_addr_rdata[i] = sv2v_tmp_313D8; - assign pmp_cfg_rdata[i] = {ibex_pkg_PMP_CFG_W {1'sb0}}; - end - for (i = 0; i < PMPNumRegions; i = i + 1) begin : g_outputs - function automatic [5:0] sv2v_cast_6; - input reg [5:0] inp; - sv2v_cast_6 = inp; - endfunction - assign csr_pmp_cfg_o[(0 >= (PMPNumRegions - 1) ? i : (PMPNumRegions - 1) - i) * 6+:6] = sv2v_cast_6(1'b0); - assign csr_pmp_addr_o[(0 >= (PMPNumRegions - 1) ? i : (PMPNumRegions - 1) - i) * 34+:34] = {34 {1'sb0}}; - end - assign pmp_csr_err = 1'b0; - end - endgenerate - always @(*) begin : mcountinhibit_update - if (mcountinhibit_we == 1'b1) - mcountinhibit_d = {csr_wdata_int[MHPMCounterNum + 2:2], 1'b0, csr_wdata_int[0]}; - else - mcountinhibit_d = mcountinhibit_q; - end - always @(*) begin : gen_mhpmcounter_incr - begin : sv2v_autoblock_7 - reg [31:0] i; - for (i = 0; i < 32; i = i + 1) - begin : gen_mhpmcounter_incr_inactive - mhpmcounter_incr[i] = 1'b0; - end - end - mhpmcounter_incr[0] = 1'b1; - mhpmcounter_incr[1] = 1'b0; - mhpmcounter_incr[2] = instr_ret_i; - mhpmcounter_incr[3] = dside_wait_i; - mhpmcounter_incr[4] = iside_wait_i; - mhpmcounter_incr[5] = mem_load_i; - mhpmcounter_incr[6] = mem_store_i; - mhpmcounter_incr[7] = jump_i; - mhpmcounter_incr[8] = branch_i; - mhpmcounter_incr[9] = branch_taken_i; - mhpmcounter_incr[10] = instr_ret_compressed_i; - mhpmcounter_incr[11] = mul_wait_i; - mhpmcounter_incr[12] = div_wait_i; - end - always @(*) begin : gen_mhpmevent - begin : sv2v_autoblock_8 - reg signed [31:0] i; - for (i = 0; i < 32; i = i + 1) - begin : gen_mhpmevent_active - mhpmevent[i] = {32 {1'sb0}}; - mhpmevent[i][i] = 1'b1; - end - end - mhpmevent[1] = {32 {1'sb0}}; - begin : sv2v_autoblock_9 - reg [31:0] i; - for (i = 3 + MHPMCounterNum; i < 32; i = i + 1) - begin : gen_mhpmevent_inactive - mhpmevent[i] = {32 {1'sb0}}; - end - end - end - ibex_counter #(.CounterWidth(64)) mcycle_counter_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .counter_inc_i(mhpmcounter_incr[0] & ~mcountinhibit[0]), - .counterh_we_i(mhpmcounterh_we[0]), - .counter_we_i(mhpmcounter_we[0]), - .counter_val_i(csr_wdata_int), - .counter_val_o(mhpmcounter[0]) - ); - ibex_counter #(.CounterWidth(64)) minstret_counter_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .counter_inc_i(mhpmcounter_incr[2] & ~mcountinhibit[2]), - .counterh_we_i(mhpmcounterh_we[2]), - .counter_we_i(mhpmcounter_we[2]), - .counter_val_i(csr_wdata_int), - .counter_val_o(mhpmcounter[2]) - ); - assign mhpmcounter[1] = {64 {1'sb0}}; - assign unused_mhpmcounter_we_1 = mhpmcounter_we[1]; - assign unused_mhpmcounterh_we_1 = mhpmcounterh_we[1]; - assign unused_mhpmcounter_incr_1 = mhpmcounter_incr[1]; - generate - genvar cnt; - for (cnt = 0; cnt < 29; cnt = cnt + 1) begin : gen_cntrs - if (cnt < MHPMCounterNum) begin : gen_imp - ibex_counter #(.CounterWidth(MHPMCounterWidth)) mcounters_variable_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .counter_inc_i(mhpmcounter_incr[cnt + 3] & ~mcountinhibit[cnt + 3]), - .counterh_we_i(mhpmcounterh_we[cnt + 3]), - .counter_we_i(mhpmcounter_we[cnt + 3]), - .counter_val_i(csr_wdata_int), - .counter_val_o(mhpmcounter[cnt + 3]) - ); - end - else begin : gen_unimp - assign mhpmcounter[cnt + 3] = {64 {1'sb0}}; - end - end - endgenerate - generate - if (MHPMCounterNum < 29) begin : g_mcountinhibit_reduced - wire [(29 - MHPMCounterNum) - 1:0] unused_mhphcounter_we; - wire [(29 - MHPMCounterNum) - 1:0] unused_mhphcounterh_we; - wire [(29 - MHPMCounterNum) - 1:0] unused_mhphcounter_incr; - assign mcountinhibit = {{29 - MHPMCounterNum {1'b1}}, mcountinhibit_q}; - assign unused_mhphcounter_we = mhpmcounter_we[31:MHPMCounterNum + 3]; - assign unused_mhphcounterh_we = mhpmcounterh_we[31:MHPMCounterNum + 3]; - assign unused_mhphcounter_incr = mhpmcounter_incr[31:MHPMCounterNum + 3]; - end - else begin : g_mcountinhibit_full - assign mcountinhibit = mcountinhibit_q; - end - endgenerate - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - mcountinhibit_q <= {((MHPMCounterNum + 2) >= 0 ? MHPMCounterNum + 3 : 1 - (MHPMCounterNum + 2)) {1'sb0}}; - else - mcountinhibit_q <= mcountinhibit_d; - generate - if (DbgTriggerEn) begin : gen_trigger_regs - localparam [31:0] DbgHwNumLen = (DbgHwBreakNum > 1 ? $clog2(DbgHwBreakNum) : 1); - wire [DbgHwNumLen - 1:0] tselect_d; - wire [DbgHwNumLen - 1:0] tselect_q; - wire tmatch_control_d; - wire [DbgHwBreakNum - 1:0] tmatch_control_q; - wire [31:0] tmatch_value_d; - wire [31:0] tmatch_value_q [0:DbgHwBreakNum - 1]; - wire tselect_we; - wire [DbgHwBreakNum - 1:0] tmatch_control_we; - wire [DbgHwBreakNum - 1:0] tmatch_value_we; - wire [DbgHwBreakNum - 1:0] trigger_match; - assign tselect_we = (csr_we_int & debug_mode_i) & (csr_addr_i == ibex_pkg_CSR_TSELECT); - genvar i; - for (i = 0; i < DbgHwBreakNum; i = i + 1) begin : g_dbg_tmatch_we - assign tmatch_control_we[i] = (((i[DbgHwNumLen - 1:0] == tselect_q) & csr_we_int) & debug_mode_i) & (csr_addr_i == ibex_pkg_CSR_TDATA1); - assign tmatch_value_we[i] = (((i[DbgHwNumLen - 1:0] == tselect_q) & csr_we_int) & debug_mode_i) & (csr_addr_i == ibex_pkg_CSR_TDATA2); - end - assign tselect_d = (csr_wdata_int < DbgHwBreakNum ? csr_wdata_int[DbgHwNumLen - 1:0] : DbgHwBreakNum - 1); - assign tmatch_control_d = csr_wdata_int[2]; - assign tmatch_value_d = csr_wdata_int[31:0]; - ibex_csr #( - .Width(DbgHwNumLen), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_tselect_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(tselect_d), - .wr_en_i(tselect_we), - .rd_data_o(tselect_q), - .rd_error_o() - ); - for (i = 0; i < DbgHwBreakNum; i = i + 1) begin : g_dbg_tmatch_reg - ibex_csr #( - .Width(1), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_tmatch_control_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(tmatch_control_d), - .wr_en_i(tmatch_control_we[i]), - .rd_data_o(tmatch_control_q[i]), - .rd_error_o() - ); - ibex_csr #( - .Width(32), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_tmatch_value_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(tmatch_value_d), - .wr_en_i(tmatch_value_we[i]), - .rd_data_o(tmatch_value_q[i]), - .rd_error_o() - ); - end - localparam [31:0] TSelectRdataPadlen = (DbgHwNumLen >= 32 ? 0 : 32 - DbgHwNumLen); - assign tselect_rdata = {{TSelectRdataPadlen {1'b0}}, tselect_q}; - assign tmatch_control_rdata = {4'h2, 1'b1, 6'h00, 1'b0, 1'b0, 1'b0, 2'b00, 4'h1, 1'b0, 4'h0, 1'b1, 1'b0, 1'b0, 1'b1, tmatch_control_q[tselect_q], 1'b0, 1'b0}; - assign tmatch_value_rdata = tmatch_value_q[tselect_q]; - for (i = 0; i < DbgHwBreakNum; i = i + 1) begin : g_dbg_trigger_match - assign trigger_match[i] = tmatch_control_q[i] & (pc_if_i[31:0] == tmatch_value_q[i]); - end - assign trigger_match_o = |trigger_match; - end - else begin : gen_no_trigger_regs - assign tselect_rdata = 'b0; - assign tmatch_control_rdata = 'b0; - assign tmatch_value_rdata = 'b0; - assign trigger_match_o = 'b0; - end - endgenerate - assign cpuctrl_wdata = csr_wdata_int[5:0]; - generate - if (DataIndTiming) begin : gen_dit - assign cpuctrl_d[1] = cpuctrl_wdata[1]; - end - else begin : gen_no_dit - wire unused_dit; - assign unused_dit = cpuctrl_wdata[1]; - assign cpuctrl_d[1] = 1'b0; - end - endgenerate - assign data_ind_timing_o = cpuctrl_q[1]; - generate - if (DummyInstructions) begin : gen_dummy - assign cpuctrl_d[2] = cpuctrl_wdata[2]; - assign cpuctrl_d[5-:3] = cpuctrl_wdata[5-:3]; - assign dummy_instr_seed_en_o = csr_we_int && (csr_addr == ibex_pkg_CSR_SECURESEED); - assign dummy_instr_seed_o = csr_wdata_int; - end - else begin : gen_no_dummy - wire unused_dummy_en; - wire [2:0] unused_dummy_mask; - assign unused_dummy_en = cpuctrl_wdata[2]; - assign unused_dummy_mask = cpuctrl_wdata[5-:3]; - assign cpuctrl_d[2] = 1'b0; - assign cpuctrl_d[5-:3] = 3'b000; - assign dummy_instr_seed_en_o = 1'b0; - assign dummy_instr_seed_o = {32 {1'sb0}}; - end - endgenerate - assign dummy_instr_en_o = cpuctrl_q[2]; - assign dummy_instr_mask_o = cpuctrl_q[5-:3]; - generate - if (ICache) begin : gen_icache_enable - assign cpuctrl_d[0] = cpuctrl_wdata[0]; - end - else begin : gen_no_icache - wire unused_icen; - assign unused_icen = cpuctrl_wdata[0]; - assign cpuctrl_d[0] = 1'b0; - end - endgenerate - assign icache_enable_o = cpuctrl_q[0]; - ibex_csr #( - .Width(6), - .ShadowCopy(ShadowCSR), - .ResetValue('0) - ) u_cpuctrl_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i({cpuctrl_d}), - .wr_en_i(cpuctrl_we), - .rd_data_o(cpuctrl_q), - .rd_error_o(cpuctrl_err) - ); - assign csr_shadow_err_o = ((mstatus_err | mtvec_err) | pmp_csr_err) | cpuctrl_err; -endmodule diff --git a/flow/designs/src/ibex/ibex_csr.v b/flow/designs/src/ibex/ibex_csr.v deleted file mode 100644 index edae878e0c..0000000000 --- a/flow/designs/src/ibex/ibex_csr.v +++ /dev/null @@ -1,39 +0,0 @@ -module ibex_csr ( - clk_i, - rst_ni, - wr_data_i, - wr_en_i, - rd_data_o, - rd_error_o -); - parameter [31:0] Width = 32; - parameter [0:0] ShadowCopy = 1'b0; - parameter [Width - 1:0] ResetValue = 1'sb0; - input wire clk_i; - input wire rst_ni; - input wire [Width - 1:0] wr_data_i; - input wire wr_en_i; - output wire [Width - 1:0] rd_data_o; - output wire rd_error_o; - reg [Width - 1:0] rdata_q; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - rdata_q <= ResetValue; - else if (wr_en_i) - rdata_q <= wr_data_i; - assign rd_data_o = rdata_q; - generate - if (ShadowCopy) begin : gen_shadow - reg [Width - 1:0] shadow_q; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - shadow_q <= ~ResetValue; - else if (wr_en_i) - shadow_q <= ~wr_data_i; - assign rd_error_o = rdata_q != ~shadow_q; - end - else begin : gen_no_shadow - assign rd_error_o = 1'b0; - end - endgenerate -endmodule diff --git a/flow/designs/src/ibex/ibex_decoder.v b/flow/designs/src/ibex/ibex_decoder.v deleted file mode 100644 index b41d5f0bf2..0000000000 --- a/flow/designs/src/ibex/ibex_decoder.v +++ /dev/null @@ -1,948 +0,0 @@ -module ibex_decoder ( - clk_i, - rst_ni, - illegal_insn_o, - ebrk_insn_o, - mret_insn_o, - dret_insn_o, - ecall_insn_o, - wfi_insn_o, - jump_set_o, - branch_taken_i, - icache_inval_o, - instr_first_cycle_i, - instr_rdata_i, - instr_rdata_alu_i, - illegal_c_insn_i, - imm_a_mux_sel_o, - imm_b_mux_sel_o, - bt_a_mux_sel_o, - bt_b_mux_sel_o, - imm_i_type_o, - imm_s_type_o, - imm_b_type_o, - imm_u_type_o, - imm_j_type_o, - zimm_rs1_type_o, - rf_wdata_sel_o, - rf_we_o, - rf_raddr_a_o, - rf_raddr_b_o, - rf_waddr_o, - rf_ren_a_o, - rf_ren_b_o, - alu_operator_o, - alu_op_a_mux_sel_o, - alu_op_b_mux_sel_o, - alu_multicycle_o, - mult_en_o, - div_en_o, - mult_sel_o, - div_sel_o, - multdiv_operator_o, - multdiv_signed_mode_o, - csr_access_o, - csr_op_o, - data_req_o, - data_we_o, - data_type_o, - data_sign_extension_o, - jump_in_dec_o, - branch_in_dec_o -); - parameter [0:0] RV32E = 0; - localparam integer ibex_pkg_RV32MFast = 2; - parameter integer RV32M = ibex_pkg_RV32MFast; - localparam integer ibex_pkg_RV32BNone = 0; - parameter integer RV32B = ibex_pkg_RV32BNone; - parameter [0:0] BranchTargetALU = 0; - input wire clk_i; - input wire rst_ni; - output wire illegal_insn_o; - output reg ebrk_insn_o; - output reg mret_insn_o; - output reg dret_insn_o; - output reg ecall_insn_o; - output reg wfi_insn_o; - output reg jump_set_o; - input wire branch_taken_i; - output reg icache_inval_o; - input wire instr_first_cycle_i; - input wire [31:0] instr_rdata_i; - input wire [31:0] instr_rdata_alu_i; - input wire illegal_c_insn_i; - output reg imm_a_mux_sel_o; - output reg [2:0] imm_b_mux_sel_o; - output reg [1:0] bt_a_mux_sel_o; - output reg [2:0] bt_b_mux_sel_o; - output wire [31:0] imm_i_type_o; - output wire [31:0] imm_s_type_o; - output wire [31:0] imm_b_type_o; - output wire [31:0] imm_u_type_o; - output wire [31:0] imm_j_type_o; - output wire [31:0] zimm_rs1_type_o; - output reg rf_wdata_sel_o; - output wire rf_we_o; - output wire [4:0] rf_raddr_a_o; - output wire [4:0] rf_raddr_b_o; - output wire [4:0] rf_waddr_o; - output reg rf_ren_a_o; - output reg rf_ren_b_o; - output reg [5:0] alu_operator_o; - output reg [1:0] alu_op_a_mux_sel_o; - output reg alu_op_b_mux_sel_o; - output reg alu_multicycle_o; - output wire mult_en_o; - output wire div_en_o; - output reg mult_sel_o; - output reg div_sel_o; - output reg [1:0] multdiv_operator_o; - output reg [1:0] multdiv_signed_mode_o; - output reg csr_access_o; - output reg [1:0] csr_op_o; - output reg data_req_o; - output reg data_we_o; - output reg [1:0] data_type_o; - output reg data_sign_extension_o; - output reg jump_in_dec_o; - output reg branch_in_dec_o; - reg illegal_insn; - wire illegal_reg_rv32e; - reg csr_illegal; - reg rf_we; - wire [31:0] instr; - wire [31:0] instr_alu; - wire [9:0] unused_instr_alu; - wire [4:0] instr_rs1; - wire [4:0] instr_rs2; - wire [4:0] instr_rs3; - wire [4:0] instr_rd; - reg use_rs3_d; - reg use_rs3_q; - reg [1:0] csr_op; - reg [6:0] opcode; - reg [6:0] opcode_alu; - assign instr = instr_rdata_i; - assign instr_alu = instr_rdata_alu_i; - assign imm_i_type_o = {{20 {instr[31]}}, instr[31:20]}; - assign imm_s_type_o = {{20 {instr[31]}}, instr[31:25], instr[11:7]}; - assign imm_b_type_o = {{19 {instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0}; - assign imm_u_type_o = {instr[31:12], 12'b000000000000}; - assign imm_j_type_o = {{12 {instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0}; - assign zimm_rs1_type_o = {27'b000000000000000000000000000, instr_rs1}; - generate - if (RV32B != ibex_pkg_RV32BNone) begin : gen_rs3_flop - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - use_rs3_q <= 1'b0; - else - use_rs3_q <= use_rs3_d; - end - else begin : gen_no_rs3_flop - wire [1:1] sv2v_tmp_66FD5; - assign sv2v_tmp_66FD5 = use_rs3_d; - always @(*) use_rs3_q = sv2v_tmp_66FD5; - end - endgenerate - assign instr_rs1 = instr[19:15]; - assign instr_rs2 = instr[24:20]; - assign instr_rs3 = instr[31:27]; - assign rf_raddr_a_o = (use_rs3_q & ~instr_first_cycle_i ? instr_rs3 : instr_rs1); - assign rf_raddr_b_o = instr_rs2; - assign instr_rd = instr[11:7]; - assign rf_waddr_o = instr_rd; - localparam [1:0] ibex_pkg_OP_A_REG_A = 0; - localparam [0:0] ibex_pkg_OP_B_REG_B = 0; - generate - if (RV32E) begin : gen_rv32e_reg_check_active - assign illegal_reg_rv32e = ((rf_raddr_a_o[4] & (alu_op_a_mux_sel_o == ibex_pkg_OP_A_REG_A)) | (rf_raddr_b_o[4] & (alu_op_b_mux_sel_o == ibex_pkg_OP_B_REG_B))) | (rf_waddr_o[4] & rf_we); - end - else begin : gen_rv32e_reg_check_inactive - assign illegal_reg_rv32e = 1'b0; - end - endgenerate - localparam [1:0] ibex_pkg_CSR_OP_CLEAR = 3; - localparam [1:0] ibex_pkg_CSR_OP_READ = 0; - localparam [1:0] ibex_pkg_CSR_OP_SET = 2; - always @(*) begin : csr_operand_check - csr_op_o = csr_op; - if (((csr_op == ibex_pkg_CSR_OP_SET) || (csr_op == ibex_pkg_CSR_OP_CLEAR)) && (instr_rs1 == {5 {1'sb0}})) - csr_op_o = ibex_pkg_CSR_OP_READ; - end - localparam [1:0] ibex_pkg_CSR_OP_WRITE = 1; - localparam [1:0] ibex_pkg_MD_OP_DIV = 2; - localparam [1:0] ibex_pkg_MD_OP_MULH = 1; - localparam [1:0] ibex_pkg_MD_OP_MULL = 0; - localparam [1:0] ibex_pkg_MD_OP_REM = 3; - localparam [6:0] ibex_pkg_OPCODE_AUIPC = 7'h17; - localparam [6:0] ibex_pkg_OPCODE_BRANCH = 7'h63; - localparam [6:0] ibex_pkg_OPCODE_JAL = 7'h6f; - localparam [6:0] ibex_pkg_OPCODE_JALR = 7'h67; - localparam [6:0] ibex_pkg_OPCODE_LOAD = 7'h03; - localparam [6:0] ibex_pkg_OPCODE_LUI = 7'h37; - localparam [6:0] ibex_pkg_OPCODE_MISC_MEM = 7'h0f; - localparam [6:0] ibex_pkg_OPCODE_OP = 7'h33; - localparam [6:0] ibex_pkg_OPCODE_OP_IMM = 7'h13; - localparam [6:0] ibex_pkg_OPCODE_STORE = 7'h23; - localparam [6:0] ibex_pkg_OPCODE_SYSTEM = 7'h73; - localparam [0:0] ibex_pkg_RF_WD_CSR = 1; - localparam [0:0] ibex_pkg_RF_WD_EX = 0; - localparam integer ibex_pkg_RV32BBalanced = 1; - localparam integer ibex_pkg_RV32BFull = 2; - localparam integer ibex_pkg_RV32MNone = 0; - always @(*) begin - jump_in_dec_o = 1'b0; - jump_set_o = 1'b0; - branch_in_dec_o = 1'b0; - icache_inval_o = 1'b0; - multdiv_operator_o = ibex_pkg_MD_OP_MULL; - multdiv_signed_mode_o = 2'b00; - rf_wdata_sel_o = ibex_pkg_RF_WD_EX; - rf_we = 1'b0; - rf_ren_a_o = 1'b0; - rf_ren_b_o = 1'b0; - csr_access_o = 1'b0; - csr_illegal = 1'b0; - csr_op = ibex_pkg_CSR_OP_READ; - data_we_o = 1'b0; - data_type_o = 2'b00; - data_sign_extension_o = 1'b0; - data_req_o = 1'b0; - illegal_insn = 1'b0; - ebrk_insn_o = 1'b0; - mret_insn_o = 1'b0; - dret_insn_o = 1'b0; - ecall_insn_o = 1'b0; - wfi_insn_o = 1'b0; - opcode = instr[6:0]; - case (opcode) - ibex_pkg_OPCODE_JAL: begin - jump_in_dec_o = 1'b1; - if (instr_first_cycle_i) begin - rf_we = BranchTargetALU; - jump_set_o = 1'b1; - end - else - rf_we = 1'b1; - end - ibex_pkg_OPCODE_JALR: begin - jump_in_dec_o = 1'b1; - if (instr_first_cycle_i) begin - rf_we = BranchTargetALU; - jump_set_o = 1'b1; - end - else - rf_we = 1'b1; - if (instr[14:12] != 3'b000) - illegal_insn = 1'b1; - rf_ren_a_o = 1'b1; - end - ibex_pkg_OPCODE_BRANCH: begin - branch_in_dec_o = 1'b1; - case (instr[14:12]) - 3'b000, 3'b001, 3'b100, 3'b101, 3'b110, 3'b111: illegal_insn = 1'b0; - default: illegal_insn = 1'b1; - endcase - rf_ren_a_o = 1'b1; - rf_ren_b_o = 1'b1; - end - ibex_pkg_OPCODE_STORE: begin - rf_ren_a_o = 1'b1; - rf_ren_b_o = 1'b1; - data_req_o = 1'b1; - data_we_o = 1'b1; - if (instr[14]) - illegal_insn = 1'b1; - case (instr[13:12]) - 2'b00: data_type_o = 2'b10; - 2'b01: data_type_o = 2'b01; - 2'b10: data_type_o = 2'b00; - default: illegal_insn = 1'b1; - endcase - end - ibex_pkg_OPCODE_LOAD: begin - rf_ren_a_o = 1'b1; - data_req_o = 1'b1; - data_type_o = 2'b00; - data_sign_extension_o = ~instr[14]; - case (instr[13:12]) - 2'b00: data_type_o = 2'b10; - 2'b01: data_type_o = 2'b01; - 2'b10: begin - data_type_o = 2'b00; - if (instr[14]) - illegal_insn = 1'b1; - end - default: illegal_insn = 1'b1; - endcase - end - ibex_pkg_OPCODE_LUI: rf_we = 1'b1; - ibex_pkg_OPCODE_AUIPC: rf_we = 1'b1; - ibex_pkg_OPCODE_OP_IMM: begin - rf_ren_a_o = 1'b1; - rf_we = 1'b1; - case (instr[14:12]) - 3'b000, 3'b010, 3'b011, 3'b100, 3'b110, 3'b111: illegal_insn = 1'b0; - 3'b001: - case (instr[31:27]) - 5'b00000: illegal_insn = (instr[26:25] == 2'b00 ? 1'b0 : 1'b1); - 5'b00100, 5'b01001, 5'b00101, 5'b01101: illegal_insn = (RV32B != ibex_pkg_RV32BNone ? 1'b0 : 1'b1); - 5'b00001: - if (instr[26] == 1'b0) - illegal_insn = (RV32B == ibex_pkg_RV32BFull ? 1'b0 : 1'b1); - else - illegal_insn = 1'b1; - 5'b01100: - case (instr[26:20]) - 7'b0000000, 7'b0000001, 7'b0000010, 7'b0000100, 7'b0000101: illegal_insn = (RV32B != ibex_pkg_RV32BNone ? 1'b0 : 1'b1); - 7'b0010000, 7'b0010001, 7'b0010010, 7'b0011000, 7'b0011001, 7'b0011010: illegal_insn = (RV32B == ibex_pkg_RV32BFull ? 1'b0 : 1'b1); - default: illegal_insn = 1'b1; - endcase - default: illegal_insn = 1'b1; - endcase - 3'b101: - if (instr[26]) - illegal_insn = (RV32B != ibex_pkg_RV32BNone ? 1'b0 : 1'b1); - else - case (instr[31:27]) - 5'b00000, 5'b01000: illegal_insn = (instr[26:25] == 2'b00 ? 1'b0 : 1'b1); - 5'b00100, 5'b01100, 5'b01001: illegal_insn = (RV32B != ibex_pkg_RV32BNone ? 1'b0 : 1'b1); - 5'b01101: - if (RV32B == ibex_pkg_RV32BFull) - illegal_insn = 1'b0; - else - case (instr[24:20]) - 5'b11111, 5'b11000: illegal_insn = (RV32B == ibex_pkg_RV32BBalanced ? 1'b0 : 1'b1); - default: illegal_insn = 1'b1; - endcase - 5'b00101: - if (RV32B == ibex_pkg_RV32BFull) - illegal_insn = 1'b0; - else if (instr[24:20] == 5'b00111) - illegal_insn = (RV32B == ibex_pkg_RV32BBalanced ? 1'b0 : 1'b1); - else - illegal_insn = 1'b1; - 5'b00001: - if (instr[26] == 1'b0) - illegal_insn = (RV32B == ibex_pkg_RV32BFull ? 1'b0 : 1'b1); - else - illegal_insn = 1'b1; - default: illegal_insn = 1'b1; - endcase - default: illegal_insn = 1'b1; - endcase - end - ibex_pkg_OPCODE_OP: begin - rf_ren_a_o = 1'b1; - rf_ren_b_o = 1'b1; - rf_we = 1'b1; - if ({instr[26], instr[13:12]} == {1'b1, 2'b01}) - illegal_insn = (RV32B != ibex_pkg_RV32BNone ? 1'b0 : 1'b1); - else - case ({instr[31:25], instr[14:12]}) - {7'b0000000, 3'b000}, {7'b0100000, 3'b000}, {7'b0000000, 3'b010}, {7'b0000000, 3'b011}, {7'b0000000, 3'b100}, {7'b0000000, 3'b110}, {7'b0000000, 3'b111}, {7'b0000000, 3'b001}, {7'b0000000, 3'b101}, {7'b0100000, 3'b101}: illegal_insn = 1'b0; - {7'b0100000, 3'b111}, {7'b0100000, 3'b110}, {7'b0100000, 3'b100}, {7'b0010000, 3'b001}, {7'b0010000, 3'b101}, {7'b0110000, 3'b001}, {7'b0110000, 3'b101}, {7'b0000101, 3'b100}, {7'b0000101, 3'b101}, {7'b0000101, 3'b110}, {7'b0000101, 3'b111}, {7'b0000100, 3'b100}, {7'b0100100, 3'b100}, {7'b0000100, 3'b111}, {7'b0100100, 3'b001}, {7'b0010100, 3'b001}, {7'b0110100, 3'b001}, {7'b0100100, 3'b101}, {7'b0100100, 3'b111}: illegal_insn = (RV32B != ibex_pkg_RV32BNone ? 1'b0 : 1'b1); - {7'b0100100, 3'b110}, {7'b0000100, 3'b110}, {7'b0110100, 3'b101}, {7'b0010100, 3'b101}, {7'b0000100, 3'b001}, {7'b0000100, 3'b101}, {7'b0000101, 3'b001}, {7'b0000101, 3'b010}, {7'b0000101, 3'b011}: illegal_insn = (RV32B == ibex_pkg_RV32BFull ? 1'b0 : 1'b1); - {7'b0000001, 3'b000}: begin - multdiv_operator_o = ibex_pkg_MD_OP_MULL; - multdiv_signed_mode_o = 2'b00; - illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0); - end - {7'b0000001, 3'b001}: begin - multdiv_operator_o = ibex_pkg_MD_OP_MULH; - multdiv_signed_mode_o = 2'b11; - illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0); - end - {7'b0000001, 3'b010}: begin - multdiv_operator_o = ibex_pkg_MD_OP_MULH; - multdiv_signed_mode_o = 2'b01; - illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0); - end - {7'b0000001, 3'b011}: begin - multdiv_operator_o = ibex_pkg_MD_OP_MULH; - multdiv_signed_mode_o = 2'b00; - illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0); - end - {7'b0000001, 3'b100}: begin - multdiv_operator_o = ibex_pkg_MD_OP_DIV; - multdiv_signed_mode_o = 2'b11; - illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0); - end - {7'b0000001, 3'b101}: begin - multdiv_operator_o = ibex_pkg_MD_OP_DIV; - multdiv_signed_mode_o = 2'b00; - illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0); - end - {7'b0000001, 3'b110}: begin - multdiv_operator_o = ibex_pkg_MD_OP_REM; - multdiv_signed_mode_o = 2'b11; - illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0); - end - {7'b0000001, 3'b111}: begin - multdiv_operator_o = ibex_pkg_MD_OP_REM; - multdiv_signed_mode_o = 2'b00; - illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0); - end - default: illegal_insn = 1'b1; - endcase - end - ibex_pkg_OPCODE_MISC_MEM: - case (instr[14:12]) - 3'b000: rf_we = 1'b0; - 3'b001: begin - jump_in_dec_o = 1'b1; - rf_we = 1'b0; - if (instr_first_cycle_i) begin - jump_set_o = 1'b1; - icache_inval_o = 1'b1; - end - end - default: illegal_insn = 1'b1; - endcase - ibex_pkg_OPCODE_SYSTEM: - if (instr[14:12] == 3'b000) begin - case (instr[31:20]) - 12'h000: ecall_insn_o = 1'b1; - 12'h001: ebrk_insn_o = 1'b1; - 12'h302: mret_insn_o = 1'b1; - 12'h7b2: dret_insn_o = 1'b1; - 12'h105: wfi_insn_o = 1'b1; - default: illegal_insn = 1'b1; - endcase - if ((instr_rs1 != 5'b00000) || (instr_rd != 5'b00000)) - illegal_insn = 1'b1; - end - else begin - csr_access_o = 1'b1; - rf_wdata_sel_o = ibex_pkg_RF_WD_CSR; - rf_we = 1'b1; - if (~instr[14]) - rf_ren_a_o = 1'b1; - case (instr[13:12]) - 2'b01: csr_op = ibex_pkg_CSR_OP_WRITE; - 2'b10: csr_op = ibex_pkg_CSR_OP_SET; - 2'b11: csr_op = ibex_pkg_CSR_OP_CLEAR; - default: csr_illegal = 1'b1; - endcase - illegal_insn = csr_illegal; - end - default: illegal_insn = 1'b1; - endcase - if (illegal_c_insn_i) - illegal_insn = 1'b1; - if (illegal_insn) begin - rf_we = 1'b0; - data_req_o = 1'b0; - data_we_o = 1'b0; - jump_in_dec_o = 1'b0; - jump_set_o = 1'b0; - branch_in_dec_o = 1'b0; - csr_access_o = 1'b0; - end - end - localparam [5:0] ibex_pkg_ALU_ADD = 0; - localparam [5:0] ibex_pkg_ALU_AND = 4; - localparam [5:0] ibex_pkg_ALU_ANDN = 7; - localparam [5:0] ibex_pkg_ALU_BDEP = 48; - localparam [5:0] ibex_pkg_ALU_BEXT = 47; - localparam [5:0] ibex_pkg_ALU_BFP = 49; - localparam [5:0] ibex_pkg_ALU_CLMUL = 50; - localparam [5:0] ibex_pkg_ALU_CLMULH = 52; - localparam [5:0] ibex_pkg_ALU_CLMULR = 51; - localparam [5:0] ibex_pkg_ALU_CLZ = 34; - localparam [5:0] ibex_pkg_ALU_CMIX = 40; - localparam [5:0] ibex_pkg_ALU_CMOV = 39; - localparam [5:0] ibex_pkg_ALU_CRC32C_B = 54; - localparam [5:0] ibex_pkg_ALU_CRC32C_H = 56; - localparam [5:0] ibex_pkg_ALU_CRC32C_W = 58; - localparam [5:0] ibex_pkg_ALU_CRC32_B = 53; - localparam [5:0] ibex_pkg_ALU_CRC32_H = 55; - localparam [5:0] ibex_pkg_ALU_CRC32_W = 57; - localparam [5:0] ibex_pkg_ALU_CTZ = 35; - localparam [5:0] ibex_pkg_ALU_EQ = 23; - localparam [5:0] ibex_pkg_ALU_FSL = 41; - localparam [5:0] ibex_pkg_ALU_FSR = 42; - localparam [5:0] ibex_pkg_ALU_GE = 21; - localparam [5:0] ibex_pkg_ALU_GEU = 22; - localparam [5:0] ibex_pkg_ALU_GORC = 16; - localparam [5:0] ibex_pkg_ALU_GREV = 15; - localparam [5:0] ibex_pkg_ALU_LT = 19; - localparam [5:0] ibex_pkg_ALU_LTU = 20; - localparam [5:0] ibex_pkg_ALU_MAX = 27; - localparam [5:0] ibex_pkg_ALU_MAXU = 28; - localparam [5:0] ibex_pkg_ALU_MIN = 25; - localparam [5:0] ibex_pkg_ALU_MINU = 26; - localparam [5:0] ibex_pkg_ALU_NE = 24; - localparam [5:0] ibex_pkg_ALU_OR = 3; - localparam [5:0] ibex_pkg_ALU_ORN = 6; - localparam [5:0] ibex_pkg_ALU_PACK = 29; - localparam [5:0] ibex_pkg_ALU_PACKH = 31; - localparam [5:0] ibex_pkg_ALU_PACKU = 30; - localparam [5:0] ibex_pkg_ALU_PCNT = 36; - localparam [5:0] ibex_pkg_ALU_ROL = 14; - localparam [5:0] ibex_pkg_ALU_ROR = 13; - localparam [5:0] ibex_pkg_ALU_SBCLR = 44; - localparam [5:0] ibex_pkg_ALU_SBEXT = 46; - localparam [5:0] ibex_pkg_ALU_SBINV = 45; - localparam [5:0] ibex_pkg_ALU_SBSET = 43; - localparam [5:0] ibex_pkg_ALU_SEXTB = 32; - localparam [5:0] ibex_pkg_ALU_SEXTH = 33; - localparam [5:0] ibex_pkg_ALU_SHFL = 17; - localparam [5:0] ibex_pkg_ALU_SLL = 10; - localparam [5:0] ibex_pkg_ALU_SLO = 12; - localparam [5:0] ibex_pkg_ALU_SLT = 37; - localparam [5:0] ibex_pkg_ALU_SLTU = 38; - localparam [5:0] ibex_pkg_ALU_SRA = 8; - localparam [5:0] ibex_pkg_ALU_SRL = 9; - localparam [5:0] ibex_pkg_ALU_SRO = 11; - localparam [5:0] ibex_pkg_ALU_SUB = 1; - localparam [5:0] ibex_pkg_ALU_UNSHFL = 18; - localparam [5:0] ibex_pkg_ALU_XNOR = 5; - localparam [5:0] ibex_pkg_ALU_XOR = 2; - localparam [0:0] ibex_pkg_IMM_A_Z = 0; - localparam [0:0] ibex_pkg_IMM_A_ZERO = 1; - localparam [2:0] ibex_pkg_IMM_B_B = 2; - localparam [2:0] ibex_pkg_IMM_B_I = 0; - localparam [2:0] ibex_pkg_IMM_B_INCR_PC = 5; - localparam [2:0] ibex_pkg_IMM_B_J = 4; - localparam [2:0] ibex_pkg_IMM_B_S = 1; - localparam [2:0] ibex_pkg_IMM_B_U = 3; - localparam [1:0] ibex_pkg_OP_A_CURRPC = 2; - localparam [1:0] ibex_pkg_OP_A_IMM = 3; - localparam [0:0] ibex_pkg_OP_B_IMM = 1; - always @(*) begin - alu_operator_o = ibex_pkg_ALU_SLTU; - alu_op_a_mux_sel_o = ibex_pkg_OP_A_IMM; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_a_mux_sel_o = ibex_pkg_IMM_A_ZERO; - imm_b_mux_sel_o = ibex_pkg_IMM_B_I; - bt_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - bt_b_mux_sel_o = ibex_pkg_IMM_B_I; - opcode_alu = instr_alu[6:0]; - use_rs3_d = 1'b0; - alu_multicycle_o = 1'b0; - mult_sel_o = 1'b0; - div_sel_o = 1'b0; - case (opcode_alu) - ibex_pkg_OPCODE_JAL: begin - if (BranchTargetALU) begin - bt_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - bt_b_mux_sel_o = ibex_pkg_IMM_B_J; - end - if (instr_first_cycle_i && !BranchTargetALU) begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_b_mux_sel_o = ibex_pkg_IMM_B_J; - alu_operator_o = ibex_pkg_ALU_ADD; - end - else begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_b_mux_sel_o = ibex_pkg_IMM_B_INCR_PC; - alu_operator_o = ibex_pkg_ALU_ADD; - end - end - ibex_pkg_OPCODE_JALR: begin - if (BranchTargetALU) begin - bt_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - bt_b_mux_sel_o = ibex_pkg_IMM_B_I; - end - if (instr_first_cycle_i && !BranchTargetALU) begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_b_mux_sel_o = ibex_pkg_IMM_B_I; - alu_operator_o = ibex_pkg_ALU_ADD; - end - else begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_b_mux_sel_o = ibex_pkg_IMM_B_INCR_PC; - alu_operator_o = ibex_pkg_ALU_ADD; - end - end - ibex_pkg_OPCODE_BRANCH: begin - case (instr_alu[14:12]) - 3'b000: alu_operator_o = ibex_pkg_ALU_EQ; - 3'b001: alu_operator_o = ibex_pkg_ALU_NE; - 3'b100: alu_operator_o = ibex_pkg_ALU_LT; - 3'b101: alu_operator_o = ibex_pkg_ALU_GE; - 3'b110: alu_operator_o = ibex_pkg_ALU_LTU; - 3'b111: alu_operator_o = ibex_pkg_ALU_GEU; - default: - ; - endcase - if (BranchTargetALU) begin - bt_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - bt_b_mux_sel_o = (branch_taken_i ? ibex_pkg_IMM_B_B : ibex_pkg_IMM_B_INCR_PC); - end - if (instr_first_cycle_i) begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_REG_B; - end - else begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_b_mux_sel_o = (branch_taken_i ? ibex_pkg_IMM_B_B : ibex_pkg_IMM_B_INCR_PC); - alu_operator_o = ibex_pkg_ALU_ADD; - end - end - ibex_pkg_OPCODE_STORE: begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_REG_B; - alu_operator_o = ibex_pkg_ALU_ADD; - if (!instr_alu[14]) begin - imm_b_mux_sel_o = ibex_pkg_IMM_B_S; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - end - end - ibex_pkg_OPCODE_LOAD: begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - alu_operator_o = ibex_pkg_ALU_ADD; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_b_mux_sel_o = ibex_pkg_IMM_B_I; - end - ibex_pkg_OPCODE_LUI: begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_IMM; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_a_mux_sel_o = ibex_pkg_IMM_A_ZERO; - imm_b_mux_sel_o = ibex_pkg_IMM_B_U; - alu_operator_o = ibex_pkg_ALU_ADD; - end - ibex_pkg_OPCODE_AUIPC: begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_b_mux_sel_o = ibex_pkg_IMM_B_U; - alu_operator_o = ibex_pkg_ALU_ADD; - end - ibex_pkg_OPCODE_OP_IMM: begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_b_mux_sel_o = ibex_pkg_IMM_B_I; - case (instr_alu[14:12]) - 3'b000: alu_operator_o = ibex_pkg_ALU_ADD; - 3'b010: alu_operator_o = ibex_pkg_ALU_SLT; - 3'b011: alu_operator_o = ibex_pkg_ALU_SLTU; - 3'b100: alu_operator_o = ibex_pkg_ALU_XOR; - 3'b110: alu_operator_o = ibex_pkg_ALU_OR; - 3'b111: alu_operator_o = ibex_pkg_ALU_AND; - 3'b001: - if (RV32B != ibex_pkg_RV32BNone) - case (instr_alu[31:27]) - 5'b00000: alu_operator_o = ibex_pkg_ALU_SLL; - 5'b00100: alu_operator_o = ibex_pkg_ALU_SLO; - 5'b01001: alu_operator_o = ibex_pkg_ALU_SBCLR; - 5'b00101: alu_operator_o = ibex_pkg_ALU_SBSET; - 5'b01101: alu_operator_o = ibex_pkg_ALU_SBINV; - 5'b00001: - if (instr_alu[26] == 0) - alu_operator_o = ibex_pkg_ALU_SHFL; - 5'b01100: - case (instr_alu[26:20]) - 7'b0000000: alu_operator_o = ibex_pkg_ALU_CLZ; - 7'b0000001: alu_operator_o = ibex_pkg_ALU_CTZ; - 7'b0000010: alu_operator_o = ibex_pkg_ALU_PCNT; - 7'b0000100: alu_operator_o = ibex_pkg_ALU_SEXTB; - 7'b0000101: alu_operator_o = ibex_pkg_ALU_SEXTH; - 7'b0010000: - if (RV32B == ibex_pkg_RV32BFull) begin - alu_operator_o = ibex_pkg_ALU_CRC32_B; - alu_multicycle_o = 1'b1; - end - 7'b0010001: - if (RV32B == ibex_pkg_RV32BFull) begin - alu_operator_o = ibex_pkg_ALU_CRC32_H; - alu_multicycle_o = 1'b1; - end - 7'b0010010: - if (RV32B == ibex_pkg_RV32BFull) begin - alu_operator_o = ibex_pkg_ALU_CRC32_W; - alu_multicycle_o = 1'b1; - end - 7'b0011000: - if (RV32B == ibex_pkg_RV32BFull) begin - alu_operator_o = ibex_pkg_ALU_CRC32C_B; - alu_multicycle_o = 1'b1; - end - 7'b0011001: - if (RV32B == ibex_pkg_RV32BFull) begin - alu_operator_o = ibex_pkg_ALU_CRC32C_H; - alu_multicycle_o = 1'b1; - end - 7'b0011010: - if (RV32B == ibex_pkg_RV32BFull) begin - alu_operator_o = ibex_pkg_ALU_CRC32C_W; - alu_multicycle_o = 1'b1; - end - default: - ; - endcase - default: - ; - endcase - else - alu_operator_o = ibex_pkg_ALU_SLL; - 3'b101: - if (RV32B != ibex_pkg_RV32BNone) begin - if (instr_alu[26] == 1'b1) begin - alu_operator_o = ibex_pkg_ALU_FSR; - alu_multicycle_o = 1'b1; - if (instr_first_cycle_i) - use_rs3_d = 1'b1; - else - use_rs3_d = 1'b0; - end - else - case (instr_alu[31:27]) - 5'b00000: alu_operator_o = ibex_pkg_ALU_SRL; - 5'b01000: alu_operator_o = ibex_pkg_ALU_SRA; - 5'b00100: alu_operator_o = ibex_pkg_ALU_SRO; - 5'b01001: alu_operator_o = ibex_pkg_ALU_SBEXT; - 5'b01100: begin - alu_operator_o = ibex_pkg_ALU_ROR; - alu_multicycle_o = 1'b1; - end - 5'b01101: alu_operator_o = ibex_pkg_ALU_GREV; - 5'b00101: alu_operator_o = ibex_pkg_ALU_GORC; - 5'b00001: - if (RV32B == ibex_pkg_RV32BFull) - if (instr_alu[26] == 1'b0) - alu_operator_o = ibex_pkg_ALU_UNSHFL; - default: - ; - endcase - end - else if (instr_alu[31:27] == 5'b00000) - alu_operator_o = ibex_pkg_ALU_SRL; - else if (instr_alu[31:27] == 5'b01000) - alu_operator_o = ibex_pkg_ALU_SRA; - default: - ; - endcase - end - ibex_pkg_OPCODE_OP: begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_REG_B; - if (instr_alu[26]) begin - if (RV32B != ibex_pkg_RV32BNone) - case ({instr_alu[26:25], instr_alu[14:12]}) - {2'b11, 3'b001}: begin - alu_operator_o = ibex_pkg_ALU_CMIX; - alu_multicycle_o = 1'b1; - if (instr_first_cycle_i) - use_rs3_d = 1'b1; - else - use_rs3_d = 1'b0; - end - {2'b11, 3'b101}: begin - alu_operator_o = ibex_pkg_ALU_CMOV; - alu_multicycle_o = 1'b1; - if (instr_first_cycle_i) - use_rs3_d = 1'b1; - else - use_rs3_d = 1'b0; - end - {2'b10, 3'b001}: begin - alu_operator_o = ibex_pkg_ALU_FSL; - alu_multicycle_o = 1'b1; - if (instr_first_cycle_i) - use_rs3_d = 1'b1; - else - use_rs3_d = 1'b0; - end - {2'b10, 3'b101}: begin - alu_operator_o = ibex_pkg_ALU_FSR; - alu_multicycle_o = 1'b1; - if (instr_first_cycle_i) - use_rs3_d = 1'b1; - else - use_rs3_d = 1'b0; - end - default: - ; - endcase - end - else - case ({instr_alu[31:25], instr_alu[14:12]}) - {7'b0000000, 3'b000}: alu_operator_o = ibex_pkg_ALU_ADD; - {7'b0100000, 3'b000}: alu_operator_o = ibex_pkg_ALU_SUB; - {7'b0000000, 3'b010}: alu_operator_o = ibex_pkg_ALU_SLT; - {7'b0000000, 3'b011}: alu_operator_o = ibex_pkg_ALU_SLTU; - {7'b0000000, 3'b100}: alu_operator_o = ibex_pkg_ALU_XOR; - {7'b0000000, 3'b110}: alu_operator_o = ibex_pkg_ALU_OR; - {7'b0000000, 3'b111}: alu_operator_o = ibex_pkg_ALU_AND; - {7'b0000000, 3'b001}: alu_operator_o = ibex_pkg_ALU_SLL; - {7'b0000000, 3'b101}: alu_operator_o = ibex_pkg_ALU_SRL; - {7'b0100000, 3'b101}: alu_operator_o = ibex_pkg_ALU_SRA; - {7'b0010000, 3'b001}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_SLO; - {7'b0010000, 3'b101}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_SRO; - {7'b0110000, 3'b001}: - if (RV32B != ibex_pkg_RV32BNone) begin - alu_operator_o = ibex_pkg_ALU_ROL; - alu_multicycle_o = 1'b1; - end - {7'b0110000, 3'b101}: - if (RV32B != ibex_pkg_RV32BNone) begin - alu_operator_o = ibex_pkg_ALU_ROR; - alu_multicycle_o = 1'b1; - end - {7'b0000101, 3'b100}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_MIN; - {7'b0000101, 3'b101}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_MAX; - {7'b0000101, 3'b110}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_MINU; - {7'b0000101, 3'b111}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_MAXU; - {7'b0000100, 3'b100}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_PACK; - {7'b0100100, 3'b100}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_PACKU; - {7'b0000100, 3'b111}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_PACKH; - {7'b0100000, 3'b100}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_XNOR; - {7'b0100000, 3'b110}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_ORN; - {7'b0100000, 3'b111}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_ANDN; - {7'b0100100, 3'b001}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_SBCLR; - {7'b0010100, 3'b001}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_SBSET; - {7'b0110100, 3'b001}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_SBINV; - {7'b0100100, 3'b101}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_SBEXT; - {7'b0100100, 3'b111}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_BFP; - {7'b0110100, 3'b101}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_GREV; - {7'b0010100, 3'b101}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_GORC; - {7'b0000100, 3'b001}: - if (RV32B == ibex_pkg_RV32BFull) - alu_operator_o = ibex_pkg_ALU_SHFL; - {7'b0000100, 3'b101}: - if (RV32B == ibex_pkg_RV32BFull) - alu_operator_o = ibex_pkg_ALU_UNSHFL; - {7'b0000101, 3'b001}: - if (RV32B == ibex_pkg_RV32BFull) - alu_operator_o = ibex_pkg_ALU_CLMUL; - {7'b0000101, 3'b010}: - if (RV32B == ibex_pkg_RV32BFull) - alu_operator_o = ibex_pkg_ALU_CLMULR; - {7'b0000101, 3'b011}: - if (RV32B == ibex_pkg_RV32BFull) - alu_operator_o = ibex_pkg_ALU_CLMULH; - {7'b0100100, 3'b110}: - if (RV32B == ibex_pkg_RV32BFull) begin - alu_operator_o = ibex_pkg_ALU_BDEP; - alu_multicycle_o = 1'b1; - end - {7'b0000100, 3'b110}: - if (RV32B == ibex_pkg_RV32BFull) begin - alu_operator_o = ibex_pkg_ALU_BEXT; - alu_multicycle_o = 1'b1; - end - {7'b0000001, 3'b000}: begin - alu_operator_o = ibex_pkg_ALU_ADD; - mult_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1); - end - {7'b0000001, 3'b001}: begin - alu_operator_o = ibex_pkg_ALU_ADD; - mult_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1); - end - {7'b0000001, 3'b010}: begin - alu_operator_o = ibex_pkg_ALU_ADD; - mult_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1); - end - {7'b0000001, 3'b011}: begin - alu_operator_o = ibex_pkg_ALU_ADD; - mult_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1); - end - {7'b0000001, 3'b100}: begin - alu_operator_o = ibex_pkg_ALU_ADD; - div_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1); - end - {7'b0000001, 3'b101}: begin - alu_operator_o = ibex_pkg_ALU_ADD; - div_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1); - end - {7'b0000001, 3'b110}: begin - alu_operator_o = ibex_pkg_ALU_ADD; - div_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1); - end - {7'b0000001, 3'b111}: begin - alu_operator_o = ibex_pkg_ALU_ADD; - div_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1); - end - default: - ; - endcase - end - ibex_pkg_OPCODE_MISC_MEM: - case (instr_alu[14:12]) - 3'b000: begin - alu_operator_o = ibex_pkg_ALU_ADD; - alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - end - 3'b001: - if (BranchTargetALU) begin - bt_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - bt_b_mux_sel_o = ibex_pkg_IMM_B_INCR_PC; - end - else begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_b_mux_sel_o = ibex_pkg_IMM_B_INCR_PC; - alu_operator_o = ibex_pkg_ALU_ADD; - end - default: - ; - endcase - ibex_pkg_OPCODE_SYSTEM: - if (instr_alu[14:12] == 3'b000) begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - end - else begin - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_a_mux_sel_o = ibex_pkg_IMM_A_Z; - imm_b_mux_sel_o = ibex_pkg_IMM_B_I; - if (instr_alu[14]) - alu_op_a_mux_sel_o = ibex_pkg_OP_A_IMM; - else - alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - end - default: - ; - endcase - end - assign mult_en_o = (illegal_insn ? 1'b0 : mult_sel_o); - assign div_en_o = (illegal_insn ? 1'b0 : div_sel_o); - assign illegal_insn_o = illegal_insn | illegal_reg_rv32e; - assign rf_we_o = rf_we & ~illegal_reg_rv32e; - assign unused_instr_alu = {instr_alu[19:15], instr_alu[11:7]}; -endmodule diff --git a/flow/designs/src/ibex/ibex_dummy_instr.v b/flow/designs/src/ibex/ibex_dummy_instr.v deleted file mode 100644 index e38acb35a3..0000000000 --- a/flow/designs/src/ibex/ibex_dummy_instr.v +++ /dev/null @@ -1,104 +0,0 @@ -module ibex_dummy_instr ( - clk_i, - rst_ni, - dummy_instr_en_i, - dummy_instr_mask_i, - dummy_instr_seed_en_i, - dummy_instr_seed_i, - fetch_valid_i, - id_in_ready_i, - insert_dummy_instr_o, - dummy_instr_data_o -); - input wire clk_i; - input wire rst_ni; - input wire dummy_instr_en_i; - input wire [2:0] dummy_instr_mask_i; - input wire dummy_instr_seed_en_i; - input wire [31:0] dummy_instr_seed_i; - input wire fetch_valid_i; - input wire id_in_ready_i; - output wire insert_dummy_instr_o; - output wire [31:0] dummy_instr_data_o; - localparam [31:0] TIMEOUT_CNT_W = 5; - localparam [31:0] OP_W = 5; - localparam [31:0] LFSR_OUT_W = ((2 + OP_W) + OP_W) + TIMEOUT_CNT_W; - wire [(((2 + OP_W) + OP_W) + TIMEOUT_CNT_W) - 1:0] lfsr_data; - wire [TIMEOUT_CNT_W - 1:0] dummy_cnt_incr; - wire [TIMEOUT_CNT_W - 1:0] dummy_cnt_threshold; - wire [TIMEOUT_CNT_W - 1:0] dummy_cnt_d; - reg [TIMEOUT_CNT_W - 1:0] dummy_cnt_q; - wire dummy_cnt_en; - wire lfsr_en; - wire [LFSR_OUT_W - 1:0] lfsr_state; - wire insert_dummy_instr; - reg [6:0] dummy_set; - reg [2:0] dummy_opcode; - wire [31:0] dummy_instr; - reg [31:0] dummy_instr_seed_q; - wire [31:0] dummy_instr_seed_d; - assign lfsr_en = insert_dummy_instr & id_in_ready_i; - assign dummy_instr_seed_d = dummy_instr_seed_q ^ dummy_instr_seed_i; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - dummy_instr_seed_q <= {32 {1'sb0}}; - else if (dummy_instr_seed_en_i) - dummy_instr_seed_q <= dummy_instr_seed_d; - prim_lfsr #( - .LfsrDw(32), - .StateOutDw(LFSR_OUT_W) - ) lfsr_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .seed_en_i(dummy_instr_seed_en_i), - .seed_i(dummy_instr_seed_d), - .lfsr_en_i(lfsr_en), - .entropy_i('0), - .state_o(lfsr_state) - ); - function automatic [(((2 + OP_W) + OP_W) + TIMEOUT_CNT_W) - 1:0] sv2v_cast_4AF33; - input reg [(((2 + OP_W) + OP_W) + TIMEOUT_CNT_W) - 1:0] inp; - sv2v_cast_4AF33 = inp; - endfunction - assign lfsr_data = sv2v_cast_4AF33(lfsr_state); - assign dummy_cnt_threshold = lfsr_data[TIMEOUT_CNT_W - 1-:TIMEOUT_CNT_W] & {dummy_instr_mask_i, {TIMEOUT_CNT_W - 3 {1'b1}}}; - assign dummy_cnt_incr = dummy_cnt_q + {{TIMEOUT_CNT_W - 1 {1'b0}}, 1'b1}; - assign dummy_cnt_d = (insert_dummy_instr ? {TIMEOUT_CNT_W {1'sb0}} : dummy_cnt_incr); - assign dummy_cnt_en = (dummy_instr_en_i & id_in_ready_i) & (fetch_valid_i | insert_dummy_instr); - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - dummy_cnt_q <= {TIMEOUT_CNT_W {1'sb0}}; - else if (dummy_cnt_en) - dummy_cnt_q <= dummy_cnt_d; - assign insert_dummy_instr = dummy_instr_en_i & (dummy_cnt_q == dummy_cnt_threshold); - localparam [1:0] DUMMY_ADD = 2'b00; - localparam [1:0] DUMMY_AND = 2'b11; - localparam [1:0] DUMMY_DIV = 2'b10; - localparam [1:0] DUMMY_MUL = 2'b01; - always @(*) - case (lfsr_data[2 + (OP_W + (OP_W + (TIMEOUT_CNT_W - 1)))-:((2 + (OP_W + (OP_W + (TIMEOUT_CNT_W - 1)))) >= (OP_W + (OP_W + TIMEOUT_CNT_W)) ? ((2 + (OP_W + (OP_W + (TIMEOUT_CNT_W - 1)))) - (OP_W + (OP_W + TIMEOUT_CNT_W))) + 1 : ((OP_W + (OP_W + TIMEOUT_CNT_W)) - (2 + (OP_W + (OP_W + (TIMEOUT_CNT_W - 1))))) + 1)]) - DUMMY_ADD: begin - dummy_set = 7'b0000000; - dummy_opcode = 3'b000; - end - DUMMY_MUL: begin - dummy_set = 7'b0000001; - dummy_opcode = 3'b000; - end - DUMMY_DIV: begin - dummy_set = 7'b0000001; - dummy_opcode = 3'b100; - end - DUMMY_AND: begin - dummy_set = 7'b0000000; - dummy_opcode = 3'b111; - end - default: begin - dummy_set = 7'b0000000; - dummy_opcode = 3'b000; - end - endcase - assign dummy_instr = {dummy_set, lfsr_data[OP_W + (OP_W + (TIMEOUT_CNT_W - 1))-:((OP_W + (OP_W + (TIMEOUT_CNT_W - 1))) >= (OP_W + TIMEOUT_CNT_W) ? ((OP_W + (OP_W + (TIMEOUT_CNT_W - 1))) - (OP_W + TIMEOUT_CNT_W)) + 1 : ((OP_W + TIMEOUT_CNT_W) - (OP_W + (OP_W + (TIMEOUT_CNT_W - 1)))) + 1)], lfsr_data[OP_W + (TIMEOUT_CNT_W - 1)-:((OP_W + (TIMEOUT_CNT_W - 1)) >= TIMEOUT_CNT_W ? ((OP_W + (TIMEOUT_CNT_W - 1)) - TIMEOUT_CNT_W) + 1 : (TIMEOUT_CNT_W - (OP_W + (TIMEOUT_CNT_W - 1))) + 1)], dummy_opcode, 5'h00, 7'h33}; - assign insert_dummy_instr_o = insert_dummy_instr; - assign dummy_instr_data_o = dummy_instr; -endmodule diff --git a/flow/designs/src/ibex/ibex_ex_block.v b/flow/designs/src/ibex/ibex_ex_block.v deleted file mode 100644 index 91eeb2f268..0000000000 --- a/flow/designs/src/ibex/ibex_ex_block.v +++ /dev/null @@ -1,179 +0,0 @@ -module ibex_ex_block ( - clk_i, - rst_ni, - alu_operator_i, - alu_operand_a_i, - alu_operand_b_i, - alu_instr_first_cycle_i, - bt_a_operand_i, - bt_b_operand_i, - multdiv_operator_i, - mult_en_i, - div_en_i, - mult_sel_i, - div_sel_i, - multdiv_signed_mode_i, - multdiv_operand_a_i, - multdiv_operand_b_i, - multdiv_ready_id_i, - data_ind_timing_i, - imd_val_we_o, - imd_val_d_o, - imd_val_q_i, - alu_adder_result_ex_o, - result_ex_o, - branch_target_o, - branch_decision_o, - ex_valid_o -); - localparam integer ibex_pkg_RV32MFast = 2; - parameter integer RV32M = ibex_pkg_RV32MFast; - localparam integer ibex_pkg_RV32BNone = 0; - parameter integer RV32B = ibex_pkg_RV32BNone; - parameter [0:0] BranchTargetALU = 0; - input wire clk_i; - input wire rst_ni; - input wire [5:0] alu_operator_i; - input wire [31:0] alu_operand_a_i; - input wire [31:0] alu_operand_b_i; - input wire alu_instr_first_cycle_i; - input wire [31:0] bt_a_operand_i; - input wire [31:0] bt_b_operand_i; - input wire [1:0] multdiv_operator_i; - input wire mult_en_i; - input wire div_en_i; - input wire mult_sel_i; - input wire div_sel_i; - input wire [1:0] multdiv_signed_mode_i; - input wire [31:0] multdiv_operand_a_i; - input wire [31:0] multdiv_operand_b_i; - input wire multdiv_ready_id_i; - input wire data_ind_timing_i; - output wire [1:0] imd_val_we_o; - output wire [67:0] imd_val_d_o; - input wire [67:0] imd_val_q_i; - output wire [31:0] alu_adder_result_ex_o; - output wire [31:0] result_ex_o; - output wire [31:0] branch_target_o; - output wire branch_decision_o; - output wire ex_valid_o; - wire [31:0] alu_result; - wire [31:0] multdiv_result; - wire [32:0] multdiv_alu_operand_b; - wire [32:0] multdiv_alu_operand_a; - wire [33:0] alu_adder_result_ext; - wire alu_cmp_result; - wire alu_is_equal_result; - wire multdiv_valid; - wire multdiv_sel; - wire [63:0] alu_imd_val_q; - wire [63:0] alu_imd_val_d; - wire [1:0] alu_imd_val_we; - wire [67:0] multdiv_imd_val_d; - wire [1:0] multdiv_imd_val_we; - localparam integer ibex_pkg_RV32MNone = 0; - generate - if (RV32M != ibex_pkg_RV32MNone) begin : gen_multdiv_m - assign multdiv_sel = mult_sel_i | div_sel_i; - end - else begin : gen_multdiv_no_m - assign multdiv_sel = 1'b0; - end - endgenerate - assign imd_val_d_o[34+:34] = (multdiv_sel ? multdiv_imd_val_d[34+:34] : {2'b00, alu_imd_val_d[32+:32]}); - assign imd_val_d_o[0+:34] = (multdiv_sel ? multdiv_imd_val_d[0+:34] : {2'b00, alu_imd_val_d[0+:32]}); - assign imd_val_we_o = (multdiv_sel ? multdiv_imd_val_we : alu_imd_val_we); - assign alu_imd_val_q = {imd_val_q_i[65-:32], imd_val_q_i[31-:32]}; - assign result_ex_o = (multdiv_sel ? multdiv_result : alu_result); - assign branch_decision_o = alu_cmp_result; - generate - if (BranchTargetALU) begin : g_branch_target_alu - wire [32:0] bt_alu_result; - wire unused_bt_carry; - assign bt_alu_result = bt_a_operand_i + bt_b_operand_i; - assign unused_bt_carry = bt_alu_result[32]; - assign branch_target_o = bt_alu_result[31:0]; - end - else begin : g_no_branch_target_alu - wire [31:0] unused_bt_a_operand; - wire [31:0] unused_bt_b_operand; - assign unused_bt_a_operand = bt_a_operand_i; - assign unused_bt_b_operand = bt_b_operand_i; - assign branch_target_o = alu_adder_result_ex_o; - end - endgenerate - ibex_alu #(.RV32B(RV32B)) alu_i( - .operator_i(alu_operator_i), - .operand_a_i(alu_operand_a_i), - .operand_b_i(alu_operand_b_i), - .instr_first_cycle_i(alu_instr_first_cycle_i), - .imd_val_q_i(alu_imd_val_q), - .imd_val_we_o(alu_imd_val_we), - .imd_val_d_o(alu_imd_val_d), - .multdiv_operand_a_i(multdiv_alu_operand_a), - .multdiv_operand_b_i(multdiv_alu_operand_b), - .multdiv_sel_i(multdiv_sel), - .adder_result_o(alu_adder_result_ex_o), - .adder_result_ext_o(alu_adder_result_ext), - .result_o(alu_result), - .comparison_result_o(alu_cmp_result), - .is_equal_result_o(alu_is_equal_result) - ); - localparam integer ibex_pkg_RV32MSingleCycle = 3; - localparam integer ibex_pkg_RV32MSlow = 1; - generate - if (RV32M == ibex_pkg_RV32MSlow) begin : gen_multdiv_slow - ibex_multdiv_slow multdiv_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .mult_en_i(mult_en_i), - .div_en_i(div_en_i), - .mult_sel_i(mult_sel_i), - .div_sel_i(div_sel_i), - .operator_i(multdiv_operator_i), - .signed_mode_i(multdiv_signed_mode_i), - .op_a_i(multdiv_operand_a_i), - .op_b_i(multdiv_operand_b_i), - .alu_adder_ext_i(alu_adder_result_ext), - .alu_adder_i(alu_adder_result_ex_o), - .equal_to_zero_i(alu_is_equal_result), - .data_ind_timing_i(data_ind_timing_i), - .valid_o(multdiv_valid), - .alu_operand_a_o(multdiv_alu_operand_a), - .alu_operand_b_o(multdiv_alu_operand_b), - .imd_val_q_i(imd_val_q_i), - .imd_val_d_o(multdiv_imd_val_d), - .imd_val_we_o(multdiv_imd_val_we), - .multdiv_ready_id_i(multdiv_ready_id_i), - .multdiv_result_o(multdiv_result) - ); - end - else if ((RV32M == ibex_pkg_RV32MFast) || (RV32M == ibex_pkg_RV32MSingleCycle)) begin : gen_multdiv_fast - ibex_multdiv_fast #(.RV32M(RV32M)) multdiv_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .mult_en_i(mult_en_i), - .div_en_i(div_en_i), - .mult_sel_i(mult_sel_i), - .div_sel_i(div_sel_i), - .operator_i(multdiv_operator_i), - .signed_mode_i(multdiv_signed_mode_i), - .op_a_i(multdiv_operand_a_i), - .op_b_i(multdiv_operand_b_i), - .alu_operand_a_o(multdiv_alu_operand_a), - .alu_operand_b_o(multdiv_alu_operand_b), - .alu_adder_ext_i(alu_adder_result_ext), - .alu_adder_i(alu_adder_result_ex_o), - .equal_to_zero_i(alu_is_equal_result), - .data_ind_timing_i(data_ind_timing_i), - .imd_val_q_i(imd_val_q_i), - .imd_val_d_o(multdiv_imd_val_d), - .imd_val_we_o(multdiv_imd_val_we), - .multdiv_ready_id_i(multdiv_ready_id_i), - .valid_o(multdiv_valid), - .multdiv_result_o(multdiv_result) - ); - end - endgenerate - assign ex_valid_o = (multdiv_sel ? multdiv_valid : ~(|alu_imd_val_we)); -endmodule diff --git a/flow/designs/src/ibex/ibex_fetch_fifo.v b/flow/designs/src/ibex/ibex_fetch_fifo.v deleted file mode 100644 index e83b98c504..0000000000 --- a/flow/designs/src/ibex/ibex_fetch_fifo.v +++ /dev/null @@ -1,136 +0,0 @@ -module ibex_fetch_fifo ( - clk_i, - rst_ni, - clear_i, - busy_o, - in_valid_i, - in_addr_i, - in_rdata_i, - in_err_i, - out_valid_o, - out_ready_i, - out_addr_o, - out_addr_next_o, - out_rdata_o, - out_err_o, - out_err_plus2_o -); - parameter [31:0] NUM_REQS = 2; - input wire clk_i; - input wire rst_ni; - input wire clear_i; - output wire [NUM_REQS - 1:0] busy_o; - input wire in_valid_i; - input wire [31:0] in_addr_i; - input wire [31:0] in_rdata_i; - input wire in_err_i; - output reg out_valid_o; - input wire out_ready_i; - output wire [31:0] out_addr_o; - output wire [31:0] out_addr_next_o; - output reg [31:0] out_rdata_o; - output reg out_err_o; - output reg out_err_plus2_o; - localparam [31:0] DEPTH = NUM_REQS + 1; - wire [(DEPTH * 32) - 1:0] rdata_d; - reg [(DEPTH * 32) - 1:0] rdata_q; - wire [DEPTH - 1:0] err_d; - reg [DEPTH - 1:0] err_q; - wire [DEPTH - 1:0] valid_d; - reg [DEPTH - 1:0] valid_q; - wire [DEPTH - 1:0] lowest_free_entry; - wire [DEPTH - 1:0] valid_pushed; - wire [DEPTH - 1:0] valid_popped; - wire [DEPTH - 1:0] entry_en; - wire pop_fifo; - wire [31:0] rdata; - wire [31:0] rdata_unaligned; - wire err; - wire err_unaligned; - wire err_plus2; - wire valid; - wire valid_unaligned; - wire aligned_is_compressed; - wire unaligned_is_compressed; - wire addr_incr_two; - wire [31:1] instr_addr_next; - wire [31:1] instr_addr_d; - reg [31:1] instr_addr_q; - wire instr_addr_en; - wire unused_addr_in; - assign rdata = (valid_q[0] ? rdata_q[0+:32] : in_rdata_i); - assign err = (valid_q[0] ? err_q[0] : in_err_i); - assign valid = valid_q[0] | in_valid_i; - assign rdata_unaligned = (valid_q[1] ? {rdata_q[47-:16], rdata[31:16]} : {in_rdata_i[15:0], rdata[31:16]}); - assign err_unaligned = (valid_q[1] ? (err_q[1] & ~unaligned_is_compressed) | err_q[0] : (valid_q[0] & err_q[0]) | (in_err_i & (~valid_q[0] | ~unaligned_is_compressed))); - assign err_plus2 = (valid_q[1] ? err_q[1] & ~err_q[0] : (in_err_i & valid_q[0]) & ~err_q[0]); - assign valid_unaligned = (valid_q[1] ? 1'b1 : valid_q[0] & in_valid_i); - assign unaligned_is_compressed = (rdata[17:16] != 2'b11) & ~err; - assign aligned_is_compressed = (rdata[1:0] != 2'b11) & ~err; - always @(*) - if (out_addr_o[1]) begin - out_rdata_o = rdata_unaligned; - out_err_o = err_unaligned; - out_err_plus2_o = err_plus2; - if (unaligned_is_compressed) - out_valid_o = valid; - else - out_valid_o = valid_unaligned; - end - else begin - out_rdata_o = rdata; - out_err_o = err; - out_err_plus2_o = 1'b0; - out_valid_o = valid; - end - assign instr_addr_en = clear_i | (out_ready_i & out_valid_o); - assign addr_incr_two = (instr_addr_q[1] ? unaligned_is_compressed : aligned_is_compressed); - assign instr_addr_next = instr_addr_q[31:1] + {29'd0, ~addr_incr_two, addr_incr_two}; - assign instr_addr_d = (clear_i ? in_addr_i[31:1] : instr_addr_next); - always @(posedge clk_i) - if (instr_addr_en) - instr_addr_q <= instr_addr_d; - assign out_addr_next_o = {instr_addr_next, 1'b0}; - assign out_addr_o = {instr_addr_q, 1'b0}; - assign unused_addr_in = in_addr_i[0]; - assign busy_o = valid_q[DEPTH - 1:DEPTH - NUM_REQS]; - assign pop_fifo = (out_ready_i & out_valid_o) & (~aligned_is_compressed | out_addr_o[1]); - generate - genvar i; - for (i = 0; i < (DEPTH - 1); i = i + 1) begin : g_fifo_next - if (i == 0) begin : g_ent0 - assign lowest_free_entry[i] = ~valid_q[i]; - end - else begin : g_ent_others - assign lowest_free_entry[i] = ~valid_q[i] & valid_q[i - 1]; - end - assign valid_pushed[i] = (in_valid_i & lowest_free_entry[i]) | valid_q[i]; - assign valid_popped[i] = (pop_fifo ? valid_pushed[i + 1] : valid_pushed[i]); - assign valid_d[i] = valid_popped[i] & ~clear_i; - assign entry_en[i] = (valid_pushed[i + 1] & pop_fifo) | ((in_valid_i & lowest_free_entry[i]) & ~pop_fifo); - assign rdata_d[i * 32+:32] = (valid_q[i + 1] ? rdata_q[(i + 1) * 32+:32] : in_rdata_i); - assign err_d[i] = (valid_q[i + 1] ? err_q[i + 1] : in_err_i); - end - endgenerate - assign lowest_free_entry[DEPTH - 1] = ~valid_q[DEPTH - 1] & valid_q[DEPTH - 2]; - assign valid_pushed[DEPTH - 1] = valid_q[DEPTH - 1] | (in_valid_i & lowest_free_entry[DEPTH - 1]); - assign valid_popped[DEPTH - 1] = (pop_fifo ? 1'b0 : valid_pushed[DEPTH - 1]); - assign valid_d[DEPTH - 1] = valid_popped[DEPTH - 1] & ~clear_i; - assign entry_en[DEPTH - 1] = in_valid_i & lowest_free_entry[DEPTH - 1]; - assign rdata_d[(DEPTH - 1) * 32+:32] = in_rdata_i; - assign err_d[DEPTH - 1] = in_err_i; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - valid_q <= {DEPTH {1'sb0}}; - else - valid_q <= valid_d; - generate - for (i = 0; i < DEPTH; i = i + 1) begin : g_fifo_regs - always @(posedge clk_i) - if (entry_en[i]) begin - rdata_q[i * 32+:32] <= rdata_d[i * 32+:32]; - err_q[i] <= err_d[i]; - end - end - endgenerate -endmodule diff --git a/flow/designs/src/ibex/ibex_icache.v b/flow/designs/src/ibex/ibex_icache.v deleted file mode 100644 index 808ed8562b..0000000000 --- a/flow/designs/src/ibex/ibex_icache.v +++ /dev/null @@ -1,635 +0,0 @@ -module ibex_icache ( - clk_i, - rst_ni, - req_i, - branch_i, - branch_spec_i, - addr_i, - ready_i, - valid_o, - rdata_o, - addr_o, - err_o, - err_plus2_o, - instr_req_o, - instr_gnt_i, - instr_addr_o, - instr_rdata_i, - instr_err_i, - instr_pmp_err_i, - instr_rvalid_i, - icache_enable_i, - icache_inval_i, - busy_o -); - parameter [31:0] BusWidth = 32; - parameter [31:0] CacheSizeBytes = 4096; - parameter [0:0] ICacheECC = 1'b0; - parameter [31:0] LineSize = 64; - parameter [31:0] NumWays = 2; - parameter [0:0] SpecRequest = 1'b0; - parameter [0:0] BranchCache = 1'b0; - input wire clk_i; - input wire rst_ni; - input wire req_i; - input wire branch_i; - input wire branch_spec_i; - input wire [31:0] addr_i; - input wire ready_i; - output wire valid_o; - output wire [31:0] rdata_o; - output wire [31:0] addr_o; - output wire err_o; - output wire err_plus2_o; - output wire instr_req_o; - input wire instr_gnt_i; - output wire [31:0] instr_addr_o; - input wire [BusWidth - 1:0] instr_rdata_i; - input wire instr_err_i; - input wire instr_pmp_err_i; - input wire instr_rvalid_i; - input wire icache_enable_i; - input wire icache_inval_i; - output wire busy_o; - localparam [31:0] ADDR_W = 32; - localparam [31:0] NUM_FB = 4; - localparam [31:0] FB_THRESHOLD = NUM_FB - 2; - localparam [31:0] LINE_SIZE_ECC = (ICacheECC ? LineSize + 8 : LineSize); - localparam [31:0] LINE_SIZE_BYTES = LineSize / 8; - localparam [31:0] LINE_W = $clog2(LINE_SIZE_BYTES); - localparam [31:0] BUS_BYTES = BusWidth / 8; - localparam [31:0] BUS_W = $clog2(BUS_BYTES); - localparam [31:0] LINE_BEATS = LINE_SIZE_BYTES / BUS_BYTES; - localparam [31:0] LINE_BEATS_W = $clog2(LINE_BEATS); - localparam [31:0] NUM_LINES = (CacheSizeBytes / NumWays) / LINE_SIZE_BYTES; - localparam [31:0] INDEX_W = $clog2(NUM_LINES); - localparam [31:0] INDEX_HI = (INDEX_W + LINE_W) - 1; - localparam [31:0] TAG_SIZE = ((ADDR_W - INDEX_W) - LINE_W) + 1; - localparam [31:0] TAG_SIZE_ECC = (ICacheECC ? TAG_SIZE + 6 : TAG_SIZE); - localparam [31:0] OUTPUT_BEATS = BUS_BYTES / 2; - wire [ADDR_W - 1:0] lookup_addr_aligned; - wire [ADDR_W - 1:0] prefetch_addr_d; - reg [ADDR_W - 1:0] prefetch_addr_q; - wire prefetch_addr_en; - wire branch_suppress; - wire lookup_throttle; - wire lookup_req_ic0; - wire [ADDR_W - 1:0] lookup_addr_ic0; - wire [INDEX_W - 1:0] lookup_index_ic0; - wire fill_req_ic0; - wire [INDEX_W - 1:0] fill_index_ic0; - wire [TAG_SIZE - 1:0] fill_tag_ic0; - wire [LineSize - 1:0] fill_wdata_ic0; - wire lookup_grant_ic0; - wire lookup_actual_ic0; - wire fill_grant_ic0; - wire tag_req_ic0; - wire [INDEX_W - 1:0] tag_index_ic0; - wire [NumWays - 1:0] tag_banks_ic0; - wire tag_write_ic0; - wire [TAG_SIZE_ECC - 1:0] tag_wdata_ic0; - wire data_req_ic0; - wire [INDEX_W - 1:0] data_index_ic0; - wire [NumWays - 1:0] data_banks_ic0; - wire data_write_ic0; - wire [LINE_SIZE_ECC - 1:0] data_wdata_ic0; - wire [TAG_SIZE_ECC - 1:0] tag_rdata_ic1 [0:NumWays - 1]; - wire [LINE_SIZE_ECC - 1:0] data_rdata_ic1 [0:NumWays - 1]; - reg [LINE_SIZE_ECC - 1:0] hit_data_ic1; - reg lookup_valid_ic1; - reg [ADDR_W - 1:INDEX_HI + 1] lookup_addr_ic1; - wire [NumWays - 1:0] tag_match_ic1; - wire tag_hit_ic1; - wire [NumWays - 1:0] tag_invalid_ic1; - wire [NumWays - 1:0] lowest_invalid_way_ic1; - wire [NumWays - 1:0] round_robin_way_ic1; - reg [NumWays - 1:0] round_robin_way_q; - wire [NumWays - 1:0] sel_way_ic1; - wire ecc_err_ic1; - wire ecc_write_req; - wire [NumWays - 1:0] ecc_write_ways; - wire [INDEX_W - 1:0] ecc_write_index; - wire gnt_or_pmp_err; - wire gnt_not_pmp_err; - reg [1:0] fb_fill_level; - wire fill_cache_new; - wire fill_new_alloc; - wire fill_spec_req; - wire fill_spec_done; - wire fill_spec_hold; - wire [(NUM_FB * NUM_FB) - 1:0] fill_older_d; - reg [(NUM_FB * NUM_FB) - 1:0] fill_older_q; - wire [NUM_FB - 1:0] fill_alloc_sel; - wire [NUM_FB - 1:0] fill_alloc; - wire [NUM_FB - 1:0] fill_busy_d; - reg [NUM_FB - 1:0] fill_busy_q; - wire [NUM_FB - 1:0] fill_done; - reg [NUM_FB - 1:0] fill_in_ic1; - wire [NUM_FB - 1:0] fill_stale_d; - reg [NUM_FB - 1:0] fill_stale_q; - wire [NUM_FB - 1:0] fill_cache_d; - reg [NUM_FB - 1:0] fill_cache_q; - wire [NUM_FB - 1:0] fill_hit_ic1; - wire [NUM_FB - 1:0] fill_hit_d; - reg [NUM_FB - 1:0] fill_hit_q; - wire [(LINE_BEATS_W >= 0 ? (NUM_FB * (LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - LINE_BEATS_W)) + (LINE_BEATS_W - 1)):(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W)] fill_ext_cnt_d; - reg [(LINE_BEATS_W >= 0 ? (NUM_FB * (LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - LINE_BEATS_W)) + (LINE_BEATS_W - 1)):(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W)] fill_ext_cnt_q; - wire [NUM_FB - 1:0] fill_ext_hold_d; - reg [NUM_FB - 1:0] fill_ext_hold_q; - wire [NUM_FB - 1:0] fill_ext_done; - wire [(LINE_BEATS_W >= 0 ? (NUM_FB * (LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - LINE_BEATS_W)) + (LINE_BEATS_W - 1)):(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W)] fill_rvd_cnt_d; - reg [(LINE_BEATS_W >= 0 ? (NUM_FB * (LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - LINE_BEATS_W)) + (LINE_BEATS_W - 1)):(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W)] fill_rvd_cnt_q; - wire [NUM_FB - 1:0] fill_rvd_done; - wire [NUM_FB - 1:0] fill_ram_done_d; - reg [NUM_FB - 1:0] fill_ram_done_q; - wire [NUM_FB - 1:0] fill_out_grant; - wire [(LINE_BEATS_W >= 0 ? (NUM_FB * (LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - LINE_BEATS_W)) + (LINE_BEATS_W - 1)):(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W)] fill_out_cnt_d; - reg [(LINE_BEATS_W >= 0 ? (NUM_FB * (LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - LINE_BEATS_W)) + (LINE_BEATS_W - 1)):(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W)] fill_out_cnt_q; - wire [NUM_FB - 1:0] fill_out_done; - wire [NUM_FB - 1:0] fill_ext_req; - wire [NUM_FB - 1:0] fill_rvd_exp; - wire [NUM_FB - 1:0] fill_ram_req; - wire [NUM_FB - 1:0] fill_out_req; - wire [NUM_FB - 1:0] fill_data_sel; - wire [NUM_FB - 1:0] fill_data_reg; - wire [NUM_FB - 1:0] fill_data_hit; - wire [NUM_FB - 1:0] fill_data_rvd; - wire [(NUM_FB * LINE_BEATS_W) - 1:0] fill_ext_off; - wire [(NUM_FB * LINE_BEATS_W) - 1:0] fill_rvd_off; - wire [(LINE_BEATS_W >= 0 ? (NUM_FB * (LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - LINE_BEATS_W)) + (LINE_BEATS_W - 1)):(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W)] fill_rvd_beat; - wire [NUM_FB - 1:0] fill_ext_arb; - wire [NUM_FB - 1:0] fill_ram_arb; - wire [NUM_FB - 1:0] fill_out_arb; - wire [NUM_FB - 1:0] fill_rvd_arb; - wire [NUM_FB - 1:0] fill_entry_en; - wire [NUM_FB - 1:0] fill_addr_en; - wire [NUM_FB - 1:0] fill_way_en; - wire [(NUM_FB * LINE_BEATS) - 1:0] fill_data_en; - wire [(NUM_FB * LINE_BEATS) - 1:0] fill_err_d; - reg [(NUM_FB * LINE_BEATS) - 1:0] fill_err_q; - reg [ADDR_W - 1:0] fill_addr_q [0:NUM_FB - 1]; - reg [NumWays - 1:0] fill_way_q [0:NUM_FB - 1]; - wire [LineSize - 1:0] fill_data_d [0:NUM_FB - 1]; - reg [LineSize - 1:0] fill_data_q [0:NUM_FB - 1]; - reg [ADDR_W - 1:BUS_W] fill_ext_req_addr; - reg [ADDR_W - 1:0] fill_ram_req_addr; - reg [NumWays - 1:0] fill_ram_req_way; - reg [LineSize - 1:0] fill_ram_req_data; - reg [LineSize - 1:0] fill_out_data; - reg [LINE_BEATS - 1:0] fill_out_err; - wire instr_req; - wire [ADDR_W - 1:BUS_W] instr_addr; - wire skid_complete_instr; - wire skid_ready; - wire output_compressed; - wire skid_valid_d; - reg skid_valid_q; - wire skid_en; - wire [15:0] skid_data_d; - reg [15:0] skid_data_q; - reg skid_err_q; - wire output_valid; - wire addr_incr_two; - wire output_addr_en; - wire [ADDR_W - 1:1] output_addr_d; - reg [ADDR_W - 1:1] output_addr_q; - reg [15:0] output_data_lo; - reg [15:0] output_data_hi; - wire data_valid; - wire output_ready; - wire [LineSize - 1:0] line_data; - wire [LINE_BEATS - 1:0] line_err; - reg [31:0] line_data_muxed; - reg line_err_muxed; - wire [31:0] output_data; - wire output_err; - wire start_inval; - wire inval_done; - reg reset_inval_q; - wire inval_prog_d; - reg inval_prog_q; - wire [INDEX_W - 1:0] inval_index_d; - reg [INDEX_W - 1:0] inval_index_q; - assign lookup_addr_aligned = {lookup_addr_ic0[ADDR_W - 1:LINE_W], {LINE_W {1'b0}}}; - assign prefetch_addr_d = (lookup_grant_ic0 ? lookup_addr_aligned + {{(ADDR_W - LINE_W) - 1 {1'b0}}, 1'b1, {LINE_W {1'b0}}} : addr_i); - assign prefetch_addr_en = branch_i | lookup_grant_ic0; - always @(posedge clk_i) - if (prefetch_addr_en) - prefetch_addr_q <= prefetch_addr_d; - assign lookup_throttle = fb_fill_level > FB_THRESHOLD[1:0]; - assign lookup_req_ic0 = ((req_i & ~&fill_busy_q) & (branch_i | ~lookup_throttle)) & ~ecc_write_req; - assign lookup_addr_ic0 = (branch_spec_i ? addr_i : prefetch_addr_q); - assign lookup_index_ic0 = lookup_addr_ic0[INDEX_HI:LINE_W]; - assign fill_req_ic0 = |fill_ram_req; - assign fill_index_ic0 = fill_ram_req_addr[INDEX_HI:LINE_W]; - assign fill_tag_ic0 = {~inval_prog_q & ~ecc_write_req, fill_ram_req_addr[ADDR_W - 1:INDEX_HI + 1]}; - assign fill_wdata_ic0 = fill_ram_req_data; - assign branch_suppress = branch_spec_i & ~branch_i; - assign lookup_grant_ic0 = lookup_req_ic0 & ~branch_suppress; - assign fill_grant_ic0 = ((fill_req_ic0 & (~lookup_req_ic0 | branch_suppress)) & ~inval_prog_q) & ~ecc_write_req; - assign lookup_actual_ic0 = ((lookup_grant_ic0 & icache_enable_i) & ~inval_prog_q) & ~start_inval; - assign tag_req_ic0 = ((lookup_req_ic0 | fill_req_ic0) | inval_prog_q) | ecc_write_req; - assign tag_index_ic0 = (inval_prog_q ? inval_index_q : (ecc_write_req ? ecc_write_index : (fill_grant_ic0 ? fill_index_ic0 : lookup_index_ic0))); - assign tag_banks_ic0 = (ecc_write_req ? ecc_write_ways : (fill_grant_ic0 ? fill_ram_req_way : {NumWays {1'b1}})); - assign tag_write_ic0 = (fill_grant_ic0 | inval_prog_q) | ecc_write_req; - assign data_req_ic0 = lookup_req_ic0 | fill_req_ic0; - assign data_index_ic0 = tag_index_ic0; - assign data_banks_ic0 = tag_banks_ic0; - assign data_write_ic0 = tag_write_ic0; - generate - if (ICacheECC) begin : gen_ecc_wdata - wire [21:0] tag_ecc_input_padded; - wire [27:0] tag_ecc_output_padded; - wire [22 - TAG_SIZE:0] tag_ecc_output_unused; - assign tag_ecc_input_padded = {{22 - TAG_SIZE {1'b0}}, fill_tag_ic0}; - assign tag_ecc_output_unused = tag_ecc_output_padded[21:TAG_SIZE - 1]; - prim_secded_28_22_enc tag_ecc_enc( - .in(tag_ecc_input_padded), - .out(tag_ecc_output_padded) - ); - assign tag_wdata_ic0 = {tag_ecc_output_padded[27:22], tag_ecc_output_padded[TAG_SIZE - 1:0]}; - prim_secded_72_64_enc data_ecc_enc( - .in(fill_wdata_ic0), - .out(data_wdata_ic0) - ); - end - else begin : gen_noecc_wdata - assign tag_wdata_ic0 = fill_tag_ic0; - assign data_wdata_ic0 = fill_wdata_ic0; - end - endgenerate - generate - genvar way; - for (way = 0; way < NumWays; way = way + 1) begin : gen_rams - prim_ram_1p #( - .Width(TAG_SIZE_ECC), - .Depth(NUM_LINES), - .DataBitsPerMask(TAG_SIZE_ECC) - ) tag_bank( - .clk_i(clk_i), - .req_i(tag_req_ic0 & tag_banks_ic0[way]), - .write_i(tag_write_ic0), - .wmask_i({TAG_SIZE_ECC {1'b1}}), - .addr_i(tag_index_ic0), - .wdata_i(tag_wdata_ic0), - .rdata_o(tag_rdata_ic1[way]) - ); - prim_ram_1p #( - .Width(LINE_SIZE_ECC), - .Depth(NUM_LINES), - .DataBitsPerMask(LINE_SIZE_ECC) - ) data_bank( - .clk_i(clk_i), - .req_i(data_req_ic0 & data_banks_ic0[way]), - .write_i(data_write_ic0), - .wmask_i({LINE_SIZE_ECC {1'b1}}), - .addr_i(data_index_ic0), - .wdata_i(data_wdata_ic0), - .rdata_o(data_rdata_ic1[way]) - ); - end - endgenerate - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - lookup_valid_ic1 <= 1'b0; - else - lookup_valid_ic1 <= lookup_actual_ic0; - always @(posedge clk_i) - if (lookup_grant_ic0) begin - lookup_addr_ic1 <= lookup_addr_ic0[ADDR_W - 1:INDEX_HI + 1]; - fill_in_ic1 <= fill_alloc_sel; - end - generate - for (way = 0; way < NumWays; way = way + 1) begin : gen_tag_match - assign tag_match_ic1[way] = tag_rdata_ic1[way][TAG_SIZE - 1:0] == {1'b1, lookup_addr_ic1[ADDR_W - 1:INDEX_HI + 1]}; - assign tag_invalid_ic1[way] = ~tag_rdata_ic1[way][TAG_SIZE - 1]; - end - endgenerate - assign tag_hit_ic1 = |tag_match_ic1; - always @(*) begin - hit_data_ic1 = 'b0; - begin : sv2v_autoblock_1 - reg signed [31:0] way; - for (way = 0; way < NumWays; way = way + 1) - if (tag_match_ic1[way]) - hit_data_ic1 = hit_data_ic1 | data_rdata_ic1[way]; - end - end - assign lowest_invalid_way_ic1[0] = tag_invalid_ic1[0]; - assign round_robin_way_ic1[0] = round_robin_way_q[NumWays - 1]; - generate - for (way = 1; way < NumWays; way = way + 1) begin : gen_lowest_way - assign lowest_invalid_way_ic1[way] = tag_invalid_ic1[way] & ~|tag_invalid_ic1[way - 1:0]; - assign round_robin_way_ic1[way] = round_robin_way_q[way - 1]; - end - endgenerate - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - round_robin_way_q <= {{NumWays - 1 {1'b0}}, 1'b1}; - else if (lookup_valid_ic1) - round_robin_way_q <= round_robin_way_ic1; - assign sel_way_ic1 = (|tag_invalid_ic1 ? lowest_invalid_way_ic1 : round_robin_way_q); - generate - if (ICacheECC) begin : gen_data_ecc_checking - wire [NumWays - 1:0] tag_err_ic1; - wire [1:0] data_err_ic1; - wire ecc_correction_write_d; - reg ecc_correction_write_q; - wire [NumWays - 1:0] ecc_correction_ways_d; - reg [NumWays - 1:0] ecc_correction_ways_q; - reg [INDEX_W - 1:0] lookup_index_ic1; - reg [INDEX_W - 1:0] ecc_correction_index_q; - for (way = 0; way < NumWays; way = way + 1) begin : gen_tag_ecc - wire [1:0] tag_err_bank_ic1; - wire [27:0] tag_rdata_padded_ic1; - assign tag_rdata_padded_ic1 = {tag_rdata_ic1[way][TAG_SIZE_ECC - 1-:6], {22 - TAG_SIZE {1'b0}}, tag_rdata_ic1[way][TAG_SIZE - 1:0]}; - prim_secded_28_22_dec data_ecc_dec( - .in(tag_rdata_padded_ic1), - .d_o(), - .syndrome_o(), - .err_o(tag_err_bank_ic1) - ); - assign tag_err_ic1[way] = |tag_err_bank_ic1; - end - prim_secded_72_64_dec data_ecc_dec( - .in(hit_data_ic1), - .d_o(), - .syndrome_o(), - .err_o(data_err_ic1) - ); - assign ecc_err_ic1 = lookup_valid_ic1 & (|data_err_ic1 | |tag_err_ic1); - assign ecc_correction_ways_d = {NumWays {|tag_err_ic1}} | (tag_match_ic1 & {NumWays {|data_err_ic1}}); - assign ecc_correction_write_d = ecc_err_ic1; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - ecc_correction_write_q <= 1'b0; - else - ecc_correction_write_q <= ecc_correction_write_d; - always @(posedge clk_i) - if (lookup_grant_ic0) - lookup_index_ic1 <= lookup_addr_ic0[INDEX_HI-:INDEX_W]; - always @(posedge clk_i) - if (ecc_err_ic1) begin - ecc_correction_ways_q <= ecc_correction_ways_d; - ecc_correction_index_q <= lookup_index_ic1; - end - assign ecc_write_req = ecc_correction_write_q; - assign ecc_write_ways = ecc_correction_ways_q; - assign ecc_write_index = ecc_correction_index_q; - end - else begin : gen_no_data_ecc - assign ecc_err_ic1 = 1'b0; - assign ecc_write_req = 1'b0; - assign ecc_write_ways = {NumWays {1'sb0}}; - assign ecc_write_index = {INDEX_W {1'sb0}}; - end - endgenerate - generate - if (BranchCache) begin : gen_caching_logic - localparam [31:0] CACHE_AHEAD = 2; - localparam [31:0] CACHE_CNT_W = (CACHE_AHEAD == 1 ? 1 : 2); - wire cache_cnt_dec; - wire [CACHE_CNT_W - 1:0] cache_cnt_d; - reg [CACHE_CNT_W - 1:0] cache_cnt_q; - assign cache_cnt_dec = lookup_grant_ic0 & |cache_cnt_q; - assign cache_cnt_d = (branch_i ? CACHE_AHEAD[CACHE_CNT_W - 1:0] : cache_cnt_q - {{CACHE_CNT_W - 1 {1'b0}}, cache_cnt_dec}); - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - cache_cnt_q <= {CACHE_CNT_W {1'sb0}}; - else - cache_cnt_q <= cache_cnt_d; - assign fill_cache_new = (((branch_i | |cache_cnt_q) & icache_enable_i) & ~icache_inval_i) & ~inval_prog_q; - end - else begin : gen_cache_all - assign fill_cache_new = (icache_enable_i & ~start_inval) & ~inval_prog_q; - end - endgenerate - always @(*) begin - fb_fill_level = {2 {1'sb0}}; - begin : sv2v_autoblock_2 - reg signed [31:0] i; - for (i = 0; i < NUM_FB; i = i + 1) - if (fill_busy_q[i] & ~fill_stale_q[i]) - fb_fill_level = fb_fill_level + {1'b0, 1'b1}; - end - end - assign gnt_or_pmp_err = instr_gnt_i | instr_pmp_err_i; - assign gnt_not_pmp_err = instr_gnt_i & ~instr_pmp_err_i; - assign fill_new_alloc = lookup_grant_ic0; - assign fill_spec_req = (SpecRequest | branch_i) & ~|fill_ext_req; - assign fill_spec_done = fill_spec_req & gnt_not_pmp_err; - assign fill_spec_hold = fill_spec_req & ~gnt_or_pmp_err; - generate - genvar fb; - for (fb = 0; fb < NUM_FB; fb = fb + 1) begin : gen_fbs - if (fb == 0) begin : gen_fb_zero - assign fill_alloc_sel[fb] = ~fill_busy_q[fb]; - end - else begin : gen_fb_rest - assign fill_alloc_sel[fb] = ~fill_busy_q[fb] & &fill_busy_q[fb - 1:0]; - end - assign fill_alloc[fb] = fill_alloc_sel[fb] & fill_new_alloc; - assign fill_busy_d[fb] = fill_alloc[fb] | (fill_busy_q[fb] & ~fill_done[fb]); - assign fill_older_d[fb * NUM_FB+:NUM_FB] = (fill_alloc[fb] ? fill_busy_q : fill_older_q[fb * NUM_FB+:NUM_FB]) & ~fill_done; - assign fill_done[fb] = ((((fill_ram_done_q[fb] | fill_hit_q[fb]) | ~fill_cache_q[fb]) | |fill_err_q[fb * LINE_BEATS+:LINE_BEATS]) & ((fill_out_done[fb] | fill_stale_q[fb]) | branch_i)) & fill_rvd_done[fb]; - assign fill_stale_d[fb] = fill_busy_q[fb] & (branch_i | fill_stale_q[fb]); - assign fill_cache_d[fb] = (fill_alloc[fb] & fill_cache_new) | (((fill_cache_q[fb] & fill_busy_q[fb]) & icache_enable_i) & ~icache_inval_i); - assign fill_hit_ic1[fb] = ((lookup_valid_ic1 & fill_in_ic1[fb]) & tag_hit_ic1) & ~ecc_err_ic1; - assign fill_hit_d[fb] = fill_hit_ic1[fb] | (fill_hit_q[fb] & fill_busy_q[fb]); - assign fill_ext_req[fb] = fill_busy_q[fb] & ~fill_ext_done[fb]; - assign fill_ext_cnt_d[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] = (fill_alloc[fb] ? {{LINE_BEATS_W {1'b0}}, fill_spec_done} : fill_ext_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] + {{LINE_BEATS_W {1'b0}}, fill_ext_arb[fb] & gnt_not_pmp_err}); - assign fill_ext_hold_d[fb] = (fill_alloc[fb] & fill_spec_hold) | (fill_ext_arb[fb] & ~gnt_or_pmp_err); - assign fill_ext_done[fb] = ((((fill_ext_cnt_q[(fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W : LINE_BEATS_W - LINE_BEATS_W)] | fill_hit_ic1[fb]) | fill_hit_q[fb]) | fill_err_q[(fb * LINE_BEATS) + fill_ext_off[fb * LINE_BEATS_W+:LINE_BEATS_W]]) | (~fill_cache_q[fb] & (branch_i | fill_stale_q[fb]))) & ~fill_ext_hold_q[fb]; - assign fill_rvd_exp[fb] = fill_busy_q[fb] & ~fill_rvd_done[fb]; - assign fill_rvd_cnt_d[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] = (fill_alloc[fb] ? {(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W) {1'sb0}} : fill_rvd_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] + {{LINE_BEATS_W {1'b0}}, fill_rvd_arb[fb]}); - assign fill_rvd_done[fb] = fill_ext_done[fb] & (fill_rvd_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] == fill_ext_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)]); - assign fill_out_req[fb] = ((fill_busy_q[fb] & ~fill_stale_q[fb]) & ~fill_out_done[fb]) & ((((fill_hit_ic1[fb] | fill_hit_q[fb]) | fill_err_q[(fb * LINE_BEATS) + fill_out_cnt_q[(LINE_BEATS_W >= 0 ? (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W - 1 : LINE_BEATS_W - (LINE_BEATS_W - 1)) : (((fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W - 1 : LINE_BEATS_W - (LINE_BEATS_W - 1))) + LINE_BEATS_W) - 1)-:LINE_BEATS_W]]) | (fill_rvd_beat[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] > fill_out_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)])) | fill_rvd_arb[fb]); - assign fill_out_grant[fb] = fill_out_arb[fb] & output_ready; - assign fill_out_cnt_d[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] = (fill_alloc[fb] ? {1'b0, lookup_addr_ic0[LINE_W - 1:BUS_W]} : fill_out_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] + {{LINE_BEATS_W {1'b0}}, fill_out_grant[fb]}); - assign fill_out_done[fb] = fill_out_cnt_q[(fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W : LINE_BEATS_W - LINE_BEATS_W)]; - assign fill_ram_req[fb] = ((((fill_busy_q[fb] & fill_rvd_cnt_q[(fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W : LINE_BEATS_W - LINE_BEATS_W)]) & ~fill_hit_q[fb]) & fill_cache_q[fb]) & ~|fill_err_q[fb * LINE_BEATS+:LINE_BEATS]) & ~fill_ram_done_q[fb]; - assign fill_ram_done_d[fb] = fill_ram_arb[fb] | (fill_ram_done_q[fb] & fill_busy_q[fb]); - assign fill_rvd_beat[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] = {1'b0, fill_addr_q[fb][LINE_W - 1:BUS_W]} + fill_rvd_cnt_q[(LINE_BEATS_W >= 0 ? (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? (LINE_BEATS_W >= 0 ? LINE_BEATS_W : (LINE_BEATS_W + (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) - 1) : LINE_BEATS_W - (LINE_BEATS_W >= 0 ? LINE_BEATS_W : (LINE_BEATS_W + (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) - 1)) : (((fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? (LINE_BEATS_W >= 0 ? LINE_BEATS_W : (LINE_BEATS_W + (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) - 1) : LINE_BEATS_W - (LINE_BEATS_W >= 0 ? LINE_BEATS_W : (LINE_BEATS_W + (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) - 1))) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) - 1)-:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)]; - assign fill_ext_off[fb * LINE_BEATS_W+:LINE_BEATS_W] = fill_addr_q[fb][LINE_W - 1:BUS_W] + fill_ext_cnt_q[(LINE_BEATS_W >= 0 ? (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W - 1 : LINE_BEATS_W - (LINE_BEATS_W - 1)) : (((fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W - 1 : LINE_BEATS_W - (LINE_BEATS_W - 1))) + LINE_BEATS_W) - 1)-:LINE_BEATS_W]; - assign fill_rvd_off[fb * LINE_BEATS_W+:LINE_BEATS_W] = fill_rvd_beat[(LINE_BEATS_W >= 0 ? (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W - 1 : LINE_BEATS_W - (LINE_BEATS_W - 1)) : (((fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W - 1 : LINE_BEATS_W - (LINE_BEATS_W - 1))) + LINE_BEATS_W) - 1)-:LINE_BEATS_W]; - assign fill_ext_arb[fb] = fill_ext_req[fb] & ~|(fill_ext_req & fill_older_q[fb * NUM_FB+:NUM_FB]); - assign fill_ram_arb[fb] = (fill_ram_req[fb] & fill_grant_ic0) & ~|(fill_ram_req & fill_older_q[fb * NUM_FB+:NUM_FB]); - assign fill_data_sel[fb] = ~|(((fill_busy_q & ~fill_out_done) & ~fill_stale_q) & fill_older_q[fb * NUM_FB+:NUM_FB]); - assign fill_out_arb[fb] = fill_out_req[fb] & fill_data_sel[fb]; - assign fill_rvd_arb[fb] = (instr_rvalid_i & fill_rvd_exp[fb]) & ~|(fill_rvd_exp & fill_older_q[fb * NUM_FB+:NUM_FB]); - assign fill_data_reg[fb] = (((fill_busy_q[fb] & ~fill_stale_q[fb]) & ~fill_out_done[fb]) & fill_data_sel[fb]) & (((fill_rvd_beat[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] > fill_out_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)]) | fill_hit_q[fb]) | |fill_err_q[fb * LINE_BEATS+:LINE_BEATS]); - assign fill_data_hit[fb] = (fill_busy_q[fb] & fill_hit_ic1[fb]) & fill_data_sel[fb]; - assign fill_data_rvd[fb] = ((((((fill_busy_q[fb] & fill_rvd_arb[fb]) & ~fill_hit_q[fb]) & ~fill_hit_ic1[fb]) & ~fill_stale_q[fb]) & ~fill_out_done[fb]) & (fill_rvd_beat[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] == fill_out_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)])) & fill_data_sel[fb]; - assign fill_entry_en[fb] = fill_alloc[fb] | fill_busy_q[fb]; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) begin - fill_busy_q[fb] <= 1'b0; - fill_older_q[fb * NUM_FB+:NUM_FB] <= {NUM_FB {1'sb0}}; - fill_stale_q[fb] <= 1'b0; - fill_cache_q[fb] <= 1'b0; - fill_hit_q[fb] <= 1'b0; - fill_ext_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] <= {(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W) {1'sb0}}; - fill_ext_hold_q[fb] <= 1'b0; - fill_rvd_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] <= {(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W) {1'sb0}}; - fill_ram_done_q[fb] <= 1'b0; - fill_out_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] <= {(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W) {1'sb0}}; - end - else if (fill_entry_en[fb]) begin - fill_busy_q[fb] <= fill_busy_d[fb]; - fill_older_q[fb * NUM_FB+:NUM_FB] <= fill_older_d[fb * NUM_FB+:NUM_FB]; - fill_stale_q[fb] <= fill_stale_d[fb]; - fill_cache_q[fb] <= fill_cache_d[fb]; - fill_hit_q[fb] <= fill_hit_d[fb]; - fill_ext_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] <= fill_ext_cnt_d[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)]; - fill_ext_hold_q[fb] <= fill_ext_hold_d[fb]; - fill_rvd_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] <= fill_rvd_cnt_d[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)]; - fill_ram_done_q[fb] <= fill_ram_done_d[fb]; - fill_out_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] <= fill_out_cnt_d[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)]; - end - assign fill_addr_en[fb] = fill_alloc[fb]; - assign fill_way_en[fb] = lookup_valid_ic1 & fill_in_ic1[fb]; - always @(posedge clk_i) - if (fill_addr_en[fb]) - fill_addr_q[fb] <= lookup_addr_ic0; - always @(posedge clk_i) - if (fill_way_en[fb]) - fill_way_q[fb] <= sel_way_ic1; - assign fill_data_d[fb] = (fill_hit_ic1[fb] ? hit_data_ic1[LineSize - 1:0] : {LINE_BEATS {instr_rdata_i}}); - genvar b; - for (b = 0; b < LINE_BEATS; b = b + 1) begin : gen_data_buf - assign fill_err_d[(fb * LINE_BEATS) + b] = (((((instr_pmp_err_i & fill_alloc[fb]) & fill_spec_req) & (lookup_addr_ic0[LINE_W - 1:BUS_W] == b[LINE_BEATS_W - 1:0])) | ((instr_pmp_err_i & fill_ext_arb[fb]) & (fill_ext_off[fb * LINE_BEATS_W+:LINE_BEATS_W] == b[LINE_BEATS_W - 1:0]))) | ((fill_rvd_arb[fb] & instr_err_i) & (fill_rvd_off[fb * LINE_BEATS_W+:LINE_BEATS_W] == b[LINE_BEATS_W - 1:0]))) | (fill_busy_q[fb] & fill_err_q[(fb * LINE_BEATS) + b]); - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - fill_err_q[(fb * LINE_BEATS) + b] <= 1'b0; - else if (fill_entry_en[fb]) - fill_err_q[(fb * LINE_BEATS) + b] <= fill_err_d[(fb * LINE_BEATS) + b]; - assign fill_data_en[(fb * LINE_BEATS) + b] = fill_hit_ic1[fb] | ((fill_rvd_arb[fb] & ~fill_hit_q[fb]) & (fill_rvd_off[fb * LINE_BEATS_W+:LINE_BEATS_W] == b[LINE_BEATS_W - 1:0])); - always @(posedge clk_i) - if (fill_data_en[(fb * LINE_BEATS) + b]) - fill_data_q[fb][b * BusWidth+:BusWidth] <= fill_data_d[fb][b * BusWidth+:BusWidth]; - end - end - endgenerate - always @(*) begin - fill_ext_req_addr = {((ADDR_W - 1) >= BUS_W ? ((ADDR_W - 1) - BUS_W) + 1 : (BUS_W - (ADDR_W - 1)) + 1) {1'sb0}}; - begin : sv2v_autoblock_3 - reg signed [31:0] i; - for (i = 0; i < NUM_FB; i = i + 1) - if (fill_ext_arb[i]) - fill_ext_req_addr = fill_ext_req_addr | {fill_addr_q[i][ADDR_W - 1:LINE_W], fill_ext_off[i * LINE_BEATS_W+:LINE_BEATS_W]}; - end - end - always @(*) begin - fill_ram_req_addr = {ADDR_W {1'sb0}}; - fill_ram_req_way = {NumWays {1'sb0}}; - fill_ram_req_data = {LineSize {1'sb0}}; - begin : sv2v_autoblock_4 - reg signed [31:0] i; - for (i = 0; i < NUM_FB; i = i + 1) - if (fill_ram_arb[i]) begin - fill_ram_req_addr = fill_ram_req_addr | fill_addr_q[i]; - fill_ram_req_way = fill_ram_req_way | fill_way_q[i]; - fill_ram_req_data = fill_ram_req_data | fill_data_q[i]; - end - end - end - always @(*) begin - fill_out_data = {LineSize {1'sb0}}; - fill_out_err = {LINE_BEATS {1'sb0}}; - begin : sv2v_autoblock_5 - reg signed [31:0] i; - for (i = 0; i < NUM_FB; i = i + 1) - if (fill_data_reg[i]) begin - fill_out_data = fill_out_data | fill_data_q[i]; - fill_out_err = fill_out_err | (fill_err_q[i * LINE_BEATS+:LINE_BEATS] & ~{LINE_BEATS {fill_hit_q[i]}}); - end - end - end - assign instr_req = ((SpecRequest | branch_i) & lookup_grant_ic0) | |fill_ext_req; - assign instr_addr = (|fill_ext_req ? fill_ext_req_addr : lookup_addr_ic0[ADDR_W - 1:BUS_W]); - assign instr_req_o = instr_req; - assign instr_addr_o = {instr_addr[ADDR_W - 1:BUS_W], {BUS_W {1'b0}}}; - assign line_data = (|fill_data_hit ? hit_data_ic1[LineSize - 1:0] : fill_out_data); - assign line_err = (|fill_data_hit ? {LINE_BEATS {1'b0}} : fill_out_err); - always @(*) begin - line_data_muxed = {32 {1'sb0}}; - line_err_muxed = 1'b0; - begin : sv2v_autoblock_6 - reg signed [31:0] i; - for (i = 0; i < LINE_BEATS; i = i + 1) - if ((output_addr_q[LINE_W - 1:BUS_W] + {{LINE_BEATS_W - 1 {1'b0}}, skid_valid_q}) == i[LINE_BEATS_W - 1:0]) begin - line_data_muxed = line_data_muxed | line_data[i * 32+:32]; - line_err_muxed = line_err_muxed | line_err[i]; - end - end - end - assign output_data = (|fill_data_rvd ? instr_rdata_i : line_data_muxed); - assign output_err = (|fill_data_rvd ? instr_err_i : line_err_muxed); - assign data_valid = |fill_out_arb; - assign skid_data_d = output_data[31:16]; - assign skid_en = data_valid & (ready_i | skid_ready); - always @(posedge clk_i) - if (skid_en) begin - skid_data_q <= skid_data_d; - skid_err_q <= output_err; - end - assign skid_complete_instr = skid_valid_q & ((skid_data_q[1:0] != 2'b11) | skid_err_q); - assign skid_ready = (output_addr_q[1] & ~skid_valid_q) & (~output_compressed | output_err); - assign output_ready = (ready_i | skid_ready) & ~skid_complete_instr; - assign output_compressed = rdata_o[1:0] != 2'b11; - assign skid_valid_d = (branch_i ? 1'b0 : (skid_valid_q ? ~(ready_i & ((skid_data_q[1:0] != 2'b11) | skid_err_q)) : ((output_addr_q[1] & (~output_compressed | output_err)) | (((~output_addr_q[1] & output_compressed) & ~output_err) & ready_i)) & data_valid)); - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - skid_valid_q <= 1'b0; - else - skid_valid_q <= skid_valid_d; - assign output_valid = skid_complete_instr | (data_valid & (((~output_addr_q[1] | skid_valid_q) | output_err) | (output_data[17:16] != 2'b11))); - assign output_addr_en = branch_i | (ready_i & valid_o); - assign addr_incr_two = output_compressed & ~err_o; - assign output_addr_d = (branch_i ? addr_i[31:1] : output_addr_q[31:1] + {29'd0, ~addr_incr_two, addr_incr_two}); - always @(posedge clk_i) - if (output_addr_en) - output_addr_q <= output_addr_d; - always @(*) begin - output_data_lo = {16 {1'sb0}}; - begin : sv2v_autoblock_7 - reg signed [31:0] i; - for (i = 0; i < OUTPUT_BEATS; i = i + 1) - if (output_addr_q[BUS_W - 1:1] == i[BUS_W - 2:0]) - output_data_lo = output_data_lo | output_data[i * 16+:16]; - end - end - always @(*) begin - output_data_hi = {16 {1'sb0}}; - begin : sv2v_autoblock_8 - reg signed [31:0] i; - for (i = 0; i < (OUTPUT_BEATS - 1); i = i + 1) - if (output_addr_q[BUS_W - 1:1] == i[BUS_W - 2:0]) - output_data_hi = output_data_hi | output_data[(i + 1) * 16+:16]; - end - if (&output_addr_q[BUS_W - 1:1]) - output_data_hi = output_data_hi | output_data[15:0]; - end - assign valid_o = output_valid; - assign rdata_o = {output_data_hi, (skid_valid_q ? skid_data_q : output_data_lo)}; - assign addr_o = {output_addr_q, 1'b0}; - assign err_o = (skid_valid_q & skid_err_q) | (~skid_complete_instr & output_err); - assign err_plus2_o = skid_valid_q & ~skid_err_q; - assign start_inval = (~reset_inval_q | icache_inval_i) & ~inval_prog_q; - assign inval_prog_d = start_inval | (inval_prog_q & ~inval_done); - assign inval_done = &inval_index_q; - assign inval_index_d = (start_inval ? {INDEX_W {1'sb0}} : inval_index_q + {{INDEX_W - 1 {1'b0}}, 1'b1}); - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) begin - inval_prog_q <= 1'b0; - reset_inval_q <= 1'b0; - end - else begin - inval_prog_q <= inval_prog_d; - reset_inval_q <= 1'b1; - end - always @(posedge clk_i) - if (inval_prog_d) - inval_index_q <= inval_index_d; - assign busy_o = inval_prog_q | |(fill_busy_q & ~fill_rvd_done); -endmodule diff --git a/flow/designs/src/ibex/ibex_id_stage.v b/flow/designs/src/ibex/ibex_id_stage.v deleted file mode 100644 index 10187d0c85..0000000000 --- a/flow/designs/src/ibex/ibex_id_stage.v +++ /dev/null @@ -1,751 +0,0 @@ -module ibex_id_stage ( - clk_i, - rst_ni, - ctrl_busy_o, - illegal_insn_o, - instr_valid_i, - instr_rdata_i, - instr_rdata_alu_i, - instr_rdata_c_i, - instr_is_compressed_i, - instr_bp_taken_i, - instr_req_o, - instr_first_cycle_id_o, - instr_valid_clear_o, - id_in_ready_o, - icache_inval_o, - branch_decision_i, - pc_set_o, - pc_set_spec_o, - pc_mux_o, - nt_branch_mispredict_o, - exc_pc_mux_o, - exc_cause_o, - illegal_c_insn_i, - instr_fetch_err_i, - instr_fetch_err_plus2_i, - pc_id_i, - ex_valid_i, - lsu_resp_valid_i, - alu_operator_ex_o, - alu_operand_a_ex_o, - alu_operand_b_ex_o, - imd_val_we_ex_i, - imd_val_d_ex_i, - imd_val_q_ex_o, - bt_a_operand_o, - bt_b_operand_o, - mult_en_ex_o, - div_en_ex_o, - mult_sel_ex_o, - div_sel_ex_o, - multdiv_operator_ex_o, - multdiv_signed_mode_ex_o, - multdiv_operand_a_ex_o, - multdiv_operand_b_ex_o, - multdiv_ready_id_o, - csr_access_o, - csr_op_o, - csr_op_en_o, - csr_save_if_o, - csr_save_id_o, - csr_save_wb_o, - csr_restore_mret_id_o, - csr_restore_dret_id_o, - csr_save_cause_o, - csr_mtval_o, - priv_mode_i, - csr_mstatus_tw_i, - illegal_csr_insn_i, - data_ind_timing_i, - lsu_req_o, - lsu_we_o, - lsu_type_o, - lsu_sign_ext_o, - lsu_wdata_o, - lsu_req_done_i, - lsu_addr_incr_req_i, - lsu_addr_last_i, - csr_mstatus_mie_i, - irq_pending_i, - irqs_i, - irq_nm_i, - nmi_mode_o, - lsu_load_err_i, - lsu_store_err_i, - debug_mode_o, - debug_cause_o, - debug_csr_save_o, - debug_req_i, - debug_single_step_i, - debug_ebreakm_i, - debug_ebreaku_i, - trigger_match_i, - result_ex_i, - csr_rdata_i, - rf_raddr_a_o, - rf_rdata_a_i, - rf_raddr_b_o, - rf_rdata_b_i, - rf_ren_a_o, - rf_ren_b_o, - rf_waddr_id_o, - rf_wdata_id_o, - rf_we_id_o, - rf_rd_a_wb_match_o, - rf_rd_b_wb_match_o, - rf_waddr_wb_i, - rf_wdata_fwd_wb_i, - rf_write_wb_i, - en_wb_o, - instr_type_wb_o, - instr_perf_count_id_o, - ready_wb_i, - outstanding_load_wb_i, - outstanding_store_wb_i, - perf_jump_o, - perf_branch_o, - perf_tbranch_o, - perf_dside_wait_o, - perf_mul_wait_o, - perf_div_wait_o, - instr_id_done_o -); - parameter [0:0] RV32E = 0; - localparam integer ibex_pkg_RV32MFast = 2; - parameter integer RV32M = ibex_pkg_RV32MFast; - localparam integer ibex_pkg_RV32BNone = 0; - parameter integer RV32B = ibex_pkg_RV32BNone; - parameter [0:0] DataIndTiming = 1'b0; - parameter [0:0] BranchTargetALU = 0; - parameter [0:0] SpecBranch = 0; - parameter [0:0] WritebackStage = 0; - parameter [0:0] BranchPredictor = 0; - input wire clk_i; - input wire rst_ni; - output wire ctrl_busy_o; - output wire illegal_insn_o; - input wire instr_valid_i; - input wire [31:0] instr_rdata_i; - input wire [31:0] instr_rdata_alu_i; - input wire [15:0] instr_rdata_c_i; - input wire instr_is_compressed_i; - input wire instr_bp_taken_i; - output wire instr_req_o; - output wire instr_first_cycle_id_o; - output wire instr_valid_clear_o; - output wire id_in_ready_o; - output wire icache_inval_o; - input wire branch_decision_i; - output wire pc_set_o; - output wire pc_set_spec_o; - output wire [2:0] pc_mux_o; - output wire nt_branch_mispredict_o; - output wire [1:0] exc_pc_mux_o; - output wire [5:0] exc_cause_o; - input wire illegal_c_insn_i; - input wire instr_fetch_err_i; - input wire instr_fetch_err_plus2_i; - input wire [31:0] pc_id_i; - input wire ex_valid_i; - input wire lsu_resp_valid_i; - output wire [5:0] alu_operator_ex_o; - output wire [31:0] alu_operand_a_ex_o; - output wire [31:0] alu_operand_b_ex_o; - input wire [1:0] imd_val_we_ex_i; - input wire [67:0] imd_val_d_ex_i; - output wire [67:0] imd_val_q_ex_o; - output reg [31:0] bt_a_operand_o; - output reg [31:0] bt_b_operand_o; - output wire mult_en_ex_o; - output wire div_en_ex_o; - output wire mult_sel_ex_o; - output wire div_sel_ex_o; - output wire [1:0] multdiv_operator_ex_o; - output wire [1:0] multdiv_signed_mode_ex_o; - output wire [31:0] multdiv_operand_a_ex_o; - output wire [31:0] multdiv_operand_b_ex_o; - output wire multdiv_ready_id_o; - output wire csr_access_o; - output wire [1:0] csr_op_o; - output wire csr_op_en_o; - output wire csr_save_if_o; - output wire csr_save_id_o; - output wire csr_save_wb_o; - output wire csr_restore_mret_id_o; - output wire csr_restore_dret_id_o; - output wire csr_save_cause_o; - output wire [31:0] csr_mtval_o; - input wire [1:0] priv_mode_i; - input wire csr_mstatus_tw_i; - input wire illegal_csr_insn_i; - input wire data_ind_timing_i; - output wire lsu_req_o; - output wire lsu_we_o; - output wire [1:0] lsu_type_o; - output wire lsu_sign_ext_o; - output wire [31:0] lsu_wdata_o; - input wire lsu_req_done_i; - input wire lsu_addr_incr_req_i; - input wire [31:0] lsu_addr_last_i; - input wire csr_mstatus_mie_i; - input wire irq_pending_i; - input wire [17:0] irqs_i; - input wire irq_nm_i; - output wire nmi_mode_o; - input wire lsu_load_err_i; - input wire lsu_store_err_i; - output wire debug_mode_o; - output wire [2:0] debug_cause_o; - output wire debug_csr_save_o; - input wire debug_req_i; - input wire debug_single_step_i; - input wire debug_ebreakm_i; - input wire debug_ebreaku_i; - input wire trigger_match_i; - input wire [31:0] result_ex_i; - input wire [31:0] csr_rdata_i; - output wire [4:0] rf_raddr_a_o; - input wire [31:0] rf_rdata_a_i; - output wire [4:0] rf_raddr_b_o; - input wire [31:0] rf_rdata_b_i; - output wire rf_ren_a_o; - output wire rf_ren_b_o; - output wire [4:0] rf_waddr_id_o; - output reg [31:0] rf_wdata_id_o; - output wire rf_we_id_o; - output wire rf_rd_a_wb_match_o; - output wire rf_rd_b_wb_match_o; - input wire [4:0] rf_waddr_wb_i; - input wire [31:0] rf_wdata_fwd_wb_i; - input wire rf_write_wb_i; - output wire en_wb_o; - output wire [1:0] instr_type_wb_o; - output wire instr_perf_count_id_o; - input wire ready_wb_i; - input wire outstanding_load_wb_i; - input wire outstanding_store_wb_i; - output wire perf_jump_o; - output reg perf_branch_o; - output wire perf_tbranch_o; - output wire perf_dside_wait_o; - output wire perf_mul_wait_o; - output wire perf_div_wait_o; - output wire instr_id_done_o; - wire illegal_insn_dec; - wire ebrk_insn; - wire mret_insn_dec; - wire dret_insn_dec; - wire ecall_insn_dec; - wire wfi_insn_dec; - wire wb_exception; - wire branch_in_dec; - reg branch_spec; - wire branch_set_spec; - wire branch_set; - reg branch_set_d; - reg branch_not_set; - wire branch_taken; - wire jump_in_dec; - wire jump_set_dec; - reg jump_set; - wire instr_first_cycle; - wire instr_executing; - wire instr_done; - wire controller_run; - wire stall_ld_hz; - wire stall_mem; - reg stall_multdiv; - reg stall_branch; - reg stall_jump; - wire stall_id; - wire stall_wb; - wire flush_id; - wire multicycle_done; - wire [31:0] imm_i_type; - wire [31:0] imm_s_type; - wire [31:0] imm_b_type; - wire [31:0] imm_u_type; - wire [31:0] imm_j_type; - wire [31:0] zimm_rs1_type; - wire [31:0] imm_a; - reg [31:0] imm_b; - wire rf_wdata_sel; - wire rf_we_dec; - reg rf_we_raw; - wire rf_ren_a; - wire rf_ren_b; - assign rf_ren_a_o = rf_ren_a; - assign rf_ren_b_o = rf_ren_b; - wire [31:0] rf_rdata_a_fwd; - wire [31:0] rf_rdata_b_fwd; - wire [5:0] alu_operator; - wire [1:0] alu_op_a_mux_sel; - wire [1:0] alu_op_a_mux_sel_dec; - wire alu_op_b_mux_sel; - wire alu_op_b_mux_sel_dec; - wire alu_multicycle_dec; - reg stall_alu; - reg [67:0] imd_val_q; - wire [1:0] bt_a_mux_sel; - wire [2:0] bt_b_mux_sel; - wire imm_a_mux_sel; - wire [2:0] imm_b_mux_sel; - wire [2:0] imm_b_mux_sel_dec; - wire mult_en_id; - wire mult_en_dec; - wire div_en_id; - wire div_en_dec; - wire multdiv_en_dec; - wire [1:0] multdiv_operator; - wire [1:0] multdiv_signed_mode; - wire lsu_we; - wire [1:0] lsu_type; - wire lsu_sign_ext; - wire lsu_req; - wire lsu_req_dec; - wire data_req_allowed; - reg csr_pipe_flush; - reg [31:0] alu_operand_a; - wire [31:0] alu_operand_b; - localparam [1:0] ibex_pkg_OP_A_FWD = 1; - assign alu_op_a_mux_sel = (lsu_addr_incr_req_i ? ibex_pkg_OP_A_FWD : alu_op_a_mux_sel_dec); - localparam [0:0] ibex_pkg_OP_B_IMM = 1; - assign alu_op_b_mux_sel = (lsu_addr_incr_req_i ? ibex_pkg_OP_B_IMM : alu_op_b_mux_sel_dec); - localparam [2:0] ibex_pkg_IMM_B_INCR_ADDR = 6; - assign imm_b_mux_sel = (lsu_addr_incr_req_i ? ibex_pkg_IMM_B_INCR_ADDR : imm_b_mux_sel_dec); - localparam [0:0] ibex_pkg_IMM_A_Z = 0; - assign imm_a = (imm_a_mux_sel == ibex_pkg_IMM_A_Z ? zimm_rs1_type : {32 {1'sb0}}); - localparam [1:0] ibex_pkg_OP_A_CURRPC = 2; - localparam [1:0] ibex_pkg_OP_A_IMM = 3; - localparam [1:0] ibex_pkg_OP_A_REG_A = 0; - always @(*) begin : alu_operand_a_mux - case (alu_op_a_mux_sel) - ibex_pkg_OP_A_REG_A: alu_operand_a = rf_rdata_a_fwd; - ibex_pkg_OP_A_FWD: alu_operand_a = lsu_addr_last_i; - ibex_pkg_OP_A_CURRPC: alu_operand_a = pc_id_i; - ibex_pkg_OP_A_IMM: alu_operand_a = imm_a; - default: alu_operand_a = pc_id_i; - endcase - end - localparam [2:0] ibex_pkg_IMM_B_B = 2; - localparam [2:0] ibex_pkg_IMM_B_I = 0; - localparam [2:0] ibex_pkg_IMM_B_INCR_PC = 5; - localparam [2:0] ibex_pkg_IMM_B_J = 4; - localparam [2:0] ibex_pkg_IMM_B_S = 1; - localparam [2:0] ibex_pkg_IMM_B_U = 3; - generate - if (BranchTargetALU) begin : g_btalu_muxes - always @(*) begin : bt_operand_a_mux - case (bt_a_mux_sel) - ibex_pkg_OP_A_REG_A: bt_a_operand_o = rf_rdata_a_fwd; - ibex_pkg_OP_A_CURRPC: bt_a_operand_o = pc_id_i; - default: bt_a_operand_o = pc_id_i; - endcase - end - always @(*) begin : bt_immediate_b_mux - case (bt_b_mux_sel) - ibex_pkg_IMM_B_I: bt_b_operand_o = imm_i_type; - ibex_pkg_IMM_B_B: bt_b_operand_o = imm_b_type; - ibex_pkg_IMM_B_J: bt_b_operand_o = imm_j_type; - ibex_pkg_IMM_B_INCR_PC: bt_b_operand_o = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004); - default: bt_b_operand_o = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004); - endcase - end - always @(*) begin : immediate_b_mux - case (imm_b_mux_sel) - ibex_pkg_IMM_B_I: imm_b = imm_i_type; - ibex_pkg_IMM_B_S: imm_b = imm_s_type; - ibex_pkg_IMM_B_U: imm_b = imm_u_type; - ibex_pkg_IMM_B_INCR_PC: imm_b = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004); - ibex_pkg_IMM_B_INCR_ADDR: imm_b = 32'h00000004; - default: imm_b = 32'h00000004; - endcase - end - end - else begin : g_nobtalu - wire [1:0] unused_a_mux_sel; - wire [2:0] unused_b_mux_sel; - assign unused_a_mux_sel = bt_a_mux_sel; - assign unused_b_mux_sel = bt_b_mux_sel; - wire [32:1] sv2v_tmp_456A8; - assign sv2v_tmp_456A8 = {32 {1'sb0}}; - always @(*) bt_a_operand_o = sv2v_tmp_456A8; - wire [32:1] sv2v_tmp_EDBFD; - assign sv2v_tmp_EDBFD = {32 {1'sb0}}; - always @(*) bt_b_operand_o = sv2v_tmp_EDBFD; - always @(*) begin : immediate_b_mux - case (imm_b_mux_sel) - ibex_pkg_IMM_B_I: imm_b = imm_i_type; - ibex_pkg_IMM_B_S: imm_b = imm_s_type; - ibex_pkg_IMM_B_B: imm_b = imm_b_type; - ibex_pkg_IMM_B_U: imm_b = imm_u_type; - ibex_pkg_IMM_B_J: imm_b = imm_j_type; - ibex_pkg_IMM_B_INCR_PC: imm_b = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004); - ibex_pkg_IMM_B_INCR_ADDR: imm_b = 32'h00000004; - default: imm_b = 32'h00000004; - endcase - end - end - endgenerate - assign alu_operand_b = (alu_op_b_mux_sel == ibex_pkg_OP_B_IMM ? imm_b : rf_rdata_b_fwd); - generate - genvar i; - for (i = 0; i < 2; i = i + 1) begin : gen_intermediate_val_reg - always @(posedge clk_i or negedge rst_ni) begin : intermediate_val_reg - if (!rst_ni) - imd_val_q[(1 - i) * 34+:34] <= {34 {1'sb0}}; - else if (imd_val_we_ex_i[i]) - imd_val_q[(1 - i) * 34+:34] <= imd_val_d_ex_i[(1 - i) * 34+:34]; - end - end - endgenerate - assign imd_val_q_ex_o = imd_val_q; - assign rf_we_id_o = (rf_we_raw & instr_executing) & ~illegal_csr_insn_i; - localparam [0:0] ibex_pkg_RF_WD_CSR = 1; - localparam [0:0] ibex_pkg_RF_WD_EX = 0; - always @(*) begin : rf_wdata_id_mux - case (rf_wdata_sel) - ibex_pkg_RF_WD_EX: rf_wdata_id_o = result_ex_i; - ibex_pkg_RF_WD_CSR: rf_wdata_id_o = csr_rdata_i; - default: rf_wdata_id_o = result_ex_i; - endcase - end - ibex_decoder #( - .RV32E(RV32E), - .RV32M(RV32M), - .RV32B(RV32B), - .BranchTargetALU(BranchTargetALU) - ) decoder_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .illegal_insn_o(illegal_insn_dec), - .ebrk_insn_o(ebrk_insn), - .mret_insn_o(mret_insn_dec), - .dret_insn_o(dret_insn_dec), - .ecall_insn_o(ecall_insn_dec), - .wfi_insn_o(wfi_insn_dec), - .jump_set_o(jump_set_dec), - .branch_taken_i(branch_taken), - .icache_inval_o(icache_inval_o), - .instr_first_cycle_i(instr_first_cycle), - .instr_rdata_i(instr_rdata_i), - .instr_rdata_alu_i(instr_rdata_alu_i), - .illegal_c_insn_i(illegal_c_insn_i), - .imm_a_mux_sel_o(imm_a_mux_sel), - .imm_b_mux_sel_o(imm_b_mux_sel_dec), - .bt_a_mux_sel_o(bt_a_mux_sel), - .bt_b_mux_sel_o(bt_b_mux_sel), - .imm_i_type_o(imm_i_type), - .imm_s_type_o(imm_s_type), - .imm_b_type_o(imm_b_type), - .imm_u_type_o(imm_u_type), - .imm_j_type_o(imm_j_type), - .zimm_rs1_type_o(zimm_rs1_type), - .rf_wdata_sel_o(rf_wdata_sel), - .rf_we_o(rf_we_dec), - .rf_raddr_a_o(rf_raddr_a_o), - .rf_raddr_b_o(rf_raddr_b_o), - .rf_waddr_o(rf_waddr_id_o), - .rf_ren_a_o(rf_ren_a), - .rf_ren_b_o(rf_ren_b), - .alu_operator_o(alu_operator), - .alu_op_a_mux_sel_o(alu_op_a_mux_sel_dec), - .alu_op_b_mux_sel_o(alu_op_b_mux_sel_dec), - .alu_multicycle_o(alu_multicycle_dec), - .mult_en_o(mult_en_dec), - .div_en_o(div_en_dec), - .mult_sel_o(mult_sel_ex_o), - .div_sel_o(div_sel_ex_o), - .multdiv_operator_o(multdiv_operator), - .multdiv_signed_mode_o(multdiv_signed_mode), - .csr_access_o(csr_access_o), - .csr_op_o(csr_op_o), - .data_req_o(lsu_req_dec), - .data_we_o(lsu_we), - .data_type_o(lsu_type), - .data_sign_extension_o(lsu_sign_ext), - .jump_in_dec_o(jump_in_dec), - .branch_in_dec_o(branch_in_dec) - ); - localparam [11:0] ibex_pkg_CSR_DCSR = 12'h7b0; - localparam [11:0] ibex_pkg_CSR_DPC = 12'h7b1; - localparam [11:0] ibex_pkg_CSR_DSCRATCH0 = 12'h7b2; - localparam [11:0] ibex_pkg_CSR_DSCRATCH1 = 12'h7b3; - localparam [11:0] ibex_pkg_CSR_MIE = 12'h304; - localparam [11:0] ibex_pkg_CSR_MSTATUS = 12'h300; - localparam [1:0] ibex_pkg_CSR_OP_READ = 0; - localparam [1:0] ibex_pkg_CSR_OP_SET = 2; - localparam [1:0] ibex_pkg_CSR_OP_WRITE = 1; - always @(*) begin : csr_pipeline_flushes - csr_pipe_flush = 1'b0; - if ((csr_op_en_o == 1'b1) && ((csr_op_o == ibex_pkg_CSR_OP_WRITE) || (csr_op_o == ibex_pkg_CSR_OP_SET))) begin - if ((instr_rdata_i[31:20] == ibex_pkg_CSR_MSTATUS) || (instr_rdata_i[31:20] == ibex_pkg_CSR_MIE)) - csr_pipe_flush = 1'b1; - end - else if ((csr_op_en_o == 1'b1) && (csr_op_o != ibex_pkg_CSR_OP_READ)) - if ((((instr_rdata_i[31:20] == ibex_pkg_CSR_DCSR) || (instr_rdata_i[31:20] == ibex_pkg_CSR_DPC)) || (instr_rdata_i[31:20] == ibex_pkg_CSR_DSCRATCH0)) || (instr_rdata_i[31:20] == ibex_pkg_CSR_DSCRATCH1)) - csr_pipe_flush = 1'b1; - end - assign illegal_insn_o = instr_valid_i & (illegal_insn_dec | illegal_csr_insn_i); - ibex_controller #( - .WritebackStage(WritebackStage), - .BranchPredictor(BranchPredictor) - ) controller_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .ctrl_busy_o(ctrl_busy_o), - .illegal_insn_i(illegal_insn_o), - .ecall_insn_i(ecall_insn_dec), - .mret_insn_i(mret_insn_dec), - .dret_insn_i(dret_insn_dec), - .wfi_insn_i(wfi_insn_dec), - .ebrk_insn_i(ebrk_insn), - .csr_pipe_flush_i(csr_pipe_flush), - .instr_valid_i(instr_valid_i), - .instr_i(instr_rdata_i), - .instr_compressed_i(instr_rdata_c_i), - .instr_is_compressed_i(instr_is_compressed_i), - .instr_bp_taken_i(instr_bp_taken_i), - .instr_fetch_err_i(instr_fetch_err_i), - .instr_fetch_err_plus2_i(instr_fetch_err_plus2_i), - .pc_id_i(pc_id_i), - .instr_valid_clear_o(instr_valid_clear_o), - .id_in_ready_o(id_in_ready_o), - .controller_run_o(controller_run), - .instr_req_o(instr_req_o), - .pc_set_o(pc_set_o), - .pc_set_spec_o(pc_set_spec_o), - .pc_mux_o(pc_mux_o), - .nt_branch_mispredict_o(nt_branch_mispredict_o), - .exc_pc_mux_o(exc_pc_mux_o), - .exc_cause_o(exc_cause_o), - .lsu_addr_last_i(lsu_addr_last_i), - .load_err_i(lsu_load_err_i), - .store_err_i(lsu_store_err_i), - .wb_exception_o(wb_exception), - .branch_set_i(branch_set), - .branch_set_spec_i(branch_set_spec), - .branch_not_set_i(branch_not_set), - .jump_set_i(jump_set), - .csr_mstatus_mie_i(csr_mstatus_mie_i), - .irq_pending_i(irq_pending_i), - .irqs_i(irqs_i), - .irq_nm_i(irq_nm_i), - .nmi_mode_o(nmi_mode_o), - .csr_save_if_o(csr_save_if_o), - .csr_save_id_o(csr_save_id_o), - .csr_save_wb_o(csr_save_wb_o), - .csr_restore_mret_id_o(csr_restore_mret_id_o), - .csr_restore_dret_id_o(csr_restore_dret_id_o), - .csr_save_cause_o(csr_save_cause_o), - .csr_mtval_o(csr_mtval_o), - .priv_mode_i(priv_mode_i), - .csr_mstatus_tw_i(csr_mstatus_tw_i), - .debug_mode_o(debug_mode_o), - .debug_cause_o(debug_cause_o), - .debug_csr_save_o(debug_csr_save_o), - .debug_req_i(debug_req_i), - .debug_single_step_i(debug_single_step_i), - .debug_ebreakm_i(debug_ebreakm_i), - .debug_ebreaku_i(debug_ebreaku_i), - .trigger_match_i(trigger_match_i), - .stall_id_i(stall_id), - .stall_wb_i(stall_wb), - .flush_id_o(flush_id), - .ready_wb_i(ready_wb_i), - .perf_jump_o(perf_jump_o), - .perf_tbranch_o(perf_tbranch_o) - ); - assign multdiv_en_dec = mult_en_dec | div_en_dec; - assign lsu_req = (instr_executing ? data_req_allowed & lsu_req_dec : 1'b0); - assign mult_en_id = (instr_executing ? mult_en_dec : 1'b0); - assign div_en_id = (instr_executing ? div_en_dec : 1'b0); - assign lsu_req_o = lsu_req; - assign lsu_we_o = lsu_we; - assign lsu_type_o = lsu_type; - assign lsu_sign_ext_o = lsu_sign_ext; - assign lsu_wdata_o = rf_rdata_b_fwd; - assign csr_op_en_o = (csr_access_o & instr_executing) & instr_id_done_o; - assign alu_operator_ex_o = alu_operator; - assign alu_operand_a_ex_o = alu_operand_a; - assign alu_operand_b_ex_o = alu_operand_b; - assign mult_en_ex_o = mult_en_id; - assign div_en_ex_o = div_en_id; - assign multdiv_operator_ex_o = multdiv_operator; - assign multdiv_signed_mode_ex_o = multdiv_signed_mode; - assign multdiv_operand_a_ex_o = rf_rdata_a_fwd; - assign multdiv_operand_b_ex_o = rf_rdata_b_fwd; - generate - if (BranchTargetALU && !DataIndTiming) begin : g_branch_set_direct - assign branch_set = branch_set_d; - assign branch_set_spec = branch_spec; - end - else begin : g_branch_set_flop - reg branch_set_q; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - branch_set_q <= 1'b0; - else - branch_set_q <= branch_set_d; - assign branch_set = (BranchTargetALU && !data_ind_timing_i ? branch_set_d : branch_set_q); - assign branch_set_spec = (BranchTargetALU && !data_ind_timing_i ? branch_spec : branch_set_q); - end - endgenerate - generate - if (DataIndTiming) begin : g_sec_branch_taken - reg branch_taken_q; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - branch_taken_q <= 1'b0; - else - branch_taken_q <= branch_decision_i; - assign branch_taken = ~data_ind_timing_i | branch_taken_q; - end - else begin : g_nosec_branch_taken - assign branch_taken = 1'b1; - end - endgenerate - reg id_fsm_q; - reg id_fsm_d; - localparam [0:0] FIRST_CYCLE = 0; - always @(posedge clk_i or negedge rst_ni) begin : id_pipeline_reg - if (!rst_ni) - id_fsm_q <= FIRST_CYCLE; - else - id_fsm_q <= id_fsm_d; - end - localparam [0:0] MULTI_CYCLE = 1; - always @(*) begin - id_fsm_d = id_fsm_q; - rf_we_raw = rf_we_dec; - stall_multdiv = 1'b0; - stall_jump = 1'b0; - stall_branch = 1'b0; - stall_alu = 1'b0; - branch_set_d = 1'b0; - branch_spec = 1'b0; - branch_not_set = 1'b0; - jump_set = 1'b0; - perf_branch_o = 1'b0; - if (instr_executing) - case (id_fsm_q) - FIRST_CYCLE: - case (1'b1) - lsu_req_dec: - if (!WritebackStage) - id_fsm_d = MULTI_CYCLE; - else if (~lsu_req_done_i) - id_fsm_d = MULTI_CYCLE; - multdiv_en_dec: - if (~ex_valid_i) begin - id_fsm_d = MULTI_CYCLE; - rf_we_raw = 1'b0; - stall_multdiv = 1'b1; - end - branch_in_dec: begin - id_fsm_d = (data_ind_timing_i || (!BranchTargetALU && branch_decision_i) ? MULTI_CYCLE : FIRST_CYCLE); - stall_branch = (~BranchTargetALU & branch_decision_i) | data_ind_timing_i; - branch_set_d = branch_decision_i | data_ind_timing_i; - if (BranchPredictor) - branch_not_set = ~branch_decision_i; - branch_spec = (SpecBranch ? 1'b1 : branch_decision_i); - perf_branch_o = 1'b1; - end - jump_in_dec: begin - id_fsm_d = (BranchTargetALU ? FIRST_CYCLE : MULTI_CYCLE); - stall_jump = ~BranchTargetALU; - jump_set = jump_set_dec; - end - alu_multicycle_dec: begin - stall_alu = 1'b1; - id_fsm_d = MULTI_CYCLE; - rf_we_raw = 1'b0; - end - default: id_fsm_d = FIRST_CYCLE; - endcase - MULTI_CYCLE: begin - if (multdiv_en_dec) - rf_we_raw = rf_we_dec & ex_valid_i; - if (multicycle_done & ready_wb_i) - id_fsm_d = FIRST_CYCLE; - else begin - stall_multdiv = multdiv_en_dec; - stall_branch = branch_in_dec; - stall_jump = jump_in_dec; - end - end - default: id_fsm_d = FIRST_CYCLE; - endcase - end - assign multdiv_ready_id_o = ready_wb_i; - assign stall_id = ((((stall_ld_hz | stall_mem) | stall_multdiv) | stall_jump) | stall_branch) | stall_alu; - assign instr_done = (~stall_id & ~flush_id) & instr_executing; - assign instr_first_cycle = instr_valid_i & (id_fsm_q == FIRST_CYCLE); - assign instr_first_cycle_id_o = instr_first_cycle; - localparam [1:0] ibex_pkg_WB_INSTR_LOAD = 0; - localparam [1:0] ibex_pkg_WB_INSTR_OTHER = 2; - localparam [1:0] ibex_pkg_WB_INSTR_STORE = 1; - generate - if (WritebackStage) begin : gen_stall_mem - wire rf_rd_a_wb_match; - wire rf_rd_b_wb_match; - wire rf_rd_a_hz; - wire rf_rd_b_hz; - wire outstanding_memory_access; - wire instr_kill; - assign multicycle_done = (lsu_req_dec ? ~stall_mem : ex_valid_i); - assign outstanding_memory_access = (outstanding_load_wb_i | outstanding_store_wb_i) & ~lsu_resp_valid_i; - assign data_req_allowed = ~outstanding_memory_access; - assign instr_kill = (instr_fetch_err_i | wb_exception) | ~controller_run; - assign instr_executing = ((instr_valid_i & ~instr_kill) & ~stall_ld_hz) & ~outstanding_memory_access; - assign stall_mem = instr_valid_i & (outstanding_memory_access | (lsu_req_dec & ~lsu_req_done_i)); - assign rf_rd_a_wb_match = (rf_waddr_wb_i == rf_raddr_a_o) & |rf_raddr_a_o; - assign rf_rd_b_wb_match = (rf_waddr_wb_i == rf_raddr_b_o) & |rf_raddr_b_o; - assign rf_rd_a_wb_match_o = rf_rd_a_wb_match; - assign rf_rd_b_wb_match_o = rf_rd_b_wb_match; - assign rf_rd_a_hz = rf_rd_a_wb_match & rf_ren_a; - assign rf_rd_b_hz = rf_rd_b_wb_match & rf_ren_b; - assign rf_rdata_a_fwd = (rf_rd_a_wb_match & rf_write_wb_i ? rf_wdata_fwd_wb_i : rf_rdata_a_i); - assign rf_rdata_b_fwd = (rf_rd_b_wb_match & rf_write_wb_i ? rf_wdata_fwd_wb_i : rf_rdata_b_i); - assign stall_ld_hz = outstanding_load_wb_i & (rf_rd_a_hz | rf_rd_b_hz); - assign instr_type_wb_o = (~lsu_req_dec ? ibex_pkg_WB_INSTR_OTHER : (lsu_we ? ibex_pkg_WB_INSTR_STORE : ibex_pkg_WB_INSTR_LOAD)); - assign instr_id_done_o = en_wb_o & ready_wb_i; - assign stall_wb = en_wb_o & ~ready_wb_i; - assign perf_dside_wait_o = (instr_valid_i & ~instr_kill) & (outstanding_memory_access | stall_ld_hz); - end - else begin : gen_no_stall_mem - assign multicycle_done = (lsu_req_dec ? lsu_resp_valid_i : ex_valid_i); - assign data_req_allowed = instr_first_cycle; - assign stall_mem = instr_valid_i & (lsu_req_dec & (~lsu_resp_valid_i | instr_first_cycle)); - assign stall_ld_hz = 1'b0; - assign instr_executing = (instr_valid_i & ~instr_fetch_err_i) & controller_run; - assign rf_rdata_a_fwd = rf_rdata_a_i; - assign rf_rdata_b_fwd = rf_rdata_b_i; - assign rf_rd_a_wb_match_o = 1'b0; - assign rf_rd_b_wb_match_o = 1'b0; - wire unused_data_req_done_ex; - wire [4:0] unused_rf_waddr_wb; - wire unused_rf_write_wb; - wire unused_outstanding_load_wb; - wire unused_outstanding_store_wb; - wire unused_wb_exception; - wire [31:0] unused_rf_wdata_fwd_wb; - assign unused_data_req_done_ex = lsu_req_done_i; - assign unused_rf_waddr_wb = rf_waddr_wb_i; - assign unused_rf_write_wb = rf_write_wb_i; - assign unused_outstanding_load_wb = outstanding_load_wb_i; - assign unused_outstanding_store_wb = outstanding_store_wb_i; - assign unused_wb_exception = wb_exception; - assign unused_rf_wdata_fwd_wb = rf_wdata_fwd_wb_i; - assign instr_type_wb_o = ibex_pkg_WB_INSTR_OTHER; - assign stall_wb = 1'b0; - assign perf_dside_wait_o = (instr_executing & lsu_req_dec) & ~lsu_resp_valid_i; - assign instr_id_done_o = instr_done; - end - endgenerate - assign instr_perf_count_id_o = (((~ebrk_insn & ~ecall_insn_dec) & ~illegal_insn_dec) & ~illegal_csr_insn_i) & ~instr_fetch_err_i; - assign en_wb_o = instr_done; - assign perf_mul_wait_o = stall_multdiv & mult_en_dec; - assign perf_div_wait_o = stall_multdiv & div_en_dec; -endmodule diff --git a/flow/designs/src/ibex/ibex_if_stage.v b/flow/designs/src/ibex/ibex_if_stage.v deleted file mode 100644 index 712cb73b5e..0000000000 --- a/flow/designs/src/ibex/ibex_if_stage.v +++ /dev/null @@ -1,396 +0,0 @@ -module ibex_if_stage ( - clk_i, - rst_ni, - boot_addr_i, - req_i, - instr_req_o, - instr_addr_o, - instr_gnt_i, - instr_rvalid_i, - instr_rdata_i, - instr_err_i, - instr_pmp_err_i, - instr_valid_id_o, - instr_new_id_o, - instr_rdata_id_o, - instr_rdata_alu_id_o, - instr_rdata_c_id_o, - instr_is_compressed_id_o, - instr_bp_taken_o, - instr_fetch_err_o, - instr_fetch_err_plus2_o, - illegal_c_insn_id_o, - dummy_instr_id_o, - pc_if_o, - pc_id_o, - instr_valid_clear_i, - pc_set_i, - pc_set_spec_i, - pc_mux_i, - nt_branch_mispredict_i, - exc_pc_mux_i, - exc_cause, - dummy_instr_en_i, - dummy_instr_mask_i, - dummy_instr_seed_en_i, - dummy_instr_seed_i, - icache_enable_i, - icache_inval_i, - branch_target_ex_i, - csr_mepc_i, - csr_depc_i, - csr_mtvec_i, - csr_mtvec_init_o, - id_in_ready_i, - pc_mismatch_alert_o, - if_busy_o -); - parameter [31:0] DmHaltAddr = 32'h1a110800; - parameter [31:0] DmExceptionAddr = 32'h1a110808; - parameter [0:0] DummyInstructions = 1'b0; - parameter [0:0] ICache = 1'b0; - parameter [0:0] ICacheECC = 1'b0; - parameter [0:0] PCIncrCheck = 1'b0; - parameter [0:0] BranchPredictor = 1'b0; - input wire clk_i; - input wire rst_ni; - input wire [31:0] boot_addr_i; - input wire req_i; - output wire instr_req_o; - output wire [31:0] instr_addr_o; - input wire instr_gnt_i; - input wire instr_rvalid_i; - input wire [31:0] instr_rdata_i; - input wire instr_err_i; - input wire instr_pmp_err_i; - output wire instr_valid_id_o; - output wire instr_new_id_o; - output reg [31:0] instr_rdata_id_o; - output reg [31:0] instr_rdata_alu_id_o; - output reg [15:0] instr_rdata_c_id_o; - output reg instr_is_compressed_id_o; - output wire instr_bp_taken_o; - output reg instr_fetch_err_o; - output reg instr_fetch_err_plus2_o; - output reg illegal_c_insn_id_o; - output reg dummy_instr_id_o; - output wire [31:0] pc_if_o; - output reg [31:0] pc_id_o; - input wire instr_valid_clear_i; - input wire pc_set_i; - input wire pc_set_spec_i; - input wire [2:0] pc_mux_i; - input wire nt_branch_mispredict_i; - input wire [1:0] exc_pc_mux_i; - input wire [5:0] exc_cause; - input wire dummy_instr_en_i; - input wire [2:0] dummy_instr_mask_i; - input wire dummy_instr_seed_en_i; - input wire [31:0] dummy_instr_seed_i; - input wire icache_enable_i; - input wire icache_inval_i; - input wire [31:0] branch_target_ex_i; - input wire [31:0] csr_mepc_i; - input wire [31:0] csr_depc_i; - input wire [31:0] csr_mtvec_i; - output wire csr_mtvec_init_o; - input wire id_in_ready_i; - output wire pc_mismatch_alert_o; - output wire if_busy_o; - wire instr_valid_id_d; - reg instr_valid_id_q; - wire instr_new_id_d; - reg instr_new_id_q; - wire prefetch_busy; - wire branch_req; - wire branch_spec; - wire predicted_branch; - reg [31:0] fetch_addr_n; - wire unused_fetch_addr_n0; - wire fetch_valid; - wire fetch_ready; - wire [31:0] fetch_rdata; - wire [31:0] fetch_addr; - wire fetch_err; - wire fetch_err_plus2; - wire if_instr_valid; - wire [31:0] if_instr_rdata; - wire [31:0] if_instr_addr; - wire if_instr_err; - reg [31:0] exc_pc; - wire [5:0] irq_id; - wire unused_irq_bit; - wire if_id_pipe_reg_we; - wire stall_dummy_instr; - wire [31:0] instr_out; - wire instr_is_compressed_out; - wire illegal_c_instr_out; - wire instr_err_out; - wire predict_branch_taken; - wire [31:0] predict_branch_pc; - wire [2:0] pc_mux_internal; - wire [7:0] unused_boot_addr; - wire [7:0] unused_csr_mtvec; - assign unused_boot_addr = boot_addr_i[7:0]; - assign unused_csr_mtvec = csr_mtvec_i[7:0]; - assign irq_id = {exc_cause}; - assign unused_irq_bit = irq_id[5]; - localparam [1:0] ibex_pkg_EXC_PC_DBD = 2; - localparam [1:0] ibex_pkg_EXC_PC_DBG_EXC = 3; - localparam [1:0] ibex_pkg_EXC_PC_EXC = 0; - localparam [1:0] ibex_pkg_EXC_PC_IRQ = 1; - always @(*) begin : exc_pc_mux - case (exc_pc_mux_i) - ibex_pkg_EXC_PC_EXC: exc_pc = {csr_mtvec_i[31:8], 8'h00}; - ibex_pkg_EXC_PC_IRQ: exc_pc = {csr_mtvec_i[31:8], 1'b0, irq_id[4:0], 2'b00}; - ibex_pkg_EXC_PC_DBD: exc_pc = DmHaltAddr; - ibex_pkg_EXC_PC_DBG_EXC: exc_pc = DmExceptionAddr; - default: exc_pc = {csr_mtvec_i[31:8], 8'h00}; - endcase - end - localparam [2:0] ibex_pkg_PC_BP = 5; - assign pc_mux_internal = ((BranchPredictor && predict_branch_taken) && !pc_set_i ? ibex_pkg_PC_BP : pc_mux_i); - localparam [2:0] ibex_pkg_PC_BOOT = 0; - localparam [2:0] ibex_pkg_PC_DRET = 4; - localparam [2:0] ibex_pkg_PC_ERET = 3; - localparam [2:0] ibex_pkg_PC_EXC = 2; - localparam [2:0] ibex_pkg_PC_JUMP = 1; - always @(*) begin : fetch_addr_mux - case (pc_mux_internal) - ibex_pkg_PC_BOOT: fetch_addr_n = {boot_addr_i[31:8], 8'h80}; - ibex_pkg_PC_JUMP: fetch_addr_n = branch_target_ex_i; - ibex_pkg_PC_EXC: fetch_addr_n = exc_pc; - ibex_pkg_PC_ERET: fetch_addr_n = csr_mepc_i; - ibex_pkg_PC_DRET: fetch_addr_n = csr_depc_i; - ibex_pkg_PC_BP: fetch_addr_n = (BranchPredictor ? predict_branch_pc : {boot_addr_i[31:8], 8'h80}); - default: fetch_addr_n = {boot_addr_i[31:8], 8'h80}; - endcase - end - assign csr_mtvec_init_o = (pc_mux_i == ibex_pkg_PC_BOOT) & pc_set_i; - generate - if (ICache) begin : gen_icache - ibex_icache #(.ICacheECC(ICacheECC)) icache_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .req_i(req_i), - .branch_i(branch_req), - .branch_spec_i(branch_spec), - .addr_i({fetch_addr_n[31:1], 1'b0}), - .ready_i(fetch_ready), - .valid_o(fetch_valid), - .rdata_o(fetch_rdata), - .addr_o(fetch_addr), - .err_o(fetch_err), - .err_plus2_o(fetch_err_plus2), - .instr_req_o(instr_req_o), - .instr_addr_o(instr_addr_o), - .instr_gnt_i(instr_gnt_i), - .instr_rvalid_i(instr_rvalid_i), - .instr_rdata_i(instr_rdata_i), - .instr_err_i(instr_err_i), - .instr_pmp_err_i(instr_pmp_err_i), - .icache_enable_i(icache_enable_i), - .icache_inval_i(icache_inval_i), - .busy_o(prefetch_busy) - ); - wire unused_nt_branch_mispredict; - wire unused_predicted_branch; - assign unused_nt_branch_mispredict = nt_branch_mispredict_i; - assign unused_predicted_branch = predicted_branch; - end - else begin : gen_prefetch_buffer - ibex_prefetch_buffer #(.BranchPredictor(BranchPredictor)) prefetch_buffer_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .req_i(req_i), - .branch_i(branch_req), - .branch_spec_i(branch_spec), - .predicted_branch_i(predicted_branch), - .branch_mispredict_i(nt_branch_mispredict_i), - .addr_i({fetch_addr_n[31:1], 1'b0}), - .ready_i(fetch_ready), - .valid_o(fetch_valid), - .rdata_o(fetch_rdata), - .addr_o(fetch_addr), - .err_o(fetch_err), - .err_plus2_o(fetch_err_plus2), - .instr_req_o(instr_req_o), - .instr_addr_o(instr_addr_o), - .instr_gnt_i(instr_gnt_i), - .instr_rvalid_i(instr_rvalid_i), - .instr_rdata_i(instr_rdata_i), - .instr_err_i(instr_err_i), - .instr_pmp_err_i(instr_pmp_err_i), - .busy_o(prefetch_busy) - ); - wire unused_icen; - wire unused_icinv; - assign unused_icen = icache_enable_i; - assign unused_icinv = icache_inval_i; - end - endgenerate - assign unused_fetch_addr_n0 = fetch_addr_n[0]; - assign branch_req = pc_set_i | predict_branch_taken; - assign branch_spec = pc_set_spec_i | predict_branch_taken; - assign pc_if_o = if_instr_addr; - assign if_busy_o = prefetch_busy; - wire [31:0] instr_decompressed; - wire illegal_c_insn; - wire instr_is_compressed; - ibex_compressed_decoder compressed_decoder_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .valid_i(fetch_valid & ~fetch_err), - .instr_i(if_instr_rdata), - .instr_o(instr_decompressed), - .is_compressed_o(instr_is_compressed), - .illegal_instr_o(illegal_c_insn) - ); - generate - if (DummyInstructions) begin : gen_dummy_instr - wire insert_dummy_instr; - wire [31:0] dummy_instr_data; - ibex_dummy_instr dummy_instr_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .dummy_instr_en_i(dummy_instr_en_i), - .dummy_instr_mask_i(dummy_instr_mask_i), - .dummy_instr_seed_en_i(dummy_instr_seed_en_i), - .dummy_instr_seed_i(dummy_instr_seed_i), - .fetch_valid_i(fetch_valid), - .id_in_ready_i(id_in_ready_i), - .insert_dummy_instr_o(insert_dummy_instr), - .dummy_instr_data_o(dummy_instr_data) - ); - assign instr_out = (insert_dummy_instr ? dummy_instr_data : instr_decompressed); - assign instr_is_compressed_out = (insert_dummy_instr ? 1'b0 : instr_is_compressed); - assign illegal_c_instr_out = (insert_dummy_instr ? 1'b0 : illegal_c_insn); - assign instr_err_out = (insert_dummy_instr ? 1'b0 : if_instr_err); - assign stall_dummy_instr = insert_dummy_instr; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - dummy_instr_id_o <= 1'b0; - else if (if_id_pipe_reg_we) - dummy_instr_id_o <= insert_dummy_instr; - end - else begin : gen_no_dummy_instr - wire unused_dummy_en; - wire [2:0] unused_dummy_mask; - wire unused_dummy_seed_en; - wire [31:0] unused_dummy_seed; - assign unused_dummy_en = dummy_instr_en_i; - assign unused_dummy_mask = dummy_instr_mask_i; - assign unused_dummy_seed_en = dummy_instr_seed_en_i; - assign unused_dummy_seed = dummy_instr_seed_i; - assign instr_out = instr_decompressed; - assign instr_is_compressed_out = instr_is_compressed; - assign illegal_c_instr_out = illegal_c_insn; - assign instr_err_out = if_instr_err; - assign stall_dummy_instr = 1'b0; - wire [1:1] sv2v_tmp_253B9; - assign sv2v_tmp_253B9 = 1'b0; - always @(*) dummy_instr_id_o = sv2v_tmp_253B9; - end - endgenerate - assign instr_valid_id_d = ((if_instr_valid & id_in_ready_i) & ~pc_set_i) | (instr_valid_id_q & ~instr_valid_clear_i); - assign instr_new_id_d = if_instr_valid & id_in_ready_i; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) begin - instr_valid_id_q <= 1'b0; - instr_new_id_q <= 1'b0; - end - else begin - instr_valid_id_q <= instr_valid_id_d; - instr_new_id_q <= instr_new_id_d; - end - assign instr_valid_id_o = instr_valid_id_q; - assign instr_new_id_o = instr_new_id_q; - assign if_id_pipe_reg_we = instr_new_id_d; - always @(posedge clk_i) - if (if_id_pipe_reg_we) begin - instr_rdata_id_o <= instr_out; - instr_rdata_alu_id_o <= instr_out; - instr_fetch_err_o <= instr_err_out; - instr_fetch_err_plus2_o <= fetch_err_plus2; - instr_rdata_c_id_o <= if_instr_rdata[15:0]; - instr_is_compressed_id_o <= instr_is_compressed_out; - illegal_c_insn_id_o <= illegal_c_instr_out; - pc_id_o <= pc_if_o; - end - generate - if (PCIncrCheck) begin : g_secure_pc - wire [31:0] prev_instr_addr_incr; - reg prev_instr_seq_q; - wire prev_instr_seq_d; - assign prev_instr_seq_d = ((prev_instr_seq_q | instr_new_id_d) & ~branch_req) & ~stall_dummy_instr; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - prev_instr_seq_q <= 1'b0; - else - prev_instr_seq_q <= prev_instr_seq_d; - assign prev_instr_addr_incr = pc_id_o + (instr_is_compressed_id_o && !instr_fetch_err_o ? 32'd2 : 32'd4); - assign pc_mismatch_alert_o = prev_instr_seq_q & (pc_if_o != prev_instr_addr_incr); - end - else begin : g_no_secure_pc - assign pc_mismatch_alert_o = 1'b0; - end - endgenerate - generate - if (BranchPredictor) begin : g_branch_predictor - reg [31:0] instr_skid_data_q; - reg [31:0] instr_skid_addr_q; - reg instr_skid_bp_taken_q; - reg instr_skid_valid_q; - wire instr_skid_valid_d; - wire instr_skid_en; - reg instr_bp_taken_q; - wire instr_bp_taken_d; - wire predict_branch_taken_raw; - always @(posedge clk_i) - if (if_id_pipe_reg_we) - instr_bp_taken_q <= instr_bp_taken_d; - assign instr_skid_en = (predicted_branch & ~id_in_ready_i) & ~instr_skid_valid_q; - assign instr_skid_valid_d = ((instr_skid_valid_q & ~id_in_ready_i) & ~stall_dummy_instr) | instr_skid_en; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - instr_skid_valid_q <= 1'b0; - else - instr_skid_valid_q <= instr_skid_valid_d; - always @(posedge clk_i) - if (instr_skid_en) begin - instr_skid_bp_taken_q <= predict_branch_taken; - instr_skid_data_q <= fetch_rdata; - instr_skid_addr_q <= fetch_addr; - end - ibex_branch_predict branch_predict_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .fetch_rdata_i(fetch_rdata), - .fetch_pc_i(fetch_addr), - .fetch_valid_i(fetch_valid), - .predict_branch_taken_o(predict_branch_taken_raw), - .predict_branch_pc_o(predict_branch_pc) - ); - assign predict_branch_taken = (predict_branch_taken_raw & ~instr_skid_valid_q) & ~fetch_err; - assign predicted_branch = predict_branch_taken & ~pc_set_i; - assign if_instr_valid = fetch_valid | instr_skid_valid_q; - assign if_instr_rdata = (instr_skid_valid_q ? instr_skid_data_q : fetch_rdata); - assign if_instr_addr = (instr_skid_valid_q ? instr_skid_addr_q : fetch_addr); - assign if_instr_err = ~instr_skid_valid_q & fetch_err; - assign instr_bp_taken_d = (instr_skid_valid_q ? instr_skid_bp_taken_q : predict_branch_taken); - assign fetch_ready = (id_in_ready_i & ~stall_dummy_instr) & ~instr_skid_valid_q; - assign instr_bp_taken_o = instr_bp_taken_q; - end - else begin : g_no_branch_predictor - assign instr_bp_taken_o = 1'b0; - assign predict_branch_taken = 1'b0; - assign predicted_branch = 1'b0; - assign predict_branch_pc = 32'b00000000000000000000000000000000; - assign if_instr_valid = fetch_valid; - assign if_instr_rdata = fetch_rdata; - assign if_instr_addr = fetch_addr; - assign if_instr_err = fetch_err; - assign fetch_ready = id_in_ready_i & ~stall_dummy_instr; - end - endgenerate -endmodule diff --git a/flow/designs/src/ibex/ibex_load_store_unit.v b/flow/designs/src/ibex/ibex_load_store_unit.v deleted file mode 100644 index c302b6130e..0000000000 --- a/flow/designs/src/ibex/ibex_load_store_unit.v +++ /dev/null @@ -1,337 +0,0 @@ -module ibex_load_store_unit ( - clk_i, - rst_ni, - data_req_o, - data_gnt_i, - data_rvalid_i, - data_err_i, - data_pmp_err_i, - data_addr_o, - data_we_o, - data_be_o, - data_wdata_o, - data_rdata_i, - lsu_we_i, - lsu_type_i, - lsu_wdata_i, - lsu_sign_ext_i, - lsu_rdata_o, - lsu_rdata_valid_o, - lsu_req_i, - adder_result_ex_i, - addr_incr_req_o, - addr_last_o, - lsu_req_done_o, - lsu_resp_valid_o, - load_err_o, - store_err_o, - busy_o, - perf_load_o, - perf_store_o -); - input wire clk_i; - input wire rst_ni; - output reg data_req_o; - input wire data_gnt_i; - input wire data_rvalid_i; - input wire data_err_i; - input wire data_pmp_err_i; - output wire [31:0] data_addr_o; - output wire data_we_o; - output wire [3:0] data_be_o; - output wire [31:0] data_wdata_o; - input wire [31:0] data_rdata_i; - input wire lsu_we_i; - input wire [1:0] lsu_type_i; - input wire [31:0] lsu_wdata_i; - input wire lsu_sign_ext_i; - output wire [31:0] lsu_rdata_o; - output wire lsu_rdata_valid_o; - input wire lsu_req_i; - input wire [31:0] adder_result_ex_i; - output reg addr_incr_req_o; - output wire [31:0] addr_last_o; - output wire lsu_req_done_o; - output wire lsu_resp_valid_o; - output wire load_err_o; - output wire store_err_o; - output wire busy_o; - output reg perf_load_o; - output reg perf_store_o; - wire [31:0] data_addr; - wire [31:0] data_addr_w_aligned; - reg [31:0] addr_last_q; - reg addr_update; - reg ctrl_update; - reg rdata_update; - reg [31:8] rdata_q; - reg [1:0] rdata_offset_q; - reg [1:0] data_type_q; - reg data_sign_ext_q; - reg data_we_q; - wire [1:0] data_offset; - reg [3:0] data_be; - reg [31:0] data_wdata; - reg [31:0] data_rdata_ext; - reg [31:0] rdata_w_ext; - reg [31:0] rdata_h_ext; - reg [31:0] rdata_b_ext; - wire split_misaligned_access; - reg handle_misaligned_q; - reg handle_misaligned_d; - reg pmp_err_q; - reg pmp_err_d; - reg lsu_err_q; - reg lsu_err_d; - wire data_or_pmp_err; - reg [2:0] ls_fsm_cs; - reg [2:0] ls_fsm_ns; - assign data_addr = adder_result_ex_i; - assign data_offset = data_addr[1:0]; - always @(*) - case (lsu_type_i) - 2'b00: - if (!handle_misaligned_q) - case (data_offset) - 2'b00: data_be = 4'b1111; - 2'b01: data_be = 4'b1110; - 2'b10: data_be = 4'b1100; - 2'b11: data_be = 4'b1000; - default: data_be = 4'b1111; - endcase - else - case (data_offset) - 2'b00: data_be = 4'b0000; - 2'b01: data_be = 4'b0001; - 2'b10: data_be = 4'b0011; - 2'b11: data_be = 4'b0111; - default: data_be = 4'b1111; - endcase - 2'b01: - if (!handle_misaligned_q) - case (data_offset) - 2'b00: data_be = 4'b0011; - 2'b01: data_be = 4'b0110; - 2'b10: data_be = 4'b1100; - 2'b11: data_be = 4'b1000; - default: data_be = 4'b1111; - endcase - else - data_be = 4'b0001; - 2'b10, 2'b11: - case (data_offset) - 2'b00: data_be = 4'b0001; - 2'b01: data_be = 4'b0010; - 2'b10: data_be = 4'b0100; - 2'b11: data_be = 4'b1000; - default: data_be = 4'b1111; - endcase - default: data_be = 4'b1111; - endcase - always @(*) - case (data_offset) - 2'b00: data_wdata = lsu_wdata_i[31:0]; - 2'b01: data_wdata = {lsu_wdata_i[23:0], lsu_wdata_i[31:24]}; - 2'b10: data_wdata = {lsu_wdata_i[15:0], lsu_wdata_i[31:16]}; - 2'b11: data_wdata = {lsu_wdata_i[7:0], lsu_wdata_i[31:8]}; - default: data_wdata = lsu_wdata_i[31:0]; - endcase - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - rdata_q <= {24 {1'sb0}}; - else if (rdata_update) - rdata_q <= data_rdata_i[31:8]; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) begin - rdata_offset_q <= 2'h0; - data_type_q <= 2'h0; - data_sign_ext_q <= 1'b0; - data_we_q <= 1'b0; - end - else if (ctrl_update) begin - rdata_offset_q <= data_offset; - data_type_q <= lsu_type_i; - data_sign_ext_q <= lsu_sign_ext_i; - data_we_q <= lsu_we_i; - end - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - addr_last_q <= {32 {1'sb0}}; - else if (addr_update) - addr_last_q <= data_addr; - always @(*) - case (rdata_offset_q) - 2'b00: rdata_w_ext = data_rdata_i[31:0]; - 2'b01: rdata_w_ext = {data_rdata_i[7:0], rdata_q[31:8]}; - 2'b10: rdata_w_ext = {data_rdata_i[15:0], rdata_q[31:16]}; - 2'b11: rdata_w_ext = {data_rdata_i[23:0], rdata_q[31:24]}; - default: rdata_w_ext = data_rdata_i[31:0]; - endcase - always @(*) - case (rdata_offset_q) - 2'b00: - if (!data_sign_ext_q) - rdata_h_ext = {16'h0000, data_rdata_i[15:0]}; - else - rdata_h_ext = {{16 {data_rdata_i[15]}}, data_rdata_i[15:0]}; - 2'b01: - if (!data_sign_ext_q) - rdata_h_ext = {16'h0000, data_rdata_i[23:8]}; - else - rdata_h_ext = {{16 {data_rdata_i[23]}}, data_rdata_i[23:8]}; - 2'b10: - if (!data_sign_ext_q) - rdata_h_ext = {16'h0000, data_rdata_i[31:16]}; - else - rdata_h_ext = {{16 {data_rdata_i[31]}}, data_rdata_i[31:16]}; - 2'b11: - if (!data_sign_ext_q) - rdata_h_ext = {16'h0000, data_rdata_i[7:0], rdata_q[31:24]}; - else - rdata_h_ext = {{16 {data_rdata_i[7]}}, data_rdata_i[7:0], rdata_q[31:24]}; - default: rdata_h_ext = {16'h0000, data_rdata_i[15:0]}; - endcase - always @(*) - case (rdata_offset_q) - 2'b00: - if (!data_sign_ext_q) - rdata_b_ext = {24'h000000, data_rdata_i[7:0]}; - else - rdata_b_ext = {{24 {data_rdata_i[7]}}, data_rdata_i[7:0]}; - 2'b01: - if (!data_sign_ext_q) - rdata_b_ext = {24'h000000, data_rdata_i[15:8]}; - else - rdata_b_ext = {{24 {data_rdata_i[15]}}, data_rdata_i[15:8]}; - 2'b10: - if (!data_sign_ext_q) - rdata_b_ext = {24'h000000, data_rdata_i[23:16]}; - else - rdata_b_ext = {{24 {data_rdata_i[23]}}, data_rdata_i[23:16]}; - 2'b11: - if (!data_sign_ext_q) - rdata_b_ext = {24'h000000, data_rdata_i[31:24]}; - else - rdata_b_ext = {{24 {data_rdata_i[31]}}, data_rdata_i[31:24]}; - default: rdata_b_ext = {24'h000000, data_rdata_i[7:0]}; - endcase - always @(*) - case (data_type_q) - 2'b00: data_rdata_ext = rdata_w_ext; - 2'b01: data_rdata_ext = rdata_h_ext; - 2'b10, 2'b11: data_rdata_ext = rdata_b_ext; - default: data_rdata_ext = rdata_w_ext; - endcase - assign split_misaligned_access = ((lsu_type_i == 2'b00) && (data_offset != 2'b00)) || ((lsu_type_i == 2'b01) && (data_offset == 2'b11)); - localparam [2:0] IDLE = 0; - localparam [2:0] WAIT_GNT = 3; - localparam [2:0] WAIT_GNT_MIS = 1; - localparam [2:0] WAIT_RVALID_MIS = 2; - localparam [2:0] WAIT_RVALID_MIS_GNTS_DONE = 4; - always @(*) begin - ls_fsm_ns = ls_fsm_cs; - data_req_o = 1'b0; - addr_incr_req_o = 1'b0; - handle_misaligned_d = handle_misaligned_q; - pmp_err_d = pmp_err_q; - lsu_err_d = lsu_err_q; - addr_update = 1'b0; - ctrl_update = 1'b0; - rdata_update = 1'b0; - perf_load_o = 1'b0; - perf_store_o = 1'b0; - case (ls_fsm_cs) - IDLE: begin - pmp_err_d = 1'b0; - if (lsu_req_i) begin - data_req_o = 1'b1; - pmp_err_d = data_pmp_err_i; - lsu_err_d = 1'b0; - perf_load_o = ~lsu_we_i; - perf_store_o = lsu_we_i; - if (data_gnt_i) begin - ctrl_update = 1'b1; - addr_update = 1'b1; - handle_misaligned_d = split_misaligned_access; - ls_fsm_ns = (split_misaligned_access ? WAIT_RVALID_MIS : IDLE); - end - else - ls_fsm_ns = (split_misaligned_access ? WAIT_GNT_MIS : WAIT_GNT); - end - end - WAIT_GNT_MIS: begin - data_req_o = 1'b1; - if (data_gnt_i || pmp_err_q) begin - addr_update = 1'b1; - ctrl_update = 1'b1; - handle_misaligned_d = 1'b1; - ls_fsm_ns = WAIT_RVALID_MIS; - end - end - WAIT_RVALID_MIS: begin - data_req_o = 1'b1; - addr_incr_req_o = 1'b1; - if (data_rvalid_i || pmp_err_q) begin - pmp_err_d = data_pmp_err_i; - lsu_err_d = data_err_i | pmp_err_q; - rdata_update = ~data_we_q; - ls_fsm_ns = (data_gnt_i ? IDLE : WAIT_GNT); - addr_update = data_gnt_i & ~(data_err_i | pmp_err_q); - handle_misaligned_d = ~data_gnt_i; - end - else if (data_gnt_i) begin - ls_fsm_ns = WAIT_RVALID_MIS_GNTS_DONE; - handle_misaligned_d = 1'b0; - end - end - WAIT_GNT: begin - addr_incr_req_o = handle_misaligned_q; - data_req_o = 1'b1; - if (data_gnt_i || pmp_err_q) begin - ctrl_update = 1'b1; - addr_update = ~lsu_err_q; - ls_fsm_ns = IDLE; - handle_misaligned_d = 1'b0; - end - end - WAIT_RVALID_MIS_GNTS_DONE: begin - addr_incr_req_o = 1'b1; - if (data_rvalid_i) begin - pmp_err_d = data_pmp_err_i; - lsu_err_d = data_err_i; - addr_update = ~data_err_i; - rdata_update = ~data_we_q; - ls_fsm_ns = IDLE; - end - end - default: ls_fsm_ns = IDLE; - endcase - end - assign lsu_req_done_o = (lsu_req_i | (ls_fsm_cs != IDLE)) & (ls_fsm_ns == IDLE); - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) begin - ls_fsm_cs <= IDLE; - handle_misaligned_q <= 1'b0; - pmp_err_q <= 1'b0; - lsu_err_q <= 1'b0; - end - else begin - ls_fsm_cs <= ls_fsm_ns; - handle_misaligned_q <= handle_misaligned_d; - pmp_err_q <= pmp_err_d; - lsu_err_q <= lsu_err_d; - end - assign data_or_pmp_err = (lsu_err_q | data_err_i) | pmp_err_q; - assign lsu_resp_valid_o = (data_rvalid_i | pmp_err_q) & (ls_fsm_cs == IDLE); - assign lsu_rdata_valid_o = (((ls_fsm_cs == IDLE) & data_rvalid_i) & ~data_or_pmp_err) & ~data_we_q; - assign lsu_rdata_o = data_rdata_ext; - assign data_addr_w_aligned = {data_addr[31:2], 2'b00}; - assign data_addr_o = data_addr_w_aligned; - assign data_wdata_o = data_wdata; - assign data_we_o = lsu_we_i; - assign data_be_o = data_be; - assign addr_last_o = addr_last_q; - assign load_err_o = (data_or_pmp_err & ~data_we_q) & lsu_resp_valid_o; - assign store_err_o = (data_or_pmp_err & data_we_q) & lsu_resp_valid_o; - assign busy_o = ls_fsm_cs != IDLE; -endmodule diff --git a/flow/designs/src/ibex/ibex_multdiv_fast.v b/flow/designs/src/ibex/ibex_multdiv_fast.v deleted file mode 100644 index 695e01b622..0000000000 --- a/flow/designs/src/ibex/ibex_multdiv_fast.v +++ /dev/null @@ -1,400 +0,0 @@ -module ibex_multdiv_fast ( - clk_i, - rst_ni, - mult_en_i, - div_en_i, - mult_sel_i, - div_sel_i, - operator_i, - signed_mode_i, - op_a_i, - op_b_i, - alu_adder_ext_i, - alu_adder_i, - equal_to_zero_i, - data_ind_timing_i, - alu_operand_a_o, - alu_operand_b_o, - imd_val_q_i, - imd_val_d_o, - imd_val_we_o, - multdiv_ready_id_i, - multdiv_result_o, - valid_o -); - localparam integer ibex_pkg_RV32MFast = 2; - parameter integer RV32M = ibex_pkg_RV32MFast; - input wire clk_i; - input wire rst_ni; - input wire mult_en_i; - input wire div_en_i; - input wire mult_sel_i; - input wire div_sel_i; - input wire [1:0] operator_i; - input wire [1:0] signed_mode_i; - input wire [31:0] op_a_i; - input wire [31:0] op_b_i; - input wire [33:0] alu_adder_ext_i; - input wire [31:0] alu_adder_i; - input wire equal_to_zero_i; - input wire data_ind_timing_i; - output reg [32:0] alu_operand_a_o; - output reg [32:0] alu_operand_b_o; - input wire [67:0] imd_val_q_i; - output wire [67:0] imd_val_d_o; - output wire [1:0] imd_val_we_o; - input wire multdiv_ready_id_i; - output wire [31:0] multdiv_result_o; - output wire valid_o; - wire signed [34:0] mac_res_signed; - wire [34:0] mac_res_ext; - reg [33:0] accum; - reg sign_a; - reg sign_b; - reg mult_valid; - wire signed_mult; - reg [33:0] mac_res_d; - reg [33:0] op_remainder_d; - wire [33:0] mac_res; - wire div_sign_a; - wire div_sign_b; - reg is_greater_equal; - wire div_change_sign; - wire rem_change_sign; - wire [31:0] one_shift; - wire [31:0] op_denominator_q; - reg [31:0] op_numerator_q; - reg [31:0] op_quotient_q; - reg [31:0] op_denominator_d; - reg [31:0] op_numerator_d; - reg [31:0] op_quotient_d; - wire [31:0] next_remainder; - wire [32:0] next_quotient; - wire [31:0] res_adder_h; - reg div_valid; - reg [4:0] div_counter_q; - reg [4:0] div_counter_d; - wire multdiv_en; - reg mult_hold; - reg div_hold; - reg div_by_zero_d; - reg div_by_zero_q; - wire mult_en_internal; - wire div_en_internal; - reg [2:0] md_state_q; - reg [2:0] md_state_d; - wire unused_mult_sel_i; - assign unused_mult_sel_i = mult_sel_i; - assign mult_en_internal = mult_en_i & ~mult_hold; - assign div_en_internal = div_en_i & ~div_hold; - localparam [2:0] MD_IDLE = 0; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) begin - div_counter_q <= {5 {1'sb0}}; - md_state_q <= MD_IDLE; - op_numerator_q <= {32 {1'sb0}}; - op_quotient_q <= {32 {1'sb0}}; - div_by_zero_q <= 1'b0; - end - else if (div_en_internal) begin - div_counter_q <= div_counter_d; - op_numerator_q <= op_numerator_d; - op_quotient_q <= op_quotient_d; - md_state_q <= md_state_d; - div_by_zero_q <= div_by_zero_d; - end - assign multdiv_en = mult_en_internal | div_en_internal; - assign imd_val_d_o[34+:34] = (div_sel_i ? op_remainder_d : mac_res_d); - assign imd_val_we_o[0] = multdiv_en; - assign imd_val_d_o[0+:34] = {2'b00, op_denominator_d}; - assign imd_val_we_o[1] = div_en_internal; - assign op_denominator_q = imd_val_q_i[31-:32]; - wire [1:0] unused_imd_val; - assign unused_imd_val = imd_val_q_i[33-:2]; - wire unused_mac_res_ext; - assign unused_mac_res_ext = mac_res_ext[34]; - assign signed_mult = signed_mode_i != 2'b00; - assign multdiv_result_o = (div_sel_i ? imd_val_q_i[65-:32] : mac_res_d[31:0]); - localparam [1:0] AHBH = 3; - localparam [1:0] AHBL = 2; - localparam [1:0] ALBH = 1; - localparam [1:0] ALBL = 0; - localparam [0:0] MULH = 1; - localparam [0:0] MULL = 0; - localparam [1:0] ibex_pkg_MD_OP_MULL = 0; - localparam integer ibex_pkg_RV32MSingleCycle = 3; - generate - if (RV32M == ibex_pkg_RV32MSingleCycle) begin : gen_mult_single_cycle - reg mult_state_q; - reg mult_state_d; - wire signed [33:0] mult1_res; - wire signed [33:0] mult2_res; - wire signed [33:0] mult3_res; - wire [33:0] mult1_res_uns; - wire [33:32] unused_mult1_res_uns; - wire [15:0] mult1_op_a; - wire [15:0] mult1_op_b; - wire [15:0] mult2_op_a; - wire [15:0] mult2_op_b; - reg [15:0] mult3_op_a; - reg [15:0] mult3_op_b; - wire mult1_sign_a; - wire mult1_sign_b; - wire mult2_sign_a; - wire mult2_sign_b; - reg mult3_sign_a; - reg mult3_sign_b; - reg [33:0] summand1; - reg [33:0] summand2; - reg [33:0] summand3; - assign mult1_res = $signed({mult1_sign_a, mult1_op_a}) * $signed({mult1_sign_b, mult1_op_b}); - assign mult2_res = $signed({mult2_sign_a, mult2_op_a}) * $signed({mult2_sign_b, mult2_op_b}); - assign mult3_res = $signed({mult3_sign_a, mult3_op_a}) * $signed({mult3_sign_b, mult3_op_b}); - assign mac_res_signed = ($signed(summand1) + $signed(summand2)) + $signed(summand3); - assign mult1_res_uns = $unsigned(mult1_res); - assign mac_res_ext = $unsigned(mac_res_signed); - assign mac_res = mac_res_ext[33:0]; - wire [1:1] sv2v_tmp_1E8D3; - assign sv2v_tmp_1E8D3 = signed_mode_i[0] & op_a_i[31]; - always @(*) sign_a = sv2v_tmp_1E8D3; - wire [1:1] sv2v_tmp_3B65C; - assign sv2v_tmp_3B65C = signed_mode_i[1] & op_b_i[31]; - always @(*) sign_b = sv2v_tmp_3B65C; - assign mult1_sign_a = 1'b0; - assign mult1_sign_b = 1'b0; - assign mult1_op_a = op_a_i[15:0]; - assign mult1_op_b = op_b_i[15:0]; - assign mult2_sign_a = 1'b0; - assign mult2_sign_b = sign_b; - assign mult2_op_a = op_a_i[15:0]; - assign mult2_op_b = op_b_i[31:16]; - wire [18:1] sv2v_tmp_4D45D; - assign sv2v_tmp_4D45D = imd_val_q_i[67-:18]; - always @(*) accum[17:0] = sv2v_tmp_4D45D; - wire [16:1] sv2v_tmp_D5F47; - assign sv2v_tmp_D5F47 = {16 {signed_mult & imd_val_q_i[67]}}; - always @(*) accum[33:18] = sv2v_tmp_D5F47; - always @(*) begin - mult3_sign_a = sign_a; - mult3_sign_b = 1'b0; - mult3_op_a = op_a_i[31:16]; - mult3_op_b = op_b_i[15:0]; - summand1 = {18'h00000, mult1_res_uns[31:16]}; - summand2 = $unsigned(mult2_res); - summand3 = $unsigned(mult3_res); - mac_res_d = {2'b00, mac_res[15:0], mult1_res_uns[15:0]}; - mult_valid = mult_en_i; - mult_state_d = MULL; - mult_hold = 1'b0; - case (mult_state_q) - MULL: - if (operator_i != ibex_pkg_MD_OP_MULL) begin - mac_res_d = mac_res; - mult_valid = 1'b0; - mult_state_d = MULH; - end - else - mult_hold = ~multdiv_ready_id_i; - MULH: begin - mult3_sign_a = sign_a; - mult3_sign_b = sign_b; - mult3_op_a = op_a_i[31:16]; - mult3_op_b = op_b_i[31:16]; - mac_res_d = mac_res; - summand1 = {34 {1'sb0}}; - summand2 = accum; - summand3 = mult3_res; - mult_state_d = MULL; - mult_valid = 1'b1; - mult_hold = ~multdiv_ready_id_i; - end - default: mult_state_d = MULL; - endcase - end - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - mult_state_q <= MULL; - else if (mult_en_internal) - mult_state_q <= mult_state_d; - assign unused_mult1_res_uns = mult1_res_uns[33:32]; - end - else begin : gen_mult_fast - reg [15:0] mult_op_a; - reg [15:0] mult_op_b; - reg [1:0] mult_state_q; - reg [1:0] mult_state_d; - assign mac_res_signed = ($signed({sign_a, mult_op_a}) * $signed({sign_b, mult_op_b})) + $signed(accum); - assign mac_res_ext = $unsigned(mac_res_signed); - assign mac_res = mac_res_ext[33:0]; - always @(*) begin - mult_op_a = op_a_i[15:0]; - mult_op_b = op_b_i[15:0]; - sign_a = 1'b0; - sign_b = 1'b0; - accum = imd_val_q_i[34+:34]; - mac_res_d = mac_res; - mult_state_d = mult_state_q; - mult_valid = 1'b0; - mult_hold = 1'b0; - case (mult_state_q) - ALBL: begin - mult_op_a = op_a_i[15:0]; - mult_op_b = op_b_i[15:0]; - sign_a = 1'b0; - sign_b = 1'b0; - accum = {34 {1'sb0}}; - mac_res_d = mac_res; - mult_state_d = ALBH; - end - ALBH: begin - mult_op_a = op_a_i[15:0]; - mult_op_b = op_b_i[31:16]; - sign_a = 1'b0; - sign_b = signed_mode_i[1] & op_b_i[31]; - accum = {18'b000000000000000000, imd_val_q_i[65-:16]}; - if (operator_i == ibex_pkg_MD_OP_MULL) - mac_res_d = {2'b00, mac_res[15:0], imd_val_q_i[49-:16]}; - else - mac_res_d = mac_res; - mult_state_d = AHBL; - end - AHBL: begin - mult_op_a = op_a_i[31:16]; - mult_op_b = op_b_i[15:0]; - sign_a = signed_mode_i[0] & op_a_i[31]; - sign_b = 1'b0; - if (operator_i == ibex_pkg_MD_OP_MULL) begin - accum = {18'b000000000000000000, imd_val_q_i[65-:16]}; - mac_res_d = {2'b00, mac_res[15:0], imd_val_q_i[49-:16]}; - mult_valid = 1'b1; - mult_state_d = ALBL; - mult_hold = ~multdiv_ready_id_i; - end - else begin - accum = imd_val_q_i[34+:34]; - mac_res_d = mac_res; - mult_state_d = AHBH; - end - end - AHBH: begin - mult_op_a = op_a_i[31:16]; - mult_op_b = op_b_i[31:16]; - sign_a = signed_mode_i[0] & op_a_i[31]; - sign_b = signed_mode_i[1] & op_b_i[31]; - accum[17:0] = imd_val_q_i[67-:18]; - accum[33:18] = {16 {signed_mult & imd_val_q_i[67]}}; - mac_res_d = mac_res; - mult_valid = 1'b1; - mult_state_d = ALBL; - mult_hold = ~multdiv_ready_id_i; - end - default: mult_state_d = ALBL; - endcase - end - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - mult_state_q <= ALBL; - else if (mult_en_internal) - mult_state_q <= mult_state_d; - end - endgenerate - assign res_adder_h = alu_adder_ext_i[32:1]; - wire [1:0] unused_alu_adder_ext; - assign unused_alu_adder_ext = {alu_adder_ext_i[33], alu_adder_ext_i[0]}; - assign next_remainder = (is_greater_equal ? res_adder_h[31:0] : imd_val_q_i[65-:32]); - assign next_quotient = (is_greater_equal ? {1'b0, op_quotient_q} | {1'b0, one_shift} : {1'b0, op_quotient_q}); - assign one_shift = {31'b0000000000000000000000000000000, 1'b1} << div_counter_q; - always @(*) - if ((imd_val_q_i[65] ^ op_denominator_q[31]) == 1'b0) - is_greater_equal = res_adder_h[31] == 1'b0; - else - is_greater_equal = imd_val_q_i[65]; - assign div_sign_a = op_a_i[31] & signed_mode_i[0]; - assign div_sign_b = op_b_i[31] & signed_mode_i[1]; - assign div_change_sign = (div_sign_a ^ div_sign_b) & ~div_by_zero_q; - assign rem_change_sign = div_sign_a; - localparam [2:0] MD_ABS_A = 1; - localparam [2:0] MD_ABS_B = 2; - localparam [2:0] MD_CHANGE_SIGN = 5; - localparam [2:0] MD_COMP = 3; - localparam [2:0] MD_FINISH = 6; - localparam [2:0] MD_LAST = 4; - localparam [1:0] ibex_pkg_MD_OP_DIV = 2; - always @(*) begin - div_counter_d = div_counter_q - 5'h01; - op_remainder_d = imd_val_q_i[34+:34]; - op_quotient_d = op_quotient_q; - md_state_d = md_state_q; - op_numerator_d = op_numerator_q; - op_denominator_d = op_denominator_q; - alu_operand_a_o = {32'h00000000, 1'b1}; - alu_operand_b_o = {~op_b_i, 1'b1}; - div_valid = 1'b0; - div_hold = 1'b0; - div_by_zero_d = div_by_zero_q; - case (md_state_q) - MD_IDLE: begin - if (operator_i == ibex_pkg_MD_OP_DIV) begin - op_remainder_d = {34 {1'sb1}}; - md_state_d = (!data_ind_timing_i && equal_to_zero_i ? MD_FINISH : MD_ABS_A); - div_by_zero_d = equal_to_zero_i; - end - else begin - op_remainder_d = {2'b00, op_a_i}; - md_state_d = (!data_ind_timing_i && equal_to_zero_i ? MD_FINISH : MD_ABS_A); - end - alu_operand_a_o = {32'h00000000, 1'b1}; - alu_operand_b_o = {~op_b_i, 1'b1}; - div_counter_d = 5'd31; - end - MD_ABS_A: begin - op_quotient_d = {32 {1'sb0}}; - op_numerator_d = (div_sign_a ? alu_adder_i : op_a_i); - md_state_d = MD_ABS_B; - div_counter_d = 5'd31; - alu_operand_a_o = {32'h00000000, 1'b1}; - alu_operand_b_o = {~op_a_i, 1'b1}; - end - MD_ABS_B: begin - op_remainder_d = {33'h000000000, op_numerator_q[31]}; - op_denominator_d = (div_sign_b ? alu_adder_i : op_b_i); - md_state_d = MD_COMP; - div_counter_d = 5'd31; - alu_operand_a_o = {32'h00000000, 1'b1}; - alu_operand_b_o = {~op_b_i, 1'b1}; - end - MD_COMP: begin - op_remainder_d = {1'b0, next_remainder[31:0], op_numerator_q[div_counter_d]}; - op_quotient_d = next_quotient[31:0]; - md_state_d = (div_counter_q == 5'd1 ? MD_LAST : MD_COMP); - alu_operand_a_o = {imd_val_q_i[65-:32], 1'b1}; - alu_operand_b_o = {~op_denominator_q[31:0], 1'b1}; - end - MD_LAST: begin - if (operator_i == ibex_pkg_MD_OP_DIV) - op_remainder_d = {1'b0, next_quotient}; - else - op_remainder_d = {2'b00, next_remainder[31:0]}; - alu_operand_a_o = {imd_val_q_i[65-:32], 1'b1}; - alu_operand_b_o = {~op_denominator_q[31:0], 1'b1}; - md_state_d = MD_CHANGE_SIGN; - end - MD_CHANGE_SIGN: begin - md_state_d = MD_FINISH; - if (operator_i == ibex_pkg_MD_OP_DIV) - op_remainder_d = (div_change_sign ? {2'h0, alu_adder_i} : imd_val_q_i[34+:34]); - else - op_remainder_d = (rem_change_sign ? {2'h0, alu_adder_i} : imd_val_q_i[34+:34]); - alu_operand_a_o = {32'h00000000, 1'b1}; - alu_operand_b_o = {~imd_val_q_i[65-:32], 1'b1}; - end - MD_FINISH: begin - md_state_d = MD_IDLE; - div_hold = ~multdiv_ready_id_i; - div_valid = 1'b1; - end - default: md_state_d = MD_IDLE; - endcase - end - assign valid_o = mult_valid | div_valid; -endmodule diff --git a/flow/designs/src/ibex/ibex_multdiv_slow.v b/flow/designs/src/ibex/ibex_multdiv_slow.v deleted file mode 100644 index 84934ee753..0000000000 --- a/flow/designs/src/ibex/ibex_multdiv_slow.v +++ /dev/null @@ -1,279 +0,0 @@ -module ibex_multdiv_slow ( - clk_i, - rst_ni, - mult_en_i, - div_en_i, - mult_sel_i, - div_sel_i, - operator_i, - signed_mode_i, - op_a_i, - op_b_i, - alu_adder_ext_i, - alu_adder_i, - equal_to_zero_i, - data_ind_timing_i, - alu_operand_a_o, - alu_operand_b_o, - imd_val_q_i, - imd_val_d_o, - imd_val_we_o, - multdiv_ready_id_i, - multdiv_result_o, - valid_o -); - input wire clk_i; - input wire rst_ni; - input wire mult_en_i; - input wire div_en_i; - input wire mult_sel_i; - input wire div_sel_i; - input wire [1:0] operator_i; - input wire [1:0] signed_mode_i; - input wire [31:0] op_a_i; - input wire [31:0] op_b_i; - input wire [33:0] alu_adder_ext_i; - input wire [31:0] alu_adder_i; - input wire equal_to_zero_i; - input wire data_ind_timing_i; - output reg [32:0] alu_operand_a_o; - output reg [32:0] alu_operand_b_o; - input wire [67:0] imd_val_q_i; - output wire [67:0] imd_val_d_o; - output wire [1:0] imd_val_we_o; - input wire multdiv_ready_id_i; - output wire [31:0] multdiv_result_o; - output wire valid_o; - reg [2:0] md_state_q; - reg [2:0] md_state_d; - wire [32:0] accum_window_q; - reg [32:0] accum_window_d; - wire unused_imd_val0; - wire [1:0] unused_imd_val1; - wire [32:0] res_adder_l; - wire [32:0] res_adder_h; - reg [4:0] multdiv_count_q; - reg [4:0] multdiv_count_d; - reg [32:0] op_b_shift_q; - reg [32:0] op_b_shift_d; - reg [32:0] op_a_shift_q; - reg [32:0] op_a_shift_d; - wire [32:0] op_a_ext; - wire [32:0] op_b_ext; - wire [32:0] one_shift; - wire [32:0] op_a_bw_pp; - wire [32:0] op_a_bw_last_pp; - wire [31:0] b_0; - wire sign_a; - wire sign_b; - wire [32:0] next_quotient; - wire [31:0] next_remainder; - wire [31:0] op_numerator_q; - reg [31:0] op_numerator_d; - wire is_greater_equal; - wire div_change_sign; - wire rem_change_sign; - reg div_by_zero_d; - reg div_by_zero_q; - reg multdiv_hold; - wire multdiv_en; - assign res_adder_l = alu_adder_ext_i[32:0]; - assign res_adder_h = alu_adder_ext_i[33:1]; - assign imd_val_d_o[34+:34] = {1'b0, accum_window_d}; - assign imd_val_we_o[0] = ~multdiv_hold; - assign accum_window_q = imd_val_q_i[66-:33]; - assign unused_imd_val0 = imd_val_q_i[67]; - assign imd_val_d_o[0+:34] = {2'b00, op_numerator_d}; - assign imd_val_we_o[1] = multdiv_en; - assign op_numerator_q = imd_val_q_i[31-:32]; - assign unused_imd_val1 = imd_val_q_i[33-:2]; - localparam [2:0] MD_ABS_A = 1; - localparam [2:0] MD_ABS_B = 2; - localparam [2:0] MD_CHANGE_SIGN = 5; - localparam [2:0] MD_IDLE = 0; - localparam [2:0] MD_LAST = 4; - localparam [1:0] ibex_pkg_MD_OP_DIV = 2; - localparam [1:0] ibex_pkg_MD_OP_MULH = 1; - localparam [1:0] ibex_pkg_MD_OP_MULL = 0; - localparam [1:0] ibex_pkg_MD_OP_REM = 3; - always @(*) begin - alu_operand_a_o = accum_window_q; - case (operator_i) - ibex_pkg_MD_OP_MULL: alu_operand_b_o = op_a_bw_pp; - ibex_pkg_MD_OP_MULH: alu_operand_b_o = (md_state_q == MD_LAST ? op_a_bw_last_pp : op_a_bw_pp); - ibex_pkg_MD_OP_DIV, ibex_pkg_MD_OP_REM: - case (md_state_q) - MD_IDLE: begin - alu_operand_a_o = {32'h00000000, 1'b1}; - alu_operand_b_o = {~op_b_i, 1'b1}; - end - MD_ABS_A: begin - alu_operand_a_o = {32'h00000000, 1'b1}; - alu_operand_b_o = {~op_a_i, 1'b1}; - end - MD_ABS_B: begin - alu_operand_a_o = {32'h00000000, 1'b1}; - alu_operand_b_o = {~op_b_i, 1'b1}; - end - MD_CHANGE_SIGN: begin - alu_operand_a_o = {32'h00000000, 1'b1}; - alu_operand_b_o = {~accum_window_q[31:0], 1'b1}; - end - default: begin - alu_operand_a_o = {accum_window_q[31:0], 1'b1}; - alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1}; - end - endcase - default: begin - alu_operand_a_o = accum_window_q; - alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1}; - end - endcase - end - assign b_0 = {32 {op_b_shift_q[0]}}; - assign op_a_bw_pp = {~(op_a_shift_q[32] & op_b_shift_q[0]), op_a_shift_q[31:0] & b_0}; - assign op_a_bw_last_pp = {op_a_shift_q[32] & op_b_shift_q[0], ~(op_a_shift_q[31:0] & b_0)}; - assign sign_a = op_a_i[31] & signed_mode_i[0]; - assign sign_b = op_b_i[31] & signed_mode_i[1]; - assign op_a_ext = {sign_a, op_a_i}; - assign op_b_ext = {sign_b, op_b_i}; - assign is_greater_equal = (accum_window_q[31] == op_b_shift_q[31] ? ~res_adder_h[31] : accum_window_q[31]); - assign one_shift = {32'b00000000000000000000000000000000, 1'b1} << multdiv_count_q; - assign next_remainder = (is_greater_equal ? res_adder_h[31:0] : accum_window_q[31:0]); - assign next_quotient = (is_greater_equal ? op_a_shift_q | one_shift : op_a_shift_q); - assign div_change_sign = (sign_a ^ sign_b) & ~div_by_zero_q; - assign rem_change_sign = sign_a; - localparam [2:0] MD_COMP = 3; - localparam [2:0] MD_FINISH = 6; - always @(*) begin - multdiv_count_d = multdiv_count_q; - accum_window_d = accum_window_q; - op_b_shift_d = op_b_shift_q; - op_a_shift_d = op_a_shift_q; - op_numerator_d = op_numerator_q; - md_state_d = md_state_q; - multdiv_hold = 1'b0; - div_by_zero_d = div_by_zero_q; - if (mult_sel_i || div_sel_i) - case (md_state_q) - MD_IDLE: begin - case (operator_i) - ibex_pkg_MD_OP_MULL: begin - op_a_shift_d = op_a_ext << 1; - accum_window_d = {~(op_a_ext[32] & op_b_i[0]), op_a_ext[31:0] & {32 {op_b_i[0]}}}; - op_b_shift_d = op_b_ext >> 1; - md_state_d = (!data_ind_timing_i && ((op_b_ext >> 1) == 0) ? MD_LAST : MD_COMP); - end - ibex_pkg_MD_OP_MULH: begin - op_a_shift_d = op_a_ext; - accum_window_d = {1'b1, ~(op_a_ext[32] & op_b_i[0]), op_a_ext[31:1] & {31 {op_b_i[0]}}}; - op_b_shift_d = op_b_ext >> 1; - md_state_d = MD_COMP; - end - ibex_pkg_MD_OP_DIV: begin - accum_window_d = {33 {1'b1}}; - md_state_d = (!data_ind_timing_i && equal_to_zero_i ? MD_FINISH : MD_ABS_A); - div_by_zero_d = equal_to_zero_i; - end - ibex_pkg_MD_OP_REM: begin - accum_window_d = op_a_ext; - md_state_d = (!data_ind_timing_i && equal_to_zero_i ? MD_FINISH : MD_ABS_A); - end - default: - ; - endcase - multdiv_count_d = 5'd31; - end - MD_ABS_A: begin - op_a_shift_d = {33 {1'sb0}}; - op_numerator_d = (sign_a ? alu_adder_i : op_a_i); - md_state_d = MD_ABS_B; - end - MD_ABS_B: begin - accum_window_d = {32'h00000000, op_numerator_q[31]}; - op_b_shift_d = (sign_b ? {1'b0, alu_adder_i} : {1'b0, op_b_i}); - md_state_d = MD_COMP; - end - MD_COMP: begin - multdiv_count_d = multdiv_count_q - 5'h01; - case (operator_i) - ibex_pkg_MD_OP_MULL: begin - accum_window_d = res_adder_l; - op_a_shift_d = op_a_shift_q << 1; - op_b_shift_d = op_b_shift_q >> 1; - md_state_d = ((!data_ind_timing_i && (op_b_shift_d == 0)) || (multdiv_count_q == 5'd1) ? MD_LAST : MD_COMP); - end - ibex_pkg_MD_OP_MULH: begin - accum_window_d = res_adder_h; - op_a_shift_d = op_a_shift_q; - op_b_shift_d = op_b_shift_q >> 1; - md_state_d = (multdiv_count_q == 5'd1 ? MD_LAST : MD_COMP); - end - ibex_pkg_MD_OP_DIV, ibex_pkg_MD_OP_REM: begin - accum_window_d = {next_remainder[31:0], op_numerator_q[multdiv_count_d]}; - op_a_shift_d = next_quotient; - md_state_d = (multdiv_count_q == 5'd1 ? MD_LAST : MD_COMP); - end - default: - ; - endcase - end - MD_LAST: - case (operator_i) - ibex_pkg_MD_OP_MULL: begin - accum_window_d = res_adder_l; - md_state_d = MD_IDLE; - multdiv_hold = ~multdiv_ready_id_i; - end - ibex_pkg_MD_OP_MULH: begin - accum_window_d = res_adder_l; - md_state_d = MD_IDLE; - md_state_d = MD_IDLE; - multdiv_hold = ~multdiv_ready_id_i; - end - ibex_pkg_MD_OP_DIV: begin - accum_window_d = next_quotient; - md_state_d = MD_CHANGE_SIGN; - end - ibex_pkg_MD_OP_REM: begin - accum_window_d = {1'b0, next_remainder[31:0]}; - md_state_d = MD_CHANGE_SIGN; - end - default: - ; - endcase - MD_CHANGE_SIGN: begin - md_state_d = MD_FINISH; - case (operator_i) - ibex_pkg_MD_OP_DIV: accum_window_d = (div_change_sign ? {1'b0, alu_adder_i} : accum_window_q); - ibex_pkg_MD_OP_REM: accum_window_d = (rem_change_sign ? {1'b0, alu_adder_i} : accum_window_q); - default: - ; - endcase - end - MD_FINISH: begin - md_state_d = MD_IDLE; - multdiv_hold = ~multdiv_ready_id_i; - end - default: md_state_d = MD_IDLE; - endcase - end - assign multdiv_en = (mult_en_i | div_en_i) & ~multdiv_hold; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) begin - multdiv_count_q <= 5'h00; - op_b_shift_q <= 33'h000000000; - op_a_shift_q <= 33'h000000000; - md_state_q <= MD_IDLE; - div_by_zero_q <= 1'b0; - end - else if (multdiv_en) begin - multdiv_count_q <= multdiv_count_d; - op_b_shift_q <= op_b_shift_d; - op_a_shift_q <= op_a_shift_d; - md_state_q <= md_state_d; - div_by_zero_q <= div_by_zero_d; - end - assign valid_o = (md_state_q == MD_FINISH) | ((md_state_q == MD_LAST) & ((operator_i == ibex_pkg_MD_OP_MULL) | (operator_i == ibex_pkg_MD_OP_MULH))); - assign multdiv_result_o = (div_en_i ? accum_window_q[31:0] : res_adder_l[31:0]); -endmodule diff --git a/flow/designs/src/ibex/ibex_pmp.v b/flow/designs/src/ibex/ibex_pmp.v deleted file mode 100644 index 5487cc0271..0000000000 --- a/flow/designs/src/ibex/ibex_pmp.v +++ /dev/null @@ -1,89 +0,0 @@ -module ibex_pmp ( - clk_i, - rst_ni, - csr_pmp_cfg_i, - csr_pmp_addr_i, - priv_mode_i, - pmp_req_addr_i, - pmp_req_type_i, - pmp_req_err_o -); - parameter [31:0] PMPGranularity = 0; - parameter [31:0] PMPNumChan = 2; - parameter [31:0] PMPNumRegions = 4; - input wire clk_i; - input wire rst_ni; - input wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 6) + (((PMPNumRegions - 1) * 6) - 1) : (PMPNumRegions * 6) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 6 : 0)] csr_pmp_cfg_i; - input wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 34) + (((PMPNumRegions - 1) * 34) - 1) : (PMPNumRegions * 34) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 34 : 0)] csr_pmp_addr_i; - input wire [(0 >= (PMPNumChan - 1) ? ((2 - PMPNumChan) * 2) + (((PMPNumChan - 1) * 2) - 1) : (PMPNumChan * 2) - 1):(0 >= (PMPNumChan - 1) ? (PMPNumChan - 1) * 2 : 0)] priv_mode_i; - input wire [(0 >= (PMPNumChan - 1) ? ((2 - PMPNumChan) * 34) + (((PMPNumChan - 1) * 34) - 1) : (PMPNumChan * 34) - 1):(0 >= (PMPNumChan - 1) ? (PMPNumChan - 1) * 34 : 0)] pmp_req_addr_i; - input wire [(0 >= (PMPNumChan - 1) ? ((2 - PMPNumChan) * 2) + (((PMPNumChan - 1) * 2) - 1) : (PMPNumChan * 2) - 1):(0 >= (PMPNumChan - 1) ? (PMPNumChan - 1) * 2 : 0)] pmp_req_type_i; - output wire [0:PMPNumChan - 1] pmp_req_err_o; - wire [33:0] region_start_addr [0:PMPNumRegions - 1]; - wire [33:PMPGranularity + 2] region_addr_mask [0:PMPNumRegions - 1]; - wire [(PMPNumChan * PMPNumRegions) - 1:0] region_match_gt; - wire [(PMPNumChan * PMPNumRegions) - 1:0] region_match_lt; - wire [(PMPNumChan * PMPNumRegions) - 1:0] region_match_eq; - reg [(PMPNumChan * PMPNumRegions) - 1:0] region_match_all; - wire [(PMPNumChan * PMPNumRegions) - 1:0] region_perm_check; - reg [PMPNumChan - 1:0] access_fault; - localparam [1:0] ibex_pkg_PMP_MODE_NAPOT = 2'b11; - localparam [1:0] ibex_pkg_PMP_MODE_TOR = 2'b01; - generate - genvar r; - for (r = 0; r < PMPNumRegions; r = r + 1) begin : g_addr_exp - if (r == 0) begin : g_entry0 - assign region_start_addr[r] = (csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2] == ibex_pkg_PMP_MODE_TOR ? 34'h000000000 : csr_pmp_addr_i[(0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 34+:34]); - end - else begin : g_oth - assign region_start_addr[r] = (csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2] == ibex_pkg_PMP_MODE_TOR ? csr_pmp_addr_i[(0 >= (PMPNumRegions - 1) ? r - 1 : (PMPNumRegions - 1) - (r - 1)) * 34+:34] : csr_pmp_addr_i[(0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 34+:34]); - end - genvar b; - for (b = PMPGranularity + 2; b < 34; b = b + 1) begin : g_bitmask - if (b == 2) begin : g_bit0 - assign region_addr_mask[r][b] = csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2] != ibex_pkg_PMP_MODE_NAPOT; - end - else begin : g_others - assign region_addr_mask[r][b] = (csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2] != ibex_pkg_PMP_MODE_NAPOT) | ~&csr_pmp_addr_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 34) + ((b - 1) >= (PMPGranularity + 1) ? b - 1 : ((b - 1) + ((b - 1) >= (PMPGranularity + 1) ? ((b - 1) - (PMPGranularity + 1)) + 1 : ((PMPGranularity + 1) - (b - 1)) + 1)) - 1)-:((b - 1) >= (PMPGranularity + 1) ? ((b - 1) - (PMPGranularity + 1)) + 1 : ((PMPGranularity + 1) - (b - 1)) + 1)]; - end - end - end - endgenerate - localparam [1:0] ibex_pkg_PMP_ACC_EXEC = 2'b00; - localparam [1:0] ibex_pkg_PMP_ACC_READ = 2'b10; - localparam [1:0] ibex_pkg_PMP_ACC_WRITE = 2'b01; - localparam [1:0] ibex_pkg_PMP_MODE_NA4 = 2'b10; - localparam [1:0] ibex_pkg_PMP_MODE_OFF = 2'b00; - localparam [1:0] ibex_pkg_PRIV_LVL_M = 2'b11; - generate - genvar c; - for (c = 0; c < PMPNumChan; c = c + 1) begin : g_access_check - for (r = 0; r < PMPNumRegions; r = r + 1) begin : g_regions - assign region_match_eq[(c * PMPNumRegions) + r] = (pmp_req_addr_i[((0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 34) + (33 >= (PMPGranularity + 2) ? 33 : (33 + (33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)) - 1)-:(33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)] & region_addr_mask[r]) == (region_start_addr[r][33:PMPGranularity + 2] & region_addr_mask[r]); - assign region_match_gt[(c * PMPNumRegions) + r] = pmp_req_addr_i[((0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 34) + (33 >= (PMPGranularity + 2) ? 33 : (33 + (33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)) - 1)-:(33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)] > region_start_addr[r][33:PMPGranularity + 2]; - assign region_match_lt[(c * PMPNumRegions) + r] = pmp_req_addr_i[((0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 34) + (33 >= (PMPGranularity + 2) ? 33 : (33 + (33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)) - 1)-:(33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)] < csr_pmp_addr_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 34) + (33 >= (PMPGranularity + 2) ? 33 : (33 + (33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)) - 1)-:(33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)]; - always @(*) begin - region_match_all[(c * PMPNumRegions) + r] = 1'b0; - case (csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2]) - ibex_pkg_PMP_MODE_OFF: region_match_all[(c * PMPNumRegions) + r] = 1'b0; - ibex_pkg_PMP_MODE_NA4: region_match_all[(c * PMPNumRegions) + r] = region_match_eq[(c * PMPNumRegions) + r]; - ibex_pkg_PMP_MODE_NAPOT: region_match_all[(c * PMPNumRegions) + r] = region_match_eq[(c * PMPNumRegions) + r]; - ibex_pkg_PMP_MODE_TOR: region_match_all[(c * PMPNumRegions) + r] = (region_match_eq[(c * PMPNumRegions) + r] | region_match_gt[(c * PMPNumRegions) + r]) & region_match_lt[(c * PMPNumRegions) + r]; - default: region_match_all[(c * PMPNumRegions) + r] = 1'b0; - endcase - end - assign region_perm_check[(c * PMPNumRegions) + r] = (((pmp_req_type_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] == ibex_pkg_PMP_ACC_EXEC) & csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 2]) | ((pmp_req_type_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] == ibex_pkg_PMP_ACC_WRITE) & csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 1])) | ((pmp_req_type_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] == ibex_pkg_PMP_ACC_READ) & csr_pmp_cfg_i[(0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6]); - end - always @(*) begin - access_fault[c] = priv_mode_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] != ibex_pkg_PRIV_LVL_M; - begin : sv2v_autoblock_1 - reg signed [31:0] r; - for (r = PMPNumRegions - 1; r >= 0; r = r - 1) - if (region_match_all[(c * PMPNumRegions) + r]) - access_fault[c] = (priv_mode_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] == ibex_pkg_PRIV_LVL_M ? csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 5] & ~region_perm_check[(c * PMPNumRegions) + r] : ~region_perm_check[(c * PMPNumRegions) + r]); - end - end - assign pmp_req_err_o[c] = access_fault[c]; - end - endgenerate -endmodule diff --git a/flow/designs/src/ibex/ibex_prefetch_buffer.v b/flow/designs/src/ibex/ibex_prefetch_buffer.v deleted file mode 100644 index c954b108c3..0000000000 --- a/flow/designs/src/ibex/ibex_prefetch_buffer.v +++ /dev/null @@ -1,188 +0,0 @@ -module ibex_prefetch_buffer ( - clk_i, - rst_ni, - req_i, - branch_i, - branch_spec_i, - predicted_branch_i, - branch_mispredict_i, - addr_i, - ready_i, - valid_o, - rdata_o, - addr_o, - err_o, - err_plus2_o, - instr_req_o, - instr_gnt_i, - instr_addr_o, - instr_rdata_i, - instr_err_i, - instr_pmp_err_i, - instr_rvalid_i, - busy_o -); - parameter [0:0] BranchPredictor = 1'b0; - input wire clk_i; - input wire rst_ni; - input wire req_i; - input wire branch_i; - input wire branch_spec_i; - input wire predicted_branch_i; - input wire branch_mispredict_i; - input wire [31:0] addr_i; - input wire ready_i; - output wire valid_o; - output wire [31:0] rdata_o; - output wire [31:0] addr_o; - output wire err_o; - output wire err_plus2_o; - output wire instr_req_o; - input wire instr_gnt_i; - output wire [31:0] instr_addr_o; - input wire [31:0] instr_rdata_i; - input wire instr_err_i; - input wire instr_pmp_err_i; - input wire instr_rvalid_i; - output wire busy_o; - localparam [31:0] NUM_REQS = 2; - wire branch_suppress; - wire valid_new_req; - wire valid_req; - wire valid_req_d; - reg valid_req_q; - wire discard_req_d; - reg discard_req_q; - wire gnt_or_pmp_err; - wire rvalid_or_pmp_err; - wire [NUM_REQS - 1:0] rdata_outstanding_n; - wire [NUM_REQS - 1:0] rdata_outstanding_s; - reg [NUM_REQS - 1:0] rdata_outstanding_q; - wire [NUM_REQS - 1:0] branch_discard_n; - wire [NUM_REQS - 1:0] branch_discard_s; - reg [NUM_REQS - 1:0] branch_discard_q; - wire [NUM_REQS - 1:0] rdata_pmp_err_n; - wire [NUM_REQS - 1:0] rdata_pmp_err_s; - reg [NUM_REQS - 1:0] rdata_pmp_err_q; - wire [NUM_REQS - 1:0] rdata_outstanding_rev; - wire [31:0] stored_addr_d; - reg [31:0] stored_addr_q; - wire stored_addr_en; - wire [31:0] fetch_addr_d; - reg [31:0] fetch_addr_q; - wire fetch_addr_en; - wire [31:0] branch_mispredict_addr; - wire [31:0] instr_addr; - wire [31:0] instr_addr_w_aligned; - wire instr_or_pmp_err; - wire fifo_valid; - wire [31:0] fifo_addr; - wire fifo_ready; - wire fifo_clear; - wire [NUM_REQS - 1:0] fifo_busy; - wire valid_raw; - wire [31:0] addr_next; - wire branch_or_mispredict; - assign busy_o = |rdata_outstanding_q | instr_req_o; - assign branch_or_mispredict = branch_i | branch_mispredict_i; - assign instr_or_pmp_err = instr_err_i | rdata_pmp_err_q[0]; - assign fifo_clear = branch_or_mispredict; - generate - genvar i; - for (i = 0; i < NUM_REQS; i = i + 1) begin : gen_rd_rev - assign rdata_outstanding_rev[i] = rdata_outstanding_q[(NUM_REQS - 1) - i]; - end - endgenerate - assign fifo_ready = ~&(fifo_busy | rdata_outstanding_rev); - ibex_fetch_fifo #(.NUM_REQS(NUM_REQS)) fifo_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .clear_i(fifo_clear), - .busy_o(fifo_busy), - .in_valid_i(fifo_valid), - .in_addr_i(fifo_addr), - .in_rdata_i(instr_rdata_i), - .in_err_i(instr_or_pmp_err), - .out_valid_o(valid_raw), - .out_ready_i(ready_i), - .out_rdata_o(rdata_o), - .out_addr_o(addr_o), - .out_addr_next_o(addr_next), - .out_err_o(err_o), - .out_err_plus2_o(err_plus2_o) - ); - assign branch_suppress = branch_spec_i & ~branch_i; - assign valid_new_req = ((~branch_suppress & req_i) & (fifo_ready | branch_or_mispredict)) & ~rdata_outstanding_q[NUM_REQS - 1]; - assign valid_req = valid_req_q | valid_new_req; - assign gnt_or_pmp_err = instr_gnt_i | instr_pmp_err_i; - assign rvalid_or_pmp_err = rdata_outstanding_q[0] & (instr_rvalid_i | rdata_pmp_err_q[0]); - assign valid_req_d = valid_req & ~gnt_or_pmp_err; - assign discard_req_d = valid_req_q & (branch_or_mispredict | discard_req_q); - assign stored_addr_en = (valid_new_req & ~valid_req_q) & ~gnt_or_pmp_err; - assign stored_addr_d = instr_addr; - always @(posedge clk_i) - if (stored_addr_en) - stored_addr_q <= stored_addr_d; - generate - if (BranchPredictor) begin : g_branch_predictor - reg [31:0] branch_mispredict_addr_q; - wire branch_mispredict_addr_en; - assign branch_mispredict_addr_en = branch_i & predicted_branch_i; - always @(posedge clk_i) - if (branch_mispredict_addr_en) - branch_mispredict_addr_q <= addr_next; - assign branch_mispredict_addr = branch_mispredict_addr_q; - end - else begin : g_no_branch_predictor - wire unused_predicted_branch; - wire [31:0] unused_addr_next; - assign unused_predicted_branch = predicted_branch_i; - assign unused_addr_next = addr_next; - assign branch_mispredict_addr = {32 {1'sb0}}; - end - endgenerate - assign fetch_addr_en = branch_or_mispredict | (valid_new_req & ~valid_req_q); - assign fetch_addr_d = (branch_i ? addr_i : (branch_mispredict_i ? {branch_mispredict_addr[31:2], 2'b00} : {fetch_addr_q[31:2], 2'b00})) + {{29 {1'b0}}, valid_new_req & ~valid_req_q, 2'b00}; - always @(posedge clk_i) - if (fetch_addr_en) - fetch_addr_q <= fetch_addr_d; - assign instr_addr = (valid_req_q ? stored_addr_q : (branch_spec_i ? addr_i : (branch_mispredict_i ? branch_mispredict_addr : fetch_addr_q))); - assign instr_addr_w_aligned = {instr_addr[31:2], 2'b00}; - generate - for (i = 0; i < NUM_REQS; i = i + 1) begin : g_outstanding_reqs - if (i == 0) begin : g_req0 - assign rdata_outstanding_n[i] = (valid_req & gnt_or_pmp_err) | rdata_outstanding_q[i]; - assign branch_discard_n[i] = (((valid_req & gnt_or_pmp_err) & discard_req_d) | (branch_or_mispredict & rdata_outstanding_q[i])) | branch_discard_q[i]; - assign rdata_pmp_err_n[i] = ((valid_req & ~rdata_outstanding_q[i]) & instr_pmp_err_i) | rdata_pmp_err_q[i]; - end - else begin : g_reqtop - assign rdata_outstanding_n[i] = ((valid_req & gnt_or_pmp_err) & rdata_outstanding_q[i - 1]) | rdata_outstanding_q[i]; - assign branch_discard_n[i] = ((((valid_req & gnt_or_pmp_err) & discard_req_d) & rdata_outstanding_q[i - 1]) | (branch_or_mispredict & rdata_outstanding_q[i])) | branch_discard_q[i]; - assign rdata_pmp_err_n[i] = (((valid_req & ~rdata_outstanding_q[i]) & instr_pmp_err_i) & rdata_outstanding_q[i - 1]) | rdata_pmp_err_q[i]; - end - end - endgenerate - assign rdata_outstanding_s = (rvalid_or_pmp_err ? {1'b0, rdata_outstanding_n[NUM_REQS - 1:1]} : rdata_outstanding_n); - assign branch_discard_s = (rvalid_or_pmp_err ? {1'b0, branch_discard_n[NUM_REQS - 1:1]} : branch_discard_n); - assign rdata_pmp_err_s = (rvalid_or_pmp_err ? {1'b0, rdata_pmp_err_n[NUM_REQS - 1:1]} : rdata_pmp_err_n); - assign fifo_valid = rvalid_or_pmp_err & ~branch_discard_q[0]; - assign fifo_addr = (branch_mispredict_i ? branch_mispredict_addr : addr_i); - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) begin - valid_req_q <= 1'b0; - discard_req_q <= 1'b0; - rdata_outstanding_q <= 'b0; - branch_discard_q <= 'b0; - rdata_pmp_err_q <= 'b0; - end - else begin - valid_req_q <= valid_req_d; - discard_req_q <= discard_req_d; - rdata_outstanding_q <= rdata_outstanding_s; - branch_discard_q <= branch_discard_s; - rdata_pmp_err_q <= rdata_pmp_err_s; - end - assign instr_req_o = valid_req; - assign instr_addr_o = instr_addr_w_aligned; - assign valid_o = valid_raw & ~branch_mispredict_i; -endmodule diff --git a/flow/designs/src/ibex/ibex_register_file_ff.v b/flow/designs/src/ibex/ibex_register_file_ff.v deleted file mode 100644 index d70dad1e53..0000000000 --- a/flow/designs/src/ibex/ibex_register_file_ff.v +++ /dev/null @@ -1,77 +0,0 @@ -module ibex_register_file_ff ( - clk_i, - rst_ni, - test_en_i, - dummy_instr_id_i, - raddr_a_i, - rdata_a_o, - raddr_b_i, - rdata_b_o, - waddr_a_i, - wdata_a_i, - we_a_i -); - parameter [0:0] RV32E = 0; - parameter [31:0] DataWidth = 32; - parameter [0:0] DummyInstructions = 0; - input wire clk_i; - input wire rst_ni; - input wire test_en_i; - input wire dummy_instr_id_i; - input wire [4:0] raddr_a_i; - output wire [DataWidth - 1:0] rdata_a_o; - input wire [4:0] raddr_b_i; - output wire [DataWidth - 1:0] rdata_b_o; - input wire [4:0] waddr_a_i; - input wire [DataWidth - 1:0] wdata_a_i; - input wire we_a_i; - localparam [31:0] ADDR_WIDTH = (RV32E ? 4 : 5); - localparam [31:0] NUM_WORDS = 2 ** ADDR_WIDTH; - wire [(NUM_WORDS * DataWidth) - 1:0] rf_reg; - reg [((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) * DataWidth) + (DataWidth - 1) : ((3 - NUM_WORDS) * DataWidth) + (((NUM_WORDS - 1) * DataWidth) - 1)):((NUM_WORDS - 1) >= 1 ? DataWidth : (NUM_WORDS - 1) * DataWidth)] rf_reg_q; - reg [NUM_WORDS - 1:1] we_a_dec; - function automatic [4:0] sv2v_cast_5; - input reg [4:0] inp; - sv2v_cast_5 = inp; - endfunction - always @(*) begin : we_a_decoder - begin : sv2v_autoblock_2 - reg [31:0] i; - for (i = 1; i < NUM_WORDS; i = i + 1) - we_a_dec[i] = (waddr_a_i == sv2v_cast_5(i) ? we_a_i : 1'b0); - end - end - generate - genvar i; - for (i = 1; i < NUM_WORDS; i = i + 1) begin : g_rf_flops - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - rf_reg_q[((NUM_WORDS - 1) >= 1 ? i : 1 - (i - (NUM_WORDS - 1))) * DataWidth+:DataWidth] <= {DataWidth {1'sb0}}; - else if (we_a_dec[i]) - rf_reg_q[((NUM_WORDS - 1) >= 1 ? i : 1 - (i - (NUM_WORDS - 1))) * DataWidth+:DataWidth] <= wdata_a_i; - end - endgenerate - generate - if (DummyInstructions) begin : g_dummy_r0 - wire we_r0_dummy; - reg [DataWidth - 1:0] rf_r0_q; - assign we_r0_dummy = we_a_i & dummy_instr_id_i; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - rf_r0_q <= {DataWidth {1'sb0}}; - else if (we_r0_dummy) - rf_r0_q <= wdata_a_i; - assign rf_reg[0+:DataWidth] = (dummy_instr_id_i ? rf_r0_q : {DataWidth {1'sb0}}); - end - else begin : g_normal_r0 - wire unused_dummy_instr_id; - assign unused_dummy_instr_id = dummy_instr_id_i; - assign rf_reg[0+:DataWidth] = {DataWidth {1'sb0}}; - end - endgenerate - assign rf_reg[DataWidth * (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1) - (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS) - 1))+:DataWidth * ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)] = rf_reg_q[DataWidth * ((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1) - (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS) - 1) : ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1)) : 1 - (((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1) - (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS) - 1) : ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1)) - (NUM_WORDS - 1)))+:DataWidth * ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)]; - assign rdata_a_o = rf_reg[raddr_a_i * DataWidth+:DataWidth]; - assign rdata_b_o = rf_reg[raddr_b_i * DataWidth+:DataWidth]; - wire unused_test_en; - assign unused_test_en = test_en_i; -endmodule diff --git a/flow/designs/src/ibex/ibex_register_file_fpga.v b/flow/designs/src/ibex/ibex_register_file_fpga.v deleted file mode 100644 index a249fcfb4e..0000000000 --- a/flow/designs/src/ibex/ibex_register_file_fpga.v +++ /dev/null @@ -1,45 +0,0 @@ -module ibex_register_file_fpga ( - clk_i, - rst_ni, - test_en_i, - dummy_instr_id_i, - raddr_a_i, - rdata_a_o, - raddr_b_i, - rdata_b_o, - waddr_a_i, - wdata_a_i, - we_a_i -); - parameter [0:0] RV32E = 0; - parameter [31:0] DataWidth = 32; - parameter [0:0] DummyInstructions = 0; - input wire clk_i; - input wire rst_ni; - input wire test_en_i; - input wire dummy_instr_id_i; - input wire [4:0] raddr_a_i; - output wire [DataWidth - 1:0] rdata_a_o; - input wire [4:0] raddr_b_i; - output wire [DataWidth - 1:0] rdata_b_o; - input wire [4:0] waddr_a_i; - input wire [DataWidth - 1:0] wdata_a_i; - input wire we_a_i; - localparam signed [31:0] ADDR_WIDTH = (RV32E ? 4 : 5); - localparam signed [31:0] NUM_WORDS = 2 ** ADDR_WIDTH; - reg [DataWidth - 1:0] mem [0:NUM_WORDS - 1]; - wire we; - assign rdata_a_o = (raddr_a_i == {5 {1'sb0}} ? {DataWidth {1'sb0}} : mem[raddr_a_i]); - assign rdata_b_o = (raddr_b_i == {5 {1'sb0}} ? {DataWidth {1'sb0}} : mem[raddr_b_i]); - assign we = (waddr_a_i == {5 {1'sb0}} ? 1'b0 : we_a_i); - always @(posedge clk_i) begin : sync_write - if (we == 1'b1) - mem[waddr_a_i] <= wdata_a_i; - end - wire unused_rst_ni; - assign unused_rst_ni = rst_ni; - wire unused_dummy_instr; - assign unused_dummy_instr = dummy_instr_id_i; - wire unused_test_en; - assign unused_test_en = test_en_i; -endmodule diff --git a/flow/designs/src/ibex/ibex_register_file_latch.v b/flow/designs/src/ibex/ibex_register_file_latch.v deleted file mode 100644 index c9a02bfcb8..0000000000 --- a/flow/designs/src/ibex/ibex_register_file_latch.v +++ /dev/null @@ -1,118 +0,0 @@ -module ibex_register_file_latch ( - clk_i, - rst_ni, - test_en_i, - dummy_instr_id_i, - raddr_a_i, - rdata_a_o, - raddr_b_i, - rdata_b_o, - waddr_a_i, - wdata_a_i, - we_a_i -); - parameter [0:0] RV32E = 0; - parameter [31:0] DataWidth = 32; - parameter [0:0] DummyInstructions = 0; - input wire clk_i; - input wire rst_ni; - input wire test_en_i; - input wire dummy_instr_id_i; - input wire [4:0] raddr_a_i; - output wire [DataWidth - 1:0] rdata_a_o; - input wire [4:0] raddr_b_i; - output wire [DataWidth - 1:0] rdata_b_o; - input wire [4:0] waddr_a_i; - input wire [DataWidth - 1:0] wdata_a_i; - input wire we_a_i; - localparam [31:0] ADDR_WIDTH = (RV32E ? 4 : 5); - localparam [31:0] NUM_WORDS = 2 ** ADDR_WIDTH; - reg [DataWidth - 1:0] mem [0:NUM_WORDS - 1]; - reg [NUM_WORDS - 1:1] waddr_onehot_a; - wire [NUM_WORDS - 1:1] mem_clocks; - reg [DataWidth - 1:0] wdata_a_q; - wire [ADDR_WIDTH - 1:0] raddr_a_int; - wire [ADDR_WIDTH - 1:0] raddr_b_int; - wire [ADDR_WIDTH - 1:0] waddr_a_int; - assign raddr_a_int = raddr_a_i[ADDR_WIDTH - 1:0]; - assign raddr_b_int = raddr_b_i[ADDR_WIDTH - 1:0]; - assign waddr_a_int = waddr_a_i[ADDR_WIDTH - 1:0]; - wire clk_int; - assign rdata_a_o = mem[raddr_a_int]; - assign rdata_b_o = mem[raddr_b_int]; - prim_clock_gating cg_we_global( - .clk_i(clk_i), - .en_i(we_a_i), - .test_en_i(test_en_i), - .clk_o(clk_int) - ); - always @(posedge clk_int or negedge rst_ni) begin : sample_wdata - if (!rst_ni) - wdata_a_q <= {DataWidth {1'sb0}}; - else if (we_a_i) - wdata_a_q <= wdata_a_i; - end - function automatic signed [4:0] sv2v_cast_5_signed; - input reg signed [4:0] inp; - sv2v_cast_5_signed = inp; - endfunction - always @(*) begin : wad - begin : sv2v_autoblock_5 - reg signed [31:0] i; - for (i = 1; i < NUM_WORDS; i = i + 1) - begin : wad_word_iter - if (we_a_i && (waddr_a_int == sv2v_cast_5_signed(i))) - waddr_onehot_a[i] = 1'b1; - else - waddr_onehot_a[i] = 1'b0; - end - end - end - generate - genvar x; - for (x = 1; x < NUM_WORDS; x = x + 1) begin : gen_cg_word_iter - prim_clock_gating cg_i( - .clk_i(clk_int), - .en_i(waddr_onehot_a[x]), - .test_en_i(test_en_i), - .clk_o(mem_clocks[x]) - ); - end - endgenerate - generate - genvar i; - for (i = 1; i < NUM_WORDS; i = i + 1) begin : g_rf_latches - always @(*) - if (mem_clocks[i]) - mem[i] = wdata_a_q; - end - endgenerate - generate - if (DummyInstructions) begin : g_dummy_r0 - wire we_r0_dummy; - wire r0_clock; - reg [DataWidth - 1:0] mem_r0; - assign we_r0_dummy = we_a_i & dummy_instr_id_i; - prim_clock_gating cg_i( - .clk_i(clk_int), - .en_i(we_r0_dummy), - .test_en_i(test_en_i), - .clk_o(r0_clock) - ); - always @(*) begin : latch_wdata - if (r0_clock) - mem_r0 = wdata_a_q; - end - wire [(DataWidth >= DataWidth ? DataWidth : DataWidth):1] sv2v_tmp_22903; - assign sv2v_tmp_22903 = (dummy_instr_id_i ? mem_r0 : {DataWidth {1'sb0}}); - always @(*) mem[0] = sv2v_tmp_22903; - end - else begin : g_normal_r0 - wire unused_dummy_instr_id; - assign unused_dummy_instr_id = dummy_instr_id_i; - wire [DataWidth:1] sv2v_tmp_F0978; - assign sv2v_tmp_F0978 = {DataWidth {1'sb0}}; - always @(*) mem[0] = sv2v_tmp_F0978; - end - endgenerate -endmodule diff --git a/flow/designs/src/ibex/ibex_wb_stage.v b/flow/designs/src/ibex/ibex_wb_stage.v deleted file mode 100644 index f92c4e93cc..0000000000 --- a/flow/designs/src/ibex/ibex_wb_stage.v +++ /dev/null @@ -1,130 +0,0 @@ -module ibex_wb_stage ( - clk_i, - rst_ni, - en_wb_i, - instr_type_wb_i, - pc_id_i, - instr_is_compressed_id_i, - instr_perf_count_id_i, - ready_wb_o, - rf_write_wb_o, - outstanding_load_wb_o, - outstanding_store_wb_o, - pc_wb_o, - perf_instr_ret_wb_o, - perf_instr_ret_compressed_wb_o, - rf_waddr_id_i, - rf_wdata_id_i, - rf_we_id_i, - rf_wdata_lsu_i, - rf_we_lsu_i, - rf_wdata_fwd_wb_o, - rf_waddr_wb_o, - rf_wdata_wb_o, - rf_we_wb_o, - lsu_resp_valid_i, - lsu_resp_err_i, - instr_done_wb_o -); - parameter [0:0] WritebackStage = 1'b0; - input wire clk_i; - input wire rst_ni; - input wire en_wb_i; - input wire [1:0] instr_type_wb_i; - input wire [31:0] pc_id_i; - input wire instr_is_compressed_id_i; - input wire instr_perf_count_id_i; - output wire ready_wb_o; - output wire rf_write_wb_o; - output wire outstanding_load_wb_o; - output wire outstanding_store_wb_o; - output wire [31:0] pc_wb_o; - output wire perf_instr_ret_wb_o; - output wire perf_instr_ret_compressed_wb_o; - input wire [4:0] rf_waddr_id_i; - input wire [31:0] rf_wdata_id_i; - input wire rf_we_id_i; - input wire [31:0] rf_wdata_lsu_i; - input wire rf_we_lsu_i; - output wire [31:0] rf_wdata_fwd_wb_o; - output wire [4:0] rf_waddr_wb_o; - output wire [31:0] rf_wdata_wb_o; - output wire rf_we_wb_o; - input wire lsu_resp_valid_i; - input wire lsu_resp_err_i; - output wire instr_done_wb_o; - wire [31:0] rf_wdata_wb_mux [0:1]; - wire [1:0] rf_wdata_wb_mux_we; - localparam [1:0] ibex_pkg_WB_INSTR_LOAD = 0; - localparam [1:0] ibex_pkg_WB_INSTR_OTHER = 2; - localparam [1:0] ibex_pkg_WB_INSTR_STORE = 1; - generate - if (WritebackStage) begin : g_writeback_stage - reg [31:0] rf_wdata_wb_q; - reg rf_we_wb_q; - reg [4:0] rf_waddr_wb_q; - wire wb_done; - reg wb_valid_q; - reg [31:0] wb_pc_q; - reg wb_compressed_q; - reg wb_count_q; - reg [1:0] wb_instr_type_q; - wire wb_valid_d; - assign wb_valid_d = (en_wb_i & ready_wb_o) | (wb_valid_q & ~wb_done); - assign wb_done = (wb_instr_type_q == ibex_pkg_WB_INSTR_OTHER) | lsu_resp_valid_i; - always @(posedge clk_i or negedge rst_ni) - if (~rst_ni) - wb_valid_q <= 1'b0; - else - wb_valid_q <= wb_valid_d; - always @(posedge clk_i) - if (en_wb_i) begin - rf_we_wb_q <= rf_we_id_i; - rf_waddr_wb_q <= rf_waddr_id_i; - rf_wdata_wb_q <= rf_wdata_id_i; - wb_instr_type_q <= instr_type_wb_i; - wb_pc_q <= pc_id_i; - wb_compressed_q <= instr_is_compressed_id_i; - wb_count_q <= instr_perf_count_id_i; - end - assign rf_waddr_wb_o = rf_waddr_wb_q; - assign rf_wdata_wb_mux[0] = rf_wdata_wb_q; - assign rf_wdata_wb_mux_we[0] = rf_we_wb_q & wb_valid_q; - assign ready_wb_o = ~wb_valid_q | wb_done; - assign rf_write_wb_o = wb_valid_q & (rf_we_wb_q | (wb_instr_type_q == ibex_pkg_WB_INSTR_LOAD)); - assign outstanding_load_wb_o = wb_valid_q & (wb_instr_type_q == ibex_pkg_WB_INSTR_LOAD); - assign outstanding_store_wb_o = wb_valid_q & (wb_instr_type_q == ibex_pkg_WB_INSTR_STORE); - assign pc_wb_o = wb_pc_q; - assign instr_done_wb_o = wb_valid_q & wb_done; - assign perf_instr_ret_wb_o = (instr_done_wb_o & wb_count_q) & ~(lsu_resp_valid_i & lsu_resp_err_i); - assign perf_instr_ret_compressed_wb_o = perf_instr_ret_wb_o & wb_compressed_q; - assign rf_wdata_fwd_wb_o = rf_wdata_wb_q; - end - else begin : g_bypass_wb - assign rf_waddr_wb_o = rf_waddr_id_i; - assign rf_wdata_wb_mux[0] = rf_wdata_id_i; - assign rf_wdata_wb_mux_we[0] = rf_we_id_i; - assign perf_instr_ret_wb_o = (instr_perf_count_id_i & en_wb_i) & ~(lsu_resp_valid_i & lsu_resp_err_i); - assign perf_instr_ret_compressed_wb_o = perf_instr_ret_wb_o & instr_is_compressed_id_i; - assign ready_wb_o = 1'b1; - wire unused_clk; - wire unused_rst; - wire [1:0] unused_instr_type_wb; - wire [31:0] unused_pc_id; - assign unused_clk = clk_i; - assign unused_rst = rst_ni; - assign unused_instr_type_wb = instr_type_wb_i; - assign unused_pc_id = pc_id_i; - assign outstanding_load_wb_o = 1'b0; - assign outstanding_store_wb_o = 1'b0; - assign pc_wb_o = {32 {1'sb0}}; - assign rf_write_wb_o = 1'b0; - assign rf_wdata_fwd_wb_o = 32'b00000000000000000000000000000000; - assign instr_done_wb_o = 1'b0; - end - endgenerate - assign rf_wdata_wb_mux[1] = rf_wdata_lsu_i; - assign rf_wdata_wb_mux_we[1] = rf_we_lsu_i; - assign rf_wdata_wb_o = (rf_wdata_wb_mux_we[0] ? rf_wdata_wb_mux[0] : rf_wdata_wb_mux[1]); - assign rf_we_wb_o = |rf_wdata_wb_mux_we; -endmodule diff --git a/flow/designs/src/ibex/prim_badbit_ram_1p.v b/flow/designs/src/ibex/prim_badbit_ram_1p.v deleted file mode 100644 index 1099bd11eb..0000000000 --- a/flow/designs/src/ibex/prim_badbit_ram_1p.v +++ /dev/null @@ -1,51 +0,0 @@ -module prim_badbit_ram_1p ( - clk_i, - req_i, - write_i, - addr_i, - wdata_i, - wmask_i, - rdata_o -); - parameter signed [31:0] Width = 32; - parameter signed [31:0] Depth = 128; - parameter signed [31:0] DataBitsPerMask = 1; - parameter _sv2v_width_MemInitFile = 1; - parameter [_sv2v_width_MemInitFile - 1:0] MemInitFile = ""; - localparam signed [31:0] Aw = $clog2(Depth); - input wire clk_i; - input wire req_i; - input wire write_i; - input wire [Aw - 1:0] addr_i; - input wire [Width - 1:0] wdata_i; - input wire [Width - 1:0] wmask_i; - output wire [Width - 1:0] rdata_o; - wire [Width - 1:0] sram_rdata; - prim_generic_ram_1p #( - .Width(Width), - .Depth(Depth), - .DataBitsPerMask(DataBitsPerMask), - .MemInitFile(MemInitFile) - ) u_mem( - .clk_i(clk_i), - .req_i(req_i), - .write_i(write_i), - .addr_i(addr_i), - .wdata_i(wdata_i), - .wmask_i(wmask_i), - .rdata_o(sram_rdata) - ); - wire [31:0] width; - assign width = Width; - wire [31:0] addr; - wire [127:0] wdata; - wire [127:0] wmask; - wire [127:0] rdata; - assign addr = {{32 - Aw {1'b0}}, addr_i}; - assign wdata = {{128 - Width {1'b0}}, wdata_i}; - assign wmask = {{128 - Width {1'b0}}, wmask_i}; - assign rdata = {{128 - Width {1'b0}}, sram_rdata}; - wor [127:0] bad_bit_mask; - assign bad_bit_mask = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; - assign rdata_o = sram_rdata ^ bad_bit_mask; -endmodule diff --git a/flow/designs/src/ibex/prim_generic_clock_gating.v b/flow/designs/src/ibex/prim_generic_clock_gating.v deleted file mode 100644 index c88af55ee6..0000000000 --- a/flow/designs/src/ibex/prim_generic_clock_gating.v +++ /dev/null @@ -1,16 +0,0 @@ -module prim_generic_clock_gating ( - clk_i, - en_i, - test_en_i, - clk_o -); - input clk_i; - input en_i; - input test_en_i; - output wire clk_o; - reg en_latch; - always @(*) - if (!clk_i) - en_latch = en_i | test_en_i; - assign clk_o = en_latch & clk_i; -endmodule diff --git a/flow/designs/src/ibex/prim_generic_ram_1p.v b/flow/designs/src/ibex/prim_generic_ram_1p.v deleted file mode 100644 index 3278371897..0000000000 --- a/flow/designs/src/ibex/prim_generic_ram_1p.v +++ /dev/null @@ -1,46 +0,0 @@ -module prim_generic_ram_1p ( - clk_i, - req_i, - write_i, - addr_i, - wdata_i, - wmask_i, - rdata_o -); - parameter signed [31:0] Width = 32; - parameter signed [31:0] Depth = 128; - parameter signed [31:0] DataBitsPerMask = 1; - parameter _sv2v_width_MemInitFile = 1; - parameter [_sv2v_width_MemInitFile - 1:0] MemInitFile = ""; - localparam signed [31:0] Aw = $clog2(Depth); - input wire clk_i; - input wire req_i; - input wire write_i; - input wire [Aw - 1:0] addr_i; - input wire [Width - 1:0] wdata_i; - input wire [Width - 1:0] wmask_i; - output reg [Width - 1:0] rdata_o; - localparam signed [31:0] MaskWidth = Width / DataBitsPerMask; - reg [Width - 1:0] mem [0:Depth - 1]; - wire [MaskWidth - 1:0] wmask; - generate - genvar k; - for (k = 0; k < MaskWidth; k = k + 1) begin : gen_wmask - assign wmask[k] = &wmask_i[k * DataBitsPerMask+:DataBitsPerMask]; - end - endgenerate - always @(posedge clk_i) - if (req_i) - if (write_i) begin : sv2v_autoblock_2 - reg signed [31:0] i; - for (i = 0; i < MaskWidth; i = i + 1) - if (wmask[i]) - mem[addr_i][i * DataBitsPerMask+:DataBitsPerMask] <= wdata_i[i * DataBitsPerMask+:DataBitsPerMask]; - end - else - rdata_o <= mem[addr_i]; - initial if (MemInitFile != "") begin : gen_meminit - $display("Initializing memory %m from file '%s'.", MemInitFile); - $readmemh(MemInitFile, mem); - end -endmodule diff --git a/flow/designs/src/ibex/prim_lfsr.v b/flow/designs/src/ibex/prim_lfsr.v deleted file mode 100644 index c4a5912331..0000000000 --- a/flow/designs/src/ibex/prim_lfsr.v +++ /dev/null @@ -1,88 +0,0 @@ -module prim_lfsr ( - clk_i, - rst_ni, - seed_en_i, - seed_i, - lfsr_en_i, - entropy_i, - state_o -); - parameter _sv2v_width_LfsrType = 56; - parameter [_sv2v_width_LfsrType - 1:0] LfsrType = "GAL_XOR"; - parameter [31:0] LfsrDw = 32; - parameter [31:0] EntropyDw = 8; - parameter [31:0] StateOutDw = 8; - function automatic signed [LfsrDw - 1:0] sv2v_cast_FFBD2_signed; - input reg signed [LfsrDw - 1:0] inp; - sv2v_cast_FFBD2_signed = inp; - endfunction - parameter [LfsrDw - 1:0] DefaultSeed = sv2v_cast_FFBD2_signed(1); - parameter [LfsrDw - 1:0] CustomCoeffs = 1'sb0; - parameter [0:0] MaxLenSVA = 1'b1; - parameter [0:0] LockupSVA = 1'b1; - parameter [0:0] ExtSeedSVA = 1'b1; - input clk_i; - input rst_ni; - input seed_en_i; - input [LfsrDw - 1:0] seed_i; - input lfsr_en_i; - input [EntropyDw - 1:0] entropy_i; - output wire [StateOutDw - 1:0] state_o; - localparam [31:0] GAL_XOR_LUT_OFF = 4; - localparam [3903:0] GAL_XOR_COEFFS = {64'h0000000000000009, 64'h0000000000000012, 64'h0000000000000021, 64'h0000000000000041, 64'h000000000000008e, 64'h0000000000000108, 64'h0000000000000204, 64'h0000000000000402, 64'h0000000000000829, 64'h000000000000100d, 64'h0000000000002015, 64'h0000000000004001, 64'h0000000000008016, 64'h0000000000010004, 64'h0000000000020013, 64'h0000000000040013, 64'h0000000000080004, 64'h0000000000100002, 64'h0000000000200001, 64'h0000000000400010, 64'h000000000080000d, 64'h0000000001000004, 64'h0000000002000023, 64'h0000000004000013, 64'h0000000008000004, 64'h0000000010000002, 64'h0000000020000029, 64'h0000000040000004, 64'h0000000080000057, 64'h0000000100000029, 64'h0000000200000073, 64'h0000000400000002, 64'h000000080000003b, 64'h000000100000001f, 64'h0000002000000031, 64'h0000004000000008, 64'h000000800000001c, 64'h0000010000000004, 64'h000002000000001f, 64'h000004000000002c, 64'h0000080000000032, 64'h000010000000000d, 64'h0000200000000097, 64'h0000400000000010, 64'h000080000000005b, 64'h0001000000000038, 64'h000200000000000e, 64'h0004000000000025, 64'h0008000000000004, 64'h0010000000000023, 64'h002000000000003e, 64'h0040000000000023, 64'h008000000000004a, 64'h0100000000000016, 64'h0200000000000031, 64'h040000000000003d, 64'h0800000000000001, 64'h1000000000000013, 64'h2000000000000034, 64'h4000000000000001, 64'h800000000000000d}; - localparam [31:0] FIB_XNOR_LUT_OFF = 3; - localparam [27887:0] FIB_XNOR_COEFFS = {168'h000000000000000000000000000000000000000006, 168'h00000000000000000000000000000000000000000c, 168'h000000000000000000000000000000000000000014, 168'h000000000000000000000000000000000000000030, 168'h000000000000000000000000000000000000000060, 168'h0000000000000000000000000000000000000000b8, 168'h000000000000000000000000000000000000000110, 168'h000000000000000000000000000000000000000240, 168'h000000000000000000000000000000000000000500, 168'h000000000000000000000000000000000000000829, 168'h00000000000000000000000000000000000000100d, 168'h000000000000000000000000000000000000002015, 168'h000000000000000000000000000000000000006000, 168'h00000000000000000000000000000000000000d008, 168'h000000000000000000000000000000000000012000, 168'h000000000000000000000000000000000000020400, 168'h000000000000000000000000000000000000040023, 168'h000000000000000000000000000000000000090000, 168'h000000000000000000000000000000000000140000, 168'h000000000000000000000000000000000000300000, 168'h000000000000000000000000000000000000420000, 168'h000000000000000000000000000000000000e10000, 168'h000000000000000000000000000000000001200000, 168'h000000000000000000000000000000000002000023, 168'h000000000000000000000000000000000004000013, 168'h000000000000000000000000000000000009000000, 168'h000000000000000000000000000000000014000000, 168'h000000000000000000000000000000000020000029, 168'h000000000000000000000000000000000048000000, 168'h000000000000000000000000000000000080200003, 168'h000000000000000000000000000000000100080000, 168'h000000000000000000000000000000000204000003, 168'h000000000000000000000000000000000500000000, 168'h000000000000000000000000000000000801000000, 168'h00000000000000000000000000000000100000001f, 168'h000000000000000000000000000000002000000031, 168'h000000000000000000000000000000004400000000, 168'h00000000000000000000000000000000a000140000, 168'h000000000000000000000000000000012000000000, 168'h0000000000000000000000000000000300000c0000, 168'h000000000000000000000000000000063000000000, 168'h0000000000000000000000000000000c0000030000, 168'h0000000000000000000000000000001b0000000000, 168'h000000000000000000000000000000300003000000, 168'h000000000000000000000000000000420000000000, 168'h000000000000000000000000000000c00000180000, 168'h000000000000000000000000000001008000000000, 168'h000000000000000000000000000003000000c00000, 168'h000000000000000000000000000006000c00000000, 168'h000000000000000000000000000009000000000000, 168'h000000000000000000000000000018003000000000, 168'h000000000000000000000000000030000000030000, 168'h000000000000000000000000000040000040000000, 168'h0000000000000000000000000000c0000600000000, 168'h000000000000000000000000000102000000000000, 168'h000000000000000000000000000200004000000000, 168'h000000000000000000000000000600003000000000, 168'h000000000000000000000000000c00000000000000, 168'h000000000000000000000000001800300000000000, 168'h000000000000000000000000003000000000000030, 168'h000000000000000000000000006000000000000000, 168'h00000000000000000000000000d800000000000000, 168'h000000000000000000000000010000400000000000, 168'h000000000000000000000000030180000000000000, 168'h000000000000000000000000060300000000000000, 168'h000000000000000000000000080400000000000000, 168'h000000000000000000000000140000028000000000, 168'h000000000000000000000000300060000000000000, 168'h000000000000000000000000410000000000000000, 168'h000000000000000000000000820000000001040000, 168'h000000000000000000000001000000800000000000, 168'h000000000000000000000003000600000000000000, 168'h000000000000000000000006018000000000000000, 168'h00000000000000000000000c000000018000000000, 168'h000000000000000000000018000000600000000000, 168'h000000000000000000000030000600000000000000, 168'h000000000000000000000040200000000000000000, 168'h0000000000000000000000c0000000060000000000, 168'h000000000000000000000110000000000000000000, 168'h000000000000000000000240000000480000000000, 168'h000000000000000000000600000000003000000000, 168'h000000000000000000000800400000000000000000, 168'h000000000000000000001800000300000000000000, 168'h000000000000000000003003000000000000000000, 168'h000000000000000000004002000000000000000000, 168'h00000000000000000000c000000000000000018000, 168'h000000000000000000010000000004000000000000, 168'h000000000000000000030000c00000000000000000, 168'h0000000000000000000600000000000000000000c0, 168'h0000000000000000000c00c0000000000000000000, 168'h000000000000000000140000000000000000000000, 168'h000000000000000000200001000000000000000000, 168'h000000000000000000400800000000000000000000, 168'h000000000000000000a00000000001400000000000, 168'h000000000000000001040000000000000000000000, 168'h000000000000000002004000000000000000000000, 168'h000000000000000005000000000028000000000000, 168'h000000000000000008000000004000000000000000, 168'h000000000000000018600000000000000000000000, 168'h000000000000000030000000000000000c00000000, 168'h000000000000000040200000000000000000000000, 168'h0000000000000000c0300000000000000000000000, 168'h000000000000000100010000000000000000000000, 168'h000000000000000200040000000000000000000000, 168'h0000000000000005000000000000000a0000000000, 168'h000000000000000800000010000000000000000000, 168'h000000000000001860000000000000000000000000, 168'h000000000000003003000000000000000000000000, 168'h000000000000004010000000000000000000000000, 168'h00000000000000a000000000140000000000000000, 168'h000000000000010080000000000000000000000000, 168'h000000000000030000000000000000000180000000, 168'h000000000000060018000000000000000000000000, 168'h0000000000000c0000000000000000300000000000, 168'h000000000000140005000000000000000000000000, 168'h000000000000200000001000000000000000000000, 168'h000000000000404000000000000000000000000000, 168'h000000000000810000000000000000000000000102, 168'h000000000001000040000000000000000000000000, 168'h000000000003000000000000006000000000000000, 168'h000000000005000000000000000000000000000000, 168'h000000000008000000004000000000000000000000, 168'h000000000018000000000000000000000000030000, 168'h000000000030000000030000000000000000000000, 168'h000000000060000000000000000000000000000000, 168'h0000000000a0000014000000000000000000000000, 168'h000000000108000000000000000000000000000000, 168'h000000000240000000000000000000000000000000, 168'h000000000600000000000c00000000000000000000, 168'h000000000800000040000000000000000000000000, 168'h000000001800000000000300000000000000000000, 168'h000000002000000000000010000000000000000000, 168'h000000004008000000000000000000000000000000, 168'h00000000c000000000000000000000000000000600, 168'h000000010000080000000000000000000000000000, 168'h000000030600000000000000000000000000000000, 168'h00000004a400000000000000000000000000000000, 168'h000000080000004000000000000000000000000000, 168'h000000180000003000000000000000000000000000, 168'h000000200001000000000000000000000000000000, 168'h000000600006000000000000000000000000000000, 168'h000000c00000000000000006000000000000000000, 168'h000001000000000000100000000000000000000000, 168'h000003000000000000006000000000000000000000, 168'h000006000000003000000000000000000000000000, 168'h000008000001000000000000000000000000000000, 168'h00001800000000000000000000000000c000000000, 168'h000020000000000001000000000000000000000000, 168'h000048000000000000000000000000000000000000, 168'h0000c0000000000000006000000000000000000000, 168'h000180000000000000000000000000000000000000, 168'h000280000000000000000000000000000005000000, 168'h00060000000c000000000000000000000000000000, 168'h000c00000000000000000000000000018000000000, 168'h001800000600000000000000000000000000000000, 168'h003000000c00000000000000000000000000000000, 168'h004000000080000000000000000000000000000000, 168'h00c000300000000000000000000000000000000000, 168'h010000400000000000000000000000000000000000, 168'h030000000000000000000006000000000000000000, 168'h0600000000000000c0000000000000000000000000, 168'h0c0060000000000000000000000000000000000000, 168'h180000006000000000000000000000000000000000, 168'h3000000000c0000000000000000000000000000000, 168'h410000000000000000000000000000000000000000, 168'ha00140000000000000000000000000000000000000}; - wire lockup; - wire [LfsrDw - 1:0] lfsr_d; - reg [LfsrDw - 1:0] lfsr_q; - wire [LfsrDw - 1:0] next_lfsr_state; - wire [LfsrDw - 1:0] coeffs; - generate - function automatic [63:0] sv2v_cast_64; - input reg [63:0] inp; - sv2v_cast_64 = inp; - endfunction - if (sv2v_cast_64(LfsrType) == sv2v_cast_64("GAL_XOR")) begin : gen_gal_xor - if (CustomCoeffs > 0) begin : gen_custom - assign coeffs = CustomCoeffs[LfsrDw - 1:0]; - end - else begin : gen_lut - assign coeffs = GAL_XOR_COEFFS[((60 - (LfsrDw - GAL_XOR_LUT_OFF)) * 64) + (LfsrDw - 1)-:LfsrDw]; - end - function automatic [LfsrDw - 1:0] sv2v_cast_FFBD2; - input reg [LfsrDw - 1:0] inp; - sv2v_cast_FFBD2 = inp; - endfunction - assign next_lfsr_state = (sv2v_cast_FFBD2(entropy_i) ^ ({LfsrDw {lfsr_q[0]}} & coeffs)) ^ (lfsr_q >> 1); - assign lockup = ~(|lfsr_q); - end - else begin - function automatic [63:0] sv2v_cast_64; - input reg [63:0] inp; - sv2v_cast_64 = inp; - endfunction - if (sv2v_cast_64(LfsrType) == "FIB_XNOR") begin : gen_fib_xnor - if (CustomCoeffs > 0) begin : gen_custom - assign coeffs = CustomCoeffs[LfsrDw - 1:0]; - end - else begin : gen_lut - assign coeffs = FIB_XNOR_COEFFS[((165 - (LfsrDw - FIB_XNOR_LUT_OFF)) * 168) + (LfsrDw - 1)-:LfsrDw]; - end - function automatic [LfsrDw - 1:0] sv2v_cast_FFBD2; - input reg [LfsrDw - 1:0] inp; - sv2v_cast_FFBD2 = inp; - endfunction - assign next_lfsr_state = sv2v_cast_FFBD2(entropy_i) ^ {lfsr_q[LfsrDw - 2:0], ~(^(lfsr_q & coeffs))}; - assign lockup = &lfsr_q; - end - end - endgenerate - assign lfsr_d = (seed_en_i ? seed_i : (lfsr_en_i && lockup ? DefaultSeed : (lfsr_en_i ? next_lfsr_state : lfsr_q))); - assign state_o = lfsr_q[StateOutDw - 1:0]; - always @(posedge clk_i or negedge rst_ni) begin : p_reg - if (!rst_ni) - lfsr_q <= DefaultSeed; - else - lfsr_q <= lfsr_d; - end -endmodule diff --git a/flow/designs/src/ibex/prim_ram_1p.v b/flow/designs/src/ibex/prim_ram_1p.v deleted file mode 100644 index 93f789f42a..0000000000 --- a/flow/designs/src/ibex/prim_ram_1p.v +++ /dev/null @@ -1,44 +0,0 @@ -module prim_ram_1p ( - clk_i, - req_i, - write_i, - addr_i, - wdata_i, - wmask_i, - rdata_o -); - parameter signed [31:0] Width = 32; - parameter signed [31:0] Depth = 128; - parameter signed [31:0] DataBitsPerMask = 1; - parameter _sv2v_width_MemInitFile = 1; - parameter [_sv2v_width_MemInitFile - 1:0] MemInitFile = ""; - localparam signed [31:0] Aw = $clog2(Depth); - input wire clk_i; - input wire req_i; - input wire write_i; - input wire [Aw - 1:0] addr_i; - input wire [Width - 1:0] wdata_i; - input wire [Width - 1:0] wmask_i; - output wire [Width - 1:0] rdata_o; - localparam integer prim_pkg_ImplGeneric = 0; - parameter integer Impl = prim_pkg_ImplGeneric; - localparam integer prim_pkg_ImplBadbit = 2; - generate - if (Impl == prim_pkg_ImplBadbit) begin : gen_badbit - prim_badbit_ram_1p #( - .Depth(Depth), - .Width(Width), - .MemInitFile(MemInitFile), - .DataBitsPerMask(DataBitsPerMask) - ) u_impl_badbit(.*); - end - else begin : gen_generic - prim_generic_ram_1p #( - .Depth(Depth), - .Width(Width), - .MemInitFile(MemInitFile), - .DataBitsPerMask(DataBitsPerMask) - ) u_impl_generic(.*); - end - endgenerate -endmodule diff --git a/flow/designs/src/ibex/prim_secded_28_22_dec.v b/flow/designs/src/ibex/prim_secded_28_22_dec.v deleted file mode 100644 index 40753d1e8b..0000000000 --- a/flow/designs/src/ibex/prim_secded_28_22_dec.v +++ /dev/null @@ -1,43 +0,0 @@ -module prim_secded_28_22_dec ( - in, - d_o, - syndrome_o, - err_o -); - input [27:0] in; - output wire [21:0] d_o; - output wire [5:0] syndrome_o; - output wire [1:0] err_o; - wire single_error; - assign syndrome_o[0] = (((((((((((in[22] ^ in[0]) ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[6]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[20]) ^ in[21]; - assign syndrome_o[1] = (((((((((((in[23] ^ in[0]) ^ in[1]) ^ in[2]) ^ in[3]) ^ in[10]) ^ in[11]) ^ in[12]) ^ in[13]) ^ in[14]) ^ in[15]) ^ in[20]) ^ in[21]; - assign syndrome_o[2] = ((((((((((in[24] ^ in[0]) ^ in[4]) ^ in[5]) ^ in[6]) ^ in[10]) ^ in[11]) ^ in[12]) ^ in[16]) ^ in[17]) ^ in[18]) ^ in[20]; - assign syndrome_o[3] = ((((((((((in[25] ^ in[1]) ^ in[4]) ^ in[7]) ^ in[8]) ^ in[10]) ^ in[13]) ^ in[14]) ^ in[16]) ^ in[17]) ^ in[19]) ^ in[21]; - assign syndrome_o[4] = (((((((((((in[26] ^ in[2]) ^ in[5]) ^ in[7]) ^ in[9]) ^ in[11]) ^ in[13]) ^ in[15]) ^ in[16]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[21]; - assign syndrome_o[5] = (((((((((((in[27] ^ in[3]) ^ in[6]) ^ in[8]) ^ in[9]) ^ in[12]) ^ in[14]) ^ in[15]) ^ in[17]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[21]; - assign d_o[0] = (syndrome_o == 6'h07) ^ in[0]; - assign d_o[1] = (syndrome_o == 6'h0b) ^ in[1]; - assign d_o[2] = (syndrome_o == 6'h13) ^ in[2]; - assign d_o[3] = (syndrome_o == 6'h23) ^ in[3]; - assign d_o[4] = (syndrome_o == 6'h0d) ^ in[4]; - assign d_o[5] = (syndrome_o == 6'h15) ^ in[5]; - assign d_o[6] = (syndrome_o == 6'h25) ^ in[6]; - assign d_o[7] = (syndrome_o == 6'h19) ^ in[7]; - assign d_o[8] = (syndrome_o == 6'h29) ^ in[8]; - assign d_o[9] = (syndrome_o == 6'h31) ^ in[9]; - assign d_o[10] = (syndrome_o == 6'h0e) ^ in[10]; - assign d_o[11] = (syndrome_o == 6'h16) ^ in[11]; - assign d_o[12] = (syndrome_o == 6'h26) ^ in[12]; - assign d_o[13] = (syndrome_o == 6'h1a) ^ in[13]; - assign d_o[14] = (syndrome_o == 6'h2a) ^ in[14]; - assign d_o[15] = (syndrome_o == 6'h32) ^ in[15]; - assign d_o[16] = (syndrome_o == 6'h1c) ^ in[16]; - assign d_o[17] = (syndrome_o == 6'h2c) ^ in[17]; - assign d_o[18] = (syndrome_o == 6'h34) ^ in[18]; - assign d_o[19] = (syndrome_o == 6'h38) ^ in[19]; - assign d_o[20] = (syndrome_o == 6'h37) ^ in[20]; - assign d_o[21] = (syndrome_o == 6'h3b) ^ in[21]; - assign single_error = ^syndrome_o; - assign err_o[0] = single_error; - assign err_o[1] = ~single_error & |syndrome_o; -endmodule diff --git a/flow/designs/src/ibex/prim_secded_28_22_enc.v b/flow/designs/src/ibex/prim_secded_28_22_enc.v deleted file mode 100644 index 45069c8973..0000000000 --- a/flow/designs/src/ibex/prim_secded_28_22_enc.v +++ /dev/null @@ -1,35 +0,0 @@ -module prim_secded_28_22_enc ( - in, - out -); - input [21:0] in; - output wire [27:0] out; - assign out[0] = in[0]; - assign out[1] = in[1]; - assign out[2] = in[2]; - assign out[3] = in[3]; - assign out[4] = in[4]; - assign out[5] = in[5]; - assign out[6] = in[6]; - assign out[7] = in[7]; - assign out[8] = in[8]; - assign out[9] = in[9]; - assign out[10] = in[10]; - assign out[11] = in[11]; - assign out[12] = in[12]; - assign out[13] = in[13]; - assign out[14] = in[14]; - assign out[15] = in[15]; - assign out[16] = in[16]; - assign out[17] = in[17]; - assign out[18] = in[18]; - assign out[19] = in[19]; - assign out[20] = in[20]; - assign out[21] = in[21]; - assign out[22] = ((((((((((in[0] ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[6]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[20]) ^ in[21]; - assign out[23] = ((((((((((in[0] ^ in[1]) ^ in[2]) ^ in[3]) ^ in[10]) ^ in[11]) ^ in[12]) ^ in[13]) ^ in[14]) ^ in[15]) ^ in[20]) ^ in[21]; - assign out[24] = (((((((((in[0] ^ in[4]) ^ in[5]) ^ in[6]) ^ in[10]) ^ in[11]) ^ in[12]) ^ in[16]) ^ in[17]) ^ in[18]) ^ in[20]; - assign out[25] = (((((((((in[1] ^ in[4]) ^ in[7]) ^ in[8]) ^ in[10]) ^ in[13]) ^ in[14]) ^ in[16]) ^ in[17]) ^ in[19]) ^ in[21]; - assign out[26] = ((((((((((in[2] ^ in[5]) ^ in[7]) ^ in[9]) ^ in[11]) ^ in[13]) ^ in[15]) ^ in[16]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[21]; - assign out[27] = ((((((((((in[3] ^ in[6]) ^ in[8]) ^ in[9]) ^ in[12]) ^ in[14]) ^ in[15]) ^ in[17]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[21]; -endmodule diff --git a/flow/designs/src/ibex/prim_secded_39_32_dec.v b/flow/designs/src/ibex/prim_secded_39_32_dec.v deleted file mode 100644 index e4f90ca0eb..0000000000 --- a/flow/designs/src/ibex/prim_secded_39_32_dec.v +++ /dev/null @@ -1,54 +0,0 @@ -module prim_secded_39_32_dec ( - in, - d_o, - syndrome_o, - err_o -); - input [38:0] in; - output wire [31:0] d_o; - output wire [6:0] syndrome_o; - output wire [1:0] err_o; - wire single_error; - assign syndrome_o[0] = ((((((((((((in[32] ^ in[2]) ^ in[3]) ^ in[7]) ^ in[8]) ^ in[14]) ^ in[15]) ^ in[16]) ^ in[18]) ^ in[19]) ^ in[23]) ^ in[24]) ^ in[28]) ^ in[29]; - assign syndrome_o[1] = (((((((((((((in[33] ^ in[3]) ^ in[6]) ^ in[8]) ^ in[12]) ^ in[13]) ^ in[15]) ^ in[17]) ^ in[19]) ^ in[21]) ^ in[25]) ^ in[27]) ^ in[29]) ^ in[30]) ^ in[31]; - assign syndrome_o[2] = (((((((((((((in[34] ^ in[0]) ^ in[5]) ^ in[7]) ^ in[9]) ^ in[10]) ^ in[12]) ^ in[13]) ^ in[15]) ^ in[16]) ^ in[22]) ^ in[23]) ^ in[26]) ^ in[27]) ^ in[31]; - assign syndrome_o[3] = (((((((((((((in[35] ^ in[0]) ^ in[1]) ^ in[4]) ^ in[6]) ^ in[9]) ^ in[11]) ^ in[12]) ^ in[14]) ^ in[22]) ^ in[23]) ^ in[25]) ^ in[28]) ^ in[29]) ^ in[30]; - assign syndrome_o[4] = (((((((((((in[36] ^ in[0]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[11]) ^ in[17]) ^ in[20]) ^ in[24]) ^ in[26]) ^ in[27]) ^ in[30]; - assign syndrome_o[5] = (((((((((((((in[37] ^ in[1]) ^ in[2]) ^ in[4]) ^ in[6]) ^ in[10]) ^ in[13]) ^ in[14]) ^ in[16]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[21]) ^ in[22]) ^ in[26]; - assign syndrome_o[6] = ((((((((((((((in[38] ^ in[1]) ^ in[5]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[10]) ^ in[11]) ^ in[17]) ^ in[18]) ^ in[20]) ^ in[21]) ^ in[24]) ^ in[25]) ^ in[28]) ^ in[31]; - assign d_o[0] = (syndrome_o == 7'h1c) ^ in[0]; - assign d_o[1] = (syndrome_o == 7'h68) ^ in[1]; - assign d_o[2] = (syndrome_o == 7'h31) ^ in[2]; - assign d_o[3] = (syndrome_o == 7'h13) ^ in[3]; - assign d_o[4] = (syndrome_o == 7'h38) ^ in[4]; - assign d_o[5] = (syndrome_o == 7'h54) ^ in[5]; - assign d_o[6] = (syndrome_o == 7'h2a) ^ in[6]; - assign d_o[7] = (syndrome_o == 7'h45) ^ in[7]; - assign d_o[8] = (syndrome_o == 7'h43) ^ in[8]; - assign d_o[9] = (syndrome_o == 7'h4c) ^ in[9]; - assign d_o[10] = (syndrome_o == 7'h64) ^ in[10]; - assign d_o[11] = (syndrome_o == 7'h58) ^ in[11]; - assign d_o[12] = (syndrome_o == 7'h0e) ^ in[12]; - assign d_o[13] = (syndrome_o == 7'h26) ^ in[13]; - assign d_o[14] = (syndrome_o == 7'h29) ^ in[14]; - assign d_o[15] = (syndrome_o == 7'h07) ^ in[15]; - assign d_o[16] = (syndrome_o == 7'h25) ^ in[16]; - assign d_o[17] = (syndrome_o == 7'h52) ^ in[17]; - assign d_o[18] = (syndrome_o == 7'h61) ^ in[18]; - assign d_o[19] = (syndrome_o == 7'h23) ^ in[19]; - assign d_o[20] = (syndrome_o == 7'h70) ^ in[20]; - assign d_o[21] = (syndrome_o == 7'h62) ^ in[21]; - assign d_o[22] = (syndrome_o == 7'h2c) ^ in[22]; - assign d_o[23] = (syndrome_o == 7'h0d) ^ in[23]; - assign d_o[24] = (syndrome_o == 7'h51) ^ in[24]; - assign d_o[25] = (syndrome_o == 7'h4a) ^ in[25]; - assign d_o[26] = (syndrome_o == 7'h34) ^ in[26]; - assign d_o[27] = (syndrome_o == 7'h16) ^ in[27]; - assign d_o[28] = (syndrome_o == 7'h49) ^ in[28]; - assign d_o[29] = (syndrome_o == 7'h0b) ^ in[29]; - assign d_o[30] = (syndrome_o == 7'h1a) ^ in[30]; - assign d_o[31] = (syndrome_o == 7'h46) ^ in[31]; - assign single_error = ^syndrome_o; - assign err_o[0] = single_error; - assign err_o[1] = ~single_error & |syndrome_o; -endmodule diff --git a/flow/designs/src/ibex/prim_secded_39_32_enc.v b/flow/designs/src/ibex/prim_secded_39_32_enc.v deleted file mode 100644 index c8bcadafcb..0000000000 --- a/flow/designs/src/ibex/prim_secded_39_32_enc.v +++ /dev/null @@ -1,46 +0,0 @@ -module prim_secded_39_32_enc ( - in, - out -); - input [31:0] in; - output wire [38:0] out; - assign out[0] = in[0]; - assign out[1] = in[1]; - assign out[2] = in[2]; - assign out[3] = in[3]; - assign out[4] = in[4]; - assign out[5] = in[5]; - assign out[6] = in[6]; - assign out[7] = in[7]; - assign out[8] = in[8]; - assign out[9] = in[9]; - assign out[10] = in[10]; - assign out[11] = in[11]; - assign out[12] = in[12]; - assign out[13] = in[13]; - assign out[14] = in[14]; - assign out[15] = in[15]; - assign out[16] = in[16]; - assign out[17] = in[17]; - assign out[18] = in[18]; - assign out[19] = in[19]; - assign out[20] = in[20]; - assign out[21] = in[21]; - assign out[22] = in[22]; - assign out[23] = in[23]; - assign out[24] = in[24]; - assign out[25] = in[25]; - assign out[26] = in[26]; - assign out[27] = in[27]; - assign out[28] = in[28]; - assign out[29] = in[29]; - assign out[30] = in[30]; - assign out[31] = in[31]; - assign out[32] = (((((((((((in[2] ^ in[3]) ^ in[7]) ^ in[8]) ^ in[14]) ^ in[15]) ^ in[16]) ^ in[18]) ^ in[19]) ^ in[23]) ^ in[24]) ^ in[28]) ^ in[29]; - assign out[33] = ((((((((((((in[3] ^ in[6]) ^ in[8]) ^ in[12]) ^ in[13]) ^ in[15]) ^ in[17]) ^ in[19]) ^ in[21]) ^ in[25]) ^ in[27]) ^ in[29]) ^ in[30]) ^ in[31]; - assign out[34] = ((((((((((((in[0] ^ in[5]) ^ in[7]) ^ in[9]) ^ in[10]) ^ in[12]) ^ in[13]) ^ in[15]) ^ in[16]) ^ in[22]) ^ in[23]) ^ in[26]) ^ in[27]) ^ in[31]; - assign out[35] = ((((((((((((in[0] ^ in[1]) ^ in[4]) ^ in[6]) ^ in[9]) ^ in[11]) ^ in[12]) ^ in[14]) ^ in[22]) ^ in[23]) ^ in[25]) ^ in[28]) ^ in[29]) ^ in[30]; - assign out[36] = ((((((((((in[0] ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[11]) ^ in[17]) ^ in[20]) ^ in[24]) ^ in[26]) ^ in[27]) ^ in[30]; - assign out[37] = ((((((((((((in[1] ^ in[2]) ^ in[4]) ^ in[6]) ^ in[10]) ^ in[13]) ^ in[14]) ^ in[16]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[21]) ^ in[22]) ^ in[26]; - assign out[38] = (((((((((((((in[1] ^ in[5]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[10]) ^ in[11]) ^ in[17]) ^ in[18]) ^ in[20]) ^ in[21]) ^ in[24]) ^ in[25]) ^ in[28]) ^ in[31]; -endmodule diff --git a/flow/designs/src/ibex/prim_secded_72_64_dec.v b/flow/designs/src/ibex/prim_secded_72_64_dec.v deleted file mode 100644 index ccd34844a2..0000000000 --- a/flow/designs/src/ibex/prim_secded_72_64_dec.v +++ /dev/null @@ -1,87 +0,0 @@ -module prim_secded_72_64_dec ( - in, - d_o, - syndrome_o, - err_o -); - input [71:0] in; - output wire [63:0] d_o; - output wire [7:0] syndrome_o; - output wire [1:0] err_o; - wire single_error; - assign syndrome_o[0] = (((((((((((((((((((((((((in[64] ^ in[0]) ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[6]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[10]) ^ in[11]) ^ in[12]) ^ in[13]) ^ in[14]) ^ in[15]) ^ in[16]) ^ in[17]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[57]) ^ in[58]) ^ in[61]) ^ in[62]) ^ in[63]; - assign syndrome_o[1] = (((((((((((((((((((((((((in[65] ^ in[0]) ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[21]) ^ in[22]) ^ in[23]) ^ in[24]) ^ in[25]) ^ in[26]) ^ in[27]) ^ in[28]) ^ in[29]) ^ in[30]) ^ in[31]) ^ in[32]) ^ in[33]) ^ in[34]) ^ in[35]) ^ in[58]) ^ in[59]) ^ in[60]) ^ in[62]) ^ in[63]; - assign syndrome_o[2] = (((((((((((((((((((((((((in[66] ^ in[0]) ^ in[6]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[10]) ^ in[21]) ^ in[22]) ^ in[23]) ^ in[24]) ^ in[25]) ^ in[36]) ^ in[37]) ^ in[38]) ^ in[39]) ^ in[40]) ^ in[41]) ^ in[42]) ^ in[43]) ^ in[44]) ^ in[45]) ^ in[56]) ^ in[57]) ^ in[59]) ^ in[60]) ^ in[63]; - assign syndrome_o[3] = (((((((((((((((((((((((((in[67] ^ in[1]) ^ in[6]) ^ in[11]) ^ in[12]) ^ in[13]) ^ in[14]) ^ in[21]) ^ in[26]) ^ in[27]) ^ in[28]) ^ in[29]) ^ in[36]) ^ in[37]) ^ in[38]) ^ in[39]) ^ in[46]) ^ in[47]) ^ in[48]) ^ in[49]) ^ in[50]) ^ in[51]) ^ in[56]) ^ in[57]) ^ in[58]) ^ in[61]) ^ in[63]; - assign syndrome_o[4] = (((((((((((((((((((((((((in[68] ^ in[2]) ^ in[7]) ^ in[11]) ^ in[15]) ^ in[16]) ^ in[17]) ^ in[22]) ^ in[26]) ^ in[30]) ^ in[31]) ^ in[32]) ^ in[36]) ^ in[40]) ^ in[41]) ^ in[42]) ^ in[46]) ^ in[47]) ^ in[48]) ^ in[52]) ^ in[53]) ^ in[54]) ^ in[56]) ^ in[58]) ^ in[59]) ^ in[61]) ^ in[62]; - assign syndrome_o[5] = (((((((((((((((((((((((((in[69] ^ in[3]) ^ in[8]) ^ in[12]) ^ in[15]) ^ in[18]) ^ in[19]) ^ in[23]) ^ in[27]) ^ in[30]) ^ in[33]) ^ in[34]) ^ in[37]) ^ in[40]) ^ in[43]) ^ in[44]) ^ in[46]) ^ in[49]) ^ in[50]) ^ in[52]) ^ in[53]) ^ in[55]) ^ in[56]) ^ in[57]) ^ in[59]) ^ in[60]) ^ in[61]; - assign syndrome_o[6] = (((((((((((((((((((((((((in[70] ^ in[4]) ^ in[9]) ^ in[13]) ^ in[16]) ^ in[18]) ^ in[20]) ^ in[24]) ^ in[28]) ^ in[31]) ^ in[33]) ^ in[35]) ^ in[38]) ^ in[41]) ^ in[43]) ^ in[45]) ^ in[47]) ^ in[49]) ^ in[51]) ^ in[52]) ^ in[54]) ^ in[55]) ^ in[56]) ^ in[59]) ^ in[60]) ^ in[61]) ^ in[62]; - assign syndrome_o[7] = (((((((((((((((((((((((((in[71] ^ in[5]) ^ in[10]) ^ in[14]) ^ in[17]) ^ in[19]) ^ in[20]) ^ in[25]) ^ in[29]) ^ in[32]) ^ in[34]) ^ in[35]) ^ in[39]) ^ in[42]) ^ in[44]) ^ in[45]) ^ in[48]) ^ in[50]) ^ in[51]) ^ in[53]) ^ in[54]) ^ in[55]) ^ in[57]) ^ in[58]) ^ in[60]) ^ in[62]) ^ in[63]; - assign d_o[0] = (syndrome_o == 8'h07) ^ in[0]; - assign d_o[1] = (syndrome_o == 8'h0b) ^ in[1]; - assign d_o[2] = (syndrome_o == 8'h13) ^ in[2]; - assign d_o[3] = (syndrome_o == 8'h23) ^ in[3]; - assign d_o[4] = (syndrome_o == 8'h43) ^ in[4]; - assign d_o[5] = (syndrome_o == 8'h83) ^ in[5]; - assign d_o[6] = (syndrome_o == 8'h0d) ^ in[6]; - assign d_o[7] = (syndrome_o == 8'h15) ^ in[7]; - assign d_o[8] = (syndrome_o == 8'h25) ^ in[8]; - assign d_o[9] = (syndrome_o == 8'h45) ^ in[9]; - assign d_o[10] = (syndrome_o == 8'h85) ^ in[10]; - assign d_o[11] = (syndrome_o == 8'h19) ^ in[11]; - assign d_o[12] = (syndrome_o == 8'h29) ^ in[12]; - assign d_o[13] = (syndrome_o == 8'h49) ^ in[13]; - assign d_o[14] = (syndrome_o == 8'h89) ^ in[14]; - assign d_o[15] = (syndrome_o == 8'h31) ^ in[15]; - assign d_o[16] = (syndrome_o == 8'h51) ^ in[16]; - assign d_o[17] = (syndrome_o == 8'h91) ^ in[17]; - assign d_o[18] = (syndrome_o == 8'h61) ^ in[18]; - assign d_o[19] = (syndrome_o == 8'ha1) ^ in[19]; - assign d_o[20] = (syndrome_o == 8'hc1) ^ in[20]; - assign d_o[21] = (syndrome_o == 8'h0e) ^ in[21]; - assign d_o[22] = (syndrome_o == 8'h16) ^ in[22]; - assign d_o[23] = (syndrome_o == 8'h26) ^ in[23]; - assign d_o[24] = (syndrome_o == 8'h46) ^ in[24]; - assign d_o[25] = (syndrome_o == 8'h86) ^ in[25]; - assign d_o[26] = (syndrome_o == 8'h1a) ^ in[26]; - assign d_o[27] = (syndrome_o == 8'h2a) ^ in[27]; - assign d_o[28] = (syndrome_o == 8'h4a) ^ in[28]; - assign d_o[29] = (syndrome_o == 8'h8a) ^ in[29]; - assign d_o[30] = (syndrome_o == 8'h32) ^ in[30]; - assign d_o[31] = (syndrome_o == 8'h52) ^ in[31]; - assign d_o[32] = (syndrome_o == 8'h92) ^ in[32]; - assign d_o[33] = (syndrome_o == 8'h62) ^ in[33]; - assign d_o[34] = (syndrome_o == 8'ha2) ^ in[34]; - assign d_o[35] = (syndrome_o == 8'hc2) ^ in[35]; - assign d_o[36] = (syndrome_o == 8'h1c) ^ in[36]; - assign d_o[37] = (syndrome_o == 8'h2c) ^ in[37]; - assign d_o[38] = (syndrome_o == 8'h4c) ^ in[38]; - assign d_o[39] = (syndrome_o == 8'h8c) ^ in[39]; - assign d_o[40] = (syndrome_o == 8'h34) ^ in[40]; - assign d_o[41] = (syndrome_o == 8'h54) ^ in[41]; - assign d_o[42] = (syndrome_o == 8'h94) ^ in[42]; - assign d_o[43] = (syndrome_o == 8'h64) ^ in[43]; - assign d_o[44] = (syndrome_o == 8'ha4) ^ in[44]; - assign d_o[45] = (syndrome_o == 8'hc4) ^ in[45]; - assign d_o[46] = (syndrome_o == 8'h38) ^ in[46]; - assign d_o[47] = (syndrome_o == 8'h58) ^ in[47]; - assign d_o[48] = (syndrome_o == 8'h98) ^ in[48]; - assign d_o[49] = (syndrome_o == 8'h68) ^ in[49]; - assign d_o[50] = (syndrome_o == 8'ha8) ^ in[50]; - assign d_o[51] = (syndrome_o == 8'hc8) ^ in[51]; - assign d_o[52] = (syndrome_o == 8'h70) ^ in[52]; - assign d_o[53] = (syndrome_o == 8'hb0) ^ in[53]; - assign d_o[54] = (syndrome_o == 8'hd0) ^ in[54]; - assign d_o[55] = (syndrome_o == 8'he0) ^ in[55]; - assign d_o[56] = (syndrome_o == 8'h7c) ^ in[56]; - assign d_o[57] = (syndrome_o == 8'had) ^ in[57]; - assign d_o[58] = (syndrome_o == 8'h9b) ^ in[58]; - assign d_o[59] = (syndrome_o == 8'h76) ^ in[59]; - assign d_o[60] = (syndrome_o == 8'he6) ^ in[60]; - assign d_o[61] = (syndrome_o == 8'h79) ^ in[61]; - assign d_o[62] = (syndrome_o == 8'hd3) ^ in[62]; - assign d_o[63] = (syndrome_o == 8'h8f) ^ in[63]; - assign single_error = ^syndrome_o; - assign err_o[0] = single_error; - assign err_o[1] = ~single_error & |syndrome_o; -endmodule diff --git a/flow/designs/src/ibex/prim_secded_72_64_enc.v b/flow/designs/src/ibex/prim_secded_72_64_enc.v deleted file mode 100644 index e2003508f7..0000000000 --- a/flow/designs/src/ibex/prim_secded_72_64_enc.v +++ /dev/null @@ -1,79 +0,0 @@ -module prim_secded_72_64_enc ( - in, - out -); - input [63:0] in; - output wire [71:0] out; - assign out[0] = in[0]; - assign out[1] = in[1]; - assign out[2] = in[2]; - assign out[3] = in[3]; - assign out[4] = in[4]; - assign out[5] = in[5]; - assign out[6] = in[6]; - assign out[7] = in[7]; - assign out[8] = in[8]; - assign out[9] = in[9]; - assign out[10] = in[10]; - assign out[11] = in[11]; - assign out[12] = in[12]; - assign out[13] = in[13]; - assign out[14] = in[14]; - assign out[15] = in[15]; - assign out[16] = in[16]; - assign out[17] = in[17]; - assign out[18] = in[18]; - assign out[19] = in[19]; - assign out[20] = in[20]; - assign out[21] = in[21]; - assign out[22] = in[22]; - assign out[23] = in[23]; - assign out[24] = in[24]; - assign out[25] = in[25]; - assign out[26] = in[26]; - assign out[27] = in[27]; - assign out[28] = in[28]; - assign out[29] = in[29]; - assign out[30] = in[30]; - assign out[31] = in[31]; - assign out[32] = in[32]; - assign out[33] = in[33]; - assign out[34] = in[34]; - assign out[35] = in[35]; - assign out[36] = in[36]; - assign out[37] = in[37]; - assign out[38] = in[38]; - assign out[39] = in[39]; - assign out[40] = in[40]; - assign out[41] = in[41]; - assign out[42] = in[42]; - assign out[43] = in[43]; - assign out[44] = in[44]; - assign out[45] = in[45]; - assign out[46] = in[46]; - assign out[47] = in[47]; - assign out[48] = in[48]; - assign out[49] = in[49]; - assign out[50] = in[50]; - assign out[51] = in[51]; - assign out[52] = in[52]; - assign out[53] = in[53]; - assign out[54] = in[54]; - assign out[55] = in[55]; - assign out[56] = in[56]; - assign out[57] = in[57]; - assign out[58] = in[58]; - assign out[59] = in[59]; - assign out[60] = in[60]; - assign out[61] = in[61]; - assign out[62] = in[62]; - assign out[63] = in[63]; - assign out[64] = ((((((((((((((((((((((((in[0] ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[6]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[10]) ^ in[11]) ^ in[12]) ^ in[13]) ^ in[14]) ^ in[15]) ^ in[16]) ^ in[17]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[57]) ^ in[58]) ^ in[61]) ^ in[62]) ^ in[63]; - assign out[65] = ((((((((((((((((((((((((in[0] ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[21]) ^ in[22]) ^ in[23]) ^ in[24]) ^ in[25]) ^ in[26]) ^ in[27]) ^ in[28]) ^ in[29]) ^ in[30]) ^ in[31]) ^ in[32]) ^ in[33]) ^ in[34]) ^ in[35]) ^ in[58]) ^ in[59]) ^ in[60]) ^ in[62]) ^ in[63]; - assign out[66] = ((((((((((((((((((((((((in[0] ^ in[6]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[10]) ^ in[21]) ^ in[22]) ^ in[23]) ^ in[24]) ^ in[25]) ^ in[36]) ^ in[37]) ^ in[38]) ^ in[39]) ^ in[40]) ^ in[41]) ^ in[42]) ^ in[43]) ^ in[44]) ^ in[45]) ^ in[56]) ^ in[57]) ^ in[59]) ^ in[60]) ^ in[63]; - assign out[67] = ((((((((((((((((((((((((in[1] ^ in[6]) ^ in[11]) ^ in[12]) ^ in[13]) ^ in[14]) ^ in[21]) ^ in[26]) ^ in[27]) ^ in[28]) ^ in[29]) ^ in[36]) ^ in[37]) ^ in[38]) ^ in[39]) ^ in[46]) ^ in[47]) ^ in[48]) ^ in[49]) ^ in[50]) ^ in[51]) ^ in[56]) ^ in[57]) ^ in[58]) ^ in[61]) ^ in[63]; - assign out[68] = ((((((((((((((((((((((((in[2] ^ in[7]) ^ in[11]) ^ in[15]) ^ in[16]) ^ in[17]) ^ in[22]) ^ in[26]) ^ in[30]) ^ in[31]) ^ in[32]) ^ in[36]) ^ in[40]) ^ in[41]) ^ in[42]) ^ in[46]) ^ in[47]) ^ in[48]) ^ in[52]) ^ in[53]) ^ in[54]) ^ in[56]) ^ in[58]) ^ in[59]) ^ in[61]) ^ in[62]; - assign out[69] = ((((((((((((((((((((((((in[3] ^ in[8]) ^ in[12]) ^ in[15]) ^ in[18]) ^ in[19]) ^ in[23]) ^ in[27]) ^ in[30]) ^ in[33]) ^ in[34]) ^ in[37]) ^ in[40]) ^ in[43]) ^ in[44]) ^ in[46]) ^ in[49]) ^ in[50]) ^ in[52]) ^ in[53]) ^ in[55]) ^ in[56]) ^ in[57]) ^ in[59]) ^ in[60]) ^ in[61]; - assign out[70] = ((((((((((((((((((((((((in[4] ^ in[9]) ^ in[13]) ^ in[16]) ^ in[18]) ^ in[20]) ^ in[24]) ^ in[28]) ^ in[31]) ^ in[33]) ^ in[35]) ^ in[38]) ^ in[41]) ^ in[43]) ^ in[45]) ^ in[47]) ^ in[49]) ^ in[51]) ^ in[52]) ^ in[54]) ^ in[55]) ^ in[56]) ^ in[59]) ^ in[60]) ^ in[61]) ^ in[62]; - assign out[71] = ((((((((((((((((((((((((in[5] ^ in[10]) ^ in[14]) ^ in[17]) ^ in[19]) ^ in[20]) ^ in[25]) ^ in[29]) ^ in[32]) ^ in[34]) ^ in[35]) ^ in[39]) ^ in[42]) ^ in[44]) ^ in[45]) ^ in[48]) ^ in[50]) ^ in[51]) ^ in[53]) ^ in[54]) ^ in[55]) ^ in[57]) ^ in[58]) ^ in[60]) ^ in[62]) ^ in[63]; -endmodule diff --git a/flow/designs/src/ibex/prim_xilinx_clock_gating.v b/flow/designs/src/ibex/prim_xilinx_clock_gating.v deleted file mode 100644 index 0f9bd6bd1e..0000000000 --- a/flow/designs/src/ibex/prim_xilinx_clock_gating.v +++ /dev/null @@ -1,16 +0,0 @@ -module prim_xilinx_clock_gating ( - clk_i, - en_i, - test_en_i, - clk_o -); - input clk_i; - input en_i; - input test_en_i; - output wire clk_o; - BUFGCE u_bufgce( - .I(clk_i), - .CE(en_i | test_en_i), - .O(clk_o) - ); -endmodule diff --git a/flow/designs/src/ibex_sv/BUILD.bazel b/flow/designs/src/ibex_sv/BUILD.bazel new file mode 100644 index 0000000000..964365b4e1 --- /dev/null +++ b/flow/designs/src/ibex_sv/BUILD.bazel @@ -0,0 +1,9 @@ +filegroup( + name = "verilog", + srcs = glob(include = [ + "**/*.sv", + "**/*.svh", + "**/*.v", + ]), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/ibex/LICENSE b/flow/designs/src/ibex_sv/LICENSE similarity index 100% rename from flow/designs/src/ibex/LICENSE rename to flow/designs/src/ibex_sv/LICENSE diff --git a/flow/designs/src/ibex/README.md b/flow/designs/src/ibex_sv/README.md similarity index 80% rename from flow/designs/src/ibex/README.md rename to flow/designs/src/ibex_sv/README.md index cc32773ce0..0ee889695e 100644 --- a/flow/designs/src/ibex/README.md +++ b/flow/designs/src/ibex_sv/README.md @@ -10,6 +10,6 @@ Cloned from https://github.com/lowRISC/ibex (`commit 77d801001554cce8fe69e742e96 # Modifications - Default configuration from Repository. -- Converted to verilog [using](https://github.com/zachjs/sv2v). +- Pruned to only those source files which are used and moved most to the top directory. - Added timing constraints. - Added LICENSE. diff --git a/flow/designs/src/ibex_sv/ibex_alu.sv b/flow/designs/src/ibex_sv/ibex_alu.sv new file mode 100644 index 0000000000..1438ff5c7f --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_alu.sv @@ -0,0 +1,1271 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Arithmetic logic unit + */ +module ibex_alu #( + parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone +) ( + input ibex_pkg::alu_op_e operator_i, + input logic [31:0] operand_a_i, + input logic [31:0] operand_b_i, + + input logic instr_first_cycle_i, + + input logic [32:0] multdiv_operand_a_i, + input logic [32:0] multdiv_operand_b_i, + + input logic multdiv_sel_i, + + input logic [31:0] imd_val_q_i[2], + output logic [31:0] imd_val_d_o[2], + output logic [1:0] imd_val_we_o, + + output logic [31:0] adder_result_o, + output logic [33:0] adder_result_ext_o, + + output logic [31:0] result_o, + output logic comparison_result_o, + output logic is_equal_result_o +); + import ibex_pkg::*; + + logic [31:0] operand_a_rev; + logic [32:0] operand_b_neg; + + // bit reverse operand_a for left shifts and bit counting + for (genvar k = 0; k < 32; k++) begin : gen_rev_operand_a + assign operand_a_rev[k] = operand_a_i[31-k]; + end + + /////////// + // Adder // + /////////// + + logic adder_op_b_negate; + logic [32:0] adder_in_a, adder_in_b; + logic [31:0] adder_result; + + always_comb begin + adder_op_b_negate = 1'b0; + unique case (operator_i) + // Adder OPs + ALU_SUB, + + // Comparator OPs + ALU_EQ, ALU_NE, + ALU_GE, ALU_GEU, + ALU_LT, ALU_LTU, + ALU_SLT, ALU_SLTU, + + // MinMax OPs (RV32B Ops) + ALU_MIN, ALU_MINU, + ALU_MAX, ALU_MAXU: adder_op_b_negate = 1'b1; + + default:; + endcase + end + + // prepare operand a + assign adder_in_a = multdiv_sel_i ? multdiv_operand_a_i : {operand_a_i,1'b1}; + + // prepare operand b + assign operand_b_neg = {operand_b_i,1'b0} ^ {33{1'b1}}; + always_comb begin + unique case(1'b1) + multdiv_sel_i: adder_in_b = multdiv_operand_b_i; + adder_op_b_negate: adder_in_b = operand_b_neg; + default : adder_in_b = {operand_b_i, 1'b0}; + endcase + end + + // actual adder + assign adder_result_ext_o = $unsigned(adder_in_a) + $unsigned(adder_in_b); + + assign adder_result = adder_result_ext_o[32:1]; + + assign adder_result_o = adder_result; + + //////////////// + // Comparison // + //////////////// + + logic is_equal; + logic is_greater_equal; // handles both signed and unsigned forms + logic cmp_signed; + + always_comb begin + unique case (operator_i) + ALU_GE, + ALU_LT, + ALU_SLT, + // RV32B only + ALU_MIN, + ALU_MAX: cmp_signed = 1'b1; + + default: cmp_signed = 1'b0; + endcase + end + + assign is_equal = (adder_result == 32'b0); + assign is_equal_result_o = is_equal; + + // Is greater equal + always_comb begin + if ((operand_a_i[31] ^ operand_b_i[31]) == 1'b0) begin + is_greater_equal = (adder_result[31] == 1'b0); + end else begin + is_greater_equal = operand_a_i[31] ^ (cmp_signed); + end + end + + // GTE unsigned: + // (a[31] == 1 && b[31] == 1) => adder_result[31] == 0 + // (a[31] == 0 && b[31] == 0) => adder_result[31] == 0 + // (a[31] == 1 && b[31] == 0) => 1 + // (a[31] == 0 && b[31] == 1) => 0 + + // GTE signed: + // (a[31] == 1 && b[31] == 1) => adder_result[31] == 0 + // (a[31] == 0 && b[31] == 0) => adder_result[31] == 0 + // (a[31] == 1 && b[31] == 0) => 0 + // (a[31] == 0 && b[31] == 1) => 1 + + // generate comparison result + logic cmp_result; + + always_comb begin + unique case (operator_i) + ALU_EQ: cmp_result = is_equal; + ALU_NE: cmp_result = ~is_equal; + ALU_GE, ALU_GEU, + ALU_MAX, ALU_MAXU: cmp_result = is_greater_equal; // RV32B only + ALU_LT, ALU_LTU, + ALU_MIN, ALU_MINU, //RV32B only + ALU_SLT, ALU_SLTU: cmp_result = ~is_greater_equal; + + default: cmp_result = is_equal; + endcase + end + + assign comparison_result_o = cmp_result; + + /////////// + // Shift // + /////////// + + // The shifter structure consists of a 33-bit shifter: 32-bit operand + 1 bit extension for + // arithmetic shifts and one-shift support. + // Rotations and funnel shifts are implemented as multi-cycle instructions. + // The shifter is also used for single-bit instructions and bit-field place as detailed below. + // + // Standard Shifts + // =============== + // For standard shift instructions, the direction of the shift is to the right by default. For + // left shifts, the signal shift_left signal is set. If so, the operand is initially reversed, + // shifted to the right by the specified amount and shifted back again. For arithmetic- and + // one-shifts the 33rd bit of the shifter operand can is set accordingly. + // + // Multicycle Shifts + // ================= + // + // Rotation + // -------- + // For rotations, the operand signals operand_a_i and operand_b_i are kept constant to rs1 and + // rs2 respectively. + // + // Rotation pseudocode: + // shift_amt = rs2 & 31; + // multicycle_result = (rs1 >> shift_amt) | (rs1 << (32 - shift_amt)); + // ^-- cycle 0 -----^ ^-- cycle 1 --------------^ + // + // Funnel Shifts + // ------------- + // For funnel shifs, operand_a_i is tied to rs1 in the first cycle and rs3 in the + // second cycle. operand_b_i is always tied to rs2. The order of applying the shift amount or + // its complement is determined by bit [5] of shift_amt. + // + // Funnel shift Pseudocode: (fsl) + // shift_amt = rs2 & 63; + // shift_amt_compl = 32 - shift_amt[4:0] + // if (shift_amt >=33): + // multicycle_result = (rs1 >> shift_amt_compl[4:0]) | (rs3 << shift_amt[4:0]); + // ^-- cycle 0 ----------------^ ^-- cycle 1 ------------^ + // else if (shift_amt <= 31 && shift_amt > 0): + // multicycle_result = (rs1 << shift_amt[4:0]) | (rs3 >> shift_amt_compl[4:0]); + // ^-- cycle 0 ----------^ ^-- cycle 1 -------------------^ + // For shift_amt == 0, 32, both shift_amt[4:0] and shift_amt_compl[4:0] == '0. + // these cases need to be handled separately outside the shifting structure: + // else if (shift_amt == 32): + // multicycle_result = rs3 + // else if (shift_amt == 0): + // multicycle_result = rs1. + // + // Single-Bit Instructions + // ======================= + // Single bit instructions operate on bit operand_b_i[4:0] of operand_a_i. + + // The operations sbset, sbclr and sbinv are implemented by generation of a bit-mask using the + // shifter structure. This is done by left-shifting the operand 32'h1 by the required amount. + // The signal shift_sbmode multiplexes the shifter input and sets the signal shift_left. + // Further processing is taken care of by a separate structure. + // + // For sbext, the bit defined by operand_b_i[4:0] is to be returned. This is done by simply + // shifting operand_a_i to the right by the required amount and returning bit [0] of the result. + // + // Bit-Field Place + // =============== + // The shifter structure is shared to compute bfp_mask << bfp_off. + + logic shift_left; + logic shift_ones; + logic shift_arith; + logic shift_funnel; + logic shift_sbmode; + logic [5:0] shift_amt; + logic [5:0] shift_amt_compl; // complementary shift amount (32 - shift_amt) + + logic [31:0] shift_operand; + logic [32:0] shift_result_ext; + logic unused_shift_result_ext; + logic [31:0] shift_result; + logic [31:0] shift_result_rev; + + // zbf + logic bfp_op; + logic [4:0] bfp_len; + logic [4:0] bfp_off; + logic [31:0] bfp_mask; + logic [31:0] bfp_mask_rev; + logic [31:0] bfp_result; + + // bfp: shares the shifter structure to compute bfp_mask << bfp_off + assign bfp_op = (RV32B != RV32BNone) ? (operator_i == ALU_BFP) : 1'b0; + assign bfp_len = {~(|operand_b_i[27:24]), operand_b_i[27:24]}; // len = 0 encodes for len = 16 + assign bfp_off = operand_b_i[20:16]; + assign bfp_mask = (RV32B != RV32BNone) ? ~(32'hffff_ffff << bfp_len) : '0; + for (genvar i=0; i<32; i++) begin : gen_rev_bfp_mask + assign bfp_mask_rev[i] = bfp_mask[31-i]; + end + + assign bfp_result =(RV32B != RV32BNone) ? + (~shift_result & operand_a_i) | ((operand_b_i & bfp_mask) << bfp_off) : '0; + + // bit shift_amt[5]: word swap bit: only considered for FSL/FSR. + // if set, reverse operations in first and second cycle. + assign shift_amt[5] = operand_b_i[5] & shift_funnel; + assign shift_amt_compl = 32 - operand_b_i[4:0]; + + always_comb begin + if (bfp_op) begin + shift_amt[4:0] = bfp_off ; // length field of bfp control word + end else begin + shift_amt[4:0] = instr_first_cycle_i ? + (operand_b_i[5] && shift_funnel ? shift_amt_compl[4:0] : operand_b_i[4:0]) : + (operand_b_i[5] && shift_funnel ? operand_b_i[4:0] : shift_amt_compl[4:0]); + end + end + + // single-bit mode: shift + assign shift_sbmode = (RV32B != RV32BNone) ? + (operator_i == ALU_SBSET) | (operator_i == ALU_SBCLR) | (operator_i == ALU_SBINV) : 1'b0; + + // left shift if this is: + // * a standard left shift (slo, sll) + // * a rol in the first cycle + // * a ror in the second cycle + // * fsl: without word-swap bit: first cycle, else: second cycle + // * fsr: without word-swap bit: second cycle, else: first cycle + // * a single-bit instruction: sbclr, sbset, sbinv (excluding sbext) + // * bfp: bfp_mask << bfp_off + always_comb begin + unique case (operator_i) + ALU_SLL: shift_left = 1'b1; + ALU_SLO, + ALU_BFP: shift_left = (RV32B != RV32BNone) ? 1'b1 : 1'b0; + ALU_ROL: shift_left = (RV32B != RV32BNone) ? instr_first_cycle_i : 0; + ALU_ROR: shift_left = (RV32B != RV32BNone) ? ~instr_first_cycle_i : 0; + ALU_FSL: shift_left = (RV32B != RV32BNone) ? + (shift_amt[5] ? ~instr_first_cycle_i : instr_first_cycle_i) : 1'b0; + ALU_FSR: shift_left = (RV32B != RV32BNone) ? + (shift_amt[5] ? instr_first_cycle_i : ~instr_first_cycle_i) : 1'b0; + default: shift_left = 1'b0; + endcase + if (shift_sbmode) begin + shift_left = 1'b1; + end + end + + assign shift_arith = (operator_i == ALU_SRA); + assign shift_ones = + (RV32B != RV32BNone) ? (operator_i == ALU_SLO) | (operator_i == ALU_SRO) : 1'b0; + assign shift_funnel = + (RV32B != RV32BNone) ? (operator_i == ALU_FSL) | (operator_i == ALU_FSR) : 1'b0; + + // shifter structure. + always_comb begin + // select shifter input + // for bfp, sbmode and shift_left the corresponding bit-reversed input is chosen. + if (RV32B == RV32BNone) begin + shift_operand = shift_left ? operand_a_rev : operand_a_i; + end else begin + unique case (1'b1) + bfp_op: shift_operand = bfp_mask_rev; + shift_sbmode: shift_operand = 32'h8000_0000; + default: shift_operand = shift_left ? operand_a_rev : operand_a_i; + endcase + end + + shift_result_ext = + $unsigned($signed({shift_ones | (shift_arith & shift_operand[31]), shift_operand}) >>> + shift_amt[4:0]); + + shift_result = shift_result_ext[31:0]; + unused_shift_result_ext = shift_result_ext[32]; + + for (int unsigned i=0; i<32; i++) begin + shift_result_rev[i] = shift_result[31-i]; + end + + shift_result = shift_left ? shift_result_rev : shift_result; + + end + + /////////////////// + // Bitwise Logic // + /////////////////// + + logic bwlogic_or; + logic bwlogic_and; + logic [31:0] bwlogic_operand_b; + logic [31:0] bwlogic_or_result; + logic [31:0] bwlogic_and_result; + logic [31:0] bwlogic_xor_result; + logic [31:0] bwlogic_result; + + logic bwlogic_op_b_negate; + + always_comb begin + unique case (operator_i) + // Logic-with-negate OPs (RV32B Ops) + ALU_XNOR, + ALU_ORN, + ALU_ANDN: bwlogic_op_b_negate = (RV32B != RV32BNone) ? 1'b1 : 1'b0; + ALU_CMIX: bwlogic_op_b_negate = (RV32B != RV32BNone) ? ~instr_first_cycle_i : 1'b0; + default: bwlogic_op_b_negate = 1'b0; + endcase + end + + assign bwlogic_operand_b = bwlogic_op_b_negate ? operand_b_neg[32:1] : operand_b_i; + + assign bwlogic_or_result = operand_a_i | bwlogic_operand_b; + assign bwlogic_and_result = operand_a_i & bwlogic_operand_b; + assign bwlogic_xor_result = operand_a_i ^ bwlogic_operand_b; + + assign bwlogic_or = (operator_i == ALU_OR) | (operator_i == ALU_ORN); + assign bwlogic_and = (operator_i == ALU_AND) | (operator_i == ALU_ANDN); + + always_comb begin + unique case (1'b1) + bwlogic_or: bwlogic_result = bwlogic_or_result; + bwlogic_and: bwlogic_result = bwlogic_and_result; + default: bwlogic_result = bwlogic_xor_result; + endcase + end + + logic [5:0] bitcnt_result; + logic [31:0] minmax_result; + logic [31:0] pack_result; + logic [31:0] sext_result; + logic [31:0] singlebit_result; + logic [31:0] rev_result; + logic [31:0] shuffle_result; + logic [31:0] butterfly_result; + logic [31:0] invbutterfly_result; + logic [31:0] clmul_result; + logic [31:0] multicycle_result; + + if (RV32B != RV32BNone) begin : g_alu_rvb + + ///////////////// + // Bitcounting // + ///////////////// + + // The bit-counter structure computes the number of set bits in its operand. Partial results + // (from left to right) are needed to compute the control masks for computation of bext/bdep + // by the butterfly network, if implemented. + // For pcnt, clz and ctz, only the end result is used. + + logic zbe_op; + logic bitcnt_ctz; + logic bitcnt_clz; + logic bitcnt_cz; + logic [31:0] bitcnt_bits; + logic [31:0] bitcnt_mask_op; + logic [31:0] bitcnt_bit_mask; + logic [ 5:0] bitcnt_partial [32]; + logic [31:0] bitcnt_partial_lsb_d; + logic [31:0] bitcnt_partial_msb_d; + + + assign bitcnt_ctz = operator_i == ALU_CTZ; + assign bitcnt_clz = operator_i == ALU_CLZ; + assign bitcnt_cz = bitcnt_ctz | bitcnt_clz; + assign bitcnt_result = bitcnt_partial[31]; + + // Bit-mask generation for clz and ctz: + // The bit mask is generated by spreading the lowest-order set bit in the operand to all + // higher order bits. The resulting mask is inverted to cover the lowest order zeros. In order + // to create the bit mask for leading zeros, the input operand needs to be reversed. + assign bitcnt_mask_op = bitcnt_clz ? operand_a_rev : operand_a_i; + + always_comb begin + bitcnt_bit_mask = bitcnt_mask_op; + bitcnt_bit_mask |= bitcnt_bit_mask << 1; + bitcnt_bit_mask |= bitcnt_bit_mask << 2; + bitcnt_bit_mask |= bitcnt_bit_mask << 4; + bitcnt_bit_mask |= bitcnt_bit_mask << 8; + bitcnt_bit_mask |= bitcnt_bit_mask << 16; + bitcnt_bit_mask = ~bitcnt_bit_mask; + end + + assign zbe_op = (operator_i == ALU_BEXT) | (operator_i == ALU_BDEP); + + always_comb begin + case(1'b1) + zbe_op: bitcnt_bits = operand_b_i; + bitcnt_cz: bitcnt_bits = bitcnt_bit_mask & ~bitcnt_mask_op; // clz / ctz + default: bitcnt_bits = operand_a_i; // pcnt + endcase + end + + // The parallel prefix counter is of the structure of a Brent-Kung Adder. In the first + // log2(width) stages, the sum of the n preceding bit lines is computed for the bit lines at + // positions 2**n-1 (power-of-two positions) where n denotes the current stage. + // In stage n=log2(width), the count for position width-1 (the MSB) is finished. + // For the intermediate values, an inverse adder tree then computes the bit counts for the bit + // lines at positions + // m = 2**(n-1) + i*2**(n-2), where i = [1 ... width / 2**(n-1)-1] and n = [log2(width) ... 2]. + // Thus, at every subsequent stage the result of two previously unconnected sub-trees is + // summed, starting at the node summing bits [width/2-1 : 0] and [3*width/4-1: width/2] + // and moving to iteratively sum up all the sub-trees. + // The inverse adder tree thus features log2(width) - 1 stages the first of these stages is a + // single addition at position 3*width/4 - 1. It does not interfere with the last + // stage of the primary adder tree. These stages can thus be folded together, resulting in a + // total of 2*log2(width)-2 stages. + // For more details refer to R. Brent, H. T. Kung, "A Regular Layout for Parallel Adders", + // (1982). + // For a bitline at position p, only bits + // bitcnt_partial[max(i, such that p % log2(i) == 0)-1 : 0] are needed for generation of the + // butterfly network control signals. The adders in the intermediate value adder tree thus need + // not be full 5-bit adders. We leave the optimization to the synthesis tools. + // + // Consider the following 8-bit example for illustraton. + // + // let bitcnt_bits = 8'babcdefgh. + // + // a b c d e f g h + // | /: | /: | /: | /: + // |/ : |/ : |/ : |/ : + // stage 1: + : + : + : + : + // | : /: : | : /: : + // |,--+ : : |,--+ : : + // stage 2: + : : : + : : : + // | : | : /: : : : + // |,-----,--+ : : : : ^-primary adder tree + // stage 3: + : + : : : : : ------------------------- + // : | /| /| /| /| /| : ,-intermediate adder tree + // : |/ |/ |/ |/ |/ : : + // stage 4 : + + + + + : : + // : : : : : : : : + // bitcnt_partial[i] 7 6 5 4 3 2 1 0 + + always_comb begin + bitcnt_partial = '{default: '0}; + // stage 1 + for (int unsigned i=1; i<32; i+=2) begin + bitcnt_partial[i] = {5'h0, bitcnt_bits[i]} + {5'h0, bitcnt_bits[i-1]}; + end + // stage 2 + for (int unsigned i=3; i<32; i+=4) begin + bitcnt_partial[i] = bitcnt_partial[i-2] + bitcnt_partial[i]; + end + // stage 3 + for (int unsigned i=7; i<32; i+=8) begin + bitcnt_partial[i] = bitcnt_partial[i-4] + bitcnt_partial[i]; + end + // stage 4 + for (int unsigned i=15; i <32; i+=16) begin + bitcnt_partial[i] = bitcnt_partial[i-8] + bitcnt_partial[i]; + end + // stage 5 + bitcnt_partial[31] = bitcnt_partial[15] + bitcnt_partial[31]; + // ^- primary adder tree + // ------------------------------- + // ,-intermediate value adder tree + bitcnt_partial[23] = bitcnt_partial[15] + bitcnt_partial[23]; + + // stage 6 + for (int unsigned i=11; i<32; i+=8) begin + bitcnt_partial[i] = bitcnt_partial[i-4] + bitcnt_partial[i]; + end + + // stage 7 + for (int unsigned i=5; i<32; i+=4) begin + bitcnt_partial[i] = bitcnt_partial[i-2] + bitcnt_partial[i]; + end + // stage 8 + bitcnt_partial[0] = {5'h0, bitcnt_bits[0]}; + for (int unsigned i=2; i<32; i+=2) begin + bitcnt_partial[i] = bitcnt_partial[i-1] + {5'h0, bitcnt_bits[i]}; + end + end + + /////////////// + // Min / Max // + /////////////// + + assign minmax_result = cmp_result ? operand_a_i : operand_b_i; + + ////////// + // Pack // + ////////// + + logic packu; + logic packh; + assign packu = operator_i == ALU_PACKU; + assign packh = operator_i == ALU_PACKH; + + always_comb begin + unique case (1'b1) + packu: pack_result = {operand_b_i[31:16], operand_a_i[31:16]}; + packh: pack_result = {16'h0, operand_b_i[7:0], operand_a_i[7:0]}; + default: pack_result = {operand_b_i[15:0], operand_a_i[15:0]}; + endcase + end + + ////////// + // Sext // + ////////// + + assign sext_result = (operator_i == ALU_SEXTB) ? + { {24{operand_a_i[7]}}, operand_a_i[7:0]} : { {16{operand_a_i[15]}}, operand_a_i[15:0]}; + + ///////////////////////////// + // Single-bit Instructions // + ///////////////////////////// + + always_comb begin + unique case (operator_i) + ALU_SBSET: singlebit_result = operand_a_i | shift_result; + ALU_SBCLR: singlebit_result = operand_a_i & ~shift_result; + ALU_SBINV: singlebit_result = operand_a_i ^ shift_result; + default: singlebit_result = {31'h0, shift_result[0]}; // ALU_SBEXT + endcase + end + + //////////////////////////////////// + // General Reverse and Or-combine // + //////////////////////////////////// + + // Only a subset of the General reverse and or-combine instructions are implemented in the + // balanced version of the B extension. Currently rev, rev8 and orc.b are supported in the + // base extension. + + logic [4:0] zbp_shift_amt; + logic gorc_op; + + assign gorc_op = (operator_i == ALU_GORC); + assign zbp_shift_amt[2:0] = (RV32B == RV32BFull) ? shift_amt[2:0] : {3{&shift_amt[2:0]}}; + assign zbp_shift_amt[4:3] = (RV32B == RV32BFull) ? shift_amt[4:3] : {2{&shift_amt[4:3]}}; + + always_comb begin + rev_result = operand_a_i; + + if (zbp_shift_amt[0]) begin + rev_result = (gorc_op ? rev_result : 32'h0) | + ((rev_result & 32'h5555_5555) << 1) | + ((rev_result & 32'haaaa_aaaa) >> 1); + end + + if (zbp_shift_amt[1]) begin + rev_result = (gorc_op ? rev_result : 32'h0) | + ((rev_result & 32'h3333_3333) << 2) | + ((rev_result & 32'hcccc_cccc) >> 2); + end + + if (zbp_shift_amt[2]) begin + rev_result = (gorc_op ? rev_result : 32'h0) | + ((rev_result & 32'h0f0f_0f0f) << 4) | + ((rev_result & 32'hf0f0_f0f0) >> 4); + end + + if (zbp_shift_amt[3]) begin + rev_result = (gorc_op & (RV32B == RV32BFull) ? rev_result : 32'h0) | + ((rev_result & 32'h00ff_00ff) << 8) | + ((rev_result & 32'hff00_ff00) >> 8); + end + + if (zbp_shift_amt[4]) begin + rev_result = (gorc_op & (RV32B == RV32BFull) ? rev_result : 32'h0) | + ((rev_result & 32'h0000_ffff) << 16) | + ((rev_result & 32'hffff_0000) >> 16); + end + end + + logic crc_hmode; + logic crc_bmode; + logic [31:0] clmul_result_rev; + + if (RV32B == RV32BFull) begin : gen_alu_rvb_full + + ///////////////////////// + // Shuffle / Unshuffle // + ///////////////////////// + + localparam logic [31:0] SHUFFLE_MASK_L [4] = + '{32'h00ff_0000, 32'h0f00_0f00, 32'h3030_3030, 32'h4444_4444}; + localparam logic [31:0] SHUFFLE_MASK_R [4] = + '{32'h0000_ff00, 32'h00f0_00f0, 32'h0c0c_0c0c, 32'h2222_2222}; + + localparam logic [31:0] FLIP_MASK_L [4] = + '{32'h2200_1100, 32'h0044_0000, 32'h4411_0000, 32'h1100_0000}; + localparam logic [31:0] FLIP_MASK_R [4] = + '{32'h0088_0044, 32'h0000_2200, 32'h0000_8822, 32'h0000_0088}; + + logic [31:0] SHUFFLE_MASK_NOT [4]; + for(genvar i = 0; i < 4; i++) begin : gen_shuffle_mask_not + assign SHUFFLE_MASK_NOT[i] = ~(SHUFFLE_MASK_L[i] | SHUFFLE_MASK_R[i]); + end + + logic shuffle_flip; + assign shuffle_flip = operator_i == ALU_UNSHFL; + + logic [3:0] shuffle_mode; + + always_comb begin + shuffle_result = operand_a_i; + + if (shuffle_flip) begin + shuffle_mode[3] = shift_amt[0]; + shuffle_mode[2] = shift_amt[1]; + shuffle_mode[1] = shift_amt[2]; + shuffle_mode[0] = shift_amt[3]; + end else begin + shuffle_mode = shift_amt[3:0]; + end + + if (shuffle_flip) begin + shuffle_result = (shuffle_result & 32'h8822_4411) | + ((shuffle_result << 6) & FLIP_MASK_L[0]) | + ((shuffle_result >> 6) & FLIP_MASK_R[0]) | + ((shuffle_result << 9) & FLIP_MASK_L[1]) | + ((shuffle_result >> 9) & FLIP_MASK_R[1]) | + ((shuffle_result << 15) & FLIP_MASK_L[2]) | + ((shuffle_result >> 15) & FLIP_MASK_R[2]) | + ((shuffle_result << 21) & FLIP_MASK_L[3]) | + ((shuffle_result >> 21) & FLIP_MASK_R[3]); + end + + if (shuffle_mode[3]) begin + shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[0]) | + (((shuffle_result << 8) & SHUFFLE_MASK_L[0]) | + ((shuffle_result >> 8) & SHUFFLE_MASK_R[0])); + end + if (shuffle_mode[2]) begin + shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[1]) | + (((shuffle_result << 4) & SHUFFLE_MASK_L[1]) | + ((shuffle_result >> 4) & SHUFFLE_MASK_R[1])); + end + if (shuffle_mode[1]) begin + shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[2]) | + (((shuffle_result << 2) & SHUFFLE_MASK_L[2]) | + ((shuffle_result >> 2) & SHUFFLE_MASK_R[2])); + end + if (shuffle_mode[0]) begin + shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[3]) | + (((shuffle_result << 1) & SHUFFLE_MASK_L[3]) | + ((shuffle_result >> 1) & SHUFFLE_MASK_R[3])); + end + + if (shuffle_flip) begin + shuffle_result = (shuffle_result & 32'h8822_4411) | + ((shuffle_result << 6) & FLIP_MASK_L[0]) | + ((shuffle_result >> 6) & FLIP_MASK_R[0]) | + ((shuffle_result << 9) & FLIP_MASK_L[1]) | + ((shuffle_result >> 9) & FLIP_MASK_R[1]) | + ((shuffle_result << 15) & FLIP_MASK_L[2]) | + ((shuffle_result >> 15) & FLIP_MASK_R[2]) | + ((shuffle_result << 21) & FLIP_MASK_L[3]) | + ((shuffle_result >> 21) & FLIP_MASK_R[3]); + end + end + + /////////////// + // Butterfly // + /////////////// + + // The butterfly / inverse butterfly network executing bext/bdep (zbe) instructions. + // For bdep, the control bits mask of a local left region is generated by + // the inverse of a n-bit left rotate and complement upon wrap (LROTC) operation by the number + // of ones in the deposit bitmask to the right of the segment. n hereby denotes the width + // of the according segment. The bitmask for a pertaining local right region is equal to the + // corresponding local left region. Bext uses an analogue inverse process. + // Consider the following 8-bit example. For details, see Hilewitz et al. "Fast Bit Gather, + // Bit Scatter and Bit Permuation Instructions for Commodity Microprocessors", (2008). + // + // The bext/bdep instructions are completed in 2 cycles. In the first cycle, the control + // bitmask is prepared by executing the parallel prefix bit count. In the second cycle, + // the bit swapping is executed according to the control masks. + + // 8-bit example: (Hilewitz et al.) + // Consider the instruction bdep operand_a_i deposit_mask + // Let operand_a_i = 8'babcd_efgh + // deposit_mask = 8'b1010_1101 + // + // control bitmask for stage 1: + // - number of ones in the right half of the deposit bitmask: 3 + // - width of the segment: 4 + // - control bitmask = ~LROTC(4'b0, 3)[3:0] = 4'b1000 + // + // control bitmask: c3 c2 c1 c0 c3 c2 c1 c0 + // 1 0 0 0 1 0 0 0 + // <- L -----> <- R -----> + // operand_a_i a b c d e f g h + // :\ | | | /: | | | + // : +|---|--|-+ : | | | + // :/ | | | \: | | | + // stage 1 e b c d a f g h + // + // control bitmask: c3 c2 c3 c2 c1 c0 c1 c0 + // 1 1 1 1 1 0 1 0 + // :\ :\ /: /: :\ | /: | + // : +:-+-:+ : : +|-+ : | + // :/ :/ \: \: :/ | \: | + // stage 2 c d e b g f a h + // L R L R L R L R + // control bitmask: c3 c3 c2 c2 c1 c1 c0 c0 + // 1 1 0 0 1 1 0 0 + // :\/: | | :\/: | | + // : : | | : : | | + // :/\: | | :/\: | | + // stage 3 d c e b f g a h + // & deposit bitmask: 1 0 1 0 1 1 0 1 + // result: d 0 e 0 f g 0 h + + logic [ 5:0] bitcnt_partial_q [32]; + + // first cycle + // Store partial bitcnts + for (genvar i=0; i<32; i++) begin : gen_bitcnt_reg_in_lsb + assign bitcnt_partial_lsb_d[i] = bitcnt_partial[i][0]; + end + + for (genvar i=0; i<16; i++) begin : gen_bitcnt_reg_in_b1 + assign bitcnt_partial_msb_d[i] = bitcnt_partial[2*i+1][1]; + end + + for (genvar i=0; i<8; i++) begin : gen_bitcnt_reg_in_b2 + assign bitcnt_partial_msb_d[16+i] = bitcnt_partial[4*i+3][2]; + end + + for (genvar i=0; i<4; i++) begin : gen_bitcnt_reg_in_b3 + assign bitcnt_partial_msb_d[24+i] = bitcnt_partial[8*i+7][3]; + end + + for (genvar i=0; i<2; i++) begin : gen_bitcnt_reg_in_b4 + assign bitcnt_partial_msb_d[28+i] = bitcnt_partial[16*i+15][4]; + end + + assign bitcnt_partial_msb_d[30] = bitcnt_partial[31][5]; + assign bitcnt_partial_msb_d[31] = 1'b0; // unused + + // Second cycle + // Load partial bitcnts + always_comb begin + bitcnt_partial_q = '{default: '0}; + + for (int unsigned i=0; i<32; i++) begin : gen_bitcnt_reg_out_lsb + bitcnt_partial_q[i][0] = imd_val_q_i[0][i]; + end + + for (int unsigned i=0; i<16; i++) begin : gen_bitcnt_reg_out_b1 + bitcnt_partial_q[2*i+1][1] = imd_val_q_i[1][i]; + end + + for (int unsigned i=0; i<8; i++) begin : gen_bitcnt_reg_out_b2 + bitcnt_partial_q[4*i+3][2] = imd_val_q_i[1][16+i]; + end + + for (int unsigned i=0; i<4; i++) begin : gen_bitcnt_reg_out_b3 + bitcnt_partial_q[8*i+7][3] = imd_val_q_i[1][24+i]; + end + + for (int unsigned i=0; i<2; i++) begin : gen_bitcnt_reg_out_b4 + bitcnt_partial_q[16*i+15][4] = imd_val_q_i[1][28+i]; + end + + bitcnt_partial_q[31][5] = imd_val_q_i[1][30]; + end + + logic [31:0] butterfly_mask_l[5]; + logic [31:0] butterfly_mask_r[5]; + logic [31:0] butterfly_mask_not[5]; + logic [31:0] lrotc_stage [5]; // left rotate and complement upon wrap + + // number of bits in local r = 32 / 2**(stage + 1) = 16/2**stage + `define _N(stg) (16 >> stg) + + // bext / bdep control bit generation + for (genvar stg=0; stg<5; stg++) begin : gen_butterfly_ctrl_stage + // number of segs: 2** stg + for (genvar seg=0; seg<2**stg; seg++) begin : gen_butterfly_ctrl + + assign lrotc_stage[stg][2*`_N(stg)*(seg+1)-1 : 2*`_N(stg)*seg] = + {{`_N(stg){1'b0}},{`_N(stg){1'b1}}} << + bitcnt_partial_q[`_N(stg)*(2*seg+1)-1][$clog2(`_N(stg)):0]; + + assign butterfly_mask_l[stg][`_N(stg)*(2*seg+2)-1 : `_N(stg)*(2*seg+1)] + = ~lrotc_stage[stg][`_N(stg)*(2*seg+2)-1 : `_N(stg)*(2*seg+1)]; + + assign butterfly_mask_r[stg][`_N(stg)*(2*seg+1)-1 : `_N(stg)*(2*seg)] + = ~lrotc_stage[stg][`_N(stg)*(2*seg+2)-1 : `_N(stg)*(2*seg+1)]; + + assign butterfly_mask_l[stg][`_N(stg)*(2*seg+1)-1 : `_N(stg)*(2*seg)] = '0; + assign butterfly_mask_r[stg][`_N(stg)*(2*seg+2)-1 : `_N(stg)*(2*seg+1)] = '0; + end + end + `undef _N + + for (genvar stg=0; stg<5; stg++) begin : gen_butterfly_not + assign butterfly_mask_not[stg] = + ~(butterfly_mask_l[stg] | butterfly_mask_r[stg]); + end + + always_comb begin + butterfly_result = operand_a_i; + + butterfly_result = butterfly_result & butterfly_mask_not[0] | + ((butterfly_result & butterfly_mask_l[0]) >> 16)| + ((butterfly_result & butterfly_mask_r[0]) << 16); + + butterfly_result = butterfly_result & butterfly_mask_not[1] | + ((butterfly_result & butterfly_mask_l[1]) >> 8)| + ((butterfly_result & butterfly_mask_r[1]) << 8); + + butterfly_result = butterfly_result & butterfly_mask_not[2] | + ((butterfly_result & butterfly_mask_l[2]) >> 4)| + ((butterfly_result & butterfly_mask_r[2]) << 4); + + butterfly_result = butterfly_result & butterfly_mask_not[3] | + ((butterfly_result & butterfly_mask_l[3]) >> 2)| + ((butterfly_result & butterfly_mask_r[3]) << 2); + + butterfly_result = butterfly_result & butterfly_mask_not[4] | + ((butterfly_result & butterfly_mask_l[4]) >> 1)| + ((butterfly_result & butterfly_mask_r[4]) << 1); + + butterfly_result = butterfly_result & operand_b_i; + end + + always_comb begin + invbutterfly_result = operand_a_i & operand_b_i; + + invbutterfly_result = invbutterfly_result & butterfly_mask_not[4] | + ((invbutterfly_result & butterfly_mask_l[4]) >> 1)| + ((invbutterfly_result & butterfly_mask_r[4]) << 1); + + invbutterfly_result = invbutterfly_result & butterfly_mask_not[3] | + ((invbutterfly_result & butterfly_mask_l[3]) >> 2)| + ((invbutterfly_result & butterfly_mask_r[3]) << 2); + + invbutterfly_result = invbutterfly_result & butterfly_mask_not[2] | + ((invbutterfly_result & butterfly_mask_l[2]) >> 4)| + ((invbutterfly_result & butterfly_mask_r[2]) << 4); + + invbutterfly_result = invbutterfly_result & butterfly_mask_not[1] | + ((invbutterfly_result & butterfly_mask_l[1]) >> 8)| + ((invbutterfly_result & butterfly_mask_r[1]) << 8); + + invbutterfly_result = invbutterfly_result & butterfly_mask_not[0] | + ((invbutterfly_result & butterfly_mask_l[0]) >> 16)| + ((invbutterfly_result & butterfly_mask_r[0]) << 16); + end + + /////////////////////////////////////////////////// + // Carry-less Multiply + Cyclic Redundancy Check // + /////////////////////////////////////////////////// + + // Carry-less multiplication can be understood as multiplication based on + // the addition interpreted as the bit-wise xor operation. + // + // Example: 1101 X 1011 = 1111111: + // + // 1011 X 1101 + // ----------- + // 1101 + // xor 1101 + // --------- + // 10111 + // xor 0000 + // ---------- + // 010111 + // xor 1101 + // ----------- + // 1111111 + // + // Architectural details: + // A 32 x 32-bit array + // [ operand_b[i] ? (operand_a << i) : '0 for i in 0 ... 31 ] + // is generated. The entries of the array are pairwise 'xor-ed' + // together in a 5-stage binary tree. + // + // + // Cyclic Redundancy Check: + // + // CRC-32 (CRC-32/ISO-HDLC) and CRC-32C (CRC-32/ISCSI) are directly implemented. For + // documentation of the crc configuration (crc-polynomials, initialization, reflection, etc.) + // see http://reveng.sourceforge.net/crc-catalogue/all.htm + // A useful guide to crc arithmetic and algorithms is given here: + // http://www.piclist.com/techref/method/math/crcguide.html. + // + // The CRC operation solves the following equation using binary polynomial arithmetic: + // + // rev(rd)(x) = rev(rs1)(x) * x**n mod {1, P}(x) + // + // where P denotes lower 32 bits of the corresponding CRC polynomial, rev(a) the bit reversal + // of a, n = 8,16, or 32 for .b, .h, .w -variants. {a, b} denotes bit concatenation. + // + // Using barret reduction, one can show that + // + // M(x) mod P(x) = R(x) = + // (M(x) * x**n) & {deg(P(x)'{1'b1}}) ^ (M(x) x**-(deg(P(x) - n)) cx mu(x) cx P(x), + // + // Where mu(x) = polydiv(x**64, {1,P}) & 0xffffffff. Here, 'cx' refers to carry-less + // multiplication. Substituting rev(rd)(x) for R(x) and rev(rs1)(x) for M(x) and solving for + // rd(x) with P(x) a crc32 polynomial (deg(P(x)) = 32), we get + // + // rd = rev( (rev(rs1) << n) ^ ((rev(rs1) >> (32-n)) cx mu cx P) + // = (rs1 >> n) ^ rev(rev( (rs1 << (32-n)) cx rev(mu)) cx P) + // ^-- cycle 0--------------------^ + // ^- cycle 1 -------------------------------------------^ + // + // In the last step we used the fact that carry-less multiplication is bit-order agnostic: + // rev(a cx b) = rev(a) cx rev(b). + + logic clmul_rmode; + logic clmul_hmode; + logic [31:0] clmul_op_a; + logic [31:0] clmul_op_b; + logic [31:0] operand_b_rev; + logic [31:0] clmul_and_stage[32]; + logic [31:0] clmul_xor_stage1[16]; + logic [31:0] clmul_xor_stage2[8]; + logic [31:0] clmul_xor_stage3[4]; + logic [31:0] clmul_xor_stage4[2]; + + logic [31:0] clmul_result_raw; + + for (genvar i=0; i<32; i++) begin: gen_rev_operand_b + assign operand_b_rev[i] = operand_b_i[31-i]; + end + + assign clmul_rmode = operator_i == ALU_CLMULR; + assign clmul_hmode = operator_i == ALU_CLMULH; + + // CRC + localparam logic [31:0] CRC32_POLYNOMIAL = 32'h04c1_1db7; + localparam logic [31:0] CRC32_MU_REV = 32'hf701_1641; + + localparam logic [31:0] CRC32C_POLYNOMIAL = 32'h1edc_6f41; + localparam logic [31:0] CRC32C_MU_REV = 32'hdea7_13f1; + + logic crc_op; + + logic crc_cpoly; + + logic [31:0] crc_operand; + logic [31:0] crc_poly; + logic [31:0] crc_mu_rev; + + assign crc_op = (operator_i == ALU_CRC32C_W) | (operator_i == ALU_CRC32_W) | + (operator_i == ALU_CRC32C_H) | (operator_i == ALU_CRC32_H) | + (operator_i == ALU_CRC32C_B) | (operator_i == ALU_CRC32_B); + + assign crc_cpoly = (operator_i == ALU_CRC32C_W) | + (operator_i == ALU_CRC32C_H) | + (operator_i == ALU_CRC32C_B); + + assign crc_hmode = (operator_i == ALU_CRC32_H) | (operator_i == ALU_CRC32C_H); + assign crc_bmode = (operator_i == ALU_CRC32_B) | (operator_i == ALU_CRC32C_B); + + assign crc_poly = crc_cpoly ? CRC32C_POLYNOMIAL : CRC32_POLYNOMIAL; + assign crc_mu_rev = crc_cpoly ? CRC32C_MU_REV : CRC32_MU_REV; + + always_comb begin + unique case(1'b1) + crc_bmode: crc_operand = {operand_a_i[7:0], 24'h0}; + crc_hmode: crc_operand = {operand_a_i[15:0], 16'h0}; + default: crc_operand = operand_a_i; + endcase + end + + // Select clmul input + always_comb begin + if (crc_op) begin + clmul_op_a = instr_first_cycle_i ? crc_operand : imd_val_q_i[0]; + clmul_op_b = instr_first_cycle_i ? crc_mu_rev : crc_poly; + end else begin + clmul_op_a = clmul_rmode | clmul_hmode ? operand_a_rev : operand_a_i; + clmul_op_b = clmul_rmode | clmul_hmode ? operand_b_rev : operand_b_i; + end + end + + for (genvar i=0; i<32; i++) begin : gen_clmul_and_op + assign clmul_and_stage[i] = clmul_op_b[i] ? clmul_op_a << i : '0; + end + + for (genvar i=0; i<16; i++) begin : gen_clmul_xor_op_l1 + assign clmul_xor_stage1[i] = clmul_and_stage[2*i] ^ clmul_and_stage[2*i+1]; + end + + for (genvar i=0; i<8; i++) begin : gen_clmul_xor_op_l2 + assign clmul_xor_stage2[i] = clmul_xor_stage1[2*i] ^ clmul_xor_stage1[2*i+1]; + end + + for (genvar i=0; i<4; i++) begin : gen_clmul_xor_op_l3 + assign clmul_xor_stage3[i] = clmul_xor_stage2[2*i] ^ clmul_xor_stage2[2*i+1]; + end + + for (genvar i=0; i<2; i++) begin : gen_clmul_xor_op_l4 + assign clmul_xor_stage4[i] = clmul_xor_stage3[2*i] ^ clmul_xor_stage3[2*i+1]; + end + + assign clmul_result_raw = clmul_xor_stage4[0] ^ clmul_xor_stage4[1]; + + for (genvar i=0; i<32; i++) begin : gen_rev_clmul_result + assign clmul_result_rev[i] = clmul_result_raw[31-i]; + end + + // clmulr_result = rev(clmul(rev(a), rev(b))) + // clmulh_result = clmulr_result >> 1 + always_comb begin + case(1'b1) + clmul_rmode: clmul_result = clmul_result_rev; + clmul_hmode: clmul_result = {1'b0, clmul_result_rev[31:1]}; + default: clmul_result = clmul_result_raw; + endcase + end + end else begin : gen_alu_rvb_notfull + logic [31:0] unused_imd_val_q_1; + assign unused_imd_val_q_1 = imd_val_q_i[1]; + assign shuffle_result = '0; + assign butterfly_result = '0; + assign invbutterfly_result = '0; + assign clmul_result = '0; + // support signals + assign bitcnt_partial_lsb_d = '0; + assign bitcnt_partial_msb_d = '0; + assign clmul_result_rev = '0; + assign crc_bmode = '0; + assign crc_hmode = '0; + end + + ////////////////////////////////////// + // Multicycle Bitmanip Instructions // + ////////////////////////////////////// + // Ternary instructions + Shift Rotations + Bit extract/deposit + CRC + // For ternary instructions (zbt), operand_a_i is tied to rs1 in the first cycle and rs3 in the + // second cycle. operand_b_i is always tied to rs2. + + always_comb begin + unique case (operator_i) + ALU_CMOV: begin + multicycle_result = (operand_b_i == 32'h0) ? operand_a_i : imd_val_q_i[0]; + imd_val_d_o = '{operand_a_i, 32'h0}; + if (instr_first_cycle_i) begin + imd_val_we_o = 2'b01; + end else begin + imd_val_we_o = 2'b00; + end + end + + ALU_CMIX: begin + multicycle_result = imd_val_q_i[0] | bwlogic_and_result; + imd_val_d_o = '{bwlogic_and_result, 32'h0}; + if (instr_first_cycle_i) begin + imd_val_we_o = 2'b01; + end else begin + imd_val_we_o = 2'b00; + end + end + + ALU_FSR, ALU_FSL, + ALU_ROL, ALU_ROR: begin + if (shift_amt[4:0] == 5'h0) begin + multicycle_result = shift_amt[5] ? operand_a_i : imd_val_q_i[0]; + end else begin + multicycle_result = imd_val_q_i[0] | shift_result; + end + imd_val_d_o = '{shift_result, 32'h0}; + if (instr_first_cycle_i) begin + imd_val_we_o = 2'b01; + end else begin + imd_val_we_o = 2'b00; + end + end + + ALU_CRC32_W, ALU_CRC32C_W, + ALU_CRC32_H, ALU_CRC32C_H, + ALU_CRC32_B, ALU_CRC32C_B: begin + if (RV32B == RV32BFull) begin + unique case(1'b1) + crc_bmode: multicycle_result = clmul_result_rev ^ (operand_a_i >> 8); + crc_hmode: multicycle_result = clmul_result_rev ^ (operand_a_i >> 16); + default: multicycle_result = clmul_result_rev; + endcase + imd_val_d_o = '{clmul_result_rev, 32'h0}; + if (instr_first_cycle_i) begin + imd_val_we_o = 2'b01; + end else begin + imd_val_we_o = 2'b00; + end + end else begin + imd_val_d_o = '{operand_a_i, 32'h0}; + imd_val_we_o = 2'b00; + multicycle_result = '0; + end + end + + ALU_BEXT, ALU_BDEP: begin + if (RV32B == RV32BFull) begin + multicycle_result = (operator_i == ALU_BDEP) ? butterfly_result : invbutterfly_result; + imd_val_d_o = '{bitcnt_partial_lsb_d, bitcnt_partial_msb_d}; + if (instr_first_cycle_i) begin + imd_val_we_o = 2'b11; + end else begin + imd_val_we_o = 2'b00; + end + end else begin + imd_val_d_o = '{operand_a_i, 32'h0}; + imd_val_we_o = 2'b00; + multicycle_result = '0; + end + end + + default: begin + imd_val_d_o = '{operand_a_i, 32'h0}; + imd_val_we_o = 2'b00; + multicycle_result = '0; + end + endcase + end + + + end else begin : g_no_alu_rvb + logic [31:0] unused_imd_val_q[2]; + assign unused_imd_val_q = imd_val_q_i; + logic [31:0] unused_butterfly_result; + assign unused_butterfly_result = butterfly_result; + logic [31:0] unused_invbutterfly_result; + assign unused_invbutterfly_result = invbutterfly_result; + // RV32B result signals + assign bitcnt_result = '0; + assign minmax_result = '0; + assign pack_result = '0; + assign sext_result = '0; + assign singlebit_result = '0; + assign rev_result = '0; + assign shuffle_result = '0; + assign butterfly_result = '0; + assign invbutterfly_result = '0; + assign clmul_result = '0; + assign multicycle_result = '0; + // RV32B support signals + assign imd_val_d_o = '{default: '0}; + assign imd_val_we_o = '{default: '0}; + end + + //////////////// + // Result mux // + //////////////// + + always_comb begin + result_o = '0; + + unique case (operator_i) + // Bitwise Logic Operations (negate: RV32B) + ALU_XOR, ALU_XNOR, + ALU_OR, ALU_ORN, + ALU_AND, ALU_ANDN: result_o = bwlogic_result; + + // Adder Operations + ALU_ADD, ALU_SUB: result_o = adder_result; + + // Shift Operations + ALU_SLL, ALU_SRL, + ALU_SRA, + // RV32B + ALU_SLO, ALU_SRO: result_o = shift_result; + + // Shuffle Operations (RV32B) + ALU_SHFL, ALU_UNSHFL: result_o = shuffle_result; + + // Comparison Operations + ALU_EQ, ALU_NE, + ALU_GE, ALU_GEU, + ALU_LT, ALU_LTU, + ALU_SLT, ALU_SLTU: result_o = {31'h0,cmp_result}; + + // MinMax Operations (RV32B) + ALU_MIN, ALU_MAX, + ALU_MINU, ALU_MAXU: result_o = minmax_result; + + // Bitcount Operations (RV32B) + ALU_CLZ, ALU_CTZ, + ALU_PCNT: result_o = {26'h0, bitcnt_result}; + + // Pack Operations (RV32B) + ALU_PACK, ALU_PACKH, + ALU_PACKU: result_o = pack_result; + + // Sign-Extend (RV32B) + ALU_SEXTB, ALU_SEXTH: result_o = sext_result; + + // Ternary Bitmanip Operations (RV32B) + ALU_CMIX, ALU_CMOV, + ALU_FSL, ALU_FSR, + // Rotate Shift (RV32B) + ALU_ROL, ALU_ROR, + // Cyclic Redundancy Checks (RV32B) + ALU_CRC32_W, ALU_CRC32C_W, + ALU_CRC32_H, ALU_CRC32C_H, + ALU_CRC32_B, ALU_CRC32C_B, + // Bit Extract / Deposit (RV32B) + ALU_BEXT, ALU_BDEP: result_o = multicycle_result; + + // Single-Bit Bitmanip Operations (RV32B) + ALU_SBSET, ALU_SBCLR, + ALU_SBINV, ALU_SBEXT: result_o = singlebit_result; + + // General Reverse / Or-combine (RV32B) + ALU_GREV, ALU_GORC: result_o = rev_result; + + // Bit Field Place (RV32B) + ALU_BFP: result_o = bfp_result; + + // Carry-less Multiply Operations (RV32B) + ALU_CLMUL, ALU_CLMULR, + ALU_CLMULH: result_o = clmul_result; + + default: ; + endcase + end + + logic unused_shift_amt_compl; + assign unused_shift_amt_compl = shift_amt_compl[5]; + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_compressed_decoder.sv b/flow/designs/src/ibex_sv/ibex_compressed_decoder.sv new file mode 100644 index 0000000000..12a487fe1d --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_compressed_decoder.sv @@ -0,0 +1,300 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Compressed instruction decoder + * + * Decodes RISC-V compressed instructions into their RV32 equivalent. + * This module is fully combinatorial, clock and reset are used for + * assertions only. + */ + +`include "prim_assert.sv" + +module ibex_compressed_decoder ( + input logic clk_i, + input logic rst_ni, + input logic valid_i, + input logic [31:0] instr_i, + output logic [31:0] instr_o, + output logic is_compressed_o, + output logic illegal_instr_o +); + import ibex_pkg::*; + + // valid_i indicates if instr_i is valid and is used for assertions only. + // The following signal is used to avoid possible lint errors. + logic unused_valid; + assign unused_valid = valid_i; + + //////////////////////// + // Compressed decoder // + //////////////////////// + + always_comb begin + // By default, forward incoming instruction, mark it as legal. + instr_o = instr_i; + illegal_instr_o = 1'b0; + + // Check if incoming instruction is compressed. + unique case (instr_i[1:0]) + // C0 + 2'b00: begin + unique case (instr_i[15:13]) + 3'b000: begin + // c.addi4spn -> addi rd', x2, imm + instr_o = {2'b0, instr_i[10:7], instr_i[12:11], instr_i[5], + instr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], {OPCODE_OP_IMM}}; + if (instr_i[12:5] == 8'b0) illegal_instr_o = 1'b1; + end + + 3'b010: begin + // c.lw -> lw rd', imm(rs1') + instr_o = {5'b0, instr_i[5], instr_i[12:10], instr_i[6], + 2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], {OPCODE_LOAD}}; + end + + 3'b110: begin + // c.sw -> sw rs2', imm(rs1') + instr_o = {5'b0, instr_i[5], instr_i[12], 2'b01, instr_i[4:2], + 2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6], + 2'b00, {OPCODE_STORE}}; + end + + 3'b001, + 3'b011, + 3'b100, + 3'b101, + 3'b111: begin + illegal_instr_o = 1'b1; + end + + default: begin + illegal_instr_o = 1'b1; + end + endcase + end + + // C1 + // + // Register address checks for RV32E are performed in the regular instruction decoder. + // If this check fails, an illegal instruction exception is triggered and the controller + // writes the actual faulting instruction to mtval. + 2'b01: begin + unique case (instr_i[15:13]) + 3'b000: begin + // c.addi -> addi rd, rd, nzimm + // c.nop + instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], + instr_i[11:7], 3'b0, instr_i[11:7], {OPCODE_OP_IMM}}; + end + + 3'b001, 3'b101: begin + // 001: c.jal -> jal x1, imm + // 101: c.j -> jal x0, imm + instr_o = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6], + instr_i[7], instr_i[2], instr_i[11], instr_i[5:3], + {9 {instr_i[12]}}, 4'b0, ~instr_i[15], {OPCODE_JAL}}; + end + + 3'b010: begin + // c.li -> addi rd, x0, nzimm + // (c.li hints are translated into an addi hint) + instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b0, + 3'b0, instr_i[11:7], {OPCODE_OP_IMM}}; + end + + 3'b011: begin + // c.lui -> lui rd, imm + // (c.lui hints are translated into a lui hint) + instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], {OPCODE_LUI}}; + + if (instr_i[11:7] == 5'h02) begin + // c.addi16sp -> addi x2, x2, nzimm + instr_o = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2], + instr_i[6], 4'b0, 5'h02, 3'b000, 5'h02, {OPCODE_OP_IMM}}; + end + + if ({instr_i[12], instr_i[6:2]} == 6'b0) illegal_instr_o = 1'b1; + end + + 3'b100: begin + unique case (instr_i[11:10]) + 2'b00, + 2'b01: begin + // 00: c.srli -> srli rd, rd, shamt + // 01: c.srai -> srai rd, rd, shamt + // (c.srli/c.srai hints are translated into a srli/srai hint) + instr_o = {1'b0, instr_i[10], 5'b0, instr_i[6:2], 2'b01, instr_i[9:7], + 3'b101, 2'b01, instr_i[9:7], {OPCODE_OP_IMM}}; + if (instr_i[12] == 1'b1) illegal_instr_o = 1'b1; + end + + 2'b10: begin + // c.andi -> andi rd, rd, imm + instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 2'b01, instr_i[9:7], + 3'b111, 2'b01, instr_i[9:7], {OPCODE_OP_IMM}}; + end + + 2'b11: begin + unique case ({instr_i[12], instr_i[6:5]}) + 3'b000: begin + // c.sub -> sub rd', rd', rs2' + instr_o = {2'b01, 5'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], + 3'b000, 2'b01, instr_i[9:7], {OPCODE_OP}}; + end + + 3'b001: begin + // c.xor -> xor rd', rd', rs2' + instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b100, + 2'b01, instr_i[9:7], {OPCODE_OP}}; + end + + 3'b010: begin + // c.or -> or rd', rd', rs2' + instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b110, + 2'b01, instr_i[9:7], {OPCODE_OP}}; + end + + 3'b011: begin + // c.and -> and rd', rd', rs2' + instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b111, + 2'b01, instr_i[9:7], {OPCODE_OP}}; + end + + 3'b100, + 3'b101, + 3'b110, + 3'b111: begin + // 100: c.subw + // 101: c.addw + illegal_instr_o = 1'b1; + end + + default: begin + illegal_instr_o = 1'b1; + end + endcase + end + + default: begin + illegal_instr_o = 1'b1; + end + endcase + end + + 3'b110, 3'b111: begin + // 0: c.beqz -> beq rs1', x0, imm + // 1: c.bnez -> bne rs1', x0, imm + instr_o = {{4 {instr_i[12]}}, instr_i[6:5], instr_i[2], 5'b0, 2'b01, + instr_i[9:7], 2'b00, instr_i[13], instr_i[11:10], instr_i[4:3], + instr_i[12], {OPCODE_BRANCH}}; + end + + default: begin + illegal_instr_o = 1'b1; + end + endcase + end + + // C2 + // + // Register address checks for RV32E are performed in the regular instruction decoder. + // If this check fails, an illegal instruction exception is triggered and the controller + // writes the actual faulting instruction to mtval. + 2'b10: begin + unique case (instr_i[15:13]) + 3'b000: begin + // c.slli -> slli rd, rd, shamt + // (c.ssli hints are translated into a slli hint) + instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b001, instr_i[11:7], {OPCODE_OP_IMM}}; + if (instr_i[12] == 1'b1) illegal_instr_o = 1'b1; // reserved for custom extensions + end + + 3'b010: begin + // c.lwsp -> lw rd, imm(x2) + instr_o = {4'b0, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02, + 3'b010, instr_i[11:7], OPCODE_LOAD}; + if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1; + end + + 3'b100: begin + if (instr_i[12] == 1'b0) begin + if (instr_i[6:2] != 5'b0) begin + // c.mv -> add rd/rs1, x0, rs2 + // (c.mv hints are translated into an add hint) + instr_o = {7'b0, instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], {OPCODE_OP}}; + end else begin + // c.jr -> jalr x0, rd/rs1, 0 + instr_o = {12'b0, instr_i[11:7], 3'b0, 5'b0, {OPCODE_JALR}}; + if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1; + end + end else begin + if (instr_i[6:2] != 5'b0) begin + // c.add -> add rd, rd, rs2 + // (c.add hints are translated into an add hint) + instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], {OPCODE_OP}}; + end else begin + if (instr_i[11:7] == 5'b0) begin + // c.ebreak -> ebreak + instr_o = {32'h00_10_00_73}; + end else begin + // c.jalr -> jalr x1, rs1, 0 + instr_o = {12'b0, instr_i[11:7], 3'b000, 5'b00001, {OPCODE_JALR}}; + end + end + end + end + + 3'b110: begin + // c.swsp -> sw rs2, imm(x2) + instr_o = {4'b0, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010, + instr_i[11:9], 2'b00, {OPCODE_STORE}}; + end + + 3'b001, + 3'b011, + 3'b101, + 3'b111: begin + illegal_instr_o = 1'b1; + end + + default: begin + illegal_instr_o = 1'b1; + end + endcase + end + + // Incoming instruction is not compressed. + 2'b11:; + + default: begin + illegal_instr_o = 1'b1; + end + endcase + end + + assign is_compressed_o = (instr_i[1:0] != 2'b11); + + //////////////// + // Assertions // + //////////////// + + // Selectors must be known/valid. + `ASSERT(IbexInstrLSBsKnown, valid_i |-> + !$isunknown(instr_i[1:0])) + `ASSERT(IbexC0Known1, (valid_i && (instr_i[1:0] == 2'b00)) |-> + !$isunknown(instr_i[15:13])) + `ASSERT(IbexC1Known1, (valid_i && (instr_i[1:0] == 2'b01)) |-> + !$isunknown(instr_i[15:13])) + `ASSERT(IbexC1Known2, (valid_i && (instr_i[1:0] == 2'b01) && (instr_i[15:13] == 3'b100)) |-> + !$isunknown(instr_i[11:10])) + `ASSERT(IbexC1Known3, (valid_i && + (instr_i[1:0] == 2'b01) && (instr_i[15:13] == 3'b100) && (instr_i[11:10] == 2'b11)) |-> + !$isunknown({instr_i[12], instr_i[6:5]})) + `ASSERT(IbexC2Known1, (valid_i && (instr_i[1:0] == 2'b10)) |-> + !$isunknown(instr_i[15:13])) + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_controller.sv b/flow/designs/src/ibex_sv/ibex_controller.sv new file mode 100644 index 0000000000..b59833d5b6 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_controller.sv @@ -0,0 +1,846 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Main controller of the processor + */ + +`include "prim_assert.sv" + +module ibex_controller #( + parameter bit WritebackStage = 0, + parameter bit BranchPredictor = 0 + ) ( + input logic clk_i, + input logic rst_ni, + + output logic ctrl_busy_o, // core is busy processing instrs + + // decoder related signals + input logic illegal_insn_i, // decoder has an invalid instr + input logic ecall_insn_i, // decoder has ECALL instr + input logic mret_insn_i, // decoder has MRET instr + input logic dret_insn_i, // decoder has DRET instr + input logic wfi_insn_i, // decoder has WFI instr + input logic ebrk_insn_i, // decoder has EBREAK instr + input logic csr_pipe_flush_i, // do CSR-related pipeline flush + + // instr from IF-ID pipeline stage + input logic instr_valid_i, // instr is valid + input logic [31:0] instr_i, // uncompressed instr data for mtval + input logic [15:0] instr_compressed_i, // instr compressed data for mtval + input logic instr_is_compressed_i, // instr is compressed + input logic instr_bp_taken_i, // instr was predicted taken branch + input logic instr_fetch_err_i, // instr has error + input logic instr_fetch_err_plus2_i, // instr error is x32 + input logic [31:0] pc_id_i, // instr address + + // to IF-ID pipeline stage + output logic instr_valid_clear_o, // kill instr in IF-ID reg + output logic id_in_ready_o, // ID stage is ready for new instr + output logic controller_run_o, // Controller is in standard instruction + // run mode + + // to prefetcher + output logic instr_req_o, // start fetching instructions + output logic pc_set_o, // jump to address set by pc_mux + output logic pc_set_spec_o, // speculative branch + output ibex_pkg::pc_sel_e pc_mux_o, // IF stage fetch address selector + // (boot, normal, exception...) + output logic nt_branch_mispredict_o, // Not-taken branch in ID/EX was + // mispredicted (predicted taken) + output ibex_pkg::exc_pc_sel_e exc_pc_mux_o, // IF stage selector for exception PC + output ibex_pkg::exc_cause_e exc_cause_o, // for IF stage, CSRs + + // LSU + input logic [31:0] lsu_addr_last_i, // for mtval + input logic load_err_i, + input logic store_err_i, + output logic wb_exception_o, // Instruction in WB taking an exception + + // jump/branch signals + input logic branch_set_i, // branch set signal (branch definitely + // taken) + input logic branch_set_spec_i, // speculative branch signal (branch + // may be taken) + input logic branch_not_set_i, // branch is definitely not taken + input logic jump_set_i, // jump taken set signal + + // interrupt signals + input logic csr_mstatus_mie_i, // M-mode interrupt enable bit + input logic irq_pending_i, // interrupt request pending + input ibex_pkg::irqs_t irqs_i, // interrupt requests qualified with + // mie CSR + input logic irq_nm_i, // non-maskeable interrupt + output logic nmi_mode_o, // core executing NMI handler + + // debug signals + input logic debug_req_i, + output ibex_pkg::dbg_cause_e debug_cause_o, + output logic debug_csr_save_o, + output logic debug_mode_o, + input logic debug_single_step_i, + input logic debug_ebreakm_i, + input logic debug_ebreaku_i, + input logic trigger_match_i, + + output logic csr_save_if_o, + output logic csr_save_id_o, + output logic csr_save_wb_o, + output logic csr_restore_mret_id_o, + output logic csr_restore_dret_id_o, + output logic csr_save_cause_o, + output logic [31:0] csr_mtval_o, + input ibex_pkg::priv_lvl_e priv_mode_i, + input logic csr_mstatus_tw_i, + + // stall & flush signals + input logic stall_id_i, + input logic stall_wb_i, + output logic flush_id_o, + input logic ready_wb_i, + + // performance monitors + output logic perf_jump_o, // we are executing a jump + // instruction (j, jr, jal, jalr) + output logic perf_tbranch_o // we are executing a taken branch + // instruction +); + import ibex_pkg::*; + + // FSM state encoding + typedef enum logic [3:0] { + RESET, BOOT_SET, WAIT_SLEEP, SLEEP, FIRST_FETCH, DECODE, FLUSH, + IRQ_TAKEN, DBG_TAKEN_IF, DBG_TAKEN_ID + } ctrl_fsm_e; + + ctrl_fsm_e ctrl_fsm_cs, ctrl_fsm_ns; + + logic nmi_mode_q, nmi_mode_d; + logic debug_mode_q, debug_mode_d; + logic load_err_q, load_err_d; + logic store_err_q, store_err_d; + logic exc_req_q, exc_req_d; + logic illegal_insn_q, illegal_insn_d; + + // Of the various exception/fault signals, which one takes priority in FLUSH and hence controls + // what happens next (setting exc_cause, csr_mtval etc) + logic instr_fetch_err_prio; + logic illegal_insn_prio; + logic ecall_insn_prio; + logic ebrk_insn_prio; + logic store_err_prio; + logic load_err_prio; + + logic stall; + logic halt_if; + logic retain_id; + logic flush_id; + logic illegal_dret; + logic illegal_umode; + logic exc_req_lsu; + logic special_req_all; + logic special_req_branch; + logic enter_debug_mode; + logic ebreak_into_debug; + logic handle_irq; + + logic [3:0] mfip_id; + logic unused_irq_timer; + + logic ecall_insn; + logic mret_insn; + logic dret_insn; + logic wfi_insn; + logic ebrk_insn; + logic csr_pipe_flush; + logic instr_fetch_err; + +`ifndef SYNTHESIS + // synopsys translate_off + // make sure we are called later so that we do not generate messages for + // glitches + always_ff @(negedge clk_i) begin + // print warning in case of decoding errors + if ((ctrl_fsm_cs == DECODE) && instr_valid_i && !instr_fetch_err_i && illegal_insn_d) begin + $display("%t: Illegal instruction (hart %0x) at PC 0x%h: 0x%h", $time, ibex_core.hart_id_i, + ibex_id_stage.pc_id_i, ibex_id_stage.instr_rdata_i); + end + end + // synopsys translate_on +`endif + + //////////////// + // Exceptions // + //////////////// + + assign load_err_d = load_err_i; + assign store_err_d = store_err_i; + + // Decoder doesn't take instr_valid into account, factor it in here. + assign ecall_insn = ecall_insn_i & instr_valid_i; + assign mret_insn = mret_insn_i & instr_valid_i; + assign dret_insn = dret_insn_i & instr_valid_i; + assign wfi_insn = wfi_insn_i & instr_valid_i; + assign ebrk_insn = ebrk_insn_i & instr_valid_i; + assign csr_pipe_flush = csr_pipe_flush_i & instr_valid_i; + assign instr_fetch_err = instr_fetch_err_i & instr_valid_i; + + // "Executing DRET outside of Debug Mode causes an illegal instruction exception." + // [Debug Spec v0.13.2, p.41] + assign illegal_dret = dret_insn & ~debug_mode_q; + + // Some instructions can only be executed in M-Mode + assign illegal_umode = (priv_mode_i != PRIV_LVL_M) & + // MRET must be in M-Mode. TW means trap WFI to M-Mode. + (mret_insn | (csr_mstatus_tw_i & wfi_insn)); + + // This is recorded in the illegal_insn_q flop to help timing. Specifically + // it is needed to break the path from ibex_cs_registers/illegal_csr_insn_o + // to pc_set_o. Clear when controller is in FLUSH so it won't remain set + // once illegal instruction is handled. + // All terms in this expression are qualified by instr_valid_i + assign illegal_insn_d = (illegal_insn_i | illegal_dret | illegal_umode) & (ctrl_fsm_cs != FLUSH); + + // exception requests + // requests are flopped in exc_req_q. This is cleared when controller is in + // the FLUSH state so the cycle following exc_req_q won't remain set for an + // exception request that has just been handled. + // All terms in this expression are qualified by instr_valid_i + assign exc_req_d = (ecall_insn | ebrk_insn | illegal_insn_d | instr_fetch_err) & + (ctrl_fsm_cs != FLUSH); + + // LSU exception requests + assign exc_req_lsu = store_err_i | load_err_i; + + + // special requests: special instructions, pipeline flushes, exceptions... + + // To avoid creating a path from data_err_i -> instr_req_o and to help timing the below + // special_req_all has a version that only applies to branches. For a branch the controller needs + // to set pc_set_o but only if there is no special request. If the generic special_req_all signal + // is used then a variety of signals that will never cause a special request during a branch + // instruction end up factored into pc_set_o. The special_req_branch only considers the special + // request reasons that are relevant to a branch. + + // generic special request signal, applies to all instructions + // All terms in this expression are qualified by instr_valid_i except exc_req_lsu which can come + // from the Writeback stage with no instr_valid_i from the ID stage + assign special_req_all = mret_insn | dret_insn | wfi_insn | csr_pipe_flush | + exc_req_d | exc_req_lsu; + + // special request that can specifically occur during branch instructions + // All terms in this expression are qualified by instr_valid_i + assign special_req_branch = instr_fetch_err & (ctrl_fsm_cs != FLUSH); + + `ASSERT(SpecialReqBranchGivesSpecialReqAll, + special_req_branch |-> special_req_all) + + `ASSERT(SpecialReqAllGivesSpecialReqBranchIfBranchInst, + special_req_all && (branch_set_i || jump_set_i) |-> special_req_branch) + + // Exception/fault prioritisation is taken from Table 3.7 of Priviledged Spec v1.11 + if (WritebackStage) begin : g_wb_exceptions + always_comb begin + instr_fetch_err_prio = 0; + illegal_insn_prio = 0; + ecall_insn_prio = 0; + ebrk_insn_prio = 0; + store_err_prio = 0; + load_err_prio = 0; + + // Note that with the writeback stage store/load errors occur on the instruction in writeback, + // all other exception/faults occur on the instruction in ID/EX. The faults from writeback + // must take priority as that instruction is architecurally ordered before the one in ID/EX. + if (store_err_q) begin + store_err_prio = 1'b1; + end else if (load_err_q) begin + load_err_prio = 1'b1; + end else if (instr_fetch_err) begin + instr_fetch_err_prio = 1'b1; + end else if (illegal_insn_q) begin + illegal_insn_prio = 1'b1; + end else if (ecall_insn) begin + ecall_insn_prio = 1'b1; + end else if (ebrk_insn) begin + ebrk_insn_prio = 1'b1; + end + end + + // Instruction in writeback is generating an exception so instruction in ID must not execute + assign wb_exception_o = load_err_q | store_err_q | load_err_i | store_err_i; + end else begin : g_no_wb_exceptions + always_comb begin + instr_fetch_err_prio = 0; + illegal_insn_prio = 0; + ecall_insn_prio = 0; + ebrk_insn_prio = 0; + store_err_prio = 0; + load_err_prio = 0; + + if (instr_fetch_err) begin + instr_fetch_err_prio = 1'b1; + end else if (illegal_insn_q) begin + illegal_insn_prio = 1'b1; + end else if (ecall_insn) begin + ecall_insn_prio = 1'b1; + end else if (ebrk_insn) begin + ebrk_insn_prio = 1'b1; + end else if (store_err_q) begin + store_err_prio = 1'b1; + end else if (load_err_q) begin + load_err_prio = 1'b1; + end + end + assign wb_exception_o = 1'b0; + end + + `ASSERT_IF(IbexExceptionPrioOnehot, + $onehot({instr_fetch_err_prio, + illegal_insn_prio, + ecall_insn_prio, + ebrk_insn_prio, + store_err_prio, + load_err_prio}), + (ctrl_fsm_cs == FLUSH) & exc_req_q) + + //////////////// + // Interrupts // + //////////////// + + // Enter debug mode due to an external debug_req_i or because the core is in + // single step mode (dcsr.step == 1). Single step must be qualified with + // instruction valid otherwise the core will immediately enter debug mode + // due to a recently flushed IF (or a delay in an instruction returning from + // memory) before it has had anything to single step. + // Also enter debug mode on a trigger match (hardware breakpoint) + assign enter_debug_mode = (debug_req_i | (debug_single_step_i & instr_valid_i) | + trigger_match_i) & ~debug_mode_q; + + // Set when an ebreak should enter debug mode rather than jump to exception + // handler + assign ebreak_into_debug = priv_mode_i == PRIV_LVL_M ? debug_ebreakm_i : + priv_mode_i == PRIV_LVL_U ? debug_ebreaku_i : + 1'b0; + + // Interrupts including NMI are ignored, + // - while in debug mode [Debug Spec v0.13.2, p.39], + // - while in NMI mode (nested NMIs are not supported, NMI has highest priority and + // cannot be interrupted by regular interrupts). + assign handle_irq = ~debug_mode_q & ~nmi_mode_q & + (irq_nm_i | (irq_pending_i & csr_mstatus_mie_i)); + + // generate ID of fast interrupts, highest priority to highest ID + always_comb begin : gen_mfip_id + if (irqs_i.irq_fast[14]) mfip_id = 4'd14; + else if (irqs_i.irq_fast[13]) mfip_id = 4'd13; + else if (irqs_i.irq_fast[12]) mfip_id = 4'd12; + else if (irqs_i.irq_fast[11]) mfip_id = 4'd11; + else if (irqs_i.irq_fast[10]) mfip_id = 4'd10; + else if (irqs_i.irq_fast[ 9]) mfip_id = 4'd9; + else if (irqs_i.irq_fast[ 8]) mfip_id = 4'd8; + else if (irqs_i.irq_fast[ 7]) mfip_id = 4'd7; + else if (irqs_i.irq_fast[ 6]) mfip_id = 4'd6; + else if (irqs_i.irq_fast[ 5]) mfip_id = 4'd5; + else if (irqs_i.irq_fast[ 4]) mfip_id = 4'd4; + else if (irqs_i.irq_fast[ 3]) mfip_id = 4'd3; + else if (irqs_i.irq_fast[ 2]) mfip_id = 4'd2; + else if (irqs_i.irq_fast[ 1]) mfip_id = 4'd1; + else mfip_id = 4'd0; + end + + assign unused_irq_timer = irqs_i.irq_timer; + + ///////////////////// + // Core controller // + ///////////////////// + + always_comb begin + // Default values + instr_req_o = 1'b1; + + csr_save_if_o = 1'b0; + csr_save_id_o = 1'b0; + csr_save_wb_o = 1'b0; + csr_restore_mret_id_o = 1'b0; + csr_restore_dret_id_o = 1'b0; + csr_save_cause_o = 1'b0; + csr_mtval_o = '0; + + // The values of pc_mux and exc_pc_mux are only relevant if pc_set is set. Some of the states + // below always set pc_mux and exc_pc_mux but only set pc_set if certain conditions are met. + // This avoid having to factor those conditions into the pc_mux and exc_pc_mux select signals + // helping timing. + pc_mux_o = PC_BOOT; + pc_set_o = 1'b0; + pc_set_spec_o = 1'b0; + nt_branch_mispredict_o = 1'b0; + + exc_pc_mux_o = EXC_PC_IRQ; + exc_cause_o = EXC_CAUSE_INSN_ADDR_MISA; // = 6'h00 + + ctrl_fsm_ns = ctrl_fsm_cs; + + ctrl_busy_o = 1'b1; + + halt_if = 1'b0; + retain_id = 1'b0; + flush_id = 1'b0; + + debug_csr_save_o = 1'b0; + debug_cause_o = DBG_CAUSE_EBREAK; + debug_mode_d = debug_mode_q; + nmi_mode_d = nmi_mode_q; + + perf_tbranch_o = 1'b0; + perf_jump_o = 1'b0; + + controller_run_o = 1'b0; + + unique case (ctrl_fsm_cs) + RESET: begin + instr_req_o = 1'b0; + pc_mux_o = PC_BOOT; + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + ctrl_fsm_ns = BOOT_SET; + end + + BOOT_SET: begin + // copy boot address to instr fetch address + instr_req_o = 1'b1; + pc_mux_o = PC_BOOT; + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + + ctrl_fsm_ns = FIRST_FETCH; + end + + WAIT_SLEEP: begin + ctrl_busy_o = 1'b0; + instr_req_o = 1'b0; + halt_if = 1'b1; + flush_id = 1'b1; + ctrl_fsm_ns = SLEEP; + end + + SLEEP: begin + // instruction in IF stage is already valid + // we begin execution when an interrupt has arrived + instr_req_o = 1'b0; + halt_if = 1'b1; + flush_id = 1'b1; + + // normal execution flow + // in debug mode or single step mode we leave immediately (wfi=nop) + if (irq_nm_i || irq_pending_i || debug_req_i || debug_mode_q || debug_single_step_i) begin + ctrl_fsm_ns = FIRST_FETCH; + end else begin + // Make sure clock remains disabled. + ctrl_busy_o = 1'b0; + end + end + + FIRST_FETCH: begin + // Stall because of IF miss + if (id_in_ready_o) begin + ctrl_fsm_ns = DECODE; + end + + // handle interrupts + if (handle_irq) begin + // We are handling an interrupt. Set halt_if to tell IF not to give + // us any more instructions before it redirects to the handler, but + // don't set flush_id: we must allow this instruction to complete + // (since it might have outstanding loads or stores). + ctrl_fsm_ns = IRQ_TAKEN; + halt_if = 1'b1; + end + + // enter debug mode + if (enter_debug_mode) begin + ctrl_fsm_ns = DBG_TAKEN_IF; + // Halt IF only for now, ID will be flushed in DBG_TAKEN_IF as the + // ID state is needed for correct debug mode entry + halt_if = 1'b1; + end + end + + DECODE: begin + // normal operating mode of the ID stage, in case of debug and interrupt requests, + // priorities are as follows (lower number == higher priority) + // 1. currently running (multicycle) instructions and exceptions caused by these + // 2. debug requests + // 3. interrupt requests + + controller_run_o = 1'b1; + + // Set PC mux for branch and jump here to ease timing. Value is only relevant if pc_set_o is + // also set. Setting the mux value here avoids factoring in special_req and instr_valid_i + // which helps timing. + pc_mux_o = PC_JUMP; + + + // Get ready for special instructions, exceptions, pipeline flushes + if (special_req_all) begin + // Halt IF but don't flush ID. This leaves a valid instruction in + // ID so controller can determine appropriate action in the + // FLUSH state. + retain_id = 1'b1; + + // Wait for the writeback stage to either be ready for a new instruction or raise its own + // exception before going to FLUSH. If the instruction in writeback raises an exception it + // must take priority over any exception from an instruction in ID/EX. Only once the + // writeback stage is ready can we be certain that won't happen. Without a writeback + // stage ready_wb_i == 1 so the FSM will always go directly to FLUSH. + + if (ready_wb_i | wb_exception_o) begin + ctrl_fsm_ns = FLUSH; + end + end + + if (!special_req_branch) begin + if (branch_set_i || jump_set_i) begin + // Only set the PC if the branch predictor hasn't already done the branch for us + pc_set_o = BranchPredictor ? ~instr_bp_taken_i : 1'b1; + + perf_tbranch_o = branch_set_i; + perf_jump_o = jump_set_i; + end + + if (BranchPredictor) begin + if (instr_bp_taken_i & branch_not_set_i) begin + // If the instruction is a branch that was predicted to be taken but was not taken + // signal a mispredict. + nt_branch_mispredict_o = 1'b1; + end + end + end + + // pc_set signal excluding branch taken condition + if ((branch_set_spec_i || jump_set_i) && !special_req_branch) begin + // Only speculatively set the PC if the branch predictor hasn't already done the branch + // for us + pc_set_spec_o = BranchPredictor ? ~instr_bp_taken_i : 1'b1; + end + + // If entering debug mode or handling an IRQ the core needs to wait + // until the current instruction has finished executing. Stall IF + // during that time. + if ((enter_debug_mode || handle_irq) && stall) begin + halt_if = 1'b1; + end + + if (!stall && !special_req_all) begin + if (enter_debug_mode) begin + // enter debug mode + ctrl_fsm_ns = DBG_TAKEN_IF; + // Halt IF only for now, ID will be flushed in DBG_TAKEN_IF as the + // ID state is needed for correct debug mode entry + halt_if = 1'b1; + end else if (handle_irq) begin + // handle interrupt (not in debug mode) + ctrl_fsm_ns = IRQ_TAKEN; + // We are handling an interrupt (not in debug mode). Set halt_if to + // tell IF not to give us any more instructions before it redirects + // to the handler, but don't set flush_id: we must allow this + // instruction to complete (since it might have outstanding loads + // or stores). + halt_if = 1'b1; + end + end + + end // DECODE + + IRQ_TAKEN: begin + pc_mux_o = PC_EXC; + exc_pc_mux_o = EXC_PC_IRQ; + + if (handle_irq) begin + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + + csr_save_if_o = 1'b1; + csr_save_cause_o = 1'b1; + + // interrupt priorities according to Privileged Spec v1.11 p.31 + if (irq_nm_i && !nmi_mode_q) begin + exc_cause_o = EXC_CAUSE_IRQ_NM; + nmi_mode_d = 1'b1; // enter NMI mode + end else if (irqs_i.irq_fast != 15'b0) begin + // generate exception cause ID from fast interrupt ID: + // - first bit distinguishes interrupts from exceptions, + // - second bit adds 16 to fast interrupt ID + // for example EXC_CAUSE_IRQ_FAST_0 = {1'b1, 5'd16} + exc_cause_o = exc_cause_e'({2'b11, mfip_id}); + end else if (irqs_i.irq_external) begin + exc_cause_o = EXC_CAUSE_IRQ_EXTERNAL_M; + end else if (irqs_i.irq_software) begin + exc_cause_o = EXC_CAUSE_IRQ_SOFTWARE_M; + end else begin // irqs_i.irq_timer + exc_cause_o = EXC_CAUSE_IRQ_TIMER_M; + end + end + + ctrl_fsm_ns = DECODE; + end + + DBG_TAKEN_IF: begin + pc_mux_o = PC_EXC; + exc_pc_mux_o = EXC_PC_DBD; + + // enter debug mode and save PC in IF to dpc + // jump to debug exception handler in debug memory + if (debug_single_step_i || debug_req_i || trigger_match_i) begin + flush_id = 1'b1; + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + + csr_save_if_o = 1'b1; + debug_csr_save_o = 1'b1; + + csr_save_cause_o = 1'b1; + if (trigger_match_i) begin + debug_cause_o = DBG_CAUSE_TRIGGER; + end else if (debug_single_step_i) begin + debug_cause_o = DBG_CAUSE_STEP; + end else begin + debug_cause_o = DBG_CAUSE_HALTREQ; + end + + // enter debug mode + debug_mode_d = 1'b1; + end + + ctrl_fsm_ns = DECODE; + end + + DBG_TAKEN_ID: begin + // enter debug mode and save PC in ID to dpc, used when encountering + // 1. EBREAK during debug mode + // 2. EBREAK with forced entry into debug mode (ebreakm or ebreaku set). + // regular ebreak's go through FLUSH. + // + // for 1. do not update dcsr and dpc, for 2. do so [Debug Spec v0.13.2, p.39] + // jump to debug exception handler in debug memory + flush_id = 1'b1; + pc_mux_o = PC_EXC; + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + exc_pc_mux_o = EXC_PC_DBD; + + // update dcsr and dpc + if (ebreak_into_debug && !debug_mode_q) begin // ebreak with forced entry + + // dpc (set to the address of the EBREAK, i.e. set to PC in ID stage) + csr_save_cause_o = 1'b1; + csr_save_id_o = 1'b1; + + // dcsr + debug_csr_save_o = 1'b1; + debug_cause_o = DBG_CAUSE_EBREAK; + end + + // enter debug mode + debug_mode_d = 1'b1; + + ctrl_fsm_ns = DECODE; + end + + FLUSH: begin + // flush the pipeline + halt_if = 1'b1; + flush_id = 1'b1; + ctrl_fsm_ns = DECODE; + + // As pc_mux and exc_pc_mux can take various values in this state they aren't set early + // here. + + // exceptions: set exception PC, save PC and exception cause + // exc_req_lsu is high for one clock cycle only (in DECODE) + if (exc_req_q || store_err_q || load_err_q) begin + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + pc_mux_o = PC_EXC; + exc_pc_mux_o = debug_mode_q ? EXC_PC_DBG_EXC : EXC_PC_EXC; + + if (WritebackStage) begin : g_writeback_mepc_save + // With the writeback stage present whether an instruction accessing memory will cause + // an exception is only known when it is in writeback. So when taking such an exception + // epc must come from writeback. + csr_save_id_o = ~(store_err_q | load_err_q); + csr_save_wb_o = store_err_q | load_err_q; + end else begin : g_no_writeback_mepc_save + csr_save_id_o = 1'b0; + end + + csr_save_cause_o = 1'b1; + + // Exception/fault prioritisation logic will have set exactly 1 X_prio signal + unique case (1'b1) + instr_fetch_err_prio: begin + exc_cause_o = EXC_CAUSE_INSTR_ACCESS_FAULT; + csr_mtval_o = instr_fetch_err_plus2_i ? (pc_id_i + 32'd2) : pc_id_i; + end + illegal_insn_prio: begin + exc_cause_o = EXC_CAUSE_ILLEGAL_INSN; + csr_mtval_o = instr_is_compressed_i ? {16'b0, instr_compressed_i} : instr_i; + end + ecall_insn_prio: begin + exc_cause_o = (priv_mode_i == PRIV_LVL_M) ? EXC_CAUSE_ECALL_MMODE : + EXC_CAUSE_ECALL_UMODE; + end + ebrk_insn_prio: begin + if (debug_mode_q | ebreak_into_debug) begin + /* + * EBREAK in debug mode re-enters debug mode + * + * "The only exception is EBREAK. When that is executed in Debug + * Mode, it halts the hart again but without updating dpc or + * dcsr." [Debug Spec v0.13.2, p.39] + */ + + /* + * dcsr.ebreakm == 1: + * "EBREAK instructions in M-mode enter Debug Mode." + * [Debug Spec v0.13.2, p.42] + */ + pc_set_o = 1'b0; + pc_set_spec_o = 1'b0; + csr_save_id_o = 1'b0; + csr_save_cause_o = 1'b0; + ctrl_fsm_ns = DBG_TAKEN_ID; + flush_id = 1'b0; + end else begin + /* + * "The EBREAK instruction is used by debuggers to cause control + * to be transferred back to a debugging environment. It + * generates a breakpoint exception and performs no other + * operation. [...] ECALL and EBREAK cause the receiving + * privilege mode's epc register to be set to the address of the + * ECALL or EBREAK instruction itself, not the address of the + * following instruction." [Privileged Spec v1.11, p.40] + */ + exc_cause_o = EXC_CAUSE_BREAKPOINT; + end + end + store_err_prio: begin + exc_cause_o = EXC_CAUSE_STORE_ACCESS_FAULT; + csr_mtval_o = lsu_addr_last_i; + end + load_err_prio: begin + exc_cause_o = EXC_CAUSE_LOAD_ACCESS_FAULT; + csr_mtval_o = lsu_addr_last_i; + end + default: ; + endcase + end else begin + // special instructions and pipeline flushes + if (mret_insn) begin + pc_mux_o = PC_ERET; + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + csr_restore_mret_id_o = 1'b1; + if (nmi_mode_q) begin + nmi_mode_d = 1'b0; // exit NMI mode + end + end else if (dret_insn) begin + pc_mux_o = PC_DRET; + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + debug_mode_d = 1'b0; + csr_restore_dret_id_o = 1'b1; + end else if (wfi_insn) begin + ctrl_fsm_ns = WAIT_SLEEP; + end else if (csr_pipe_flush && handle_irq) begin + // start handling IRQs when doing CSR-related pipeline flushes + ctrl_fsm_ns = IRQ_TAKEN; + end + end // exc_req_q + + // Entering debug mode due to either single step or debug_req. Ensure + // registers are set for exception but then enter debug handler rather + // than exception handler [Debug Spec v0.13.2, p.44] + // Leave all other signals as is to ensure CSRs and PC get set as if + // core was entering exception handler, entry to debug mode will then + // see the appropriate state and setup dpc correctly. + // If an EBREAK instruction is causing us to enter debug mode on the + // same cycle as a debug_req or single step, honor the EBREAK and + // proceed to DBG_TAKEN_ID. + if (enter_debug_mode && !(ebrk_insn_prio && ebreak_into_debug)) begin + ctrl_fsm_ns = DBG_TAKEN_IF; + end + end // FLUSH + + default: begin + instr_req_o = 1'b0; + ctrl_fsm_ns = RESET; + end + endcase + end + + assign flush_id_o = flush_id; + + // signal to CSR when in debug mode + assign debug_mode_o = debug_mode_q; + + // signal to CSR when in an NMI handler (for nested exception handling) + assign nmi_mode_o = nmi_mode_q; + + /////////////////// + // Stall control // + /////////////////// + + // If high current instruction cannot complete this cycle. Either because it needs more cycles to + // finish (stall_id_i) or because the writeback stage cannot accept it yet (stall_wb_i). If there + // is no writeback stage stall_wb_i is a constant 0. + assign stall = stall_id_i | stall_wb_i; + + // signal to IF stage that ID stage is ready for next instr + assign id_in_ready_o = ~stall & ~halt_if & ~retain_id; + + // kill instr in IF-ID pipeline reg that are done, or if a + // multicycle instr causes an exception for example + // retain_id is another kind of stall, where the instr_valid bit must remain + // set (unless flush_id is set also). It cannot be factored directly into + // stall as this causes a combinational loop. + assign instr_valid_clear_o = ~(stall | retain_id) | flush_id; + + // update registers + always_ff @(posedge clk_i or negedge rst_ni) begin : update_regs + if (!rst_ni) begin + ctrl_fsm_cs <= RESET; + nmi_mode_q <= 1'b0; + debug_mode_q <= 1'b0; + load_err_q <= 1'b0; + store_err_q <= 1'b0; + exc_req_q <= 1'b0; + illegal_insn_q <= 1'b0; + end else begin + ctrl_fsm_cs <= ctrl_fsm_ns; + nmi_mode_q <= nmi_mode_d; + debug_mode_q <= debug_mode_d; + load_err_q <= load_err_d; + store_err_q <= store_err_d; + exc_req_q <= exc_req_d; + illegal_insn_q <= illegal_insn_d; + end + end + + //////////////// + // Assertions // + //////////////// + + `ASSERT(AlwaysInstrClearOnMispredict, nt_branch_mispredict_o -> instr_valid_clear_o) + + // Selectors must be known/valid. + `ASSERT(IbexCtrlStateValid, ctrl_fsm_cs inside { + RESET, BOOT_SET, WAIT_SLEEP, SLEEP, FIRST_FETCH, DECODE, FLUSH, + IRQ_TAKEN, DBG_TAKEN_IF, DBG_TAKEN_ID}) + + // The speculative branch signal should be set whenever the actual branch signal is set + `ASSERT(IbexSpecImpliesSetPC, pc_set_o |-> pc_set_spec_o) + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_core.sv b/flow/designs/src/ibex_sv/ibex_core.sv new file mode 100644 index 0000000000..ff5ecef864 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_core.sv @@ -0,0 +1,1457 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`ifdef RISCV_FORMAL + `define RVFI +`endif + +`include "prim_assert.sv" + +/** + * Top level module of the ibex RISC-V core + */ +module ibex_core #( + parameter bit PMPEnable = 1'b0, + parameter int unsigned PMPGranularity = 0, + parameter int unsigned PMPNumRegions = 4, + parameter int unsigned MHPMCounterNum = 0, + parameter int unsigned MHPMCounterWidth = 40, + parameter bit RV32E = 1'b0, + parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast, + parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone, + parameter ibex_pkg::regfile_e RegFile = ibex_pkg::RegFileFF, + parameter bit BranchTargetALU = 1'b0, + parameter bit WritebackStage = 1'b0, + parameter bit ICache = 1'b0, + parameter bit ICacheECC = 1'b0, + parameter bit BranchPredictor = 1'b0, + parameter bit DbgTriggerEn = 1'b0, + parameter int unsigned DbgHwBreakNum = 1, + parameter bit SecureIbex = 1'b0, + parameter int unsigned DmHaltAddr = 32'h1A110800, + parameter int unsigned DmExceptionAddr = 32'h1A110808 +) ( + // Clock and Reset + input logic clk_i, + input logic rst_ni, + + input logic test_en_i, // enable all clock gates for testing + + input logic [31:0] hart_id_i, + input logic [31:0] boot_addr_i, + + // Instruction memory interface + output logic instr_req_o, + input logic instr_gnt_i, + input logic instr_rvalid_i, + output logic [31:0] instr_addr_o, + input logic [31:0] instr_rdata_i, + input logic instr_err_i, + + // Data memory interface + output logic data_req_o, + input logic data_gnt_i, + input logic data_rvalid_i, + output logic data_we_o, + output logic [3:0] data_be_o, + output logic [31:0] data_addr_o, + output logic [31:0] data_wdata_o, + input logic [31:0] data_rdata_i, + input logic data_err_i, + + // Interrupt inputs + input logic irq_software_i, + input logic irq_timer_i, + input logic irq_external_i, + input logic [14:0] irq_fast_i, + input logic irq_nm_i, // non-maskeable interrupt + + // Debug Interface + input logic debug_req_i, + + // RISC-V Formal Interface + // Does not comply with the coding standards of _i/_o suffixes, but follows + // the convention of RISC-V Formal Interface Specification. +`ifdef RVFI + output logic rvfi_valid, + output logic [63:0] rvfi_order, + output logic [31:0] rvfi_insn, + output logic rvfi_trap, + output logic rvfi_halt, + output logic rvfi_intr, + output logic [ 1:0] rvfi_mode, + output logic [ 1:0] rvfi_ixl, + output logic [ 4:0] rvfi_rs1_addr, + output logic [ 4:0] rvfi_rs2_addr, + output logic [ 4:0] rvfi_rs3_addr, + output logic [31:0] rvfi_rs1_rdata, + output logic [31:0] rvfi_rs2_rdata, + output logic [31:0] rvfi_rs3_rdata, + output logic [ 4:0] rvfi_rd_addr, + output logic [31:0] rvfi_rd_wdata, + output logic [31:0] rvfi_pc_rdata, + output logic [31:0] rvfi_pc_wdata, + output logic [31:0] rvfi_mem_addr, + output logic [ 3:0] rvfi_mem_rmask, + output logic [ 3:0] rvfi_mem_wmask, + output logic [31:0] rvfi_mem_rdata, + output logic [31:0] rvfi_mem_wdata, +`endif + + // CPU Control Signals + input logic fetch_enable_i, + output logic alert_minor_o, + output logic alert_major_o, + output logic core_sleep_o +); + + import ibex_pkg::*; + + localparam int unsigned PMP_NUM_CHAN = 2; + localparam bit DataIndTiming = SecureIbex; + localparam bit DummyInstructions = SecureIbex; + localparam bit PCIncrCheck = SecureIbex; + localparam bit ShadowCSR = SecureIbex; + // Speculative branch option, trades-off performance against timing. + // Setting this to 1 eases branch target critical paths significantly but reduces performance + // by ~3% (based on CoreMark/MHz score). + // Set by default in the max PMP config which has the tightest budget for branch target timing. + localparam bit SpecBranch = PMPEnable & (PMPNumRegions == 16); + localparam bit RegFileECC = SecureIbex; + localparam int unsigned RegFileDataWidth = RegFileECC ? 32 + 7 : 32; + + // IF/ID signals + logic dummy_instr_id; + logic instr_valid_id; + logic instr_new_id; + logic [31:0] instr_rdata_id; // Instruction sampled inside IF stage + logic [31:0] instr_rdata_alu_id; // Instruction sampled inside IF stage (replicated to + // ease fan-out) + logic [15:0] instr_rdata_c_id; // Compressed instruction sampled inside IF stage + logic instr_is_compressed_id; + logic instr_perf_count_id; + logic instr_bp_taken_id; + logic instr_fetch_err; // Bus error on instr fetch + logic instr_fetch_err_plus2; // Instruction error is misaligned + logic illegal_c_insn_id; // Illegal compressed instruction sent to ID stage + logic [31:0] pc_if; // Program counter in IF stage + logic [31:0] pc_id; // Program counter in ID stage + logic [31:0] pc_wb; // Program counter in WB stage + logic [33:0] imd_val_d_ex[2]; // Intermediate register for multicycle Ops + logic [33:0] imd_val_q_ex[2]; // Intermediate register for multicycle Ops + logic [1:0] imd_val_we_ex; + + logic data_ind_timing; + logic dummy_instr_en; + logic [2:0] dummy_instr_mask; + logic dummy_instr_seed_en; + logic [31:0] dummy_instr_seed; + logic icache_enable; + logic icache_inval; + logic pc_mismatch_alert; + logic csr_shadow_err; + + logic instr_first_cycle_id; + logic instr_valid_clear; + logic pc_set; + logic pc_set_spec; + logic nt_branch_mispredict; + pc_sel_e pc_mux_id; // Mux selector for next PC + exc_pc_sel_e exc_pc_mux_id; // Mux selector for exception PC + exc_cause_e exc_cause; // Exception cause + + logic lsu_load_err; + logic lsu_store_err; + + // LSU signals + logic lsu_addr_incr_req; + logic [31:0] lsu_addr_last; + + // Jump and branch target and decision (EX->IF) + logic [31:0] branch_target_ex; + logic branch_decision; + + // Core busy signals + logic ctrl_busy; + logic if_busy; + logic lsu_busy; + logic core_busy_d, core_busy_q; + + // Register File + logic [4:0] rf_raddr_a; + logic [31:0] rf_rdata_a; + logic [4:0] rf_raddr_b; + logic [31:0] rf_rdata_b; + logic rf_ren_a; + logic rf_ren_b; + logic [4:0] rf_waddr_wb; + logic [31:0] rf_wdata_wb; + // Writeback register write data that can be used on the forwarding path (doesn't factor in memory + // read data as this is too late for the forwarding path) + logic [31:0] rf_wdata_fwd_wb; + logic [31:0] rf_wdata_lsu; + logic rf_we_wb; + logic rf_we_lsu; + + logic [4:0] rf_waddr_id; + logic [31:0] rf_wdata_id; + logic rf_we_id; + logic rf_rd_a_wb_match; + logic rf_rd_b_wb_match; + + // ALU Control + alu_op_e alu_operator_ex; + logic [31:0] alu_operand_a_ex; + logic [31:0] alu_operand_b_ex; + + logic [31:0] bt_a_operand; + logic [31:0] bt_b_operand; + + logic [31:0] alu_adder_result_ex; // Used to forward computed address to LSU + logic [31:0] result_ex; + + // Multiplier Control + logic mult_en_ex; + logic div_en_ex; + logic mult_sel_ex; + logic div_sel_ex; + md_op_e multdiv_operator_ex; + logic [1:0] multdiv_signed_mode_ex; + logic [31:0] multdiv_operand_a_ex; + logic [31:0] multdiv_operand_b_ex; + logic multdiv_ready_id; + + // CSR control + logic csr_access; + csr_op_e csr_op; + logic csr_op_en; + csr_num_e csr_addr; + logic [31:0] csr_rdata; + logic [31:0] csr_wdata; + logic illegal_csr_insn_id; // CSR access to non-existent register, + // with wrong priviledge level, + // or missing write permissions + + // Data Memory Control + logic lsu_we; + logic [1:0] lsu_type; + logic lsu_sign_ext; + logic lsu_req; + logic [31:0] lsu_wdata; + logic lsu_req_done; + + // stall control + logic id_in_ready; + logic ex_valid; + + logic lsu_resp_valid; + logic lsu_resp_err; + + // Signals between instruction core interface and pipe (if and id stages) + logic instr_req_int; // Id stage asserts a req to instruction core interface + + // Writeback stage + logic en_wb; + wb_instr_type_e instr_type_wb; + logic ready_wb; + logic rf_write_wb; + logic outstanding_load_wb; + logic outstanding_store_wb; + + // Interrupts + logic irq_pending; + logic nmi_mode; + irqs_t irqs; + logic csr_mstatus_mie; + logic [31:0] csr_mepc, csr_depc; + + // PMP signals + logic [33:0] csr_pmp_addr [PMPNumRegions]; + pmp_cfg_t csr_pmp_cfg [PMPNumRegions]; + logic pmp_req_err [PMP_NUM_CHAN]; + logic instr_req_out; + logic data_req_out; + + logic csr_save_if; + logic csr_save_id; + logic csr_save_wb; + logic csr_restore_mret_id; + logic csr_restore_dret_id; + logic csr_save_cause; + logic csr_mtvec_init; + logic [31:0] csr_mtvec; + logic [31:0] csr_mtval; + logic csr_mstatus_tw; + priv_lvl_e priv_mode_id; + priv_lvl_e priv_mode_if; + priv_lvl_e priv_mode_lsu; + + // debug mode and dcsr configuration + logic debug_mode; + dbg_cause_e debug_cause; + logic debug_csr_save; + logic debug_single_step; + logic debug_ebreakm; + logic debug_ebreaku; + logic trigger_match; + + // signals relating to instruction movements between pipeline stages + // used by performance counters and RVFI + logic instr_id_done; + logic instr_done_wb; + + logic perf_instr_ret_wb; + logic perf_instr_ret_compressed_wb; + logic perf_iside_wait; + logic perf_dside_wait; + logic perf_mul_wait; + logic perf_div_wait; + logic perf_jump; + logic perf_branch; + logic perf_tbranch; + logic perf_load; + logic perf_store; + + // for RVFI + logic illegal_insn_id, unused_illegal_insn_id; // ID stage sees an illegal instruction + + // RISC-V Formal Interface signals +`ifdef RVFI + logic rvfi_instr_new_wb; + logic rvfi_intr_d; + logic rvfi_intr_q; + logic rvfi_set_trap_pc_d; + logic rvfi_set_trap_pc_q; + logic [31:0] rvfi_insn_id; + logic [4:0] rvfi_rs1_addr_d; + logic [4:0] rvfi_rs1_addr_q; + logic [4:0] rvfi_rs2_addr_d; + logic [4:0] rvfi_rs2_addr_q; + logic [4:0] rvfi_rs3_addr_d; + logic [31:0] rvfi_rs1_data_d; + logic [31:0] rvfi_rs1_data_q; + logic [31:0] rvfi_rs2_data_d; + logic [31:0] rvfi_rs2_data_q; + logic [31:0] rvfi_rs3_data_d; + logic [4:0] rvfi_rd_addr_wb; + logic [4:0] rvfi_rd_addr_q; + logic [4:0] rvfi_rd_addr_d; + logic [31:0] rvfi_rd_wdata_wb; + logic [31:0] rvfi_rd_wdata_d; + logic [31:0] rvfi_rd_wdata_q; + logic rvfi_rd_we_wb; + logic [3:0] rvfi_mem_mask_int; + logic [31:0] rvfi_mem_rdata_d; + logic [31:0] rvfi_mem_rdata_q; + logic [31:0] rvfi_mem_wdata_d; + logic [31:0] rvfi_mem_wdata_q; + logic [31:0] rvfi_mem_addr_d; + logic [31:0] rvfi_mem_addr_q; +`endif + + ////////////////////// + // Clock management // + ////////////////////// + + logic clk; + + logic clock_en; + + // Before going to sleep, wait for I- and D-side + // interfaces to finish ongoing operations. + assign core_busy_d = ctrl_busy | if_busy | lsu_busy; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + core_busy_q <= 1'b0; + end else begin + core_busy_q <= core_busy_d; + end + end + // capture fetch_enable_i in fetch_enable_q, once for ever + logic fetch_enable_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + fetch_enable_q <= 1'b0; + end else if (fetch_enable_i) begin + fetch_enable_q <= 1'b1; + end + end + + assign clock_en = fetch_enable_q & (core_busy_q | debug_req_i | irq_pending | irq_nm_i); + assign core_sleep_o = ~clock_en; + + // main clock gate of the core + // generates all clocks except the one for the debug unit which is + // independent + prim_clock_gating core_clock_gate_i ( + .clk_i ( clk_i ), + .en_i ( clock_en ), + .test_en_i ( test_en_i ), + .clk_o ( clk ) + ); + + ////////////// + // IF stage // + ////////////// + + ibex_if_stage #( + .DmHaltAddr ( DmHaltAddr ), + .DmExceptionAddr ( DmExceptionAddr ), + .DummyInstructions ( DummyInstructions ), + .ICache ( ICache ), + .ICacheECC ( ICacheECC ), + .PCIncrCheck ( PCIncrCheck ), + .BranchPredictor ( BranchPredictor ) + ) if_stage_i ( + .clk_i ( clk ), + .rst_ni ( rst_ni ), + + .boot_addr_i ( boot_addr_i ), + .req_i ( instr_req_int ), // instruction request control + + // instruction cache interface + .instr_req_o ( instr_req_out ), + .instr_addr_o ( instr_addr_o ), + .instr_gnt_i ( instr_gnt_i ), + .instr_rvalid_i ( instr_rvalid_i ), + .instr_rdata_i ( instr_rdata_i ), + .instr_err_i ( instr_err_i ), + .instr_pmp_err_i ( pmp_req_err[PMP_I] ), + + // outputs to ID stage + .instr_valid_id_o ( instr_valid_id ), + .instr_new_id_o ( instr_new_id ), + .instr_rdata_id_o ( instr_rdata_id ), + .instr_rdata_alu_id_o ( instr_rdata_alu_id ), + .instr_rdata_c_id_o ( instr_rdata_c_id ), + .instr_is_compressed_id_o ( instr_is_compressed_id ), + .instr_bp_taken_o ( instr_bp_taken_id ), + .instr_fetch_err_o ( instr_fetch_err ), + .instr_fetch_err_plus2_o ( instr_fetch_err_plus2 ), + .illegal_c_insn_id_o ( illegal_c_insn_id ), + .dummy_instr_id_o ( dummy_instr_id ), + .pc_if_o ( pc_if ), + .pc_id_o ( pc_id ), + + // control signals + .instr_valid_clear_i ( instr_valid_clear ), + .pc_set_i ( pc_set ), + .pc_set_spec_i ( pc_set_spec ), + .pc_mux_i ( pc_mux_id ), + .nt_branch_mispredict_i ( nt_branch_mispredict ), + .exc_pc_mux_i ( exc_pc_mux_id ), + .exc_cause ( exc_cause ), + .dummy_instr_en_i ( dummy_instr_en ), + .dummy_instr_mask_i ( dummy_instr_mask ), + .dummy_instr_seed_en_i ( dummy_instr_seed_en ), + .dummy_instr_seed_i ( dummy_instr_seed ), + .icache_enable_i ( icache_enable ), + .icache_inval_i ( icache_inval ), + + // branch targets + .branch_target_ex_i ( branch_target_ex ), + + // CSRs + .csr_mepc_i ( csr_mepc ), // exception return address + .csr_depc_i ( csr_depc ), // debug return address + .csr_mtvec_i ( csr_mtvec ), // trap-vector base address + .csr_mtvec_init_o ( csr_mtvec_init ), + + // pipeline stalls + .id_in_ready_i ( id_in_ready ), + + .pc_mismatch_alert_o ( pc_mismatch_alert ), + .if_busy_o ( if_busy ) + ); + + // Core is waiting for the ISide when ID/EX stage is ready for a new instruction but none are + // available + assign perf_iside_wait = id_in_ready & ~instr_valid_id; + + // Qualify the instruction request with PMP error + assign instr_req_o = instr_req_out & ~pmp_req_err[PMP_I]; + + ////////////// + // ID stage // + ////////////// + + ibex_id_stage #( + .RV32E ( RV32E ), + .RV32M ( RV32M ), + .RV32B ( RV32B ), + .BranchTargetALU ( BranchTargetALU ), + .DataIndTiming ( DataIndTiming ), + .SpecBranch ( SpecBranch ), + .WritebackStage ( WritebackStage ), + .BranchPredictor ( BranchPredictor ) + ) id_stage_i ( + .clk_i ( clk ), + .rst_ni ( rst_ni ), + + // Processor Enable + .ctrl_busy_o ( ctrl_busy ), + .illegal_insn_o ( illegal_insn_id ), + + // from/to IF-ID pipeline register + .instr_valid_i ( instr_valid_id ), + .instr_rdata_i ( instr_rdata_id ), + .instr_rdata_alu_i ( instr_rdata_alu_id ), + .instr_rdata_c_i ( instr_rdata_c_id ), + .instr_is_compressed_i ( instr_is_compressed_id ), + .instr_bp_taken_i ( instr_bp_taken_id ), + + // Jumps and branches + .branch_decision_i ( branch_decision ), + + // IF and ID control signals + .instr_first_cycle_id_o ( instr_first_cycle_id ), + .instr_valid_clear_o ( instr_valid_clear ), + .id_in_ready_o ( id_in_ready ), + .instr_req_o ( instr_req_int ), + .pc_set_o ( pc_set ), + .pc_set_spec_o ( pc_set_spec ), + .pc_mux_o ( pc_mux_id ), + .nt_branch_mispredict_o ( nt_branch_mispredict ), + .exc_pc_mux_o ( exc_pc_mux_id ), + .exc_cause_o ( exc_cause ), + .icache_inval_o ( icache_inval ), + + .instr_fetch_err_i ( instr_fetch_err ), + .instr_fetch_err_plus2_i ( instr_fetch_err_plus2 ), + .illegal_c_insn_i ( illegal_c_insn_id ), + + .pc_id_i ( pc_id ), + + // Stalls + .ex_valid_i ( ex_valid ), + .lsu_resp_valid_i ( lsu_resp_valid ), + + .alu_operator_ex_o ( alu_operator_ex ), + .alu_operand_a_ex_o ( alu_operand_a_ex ), + .alu_operand_b_ex_o ( alu_operand_b_ex ), + + .imd_val_q_ex_o ( imd_val_q_ex ), + .imd_val_d_ex_i ( imd_val_d_ex ), + .imd_val_we_ex_i ( imd_val_we_ex ), + + .bt_a_operand_o ( bt_a_operand ), + .bt_b_operand_o ( bt_b_operand ), + + .mult_en_ex_o ( mult_en_ex ), + .div_en_ex_o ( div_en_ex ), + .mult_sel_ex_o ( mult_sel_ex ), + .div_sel_ex_o ( div_sel_ex ), + .multdiv_operator_ex_o ( multdiv_operator_ex ), + .multdiv_signed_mode_ex_o ( multdiv_signed_mode_ex ), + .multdiv_operand_a_ex_o ( multdiv_operand_a_ex ), + .multdiv_operand_b_ex_o ( multdiv_operand_b_ex ), + .multdiv_ready_id_o ( multdiv_ready_id ), + + // CSR ID/EX + .csr_access_o ( csr_access ), + .csr_op_o ( csr_op ), + .csr_op_en_o ( csr_op_en ), + .csr_save_if_o ( csr_save_if ), // control signal to save PC + .csr_save_id_o ( csr_save_id ), // control signal to save PC + .csr_save_wb_o ( csr_save_wb ), // control signal to save PC + .csr_restore_mret_id_o ( csr_restore_mret_id ), // restore mstatus upon MRET + .csr_restore_dret_id_o ( csr_restore_dret_id ), // restore mstatus upon MRET + .csr_save_cause_o ( csr_save_cause ), + .csr_mtval_o ( csr_mtval ), + .priv_mode_i ( priv_mode_id ), + .csr_mstatus_tw_i ( csr_mstatus_tw ), + .illegal_csr_insn_i ( illegal_csr_insn_id ), + .data_ind_timing_i ( data_ind_timing ), + + // LSU + .lsu_req_o ( lsu_req ), // to load store unit + .lsu_we_o ( lsu_we ), // to load store unit + .lsu_type_o ( lsu_type ), // to load store unit + .lsu_sign_ext_o ( lsu_sign_ext ), // to load store unit + .lsu_wdata_o ( lsu_wdata ), // to load store unit + .lsu_req_done_i ( lsu_req_done ), // from load store unit + + .lsu_addr_incr_req_i ( lsu_addr_incr_req ), + .lsu_addr_last_i ( lsu_addr_last ), + + .lsu_load_err_i ( lsu_load_err ), + .lsu_store_err_i ( lsu_store_err ), + + // Interrupt Signals + .csr_mstatus_mie_i ( csr_mstatus_mie ), + .irq_pending_i ( irq_pending ), + .irqs_i ( irqs ), + .irq_nm_i ( irq_nm_i ), + .nmi_mode_o ( nmi_mode ), + + // Debug Signal + .debug_mode_o ( debug_mode ), + .debug_cause_o ( debug_cause ), + .debug_csr_save_o ( debug_csr_save ), + .debug_req_i ( debug_req_i ), + .debug_single_step_i ( debug_single_step ), + .debug_ebreakm_i ( debug_ebreakm ), + .debug_ebreaku_i ( debug_ebreaku ), + .trigger_match_i ( trigger_match ), + + // write data to commit in the register file + .result_ex_i ( result_ex ), + .csr_rdata_i ( csr_rdata ), + + .rf_raddr_a_o ( rf_raddr_a ), + .rf_rdata_a_i ( rf_rdata_a ), + .rf_raddr_b_o ( rf_raddr_b ), + .rf_rdata_b_i ( rf_rdata_b ), + .rf_ren_a_o ( rf_ren_a ), + .rf_ren_b_o ( rf_ren_b ), + .rf_waddr_id_o ( rf_waddr_id ), + .rf_wdata_id_o ( rf_wdata_id ), + .rf_we_id_o ( rf_we_id ), + .rf_rd_a_wb_match_o ( rf_rd_a_wb_match ), + .rf_rd_b_wb_match_o ( rf_rd_b_wb_match ), + + .rf_waddr_wb_i ( rf_waddr_wb ), + .rf_wdata_fwd_wb_i ( rf_wdata_fwd_wb ), + .rf_write_wb_i ( rf_write_wb ), + + .en_wb_o ( en_wb ), + .instr_type_wb_o ( instr_type_wb ), + .instr_perf_count_id_o ( instr_perf_count_id ), + .ready_wb_i ( ready_wb ), + .outstanding_load_wb_i ( outstanding_load_wb ), + .outstanding_store_wb_i ( outstanding_store_wb ), + + // Performance Counters + .perf_jump_o ( perf_jump ), + .perf_branch_o ( perf_branch ), + .perf_tbranch_o ( perf_tbranch ), + .perf_dside_wait_o ( perf_dside_wait ), + .perf_mul_wait_o ( perf_mul_wait ), + .perf_div_wait_o ( perf_div_wait ), + .instr_id_done_o ( instr_id_done ) + ); + + // for RVFI only + assign unused_illegal_insn_id = illegal_insn_id; + + ibex_ex_block #( + .RV32M ( RV32M ), + .RV32B ( RV32B ), + .BranchTargetALU ( BranchTargetALU ) + ) ex_block_i ( + .clk_i ( clk ), + .rst_ni ( rst_ni ), + + // ALU signal from ID stage + .alu_operator_i ( alu_operator_ex ), + .alu_operand_a_i ( alu_operand_a_ex ), + .alu_operand_b_i ( alu_operand_b_ex ), + .alu_instr_first_cycle_i ( instr_first_cycle_id ), + + // Branch target ALU signal from ID stage + .bt_a_operand_i ( bt_a_operand ), + .bt_b_operand_i ( bt_b_operand ), + + // Multipler/Divider signal from ID stage + .multdiv_operator_i ( multdiv_operator_ex ), + .mult_en_i ( mult_en_ex ), + .div_en_i ( div_en_ex ), + .mult_sel_i ( mult_sel_ex ), + .div_sel_i ( div_sel_ex ), + .multdiv_signed_mode_i ( multdiv_signed_mode_ex ), + .multdiv_operand_a_i ( multdiv_operand_a_ex ), + .multdiv_operand_b_i ( multdiv_operand_b_ex ), + .multdiv_ready_id_i ( multdiv_ready_id ), + .data_ind_timing_i ( data_ind_timing ), + + // Intermediate value register + .imd_val_we_o ( imd_val_we_ex ), + .imd_val_d_o ( imd_val_d_ex ), + .imd_val_q_i ( imd_val_q_ex ), + + // Outputs + .alu_adder_result_ex_o ( alu_adder_result_ex ), // to LSU + .result_ex_o ( result_ex ), // to ID + + .branch_target_o ( branch_target_ex ), // to IF + .branch_decision_o ( branch_decision ), // to ID + + .ex_valid_o ( ex_valid ) + ); + + ///////////////////// + // Load/store unit // + ///////////////////// + + assign data_req_o = data_req_out & ~pmp_req_err[PMP_D]; + assign lsu_resp_err = lsu_load_err | lsu_store_err; + + ibex_load_store_unit load_store_unit_i ( + .clk_i ( clk ), + .rst_ni ( rst_ni ), + + // data interface + .data_req_o ( data_req_out ), + .data_gnt_i ( data_gnt_i ), + .data_rvalid_i ( data_rvalid_i ), + .data_err_i ( data_err_i ), + .data_pmp_err_i ( pmp_req_err[PMP_D] ), + + .data_addr_o ( data_addr_o ), + .data_we_o ( data_we_o ), + .data_be_o ( data_be_o ), + .data_wdata_o ( data_wdata_o ), + .data_rdata_i ( data_rdata_i ), + + // signals to/from ID/EX stage + .lsu_we_i ( lsu_we ), + .lsu_type_i ( lsu_type ), + .lsu_wdata_i ( lsu_wdata ), + .lsu_sign_ext_i ( lsu_sign_ext ), + + .lsu_rdata_o ( rf_wdata_lsu ), + .lsu_rdata_valid_o ( rf_we_lsu ), + .lsu_req_i ( lsu_req ), + .lsu_req_done_o ( lsu_req_done ), + + .adder_result_ex_i ( alu_adder_result_ex ), + + .addr_incr_req_o ( lsu_addr_incr_req ), + .addr_last_o ( lsu_addr_last ), + + + .lsu_resp_valid_o ( lsu_resp_valid ), + + // exception signals + .load_err_o ( lsu_load_err ), + .store_err_o ( lsu_store_err ), + + .busy_o ( lsu_busy ), + + .perf_load_o ( perf_load ), + .perf_store_o ( perf_store ) + ); + + ibex_wb_stage #( + .WritebackStage ( WritebackStage ) + ) wb_stage_i ( + .clk_i ( clk ), + .rst_ni ( rst_ni ), + .en_wb_i ( en_wb ), + .instr_type_wb_i ( instr_type_wb ), + .pc_id_i ( pc_id ), + .instr_is_compressed_id_i ( instr_is_compressed_id ), + .instr_perf_count_id_i ( instr_perf_count_id ), + + .ready_wb_o ( ready_wb ), + .rf_write_wb_o ( rf_write_wb ), + .outstanding_load_wb_o ( outstanding_load_wb ), + .outstanding_store_wb_o ( outstanding_store_wb ), + .pc_wb_o ( pc_wb ), + .perf_instr_ret_wb_o ( perf_instr_ret_wb ), + .perf_instr_ret_compressed_wb_o ( perf_instr_ret_compressed_wb ), + + .rf_waddr_id_i ( rf_waddr_id ), + .rf_wdata_id_i ( rf_wdata_id ), + .rf_we_id_i ( rf_we_id ), + + .rf_wdata_lsu_i ( rf_wdata_lsu ), + .rf_we_lsu_i ( rf_we_lsu ), + + .rf_wdata_fwd_wb_o ( rf_wdata_fwd_wb ), + + .rf_waddr_wb_o ( rf_waddr_wb ), + .rf_wdata_wb_o ( rf_wdata_wb ), + .rf_we_wb_o ( rf_we_wb ), + + .lsu_resp_valid_i ( lsu_resp_valid ), + .lsu_resp_err_i ( lsu_resp_err ), + + .instr_done_wb_o ( instr_done_wb ) + ); + + /////////////////////// + // Register file ECC // + /////////////////////// + + logic [RegFileDataWidth-1:0] rf_wdata_wb_ecc; + logic [RegFileDataWidth-1:0] rf_rdata_a_ecc; + logic [RegFileDataWidth-1:0] rf_rdata_b_ecc; + logic rf_ecc_err_comb; + + if (RegFileECC) begin : gen_regfile_ecc + + logic [1:0] rf_ecc_err_a, rf_ecc_err_b; + logic rf_ecc_err_a_id, rf_ecc_err_b_id; + + // ECC checkbit generation for regiter file wdata + prim_secded_39_32_enc regfile_ecc_enc ( + .in (rf_wdata_wb), + .out (rf_wdata_wb_ecc) + ); + + // ECC checking on register file rdata + prim_secded_39_32_dec regfile_ecc_dec_a ( + .in (rf_rdata_a_ecc), + .d_o (), + .syndrome_o (), + .err_o (rf_ecc_err_a) + ); + prim_secded_39_32_dec regfile_ecc_dec_b ( + .in (rf_rdata_b_ecc), + .d_o (), + .syndrome_o (), + .err_o (rf_ecc_err_b) + ); + + // Assign read outputs - no error correction, just trigger an alert + assign rf_rdata_a = rf_rdata_a_ecc[31:0]; + assign rf_rdata_b = rf_rdata_b_ecc[31:0]; + + // Calculate errors - qualify with WB forwarding to avoid xprop into the alert signal + assign rf_ecc_err_a_id = |rf_ecc_err_a & rf_ren_a & ~rf_rd_a_wb_match; + assign rf_ecc_err_b_id = |rf_ecc_err_b & rf_ren_b & ~rf_rd_b_wb_match; + + // Combined error + assign rf_ecc_err_comb = instr_valid_id & (rf_ecc_err_a_id | rf_ecc_err_b_id); + + end else begin : gen_no_regfile_ecc + logic unused_rf_ren_a, unused_rf_ren_b; + logic unused_rf_rd_a_wb_match, unused_rf_rd_b_wb_match; + + assign unused_rf_ren_a = rf_ren_a; + assign unused_rf_ren_b = rf_ren_b; + assign unused_rf_rd_a_wb_match = rf_rd_a_wb_match; + assign unused_rf_rd_b_wb_match = rf_rd_b_wb_match; + assign rf_wdata_wb_ecc = rf_wdata_wb; + assign rf_rdata_a = rf_rdata_a_ecc; + assign rf_rdata_b = rf_rdata_b_ecc; + assign rf_ecc_err_comb = 1'b0; + end + + if (RegFile == RegFileFF) begin : gen_regfile_ff + ibex_register_file_ff #( + .RV32E ( RV32E ), + .DataWidth ( RegFileDataWidth ), + .DummyInstructions ( DummyInstructions ) + ) register_file_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .test_en_i ( test_en_i ), + .dummy_instr_id_i ( dummy_instr_id ), + + .raddr_a_i ( rf_raddr_a ), + .rdata_a_o ( rf_rdata_a_ecc ), + .raddr_b_i ( rf_raddr_b ), + .rdata_b_o ( rf_rdata_b_ecc ), + .waddr_a_i ( rf_waddr_wb ), + .wdata_a_i ( rf_wdata_wb_ecc ), + .we_a_i ( rf_we_wb ) + ); + end else if (RegFile == RegFileFPGA) begin : gen_regfile_fpga + ibex_register_file_fpga #( + .RV32E ( RV32E ), + .DataWidth ( RegFileDataWidth ), + .DummyInstructions ( DummyInstructions ) + ) register_file_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .test_en_i ( test_en_i ), + .dummy_instr_id_i ( dummy_instr_id ), + + .raddr_a_i ( rf_raddr_a ), + .rdata_a_o ( rf_rdata_a_ecc ), + .raddr_b_i ( rf_raddr_b ), + .rdata_b_o ( rf_rdata_b_ecc ), + .waddr_a_i ( rf_waddr_wb ), + .wdata_a_i ( rf_wdata_wb_ecc ), + .we_a_i ( rf_we_wb ) + ); + end else if (RegFile == RegFileLatch) begin : gen_regfile_latch + ibex_register_file_latch #( + .RV32E ( RV32E ), + .DataWidth ( RegFileDataWidth ), + .DummyInstructions ( DummyInstructions ) + ) register_file_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .test_en_i ( test_en_i ), + .dummy_instr_id_i ( dummy_instr_id ), + + .raddr_a_i ( rf_raddr_a ), + .rdata_a_o ( rf_rdata_a_ecc ), + .raddr_b_i ( rf_raddr_b ), + .rdata_b_o ( rf_rdata_b_ecc ), + .waddr_a_i ( rf_waddr_wb ), + .wdata_a_i ( rf_wdata_wb_ecc ), + .we_a_i ( rf_we_wb ) + ); + end + + /////////////////// + // Alert outputs // + /////////////////// + + // Minor alert - core is in a recoverable state + // TODO add I$ ECC errors here + assign alert_minor_o = 1'b0; + + // Major alert - core is unrecoverable + assign alert_major_o = rf_ecc_err_comb | pc_mismatch_alert | csr_shadow_err; + + `ASSERT_KNOWN(IbexAlertMinorX, alert_minor_o) + `ASSERT_KNOWN(IbexAlertMajorX, alert_major_o) + + // Explict INC_ASSERT block to avoid unused signal lint warnings were asserts are not included + `ifdef INC_ASSERT + // Signals used for assertions only + logic outstanding_load_resp; + logic outstanding_store_resp; + + logic outstanding_load_id; + logic outstanding_store_id; + + assign outstanding_load_id = id_stage_i.instr_executing & id_stage_i.lsu_req_dec & + ~id_stage_i.lsu_we; + assign outstanding_store_id = id_stage_i.instr_executing & id_stage_i.lsu_req_dec & + id_stage_i.lsu_we; + + if (WritebackStage) begin : gen_wb_stage + // When the writeback stage is present a load/store could be in ID or WB. A Load/store in ID can + // see a response before it moves to WB when it is unaligned otherwise we should only see + // a response when load/store is in WB. + assign outstanding_load_resp = outstanding_load_wb | + (outstanding_load_id & load_store_unit_i.split_misaligned_access); + + assign outstanding_store_resp = outstanding_store_wb | + (outstanding_store_id & load_store_unit_i.split_misaligned_access); + + // When writing back the result of a load, the load must have made it to writeback + `ASSERT(NoMemRFWriteWithoutPendingLoad, rf_we_lsu |-> outstanding_load_wb, clk_i, !rst_ni) + end else begin : gen_no_wb_stage + // Without writeback stage only look into whether load or store is in ID to determine if + // a response is expected. + assign outstanding_load_resp = outstanding_load_id; + assign outstanding_store_resp = outstanding_store_id; + + `ASSERT(NoMemRFWriteWithoutPendingLoad, rf_we_lsu |-> outstanding_load_id, clk_i, !rst_ni) + end + + `ASSERT(NoMemResponseWithoutPendingAccess, + data_rvalid_i |-> outstanding_load_resp | outstanding_store_resp, clk_i, !rst_ni) + `endif + + //////////////////////// + // RF (Register File) // + //////////////////////// +`ifdef RVFI + assign rvfi_rd_addr_wb = rf_waddr_wb; + assign rvfi_rd_wdata_wb = rf_we_wb ? rf_wdata_wb : rf_wdata_lsu; + assign rvfi_rd_we_wb = rf_we_wb | rf_we_lsu; +`endif + + + ///////////////////////////////////////// + // CSRs (Control and Status Registers) // + ///////////////////////////////////////// + + assign csr_wdata = alu_operand_a_ex; + assign csr_addr = csr_num_e'(csr_access ? alu_operand_b_ex[11:0] : 12'b0); + + ibex_cs_registers #( + .DbgTriggerEn ( DbgTriggerEn ), + .DbgHwBreakNum ( DbgHwBreakNum ), + .DataIndTiming ( DataIndTiming ), + .DummyInstructions ( DummyInstructions ), + .ShadowCSR ( ShadowCSR ), + .ICache ( ICache ), + .MHPMCounterNum ( MHPMCounterNum ), + .MHPMCounterWidth ( MHPMCounterWidth ), + .PMPEnable ( PMPEnable ), + .PMPGranularity ( PMPGranularity ), + .PMPNumRegions ( PMPNumRegions ), + .RV32E ( RV32E ), + .RV32M ( RV32M ) + ) cs_registers_i ( + .clk_i ( clk ), + .rst_ni ( rst_ni ), + + // Hart ID from outside + .hart_id_i ( hart_id_i ), + .priv_mode_id_o ( priv_mode_id ), + .priv_mode_if_o ( priv_mode_if ), + .priv_mode_lsu_o ( priv_mode_lsu ), + + // mtvec + .csr_mtvec_o ( csr_mtvec ), + .csr_mtvec_init_i ( csr_mtvec_init ), + .boot_addr_i ( boot_addr_i ), + + // Interface to CSRs ( SRAM like ) + .csr_access_i ( csr_access ), + .csr_addr_i ( csr_addr ), + .csr_wdata_i ( csr_wdata ), + .csr_op_i ( csr_op ), + .csr_op_en_i ( csr_op_en ), + .csr_rdata_o ( csr_rdata ), + + // Interrupt related control signals + .irq_software_i ( irq_software_i ), + .irq_timer_i ( irq_timer_i ), + .irq_external_i ( irq_external_i ), + .irq_fast_i ( irq_fast_i ), + .nmi_mode_i ( nmi_mode ), + .irq_pending_o ( irq_pending ), + .irqs_o ( irqs ), + .csr_mstatus_mie_o ( csr_mstatus_mie ), + .csr_mstatus_tw_o ( csr_mstatus_tw ), + .csr_mepc_o ( csr_mepc ), + + // PMP + .csr_pmp_cfg_o ( csr_pmp_cfg ), + .csr_pmp_addr_o ( csr_pmp_addr ), + + // debug + .csr_depc_o ( csr_depc ), + .debug_mode_i ( debug_mode ), + .debug_cause_i ( debug_cause ), + .debug_csr_save_i ( debug_csr_save ), + .debug_single_step_o ( debug_single_step ), + .debug_ebreakm_o ( debug_ebreakm ), + .debug_ebreaku_o ( debug_ebreaku ), + .trigger_match_o ( trigger_match ), + + .pc_if_i ( pc_if ), + .pc_id_i ( pc_id ), + .pc_wb_i ( pc_wb ), + + .data_ind_timing_o ( data_ind_timing ), + .dummy_instr_en_o ( dummy_instr_en ), + .dummy_instr_mask_o ( dummy_instr_mask ), + .dummy_instr_seed_en_o ( dummy_instr_seed_en ), + .dummy_instr_seed_o ( dummy_instr_seed ), + .icache_enable_o ( icache_enable ), + .csr_shadow_err_o ( csr_shadow_err ), + + .csr_save_if_i ( csr_save_if ), + .csr_save_id_i ( csr_save_id ), + .csr_save_wb_i ( csr_save_wb ), + .csr_restore_mret_i ( csr_restore_mret_id ), + .csr_restore_dret_i ( csr_restore_dret_id ), + .csr_save_cause_i ( csr_save_cause ), + .csr_mcause_i ( exc_cause ), + .csr_mtval_i ( csr_mtval ), + .illegal_csr_insn_o ( illegal_csr_insn_id ), + + // performance counter related signals + .instr_ret_i ( perf_instr_ret_wb ), + .instr_ret_compressed_i ( perf_instr_ret_compressed_wb ), + .iside_wait_i ( perf_iside_wait ), + .jump_i ( perf_jump ), + .branch_i ( perf_branch ), + .branch_taken_i ( perf_tbranch ), + .mem_load_i ( perf_load ), + .mem_store_i ( perf_store ), + .dside_wait_i ( perf_dside_wait ), + .mul_wait_i ( perf_mul_wait ), + .div_wait_i ( perf_div_wait ) + ); + + // These assertions are in top-level as instr_valid_id required as the enable term + `ASSERT(IbexCsrOpValid, instr_valid_id |-> csr_op inside { + CSR_OP_READ, + CSR_OP_WRITE, + CSR_OP_SET, + CSR_OP_CLEAR + }) + `ASSERT_KNOWN_IF(IbexCsrWdataIntKnown, cs_registers_i.csr_wdata_int, csr_op_en) + + if (PMPEnable) begin : g_pmp + logic [33:0] pmp_req_addr [PMP_NUM_CHAN]; + pmp_req_e pmp_req_type [PMP_NUM_CHAN]; + priv_lvl_e pmp_priv_lvl [PMP_NUM_CHAN]; + + assign pmp_req_addr[PMP_I] = {2'b00,instr_addr_o[31:0]}; + assign pmp_req_type[PMP_I] = PMP_ACC_EXEC; + assign pmp_priv_lvl[PMP_I] = priv_mode_if; + assign pmp_req_addr[PMP_D] = {2'b00,data_addr_o[31:0]}; + assign pmp_req_type[PMP_D] = data_we_o ? PMP_ACC_WRITE : PMP_ACC_READ; + assign pmp_priv_lvl[PMP_D] = priv_mode_lsu; + + ibex_pmp #( + .PMPGranularity ( PMPGranularity ), + .PMPNumChan ( PMP_NUM_CHAN ), + .PMPNumRegions ( PMPNumRegions ) + ) pmp_i ( + .clk_i ( clk ), + .rst_ni ( rst_ni ), + // Interface to CSRs + .csr_pmp_cfg_i ( csr_pmp_cfg ), + .csr_pmp_addr_i ( csr_pmp_addr ), + .priv_mode_i ( pmp_priv_lvl ), + // Access checking channels + .pmp_req_addr_i ( pmp_req_addr ), + .pmp_req_type_i ( pmp_req_type ), + .pmp_req_err_o ( pmp_req_err ) + ); + end else begin : g_no_pmp + // Unused signal tieoff + priv_lvl_e unused_priv_lvl_if, unused_priv_lvl_ls; + logic [33:0] unused_csr_pmp_addr [PMPNumRegions]; + pmp_cfg_t unused_csr_pmp_cfg [PMPNumRegions]; + assign unused_priv_lvl_if = priv_mode_if; + assign unused_priv_lvl_ls = priv_mode_lsu; + assign unused_csr_pmp_addr = csr_pmp_addr; + assign unused_csr_pmp_cfg = csr_pmp_cfg; + + // Output tieoff + assign pmp_req_err[PMP_I] = 1'b0; + assign pmp_req_err[PMP_D] = 1'b0; + end + +`ifdef RVFI + // When writeback stage is present RVFI information is emitted when instruction is finished in + // third stage but some information must be captured whilst the instruction is in the second + // stage. Without writeback stage RVFI information is all emitted when instruction retires in + // second stage. RVFI outputs are all straight from flops. So 2 stage pipeline requires a single + // set of flops (instr_info => RVFI_out), 3 stage pipeline requires two sets (instr_info => wb + // => RVFI_out) + localparam int RVFI_STAGES = WritebackStage ? 2 : 1; + + logic rvfi_stage_valid [RVFI_STAGES]; + logic [63:0] rvfi_stage_order [RVFI_STAGES]; + logic [31:0] rvfi_stage_insn [RVFI_STAGES]; + logic rvfi_stage_trap [RVFI_STAGES]; + logic rvfi_stage_halt [RVFI_STAGES]; + logic rvfi_stage_intr [RVFI_STAGES]; + logic [ 1:0] rvfi_stage_mode [RVFI_STAGES]; + logic [ 1:0] rvfi_stage_ixl [RVFI_STAGES]; + logic [ 4:0] rvfi_stage_rs1_addr [RVFI_STAGES]; + logic [ 4:0] rvfi_stage_rs2_addr [RVFI_STAGES]; + logic [ 4:0] rvfi_stage_rs3_addr [RVFI_STAGES]; + logic [31:0] rvfi_stage_rs1_rdata [RVFI_STAGES]; + logic [31:0] rvfi_stage_rs2_rdata [RVFI_STAGES]; + logic [31:0] rvfi_stage_rs3_rdata [RVFI_STAGES]; + logic [ 4:0] rvfi_stage_rd_addr [RVFI_STAGES]; + logic [31:0] rvfi_stage_rd_wdata [RVFI_STAGES]; + logic [31:0] rvfi_stage_pc_rdata [RVFI_STAGES]; + logic [31:0] rvfi_stage_pc_wdata [RVFI_STAGES]; + logic [31:0] rvfi_stage_mem_addr [RVFI_STAGES]; + logic [ 3:0] rvfi_stage_mem_rmask [RVFI_STAGES]; + logic [ 3:0] rvfi_stage_mem_wmask [RVFI_STAGES]; + logic [31:0] rvfi_stage_mem_rdata [RVFI_STAGES]; + logic [31:0] rvfi_stage_mem_wdata [RVFI_STAGES]; + + logic rvfi_stage_valid_d [RVFI_STAGES]; + + assign rvfi_valid = rvfi_stage_valid [RVFI_STAGES-1]; + assign rvfi_order = rvfi_stage_order [RVFI_STAGES-1]; + assign rvfi_insn = rvfi_stage_insn [RVFI_STAGES-1]; + assign rvfi_trap = rvfi_stage_trap [RVFI_STAGES-1]; + assign rvfi_halt = rvfi_stage_halt [RVFI_STAGES-1]; + assign rvfi_intr = rvfi_stage_intr [RVFI_STAGES-1]; + assign rvfi_mode = rvfi_stage_mode [RVFI_STAGES-1]; + assign rvfi_ixl = rvfi_stage_ixl [RVFI_STAGES-1]; + assign rvfi_rs1_addr = rvfi_stage_rs1_addr [RVFI_STAGES-1]; + assign rvfi_rs2_addr = rvfi_stage_rs2_addr [RVFI_STAGES-1]; + assign rvfi_rs3_addr = rvfi_stage_rs3_addr [RVFI_STAGES-1]; + assign rvfi_rs1_rdata = rvfi_stage_rs1_rdata[RVFI_STAGES-1]; + assign rvfi_rs2_rdata = rvfi_stage_rs2_rdata[RVFI_STAGES-1]; + assign rvfi_rs3_rdata = rvfi_stage_rs3_rdata[RVFI_STAGES-1]; + assign rvfi_rd_addr = rvfi_stage_rd_addr [RVFI_STAGES-1]; + assign rvfi_rd_wdata = rvfi_stage_rd_wdata [RVFI_STAGES-1]; + assign rvfi_pc_rdata = rvfi_stage_pc_rdata [RVFI_STAGES-1]; + assign rvfi_pc_wdata = rvfi_stage_pc_wdata [RVFI_STAGES-1]; + assign rvfi_mem_addr = rvfi_stage_mem_addr [RVFI_STAGES-1]; + assign rvfi_mem_rmask = rvfi_stage_mem_rmask[RVFI_STAGES-1]; + assign rvfi_mem_wmask = rvfi_stage_mem_wmask[RVFI_STAGES-1]; + assign rvfi_mem_rdata = rvfi_stage_mem_rdata[RVFI_STAGES-1]; + assign rvfi_mem_wdata = rvfi_stage_mem_wdata[RVFI_STAGES-1]; + + if (WritebackStage) begin : gen_rvfi_wb_stage + logic unused_instr_new_id; + + assign unused_instr_new_id = instr_new_id; + + // With writeback stage first RVFI stage buffers instruction information captured in ID/EX + // awaiting instruction retirement and RF Write data/Mem read data whilst instruction is in WB + // So first stage becomes valid when instruction leaves ID/EX stage and remains valid until + // instruction leaves WB + assign rvfi_stage_valid_d[0] = (instr_id_done & ~dummy_instr_id) | + (rvfi_stage_valid[0] & ~instr_done_wb); + // Second stage is output stage so simple valid cycle after instruction leaves WB (and so has + // retired) + assign rvfi_stage_valid_d[1] = instr_done_wb; + + // Signal new instruction in WB cycle after instruction leaves ID/EX (to enter WB) + logic rvfi_instr_new_wb_q; + + assign rvfi_instr_new_wb = rvfi_instr_new_wb_q; + + always_ff @(posedge clk or negedge rst_ni) begin + if (~rst_ni) begin + rvfi_instr_new_wb_q <= 0; + end else begin + rvfi_instr_new_wb_q <= instr_id_done; + end + end + end else begin : gen_rvfi_no_wb_stage + // Without writeback stage first RVFI stage is output stage so simply valid the cycle after + // instruction leaves ID/EX (and so has retired) + assign rvfi_stage_valid_d[0] = instr_id_done & ~dummy_instr_id; + // Without writeback stage signal new instr_new_wb when instruction enters ID/EX to correctly + // setup register write signals + assign rvfi_instr_new_wb = instr_new_id; + end + + for (genvar i = 0;i < RVFI_STAGES; i = i + 1) begin : g_rvfi_stages + always_ff @(posedge clk or negedge rst_ni) begin + if (!rst_ni) begin + rvfi_stage_halt[i] <= '0; + rvfi_stage_trap[i] <= '0; + rvfi_stage_intr[i] <= '0; + rvfi_stage_order[i] <= '0; + rvfi_stage_insn[i] <= '0; + rvfi_stage_mode[i] <= {PRIV_LVL_M}; + rvfi_stage_ixl[i] <= CSR_MISA_MXL; + rvfi_stage_rs1_addr[i] <= '0; + rvfi_stage_rs2_addr[i] <= '0; + rvfi_stage_rs3_addr[i] <= '0; + rvfi_stage_pc_rdata[i] <= '0; + rvfi_stage_pc_wdata[i] <= '0; + rvfi_stage_mem_rmask[i] <= '0; + rvfi_stage_mem_wmask[i] <= '0; + rvfi_stage_valid[i] <= '0; + rvfi_stage_rs1_rdata[i] <= '0; + rvfi_stage_rs2_rdata[i] <= '0; + rvfi_stage_rs3_rdata[i] <= '0; + rvfi_stage_rd_wdata[i] <= '0; + rvfi_stage_rd_addr[i] <= '0; + rvfi_stage_mem_rdata[i] <= '0; + rvfi_stage_mem_wdata[i] <= '0; + rvfi_stage_mem_addr[i] <= '0; + end else begin + rvfi_stage_valid[i] <= rvfi_stage_valid_d[i]; + + if (i == 0) begin + if(instr_id_done) begin + rvfi_stage_halt[i] <= '0; + rvfi_stage_trap[i] <= illegal_insn_id; + rvfi_stage_intr[i] <= rvfi_intr_d; + rvfi_stage_order[i] <= rvfi_stage_order[i] + 64'(rvfi_stage_valid_d[i]); + rvfi_stage_insn[i] <= rvfi_insn_id; + rvfi_stage_mode[i] <= {priv_mode_id}; + rvfi_stage_ixl[i] <= CSR_MISA_MXL; + rvfi_stage_rs1_addr[i] <= rvfi_rs1_addr_d; + rvfi_stage_rs2_addr[i] <= rvfi_rs2_addr_d; + rvfi_stage_rs3_addr[i] <= rvfi_rs3_addr_d; + rvfi_stage_pc_rdata[i] <= pc_id; + rvfi_stage_pc_wdata[i] <= pc_set ? branch_target_ex : pc_if; + rvfi_stage_mem_rmask[i] <= rvfi_mem_mask_int; + rvfi_stage_mem_wmask[i] <= data_we_o ? rvfi_mem_mask_int : 4'b0000; + rvfi_stage_rs1_rdata[i] <= rvfi_rs1_data_d; + rvfi_stage_rs2_rdata[i] <= rvfi_rs2_data_d; + rvfi_stage_rs3_rdata[i] <= rvfi_rs3_data_d; + rvfi_stage_rd_addr[i] <= rvfi_rd_addr_d; + rvfi_stage_rd_wdata[i] <= rvfi_rd_wdata_d; + rvfi_stage_mem_rdata[i] <= rvfi_mem_rdata_d; + rvfi_stage_mem_wdata[i] <= rvfi_mem_wdata_d; + rvfi_stage_mem_addr[i] <= rvfi_mem_addr_d; + end + end else begin + if(instr_done_wb) begin + rvfi_stage_halt[i] <= rvfi_stage_halt[i-1]; + rvfi_stage_trap[i] <= rvfi_stage_trap[i-1]; + rvfi_stage_intr[i] <= rvfi_stage_intr[i-1]; + rvfi_stage_order[i] <= rvfi_stage_order[i-1]; + rvfi_stage_insn[i] <= rvfi_stage_insn[i-1]; + rvfi_stage_mode[i] <= rvfi_stage_mode[i-1]; + rvfi_stage_ixl[i] <= rvfi_stage_ixl[i-1]; + rvfi_stage_rs1_addr[i] <= rvfi_stage_rs1_addr[i-1]; + rvfi_stage_rs2_addr[i] <= rvfi_stage_rs2_addr[i-1]; + rvfi_stage_rs3_addr[i] <= rvfi_stage_rs3_addr[i-1]; + rvfi_stage_pc_rdata[i] <= rvfi_stage_pc_rdata[i-1]; + rvfi_stage_pc_wdata[i] <= rvfi_stage_pc_wdata[i-1]; + rvfi_stage_mem_rmask[i] <= rvfi_stage_mem_rmask[i-1]; + rvfi_stage_mem_wmask[i] <= rvfi_stage_mem_wmask[i-1]; + rvfi_stage_rs1_rdata[i] <= rvfi_stage_rs1_rdata[i-1]; + rvfi_stage_rs2_rdata[i] <= rvfi_stage_rs2_rdata[i-1]; + rvfi_stage_rs3_rdata[i] <= rvfi_stage_rs3_rdata[i-1]; + rvfi_stage_mem_wdata[i] <= rvfi_stage_mem_wdata[i-1]; + rvfi_stage_mem_addr[i] <= rvfi_stage_mem_addr[i-1]; + + // For 2 RVFI_STAGES/Writeback Stage ignore first stage flops for rd_addr, rd_wdata and + // mem_rdata. For RF write addr/data actual write happens in writeback so capture + // address/data there. For mem_rdata that is only available from the writeback stage. + // Previous stage flops still exist in RTL as they are used by the non writeback config + rvfi_stage_rd_addr[i] <= rvfi_rd_addr_d; + rvfi_stage_rd_wdata[i] <= rvfi_rd_wdata_d; + rvfi_stage_mem_rdata[i] <= rvfi_mem_rdata_d; + end + end + end + end + end + + + // Memory adddress/write data available first cycle of ld/st instruction from register read + always_comb begin + if (instr_first_cycle_id) begin + rvfi_mem_addr_d = alu_adder_result_ex; + rvfi_mem_wdata_d = lsu_wdata; + end else begin + rvfi_mem_addr_d = rvfi_mem_addr_q; + rvfi_mem_wdata_d = rvfi_mem_wdata_q; + end + end + + // Capture read data from LSU when it becomes valid + always_comb begin + if (lsu_resp_valid) begin + rvfi_mem_rdata_d = rf_wdata_lsu; + end else begin + rvfi_mem_rdata_d = rvfi_mem_rdata_q; + end + end + + always_ff @(posedge clk or negedge rst_ni) begin + if (!rst_ni) begin + rvfi_mem_addr_q <= '0; + rvfi_mem_rdata_q <= '0; + rvfi_mem_wdata_q <= '0; + end else begin + rvfi_mem_addr_q <= rvfi_mem_addr_d; + rvfi_mem_rdata_q <= rvfi_mem_rdata_d; + rvfi_mem_wdata_q <= rvfi_mem_wdata_d; + end + end + // Byte enable based on data type + always_comb begin + unique case (lsu_type) + 2'b00: rvfi_mem_mask_int = 4'b1111; + 2'b01: rvfi_mem_mask_int = 4'b0011; + 2'b10: rvfi_mem_mask_int = 4'b0001; + default: rvfi_mem_mask_int = 4'b0000; + endcase + end + + always_comb begin + if (instr_is_compressed_id) begin + rvfi_insn_id = {16'b0, instr_rdata_c_id}; + end else begin + rvfi_insn_id = instr_rdata_id; + end + end + + // Source registers 1 and 2 are read in the first instruction cycle + // Source register 3 is read in the second instruction cycle. + always_comb begin + if (instr_first_cycle_id) begin + rvfi_rs1_data_d = rf_ren_a ? multdiv_operand_a_ex : '0; + rvfi_rs1_addr_d = rf_ren_a ? rf_raddr_a : '0; + rvfi_rs2_data_d = rf_ren_b ? multdiv_operand_b_ex : '0; + rvfi_rs2_addr_d = rf_ren_b ? rf_raddr_b : '0; + rvfi_rs3_data_d = '0; + rvfi_rs3_addr_d = '0; + end else begin + rvfi_rs1_data_d = rvfi_rs1_data_q; + rvfi_rs1_addr_d = rvfi_rs1_addr_q; + rvfi_rs2_data_d = rvfi_rs2_data_q; + rvfi_rs2_addr_d = rvfi_rs2_addr_q; + rvfi_rs3_data_d = multdiv_operand_a_ex; + rvfi_rs3_addr_d = rf_raddr_a; + end + end + always_ff @(posedge clk or negedge rst_ni) begin + if (!rst_ni) begin + rvfi_rs1_data_q <= '0; + rvfi_rs1_addr_q <= '0; + rvfi_rs2_data_q <= '0; + rvfi_rs2_addr_q <= '0; + + end else begin + rvfi_rs1_data_q <= rvfi_rs1_data_d; + rvfi_rs1_addr_q <= rvfi_rs1_addr_d; + rvfi_rs2_data_q <= rvfi_rs2_data_d; + rvfi_rs2_addr_q <= rvfi_rs2_addr_d; + end + end + + always_comb begin + if(rvfi_rd_we_wb) begin + // Capture address/data of write to register file + rvfi_rd_addr_d = rvfi_rd_addr_wb; + // If writing to x0 zero write data as required by RVFI specification + if(rvfi_rd_addr_wb == 5'b0) begin + rvfi_rd_wdata_d = '0; + end else begin + rvfi_rd_wdata_d = rvfi_rd_wdata_wb; + end + end else if(rvfi_instr_new_wb) begin + // If no RF write but new instruction in Writeback (when present) or ID/EX (when no writeback + // stage present) then zero RF write address/data as required by RVFI specification + rvfi_rd_addr_d = '0; + rvfi_rd_wdata_d = '0; + end else begin + // Otherwise maintain previous value + rvfi_rd_addr_d = rvfi_rd_addr_q; + rvfi_rd_wdata_d = rvfi_rd_wdata_q; + end + end + + // RD write register is refreshed only once per cycle and + // then it is kept stable for the cycle. + always_ff @(posedge clk or negedge rst_ni) begin + if (!rst_ni) begin + rvfi_rd_addr_q <= '0; + rvfi_rd_wdata_q <= '0; + end else begin + rvfi_rd_addr_q <= rvfi_rd_addr_d; + rvfi_rd_wdata_q <= rvfi_rd_wdata_d; + end + end + + // rvfi_intr must be set for first instruction that is part of a trap handler. + // On the first cycle of a new instruction see if a trap PC was set by the previous instruction, + // otherwise maintain value. + assign rvfi_intr_d = instr_first_cycle_id ? rvfi_set_trap_pc_q : rvfi_intr_q; + + always_comb begin + rvfi_set_trap_pc_d = rvfi_set_trap_pc_q; + + if (pc_set && pc_mux_id == PC_EXC && + (exc_pc_mux_id == EXC_PC_EXC || exc_pc_mux_id == EXC_PC_IRQ)) begin + // PC is set to enter a trap handler + rvfi_set_trap_pc_d = 1'b1; + end else if (rvfi_set_trap_pc_q && instr_id_done) begin + // first instruction has been executed after PC is set to trap handler + rvfi_set_trap_pc_d = 1'b0; + end + end + + always_ff @(posedge clk or negedge rst_ni) begin + if (!rst_ni) begin + rvfi_set_trap_pc_q <= 1'b0; + rvfi_intr_q <= 1'b0; + end else begin + rvfi_set_trap_pc_q <= rvfi_set_trap_pc_d; + rvfi_intr_q <= rvfi_intr_d; + end + end + +`else + logic unused_instr_new_id, unused_instr_done_wb; + assign unused_instr_new_id = instr_new_id; + assign unused_instr_done_wb = instr_done_wb; +`endif + + // Certain parameter combinations are not supported + `ASSERT_INIT(IllegalParamSecure, !(SecureIbex && (RV32M == RV32MNone))) + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_counter.sv b/flow/designs/src/ibex_sv/ibex_counter.sv new file mode 100644 index 0000000000..0091d5af30 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_counter.sv @@ -0,0 +1,82 @@ +module ibex_counter #( + parameter int CounterWidth = 32 +) ( + input logic clk_i, + input logic rst_ni, + + input logic counter_inc_i, + input logic counterh_we_i, + input logic counter_we_i, + input logic [31:0] counter_val_i, + output logic [63:0] counter_val_o +); + + logic [63:0] counter; + logic [CounterWidth-1:0] counter_upd; + logic [63:0] counter_load; + logic we; + logic [CounterWidth-1:0] counter_d; + + // Update + always_comb begin + + // Write + we = counter_we_i | counterh_we_i; + counter_load[63:32] = counter[63:32]; + counter_load[31:0] = counter_val_i; + if (counterh_we_i) begin + counter_load[63:32] = counter_val_i; + counter_load[31:0] = counter[31:0]; + end + + // Increment + counter_upd = counter[CounterWidth-1:0] + {{CounterWidth-1{1'b0}},1'b1}; + + // Next value logic + if (we) begin + counter_d = counter_load[CounterWidth-1:0]; + end else if (counter_inc_i)begin + counter_d = counter_upd[CounterWidth-1:0]; + end else begin + counter_d = counter[CounterWidth-1:0]; + end + end + +`ifdef FPGA_XILINX + // Set DSP pragma for supported xilinx FPGAs + localparam int DspPragma = CounterWidth < 49 ? "yes" : "no"; + (* use_dsp = DspPragma *) logic [CounterWidth-1:0] counter_q; + + // DSP output register requires synchronous reset. + `define COUNTER_FLOP_RST posedge clk_i +`else + logic [CounterWidth-1:0] counter_q; + + `define COUNTER_FLOP_RST posedge clk_i or negedge rst_ni +`endif + + // Counter flop + always_ff @(`COUNTER_FLOP_RST) begin + if (!rst_ni) begin + counter_q <= '0; + end else begin + counter_q <= counter_d; + end + end + + if (CounterWidth < 64) begin : g_counter_narrow + logic [63:CounterWidth] unused_counter_load; + + assign counter[CounterWidth-1:0] = counter_q; + assign counter[63:CounterWidth] = '0; + assign unused_counter_load = counter_load[63:CounterWidth]; + end else begin : g_counter_full + assign counter = counter_q; + end + + assign counter_val_o = counter; + +endmodule + +// Keep helper defines file-local. +`undef COUNTER_FLOP_RST diff --git a/flow/designs/src/ibex_sv/ibex_cs_registers.sv b/flow/designs/src/ibex_sv/ibex_cs_registers.sv new file mode 100644 index 0000000000..16a8acd3fc --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_cs_registers.sv @@ -0,0 +1,1420 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Control and Status Registers + * + * Control and Status Registers (CSRs) following the RISC-V Privileged + * Specification, draft version 1.11 + */ + +`include "prim_assert.sv" + +module ibex_cs_registers #( + parameter bit DbgTriggerEn = 0, + parameter int unsigned DbgHwBreakNum = 1, + parameter bit DataIndTiming = 1'b0, + parameter bit DummyInstructions = 1'b0, + parameter bit ShadowCSR = 1'b0, + parameter bit ICache = 1'b0, + parameter int unsigned MHPMCounterNum = 10, + parameter int unsigned MHPMCounterWidth = 40, + parameter bit PMPEnable = 0, + parameter int unsigned PMPGranularity = 0, + parameter int unsigned PMPNumRegions = 4, + parameter bit RV32E = 0, + parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast +) ( + // Clock and Reset + input logic clk_i, + input logic rst_ni, + + // Hart ID + input logic [31:0] hart_id_i, + + // Privilege mode + output ibex_pkg::priv_lvl_e priv_mode_id_o, + output ibex_pkg::priv_lvl_e priv_mode_if_o, + output ibex_pkg::priv_lvl_e priv_mode_lsu_o, + output logic csr_mstatus_tw_o, + + // mtvec + output logic [31:0] csr_mtvec_o, + input logic csr_mtvec_init_i, + input logic [31:0] boot_addr_i, + + // Interface to registers (SRAM like) + input logic csr_access_i, + input ibex_pkg::csr_num_e csr_addr_i, + input logic [31:0] csr_wdata_i, + input ibex_pkg::csr_op_e csr_op_i, + input csr_op_en_i, + output logic [31:0] csr_rdata_o, + + // interrupts + input logic irq_software_i, + input logic irq_timer_i, + input logic irq_external_i, + input logic [14:0] irq_fast_i, + input logic nmi_mode_i, + output logic irq_pending_o, // interrupt request pending + output ibex_pkg::irqs_t irqs_o, // interrupt requests qualified with mie + output logic csr_mstatus_mie_o, + output logic [31:0] csr_mepc_o, + + // PMP + output ibex_pkg::pmp_cfg_t csr_pmp_cfg_o [PMPNumRegions], + output logic [33:0] csr_pmp_addr_o [PMPNumRegions], + + // debug + input logic debug_mode_i, + input ibex_pkg::dbg_cause_e debug_cause_i, + input logic debug_csr_save_i, + output logic [31:0] csr_depc_o, + output logic debug_single_step_o, + output logic debug_ebreakm_o, + output logic debug_ebreaku_o, + output logic trigger_match_o, + + input logic [31:0] pc_if_i, + input logic [31:0] pc_id_i, + input logic [31:0] pc_wb_i, + + // CPU control bits + output logic data_ind_timing_o, + output logic dummy_instr_en_o, + output logic [2:0] dummy_instr_mask_o, + output logic dummy_instr_seed_en_o, + output logic [31:0] dummy_instr_seed_o, + output logic icache_enable_o, + output logic csr_shadow_err_o, + + // Exception save/restore + input logic csr_save_if_i, + input logic csr_save_id_i, + input logic csr_save_wb_i, + input logic csr_restore_mret_i, + input logic csr_restore_dret_i, + input logic csr_save_cause_i, + input ibex_pkg::exc_cause_e csr_mcause_i, + input logic [31:0] csr_mtval_i, + output logic illegal_csr_insn_o, // access to non-existent CSR, + // with wrong priviledge level, or + // missing write permissions + // Performance Counters + input logic instr_ret_i, // instr retired in ID/EX stage + input logic instr_ret_compressed_i, // compressed instr retired + input logic iside_wait_i, // core waiting for the iside + input logic jump_i, // jump instr seen (j, jr, jal, jalr) + input logic branch_i, // branch instr seen (bf, bnf) + input logic branch_taken_i, // branch was taken + input logic mem_load_i, // load from memory in this cycle + input logic mem_store_i, // store to memory in this cycle + input logic dside_wait_i, // core waiting for the dside + input logic mul_wait_i, // core waiting for multiply + input logic div_wait_i // core waiting for divide +); + + import ibex_pkg::*; + + localparam int unsigned RV32MEnabled = (RV32M == RV32MNone) ? 0 : 1; + localparam int unsigned PMPAddrWidth = (PMPGranularity > 0) ? 33 - PMPGranularity : 32; + + // misa + localparam logic [31:0] MISA_VALUE = + (0 << 0) // A - Atomic Instructions extension + | (1 << 2) // C - Compressed extension + | (0 << 3) // D - Double precision floating-point extension + | (32'(RV32E) << 4) // E - RV32E base ISA + | (0 << 5) // F - Single precision floating-point extension + | (32'(!RV32E) << 8) // I - RV32I/64I/128I base ISA + | (RV32MEnabled << 12) // M - Integer Multiply/Divide extension + | (0 << 13) // N - User level interrupts supported + | (0 << 18) // S - Supervisor mode implemented + | (1 << 20) // U - User mode implemented + | (0 << 23) // X - Non-standard extensions present + | (32'(CSR_MISA_MXL) << 30); // M-XLEN + + typedef struct packed { + logic mie; + logic mpie; + priv_lvl_e mpp; + logic mprv; + logic tw; + } status_t; + + typedef struct packed { + logic mpie; + priv_lvl_e mpp; + } status_stk_t; + + typedef struct packed { + x_debug_ver_e xdebugver; + logic [11:0] zero2; + logic ebreakm; + logic zero1; + logic ebreaks; + logic ebreaku; + logic stepie; + logic stopcount; + logic stoptime; + dbg_cause_e cause; + logic zero0; + logic mprven; + logic nmip; + logic step; + priv_lvl_e prv; + } dcsr_t; + + // CPU control register fields + typedef struct packed { + logic [2:0] dummy_instr_mask; + logic dummy_instr_en; + logic data_ind_timing; + logic icache_enable; + } cpu_ctrl_t; + + // Interrupt and exception control signals + logic [31:0] exception_pc; + + // CSRs + priv_lvl_e priv_lvl_q, priv_lvl_d; + status_t mstatus_q, mstatus_d; + logic mstatus_err; + logic mstatus_en; + irqs_t mie_q, mie_d; + logic mie_en; + logic [31:0] mscratch_q; + logic mscratch_en; + logic [31:0] mepc_q, mepc_d; + logic mepc_en; + logic [5:0] mcause_q, mcause_d; + logic mcause_en; + logic [31:0] mtval_q, mtval_d; + logic mtval_en; + logic [31:0] mtvec_q, mtvec_d; + logic mtvec_err; + logic mtvec_en; + irqs_t mip; + dcsr_t dcsr_q, dcsr_d; + logic dcsr_en; + logic [31:0] depc_q, depc_d; + logic depc_en; + logic [31:0] dscratch0_q; + logic [31:0] dscratch1_q; + logic dscratch0_en, dscratch1_en; + + // CSRs for recoverable NMIs + // NOTE: these CSRS are nonstandard, see https://github.com/riscv/riscv-isa-manual/issues/261 + status_stk_t mstack_q, mstack_d; + logic mstack_en; + logic [31:0] mstack_epc_q, mstack_epc_d; + logic [5:0] mstack_cause_q, mstack_cause_d; + + // PMP Signals + logic [31:0] pmp_addr_rdata [PMP_MAX_REGIONS]; + logic [PMP_CFG_W-1:0] pmp_cfg_rdata [PMP_MAX_REGIONS]; + logic pmp_csr_err; + + // Hardware performance monitor signals + logic [31:0] mcountinhibit; + // Only have mcountinhibit flops for counters that actually exist + logic [MHPMCounterNum+3-1:0] mcountinhibit_d, mcountinhibit_q; + logic mcountinhibit_we; + + // mhpmcounter flops are elaborated below providing only the precise number that is required based + // on MHPMCounterNum/MHPMCounterWidth. This signal connects to the Q output of these flops + // where they exist and is otherwise 0. + logic [63:0] mhpmcounter [32]; + logic [31:0] mhpmcounter_we; + logic [31:0] mhpmcounterh_we; + logic [31:0] mhpmcounter_incr; + logic [31:0] mhpmevent [32]; + logic [4:0] mhpmcounter_idx; + logic unused_mhpmcounter_we_1; + logic unused_mhpmcounterh_we_1; + logic unused_mhpmcounter_incr_1; + + // Debug / trigger registers + logic [31:0] tselect_rdata; + logic [31:0] tmatch_control_rdata; + logic [31:0] tmatch_value_rdata; + + // CPU control bits + cpu_ctrl_t cpuctrl_q, cpuctrl_d, cpuctrl_wdata; + logic cpuctrl_we; + logic cpuctrl_err; + + // CSR update logic + logic [31:0] csr_wdata_int; + logic [31:0] csr_rdata_int; + logic csr_we_int; + logic csr_wreq; + + // Access violation signals + logic illegal_csr; + logic illegal_csr_priv; + logic illegal_csr_write; + + logic [7:0] unused_boot_addr; + logic [2:0] unused_csr_addr; + + assign unused_boot_addr = boot_addr_i[7:0]; + + ///////////// + // CSR reg // + ///////////// + + logic [$bits(csr_num_e)-1:0] csr_addr; + assign csr_addr = {csr_addr_i}; + assign unused_csr_addr = csr_addr[7:5]; + assign mhpmcounter_idx = csr_addr[4:0]; + + // See RISC-V Privileged Specification, version 1.11, Section 2.1 + assign illegal_csr_priv = (csr_addr[9:8] > {priv_lvl_q}); + assign illegal_csr_write = (csr_addr[11:10] == 2'b11) && csr_wreq; + assign illegal_csr_insn_o = csr_access_i & (illegal_csr | illegal_csr_write | illegal_csr_priv); + + // mip CSR is purely combinational - must be able to re-enable the clock upon WFI + assign mip.irq_software = irq_software_i; + assign mip.irq_timer = irq_timer_i; + assign mip.irq_external = irq_external_i; + assign mip.irq_fast = irq_fast_i; + + // read logic + always_comb begin + csr_rdata_int = '0; + illegal_csr = 1'b0; + + unique case (csr_addr_i) + // mhartid: unique hardware thread id + CSR_MHARTID: csr_rdata_int = hart_id_i; + + // mstatus: always M-mode, contains IE bit + CSR_MSTATUS: begin + csr_rdata_int = '0; + csr_rdata_int[CSR_MSTATUS_MIE_BIT] = mstatus_q.mie; + csr_rdata_int[CSR_MSTATUS_MPIE_BIT] = mstatus_q.mpie; + csr_rdata_int[CSR_MSTATUS_MPP_BIT_HIGH:CSR_MSTATUS_MPP_BIT_LOW] = mstatus_q.mpp; + csr_rdata_int[CSR_MSTATUS_MPRV_BIT] = mstatus_q.mprv; + csr_rdata_int[CSR_MSTATUS_TW_BIT] = mstatus_q.tw; + end + + // misa + CSR_MISA: csr_rdata_int = MISA_VALUE; + + // interrupt enable + CSR_MIE: begin + csr_rdata_int = '0; + csr_rdata_int[CSR_MSIX_BIT] = mie_q.irq_software; + csr_rdata_int[CSR_MTIX_BIT] = mie_q.irq_timer; + csr_rdata_int[CSR_MEIX_BIT] = mie_q.irq_external; + csr_rdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] = mie_q.irq_fast; + end + + CSR_MSCRATCH: csr_rdata_int = mscratch_q; + + // mtvec: trap-vector base address + CSR_MTVEC: csr_rdata_int = mtvec_q; + + // mepc: exception program counter + CSR_MEPC: csr_rdata_int = mepc_q; + + // mcause: exception cause + CSR_MCAUSE: csr_rdata_int = {mcause_q[5], 26'b0, mcause_q[4:0]}; + + // mtval: trap value + CSR_MTVAL: csr_rdata_int = mtval_q; + + // mip: interrupt pending + CSR_MIP: begin + csr_rdata_int = '0; + csr_rdata_int[CSR_MSIX_BIT] = mip.irq_software; + csr_rdata_int[CSR_MTIX_BIT] = mip.irq_timer; + csr_rdata_int[CSR_MEIX_BIT] = mip.irq_external; + csr_rdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] = mip.irq_fast; + end + + // PMP registers + CSR_PMPCFG0: csr_rdata_int = {pmp_cfg_rdata[3], pmp_cfg_rdata[2], + pmp_cfg_rdata[1], pmp_cfg_rdata[0]}; + CSR_PMPCFG1: csr_rdata_int = {pmp_cfg_rdata[7], pmp_cfg_rdata[6], + pmp_cfg_rdata[5], pmp_cfg_rdata[4]}; + CSR_PMPCFG2: csr_rdata_int = {pmp_cfg_rdata[11], pmp_cfg_rdata[10], + pmp_cfg_rdata[9], pmp_cfg_rdata[8]}; + CSR_PMPCFG3: csr_rdata_int = {pmp_cfg_rdata[15], pmp_cfg_rdata[14], + pmp_cfg_rdata[13], pmp_cfg_rdata[12]}; + CSR_PMPADDR0: csr_rdata_int = pmp_addr_rdata[0]; + CSR_PMPADDR1: csr_rdata_int = pmp_addr_rdata[1]; + CSR_PMPADDR2: csr_rdata_int = pmp_addr_rdata[2]; + CSR_PMPADDR3: csr_rdata_int = pmp_addr_rdata[3]; + CSR_PMPADDR4: csr_rdata_int = pmp_addr_rdata[4]; + CSR_PMPADDR5: csr_rdata_int = pmp_addr_rdata[5]; + CSR_PMPADDR6: csr_rdata_int = pmp_addr_rdata[6]; + CSR_PMPADDR7: csr_rdata_int = pmp_addr_rdata[7]; + CSR_PMPADDR8: csr_rdata_int = pmp_addr_rdata[8]; + CSR_PMPADDR9: csr_rdata_int = pmp_addr_rdata[9]; + CSR_PMPADDR10: csr_rdata_int = pmp_addr_rdata[10]; + CSR_PMPADDR11: csr_rdata_int = pmp_addr_rdata[11]; + CSR_PMPADDR12: csr_rdata_int = pmp_addr_rdata[12]; + CSR_PMPADDR13: csr_rdata_int = pmp_addr_rdata[13]; + CSR_PMPADDR14: csr_rdata_int = pmp_addr_rdata[14]; + CSR_PMPADDR15: csr_rdata_int = pmp_addr_rdata[15]; + + CSR_DCSR: begin + csr_rdata_int = dcsr_q; + illegal_csr = ~debug_mode_i; + end + CSR_DPC: begin + csr_rdata_int = depc_q; + illegal_csr = ~debug_mode_i; + end + CSR_DSCRATCH0: begin + csr_rdata_int = dscratch0_q; + illegal_csr = ~debug_mode_i; + end + CSR_DSCRATCH1: begin + csr_rdata_int = dscratch1_q; + illegal_csr = ~debug_mode_i; + end + + // machine counter/timers + CSR_MCOUNTINHIBIT: csr_rdata_int = mcountinhibit; + CSR_MHPMEVENT3, + CSR_MHPMEVENT4, CSR_MHPMEVENT5, CSR_MHPMEVENT6, CSR_MHPMEVENT7, + CSR_MHPMEVENT8, CSR_MHPMEVENT9, CSR_MHPMEVENT10, CSR_MHPMEVENT11, + CSR_MHPMEVENT12, CSR_MHPMEVENT13, CSR_MHPMEVENT14, CSR_MHPMEVENT15, + CSR_MHPMEVENT16, CSR_MHPMEVENT17, CSR_MHPMEVENT18, CSR_MHPMEVENT19, + CSR_MHPMEVENT20, CSR_MHPMEVENT21, CSR_MHPMEVENT22, CSR_MHPMEVENT23, + CSR_MHPMEVENT24, CSR_MHPMEVENT25, CSR_MHPMEVENT26, CSR_MHPMEVENT27, + CSR_MHPMEVENT28, CSR_MHPMEVENT29, CSR_MHPMEVENT30, CSR_MHPMEVENT31: begin + csr_rdata_int = mhpmevent[mhpmcounter_idx]; + end + + CSR_MCYCLE, + CSR_MINSTRET, + CSR_MHPMCOUNTER3, + CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER7, + CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER9, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER11, + CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER15, + CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER19, + CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER23, + CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER27, + CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER31: begin + csr_rdata_int = mhpmcounter[mhpmcounter_idx][31:0]; + end + + CSR_MCYCLEH, + CSR_MINSTRETH, + CSR_MHPMCOUNTER3H, + CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7H, + CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9H, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H, + CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H, + CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H, + CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H, + CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H, + CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H: begin + csr_rdata_int = mhpmcounter[mhpmcounter_idx][63:32]; + end + + // Debug triggers + CSR_TSELECT: begin + csr_rdata_int = tselect_rdata; + illegal_csr = ~DbgTriggerEn; + end + CSR_TDATA1: begin + csr_rdata_int = tmatch_control_rdata; + illegal_csr = ~DbgTriggerEn; + end + CSR_TDATA2: begin + csr_rdata_int = tmatch_value_rdata; + illegal_csr = ~DbgTriggerEn; + end + CSR_TDATA3: begin + csr_rdata_int = '0; + illegal_csr = ~DbgTriggerEn; + end + CSR_MCONTEXT: begin + csr_rdata_int = '0; + illegal_csr = ~DbgTriggerEn; + end + CSR_SCONTEXT: begin + csr_rdata_int = '0; + illegal_csr = ~DbgTriggerEn; + end + + // Custom CSR for controlling CPU features + CSR_CPUCTRL: begin + csr_rdata_int = {{32-$bits(cpu_ctrl_t){1'b0}},cpuctrl_q}; + end + + // Custom CSR for LFSR re-seeding (cannot be read) + CSR_SECURESEED: begin + csr_rdata_int = '0; + end + + default: begin + illegal_csr = 1'b1; + end + endcase + end + + // write logic + always_comb begin + exception_pc = pc_id_i; + + priv_lvl_d = priv_lvl_q; + mstatus_en = 1'b0; + mstatus_d = mstatus_q; + mie_en = 1'b0; + mscratch_en = 1'b0; + mepc_en = 1'b0; + mepc_d = {csr_wdata_int[31:1], 1'b0}; + mcause_en = 1'b0; + mcause_d = {csr_wdata_int[31], csr_wdata_int[4:0]}; + mtval_en = 1'b0; + mtval_d = csr_wdata_int; + mtvec_en = csr_mtvec_init_i; + // mtvec.MODE set to vectored + // mtvec.BASE must be 256-byte aligned + mtvec_d = csr_mtvec_init_i ? {boot_addr_i[31:8], 6'b0, 2'b01} : + {csr_wdata_int[31:8], 6'b0, 2'b01}; + dcsr_en = 1'b0; + dcsr_d = dcsr_q; + depc_d = {csr_wdata_int[31:1], 1'b0}; + depc_en = 1'b0; + dscratch0_en = 1'b0; + dscratch1_en = 1'b0; + + mstack_en = 1'b0; + mstack_d.mpie = mstatus_q.mpie; + mstack_d.mpp = mstatus_q.mpp; + mstack_epc_d = mepc_q; + mstack_cause_d = mcause_q; + + mcountinhibit_we = 1'b0; + mhpmcounter_we = '0; + mhpmcounterh_we = '0; + + cpuctrl_we = 1'b0; + + if (csr_we_int) begin + unique case (csr_addr_i) + // mstatus: IE bit + CSR_MSTATUS: begin + mstatus_en = 1'b1; + mstatus_d = '{ + mie: csr_wdata_int[CSR_MSTATUS_MIE_BIT], + mpie: csr_wdata_int[CSR_MSTATUS_MPIE_BIT], + mpp: priv_lvl_e'(csr_wdata_int[CSR_MSTATUS_MPP_BIT_HIGH:CSR_MSTATUS_MPP_BIT_LOW]), + mprv: csr_wdata_int[CSR_MSTATUS_MPRV_BIT], + tw: csr_wdata_int[CSR_MSTATUS_TW_BIT] + }; + // Convert illegal values to M-mode + if ((mstatus_d.mpp != PRIV_LVL_M) && (mstatus_d.mpp != PRIV_LVL_U)) begin + mstatus_d.mpp = PRIV_LVL_M; + end + end + + // interrupt enable + CSR_MIE: mie_en = 1'b1; + + CSR_MSCRATCH: mscratch_en = 1'b1; + + // mepc: exception program counter + CSR_MEPC: mepc_en = 1'b1; + + // mcause + CSR_MCAUSE: mcause_en = 1'b1; + + // mtval: trap value + CSR_MTVAL: mtval_en = 1'b1; + + // mtvec + CSR_MTVEC: mtvec_en = 1'b1; + + CSR_DCSR: begin + dcsr_d = csr_wdata_int; + dcsr_d.xdebugver = XDEBUGVER_STD; + // Change to PRIV_LVL_M if software writes an unsupported value + if ((dcsr_d.prv != PRIV_LVL_M) && (dcsr_d.prv != PRIV_LVL_U)) begin + dcsr_d.prv = PRIV_LVL_M; + end + + // Read-only for SW + dcsr_d.cause = dcsr_q.cause; + + // currently not supported: + dcsr_d.nmip = 1'b0; + dcsr_d.mprven = 1'b0; + dcsr_d.stopcount = 1'b0; + dcsr_d.stoptime = 1'b0; + + // forced to be zero + dcsr_d.zero0 = 1'b0; + dcsr_d.zero1 = 1'b0; + dcsr_d.zero2 = 12'h0; + dcsr_en = 1'b1; + end + + // dpc: debug program counter + CSR_DPC: depc_en = 1'b1; + + CSR_DSCRATCH0: dscratch0_en = 1'b1; + CSR_DSCRATCH1: dscratch1_en = 1'b1; + + // machine counter/timers + CSR_MCOUNTINHIBIT: mcountinhibit_we = 1'b1; + + CSR_MCYCLE, + CSR_MINSTRET, + CSR_MHPMCOUNTER3, + CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER7, + CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER9, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER11, + CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER15, + CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER19, + CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER23, + CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER27, + CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER31: begin + mhpmcounter_we[mhpmcounter_idx] = 1'b1; + end + + CSR_MCYCLEH, + CSR_MINSTRETH, + CSR_MHPMCOUNTER3H, + CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7H, + CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9H, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H, + CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H, + CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H, + CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H, + CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H, + CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H: begin + mhpmcounterh_we[mhpmcounter_idx] = 1'b1; + end + + CSR_CPUCTRL: cpuctrl_we = 1'b1; + + default:; + endcase + end + + // exception controller gets priority over other writes + unique case (1'b1) + + csr_save_cause_i: begin + unique case (1'b1) + csr_save_if_i: begin + exception_pc = pc_if_i; + end + csr_save_id_i: begin + exception_pc = pc_id_i; + end + csr_save_wb_i: begin + exception_pc = pc_wb_i; + end + default:; + endcase + + // Any exception, including debug mode, causes a switch to M-mode + priv_lvl_d = PRIV_LVL_M; + + if (debug_csr_save_i) begin + // all interrupts are masked + // do not update cause, epc, tval, epc and status + dcsr_d.prv = priv_lvl_q; + dcsr_d.cause = debug_cause_i; + dcsr_en = 1'b1; + depc_d = exception_pc; + depc_en = 1'b1; + end else if (!debug_mode_i) begin + // In debug mode, "exceptions do not update any registers. That + // includes cause, epc, tval, dpc and mstatus." [Debug Spec v0.13.2, p.39] + mtval_en = 1'b1; + mtval_d = csr_mtval_i; + mstatus_en = 1'b1; + mstatus_d.mie = 1'b0; // disable interrupts + // save current status + mstatus_d.mpie = mstatus_q.mie; + mstatus_d.mpp = priv_lvl_q; + mepc_en = 1'b1; + mepc_d = exception_pc; + mcause_en = 1'b1; + mcause_d = {csr_mcause_i}; + // save previous status for recoverable NMI + mstack_en = 1'b1; + end + end // csr_save_cause_i + + csr_restore_dret_i: begin // DRET + priv_lvl_d = dcsr_q.prv; + end // csr_restore_dret_i + + csr_restore_mret_i: begin // MRET + priv_lvl_d = mstatus_q.mpp; + mstatus_en = 1'b1; + mstatus_d.mie = mstatus_q.mpie; // re-enable interrupts + + if (nmi_mode_i) begin + // when returning from an NMI restore state from mstack CSR + mstatus_d.mpie = mstack_q.mpie; + mstatus_d.mpp = mstack_q.mpp; + mepc_en = 1'b1; + mepc_d = mstack_epc_q; + mcause_en = 1'b1; + mcause_d = mstack_cause_q; + end else begin + // otherwise just set mstatus.MPIE/MPP + // See RISC-V Privileged Specification, version 1.11, Section 3.1.6.1 + mstatus_d.mpie = 1'b1; + mstatus_d.mpp = PRIV_LVL_U; + end + end // csr_restore_mret_i + + default:; + endcase + end + + // Update current priv level + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + priv_lvl_q <= PRIV_LVL_M; + end else begin + priv_lvl_q <= priv_lvl_d; + end + end + + // Send current priv level to the decoder + assign priv_mode_id_o = priv_lvl_q; + // New instruction fetches need to account for updates to priv_lvl_q this cycle + assign priv_mode_if_o = priv_lvl_d; + // Load/store instructions must factor in MPRV for PMP checking + assign priv_mode_lsu_o = mstatus_q.mprv ? mstatus_q.mpp : priv_lvl_q; + + // CSR operation logic + always_comb begin + unique case (csr_op_i) + CSR_OP_WRITE: csr_wdata_int = csr_wdata_i; + CSR_OP_SET: csr_wdata_int = csr_wdata_i | csr_rdata_o; + CSR_OP_CLEAR: csr_wdata_int = ~csr_wdata_i & csr_rdata_o; + CSR_OP_READ: csr_wdata_int = csr_wdata_i; + default: csr_wdata_int = csr_wdata_i; + endcase + end + + assign csr_wreq = csr_op_en_i & + (csr_op_i inside {CSR_OP_WRITE, + CSR_OP_SET, + CSR_OP_CLEAR}); + + // only write CSRs during one clock cycle + assign csr_we_int = csr_wreq & ~illegal_csr_insn_o; + + assign csr_rdata_o = csr_rdata_int; + + // directly output some registers + assign csr_mepc_o = mepc_q; + assign csr_depc_o = depc_q; + assign csr_mtvec_o = mtvec_q; + + assign csr_mstatus_mie_o = mstatus_q.mie; + assign csr_mstatus_tw_o = mstatus_q.tw; + assign debug_single_step_o = dcsr_q.step; + assign debug_ebreakm_o = dcsr_q.ebreakm; + assign debug_ebreaku_o = dcsr_q.ebreaku; + + // Qualify incoming interrupt requests in mip CSR with mie CSR for controller and to re-enable + // clock upon WFI (must be purely combinational). + assign irqs_o = mip & mie_q; + assign irq_pending_o = |irqs_o; + + //////////////////////// + // CSR instantiations // + //////////////////////// + + // MSTATUS + localparam status_t MSTATUS_RST_VAL = '{mie: 1'b0, + mpie: 1'b1, + mpp: PRIV_LVL_U, + mprv: 1'b0, + tw: 1'b0}; + ibex_csr #( + .Width ($bits(status_t)), + .ShadowCopy (ShadowCSR), + .ResetValue ({MSTATUS_RST_VAL}) + ) u_mstatus_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i ({mstatus_d}), + .wr_en_i (mstatus_en), + .rd_data_o (mstatus_q), + .rd_error_o (mstatus_err) + ); + + // MEPC + ibex_csr #( + .Width (32), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_mepc_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (mepc_d), + .wr_en_i (mepc_en), + .rd_data_o (mepc_q), + .rd_error_o () + ); + + // MIE + assign mie_d.irq_software = csr_wdata_int[CSR_MSIX_BIT]; + assign mie_d.irq_timer = csr_wdata_int[CSR_MTIX_BIT]; + assign mie_d.irq_external = csr_wdata_int[CSR_MEIX_BIT]; + assign mie_d.irq_fast = csr_wdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW]; + ibex_csr #( + .Width ($bits(irqs_t)), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_mie_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i ({mie_d}), + .wr_en_i (mie_en), + .rd_data_o (mie_q), + .rd_error_o () + ); + + // MSCRATCH + ibex_csr #( + .Width (32), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_mscratch_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (csr_wdata_int), + .wr_en_i (mscratch_en), + .rd_data_o (mscratch_q), + .rd_error_o () + ); + + // MCAUSE + ibex_csr #( + .Width (6), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_mcause_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (mcause_d), + .wr_en_i (mcause_en), + .rd_data_o (mcause_q), + .rd_error_o () + ); + + // MTVAL + ibex_csr #( + .Width (32), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_mtval_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (mtval_d), + .wr_en_i (mtval_en), + .rd_data_o (mtval_q), + .rd_error_o () + ); + + // MTVEC + ibex_csr #( + .Width (32), + .ShadowCopy (ShadowCSR), + .ResetValue (32'd1) + ) u_mtvec_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (mtvec_d), + .wr_en_i (mtvec_en), + .rd_data_o (mtvec_q), + .rd_error_o (mtvec_err) + ); + + // DCSR + localparam dcsr_t DCSR_RESET_VAL = '{ + xdebugver: XDEBUGVER_STD, + cause: DBG_CAUSE_NONE, // 3'h0 + prv: PRIV_LVL_M, + default: '0 + }; + ibex_csr #( + .Width ($bits(dcsr_t)), + .ShadowCopy (1'b0), + .ResetValue ({DCSR_RESET_VAL}) + ) u_dcsr_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i ({dcsr_d}), + .wr_en_i (dcsr_en), + .rd_data_o (dcsr_q), + .rd_error_o () + ); + + // DEPC + ibex_csr #( + .Width (32), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_depc_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (depc_d), + .wr_en_i (depc_en), + .rd_data_o (depc_q), + .rd_error_o () + ); + + // DSCRATCH0 + ibex_csr #( + .Width (32), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_dscratch0_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (csr_wdata_int), + .wr_en_i (dscratch0_en), + .rd_data_o (dscratch0_q), + .rd_error_o () + ); + + // DSCRATCH1 + ibex_csr #( + .Width (32), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_dscratch1_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (csr_wdata_int), + .wr_en_i (dscratch1_en), + .rd_data_o (dscratch1_q), + .rd_error_o () + ); + + // MSTACK + localparam status_stk_t MSTACK_RESET_VAL = '{ + mpie: 1'b1, + mpp: PRIV_LVL_U + }; + ibex_csr #( + .Width ($bits(status_stk_t)), + .ShadowCopy (1'b0), + .ResetValue ({MSTACK_RESET_VAL}) + ) u_mstack_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i ({mstack_d}), + .wr_en_i (mstack_en), + .rd_data_o (mstack_q), + .rd_error_o () + ); + + // MSTACK_EPC + ibex_csr #( + .Width (32), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_mstack_epc_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (mstack_epc_d), + .wr_en_i (mstack_en), + .rd_data_o (mstack_epc_q), + .rd_error_o () + ); + + // MSTACK_CAUSE + ibex_csr #( + .Width (6), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_mstack_cause_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (mstack_cause_d), + .wr_en_i (mstack_en), + .rd_data_o (mstack_cause_q), + .rd_error_o () + ); + + // ----------------- + // PMP registers + // ----------------- + + if (PMPEnable) begin : g_pmp_registers + pmp_cfg_t pmp_cfg [PMPNumRegions]; + pmp_cfg_t pmp_cfg_wdata [PMPNumRegions]; + logic [PMPAddrWidth-1:0] pmp_addr [PMPNumRegions]; + logic [PMPNumRegions-1:0] pmp_cfg_we; + logic [PMPNumRegions-1:0] pmp_cfg_err; + logic [PMPNumRegions-1:0] pmp_addr_we; + logic [PMPNumRegions-1:0] pmp_addr_err; + + // Expanded / qualified register read data + for (genvar i = 0; i < PMP_MAX_REGIONS; i++) begin : g_exp_rd_data + if (i < PMPNumRegions) begin : g_implemented_regions + // Add in zero padding for reserved fields + assign pmp_cfg_rdata[i] = {pmp_cfg[i].lock, 2'b00, pmp_cfg[i].mode, + pmp_cfg[i].exec, pmp_cfg[i].write, pmp_cfg[i].read}; + + // Address field read data depends on the current programmed mode and the granularity + // See RISC-V Privileged Specification, version 1.11, Section 3.6.1 + if (PMPGranularity == 0) begin : g_pmp_g0 + // If G == 0, read data is unmodified + assign pmp_addr_rdata[i] = pmp_addr[i]; + + end else if (PMPGranularity == 1) begin : g_pmp_g1 + // If G == 1, bit [G-1] reads as zero in TOR or OFF mode + always_comb begin + pmp_addr_rdata[i] = pmp_addr[i]; + if ((pmp_cfg[i].mode == PMP_MODE_OFF) || (pmp_cfg[i].mode == PMP_MODE_TOR)) begin + pmp_addr_rdata[i][PMPGranularity-1:0] = '0; + end + end + + end else begin : g_pmp_g2 + // For G >= 2, bits are masked to one or zero depending on the mode + always_comb begin + // In NAPOT mode, bits [G-2:0] must read as one + pmp_addr_rdata[i] = {pmp_addr[i], {PMPGranularity-1{1'b1}}}; + + if ((pmp_cfg[i].mode == PMP_MODE_OFF) || (pmp_cfg[i].mode == PMP_MODE_TOR)) begin + // In TOR or OFF mode, bits [G-1:0] must read as zero + pmp_addr_rdata[i][PMPGranularity-1:0] = '0; + end + end + end + + end else begin : g_other_regions + // Non-implemented regions read as zero + assign pmp_cfg_rdata[i] = '0; + assign pmp_addr_rdata[i] = '0; + end + end + + // Write data calculation + for (genvar i = 0; i < PMPNumRegions; i++) begin : g_pmp_csrs + // ------------------------- + // Instantiate cfg registers + // ------------------------- + assign pmp_cfg_we[i] = csr_we_int & ~pmp_cfg[i].lock & + (csr_addr == (CSR_OFF_PMP_CFG + (i[11:0] >> 2))); + + // Select the correct WDATA (each CSR contains 4 CFG fields, each with 2 RES bits) + assign pmp_cfg_wdata[i].lock = csr_wdata_int[(i%4)*PMP_CFG_W+7]; + // NA4 mode is not selectable when G > 0, mode is treated as OFF + always_comb begin + unique case (csr_wdata_int[(i%4)*PMP_CFG_W+3+:2]) + 2'b00 : pmp_cfg_wdata[i].mode = PMP_MODE_OFF; + 2'b01 : pmp_cfg_wdata[i].mode = PMP_MODE_TOR; + 2'b10 : pmp_cfg_wdata[i].mode = (PMPGranularity == 0) ? PMP_MODE_NA4: + PMP_MODE_OFF; + 2'b11 : pmp_cfg_wdata[i].mode = PMP_MODE_NAPOT; + default : pmp_cfg_wdata[i].mode = PMP_MODE_OFF; + endcase + end + assign pmp_cfg_wdata[i].exec = csr_wdata_int[(i%4)*PMP_CFG_W+2]; + // W = 1, R = 0 is a reserved combination. For now, we force W to 0 if R == 0 + assign pmp_cfg_wdata[i].write = &csr_wdata_int[(i%4)*PMP_CFG_W+:2]; + assign pmp_cfg_wdata[i].read = csr_wdata_int[(i%4)*PMP_CFG_W]; + + ibex_csr #( + .Width ($bits(pmp_cfg_t)), + .ShadowCopy (ShadowCSR), + .ResetValue ('0) + ) u_pmp_cfg_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i ({pmp_cfg_wdata[i]}), + .wr_en_i (pmp_cfg_we[i]), + .rd_data_o (pmp_cfg[i]), + .rd_error_o (pmp_cfg_err[i]) + ); + + // -------------------------- + // Instantiate addr registers + // -------------------------- + if (i < PMPNumRegions - 1) begin : g_lower + assign pmp_addr_we[i] = csr_we_int & ~pmp_cfg[i].lock & + (~pmp_cfg[i+1].lock | (pmp_cfg[i+1].mode != PMP_MODE_TOR)) & + (csr_addr == (CSR_OFF_PMP_ADDR + i[11:0])); + end else begin : g_upper + assign pmp_addr_we[i] = csr_we_int & ~pmp_cfg[i].lock & + (csr_addr == (CSR_OFF_PMP_ADDR + i[11:0])); + end + + ibex_csr #( + .Width (PMPAddrWidth), + .ShadowCopy (ShadowCSR), + .ResetValue ('0) + ) u_pmp_addr_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (csr_wdata_int[31-:PMPAddrWidth]), + .wr_en_i (pmp_addr_we[i]), + .rd_data_o (pmp_addr[i]), + .rd_error_o (pmp_addr_err[i]) + ); + + assign csr_pmp_cfg_o[i] = pmp_cfg[i]; + assign csr_pmp_addr_o[i] = {pmp_addr_rdata[i], 2'b00}; + end + + assign pmp_csr_err = (|pmp_cfg_err) | (|pmp_addr_err); + + end else begin : g_no_pmp_tieoffs + // Generate tieoffs when PMP is not configured + for (genvar i = 0; i < PMP_MAX_REGIONS; i++) begin : g_rdata + assign pmp_addr_rdata[i] = '0; + assign pmp_cfg_rdata[i] = '0; + end + for (genvar i = 0; i < PMPNumRegions; i++) begin : g_outputs + assign csr_pmp_cfg_o[i] = pmp_cfg_t'(1'b0); + assign csr_pmp_addr_o[i] = '0; + end + assign pmp_csr_err = 1'b0; + end + + ////////////////////////// + // Performance monitor // + ////////////////////////// + + // update enable signals + always_comb begin : mcountinhibit_update + if (mcountinhibit_we == 1'b1) begin + // bit 1 must always be 0 + mcountinhibit_d = {csr_wdata_int[MHPMCounterNum+2:2], 1'b0, csr_wdata_int[0]}; + end else begin + mcountinhibit_d = mcountinhibit_q; + end + end + + // event selection (hardwired) & control + always_comb begin : gen_mhpmcounter_incr + + // Assign inactive counters (first to prevent latch inference) + for (int unsigned i=0; i<32; i++) begin : gen_mhpmcounter_incr_inactive + mhpmcounter_incr[i] = 1'b0; + end + + // When adding or altering performance counter meanings and default + // mappings please update dv/verilator/pcount/cpp/ibex_pcounts.cc + // appropriately. + // + // active counters + mhpmcounter_incr[0] = 1'b1; // mcycle + mhpmcounter_incr[1] = 1'b0; // reserved + mhpmcounter_incr[2] = instr_ret_i; // minstret + mhpmcounter_incr[3] = dside_wait_i; // cycles waiting for data memory + mhpmcounter_incr[4] = iside_wait_i; // cycles waiting for instr fetches + mhpmcounter_incr[5] = mem_load_i; // num of loads + mhpmcounter_incr[6] = mem_store_i; // num of stores + mhpmcounter_incr[7] = jump_i; // num of jumps (unconditional) + mhpmcounter_incr[8] = branch_i; // num of branches (conditional) + mhpmcounter_incr[9] = branch_taken_i; // num of taken branches (conditional) + mhpmcounter_incr[10] = instr_ret_compressed_i; // num of compressed instr + mhpmcounter_incr[11] = mul_wait_i; // cycles waiting for multiply + mhpmcounter_incr[12] = div_wait_i; // cycles waiting for divide + end + + // event selector (hardwired, 0 means no event) + always_comb begin : gen_mhpmevent + + // activate all + for (int i=0; i<32; i++) begin : gen_mhpmevent_active + mhpmevent[i] = '0; + mhpmevent[i][i] = 1'b1; + end + + // deactivate + mhpmevent[1] = '0; // not existing, reserved + for (int unsigned i=3+MHPMCounterNum; i<32; i++) begin : gen_mhpmevent_inactive + mhpmevent[i] = '0; + end + end + + // mcycle + ibex_counter #( + .CounterWidth(64) + ) mcycle_counter_i ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .counter_inc_i(mhpmcounter_incr[0] & ~mcountinhibit[0]), + .counterh_we_i(mhpmcounterh_we[0]), + .counter_we_i(mhpmcounter_we[0]), + .counter_val_i(csr_wdata_int), + .counter_val_o(mhpmcounter[0]) + ); + + // minstret + ibex_counter #( + .CounterWidth(64) + ) minstret_counter_i ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .counter_inc_i(mhpmcounter_incr[2] & ~mcountinhibit[2]), + .counterh_we_i(mhpmcounterh_we[2]), + .counter_we_i(mhpmcounter_we[2]), + .counter_val_i(csr_wdata_int), + .counter_val_o(mhpmcounter[2]) + ); + + // reserved: + assign mhpmcounter[1] = '0; + assign unused_mhpmcounter_we_1 = mhpmcounter_we[1]; + assign unused_mhpmcounterh_we_1 = mhpmcounterh_we[1]; + assign unused_mhpmcounter_incr_1 = mhpmcounter_incr[1]; + + for (genvar cnt=0; cnt < 29; cnt++) begin : gen_cntrs + if (cnt < MHPMCounterNum) begin : gen_imp + ibex_counter #( + .CounterWidth(MHPMCounterWidth) + ) mcounters_variable_i ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .counter_inc_i(mhpmcounter_incr[cnt+3] & ~mcountinhibit[cnt+3]), + .counterh_we_i(mhpmcounterh_we[cnt+3]), + .counter_we_i(mhpmcounter_we[cnt+3]), + .counter_val_i(csr_wdata_int), + .counter_val_o(mhpmcounter[cnt+3]) + ); + end else begin : gen_unimp + assign mhpmcounter[cnt+3] = '0; + end + end + + if(MHPMCounterNum < 29) begin : g_mcountinhibit_reduced + logic [29-MHPMCounterNum-1:0] unused_mhphcounter_we; + logic [29-MHPMCounterNum-1:0] unused_mhphcounterh_we; + logic [29-MHPMCounterNum-1:0] unused_mhphcounter_incr; + + assign mcountinhibit = {{29-MHPMCounterNum{1'b1}}, mcountinhibit_q}; + // Lint tieoffs for unused bits + assign unused_mhphcounter_we = mhpmcounter_we[31:MHPMCounterNum+3]; + assign unused_mhphcounterh_we = mhpmcounterh_we[31:MHPMCounterNum+3]; + assign unused_mhphcounter_incr = mhpmcounter_incr[31:MHPMCounterNum+3]; + end else begin : g_mcountinhibit_full + assign mcountinhibit = mcountinhibit_q; + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + mcountinhibit_q <= '0; + end else begin + mcountinhibit_q <= mcountinhibit_d; + end + end + + ///////////////////////////// + // Debug trigger registers // + ///////////////////////////// + + if (DbgTriggerEn) begin : gen_trigger_regs + localparam int unsigned DbgHwNumLen = DbgHwBreakNum > 1 ? $clog2(DbgHwBreakNum) : 1; + // Register values + logic [DbgHwNumLen-1:0] tselect_d, tselect_q; + logic tmatch_control_d; + logic [DbgHwBreakNum-1:0] tmatch_control_q; + logic [31:0] tmatch_value_d; + logic [31:0] tmatch_value_q[DbgHwBreakNum]; + // Write enables + logic tselect_we; + logic [DbgHwBreakNum-1:0] tmatch_control_we; + logic [DbgHwBreakNum-1:0] tmatch_value_we; + // Trigger comparison result + logic [DbgHwBreakNum-1:0] trigger_match; + + // Write select + assign tselect_we = csr_we_int & debug_mode_i & (csr_addr_i == CSR_TSELECT); + for (genvar i = 0; i < DbgHwBreakNum; i++) begin : g_dbg_tmatch_we + assign tmatch_control_we[i] = (i[DbgHwNumLen-1:0] == tselect_q) & csr_we_int & debug_mode_i & + (csr_addr_i == CSR_TDATA1); + assign tmatch_value_we[i] = (i[DbgHwNumLen-1:0] == tselect_q) & csr_we_int & debug_mode_i & + (csr_addr_i == CSR_TDATA2); + end + + // Debug interface tests the available number of triggers by writing and reading the trigger + // select register. Only allow changes to the register if it is within the supported region. + assign tselect_d = (csr_wdata_int < DbgHwBreakNum) ? csr_wdata_int[DbgHwNumLen-1:0] : + DbgHwBreakNum-1; + // tmatch_control is enabled when the execute bit is set + assign tmatch_control_d = csr_wdata_int[2]; + assign tmatch_value_d = csr_wdata_int[31:0]; + + // Registers + ibex_csr #( + .Width (DbgHwNumLen), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_tselect_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (tselect_d), + .wr_en_i (tselect_we), + .rd_data_o (tselect_q), + .rd_error_o () + ); + + for (genvar i = 0; i < DbgHwBreakNum; i++) begin : g_dbg_tmatch_reg + ibex_csr #( + .Width (1), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_tmatch_control_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (tmatch_control_d), + .wr_en_i (tmatch_control_we[i]), + .rd_data_o (tmatch_control_q[i]), + .rd_error_o () + ); + + ibex_csr #( + .Width (32), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_tmatch_value_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (tmatch_value_d), + .wr_en_i (tmatch_value_we[i]), + .rd_data_o (tmatch_value_q[i]), + .rd_error_o () + ); + end + + // Assign read data + // TSELECT - number of supported triggers defined by parameter DbgHwBreakNum + localparam int unsigned TSelectRdataPadlen = DbgHwNumLen >= 32 ? 0 : (32 - DbgHwNumLen); + assign tselect_rdata = {{TSelectRdataPadlen{1'b0}}, tselect_q}; + + // TDATA0 - only support simple address matching + assign tmatch_control_rdata = {4'h2, // type : address/data match + 1'b1, // dmode : access from D mode only + 6'h00, // maskmax : exact match only + 1'b0, // hit : not supported + 1'b0, // select : address match only + 1'b0, // timing : match before execution + 2'b00, // sizelo : match any access + 4'h1, // action : enter debug mode + 1'b0, // chain : not supported + 4'h0, // match : simple match + 1'b1, // m : match in m-mode + 1'b0, // 0 : zero + 1'b0, // s : not supported + 1'b1, // u : match in u-mode + tmatch_control_q[tselect_q], // execute : match instruction address + 1'b0, // store : not supported + 1'b0}; // load : not supported + // TDATA1 - address match value only + assign tmatch_value_rdata = tmatch_value_q[tselect_q]; + + // Breakpoint matching + // We match against the next address, as the breakpoint must be taken before execution + for (genvar i = 0; i < DbgHwBreakNum; i++) begin : g_dbg_trigger_match + assign trigger_match[i] = tmatch_control_q[i] & (pc_if_i[31:0] == tmatch_value_q[i]); + end + assign trigger_match_o = |trigger_match; + + end else begin : gen_no_trigger_regs + assign tselect_rdata = 'b0; + assign tmatch_control_rdata = 'b0; + assign tmatch_value_rdata = 'b0; + assign trigger_match_o = 'b0; + end + + ////////////////////////// + // CPU control register // + ////////////////////////// + + // Cast register write data + assign cpuctrl_wdata = cpu_ctrl_t'(csr_wdata_int[$bits(cpu_ctrl_t)-1:0]); + + // Generate fixed time execution bit + if (DataIndTiming) begin : gen_dit + assign cpuctrl_d.data_ind_timing = cpuctrl_wdata.data_ind_timing; + + end else begin : gen_no_dit + // tieoff for the unused bit + logic unused_dit; + assign unused_dit = cpuctrl_wdata.data_ind_timing; + + // field will always read as zero if not configured + assign cpuctrl_d.data_ind_timing = 1'b0; + end + + assign data_ind_timing_o = cpuctrl_q.data_ind_timing; + + // Generate dummy instruction signals + if (DummyInstructions) begin : gen_dummy + assign cpuctrl_d.dummy_instr_en = cpuctrl_wdata.dummy_instr_en; + assign cpuctrl_d.dummy_instr_mask = cpuctrl_wdata.dummy_instr_mask; + + // Signal a write to the seed register + assign dummy_instr_seed_en_o = csr_we_int && (csr_addr == CSR_SECURESEED); + assign dummy_instr_seed_o = csr_wdata_int; + + end else begin : gen_no_dummy + // tieoff for the unused bit + logic unused_dummy_en; + logic [2:0] unused_dummy_mask; + assign unused_dummy_en = cpuctrl_wdata.dummy_instr_en; + assign unused_dummy_mask = cpuctrl_wdata.dummy_instr_mask; + + // field will always read as zero if not configured + assign cpuctrl_d.dummy_instr_en = 1'b0; + assign cpuctrl_d.dummy_instr_mask = 3'b000; + assign dummy_instr_seed_en_o = 1'b0; + assign dummy_instr_seed_o = '0; + end + + assign dummy_instr_en_o = cpuctrl_q.dummy_instr_en; + assign dummy_instr_mask_o = cpuctrl_q.dummy_instr_mask; + + // Generate icache enable bit + if (ICache) begin : gen_icache_enable + assign cpuctrl_d.icache_enable = cpuctrl_wdata.icache_enable; + end else begin : gen_no_icache + // tieoff for the unused icen bit + logic unused_icen; + assign unused_icen = cpuctrl_wdata.icache_enable; + + // icen field will always read as zero if ICache not configured + assign cpuctrl_d.icache_enable = 1'b0; + end + + assign icache_enable_o = cpuctrl_q.icache_enable; + + ibex_csr #( + .Width ($bits(cpu_ctrl_t)), + .ShadowCopy (ShadowCSR), + .ResetValue ('0) + ) u_cpuctrl_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i ({cpuctrl_d}), + .wr_en_i (cpuctrl_we), + .rd_data_o (cpuctrl_q), + .rd_error_o (cpuctrl_err) + ); + + assign csr_shadow_err_o = mstatus_err | mtvec_err | pmp_csr_err | cpuctrl_err; + + //////////////// + // Assertions // + //////////////// + + `ASSERT(IbexCsrOpEnRequiresAccess, csr_op_en_i |-> csr_access_i) + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_csr.sv b/flow/designs/src/ibex_sv/ibex_csr.sv new file mode 100644 index 0000000000..8623fa552f --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_csr.sv @@ -0,0 +1,57 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Control / status register primitive + */ + +`include "prim_assert.sv" + +module ibex_csr #( + parameter int unsigned Width = 32, + parameter bit ShadowCopy = 1'b0, + parameter bit [Width-1:0] ResetValue = '0 + ) ( + input logic clk_i, + input logic rst_ni, + + input logic [Width-1:0] wr_data_i, + input logic wr_en_i, + output logic [Width-1:0] rd_data_o, + + output logic rd_error_o +); + + logic [Width-1:0] rdata_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rdata_q <= ResetValue; + end else if (wr_en_i) begin + rdata_q <= wr_data_i; + end + end + + assign rd_data_o = rdata_q; + + if (ShadowCopy) begin : gen_shadow + logic [Width-1:0] shadow_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + shadow_q <= ~ResetValue; + end else if (wr_en_i) begin + shadow_q <= ~wr_data_i; + end + end + + assign rd_error_o = rdata_q != ~shadow_q; + + end else begin : gen_no_shadow + assign rd_error_o = 1'b0; + end + + `ASSERT_KNOWN(IbexCSREnValid, wr_en_i) + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_decoder.sv b/flow/designs/src/ibex_sv/ibex_decoder.sv new file mode 100644 index 0000000000..b61520ed8c --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_decoder.sv @@ -0,0 +1,1155 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + + +/** + * Instruction decoder + * + * This module is fully combinatorial, clock and reset are used for + * assertions only. + */ + +`include "prim_assert.sv" + +module ibex_decoder #( + parameter bit RV32E = 0, + parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast, + parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone, + parameter bit BranchTargetALU = 0 +) ( + input logic clk_i, + input logic rst_ni, + + // to/from controller + output logic illegal_insn_o, // illegal instr encountered + output logic ebrk_insn_o, // trap instr encountered + output logic mret_insn_o, // return from exception instr + // encountered + output logic dret_insn_o, // return from debug instr encountered + output logic ecall_insn_o, // syscall instr encountered + output logic wfi_insn_o, // wait for interrupt instr encountered + output logic jump_set_o, // jump taken set signal + input logic branch_taken_i, // registered branch decision + output logic icache_inval_o, + + // from IF-ID pipeline register + input logic instr_first_cycle_i, // instruction read is in its first cycle + input logic [31:0] instr_rdata_i, // instruction read from memory/cache + input logic [31:0] instr_rdata_alu_i, // instruction read from memory/cache + // replicated to ease fan-out) + + input logic illegal_c_insn_i, // compressed instruction decode failed + + // immediates + output ibex_pkg::imm_a_sel_e imm_a_mux_sel_o, // immediate selection for operand a + output ibex_pkg::imm_b_sel_e imm_b_mux_sel_o, // immediate selection for operand b + output ibex_pkg::op_a_sel_e bt_a_mux_sel_o, // branch target selection operand a + output ibex_pkg::imm_b_sel_e bt_b_mux_sel_o, // branch target selection operand b + output logic [31:0] imm_i_type_o, + output logic [31:0] imm_s_type_o, + output logic [31:0] imm_b_type_o, + output logic [31:0] imm_u_type_o, + output logic [31:0] imm_j_type_o, + output logic [31:0] zimm_rs1_type_o, + + // register file + output ibex_pkg::rf_wd_sel_e rf_wdata_sel_o, // RF write data selection + output logic rf_we_o, // write enable for regfile + output logic [4:0] rf_raddr_a_o, + output logic [4:0] rf_raddr_b_o, + output logic [4:0] rf_waddr_o, + output logic rf_ren_a_o, // Instruction reads from RF addr A + output logic rf_ren_b_o, // Instruction reads from RF addr B + + // ALU + output ibex_pkg::alu_op_e alu_operator_o, // ALU operation selection + output ibex_pkg::op_a_sel_e alu_op_a_mux_sel_o, // operand a selection: reg value, PC, + // immediate or zero + output ibex_pkg::op_b_sel_e alu_op_b_mux_sel_o, // operand b selection: reg value or + // immediate + output logic alu_multicycle_o, // ternary bitmanip instruction + + // MULT & DIV + output logic mult_en_o, // perform integer multiplication + output logic div_en_o, // perform integer division or remainder + output logic mult_sel_o, // as above but static, for data muxes + output logic div_sel_o, // as above but static, for data muxes + + output ibex_pkg::md_op_e multdiv_operator_o, + output logic [1:0] multdiv_signed_mode_o, + + // CSRs + output logic csr_access_o, // access to CSR + output ibex_pkg::csr_op_e csr_op_o, // operation to perform on CSR + + // LSU + output logic data_req_o, // start transaction to data memory + output logic data_we_o, // write enable + output logic [1:0] data_type_o, // size of transaction: byte, half + // word or word + output logic data_sign_extension_o, // sign extension for data read from + // memory + + // jump/branches + output logic jump_in_dec_o, // jump is being calculated in ALU + output logic branch_in_dec_o +); + + import ibex_pkg::*; + + logic illegal_insn; + logic illegal_reg_rv32e; + logic csr_illegal; + logic rf_we; + + logic [31:0] instr; + logic [31:0] instr_alu; + logic [9:0] unused_instr_alu; + // Source/Destination register instruction index + logic [4:0] instr_rs1; + logic [4:0] instr_rs2; + logic [4:0] instr_rs3; + logic [4:0] instr_rd; + + logic use_rs3_d; + logic use_rs3_q; + + csr_op_e csr_op; + + opcode_e opcode; + opcode_e opcode_alu; + + // To help timing the flops containing the current instruction are replicated to reduce fan-out. + // instr_alu is used to determine the ALU control logic and associated operand/imm select signals + // as the ALU is often on the more critical timing paths. instr is used for everything else. + assign instr = instr_rdata_i; + assign instr_alu = instr_rdata_alu_i; + + ////////////////////////////////////// + // Register and immediate selection // + ////////////////////////////////////// + + // immediate extraction and sign extension + assign imm_i_type_o = { {20{instr[31]}}, instr[31:20] }; + assign imm_s_type_o = { {20{instr[31]}}, instr[31:25], instr[11:7] }; + assign imm_b_type_o = { {19{instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0 }; + assign imm_u_type_o = { instr[31:12], 12'b0 }; + assign imm_j_type_o = { {12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0 }; + + // immediate for CSR manipulation (zero extended) + assign zimm_rs1_type_o = { 27'b0, instr_rs1 }; // rs1 + + if (RV32B != RV32BNone) begin : gen_rs3_flop + // the use of rs3 is known one cycle ahead. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + use_rs3_q <= 1'b0; + end else begin + use_rs3_q <= use_rs3_d; + end + end + end else begin : gen_no_rs3_flop + // always zero + assign use_rs3_q = use_rs3_d; + end + + // source registers + assign instr_rs1 = instr[19:15]; + assign instr_rs2 = instr[24:20]; + assign instr_rs3 = instr[31:27]; + assign rf_raddr_a_o = (use_rs3_q & ~instr_first_cycle_i) ? instr_rs3 : instr_rs1; // rs3 / rs1 + assign rf_raddr_b_o = instr_rs2; // rs2 + + // destination register + assign instr_rd = instr[11:7]; + assign rf_waddr_o = instr_rd; // rd + + //////////////////// + // Register check // + //////////////////// + if (RV32E) begin : gen_rv32e_reg_check_active + assign illegal_reg_rv32e = ((rf_raddr_a_o[4] & (alu_op_a_mux_sel_o == OP_A_REG_A)) | + (rf_raddr_b_o[4] & (alu_op_b_mux_sel_o == OP_B_REG_B)) | + (rf_waddr_o[4] & rf_we)); + end else begin : gen_rv32e_reg_check_inactive + assign illegal_reg_rv32e = 1'b0; + end + + /////////////////////// + // CSR operand check // + /////////////////////// + always_comb begin : csr_operand_check + csr_op_o = csr_op; + + // CSRRSI/CSRRCI must not write 0 to CSRs (uimm[4:0]=='0) + // CSRRS/CSRRC must not write from x0 to CSRs (rs1=='0) + if ((csr_op == CSR_OP_SET || csr_op == CSR_OP_CLEAR) && + instr_rs1 == '0) begin + csr_op_o = CSR_OP_READ; + end + end + + ///////////// + // Decoder // + ///////////// + + always_comb begin + jump_in_dec_o = 1'b0; + jump_set_o = 1'b0; + branch_in_dec_o = 1'b0; + icache_inval_o = 1'b0; + + multdiv_operator_o = MD_OP_MULL; + multdiv_signed_mode_o = 2'b00; + + rf_wdata_sel_o = RF_WD_EX; + rf_we = 1'b0; + rf_ren_a_o = 1'b0; + rf_ren_b_o = 1'b0; + + csr_access_o = 1'b0; + csr_illegal = 1'b0; + csr_op = CSR_OP_READ; + + data_we_o = 1'b0; + data_type_o = 2'b00; + data_sign_extension_o = 1'b0; + data_req_o = 1'b0; + + illegal_insn = 1'b0; + ebrk_insn_o = 1'b0; + mret_insn_o = 1'b0; + dret_insn_o = 1'b0; + ecall_insn_o = 1'b0; + wfi_insn_o = 1'b0; + + opcode = opcode_e'(instr[6:0]); + + unique case (opcode) + + /////////// + // Jumps // + /////////// + + OPCODE_JAL: begin // Jump and Link + jump_in_dec_o = 1'b1; + + if (instr_first_cycle_i) begin + // Calculate jump target (and store PC + 4 if BranchTargetALU is configured) + rf_we = BranchTargetALU; + jump_set_o = 1'b1; + end else begin + // Calculate and store PC+4 + rf_we = 1'b1; + end + end + + OPCODE_JALR: begin // Jump and Link Register + jump_in_dec_o = 1'b1; + + if (instr_first_cycle_i) begin + // Calculate jump target (and store PC + 4 if BranchTargetALU is configured) + rf_we = BranchTargetALU; + jump_set_o = 1'b1; + end else begin + // Calculate and store PC+4 + rf_we = 1'b1; + end + if (instr[14:12] != 3'b0) begin + illegal_insn = 1'b1; + end + + rf_ren_a_o = 1'b1; + end + + OPCODE_BRANCH: begin // Branch + branch_in_dec_o = 1'b1; + // Check branch condition selection + unique case (instr[14:12]) + 3'b000, + 3'b001, + 3'b100, + 3'b101, + 3'b110, + 3'b111: illegal_insn = 1'b0; + default: illegal_insn = 1'b1; + endcase + + rf_ren_a_o = 1'b1; + rf_ren_b_o = 1'b1; + end + + //////////////// + // Load/store // + //////////////// + + OPCODE_STORE: begin + rf_ren_a_o = 1'b1; + rf_ren_b_o = 1'b1; + data_req_o = 1'b1; + data_we_o = 1'b1; + + if (instr[14]) begin + illegal_insn = 1'b1; + end + + // store size + unique case (instr[13:12]) + 2'b00: data_type_o = 2'b10; // sb + 2'b01: data_type_o = 2'b01; // sh + 2'b10: data_type_o = 2'b00; // sw + default: illegal_insn = 1'b1; + endcase + end + + OPCODE_LOAD: begin + rf_ren_a_o = 1'b1; + data_req_o = 1'b1; + data_type_o = 2'b00; + + // sign/zero extension + data_sign_extension_o = ~instr[14]; + + // load size + unique case (instr[13:12]) + 2'b00: data_type_o = 2'b10; // lb(u) + 2'b01: data_type_o = 2'b01; // lh(u) + 2'b10: begin + data_type_o = 2'b00; // lw + if (instr[14]) begin + illegal_insn = 1'b1; // lwu does not exist + end + end + default: begin + illegal_insn = 1'b1; + end + endcase + end + + ///////// + // ALU // + ///////// + + OPCODE_LUI: begin // Load Upper Immediate + rf_we = 1'b1; + end + + OPCODE_AUIPC: begin // Add Upper Immediate to PC + rf_we = 1'b1; + end + + OPCODE_OP_IMM: begin // Register-Immediate ALU Operations + rf_ren_a_o = 1'b1; + rf_we = 1'b1; + + unique case (instr[14:12]) + 3'b000, + 3'b010, + 3'b011, + 3'b100, + 3'b110, + 3'b111: illegal_insn = 1'b0; + + 3'b001: begin + unique case (instr[31:27]) + 5'b0_0000: illegal_insn = (instr[26:25] == 2'b00) ? 1'b0 : 1'b1; // slli + 5'b0_0100, // sloi + 5'b0_1001, // sbclri + 5'b0_0101, // sbseti + 5'b0_1101: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // sbinvi + 5'b0_0001: if (instr[26] == 1'b0) begin + illegal_insn = (RV32B == RV32BFull) ? 1'b0 : 1'b1; // shfl + end else begin + illegal_insn = 1'b1; + end + 5'b0_1100: begin + unique case(instr[26:20]) + 7'b000_0000, // clz + 7'b000_0001, // ctz + 7'b000_0010, // pcnt + 7'b000_0100, // sext.b + 7'b000_0101: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // sext.h + 7'b001_0000, // crc32.b + 7'b001_0001, // crc32.h + 7'b001_0010, // crc32.w + 7'b001_1000, // crc32c.b + 7'b001_1001, // crc32c.h + 7'b001_1010: illegal_insn = (RV32B == RV32BFull) ? 1'b0 : 1'b1; // crc32c.w + + default: illegal_insn = 1'b1; + endcase + end + default : illegal_insn = 1'b1; + endcase + end + + 3'b101: begin + if (instr[26]) begin + illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // fsri + end else begin + unique case (instr[31:27]) + 5'b0_0000, // srli + 5'b0_1000: illegal_insn = (instr[26:25] == 2'b00) ? 1'b0 : 1'b1; // srai + + 5'b0_0100, // sroi + 5'b0_1100, // rori + 5'b0_1001: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // sbexti + + 5'b0_1101: begin + if ((RV32B == RV32BFull)) begin + illegal_insn = 1'b0; // grevi + end else begin + unique case (instr[24:20]) + 5'b11111, // rev + 5'b11000: illegal_insn = (RV32B == RV32BBalanced) ? 1'b0 : 1'b1; // rev8 + + default: illegal_insn = 1'b1; + endcase + end + end + 5'b0_0101: begin + if ((RV32B == RV32BFull)) begin + illegal_insn = 1'b0; // gorci + end else if (instr[24:20] == 5'b00111) begin + illegal_insn = (RV32B == RV32BBalanced) ? 1'b0 : 1'b1; // orc.b + end else begin + illegal_insn = 1'b1; + end + end + 5'b0_0001: begin + if (instr[26] == 1'b0) begin + illegal_insn = (RV32B == RV32BFull) ? 1'b0 : 1'b1; // unshfl + end else begin + illegal_insn = 1'b1; + end + end + + default: illegal_insn = 1'b1; + endcase + end + end + + default: illegal_insn = 1'b1; + endcase + end + + OPCODE_OP: begin // Register-Register ALU operation + rf_ren_a_o = 1'b1; + rf_ren_b_o = 1'b1; + rf_we = 1'b1; + if ({instr[26], instr[13:12]} == {1'b1, 2'b01}) begin + illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // cmix / cmov / fsl / fsr + end else begin + unique case ({instr[31:25], instr[14:12]}) + // RV32I ALU operations + {7'b000_0000, 3'b000}, + {7'b010_0000, 3'b000}, + {7'b000_0000, 3'b010}, + {7'b000_0000, 3'b011}, + {7'b000_0000, 3'b100}, + {7'b000_0000, 3'b110}, + {7'b000_0000, 3'b111}, + {7'b000_0000, 3'b001}, + {7'b000_0000, 3'b101}, + {7'b010_0000, 3'b101}: illegal_insn = 1'b0; + + // RV32B zbb + {7'b010_0000, 3'b111}, // andn + {7'b010_0000, 3'b110}, // orn + {7'b010_0000, 3'b100}, // xnor + {7'b001_0000, 3'b001}, // slo + {7'b001_0000, 3'b101}, // sro + {7'b011_0000, 3'b001}, // rol + {7'b011_0000, 3'b101}, // ror + {7'b000_0101, 3'b100}, // min + {7'b000_0101, 3'b101}, // max + {7'b000_0101, 3'b110}, // minu + {7'b000_0101, 3'b111}, // maxu + {7'b000_0100, 3'b100}, // pack + {7'b010_0100, 3'b100}, // packu + {7'b000_0100, 3'b111}, // packh + // RV32B zbs + {7'b010_0100, 3'b001}, // sbclr + {7'b001_0100, 3'b001}, // sbset + {7'b011_0100, 3'b001}, // sbinv + {7'b010_0100, 3'b101}, // sbext + // RV32B zbf + {7'b010_0100, 3'b111}: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // bfp + // RV32B zbe + {7'b010_0100, 3'b110}, // bdep + {7'b000_0100, 3'b110}, // bext + // RV32B zbp + {7'b011_0100, 3'b101}, // grev + {7'b001_0100, 3'b101}, // gorc + {7'b000_0100, 3'b001}, // shfl + {7'b000_0100, 3'b101}, // unshfl + // RV32B zbc + {7'b000_0101, 3'b001}, // clmul + {7'b000_0101, 3'b010}, // clmulr + {7'b000_0101, 3'b011}: illegal_insn = (RV32B == RV32BFull) ? 1'b0 : 1'b1; // clmulh + + // RV32M instructions + {7'b000_0001, 3'b000}: begin // mul + multdiv_operator_o = MD_OP_MULL; + multdiv_signed_mode_o = 2'b00; + illegal_insn = (RV32M == RV32MNone) ? 1'b1 : 1'b0; + end + {7'b000_0001, 3'b001}: begin // mulh + multdiv_operator_o = MD_OP_MULH; + multdiv_signed_mode_o = 2'b11; + illegal_insn = (RV32M == RV32MNone) ? 1'b1 : 1'b0; + end + {7'b000_0001, 3'b010}: begin // mulhsu + multdiv_operator_o = MD_OP_MULH; + multdiv_signed_mode_o = 2'b01; + illegal_insn = (RV32M == RV32MNone) ? 1'b1 : 1'b0; + end + {7'b000_0001, 3'b011}: begin // mulhu + multdiv_operator_o = MD_OP_MULH; + multdiv_signed_mode_o = 2'b00; + illegal_insn = (RV32M == RV32MNone) ? 1'b1 : 1'b0; + end + {7'b000_0001, 3'b100}: begin // div + multdiv_operator_o = MD_OP_DIV; + multdiv_signed_mode_o = 2'b11; + illegal_insn = (RV32M == RV32MNone) ? 1'b1 : 1'b0; + end + {7'b000_0001, 3'b101}: begin // divu + multdiv_operator_o = MD_OP_DIV; + multdiv_signed_mode_o = 2'b00; + illegal_insn = (RV32M == RV32MNone) ? 1'b1 : 1'b0; + end + {7'b000_0001, 3'b110}: begin // rem + multdiv_operator_o = MD_OP_REM; + multdiv_signed_mode_o = 2'b11; + illegal_insn = (RV32M == RV32MNone) ? 1'b1 : 1'b0; + end + {7'b000_0001, 3'b111}: begin // remu + multdiv_operator_o = MD_OP_REM; + multdiv_signed_mode_o = 2'b00; + illegal_insn = (RV32M == RV32MNone) ? 1'b1 : 1'b0; + end + default: begin + illegal_insn = 1'b1; + end + endcase + end + end + + ///////////// + // Special // + ///////////// + + OPCODE_MISC_MEM: begin + unique case (instr[14:12]) + 3'b000: begin + // FENCE is treated as a NOP since all memory operations are already strictly ordered. + rf_we = 1'b0; + end + 3'b001: begin + // FENCE.I is implemented as a jump to the next PC, this gives the required flushing + // behaviour (iside prefetch buffer flushed and response to any outstanding iside + // requests will be ignored). + // If present, the ICache will also be flushed. + jump_in_dec_o = 1'b1; + + rf_we = 1'b0; + + if (instr_first_cycle_i) begin + jump_set_o = 1'b1; + icache_inval_o = 1'b1; + end + end + default: begin + illegal_insn = 1'b1; + end + endcase + end + + OPCODE_SYSTEM: begin + if (instr[14:12] == 3'b000) begin + // non CSR related SYSTEM instructions + unique case (instr[31:20]) + 12'h000: // ECALL + // environment (system) call + ecall_insn_o = 1'b1; + + 12'h001: // ebreak + // debugger trap + ebrk_insn_o = 1'b1; + + 12'h302: // mret + mret_insn_o = 1'b1; + + 12'h7b2: // dret + dret_insn_o = 1'b1; + + 12'h105: // wfi + wfi_insn_o = 1'b1; + + default: + illegal_insn = 1'b1; + endcase + + // rs1 and rd must be 0 + if (instr_rs1 != 5'b0 || instr_rd != 5'b0) begin + illegal_insn = 1'b1; + end + end else begin + // instruction to read/modify CSR + csr_access_o = 1'b1; + rf_wdata_sel_o = RF_WD_CSR; + rf_we = 1'b1; + + if (~instr[14]) begin + rf_ren_a_o = 1'b1; + end + + unique case (instr[13:12]) + 2'b01: csr_op = CSR_OP_WRITE; + 2'b10: csr_op = CSR_OP_SET; + 2'b11: csr_op = CSR_OP_CLEAR; + default: csr_illegal = 1'b1; + endcase + + illegal_insn = csr_illegal; + end + + end + default: begin + illegal_insn = 1'b1; + end + endcase + + // make sure illegal compressed instructions cause illegal instruction exceptions + if (illegal_c_insn_i) begin + illegal_insn = 1'b1; + end + + // make sure illegal instructions detected in the decoder do not propagate from decoder + // into register file, LSU, EX, WB, CSRs, PC + // NOTE: instructions can also be detected to be illegal inside the CSRs (upon accesses with + // insufficient privileges), or when accessing non-available registers in RV32E, + // these cases are not handled here + if (illegal_insn) begin + rf_we = 1'b0; + data_req_o = 1'b0; + data_we_o = 1'b0; + jump_in_dec_o = 1'b0; + jump_set_o = 1'b0; + branch_in_dec_o = 1'b0; + csr_access_o = 1'b0; + end + end + + ///////////////////////////// + // Decoder for ALU control // + ///////////////////////////// + + always_comb begin + alu_operator_o = ALU_SLTU; + alu_op_a_mux_sel_o = OP_A_IMM; + alu_op_b_mux_sel_o = OP_B_IMM; + + imm_a_mux_sel_o = IMM_A_ZERO; + imm_b_mux_sel_o = IMM_B_I; + + bt_a_mux_sel_o = OP_A_CURRPC; + bt_b_mux_sel_o = IMM_B_I; + + + opcode_alu = opcode_e'(instr_alu[6:0]); + + use_rs3_d = 1'b0; + alu_multicycle_o = 1'b0; + mult_sel_o = 1'b0; + div_sel_o = 1'b0; + + unique case (opcode_alu) + + /////////// + // Jumps // + /////////// + + OPCODE_JAL: begin // Jump and Link + if (BranchTargetALU) begin + bt_a_mux_sel_o = OP_A_CURRPC; + bt_b_mux_sel_o = IMM_B_J; + end + + // Jumps take two cycles without the BTALU + if (instr_first_cycle_i && !BranchTargetALU) begin + // Calculate jump target + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_J; + alu_operator_o = ALU_ADD; + end else begin + // Calculate and store PC+4 + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_INCR_PC; + alu_operator_o = ALU_ADD; + end + end + + OPCODE_JALR: begin // Jump and Link Register + if (BranchTargetALU) begin + bt_a_mux_sel_o = OP_A_REG_A; + bt_b_mux_sel_o = IMM_B_I; + end + + // Jumps take two cycles without the BTALU + if (instr_first_cycle_i && !BranchTargetALU) begin + // Calculate jump target + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_I; + alu_operator_o = ALU_ADD; + end else begin + // Calculate and store PC+4 + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_INCR_PC; + alu_operator_o = ALU_ADD; + end + end + + OPCODE_BRANCH: begin // Branch + // Check branch condition selection + unique case (instr_alu[14:12]) + 3'b000: alu_operator_o = ALU_EQ; + 3'b001: alu_operator_o = ALU_NE; + 3'b100: alu_operator_o = ALU_LT; + 3'b101: alu_operator_o = ALU_GE; + 3'b110: alu_operator_o = ALU_LTU; + 3'b111: alu_operator_o = ALU_GEU; + default: ; + endcase + + if (BranchTargetALU) begin + bt_a_mux_sel_o = OP_A_CURRPC; + // Not-taken branch will jump to next instruction (used in secure mode) + bt_b_mux_sel_o = branch_taken_i ? IMM_B_B : IMM_B_INCR_PC; + end + + // Without branch target ALU, a branch is a two-stage operation using the Main ALU in both + // stages + if (instr_first_cycle_i) begin + // First evaluate the branch condition + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_REG_B; + end else begin + // Then calculate jump target + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + // Not-taken branch will jump to next instruction (used in secure mode) + imm_b_mux_sel_o = branch_taken_i ? IMM_B_B : IMM_B_INCR_PC; + alu_operator_o = ALU_ADD; + end + end + + //////////////// + // Load/store // + //////////////// + + OPCODE_STORE: begin + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_REG_B; + alu_operator_o = ALU_ADD; + + if (!instr_alu[14]) begin + // offset from immediate + imm_b_mux_sel_o = IMM_B_S; + alu_op_b_mux_sel_o = OP_B_IMM; + end + end + + OPCODE_LOAD: begin + alu_op_a_mux_sel_o = OP_A_REG_A; + + // offset from immediate + alu_operator_o = ALU_ADD; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_I; + end + + ///////// + // ALU // + ///////// + + OPCODE_LUI: begin // Load Upper Immediate + alu_op_a_mux_sel_o = OP_A_IMM; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_a_mux_sel_o = IMM_A_ZERO; + imm_b_mux_sel_o = IMM_B_U; + alu_operator_o = ALU_ADD; + end + + OPCODE_AUIPC: begin // Add Upper Immediate to PC + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_U; + alu_operator_o = ALU_ADD; + end + + OPCODE_OP_IMM: begin // Register-Immediate ALU Operations + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_I; + + unique case (instr_alu[14:12]) + 3'b000: alu_operator_o = ALU_ADD; // Add Immediate + 3'b010: alu_operator_o = ALU_SLT; // Set to one if Lower Than Immediate + 3'b011: alu_operator_o = ALU_SLTU; // Set to one if Lower Than Immediate Unsigned + 3'b100: alu_operator_o = ALU_XOR; // Exclusive Or with Immediate + 3'b110: alu_operator_o = ALU_OR; // Or with Immediate + 3'b111: alu_operator_o = ALU_AND; // And with Immediate + + 3'b001: begin + if (RV32B != RV32BNone) begin + unique case (instr_alu[31:27]) + 5'b0_0000: alu_operator_o = ALU_SLL; // Shift Left Logical by Immediate + 5'b0_0100: alu_operator_o = ALU_SLO; // Shift Left Ones by Immediate + 5'b0_1001: alu_operator_o = ALU_SBCLR; // Clear bit specified by immediate + 5'b0_0101: alu_operator_o = ALU_SBSET; // Set bit specified by immediate + 5'b0_1101: alu_operator_o = ALU_SBINV; // Invert bit specified by immediate. + // Shuffle with Immediate Control Value + 5'b0_0001: if (instr_alu[26] == 0) alu_operator_o = ALU_SHFL; + 5'b0_1100: begin + unique case (instr_alu[26:20]) + 7'b000_0000: alu_operator_o = ALU_CLZ; // clz + 7'b000_0001: alu_operator_o = ALU_CTZ; // ctz + 7'b000_0010: alu_operator_o = ALU_PCNT; // pcnt + 7'b000_0100: alu_operator_o = ALU_SEXTB; // sext.b + 7'b000_0101: alu_operator_o = ALU_SEXTH; // sext.h + 7'b001_0000: begin + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_CRC32_B; // crc32.b + alu_multicycle_o = 1'b1; + end + end + 7'b001_0001: begin + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_CRC32_H; // crc32.h + alu_multicycle_o = 1'b1; + end + end + 7'b001_0010: begin + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_CRC32_W; // crc32.w + alu_multicycle_o = 1'b1; + end + end + 7'b001_1000: begin + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_CRC32C_B; // crc32c.b + alu_multicycle_o = 1'b1; + end + end + 7'b001_1001: begin + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_CRC32C_H; // crc32c.h + alu_multicycle_o = 1'b1; + end + end + 7'b001_1010: begin + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_CRC32C_W; // crc32c.w + alu_multicycle_o = 1'b1; + end + end + default: ; + endcase + end + + default: ; + endcase + end else begin + alu_operator_o = ALU_SLL; // Shift Left Logical by Immediate + end + end + + 3'b101: begin + if (RV32B != RV32BNone) begin + if (instr_alu[26] == 1'b1) begin + alu_operator_o = ALU_FSR; + alu_multicycle_o = 1'b1; + if (instr_first_cycle_i) begin + use_rs3_d = 1'b1; + end else begin + use_rs3_d = 1'b0; + end + end else begin + unique case (instr_alu[31:27]) + 5'b0_0000: alu_operator_o = ALU_SRL; // Shift Right Logical by Immediate + 5'b0_1000: alu_operator_o = ALU_SRA; // Shift Right Arithmetically by Immediate + 5'b0_0100: alu_operator_o = ALU_SRO; // Shift Right Ones by Immediate + 5'b0_1001: alu_operator_o = ALU_SBEXT; // Extract bit specified by immediate. + 5'b0_1100: begin + alu_operator_o = ALU_ROR; // Rotate Right by Immediate + alu_multicycle_o = 1'b1; + end + 5'b0_1101: alu_operator_o = ALU_GREV; // General Reverse with Imm Control Val + 5'b0_0101: alu_operator_o = ALU_GORC; // General Or-combine with Imm Control Val + // Unshuffle with Immediate Control Value + 5'b0_0001: begin + if (RV32B == RV32BFull) begin + if (instr_alu[26] == 1'b0) alu_operator_o = ALU_UNSHFL; + end + end + default: ; + endcase + end + + end else begin + if (instr_alu[31:27] == 5'b0_0000) begin + alu_operator_o = ALU_SRL; // Shift Right Logical by Immediate + end else if (instr_alu[31:27] == 5'b0_1000) begin + alu_operator_o = ALU_SRA; // Shift Right Arithmetically by Immediate + end + end + end + + default: ; + endcase + end + + OPCODE_OP: begin // Register-Register ALU operation + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_REG_B; + + if (instr_alu[26]) begin + if (RV32B != RV32BNone) begin + unique case ({instr_alu[26:25], instr_alu[14:12]}) + {2'b11, 3'b001}: begin + alu_operator_o = ALU_CMIX; // cmix + alu_multicycle_o = 1'b1; + if (instr_first_cycle_i) begin + use_rs3_d = 1'b1; + end else begin + use_rs3_d = 1'b0; + end + end + {2'b11, 3'b101}: begin + alu_operator_o = ALU_CMOV; // cmov + alu_multicycle_o = 1'b1; + if (instr_first_cycle_i) begin + use_rs3_d = 1'b1; + end else begin + use_rs3_d = 1'b0; + end + end + {2'b10, 3'b001}: begin + alu_operator_o = ALU_FSL; // fsl + alu_multicycle_o = 1'b1; + if (instr_first_cycle_i) begin + use_rs3_d = 1'b1; + end else begin + use_rs3_d = 1'b0; + end + end + {2'b10, 3'b101}: begin + alu_operator_o = ALU_FSR; // fsr + alu_multicycle_o = 1'b1; + if (instr_first_cycle_i) begin + use_rs3_d = 1'b1; + end else begin + use_rs3_d = 1'b0; + end + end + default: ; + endcase + end + end else begin + unique case ({instr_alu[31:25], instr_alu[14:12]}) + // RV32I ALU operations + {7'b000_0000, 3'b000}: alu_operator_o = ALU_ADD; // Add + {7'b010_0000, 3'b000}: alu_operator_o = ALU_SUB; // Sub + {7'b000_0000, 3'b010}: alu_operator_o = ALU_SLT; // Set Lower Than + {7'b000_0000, 3'b011}: alu_operator_o = ALU_SLTU; // Set Lower Than Unsigned + {7'b000_0000, 3'b100}: alu_operator_o = ALU_XOR; // Xor + {7'b000_0000, 3'b110}: alu_operator_o = ALU_OR; // Or + {7'b000_0000, 3'b111}: alu_operator_o = ALU_AND; // And + {7'b000_0000, 3'b001}: alu_operator_o = ALU_SLL; // Shift Left Logical + {7'b000_0000, 3'b101}: alu_operator_o = ALU_SRL; // Shift Right Logical + {7'b010_0000, 3'b101}: alu_operator_o = ALU_SRA; // Shift Right Arithmetic + + // RV32B ALU Operations + {7'b001_0000, 3'b001}: if (RV32B != RV32BNone) alu_operator_o = ALU_SLO; // slo + {7'b001_0000, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_SRO; // sro + {7'b011_0000, 3'b001}: begin + if (RV32B != RV32BNone) begin + alu_operator_o = ALU_ROL; // rol + alu_multicycle_o = 1'b1; + end + end + {7'b011_0000, 3'b101}: begin + if (RV32B != RV32BNone) begin + alu_operator_o = ALU_ROR; // ror + alu_multicycle_o = 1'b1; + end + end + + {7'b000_0101, 3'b100}: if (RV32B != RV32BNone) alu_operator_o = ALU_MIN; // min + {7'b000_0101, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_MAX; // max + {7'b000_0101, 3'b110}: if (RV32B != RV32BNone) alu_operator_o = ALU_MINU; // minu + {7'b000_0101, 3'b111}: if (RV32B != RV32BNone) alu_operator_o = ALU_MAXU; // maxu + + {7'b000_0100, 3'b100}: if (RV32B != RV32BNone) alu_operator_o = ALU_PACK; // pack + {7'b010_0100, 3'b100}: if (RV32B != RV32BNone) alu_operator_o = ALU_PACKU; // packu + {7'b000_0100, 3'b111}: if (RV32B != RV32BNone) alu_operator_o = ALU_PACKH; // packh + + {7'b010_0000, 3'b100}: if (RV32B != RV32BNone) alu_operator_o = ALU_XNOR; // xnor + {7'b010_0000, 3'b110}: if (RV32B != RV32BNone) alu_operator_o = ALU_ORN; // orn + {7'b010_0000, 3'b111}: if (RV32B != RV32BNone) alu_operator_o = ALU_ANDN; // andn + + // RV32B zbs + {7'b010_0100, 3'b001}: if (RV32B != RV32BNone) alu_operator_o = ALU_SBCLR; // sbclr + {7'b001_0100, 3'b001}: if (RV32B != RV32BNone) alu_operator_o = ALU_SBSET; // sbset + {7'b011_0100, 3'b001}: if (RV32B != RV32BNone) alu_operator_o = ALU_SBINV; // sbinv + {7'b010_0100, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_SBEXT; // sbext + + // RV32B zbf + {7'b010_0100, 3'b111}: if (RV32B != RV32BNone) alu_operator_o = ALU_BFP; // bfp + + // RV32B zbp + {7'b011_0100, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_GREV; // grev + {7'b001_0100, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_GORC; // grev + {7'b000_0100, 3'b001}: if (RV32B == RV32BFull) alu_operator_o = ALU_SHFL; // shfl + {7'b000_0100, 3'b101}: if (RV32B == RV32BFull) alu_operator_o = ALU_UNSHFL; // unshfl + + // RV32B zbc + {7'b000_0101, 3'b001}: if (RV32B == RV32BFull) alu_operator_o = ALU_CLMUL; // clmul + {7'b000_0101, 3'b010}: if (RV32B == RV32BFull) alu_operator_o = ALU_CLMULR; // clmulr + {7'b000_0101, 3'b011}: if (RV32B == RV32BFull) alu_operator_o = ALU_CLMULH; // clmulh + + // RV32B zbe + {7'b010_0100, 3'b110}: begin + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_BDEP; // bdep + alu_multicycle_o = 1'b1; + end + end + {7'b000_0100, 3'b110}: begin + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_BEXT; // bext + alu_multicycle_o = 1'b1; + end + end + + // RV32M instructions, all use the same ALU operation + {7'b000_0001, 3'b000}: begin // mul + alu_operator_o = ALU_ADD; + mult_sel_o = (RV32M == RV32MNone) ? 1'b0 : 1'b1; + end + {7'b000_0001, 3'b001}: begin // mulh + alu_operator_o = ALU_ADD; + mult_sel_o = (RV32M == RV32MNone) ? 1'b0 : 1'b1; + end + {7'b000_0001, 3'b010}: begin // mulhsu + alu_operator_o = ALU_ADD; + mult_sel_o = (RV32M == RV32MNone) ? 1'b0 : 1'b1; + end + {7'b000_0001, 3'b011}: begin // mulhu + alu_operator_o = ALU_ADD; + mult_sel_o = (RV32M == RV32MNone) ? 1'b0 : 1'b1; + end + {7'b000_0001, 3'b100}: begin // div + alu_operator_o = ALU_ADD; + div_sel_o = (RV32M == RV32MNone) ? 1'b0 : 1'b1; + end + {7'b000_0001, 3'b101}: begin // divu + alu_operator_o = ALU_ADD; + div_sel_o = (RV32M == RV32MNone) ? 1'b0 : 1'b1; + end + {7'b000_0001, 3'b110}: begin // rem + alu_operator_o = ALU_ADD; + div_sel_o = (RV32M == RV32MNone) ? 1'b0 : 1'b1; + end + {7'b000_0001, 3'b111}: begin // remu + alu_operator_o = ALU_ADD; + div_sel_o = (RV32M == RV32MNone) ? 1'b0 : 1'b1; + end + + default: ; + endcase + end + end + + ///////////// + // Special // + ///////////// + + OPCODE_MISC_MEM: begin + unique case (instr_alu[14:12]) + 3'b000: begin + // FENCE is treated as a NOP since all memory operations are already strictly ordered. + alu_operator_o = ALU_ADD; // nop + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_IMM; + end + 3'b001: begin + // FENCE.I will flush the IF stage, prefetch buffer and ICache if present. + if (BranchTargetALU) begin + bt_a_mux_sel_o = OP_A_CURRPC; + bt_b_mux_sel_o = IMM_B_INCR_PC; + end else begin + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_INCR_PC; + alu_operator_o = ALU_ADD; + end + end + default: ; + endcase + end + + OPCODE_SYSTEM: begin + if (instr_alu[14:12] == 3'b000) begin + // non CSR related SYSTEM instructions + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_IMM; + end else begin + // instruction to read/modify CSR + alu_op_b_mux_sel_o = OP_B_IMM; + imm_a_mux_sel_o = IMM_A_Z; + imm_b_mux_sel_o = IMM_B_I; // CSR address is encoded in I imm + + if (instr_alu[14]) begin + // rs1 field is used as immediate + alu_op_a_mux_sel_o = OP_A_IMM; + end else begin + alu_op_a_mux_sel_o = OP_A_REG_A; + end + end + + end + default: ; + endcase + end + + // do not enable multdiv in case of illegal instruction exceptions + assign mult_en_o = illegal_insn ? 1'b0 : mult_sel_o; + assign div_en_o = illegal_insn ? 1'b0 : div_sel_o; + + // make sure instructions accessing non-available registers in RV32E cause illegal + // instruction exceptions + assign illegal_insn_o = illegal_insn | illegal_reg_rv32e; + + // do not propgate regfile write enable if non-available registers are accessed in RV32E + assign rf_we_o = rf_we & ~illegal_reg_rv32e; + + // Not all bits are used + assign unused_instr_alu = {instr_alu[19:15],instr_alu[11:7]}; + + //////////////// + // Assertions // + //////////////// + + // Selectors must be known/valid. + `ASSERT(IbexRegImmAluOpKnown, (opcode == OPCODE_OP_IMM) |-> + !$isunknown(instr[14:12])) +endmodule // controller diff --git a/flow/designs/src/ibex_sv/ibex_ex_block.sv b/flow/designs/src/ibex_sv/ibex_ex_block.sv new file mode 100644 index 0000000000..62e039645f --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_ex_block.sv @@ -0,0 +1,199 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Execution stage + * + * Execution block: Hosts ALU and MUL/DIV unit + */ +module ibex_ex_block #( + parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast, + parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone, + parameter bit BranchTargetALU = 0 +) ( + input logic clk_i, + input logic rst_ni, + + // ALU + input ibex_pkg::alu_op_e alu_operator_i, + input logic [31:0] alu_operand_a_i, + input logic [31:0] alu_operand_b_i, + input logic alu_instr_first_cycle_i, + + // Branch Target ALU + // All of these signals are unusued when BranchTargetALU == 0 + input logic [31:0] bt_a_operand_i, + input logic [31:0] bt_b_operand_i, + + // Multiplier/Divider + input ibex_pkg::md_op_e multdiv_operator_i, + input logic mult_en_i, // dynamic enable signal, for FSM control + input logic div_en_i, // dynamic enable signal, for FSM control + input logic mult_sel_i, // static decoder output, for data muxes + input logic div_sel_i, // static decoder output, for data muxes + input logic [1:0] multdiv_signed_mode_i, + input logic [31:0] multdiv_operand_a_i, + input logic [31:0] multdiv_operand_b_i, + input logic multdiv_ready_id_i, + input logic data_ind_timing_i, + + // intermediate val reg + output logic [1:0] imd_val_we_o, + output logic [33:0] imd_val_d_o[2], + input logic [33:0] imd_val_q_i[2], + + // Outputs + output logic [31:0] alu_adder_result_ex_o, // to LSU + output logic [31:0] result_ex_o, + output logic [31:0] branch_target_o, // to IF + output logic branch_decision_o, // to ID + + output logic ex_valid_o // EX has valid output +); + + import ibex_pkg::*; + + logic [31:0] alu_result, multdiv_result; + + logic [32:0] multdiv_alu_operand_b, multdiv_alu_operand_a; + logic [33:0] alu_adder_result_ext; + logic alu_cmp_result, alu_is_equal_result; + logic multdiv_valid; + logic multdiv_sel; + logic [31:0] alu_imd_val_q[2]; + logic [31:0] alu_imd_val_d[2]; + logic [ 1:0] alu_imd_val_we; + logic [33:0] multdiv_imd_val_d[2]; + logic [ 1:0] multdiv_imd_val_we; + + /* + The multdiv_i output is never selected if RV32M=RV32MNone + At synthesis time, all the combinational and sequential logic + from the multdiv_i module are eliminated + */ + if (RV32M != RV32MNone) begin : gen_multdiv_m + assign multdiv_sel = mult_sel_i | div_sel_i; + end else begin : gen_multdiv_no_m + assign multdiv_sel = 1'b0; + end + + // Intermediate Value Register Mux + assign imd_val_d_o[0] = multdiv_sel ? multdiv_imd_val_d[0] : {2'b0, alu_imd_val_d[0]}; + assign imd_val_d_o[1] = multdiv_sel ? multdiv_imd_val_d[1] : {2'b0, alu_imd_val_d[1]}; + assign imd_val_we_o = multdiv_sel ? multdiv_imd_val_we : alu_imd_val_we; + + assign alu_imd_val_q = '{imd_val_q_i[0][31:0], imd_val_q_i[1][31:0]}; + + assign result_ex_o = multdiv_sel ? multdiv_result : alu_result; + + // branch handling + assign branch_decision_o = alu_cmp_result; + + if (BranchTargetALU) begin : g_branch_target_alu + logic [32:0] bt_alu_result; + logic unused_bt_carry; + + assign bt_alu_result = bt_a_operand_i + bt_b_operand_i; + + assign unused_bt_carry = bt_alu_result[32]; + assign branch_target_o = bt_alu_result[31:0]; + end else begin : g_no_branch_target_alu + // Unused bt_operand signals cause lint errors, this avoids them + logic [31:0] unused_bt_a_operand, unused_bt_b_operand; + + assign unused_bt_a_operand = bt_a_operand_i; + assign unused_bt_b_operand = bt_b_operand_i; + + assign branch_target_o = alu_adder_result_ex_o; + end + + ///////// + // ALU // + ///////// + + ibex_alu #( + .RV32B(RV32B) + ) alu_i ( + .operator_i ( alu_operator_i ), + .operand_a_i ( alu_operand_a_i ), + .operand_b_i ( alu_operand_b_i ), + .instr_first_cycle_i ( alu_instr_first_cycle_i ), + .imd_val_q_i ( alu_imd_val_q ), + .imd_val_we_o ( alu_imd_val_we ), + .imd_val_d_o ( alu_imd_val_d ), + .multdiv_operand_a_i ( multdiv_alu_operand_a ), + .multdiv_operand_b_i ( multdiv_alu_operand_b ), + .multdiv_sel_i ( multdiv_sel ), + .adder_result_o ( alu_adder_result_ex_o ), + .adder_result_ext_o ( alu_adder_result_ext ), + .result_o ( alu_result ), + .comparison_result_o ( alu_cmp_result ), + .is_equal_result_o ( alu_is_equal_result ) + ); + + //////////////// + // Multiplier // + //////////////// + + if (RV32M == RV32MSlow) begin : gen_multdiv_slow + ibex_multdiv_slow multdiv_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .mult_en_i ( mult_en_i ), + .div_en_i ( div_en_i ), + .mult_sel_i ( mult_sel_i ), + .div_sel_i ( div_sel_i ), + .operator_i ( multdiv_operator_i ), + .signed_mode_i ( multdiv_signed_mode_i ), + .op_a_i ( multdiv_operand_a_i ), + .op_b_i ( multdiv_operand_b_i ), + .alu_adder_ext_i ( alu_adder_result_ext ), + .alu_adder_i ( alu_adder_result_ex_o ), + .equal_to_zero_i ( alu_is_equal_result ), + .data_ind_timing_i ( data_ind_timing_i ), + .valid_o ( multdiv_valid ), + .alu_operand_a_o ( multdiv_alu_operand_a ), + .alu_operand_b_o ( multdiv_alu_operand_b ), + .imd_val_q_i ( imd_val_q_i ), + .imd_val_d_o ( multdiv_imd_val_d ), + .imd_val_we_o ( multdiv_imd_val_we ), + .multdiv_ready_id_i ( multdiv_ready_id_i ), + .multdiv_result_o ( multdiv_result ) + ); + end else if (RV32M == RV32MFast || RV32M == RV32MSingleCycle) begin : gen_multdiv_fast + ibex_multdiv_fast # ( + .RV32M ( RV32M ) + ) multdiv_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .mult_en_i ( mult_en_i ), + .div_en_i ( div_en_i ), + .mult_sel_i ( mult_sel_i ), + .div_sel_i ( div_sel_i ), + .operator_i ( multdiv_operator_i ), + .signed_mode_i ( multdiv_signed_mode_i ), + .op_a_i ( multdiv_operand_a_i ), + .op_b_i ( multdiv_operand_b_i ), + .alu_operand_a_o ( multdiv_alu_operand_a ), + .alu_operand_b_o ( multdiv_alu_operand_b ), + .alu_adder_ext_i ( alu_adder_result_ext ), + .alu_adder_i ( alu_adder_result_ex_o ), + .equal_to_zero_i ( alu_is_equal_result ), + .data_ind_timing_i ( data_ind_timing_i ), + .imd_val_q_i ( imd_val_q_i ), + .imd_val_d_o ( multdiv_imd_val_d ), + .imd_val_we_o ( multdiv_imd_val_we ), + .multdiv_ready_id_i ( multdiv_ready_id_i ), + .valid_o ( multdiv_valid ), + .multdiv_result_o ( multdiv_result ) + ); + end + + // Multiplier/divider may require multiple cycles. The ALU output is valid in the same cycle + // unless the intermediate result register is being written (which indicates this isn't the + // final cycle of ALU operation). + assign ex_valid_o = multdiv_sel ? multdiv_valid : ~(|alu_imd_val_we); + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_fetch_fifo.sv b/flow/designs/src/ibex_sv/ibex_fetch_fifo.sv new file mode 100644 index 0000000000..52fcc8ea90 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_fetch_fifo.sv @@ -0,0 +1,250 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Fetch Fifo for 32 bit memory interface + * + * input port: send address and data to the FIFO + * clear_i clears the FIFO for the following cycle, including any new request + */ + +`include "prim_assert.sv" + +module ibex_fetch_fifo #( + parameter int unsigned NUM_REQS = 2 +) ( + input logic clk_i, + input logic rst_ni, + + // control signals + input logic clear_i, // clears the contents of the FIFO + output logic [NUM_REQS-1:0] busy_o, + + // input port + input logic in_valid_i, + input logic [31:0] in_addr_i, + input logic [31:0] in_rdata_i, + input logic in_err_i, + + // output port + output logic out_valid_o, + input logic out_ready_i, + output logic [31:0] out_addr_o, + output logic [31:0] out_addr_next_o, + output logic [31:0] out_rdata_o, + output logic out_err_o, + output logic out_err_plus2_o +); + + localparam int unsigned DEPTH = NUM_REQS+1; + + // index 0 is used for output + logic [DEPTH-1:0] [31:0] rdata_d, rdata_q; + logic [DEPTH-1:0] err_d, err_q; + logic [DEPTH-1:0] valid_d, valid_q; + logic [DEPTH-1:0] lowest_free_entry; + logic [DEPTH-1:0] valid_pushed, valid_popped; + logic [DEPTH-1:0] entry_en; + + logic pop_fifo; + logic [31:0] rdata, rdata_unaligned; + logic err, err_unaligned, err_plus2; + logic valid, valid_unaligned; + + logic aligned_is_compressed, unaligned_is_compressed; + + logic addr_incr_two; + logic [31:1] instr_addr_next; + logic [31:1] instr_addr_d, instr_addr_q; + logic instr_addr_en; + logic unused_addr_in; + + ///////////////// + // Output port // + ///////////////// + + assign rdata = valid_q[0] ? rdata_q[0] : in_rdata_i; + assign err = valid_q[0] ? err_q[0] : in_err_i; + assign valid = valid_q[0] | in_valid_i; + + // The FIFO contains word aligned memory fetches, but the instructions contained in each entry + // might be half-word aligned (due to compressed instructions) + // e.g. + // | 31 16 | 15 0 | + // FIFO entry 0 | Instr 1 [15:0] | Instr 0 [15:0] | + // FIFO entry 1 | Instr 2 [15:0] | Instr 1 [31:16] | + // + // The FIFO also has a direct bypass path, so a complete instruction might be made up of data + // from the FIFO and new incoming data. + // + + // Construct the output data for an unaligned instruction + assign rdata_unaligned = valid_q[1] ? {rdata_q[1][15:0], rdata[31:16]} : + {in_rdata_i[15:0], rdata[31:16]}; + + // If entry[1] is valid, an error can come from entry[0] or entry[1], unless the + // instruction in entry[0] is compressed (entry[1] is a new instruction) + // If entry[1] is not valid, and entry[0] is, an error can come from entry[0] or the incoming + // data, unless the instruction in entry[0] is compressed + // If entry[0] is not valid, the error must come from the incoming data + assign err_unaligned = valid_q[1] ? ((err_q[1] & ~unaligned_is_compressed) | err_q[0]) : + ((valid_q[0] & err_q[0]) | + (in_err_i & (~valid_q[0] | ~unaligned_is_compressed))); + + // Record when an error is caused by the second half of an unaligned 32bit instruction. + // Only needs to be correct when unaligned and if err_unaligned is set + assign err_plus2 = valid_q[1] ? (err_q[1] & ~err_q[0]) : + (in_err_i & valid_q[0] & ~err_q[0]); + + // An uncompressed unaligned instruction is only valid if both parts are available + assign valid_unaligned = valid_q[1] ? 1'b1 : + (valid_q[0] & in_valid_i); + + // If there is an error, rdata is unknown + assign unaligned_is_compressed = (rdata[17:16] != 2'b11) & ~err; + assign aligned_is_compressed = (rdata[ 1: 0] != 2'b11) & ~err; + + //////////////////////////////////////// + // Instruction aligner (if unaligned) // + //////////////////////////////////////// + + always_comb begin + if (out_addr_o[1]) begin + // unaligned case + out_rdata_o = rdata_unaligned; + out_err_o = err_unaligned; + out_err_plus2_o = err_plus2; + + if (unaligned_is_compressed) begin + out_valid_o = valid; + end else begin + out_valid_o = valid_unaligned; + end + end else begin + // aligned case + out_rdata_o = rdata; + out_err_o = err; + out_err_plus2_o = 1'b0; + out_valid_o = valid; + end + end + + ///////////////////////// + // Instruction address // + ///////////////////////// + + // Update the address on branches and every time an instruction is driven + assign instr_addr_en = clear_i | (out_ready_i & out_valid_o); + + // Increment the address by two every time a compressed instruction is popped + assign addr_incr_two = instr_addr_q[1] ? unaligned_is_compressed : + aligned_is_compressed; + + assign instr_addr_next = (instr_addr_q[31:1] + + // Increment address by 4 or 2 + {29'd0,~addr_incr_two,addr_incr_two}); + + assign instr_addr_d = clear_i ? in_addr_i[31:1] : + instr_addr_next; + + always_ff @(posedge clk_i) begin + if (instr_addr_en) begin + instr_addr_q <= instr_addr_d; + end + end + + // Output both PC of current instruction and instruction following. PC of instruction following is + // required for the branch predictor. It's used to fetch the instruction following a branch that + // was not-taken but (mis)predicted taken. + assign out_addr_next_o = {instr_addr_next, 1'b0}; + assign out_addr_o = {instr_addr_q, 1'b0}; + + // The LSB of the address is unused, since all addresses are halfword aligned + assign unused_addr_in = in_addr_i[0]; + + ///////////////// + // FIFO status // + ///////////////// + + // Indicate the fill level of fifo-entries. This is used to determine when a new request can be + // made on the bus. The prefetch buffer only needs to know about the upper entries which overlap + // with NUM_REQS. + assign busy_o = valid_q[DEPTH-1:DEPTH-NUM_REQS]; + + ///////////////////// + // FIFO management // + ///////////////////// + + // Since an entry can contain unaligned instructions, popping an entry can leave the entry valid + assign pop_fifo = out_ready_i & out_valid_o & (~aligned_is_compressed | out_addr_o[1]); + + for (genvar i = 0; i < (DEPTH - 1); i++) begin : g_fifo_next + // Calculate lowest free entry (write pointer) + if (i == 0) begin : g_ent0 + assign lowest_free_entry[i] = ~valid_q[i]; + end else begin : g_ent_others + assign lowest_free_entry[i] = ~valid_q[i] & valid_q[i-1]; + end + + // An entry is set when an incoming request chooses the lowest available entry + assign valid_pushed[i] = (in_valid_i & lowest_free_entry[i]) | + valid_q[i]; + // Popping the FIFO shifts all entries down + assign valid_popped[i] = pop_fifo ? valid_pushed[i+1] : valid_pushed[i]; + // All entries are wiped out on a clear + assign valid_d[i] = valid_popped[i] & ~clear_i; + + // data flops are enabled if there is new data to shift into it, or + assign entry_en[i] = (valid_pushed[i+1] & pop_fifo) | + // a new request is incoming and this is the lowest free entry + (in_valid_i & lowest_free_entry[i] & ~pop_fifo); + + // take the next entry or the incoming data + assign rdata_d[i] = valid_q[i+1] ? rdata_q[i+1] : in_rdata_i; + assign err_d [i] = valid_q[i+1] ? err_q [i+1] : in_err_i; + end + // The top entry is similar but with simpler muxing + assign lowest_free_entry[DEPTH-1] = ~valid_q[DEPTH-1] & valid_q[DEPTH-2]; + assign valid_pushed [DEPTH-1] = valid_q[DEPTH-1] | (in_valid_i & lowest_free_entry[DEPTH-1]); + assign valid_popped [DEPTH-1] = pop_fifo ? 1'b0 : valid_pushed[DEPTH-1]; + assign valid_d [DEPTH-1] = valid_popped[DEPTH-1] & ~clear_i; + assign entry_en[DEPTH-1] = in_valid_i & lowest_free_entry[DEPTH-1]; + assign rdata_d [DEPTH-1] = in_rdata_i; + assign err_d [DEPTH-1] = in_err_i; + + //////////////////// + // FIFO registers // + //////////////////// + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + valid_q <= '0; + end else begin + valid_q <= valid_d; + end + end + + for (genvar i = 0; i < DEPTH; i++) begin : g_fifo_regs + always_ff @(posedge clk_i) begin + if (entry_en[i]) begin + rdata_q[i] <= rdata_d[i]; + err_q[i] <= err_d[i]; + end + end + end + + //////////////// + // Assertions // + //////////////// + + // Must not push and pop simultaneously when FIFO full. + `ASSERT(IbexFetchFifoPushPopFull, + (in_valid_i && pop_fifo) |-> (!valid_q[DEPTH-1] || clear_i)) + + // Must not push to FIFO when full. + `ASSERT(IbexFetchFifoPushFull, + (in_valid_i) |-> (!valid_q[DEPTH-1] || clear_i)) + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_id_stage.sv b/flow/designs/src/ibex_sv/ibex_id_stage.sv new file mode 100644 index 0000000000..7c91eae1ff --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_id_stage.sv @@ -0,0 +1,1044 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`ifdef RISCV_FORMAL + `define RVFI +`endif + +/** + * Instruction Decode Stage + * + * Decode stage of the core. It decodes the instructions and hosts the register + * file. + */ + +`include "prim_assert.sv" + +module ibex_id_stage #( + parameter bit RV32E = 0, + parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast, + parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone, + parameter bit DataIndTiming = 1'b0, + parameter bit BranchTargetALU = 0, + parameter bit SpecBranch = 0, + parameter bit WritebackStage = 0, + parameter bit BranchPredictor = 0 +) ( + input logic clk_i, + input logic rst_ni, + + output logic ctrl_busy_o, + output logic illegal_insn_o, + + // Interface to IF stage + input logic instr_valid_i, + input logic [31:0] instr_rdata_i, // from IF-ID pipeline registers + input logic [31:0] instr_rdata_alu_i, // from IF-ID pipeline registers + input logic [15:0] instr_rdata_c_i, // from IF-ID pipeline registers + input logic instr_is_compressed_i, + input logic instr_bp_taken_i, + output logic instr_req_o, + output logic instr_first_cycle_id_o, + output logic instr_valid_clear_o, // kill instr in IF-ID reg + output logic id_in_ready_o, // ID stage is ready for next instr + output logic icache_inval_o, + + // Jumps and branches + input logic branch_decision_i, + + // IF and ID stage signals + output logic pc_set_o, + output logic pc_set_spec_o, + output ibex_pkg::pc_sel_e pc_mux_o, + output logic nt_branch_mispredict_o, + output ibex_pkg::exc_pc_sel_e exc_pc_mux_o, + output ibex_pkg::exc_cause_e exc_cause_o, + + input logic illegal_c_insn_i, + input logic instr_fetch_err_i, + input logic instr_fetch_err_plus2_i, + + input logic [31:0] pc_id_i, + + // Stalls + input logic ex_valid_i, // EX stage has valid output + input logic lsu_resp_valid_i, // LSU has valid output, or is done + // ALU + output ibex_pkg::alu_op_e alu_operator_ex_o, + output logic [31:0] alu_operand_a_ex_o, + output logic [31:0] alu_operand_b_ex_o, + + // Multicycle Operation Stage Register + input logic [1:0] imd_val_we_ex_i, + input logic [33:0] imd_val_d_ex_i[2], + output logic [33:0] imd_val_q_ex_o[2], + + // Branch target ALU + output logic [31:0] bt_a_operand_o, + output logic [31:0] bt_b_operand_o, + + // MUL, DIV + output logic mult_en_ex_o, + output logic div_en_ex_o, + output logic mult_sel_ex_o, + output logic div_sel_ex_o, + output ibex_pkg::md_op_e multdiv_operator_ex_o, + output logic [1:0] multdiv_signed_mode_ex_o, + output logic [31:0] multdiv_operand_a_ex_o, + output logic [31:0] multdiv_operand_b_ex_o, + output logic multdiv_ready_id_o, + + // CSR + output logic csr_access_o, + output ibex_pkg::csr_op_e csr_op_o, + output logic csr_op_en_o, + output logic csr_save_if_o, + output logic csr_save_id_o, + output logic csr_save_wb_o, + output logic csr_restore_mret_id_o, + output logic csr_restore_dret_id_o, + output logic csr_save_cause_o, + output logic [31:0] csr_mtval_o, + input ibex_pkg::priv_lvl_e priv_mode_i, + input logic csr_mstatus_tw_i, + input logic illegal_csr_insn_i, + input logic data_ind_timing_i, + + // Interface to load store unit + output logic lsu_req_o, + output logic lsu_we_o, + output logic [1:0] lsu_type_o, + output logic lsu_sign_ext_o, + output logic [31:0] lsu_wdata_o, + + input logic lsu_req_done_i, // Data req to LSU is complete and + // instruction can move to writeback + // (only relevant where writeback stage is + // present) + + input logic lsu_addr_incr_req_i, + input logic [31:0] lsu_addr_last_i, + + // Interrupt signals + input logic csr_mstatus_mie_i, + input logic irq_pending_i, + input ibex_pkg::irqs_t irqs_i, + input logic irq_nm_i, + output logic nmi_mode_o, + + input logic lsu_load_err_i, + input logic lsu_store_err_i, + + // Debug Signal + output logic debug_mode_o, + output ibex_pkg::dbg_cause_e debug_cause_o, + output logic debug_csr_save_o, + input logic debug_req_i, + input logic debug_single_step_i, + input logic debug_ebreakm_i, + input logic debug_ebreaku_i, + input logic trigger_match_i, + + // Write back signal + input logic [31:0] result_ex_i, + input logic [31:0] csr_rdata_i, + + // Register file read + output logic [4:0] rf_raddr_a_o, + input logic [31:0] rf_rdata_a_i, + output logic [4:0] rf_raddr_b_o, + input logic [31:0] rf_rdata_b_i, + output logic rf_ren_a_o, + output logic rf_ren_b_o, + + // Register file write (via writeback) + output logic [4:0] rf_waddr_id_o, + output logic [31:0] rf_wdata_id_o, + output logic rf_we_id_o, + output logic rf_rd_a_wb_match_o, + output logic rf_rd_b_wb_match_o, + + // Register write information from writeback (for resolving data hazards) + input logic [4:0] rf_waddr_wb_i, + input logic [31:0] rf_wdata_fwd_wb_i, + input logic rf_write_wb_i, + + output logic en_wb_o, + output ibex_pkg::wb_instr_type_e instr_type_wb_o, + output logic instr_perf_count_id_o, + input logic ready_wb_i, + input logic outstanding_load_wb_i, + input logic outstanding_store_wb_i, + + // Performance Counters + output logic perf_jump_o, // executing a jump instr + output logic perf_branch_o, // executing a branch instr + output logic perf_tbranch_o, // executing a taken branch instr + output logic perf_dside_wait_o, // instruction in ID/EX is awaiting memory + // access to finish before proceeding + output logic perf_mul_wait_o, + output logic perf_div_wait_o, + output logic instr_id_done_o +); + + import ibex_pkg::*; + + // Decoder/Controller, ID stage internal signals + logic illegal_insn_dec; + logic ebrk_insn; + logic mret_insn_dec; + logic dret_insn_dec; + logic ecall_insn_dec; + logic wfi_insn_dec; + + logic wb_exception; + + logic branch_in_dec; + logic branch_spec, branch_set_spec; + logic branch_set, branch_set_d; + logic branch_not_set; + logic branch_taken; + logic jump_in_dec; + logic jump_set_dec; + logic jump_set; + + logic instr_first_cycle; + logic instr_executing; + logic instr_done; + logic controller_run; + logic stall_ld_hz; + logic stall_mem; + logic stall_multdiv; + logic stall_branch; + logic stall_jump; + logic stall_id; + logic stall_wb; + logic flush_id; + logic multicycle_done; + + // Immediate decoding and sign extension + logic [31:0] imm_i_type; + logic [31:0] imm_s_type; + logic [31:0] imm_b_type; + logic [31:0] imm_u_type; + logic [31:0] imm_j_type; + logic [31:0] zimm_rs1_type; + + logic [31:0] imm_a; // contains the immediate for operand b + logic [31:0] imm_b; // contains the immediate for operand b + + // Register file interface + + rf_wd_sel_e rf_wdata_sel; + logic rf_we_dec, rf_we_raw; + logic rf_ren_a, rf_ren_b; + + assign rf_ren_a_o = rf_ren_a; + assign rf_ren_b_o = rf_ren_b; + + logic [31:0] rf_rdata_a_fwd; + logic [31:0] rf_rdata_b_fwd; + + // ALU Control + alu_op_e alu_operator; + op_a_sel_e alu_op_a_mux_sel, alu_op_a_mux_sel_dec; + op_b_sel_e alu_op_b_mux_sel, alu_op_b_mux_sel_dec; + logic alu_multicycle_dec; + logic stall_alu; + + logic [33:0] imd_val_q[2]; + + op_a_sel_e bt_a_mux_sel; + imm_b_sel_e bt_b_mux_sel; + + imm_a_sel_e imm_a_mux_sel; + imm_b_sel_e imm_b_mux_sel, imm_b_mux_sel_dec; + + // Multiplier Control + logic mult_en_id, mult_en_dec; // use integer multiplier + logic div_en_id, div_en_dec; // use integer division or reminder + logic multdiv_en_dec; + md_op_e multdiv_operator; + logic [1:0] multdiv_signed_mode; + + // Data Memory Control + logic lsu_we; + logic [1:0] lsu_type; + logic lsu_sign_ext; + logic lsu_req, lsu_req_dec; + logic data_req_allowed; + + // CSR control + logic csr_pipe_flush; + + logic [31:0] alu_operand_a; + logic [31:0] alu_operand_b; + + ///////////// + // LSU Mux // + ///////////// + + // Misaligned loads/stores result in two aligned loads/stores, compute second address + assign alu_op_a_mux_sel = lsu_addr_incr_req_i ? OP_A_FWD : alu_op_a_mux_sel_dec; + assign alu_op_b_mux_sel = lsu_addr_incr_req_i ? OP_B_IMM : alu_op_b_mux_sel_dec; + assign imm_b_mux_sel = lsu_addr_incr_req_i ? IMM_B_INCR_ADDR : imm_b_mux_sel_dec; + + /////////////////// + // Operand MUXES // + /////////////////// + + // Main ALU immediate MUX for Operand A + assign imm_a = (imm_a_mux_sel == IMM_A_Z) ? zimm_rs1_type : '0; + + // Main ALU MUX for Operand A + always_comb begin : alu_operand_a_mux + unique case (alu_op_a_mux_sel) + OP_A_REG_A: alu_operand_a = rf_rdata_a_fwd; + OP_A_FWD: alu_operand_a = lsu_addr_last_i; + OP_A_CURRPC: alu_operand_a = pc_id_i; + OP_A_IMM: alu_operand_a = imm_a; + default: alu_operand_a = pc_id_i; + endcase + end + + if (BranchTargetALU) begin : g_btalu_muxes + // Branch target ALU operand A mux + always_comb begin : bt_operand_a_mux + unique case (bt_a_mux_sel) + OP_A_REG_A: bt_a_operand_o = rf_rdata_a_fwd; + OP_A_CURRPC: bt_a_operand_o = pc_id_i; + default: bt_a_operand_o = pc_id_i; + endcase + end + + // Branch target ALU operand B mux + always_comb begin : bt_immediate_b_mux + unique case (bt_b_mux_sel) + IMM_B_I: bt_b_operand_o = imm_i_type; + IMM_B_B: bt_b_operand_o = imm_b_type; + IMM_B_J: bt_b_operand_o = imm_j_type; + IMM_B_INCR_PC: bt_b_operand_o = instr_is_compressed_i ? 32'h2 : 32'h4; + default: bt_b_operand_o = instr_is_compressed_i ? 32'h2 : 32'h4; + endcase + end + + // Reduced main ALU immediate MUX for Operand B + always_comb begin : immediate_b_mux + unique case (imm_b_mux_sel) + IMM_B_I: imm_b = imm_i_type; + IMM_B_S: imm_b = imm_s_type; + IMM_B_U: imm_b = imm_u_type; + IMM_B_INCR_PC: imm_b = instr_is_compressed_i ? 32'h2 : 32'h4; + IMM_B_INCR_ADDR: imm_b = 32'h4; + default: imm_b = 32'h4; + endcase + end + `ASSERT(IbexImmBMuxSelValid, instr_valid_i |-> imm_b_mux_sel inside { + IMM_B_I, + IMM_B_S, + IMM_B_U, + IMM_B_INCR_PC, + IMM_B_INCR_ADDR}) + end else begin : g_nobtalu + op_a_sel_e unused_a_mux_sel; + imm_b_sel_e unused_b_mux_sel; + + assign unused_a_mux_sel = bt_a_mux_sel; + assign unused_b_mux_sel = bt_b_mux_sel; + assign bt_a_operand_o = '0; + assign bt_b_operand_o = '0; + + // Full main ALU immediate MUX for Operand B + always_comb begin : immediate_b_mux + unique case (imm_b_mux_sel) + IMM_B_I: imm_b = imm_i_type; + IMM_B_S: imm_b = imm_s_type; + IMM_B_B: imm_b = imm_b_type; + IMM_B_U: imm_b = imm_u_type; + IMM_B_J: imm_b = imm_j_type; + IMM_B_INCR_PC: imm_b = instr_is_compressed_i ? 32'h2 : 32'h4; + IMM_B_INCR_ADDR: imm_b = 32'h4; + default: imm_b = 32'h4; + endcase + end + `ASSERT(IbexImmBMuxSelValid, instr_valid_i |-> imm_b_mux_sel inside { + IMM_B_I, + IMM_B_S, + IMM_B_B, + IMM_B_U, + IMM_B_J, + IMM_B_INCR_PC, + IMM_B_INCR_ADDR}) + end + + // ALU MUX for Operand B + assign alu_operand_b = (alu_op_b_mux_sel == OP_B_IMM) ? imm_b : rf_rdata_b_fwd; + + ///////////////////////////////////////// + // Multicycle Operation Stage Register // + ///////////////////////////////////////// + + for (genvar i=0; i<2; i++) begin : gen_intermediate_val_reg + always_ff @(posedge clk_i or negedge rst_ni) begin : intermediate_val_reg + if (!rst_ni) begin + imd_val_q[i] <= '0; + end else if (imd_val_we_ex_i[i]) begin + imd_val_q[i] <= imd_val_d_ex_i[i]; + end + end + end + + assign imd_val_q_ex_o = imd_val_q; + + /////////////////////// + // Register File MUX // + /////////////////////// + + // Suppress register write if there is an illegal CSR access or instruction is not executing + assign rf_we_id_o = rf_we_raw & instr_executing & ~illegal_csr_insn_i; + + // Register file write data mux + always_comb begin : rf_wdata_id_mux + unique case (rf_wdata_sel) + RF_WD_EX: rf_wdata_id_o = result_ex_i; + RF_WD_CSR: rf_wdata_id_o = csr_rdata_i; + default: rf_wdata_id_o = result_ex_i; + endcase + end + + ///////////// + // Decoder // + ///////////// + + ibex_decoder #( + .RV32E ( RV32E ), + .RV32M ( RV32M ), + .RV32B ( RV32B ), + .BranchTargetALU ( BranchTargetALU ) + ) decoder_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + // controller + .illegal_insn_o ( illegal_insn_dec ), + .ebrk_insn_o ( ebrk_insn ), + .mret_insn_o ( mret_insn_dec ), + .dret_insn_o ( dret_insn_dec ), + .ecall_insn_o ( ecall_insn_dec ), + .wfi_insn_o ( wfi_insn_dec ), + .jump_set_o ( jump_set_dec ), + .branch_taken_i ( branch_taken ), + .icache_inval_o ( icache_inval_o ), + + // from IF-ID pipeline register + .instr_first_cycle_i ( instr_first_cycle ), + .instr_rdata_i ( instr_rdata_i ), + .instr_rdata_alu_i ( instr_rdata_alu_i ), + .illegal_c_insn_i ( illegal_c_insn_i ), + + // immediates + .imm_a_mux_sel_o ( imm_a_mux_sel ), + .imm_b_mux_sel_o ( imm_b_mux_sel_dec ), + .bt_a_mux_sel_o ( bt_a_mux_sel ), + .bt_b_mux_sel_o ( bt_b_mux_sel ), + + .imm_i_type_o ( imm_i_type ), + .imm_s_type_o ( imm_s_type ), + .imm_b_type_o ( imm_b_type ), + .imm_u_type_o ( imm_u_type ), + .imm_j_type_o ( imm_j_type ), + .zimm_rs1_type_o ( zimm_rs1_type ), + + // register file + .rf_wdata_sel_o ( rf_wdata_sel ), + .rf_we_o ( rf_we_dec ), + + .rf_raddr_a_o ( rf_raddr_a_o ), + .rf_raddr_b_o ( rf_raddr_b_o ), + .rf_waddr_o ( rf_waddr_id_o ), + .rf_ren_a_o ( rf_ren_a ), + .rf_ren_b_o ( rf_ren_b ), + + // ALU + .alu_operator_o ( alu_operator ), + .alu_op_a_mux_sel_o ( alu_op_a_mux_sel_dec ), + .alu_op_b_mux_sel_o ( alu_op_b_mux_sel_dec ), + .alu_multicycle_o ( alu_multicycle_dec ), + + // MULT & DIV + .mult_en_o ( mult_en_dec ), + .div_en_o ( div_en_dec ), + .mult_sel_o ( mult_sel_ex_o ), + .div_sel_o ( div_sel_ex_o ), + .multdiv_operator_o ( multdiv_operator ), + .multdiv_signed_mode_o ( multdiv_signed_mode ), + + // CSRs + .csr_access_o ( csr_access_o ), + .csr_op_o ( csr_op_o ), + + // LSU + .data_req_o ( lsu_req_dec ), + .data_we_o ( lsu_we ), + .data_type_o ( lsu_type ), + .data_sign_extension_o ( lsu_sign_ext ), + + // jump/branches + .jump_in_dec_o ( jump_in_dec ), + .branch_in_dec_o ( branch_in_dec ) + ); + + ///////////////////////////////// + // CSR-related pipline flushes // + ///////////////////////////////// + always_comb begin : csr_pipeline_flushes + csr_pipe_flush = 1'b0; + + // A pipeline flush is needed to let the controller react after modifying certain CSRs: + // - When enabling interrupts, pending IRQs become visible to the controller only during + // the next cycle. If during that cycle the core disables interrupts again, it does not + // see any pending IRQs and consequently does not start to handle interrupts. + // - When modifying debug CSRs - TODO: Check if this is really needed + if (csr_op_en_o == 1'b1 && (csr_op_o == CSR_OP_WRITE || csr_op_o == CSR_OP_SET)) begin + if (csr_num_e'(instr_rdata_i[31:20]) == CSR_MSTATUS || + csr_num_e'(instr_rdata_i[31:20]) == CSR_MIE) begin + csr_pipe_flush = 1'b1; + end + end else if (csr_op_en_o == 1'b1 && csr_op_o != CSR_OP_READ) begin + if (csr_num_e'(instr_rdata_i[31:20]) == CSR_DCSR || + csr_num_e'(instr_rdata_i[31:20]) == CSR_DPC || + csr_num_e'(instr_rdata_i[31:20]) == CSR_DSCRATCH0 || + csr_num_e'(instr_rdata_i[31:20]) == CSR_DSCRATCH1) begin + csr_pipe_flush = 1'b1; + end + end + end + + //////////////// + // Controller // + //////////////// + + assign illegal_insn_o = instr_valid_i & (illegal_insn_dec | illegal_csr_insn_i); + + ibex_controller #( + .WritebackStage ( WritebackStage ), + .BranchPredictor ( BranchPredictor ) + ) controller_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .ctrl_busy_o ( ctrl_busy_o ), + + // decoder related signals + .illegal_insn_i ( illegal_insn_o ), + .ecall_insn_i ( ecall_insn_dec ), + .mret_insn_i ( mret_insn_dec ), + .dret_insn_i ( dret_insn_dec ), + .wfi_insn_i ( wfi_insn_dec ), + .ebrk_insn_i ( ebrk_insn ), + .csr_pipe_flush_i ( csr_pipe_flush ), + + // from IF-ID pipeline + .instr_valid_i ( instr_valid_i ), + .instr_i ( instr_rdata_i ), + .instr_compressed_i ( instr_rdata_c_i ), + .instr_is_compressed_i ( instr_is_compressed_i ), + .instr_bp_taken_i ( instr_bp_taken_i ), + .instr_fetch_err_i ( instr_fetch_err_i ), + .instr_fetch_err_plus2_i ( instr_fetch_err_plus2_i ), + .pc_id_i ( pc_id_i ), + + // to IF-ID pipeline + .instr_valid_clear_o ( instr_valid_clear_o ), + .id_in_ready_o ( id_in_ready_o ), + .controller_run_o ( controller_run ), + + // to prefetcher + .instr_req_o ( instr_req_o ), + .pc_set_o ( pc_set_o ), + .pc_set_spec_o ( pc_set_spec_o ), + .pc_mux_o ( pc_mux_o ), + .nt_branch_mispredict_o ( nt_branch_mispredict_o ), + .exc_pc_mux_o ( exc_pc_mux_o ), + .exc_cause_o ( exc_cause_o ), + + // LSU + .lsu_addr_last_i ( lsu_addr_last_i ), + .load_err_i ( lsu_load_err_i ), + .store_err_i ( lsu_store_err_i ), + .wb_exception_o ( wb_exception ), + + // jump/branch control + .branch_set_i ( branch_set ), + .branch_set_spec_i ( branch_set_spec ), + .branch_not_set_i ( branch_not_set ), + .jump_set_i ( jump_set ), + + // interrupt signals + .csr_mstatus_mie_i ( csr_mstatus_mie_i ), + .irq_pending_i ( irq_pending_i ), + .irqs_i ( irqs_i ), + .irq_nm_i ( irq_nm_i ), + .nmi_mode_o ( nmi_mode_o ), + + // CSR Controller Signals + .csr_save_if_o ( csr_save_if_o ), + .csr_save_id_o ( csr_save_id_o ), + .csr_save_wb_o ( csr_save_wb_o ), + .csr_restore_mret_id_o ( csr_restore_mret_id_o ), + .csr_restore_dret_id_o ( csr_restore_dret_id_o ), + .csr_save_cause_o ( csr_save_cause_o ), + .csr_mtval_o ( csr_mtval_o ), + .priv_mode_i ( priv_mode_i ), + .csr_mstatus_tw_i ( csr_mstatus_tw_i ), + + // Debug Signal + .debug_mode_o ( debug_mode_o ), + .debug_cause_o ( debug_cause_o ), + .debug_csr_save_o ( debug_csr_save_o ), + .debug_req_i ( debug_req_i ), + .debug_single_step_i ( debug_single_step_i ), + .debug_ebreakm_i ( debug_ebreakm_i ), + .debug_ebreaku_i ( debug_ebreaku_i ), + .trigger_match_i ( trigger_match_i ), + + .stall_id_i ( stall_id ), + .stall_wb_i ( stall_wb ), + .flush_id_o ( flush_id ), + .ready_wb_i ( ready_wb_i ), + + // Performance Counters + .perf_jump_o ( perf_jump_o ), + .perf_tbranch_o ( perf_tbranch_o ) + ); + + assign multdiv_en_dec = mult_en_dec | div_en_dec; + + assign lsu_req = instr_executing ? data_req_allowed & lsu_req_dec : 1'b0; + assign mult_en_id = instr_executing ? mult_en_dec : 1'b0; + assign div_en_id = instr_executing ? div_en_dec : 1'b0; + + assign lsu_req_o = lsu_req; + assign lsu_we_o = lsu_we; + assign lsu_type_o = lsu_type; + assign lsu_sign_ext_o = lsu_sign_ext; + assign lsu_wdata_o = rf_rdata_b_fwd; + // csr_op_en_o is set when CSR access should actually happen. + // csv_access_o is set when CSR access instruction is present and is used to compute whether a CSR + // access is illegal. A combinational loop would be created if csr_op_en_o was used along (as + // asserting it for an illegal csr access would result in a flush that would need to deassert it). + assign csr_op_en_o = csr_access_o & instr_executing & instr_id_done_o; + + assign alu_operator_ex_o = alu_operator; + assign alu_operand_a_ex_o = alu_operand_a; + assign alu_operand_b_ex_o = alu_operand_b; + + assign mult_en_ex_o = mult_en_id; + assign div_en_ex_o = div_en_id; + + assign multdiv_operator_ex_o = multdiv_operator; + assign multdiv_signed_mode_ex_o = multdiv_signed_mode; + assign multdiv_operand_a_ex_o = rf_rdata_a_fwd; + assign multdiv_operand_b_ex_o = rf_rdata_b_fwd; + + //////////////////////// + // Branch set control // + //////////////////////// + + if (BranchTargetALU && !DataIndTiming) begin : g_branch_set_direct + // Branch set fed straight to controller with branch target ALU + // (condition pass/fail used same cycle as generated instruction request) + assign branch_set = branch_set_d; + assign branch_set_spec = branch_spec; + end else begin : g_branch_set_flop + // Branch set flopped without branch target ALU, or in fixed time execution mode + // (condition pass/fail used next cycle where branch target is calculated) + logic branch_set_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + branch_set_q <= 1'b0; + end else begin + branch_set_q <= branch_set_d; + end + end + + // Branches always take two cycles in fixed time execution mode, with or without the branch + // target ALU (to avoid a path from the branch decision into the branch target ALU operand + // muxing). + assign branch_set = (BranchTargetALU && !data_ind_timing_i) ? branch_set_d : branch_set_q; + // Use the speculative branch signal when BTALU is enabled + assign branch_set_spec = (BranchTargetALU && !data_ind_timing_i) ? branch_spec : branch_set_q; + end + + // Branch condition is calculated in the first cycle and flopped for use in the second cycle + // (only used in fixed time execution mode to determine branch destination). + if (DataIndTiming) begin : g_sec_branch_taken + logic branch_taken_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + branch_taken_q <= 1'b0; + end else begin + branch_taken_q <= branch_decision_i; + end + end + + assign branch_taken = ~data_ind_timing_i | branch_taken_q; + + end else begin : g_nosec_branch_taken + + // Signal unused without fixed time execution mode - only taken branches will trigger branch_set + assign branch_taken = 1'b1; + + end + + // Holding branch_set/jump_set high for more than one cycle should not cause a functional issue. + // However it could generate needless prefetch buffer flushes and instruction fetches. The ID/EX + // designs ensures that this never happens for non-predicted branches. + `ASSERT(NeverDoubleBranch, branch_set & ~instr_bp_taken_i |=> ~branch_set) + `ASSERT(NeverDoubleJump, jump_set & ~instr_bp_taken_i |=> ~jump_set) + + /////////////// + // ID-EX FSM // + /////////////// + + typedef enum logic { FIRST_CYCLE, MULTI_CYCLE } id_fsm_e; + id_fsm_e id_fsm_q, id_fsm_d; + + always_ff @(posedge clk_i or negedge rst_ni) begin : id_pipeline_reg + if (!rst_ni) begin + id_fsm_q <= FIRST_CYCLE; + end else begin + id_fsm_q <= id_fsm_d; + end + end + + // ID/EX stage can be in two states, FIRST_CYCLE and MULTI_CYCLE. An instruction enters + // MULTI_CYCLE if it requires multiple cycles to complete regardless of stalls and other + // considerations. An instruction may be held in FIRST_CYCLE if it's unable to begin executing + // (this is controlled by instr_executing). + + always_comb begin + id_fsm_d = id_fsm_q; + rf_we_raw = rf_we_dec; + stall_multdiv = 1'b0; + stall_jump = 1'b0; + stall_branch = 1'b0; + stall_alu = 1'b0; + branch_set_d = 1'b0; + branch_spec = 1'b0; + branch_not_set = 1'b0; + jump_set = 1'b0; + perf_branch_o = 1'b0; + + if (instr_executing) begin + unique case (id_fsm_q) + FIRST_CYCLE: begin + unique case (1'b1) + lsu_req_dec: begin + if (!WritebackStage) begin + // LSU operation + id_fsm_d = MULTI_CYCLE; + end else begin + if(~lsu_req_done_i) begin + id_fsm_d = MULTI_CYCLE; + end + end + end + multdiv_en_dec: begin + // MUL or DIV operation + if (~ex_valid_i) begin + // When single-cycle multiply is configured mul can finish in the first cycle so + // only enter MULTI_CYCLE state if a result isn't immediately available + id_fsm_d = MULTI_CYCLE; + rf_we_raw = 1'b0; + stall_multdiv = 1'b1; + end + end + branch_in_dec: begin + // cond branch operation + // All branches take two cycles in fixed time execution mode, regardless of branch + // condition. + id_fsm_d = (data_ind_timing_i || (!BranchTargetALU && branch_decision_i)) ? + MULTI_CYCLE : FIRST_CYCLE; + stall_branch = (~BranchTargetALU & branch_decision_i) | data_ind_timing_i; + branch_set_d = branch_decision_i | data_ind_timing_i; + + if (BranchPredictor) begin + branch_not_set = ~branch_decision_i; + end + + // Speculative branch (excludes branch_decision_i) + branch_spec = SpecBranch ? 1'b1 : branch_decision_i; + perf_branch_o = 1'b1; + end + jump_in_dec: begin + // uncond branch operation + // BTALU means jumps only need one cycle + id_fsm_d = BranchTargetALU ? FIRST_CYCLE : MULTI_CYCLE; + stall_jump = ~BranchTargetALU; + jump_set = jump_set_dec; + end + alu_multicycle_dec: begin + stall_alu = 1'b1; + id_fsm_d = MULTI_CYCLE; + rf_we_raw = 1'b0; + end + default: begin + id_fsm_d = FIRST_CYCLE; + end + endcase + end + + MULTI_CYCLE: begin + if(multdiv_en_dec) begin + rf_we_raw = rf_we_dec & ex_valid_i; + end + + if (multicycle_done & ready_wb_i) begin + id_fsm_d = FIRST_CYCLE; + end else begin + stall_multdiv = multdiv_en_dec; + stall_branch = branch_in_dec; + stall_jump = jump_in_dec; + end + end + + default: begin + id_fsm_d = FIRST_CYCLE; + end + endcase + end + end + + // Note for the two-stage configuration ready_wb_i is always set + assign multdiv_ready_id_o = ready_wb_i; + + `ASSERT(StallIDIfMulticycle, (id_fsm_q == FIRST_CYCLE) & (id_fsm_d == MULTI_CYCLE) |-> stall_id) + + // Stall ID/EX stage for reason that relates to instruction in ID/EX + assign stall_id = stall_ld_hz | stall_mem | stall_multdiv | stall_jump | stall_branch | + stall_alu; + + assign instr_done = ~stall_id & ~flush_id & instr_executing; + + // Signal instruction in ID is in it's first cycle. It can remain in its + // first cycle if it is stalled. + assign instr_first_cycle = instr_valid_i & (id_fsm_q == FIRST_CYCLE); + // Used by RVFI to know when to capture register read data + // Used by ALU to access RS3 if ternary instruction. + assign instr_first_cycle_id_o = instr_first_cycle; + + if (WritebackStage) begin : gen_stall_mem + // Register read address matches write address in WB + logic rf_rd_a_wb_match; + logic rf_rd_b_wb_match; + // Hazard between registers being read and written + logic rf_rd_a_hz; + logic rf_rd_b_hz; + + logic outstanding_memory_access; + + logic instr_kill; + + assign multicycle_done = lsu_req_dec ? ~stall_mem : ex_valid_i; + + // Is a memory access ongoing that isn't finishing this cycle + assign outstanding_memory_access = (outstanding_load_wb_i | outstanding_store_wb_i) & + ~lsu_resp_valid_i; + + // Can start a new memory access if any previous one has finished or is finishing + assign data_req_allowed = ~outstanding_memory_access; + + // Instruction won't execute because: + // - There is a pending exception in writeback + // The instruction in ID/EX will be flushed and the core will jump to an exception handler + // - The controller isn't running instructions + // This either happens in preparation for a flush and jump to an exception handler e.g. in + // response to an IRQ or debug request or whilst the core is sleeping or resetting/fetching + // first instruction in which case any valid instruction in ID/EX should be ignored. + // - There was an error on instruction fetch + assign instr_kill = instr_fetch_err_i | + wb_exception | + ~controller_run; + + // With writeback stage instructions must be prevented from executing if there is: + // - A load hazard + // - A pending memory access + // If it receives an error response this results in a precise exception from WB so ID/EX + // instruction must not execute until error response is known). + // - A load/store error + // This will cause a precise exception for the instruction in WB so ID/EX instruction must not + // execute + assign instr_executing = instr_valid_i & + ~instr_kill & + ~stall_ld_hz & + ~outstanding_memory_access; + + `ASSERT(IbexStallIfValidInstrNotExecuting, + instr_valid_i & ~instr_kill & ~instr_executing |-> stall_id) + + // Stall for reasons related to memory: + // * There is an outstanding memory access that won't resolve this cycle (need to wait to allow + // precise exceptions) + // * There is a load/store request not being granted or which is unaligned and waiting to issue + // a second request (needs to stay in ID for the address calculation) + assign stall_mem = instr_valid_i & + (outstanding_memory_access | (lsu_req_dec & ~lsu_req_done_i)); + + // If we stall a load in ID for any reason, it must not make an LSU request + // (otherwide we might issue two requests for the same instruction) + `ASSERT(IbexStallMemNoRequest, + instr_valid_i & lsu_req_dec & ~instr_done |-> ~lsu_req_done_i) + + assign rf_rd_a_wb_match = (rf_waddr_wb_i == rf_raddr_a_o) & |rf_raddr_a_o; + assign rf_rd_b_wb_match = (rf_waddr_wb_i == rf_raddr_b_o) & |rf_raddr_b_o; + + assign rf_rd_a_wb_match_o = rf_rd_a_wb_match; + assign rf_rd_b_wb_match_o = rf_rd_b_wb_match; + + // If instruction is reading register that load will be writing stall in + // ID until load is complete. No need to stall when reading zero register. + assign rf_rd_a_hz = rf_rd_a_wb_match & rf_ren_a; + assign rf_rd_b_hz = rf_rd_b_wb_match & rf_ren_b; + + // If instruction is read register that writeback is writing forward writeback data to read + // data. Note this doesn't factor in load data as it arrives too late, such hazards are + // resolved via a stall (see above). + assign rf_rdata_a_fwd = rf_rd_a_wb_match & rf_write_wb_i ? rf_wdata_fwd_wb_i : rf_rdata_a_i; + assign rf_rdata_b_fwd = rf_rd_b_wb_match & rf_write_wb_i ? rf_wdata_fwd_wb_i : rf_rdata_b_i; + + assign stall_ld_hz = outstanding_load_wb_i & (rf_rd_a_hz | rf_rd_b_hz); + + assign instr_type_wb_o = ~lsu_req_dec ? WB_INSTR_OTHER : + lsu_we ? WB_INSTR_STORE : + WB_INSTR_LOAD; + + assign instr_id_done_o = en_wb_o & ready_wb_i; + + // Stall ID/EX as instruction in ID/EX cannot proceed to writeback yet + assign stall_wb = en_wb_o & ~ready_wb_i; + + assign perf_dside_wait_o = instr_valid_i & ~instr_kill & + (outstanding_memory_access | stall_ld_hz); + end else begin : gen_no_stall_mem + + assign multicycle_done = lsu_req_dec ? lsu_resp_valid_i : ex_valid_i; + + assign data_req_allowed = instr_first_cycle; + + // Without Writeback Stage always stall the first cycle of a load/store. + // Then stall until it is complete + assign stall_mem = instr_valid_i & (lsu_req_dec & (~lsu_resp_valid_i | instr_first_cycle)); + + // No load hazards without Writeback Stage + assign stall_ld_hz = 1'b0; + + // Without writeback stage any valid instruction that hasn't seen an error will execute + assign instr_executing = instr_valid_i & ~instr_fetch_err_i & controller_run; + + `ASSERT(IbexStallIfValidInstrNotExecuting, + instr_valid_i & ~instr_fetch_err_i & ~instr_executing & controller_run |-> stall_id) + + // No data forwarding without writeback stage so always take source register data direct from + // register file + assign rf_rdata_a_fwd = rf_rdata_a_i; + assign rf_rdata_b_fwd = rf_rdata_b_i; + + assign rf_rd_a_wb_match_o = 1'b0; + assign rf_rd_b_wb_match_o = 1'b0; + + // Unused Writeback stage only IO & wiring + // Assign inputs and internal wiring to unused signals to satisfy lint checks + // Tie-off outputs to constant values + logic unused_data_req_done_ex; + logic [4:0] unused_rf_waddr_wb; + logic unused_rf_write_wb; + logic unused_outstanding_load_wb; + logic unused_outstanding_store_wb; + logic unused_wb_exception; + logic [31:0] unused_rf_wdata_fwd_wb; + + assign unused_data_req_done_ex = lsu_req_done_i; + assign unused_rf_waddr_wb = rf_waddr_wb_i; + assign unused_rf_write_wb = rf_write_wb_i; + assign unused_outstanding_load_wb = outstanding_load_wb_i; + assign unused_outstanding_store_wb = outstanding_store_wb_i; + assign unused_wb_exception = wb_exception; + assign unused_rf_wdata_fwd_wb = rf_wdata_fwd_wb_i; + + assign instr_type_wb_o = WB_INSTR_OTHER; + assign stall_wb = 1'b0; + + assign perf_dside_wait_o = instr_executing & lsu_req_dec & ~lsu_resp_valid_i; + + assign instr_id_done_o = instr_done; + end + + // Signal which instructions to count as retired in minstret, all traps along with ebrk and + // ecall instructions are not counted. + assign instr_perf_count_id_o = ~ebrk_insn & ~ecall_insn_dec & ~illegal_insn_dec & + ~illegal_csr_insn_i & ~instr_fetch_err_i; + + // An instruction is ready to move to the writeback stage (or retire if there is no writeback + // stage) + assign en_wb_o = instr_done; + + assign perf_mul_wait_o = stall_multdiv & mult_en_dec; + assign perf_div_wait_o = stall_multdiv & div_en_dec; + + //////////////// + // Assertions // + //////////////// + + // Selectors must be known/valid. + `ASSERT_KNOWN_IF(IbexAluOpMuxSelKnown, alu_op_a_mux_sel, instr_valid_i) + `ASSERT(IbexAluAOpMuxSelValid, instr_valid_i |-> alu_op_a_mux_sel inside { + OP_A_REG_A, + OP_A_FWD, + OP_A_CURRPC, + OP_A_IMM}) + `ASSERT_KNOWN_IF(IbexBTAluAOpMuxSelKnown, bt_a_mux_sel, instr_valid_i) + `ASSERT(IbexBTAluAOpMuxSelValid, instr_valid_i |-> bt_a_mux_sel inside { + OP_A_REG_A, + OP_A_CURRPC}) + `ASSERT_KNOWN_IF(IbexBTAluBOpMuxSelKnown, bt_b_mux_sel, instr_valid_i) + `ASSERT(IbexBTAluBOpMuxSelValid, instr_valid_i |-> bt_b_mux_sel inside { + IMM_B_I, + IMM_B_B, + IMM_B_J, + IMM_B_INCR_PC}) + `ASSERT(IbexRegfileWdataSelValid, instr_valid_i |-> rf_wdata_sel inside { + RF_WD_EX, + RF_WD_CSR}) + `ASSERT_KNOWN(IbexWbStateKnown, id_fsm_q) + + // Branch decision must be valid when jumping. + `ASSERT_KNOWN_IF(IbexBranchDecisionValid, branch_decision_i, + instr_valid_i && !(illegal_csr_insn_i || instr_fetch_err_i)) + + // Instruction delivered to ID stage can not contain X. + `ASSERT_KNOWN_IF(IbexIdInstrKnown, instr_rdata_i, + instr_valid_i && !(illegal_c_insn_i || instr_fetch_err_i)) + + // Instruction delivered to ID stage can not contain X. + `ASSERT_KNOWN_IF(IbexIdInstrALUKnown, instr_rdata_alu_i, + instr_valid_i && !(illegal_c_insn_i || instr_fetch_err_i)) + + // Multicycle enable signals must be unique. + `ASSERT(IbexMulticycleEnableUnique, + $onehot0({lsu_req_dec, multdiv_en_dec, branch_in_dec, jump_in_dec})) + + // Duplicated instruction flops must match + // === as DV environment can produce instructions with Xs in, so must use precise match that + // includes Xs + `ASSERT(IbexDuplicateInstrMatch, instr_valid_i |-> instr_rdata_i === instr_rdata_alu_i) + + `ifdef CHECK_MISALIGNED + `ASSERT(IbexMisalignedMemoryAccess, !lsu_addr_incr_req_i) + `endif + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_if_stage.sv b/flow/designs/src/ibex_sv/ibex_if_stage.sv new file mode 100644 index 0000000000..ee217a8c44 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_if_stage.sv @@ -0,0 +1,614 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Instruction Fetch Stage + * + * Instruction fetch unit: Selection of the next PC, and buffering (sampling) of + * the read instruction. + */ + +`include "prim_assert.sv" + +module ibex_if_stage #( + parameter int unsigned DmHaltAddr = 32'h1A110800, + parameter int unsigned DmExceptionAddr = 32'h1A110808, + parameter bit DummyInstructions = 1'b0, + parameter bit ICache = 1'b0, + parameter bit ICacheECC = 1'b0, + parameter bit PCIncrCheck = 1'b0, + parameter bit BranchPredictor = 1'b0 +) ( + input logic clk_i, + input logic rst_ni, + + input logic [31:0] boot_addr_i, // also used for mtvec + input logic req_i, // instruction request control + + // instruction cache interface + output logic instr_req_o, + output logic [31:0] instr_addr_o, + input logic instr_gnt_i, + input logic instr_rvalid_i, + input logic [31:0] instr_rdata_i, + input logic instr_err_i, + input logic instr_pmp_err_i, + + // output of ID stage + output logic instr_valid_id_o, // instr in IF-ID is valid + output logic instr_new_id_o, // instr in IF-ID is new + output logic [31:0] instr_rdata_id_o, // instr for ID stage + output logic [31:0] instr_rdata_alu_id_o, // replicated instr for ID stage + // to reduce fan-out + output logic [15:0] instr_rdata_c_id_o, // compressed instr for ID stage + // (mtval), meaningful only if + // instr_is_compressed_id_o = 1'b1 + output logic instr_is_compressed_id_o, // compressed decoder thinks this + // is a compressed instr + output logic instr_bp_taken_o, // instruction was predicted to be + // a taken branch + output logic instr_fetch_err_o, // bus error on fetch + output logic instr_fetch_err_plus2_o, // bus error misaligned + output logic illegal_c_insn_id_o, // compressed decoder thinks this + // is an invalid instr + output logic dummy_instr_id_o, // Instruction is a dummy + output logic [31:0] pc_if_o, + output logic [31:0] pc_id_o, + + // control signals + input logic instr_valid_clear_i, // clear instr valid bit in IF-ID + input logic pc_set_i, // set the PC to a new value + input logic pc_set_spec_i, + input ibex_pkg::pc_sel_e pc_mux_i, // selector for PC multiplexer + input logic nt_branch_mispredict_i, // Not-taken branch in ID/EX was + // mispredicted (predicted taken) + input ibex_pkg::exc_pc_sel_e exc_pc_mux_i, // selects ISR address + input ibex_pkg::exc_cause_e exc_cause, // selects ISR address for + // vectorized interrupt lines + input logic dummy_instr_en_i, + input logic [2:0] dummy_instr_mask_i, + input logic dummy_instr_seed_en_i, + input logic [31:0] dummy_instr_seed_i, + input logic icache_enable_i, + input logic icache_inval_i, + + // jump and branch target + input logic [31:0] branch_target_ex_i, // branch/jump target address + + // CSRs + input logic [31:0] csr_mepc_i, // PC to restore after handling + // the interrupt/exception + input logic [31:0] csr_depc_i, // PC to restore after handling + // the debug request + input logic [31:0] csr_mtvec_i, // base PC to jump to on exception + output logic csr_mtvec_init_o, // tell CS regfile to init mtvec + + // pipeline stall + input logic id_in_ready_i, // ID stage is ready for new instr + + // misc signals + output logic pc_mismatch_alert_o, + output logic if_busy_o // IF stage is busy fetching instr +); + + import ibex_pkg::*; + + logic instr_valid_id_d, instr_valid_id_q; + logic instr_new_id_d, instr_new_id_q; + + // prefetch buffer related signals + logic prefetch_busy; + logic branch_req; + logic branch_spec; + logic predicted_branch; + logic [31:0] fetch_addr_n; + logic unused_fetch_addr_n0; + + logic fetch_valid; + logic fetch_ready; + logic [31:0] fetch_rdata; + logic [31:0] fetch_addr; + logic fetch_err; + logic fetch_err_plus2; + + logic if_instr_valid; + logic [31:0] if_instr_rdata; + logic [31:0] if_instr_addr; + logic if_instr_err; + + logic [31:0] exc_pc; + + logic [5:0] irq_id; + logic unused_irq_bit; + + logic if_id_pipe_reg_we; // IF-ID pipeline reg write enable + + // Dummy instruction signals + logic stall_dummy_instr; + logic [31:0] instr_out; + logic instr_is_compressed_out; + logic illegal_c_instr_out; + logic instr_err_out; + + logic predict_branch_taken; + logic [31:0] predict_branch_pc; + + ibex_pkg::pc_sel_e pc_mux_internal; + + logic [7:0] unused_boot_addr; + logic [7:0] unused_csr_mtvec; + + assign unused_boot_addr = boot_addr_i[7:0]; + assign unused_csr_mtvec = csr_mtvec_i[7:0]; + + // extract interrupt ID from exception cause + assign irq_id = {exc_cause}; + assign unused_irq_bit = irq_id[5]; // MSB distinguishes interrupts from exceptions + + // exception PC selection mux + always_comb begin : exc_pc_mux + unique case (exc_pc_mux_i) + EXC_PC_EXC: exc_pc = { csr_mtvec_i[31:8], 8'h00 }; + EXC_PC_IRQ: exc_pc = { csr_mtvec_i[31:8], 1'b0, irq_id[4:0], 2'b00 }; + EXC_PC_DBD: exc_pc = DmHaltAddr; + EXC_PC_DBG_EXC: exc_pc = DmExceptionAddr; + default: exc_pc = { csr_mtvec_i[31:8], 8'h00 }; + endcase + end + + // The Branch predictor can provide a new PC which is internal to if_stage. Only override the mux + // select to choose this if the core isn't already trying to set a PC. + assign pc_mux_internal = + (BranchPredictor && predict_branch_taken && !pc_set_i) ? PC_BP : pc_mux_i; + + // fetch address selection mux + always_comb begin : fetch_addr_mux + unique case (pc_mux_internal) + PC_BOOT: fetch_addr_n = { boot_addr_i[31:8], 8'h80 }; + PC_JUMP: fetch_addr_n = branch_target_ex_i; + PC_EXC: fetch_addr_n = exc_pc; // set PC to exception handler + PC_ERET: fetch_addr_n = csr_mepc_i; // restore PC when returning from EXC + PC_DRET: fetch_addr_n = csr_depc_i; + // Without branch predictor will never get pc_mux_internal == PC_BP. We still handle no branch + // predictor case here to ensure redundant mux logic isn't synthesised. + PC_BP: fetch_addr_n = BranchPredictor ? predict_branch_pc : { boot_addr_i[31:8], 8'h80 }; + default: fetch_addr_n = { boot_addr_i[31:8], 8'h80 }; + endcase + end + + // tell CS register file to initialize mtvec on boot + assign csr_mtvec_init_o = (pc_mux_i == PC_BOOT) & pc_set_i; + + if (ICache) begin : gen_icache + // Full I-Cache option + ibex_icache #( + .ICacheECC (ICacheECC) + ) icache_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .req_i ( req_i ), + + .branch_i ( branch_req ), + .branch_spec_i ( branch_spec ), + .addr_i ( {fetch_addr_n[31:1], 1'b0} ), + + .ready_i ( fetch_ready ), + .valid_o ( fetch_valid ), + .rdata_o ( fetch_rdata ), + .addr_o ( fetch_addr ), + .err_o ( fetch_err ), + .err_plus2_o ( fetch_err_plus2 ), + + .instr_req_o ( instr_req_o ), + .instr_addr_o ( instr_addr_o ), + .instr_gnt_i ( instr_gnt_i ), + .instr_rvalid_i ( instr_rvalid_i ), + .instr_rdata_i ( instr_rdata_i ), + .instr_err_i ( instr_err_i ), + .instr_pmp_err_i ( instr_pmp_err_i ), + + .icache_enable_i ( icache_enable_i ), + .icache_inval_i ( icache_inval_i ), + .busy_o ( prefetch_busy ) + ); + // Branch predictor tie-offs (which are unused when the instruction cache is enabled) + logic unused_nt_branch_mispredict, unused_predicted_branch; + assign unused_nt_branch_mispredict = nt_branch_mispredict_i; + assign unused_predicted_branch = predicted_branch; + end else begin : gen_prefetch_buffer + // prefetch buffer, caches a fixed number of instructions + ibex_prefetch_buffer #( + .BranchPredictor (BranchPredictor) + ) prefetch_buffer_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .req_i ( req_i ), + + .branch_i ( branch_req ), + .branch_spec_i ( branch_spec ), + .predicted_branch_i ( predicted_branch ), + .branch_mispredict_i ( nt_branch_mispredict_i ), + .addr_i ( {fetch_addr_n[31:1], 1'b0} ), + + .ready_i ( fetch_ready ), + .valid_o ( fetch_valid ), + .rdata_o ( fetch_rdata ), + .addr_o ( fetch_addr ), + .err_o ( fetch_err ), + .err_plus2_o ( fetch_err_plus2 ), + + .instr_req_o ( instr_req_o ), + .instr_addr_o ( instr_addr_o ), + .instr_gnt_i ( instr_gnt_i ), + .instr_rvalid_i ( instr_rvalid_i ), + .instr_rdata_i ( instr_rdata_i ), + .instr_err_i ( instr_err_i ), + .instr_pmp_err_i ( instr_pmp_err_i ), + + .busy_o ( prefetch_busy ) + ); + // ICache tieoffs + logic unused_icen, unused_icinv; + assign unused_icen = icache_enable_i; + assign unused_icinv = icache_inval_i; + end + + assign unused_fetch_addr_n0 = fetch_addr_n[0]; + + assign branch_req = pc_set_i | predict_branch_taken; + assign branch_spec = pc_set_spec_i | predict_branch_taken; + + assign pc_if_o = if_instr_addr; + assign if_busy_o = prefetch_busy; + + // compressed instruction decoding, or more precisely compressed instruction + // expander + // + // since it does not matter where we decompress instructions, we do it here + // to ease timing closure + logic [31:0] instr_decompressed; + logic illegal_c_insn; + logic instr_is_compressed; + + ibex_compressed_decoder compressed_decoder_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( fetch_valid & ~fetch_err ), + .instr_i ( if_instr_rdata ), + .instr_o ( instr_decompressed ), + .is_compressed_o ( instr_is_compressed ), + .illegal_instr_o ( illegal_c_insn ) + ); + + // Dummy instruction insertion + if (DummyInstructions) begin : gen_dummy_instr + logic insert_dummy_instr; + logic [31:0] dummy_instr_data; + + ibex_dummy_instr dummy_instr_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .dummy_instr_en_i ( dummy_instr_en_i ), + .dummy_instr_mask_i ( dummy_instr_mask_i ), + .dummy_instr_seed_en_i ( dummy_instr_seed_en_i ), + .dummy_instr_seed_i ( dummy_instr_seed_i ), + .fetch_valid_i ( fetch_valid ), + .id_in_ready_i ( id_in_ready_i ), + .insert_dummy_instr_o ( insert_dummy_instr ), + .dummy_instr_data_o ( dummy_instr_data ) + ); + + // Mux between actual instructions and dummy instructions + assign instr_out = insert_dummy_instr ? dummy_instr_data : instr_decompressed; + assign instr_is_compressed_out = insert_dummy_instr ? 1'b0 : instr_is_compressed; + assign illegal_c_instr_out = insert_dummy_instr ? 1'b0 : illegal_c_insn; + assign instr_err_out = insert_dummy_instr ? 1'b0 : if_instr_err; + + // Stall the IF stage if we insert a dummy instruction. The dummy will execute between whatever + // is currently in the ID stage and whatever is valid from the prefetch buffer this cycle. The + // PC of the dummy instruction will match whatever is next from the prefetch buffer. + assign stall_dummy_instr = insert_dummy_instr; + + // Register the dummy instruction indication into the ID stage + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + dummy_instr_id_o <= 1'b0; + end else if (if_id_pipe_reg_we) begin + dummy_instr_id_o <= insert_dummy_instr; + end + end + + end else begin : gen_no_dummy_instr + logic unused_dummy_en; + logic [2:0] unused_dummy_mask; + logic unused_dummy_seed_en; + logic [31:0] unused_dummy_seed; + + assign unused_dummy_en = dummy_instr_en_i; + assign unused_dummy_mask = dummy_instr_mask_i; + assign unused_dummy_seed_en = dummy_instr_seed_en_i; + assign unused_dummy_seed = dummy_instr_seed_i; + assign instr_out = instr_decompressed; + assign instr_is_compressed_out = instr_is_compressed; + assign illegal_c_instr_out = illegal_c_insn; + assign instr_err_out = if_instr_err; + assign stall_dummy_instr = 1'b0; + assign dummy_instr_id_o = 1'b0; + end + + // The ID stage becomes valid as soon as any instruction is registered in the ID stage flops. + // Note that the current instruction is squashed by the incoming pc_set_i signal. + // Valid is held until it is explicitly cleared (due to an instruction completing or an exception) + assign instr_valid_id_d = (if_instr_valid & id_in_ready_i & ~pc_set_i) | + (instr_valid_id_q & ~instr_valid_clear_i); + assign instr_new_id_d = if_instr_valid & id_in_ready_i; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + instr_valid_id_q <= 1'b0; + instr_new_id_q <= 1'b0; + end else begin + instr_valid_id_q <= instr_valid_id_d; + instr_new_id_q <= instr_new_id_d; + end + end + + assign instr_valid_id_o = instr_valid_id_q; + // Signal when a new instruction enters the ID stage (only used for RVFI signalling). + assign instr_new_id_o = instr_new_id_q; + + // IF-ID pipeline registers, frozen when the ID stage is stalled + assign if_id_pipe_reg_we = instr_new_id_d; + + always_ff @(posedge clk_i) begin + if (if_id_pipe_reg_we) begin + instr_rdata_id_o <= instr_out; + // To reduce fan-out and help timing from the instr_rdata_id flops they are replicated. + instr_rdata_alu_id_o <= instr_out; + instr_fetch_err_o <= instr_err_out; + instr_fetch_err_plus2_o <= fetch_err_plus2; + instr_rdata_c_id_o <= if_instr_rdata[15:0]; + instr_is_compressed_id_o <= instr_is_compressed_out; + illegal_c_insn_id_o <= illegal_c_instr_out; + pc_id_o <= pc_if_o; + end + end + + // Check for expected increments of the PC when security hardening enabled + if (PCIncrCheck) begin : g_secure_pc + logic [31:0] prev_instr_addr_incr; + logic prev_instr_seq_q, prev_instr_seq_d; + + // Do not check for sequential increase after a branch, jump, exception, interrupt or debug + // request, all of which will set branch_req. Also do not check after reset or for dummys. + assign prev_instr_seq_d = (prev_instr_seq_q | instr_new_id_d) & + ~branch_req & ~stall_dummy_instr; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + prev_instr_seq_q <= 1'b0; + end else begin + prev_instr_seq_q <= prev_instr_seq_d; + end + end + + assign prev_instr_addr_incr = pc_id_o + ((instr_is_compressed_id_o && !instr_fetch_err_o) ? + 32'd2 : 32'd4); + + // Check that the address equals the previous address +2/+4 + assign pc_mismatch_alert_o = prev_instr_seq_q & (pc_if_o != prev_instr_addr_incr); + + end else begin : g_no_secure_pc + assign pc_mismatch_alert_o = 1'b0; + end + + if (BranchPredictor) begin : g_branch_predictor + logic [31:0] instr_skid_data_q; + logic [31:0] instr_skid_addr_q; + logic instr_skid_bp_taken_q; + logic instr_skid_valid_q, instr_skid_valid_d; + logic instr_skid_en; + logic instr_bp_taken_q, instr_bp_taken_d; + + logic predict_branch_taken_raw; + + // ID stages needs to know if branch was predicted taken so it can signal mispredicts + always_ff @(posedge clk_i) begin + if (if_id_pipe_reg_we) begin + instr_bp_taken_q <= instr_bp_taken_d; + end + end + + // When branch prediction is enabled a skid buffer between the IF and ID/EX stage is introduced. + // If an instruction in IF is predicted to be a taken branch and ID/EX is not ready the + // instruction in IF is moved to the skid buffer which becomes the output of the IF stage until + // the ID/EX stage accepts the instruction. The skid buffer is required as otherwise the ID/EX + // ready signal is coupled to the instr_req_o output which produces a feedthrough path from + // data_gnt_i -> instr_req_o (which needs to be avoided as for some interconnects this will + // result in a combinational loop). + + assign instr_skid_en = predicted_branch & ~id_in_ready_i & ~instr_skid_valid_q; + + assign instr_skid_valid_d = (instr_skid_valid_q & ~id_in_ready_i & ~stall_dummy_instr) | + instr_skid_en; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + instr_skid_valid_q <= 1'b0; + end else begin + instr_skid_valid_q <= instr_skid_valid_d; + end + end + + always_ff @(posedge clk_i) begin + if (instr_skid_en) begin + instr_skid_bp_taken_q <= predict_branch_taken; + instr_skid_data_q <= fetch_rdata; + instr_skid_addr_q <= fetch_addr; + end + end + + ibex_branch_predict branch_predict_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .fetch_rdata_i ( fetch_rdata ), + .fetch_pc_i ( fetch_addr ), + .fetch_valid_i ( fetch_valid ), + + .predict_branch_taken_o ( predict_branch_taken_raw ), + .predict_branch_pc_o ( predict_branch_pc ) + ); + + // If there is an instruction in the skid buffer there must be no branch prediction. + // Instructions are only placed in the skid after they have been predicted to be a taken branch + // so with the skid valid any prediction has already occurred. + // Do not branch predict on instruction errors. + assign predict_branch_taken = predict_branch_taken_raw & ~instr_skid_valid_q & ~fetch_err; + + // pc_set_i takes precendence over branch prediction + assign predicted_branch = predict_branch_taken & ~pc_set_i; + + assign if_instr_valid = fetch_valid | instr_skid_valid_q; + assign if_instr_rdata = instr_skid_valid_q ? instr_skid_data_q : fetch_rdata; + assign if_instr_addr = instr_skid_valid_q ? instr_skid_addr_q : fetch_addr; + + // Don't branch predict on instruction error so only instructions without errors end up in the + // skid buffer. + assign if_instr_err = ~instr_skid_valid_q & fetch_err; + assign instr_bp_taken_d = instr_skid_valid_q ? instr_skid_bp_taken_q : predict_branch_taken; + + assign fetch_ready = id_in_ready_i & ~stall_dummy_instr & ~instr_skid_valid_q; + + assign instr_bp_taken_o = instr_bp_taken_q; + + `ASSERT(NoPredictSkid, instr_skid_valid_q |-> ~predict_branch_taken) + `ASSERT(NoPredictIllegal, predict_branch_taken |-> ~illegal_c_insn) + end else begin : g_no_branch_predictor + assign instr_bp_taken_o = 1'b0; + assign predict_branch_taken = 1'b0; + assign predicted_branch = 1'b0; + assign predict_branch_pc = 32'b0; + + assign if_instr_valid = fetch_valid; + assign if_instr_rdata = fetch_rdata; + assign if_instr_addr = fetch_addr; + assign if_instr_err = fetch_err; + assign fetch_ready = id_in_ready_i & ~stall_dummy_instr; + end + + //////////////// + // Assertions // + //////////////// + + // Selectors must be known/valid. + `ASSERT_KNOWN(IbexExcPcMuxKnown, exc_pc_mux_i) + + if (BranchPredictor) begin : g_branch_predictor_asserts + `ASSERT_IF(IbexPcMuxValid, pc_mux_internal inside { + PC_BOOT, + PC_JUMP, + PC_EXC, + PC_ERET, + PC_DRET, + PC_BP}, + pc_set_i) + +`ifdef INC_ASSERT + /** + * Checks for branch prediction interface to fetch_fifo/icache + * + * The interface has two signals: + * - predicted_branch_i: When set with a branch (branch_i) indicates the branch is a predicted + * one, it should be ignored when a branch_i isn't set. + * - branch_mispredict_i: Indicates the previously predicted branch was mis-predicted and + * execution should resume with the not-taken side of the branch (i.e. continue with the PC + * that followed the predicted branch). This must be raised before the instruction that is + * made available following a predicted branch is accepted (Following a cycle with branch_i + * & predicted_branch_i, branch_mispredict_i can only be asserted before or on the same cycle + * as seeing fetch_valid & fetch_ready). When branch_mispredict_i is asserted, fetch_valid may + * be asserted in response. If fetch_valid is asserted on the same cycle as + * branch_mispredict_i this indicates the fetch_fifo/icache has the not-taken side of the + * branch immediately ready for use + */ + logic predicted_branch_live_q, predicted_branch_live_d; + logic [31:0] predicted_branch_nt_pc_q, predicted_branch_nt_pc_d; + logic [31:0] awaiting_instr_after_mispredict_q, awaiting_instr_after_mispredict_d; + logic [31:0] next_pc; + + logic mispredicted, mispredicted_d, mispredicted_q; + + assign next_pc = fetch_addr + (instr_is_compressed_out ? 32'd2 : 32'd4); + + always_comb begin + predicted_branch_live_d = predicted_branch_live_q; + mispredicted_d = mispredicted_q; + + if (branch_req & predicted_branch) begin + predicted_branch_live_d = 1'b1; + mispredicted_d = 1'b0; + end else if (predicted_branch_live_q) begin + if (fetch_valid & fetch_ready) begin + predicted_branch_live_d = 1'b0; + end else if (nt_branch_mispredict_i) begin + mispredicted_d = 1'b1; + end + end + end + + always @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + predicted_branch_live_q <= 1'b0; + mispredicted_q <= 1'b0; + end else begin + predicted_branch_live_q <= predicted_branch_live_d; + mispredicted_q <= mispredicted_d; + end + end + + always @(posedge clk_i) begin + if (branch_req & predicted_branch) begin + predicted_branch_nt_pc_q <= next_pc; + end + end + + // Must only see mispredict after we've performed a predicted branch but before we've accepted + // any instruction (with fetch_ready & fetch_valid) that follows that predicted branch. + `ASSERT(MispredictOnlyImmediatelyAfterPredictedBranch, + nt_branch_mispredict_i |-> predicted_branch_live_q) + // Check that on mispredict we get the correct PC for the non-taken side of the branch when + // prefetch buffer/icache makes that PC available. + `ASSERT(CorrectPCOnMispredict, + predicted_branch_live_q & mispredicted_d & fetch_valid |-> + fetch_addr == predicted_branch_nt_pc_q) + // Must not signal mispredict over multiple cycles but it's possible to have back to back + // mispredicts for different branches (core signals mispredict, prefetch buffer/icache immediate + // has not-taken side of the mispredicted branch ready, which itself is a predicted branch, + // following cycle core signal that that branch has mispredicted). + `ASSERT(MispredictSingleCycle, + nt_branch_mispredict_i & ~(fetch_valid & fetch_ready) |=> ~nt_branch_mispredict_i) +`endif + + end else begin : g_no_branch_predictor_asserts + `ASSERT_IF(IbexPcMuxValid, pc_mux_internal inside { + PC_BOOT, + PC_JUMP, + PC_EXC, + PC_ERET, + PC_DRET}, + pc_set_i) + end + + // Boot address must be aligned to 256 bytes. + `ASSERT(IbexBootAddrUnaligned, boot_addr_i[7:0] == 8'h00) + + // Address must not contain X when request is sent. + `ASSERT(IbexInstrAddrUnknown, instr_req_o |-> !$isunknown(instr_addr_o)) + + // Address must be word aligned when request is sent. + `ASSERT(IbexInstrAddrUnaligned, instr_req_o |-> (instr_addr_o[1:0] == 2'b00)) + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_load_store_unit.sv b/flow/designs/src/ibex_sv/ibex_load_store_unit.sv new file mode 100644 index 0000000000..4d89b25703 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_load_store_unit.sv @@ -0,0 +1,516 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + + +/** + * Load Store Unit + * + * Load Store Unit, used to eliminate multiple access during processor stalls, + * and to align bytes and halfwords. + */ + +`include "prim_assert.sv" + +module ibex_load_store_unit +( + input logic clk_i, + input logic rst_ni, + + // data interface + output logic data_req_o, + input logic data_gnt_i, + input logic data_rvalid_i, + input logic data_err_i, + input logic data_pmp_err_i, + + output logic [31:0] data_addr_o, + output logic data_we_o, + output logic [3:0] data_be_o, + output logic [31:0] data_wdata_o, + input logic [31:0] data_rdata_i, + + // signals to/from ID/EX stage + input logic lsu_we_i, // write enable -> from ID/EX + input logic [1:0] lsu_type_i, // data type: word, half word, byte -> from ID/EX + input logic [31:0] lsu_wdata_i, // data to write to memory -> from ID/EX + input logic lsu_sign_ext_i, // sign extension -> from ID/EX + + output logic [31:0] lsu_rdata_o, // requested data -> to ID/EX + output logic lsu_rdata_valid_o, + input logic lsu_req_i, // data request -> from ID/EX + + input logic [31:0] adder_result_ex_i, // address computed in ALU -> from ID/EX + + output logic addr_incr_req_o, // request address increment for + // misaligned accesses -> to ID/EX + output logic [31:0] addr_last_o, // address of last transaction -> to controller + // -> mtval + // -> AGU for misaligned accesses + + output logic lsu_req_done_o, // Signals that data request is complete + // (only need to await final data + // response) -> to ID/EX + + output logic lsu_resp_valid_o, // LSU has response from transaction -> to ID/EX + + // exception signals + output logic load_err_o, + output logic store_err_o, + + output logic busy_o, + + output logic perf_load_o, + output logic perf_store_o +); + + logic [31:0] data_addr; + logic [31:0] data_addr_w_aligned; + logic [31:0] addr_last_q; + + logic addr_update; + logic ctrl_update; + logic rdata_update; + logic [31:8] rdata_q; + logic [1:0] rdata_offset_q; + logic [1:0] data_type_q; + logic data_sign_ext_q; + logic data_we_q; + + logic [1:0] data_offset; // mux control for data to be written to memory + + logic [3:0] data_be; + logic [31:0] data_wdata; + + logic [31:0] data_rdata_ext; + + logic [31:0] rdata_w_ext; // word realignment for misaligned loads + logic [31:0] rdata_h_ext; // sign extension for half words + logic [31:0] rdata_b_ext; // sign extension for bytes + + logic split_misaligned_access; + logic handle_misaligned_q, handle_misaligned_d; // high after receiving grant for first + // part of a misaligned access + logic pmp_err_q, pmp_err_d; + logic lsu_err_q, lsu_err_d; + logic data_or_pmp_err; + + typedef enum logic [2:0] { + IDLE, WAIT_GNT_MIS, WAIT_RVALID_MIS, WAIT_GNT, + WAIT_RVALID_MIS_GNTS_DONE + } ls_fsm_e; + + ls_fsm_e ls_fsm_cs, ls_fsm_ns; + + assign data_addr = adder_result_ex_i; + assign data_offset = data_addr[1:0]; + + /////////////////// + // BE generation // + /////////////////// + + always_comb begin + unique case (lsu_type_i) // Data type 00 Word, 01 Half word, 11,10 byte + 2'b00: begin // Writing a word + if (!handle_misaligned_q) begin // first part of potentially misaligned transaction + unique case (data_offset) + 2'b00: data_be = 4'b1111; + 2'b01: data_be = 4'b1110; + 2'b10: data_be = 4'b1100; + 2'b11: data_be = 4'b1000; + default: data_be = 4'b1111; + endcase // case (data_offset) + end else begin // second part of misaligned transaction + unique case (data_offset) + 2'b00: data_be = 4'b0000; // this is not used, but included for completeness + 2'b01: data_be = 4'b0001; + 2'b10: data_be = 4'b0011; + 2'b11: data_be = 4'b0111; + default: data_be = 4'b1111; + endcase // case (data_offset) + end + end + + 2'b01: begin // Writing a half word + if (!handle_misaligned_q) begin // first part of potentially misaligned transaction + unique case (data_offset) + 2'b00: data_be = 4'b0011; + 2'b01: data_be = 4'b0110; + 2'b10: data_be = 4'b1100; + 2'b11: data_be = 4'b1000; + default: data_be = 4'b1111; + endcase // case (data_offset) + end else begin // second part of misaligned transaction + data_be = 4'b0001; + end + end + + 2'b10, + 2'b11: begin // Writing a byte + unique case (data_offset) + 2'b00: data_be = 4'b0001; + 2'b01: data_be = 4'b0010; + 2'b10: data_be = 4'b0100; + 2'b11: data_be = 4'b1000; + default: data_be = 4'b1111; + endcase // case (data_offset) + end + + default: data_be = 4'b1111; + endcase // case (lsu_type_i) + end + + ///////////////////// + // WData alignment // + ///////////////////// + + // prepare data to be written to the memory + // we handle misaligned accesses, half word and byte accesses here + always_comb begin + unique case (data_offset) + 2'b00: data_wdata = lsu_wdata_i[31:0]; + 2'b01: data_wdata = {lsu_wdata_i[23:0], lsu_wdata_i[31:24]}; + 2'b10: data_wdata = {lsu_wdata_i[15:0], lsu_wdata_i[31:16]}; + 2'b11: data_wdata = {lsu_wdata_i[ 7:0], lsu_wdata_i[31: 8]}; + default: data_wdata = lsu_wdata_i[31:0]; + endcase // case (data_offset) + end + + ///////////////////// + // RData alignment // + ///////////////////// + + // register for unaligned rdata + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rdata_q <= '0; + end else if (rdata_update) begin + rdata_q <= data_rdata_i[31:8]; + end + end + + // registers for transaction control + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rdata_offset_q <= 2'h0; + data_type_q <= 2'h0; + data_sign_ext_q <= 1'b0; + data_we_q <= 1'b0; + end else if (ctrl_update) begin + rdata_offset_q <= data_offset; + data_type_q <= lsu_type_i; + data_sign_ext_q <= lsu_sign_ext_i; + data_we_q <= lsu_we_i; + end + end + + // Store last address for mtval + AGU for misaligned transactions. + // Do not update in case of errors, mtval needs the (first) failing address + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + addr_last_q <= '0; + end else if (addr_update) begin + addr_last_q <= data_addr; + end + end + + // take care of misaligned words + always_comb begin + unique case (rdata_offset_q) + 2'b00: rdata_w_ext = data_rdata_i[31:0]; + 2'b01: rdata_w_ext = {data_rdata_i[ 7:0], rdata_q[31:8]}; + 2'b10: rdata_w_ext = {data_rdata_i[15:0], rdata_q[31:16]}; + 2'b11: rdata_w_ext = {data_rdata_i[23:0], rdata_q[31:24]}; + default: rdata_w_ext = data_rdata_i[31:0]; + endcase + end + + //////////////////// + // Sign extension // + //////////////////// + + // sign extension for half words + always_comb begin + unique case (rdata_offset_q) + 2'b00: begin + if (!data_sign_ext_q) begin + rdata_h_ext = {16'h0000, data_rdata_i[15:0]}; + end else begin + rdata_h_ext = {{16{data_rdata_i[15]}}, data_rdata_i[15:0]}; + end + end + + 2'b01: begin + if (!data_sign_ext_q) begin + rdata_h_ext = {16'h0000, data_rdata_i[23:8]}; + end else begin + rdata_h_ext = {{16{data_rdata_i[23]}}, data_rdata_i[23:8]}; + end + end + + 2'b10: begin + if (!data_sign_ext_q) begin + rdata_h_ext = {16'h0000, data_rdata_i[31:16]}; + end else begin + rdata_h_ext = {{16{data_rdata_i[31]}}, data_rdata_i[31:16]}; + end + end + + 2'b11: begin + if (!data_sign_ext_q) begin + rdata_h_ext = {16'h0000, data_rdata_i[7:0], rdata_q[31:24]}; + end else begin + rdata_h_ext = {{16{data_rdata_i[7]}}, data_rdata_i[7:0], rdata_q[31:24]}; + end + end + + default: rdata_h_ext = {16'h0000, data_rdata_i[15:0]}; + endcase // case (rdata_offset_q) + end + + // sign extension for bytes + always_comb begin + unique case (rdata_offset_q) + 2'b00: begin + if (!data_sign_ext_q) begin + rdata_b_ext = {24'h00_0000, data_rdata_i[7:0]}; + end else begin + rdata_b_ext = {{24{data_rdata_i[7]}}, data_rdata_i[7:0]}; + end + end + + 2'b01: begin + if (!data_sign_ext_q) begin + rdata_b_ext = {24'h00_0000, data_rdata_i[15:8]}; + end else begin + rdata_b_ext = {{24{data_rdata_i[15]}}, data_rdata_i[15:8]}; + end + end + + 2'b10: begin + if (!data_sign_ext_q) begin + rdata_b_ext = {24'h00_0000, data_rdata_i[23:16]}; + end else begin + rdata_b_ext = {{24{data_rdata_i[23]}}, data_rdata_i[23:16]}; + end + end + + 2'b11: begin + if (!data_sign_ext_q) begin + rdata_b_ext = {24'h00_0000, data_rdata_i[31:24]}; + end else begin + rdata_b_ext = {{24{data_rdata_i[31]}}, data_rdata_i[31:24]}; + end + end + + default: rdata_b_ext = {24'h00_0000, data_rdata_i[7:0]}; + endcase // case (rdata_offset_q) + end + + // select word, half word or byte sign extended version + always_comb begin + unique case (data_type_q) + 2'b00: data_rdata_ext = rdata_w_ext; + 2'b01: data_rdata_ext = rdata_h_ext; + 2'b10,2'b11: data_rdata_ext = rdata_b_ext; + default: data_rdata_ext = rdata_w_ext; + endcase // case (data_type_q) + end + + ///////////// + // LSU FSM // + ///////////// + + // check for misaligned accesses that need to be split into two word-aligned accesses + assign split_misaligned_access = + ((lsu_type_i == 2'b00) && (data_offset != 2'b00)) || // misaligned word access + ((lsu_type_i == 2'b01) && (data_offset == 2'b11)); // misaligned half-word access + + // FSM + always_comb begin + ls_fsm_ns = ls_fsm_cs; + + data_req_o = 1'b0; + addr_incr_req_o = 1'b0; + handle_misaligned_d = handle_misaligned_q; + pmp_err_d = pmp_err_q; + lsu_err_d = lsu_err_q; + + addr_update = 1'b0; + ctrl_update = 1'b0; + rdata_update = 1'b0; + + perf_load_o = 1'b0; + perf_store_o = 1'b0; + + unique case (ls_fsm_cs) + + IDLE: begin + pmp_err_d = 1'b0; + if (lsu_req_i) begin + data_req_o = 1'b1; + pmp_err_d = data_pmp_err_i; + lsu_err_d = 1'b0; + perf_load_o = ~lsu_we_i; + perf_store_o = lsu_we_i; + + if (data_gnt_i) begin + ctrl_update = 1'b1; + addr_update = 1'b1; + handle_misaligned_d = split_misaligned_access; + ls_fsm_ns = split_misaligned_access ? WAIT_RVALID_MIS : IDLE; + end else begin + ls_fsm_ns = split_misaligned_access ? WAIT_GNT_MIS : WAIT_GNT; + end + end + end + + WAIT_GNT_MIS: begin + data_req_o = 1'b1; + // data_pmp_err_i is valid during the address phase of a request. An error will block the + // external request and so a data_gnt_i might never be signalled. The registered version + // pmp_err_q is only updated for new address phases and so can be used in WAIT_GNT* and + // WAIT_RVALID* states + if (data_gnt_i || pmp_err_q) begin + addr_update = 1'b1; + ctrl_update = 1'b1; + handle_misaligned_d = 1'b1; + ls_fsm_ns = WAIT_RVALID_MIS; + end + end + + WAIT_RVALID_MIS: begin + // push out second request + data_req_o = 1'b1; + // tell ID/EX stage to update the address + addr_incr_req_o = 1'b1; + + // first part rvalid is received, or gets a PMP error + if (data_rvalid_i || pmp_err_q) begin + // Update the PMP error for the second part + pmp_err_d = data_pmp_err_i; + // Record the error status of the first part + lsu_err_d = data_err_i | pmp_err_q; + // Capture the first rdata for loads + rdata_update = ~data_we_q; + // If already granted, wait for second rvalid + ls_fsm_ns = data_gnt_i ? IDLE : WAIT_GNT; + // Update the address for the second part, if no error + addr_update = data_gnt_i & ~(data_err_i | pmp_err_q); + // clear handle_misaligned if second request is granted + handle_misaligned_d = ~data_gnt_i; + end else begin + // first part rvalid is NOT received + if (data_gnt_i) begin + // second grant is received + ls_fsm_ns = WAIT_RVALID_MIS_GNTS_DONE; + handle_misaligned_d = 1'b0; + end + end + end + + WAIT_GNT: begin + // tell ID/EX stage to update the address + addr_incr_req_o = handle_misaligned_q; + data_req_o = 1'b1; + if (data_gnt_i || pmp_err_q) begin + ctrl_update = 1'b1; + // Update the address, unless there was an error + addr_update = ~lsu_err_q; + ls_fsm_ns = IDLE; + handle_misaligned_d = 1'b0; + end + end + + WAIT_RVALID_MIS_GNTS_DONE: begin + // tell ID/EX stage to update the address (to make sure the + // second address can be captured correctly for mtval and PMP checking) + addr_incr_req_o = 1'b1; + // Wait for the first rvalid, second request is already granted + if (data_rvalid_i) begin + // Update the pmp error for the second part + pmp_err_d = data_pmp_err_i; + // The first part cannot see a PMP error in this state + lsu_err_d = data_err_i; + // Now we can update the address for the second part if no error + addr_update = ~data_err_i; + // Capture the first rdata for loads + rdata_update = ~data_we_q; + // Wait for second rvalid + ls_fsm_ns = IDLE; + end + end + + default: begin + ls_fsm_ns = IDLE; + end + endcase + end + + assign lsu_req_done_o = (lsu_req_i | (ls_fsm_cs != IDLE)) & (ls_fsm_ns == IDLE); + + // registers for FSM + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + ls_fsm_cs <= IDLE; + handle_misaligned_q <= '0; + pmp_err_q <= '0; + lsu_err_q <= '0; + end else begin + ls_fsm_cs <= ls_fsm_ns; + handle_misaligned_q <= handle_misaligned_d; + pmp_err_q <= pmp_err_d; + lsu_err_q <= lsu_err_d; + end + end + + ///////////// + // Outputs // + ///////////// + + assign data_or_pmp_err = lsu_err_q | data_err_i | pmp_err_q; + assign lsu_resp_valid_o = (data_rvalid_i | pmp_err_q) & (ls_fsm_cs == IDLE); + assign lsu_rdata_valid_o = (ls_fsm_cs == IDLE) & data_rvalid_i & ~data_or_pmp_err & ~data_we_q; + + // output to register file + assign lsu_rdata_o = data_rdata_ext; + + // output data address must be word aligned + assign data_addr_w_aligned = {data_addr[31:2], 2'b00}; + + // output to data interface + assign data_addr_o = data_addr_w_aligned; + assign data_wdata_o = data_wdata; + assign data_we_o = lsu_we_i; + assign data_be_o = data_be; + + // output to ID stage: mtval + AGU for misaligned transactions + assign addr_last_o = addr_last_q; + + // Signal a load or store error depending on the transaction type outstanding + assign load_err_o = data_or_pmp_err & ~data_we_q & lsu_resp_valid_o; + assign store_err_o = data_or_pmp_err & data_we_q & lsu_resp_valid_o; + + assign busy_o = (ls_fsm_cs != IDLE); + + //////////////// + // Assertions // + //////////////// + + // Selectors must be known/valid. + `ASSERT(IbexDataTypeKnown, (lsu_req_i | busy_o) |-> !$isunknown(lsu_type_i)) + `ASSERT(IbexDataOffsetKnown, (lsu_req_i | busy_o) |-> !$isunknown(data_offset)) + `ASSERT_KNOWN(IbexRDataOffsetQKnown, rdata_offset_q) + `ASSERT_KNOWN(IbexDataTypeQKnown, data_type_q) + `ASSERT(IbexLsuStateValid, ls_fsm_cs inside { + IDLE, WAIT_GNT_MIS, WAIT_RVALID_MIS, WAIT_GNT, + WAIT_RVALID_MIS_GNTS_DONE}) + + // Address must not contain X when request is sent. + `ASSERT(IbexDataAddrUnknown, data_req_o |-> !$isunknown(data_addr_o)) + + // Address must be word aligned when request is sent. + `ASSERT(IbexDataAddrUnaligned, data_req_o |-> (data_addr_o[1:0] == 2'b00)) + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_multdiv_fast.sv b/flow/designs/src/ibex_sv/ibex_multdiv_fast.sv new file mode 100644 index 0000000000..cf69f00541 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_multdiv_fast.sv @@ -0,0 +1,531 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`define OP_L 15:0 +`define OP_H 31:16 + +/** + * Fast Multiplier and Division + * + * 16x16 kernel multiplier and Long Division + */ + +`include "prim_assert.sv" + +module ibex_multdiv_fast #( + parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast + ) ( + input logic clk_i, + input logic rst_ni, + input logic mult_en_i, // dynamic enable signal, for FSM control + input logic div_en_i, // dynamic enable signal, for FSM control + input logic mult_sel_i, // static decoder output, for data muxes + input logic div_sel_i, // static decoder output, for data muxes + input ibex_pkg::md_op_e operator_i, + input logic [1:0] signed_mode_i, + input logic [31:0] op_a_i, + input logic [31:0] op_b_i, + input logic [33:0] alu_adder_ext_i, + input logic [31:0] alu_adder_i, + input logic equal_to_zero_i, + input logic data_ind_timing_i, + + output logic [32:0] alu_operand_a_o, + output logic [32:0] alu_operand_b_o, + + input logic [33:0] imd_val_q_i[2], + output logic [33:0] imd_val_d_o[2], + output logic [1:0] imd_val_we_o, + + input logic multdiv_ready_id_i, + + output logic [31:0] multdiv_result_o, + output logic valid_o +); + + import ibex_pkg::*; + + // Both multiplier variants + logic signed [34:0] mac_res_signed; + logic [34:0] mac_res_ext; + logic [33:0] accum; + logic sign_a, sign_b; + logic mult_valid; + logic signed_mult; + + // Results that become intermediate value depending on whether mul or div is being calculated + logic [33:0] mac_res_d, op_remainder_d; + // Raw output of MAC calculation + logic [33:0] mac_res; + + // Divider signals + logic div_sign_a, div_sign_b; + logic is_greater_equal; + logic div_change_sign, rem_change_sign; + logic [31:0] one_shift; + logic [31:0] op_denominator_q; + logic [31:0] op_numerator_q; + logic [31:0] op_quotient_q; + logic [31:0] op_denominator_d; + logic [31:0] op_numerator_d; + logic [31:0] op_quotient_d; + logic [31:0] next_remainder; + logic [32:0] next_quotient; + logic [31:0] res_adder_h; + logic div_valid; + logic [ 4:0] div_counter_q, div_counter_d; + logic multdiv_en; + logic mult_hold; + logic div_hold; + logic div_by_zero_d, div_by_zero_q; + + logic mult_en_internal; + logic div_en_internal; + + typedef enum logic [2:0] { + MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH + } md_fsm_e; + md_fsm_e md_state_q, md_state_d; + + logic unused_mult_sel_i; + assign unused_mult_sel_i = mult_sel_i; + + assign mult_en_internal = mult_en_i & ~mult_hold; + assign div_en_internal = div_en_i & ~div_hold; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + div_counter_q <= '0; + md_state_q <= MD_IDLE; + op_numerator_q <= '0; + op_quotient_q <= '0; + div_by_zero_q <= '0; + end else if (div_en_internal) begin + div_counter_q <= div_counter_d; + op_numerator_q <= op_numerator_d; + op_quotient_q <= op_quotient_d; + md_state_q <= md_state_d; + div_by_zero_q <= div_by_zero_d; + end + end + + `ASSERT_KNOWN(DivEnKnown, div_en_internal) + `ASSERT_KNOWN(MultEnKnown, mult_en_internal) + `ASSERT_KNOWN(MultDivEnKnown, multdiv_en) + + assign multdiv_en = mult_en_internal | div_en_internal; + + // Intermediate value register shared with ALU + assign imd_val_d_o[0] = div_sel_i ? op_remainder_d : mac_res_d; + assign imd_val_we_o[0] = multdiv_en; + + assign imd_val_d_o[1] = {2'b0, op_denominator_d}; + assign imd_val_we_o[1] = div_en_internal; + assign op_denominator_q = imd_val_q_i[1][31:0]; + logic [1:0] unused_imd_val; + assign unused_imd_val = imd_val_q_i[1][33:32]; + logic unused_mac_res_ext; + assign unused_mac_res_ext = mac_res_ext[34]; + + assign signed_mult = (signed_mode_i != 2'b00); + assign multdiv_result_o = div_sel_i ? imd_val_q_i[0][31:0] : mac_res_d[31:0]; + + // The single cycle multiplier uses three 17 bit multipliers to compute MUL instructions in a + // single cycle and MULH instructions in two cycles. + if (RV32M == RV32MSingleCycle) begin : gen_mult_single_cycle + + typedef enum logic { + MULL, MULH + } mult_fsm_e; + mult_fsm_e mult_state_q, mult_state_d; + + logic signed [33:0] mult1_res, mult2_res, mult3_res; + logic [33:0] mult1_res_uns; + logic [33:32] unused_mult1_res_uns; + logic [15:0] mult1_op_a, mult1_op_b; + logic [15:0] mult2_op_a, mult2_op_b; + logic [15:0] mult3_op_a, mult3_op_b; + logic mult1_sign_a, mult1_sign_b; + logic mult2_sign_a, mult2_sign_b; + logic mult3_sign_a, mult3_sign_b; + logic [33:0] summand1, summand2, summand3; + + assign mult1_res = $signed({mult1_sign_a, mult1_op_a}) * $signed({mult1_sign_b, mult1_op_b}); + assign mult2_res = $signed({mult2_sign_a, mult2_op_a}) * $signed({mult2_sign_b, mult2_op_b}); + assign mult3_res = $signed({mult3_sign_a, mult3_op_a}) * $signed({mult3_sign_b, mult3_op_b}); + + assign mac_res_signed = $signed(summand1) + $signed(summand2) + $signed(summand3); + + assign mult1_res_uns = $unsigned(mult1_res); + assign mac_res_ext = $unsigned(mac_res_signed); + assign mac_res = mac_res_ext[33:0]; + + assign sign_a = signed_mode_i[0] & op_a_i[31]; + assign sign_b = signed_mode_i[1] & op_b_i[31]; + + // The first two multipliers are only used in state 1 (MULL). We can assign them statically. + // al*bl + assign mult1_sign_a = 1'b0; + assign mult1_sign_b = 1'b0; + assign mult1_op_a = op_a_i[`OP_L]; + assign mult1_op_b = op_b_i[`OP_L]; + + // al*bh + assign mult2_sign_a = 1'b0; + assign mult2_sign_b = sign_b; + assign mult2_op_a = op_a_i[`OP_L]; + assign mult2_op_b = op_b_i[`OP_H]; + + // used in MULH + assign accum[17:0] = imd_val_q_i[0][33:16]; + assign accum[33:18] = {16{signed_mult & imd_val_q_i[0][33]}}; + + always_comb begin + // Default values == MULL + + // ah*bl + mult3_sign_a = sign_a; + mult3_sign_b = 1'b0; + mult3_op_a = op_a_i[`OP_H]; + mult3_op_b = op_b_i[`OP_L]; + + summand1 = {18'h0, mult1_res_uns[`OP_H]}; + summand2 = $unsigned(mult2_res); + summand3 = $unsigned(mult3_res); + + // mac_res = A*B[47:16], mult1_res = A*B[15:0] + mac_res_d = {2'b0, mac_res[`OP_L], mult1_res_uns[`OP_L]}; + mult_valid = mult_en_i; + mult_state_d = MULL; + + mult_hold = 1'b0; + + unique case (mult_state_q) + + MULL: begin + if (operator_i != MD_OP_MULL) begin + mac_res_d = mac_res; + mult_valid = 1'b0; + mult_state_d = MULH; + end else begin + mult_hold = ~multdiv_ready_id_i; + end + end + + MULH: begin + // ah*bh + mult3_sign_a = sign_a; + mult3_sign_b = sign_b; + mult3_op_a = op_a_i[`OP_H]; + mult3_op_b = op_b_i[`OP_H]; + mac_res_d = mac_res; + + summand1 = '0; + summand2 = accum; + summand3 = mult3_res; + + mult_state_d = MULL; + mult_valid = 1'b1; + + mult_hold = ~multdiv_ready_id_i; + end + + default: begin + mult_state_d = MULL; + end + + endcase // mult_state_q + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + mult_state_q <= MULL; + end else begin + if (mult_en_internal) begin + mult_state_q <= mult_state_d; + end + end + end + + assign unused_mult1_res_uns = mult1_res_uns[33:32]; + + // States must be knwon/valid. + `ASSERT_KNOWN(IbexMultStateKnown, mult_state_q) + + // The fast multiplier uses one 17 bit multiplier to compute MUL instructions in 3 cycles + // and MULH instructions in 4 cycles. + end else begin : gen_mult_fast + logic [15:0] mult_op_a; + logic [15:0] mult_op_b; + + typedef enum logic [1:0] { + ALBL, ALBH, AHBL, AHBH + } mult_fsm_e; + mult_fsm_e mult_state_q, mult_state_d; + + // The 2 MSBs of mac_res_ext (mac_res_ext[34:33]) are always equal since: + // 1. The 2 MSBs of the multiplicants are always equal, and + // 2. The 16 MSBs of the addend (accum[33:18]) are always equal. + // Thus, it is safe to ignore mac_res_ext[34]. + assign mac_res_signed = + $signed({sign_a, mult_op_a}) * $signed({sign_b, mult_op_b}) + $signed(accum); + assign mac_res_ext = $unsigned(mac_res_signed); + assign mac_res = mac_res_ext[33:0]; + + always_comb begin + mult_op_a = op_a_i[`OP_L]; + mult_op_b = op_b_i[`OP_L]; + sign_a = 1'b0; + sign_b = 1'b0; + accum = imd_val_q_i[0]; + mac_res_d = mac_res; + mult_state_d = mult_state_q; + mult_valid = 1'b0; + mult_hold = 1'b0; + + unique case (mult_state_q) + + ALBL: begin + // al*bl + mult_op_a = op_a_i[`OP_L]; + mult_op_b = op_b_i[`OP_L]; + sign_a = 1'b0; + sign_b = 1'b0; + accum = '0; + mac_res_d = mac_res; + mult_state_d = ALBH; + end + + ALBH: begin + // al*bh<<16 + mult_op_a = op_a_i[`OP_L]; + mult_op_b = op_b_i[`OP_H]; + sign_a = 1'b0; + sign_b = signed_mode_i[1] & op_b_i[31]; + // result of AL*BL (in imd_val_q_i[0]) always unsigned with no carry + accum = {18'b0, imd_val_q_i[0][31:16]}; + if (operator_i == MD_OP_MULL) begin + mac_res_d = {2'b0, mac_res[`OP_L], imd_val_q_i[0][`OP_L]}; + end else begin + // MD_OP_MULH + mac_res_d = mac_res; + end + mult_state_d = AHBL; + end + + AHBL: begin + // ah*bl<<16 + mult_op_a = op_a_i[`OP_H]; + mult_op_b = op_b_i[`OP_L]; + sign_a = signed_mode_i[0] & op_a_i[31]; + sign_b = 1'b0; + if (operator_i == MD_OP_MULL) begin + accum = {18'b0, imd_val_q_i[0][31:16]}; + mac_res_d = {2'b0, mac_res[15:0], imd_val_q_i[0][15:0]}; + mult_valid = 1'b1; + + // Note no state transition will occur if mult_hold is set + mult_state_d = ALBL; + mult_hold = ~multdiv_ready_id_i; + end else begin + accum = imd_val_q_i[0]; + mac_res_d = mac_res; + mult_state_d = AHBH; + end + end + + AHBH: begin + // only MD_OP_MULH here + // ah*bh + mult_op_a = op_a_i[`OP_H]; + mult_op_b = op_b_i[`OP_H]; + sign_a = signed_mode_i[0] & op_a_i[31]; + sign_b = signed_mode_i[1] & op_b_i[31]; + accum[17: 0] = imd_val_q_i[0][33:16]; + accum[33:18] = {16{signed_mult & imd_val_q_i[0][33]}}; + // result of AH*BL is not signed only if signed_mode_i == 2'b00 + mac_res_d = mac_res; + mult_valid = 1'b1; + + // Note no state transition will occur if mult_hold is set + mult_state_d = ALBL; + mult_hold = ~multdiv_ready_id_i; + end + default: begin + mult_state_d = ALBL; + end + endcase // mult_state_q + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + mult_state_q <= ALBL; + end else begin + if (mult_en_internal) begin + mult_state_q <= mult_state_d; + end + end + end + + // States must be knwon/valid. + `ASSERT_KNOWN(IbexMultStateKnown, mult_state_q) + + end // gen_mult_fast + + // Divider + assign res_adder_h = alu_adder_ext_i[32:1]; + logic [1:0] unused_alu_adder_ext; + assign unused_alu_adder_ext = {alu_adder_ext_i[33],alu_adder_ext_i[0]}; + + assign next_remainder = is_greater_equal ? res_adder_h[31:0] : imd_val_q_i[0][31:0]; + assign next_quotient = is_greater_equal ? {1'b0, op_quotient_q} | {1'b0, one_shift} : + {1'b0, op_quotient_q}; + + assign one_shift = {31'b0, 1'b1} << div_counter_q; + + // The adder in the ALU computes alu_operand_a_o + alu_operand_b_o which means + // Remainder - Divisor. If Remainder - Divisor >= 0, is_greater_equal is equal to 1, + // the next Remainder is Remainder - Divisor contained in res_adder_h and the + always_comb begin + if ((imd_val_q_i[0][31] ^ op_denominator_q[31]) == 1'b0) begin + is_greater_equal = (res_adder_h[31] == 1'b0); + end else begin + is_greater_equal = imd_val_q_i[0][31]; + end + end + + assign div_sign_a = op_a_i[31] & signed_mode_i[0]; + assign div_sign_b = op_b_i[31] & signed_mode_i[1]; + assign div_change_sign = (div_sign_a ^ div_sign_b) & ~div_by_zero_q; + assign rem_change_sign = div_sign_a; + + + always_comb begin + div_counter_d = div_counter_q - 5'h1; + op_remainder_d = imd_val_q_i[0]; + op_quotient_d = op_quotient_q; + md_state_d = md_state_q; + op_numerator_d = op_numerator_q; + op_denominator_d = op_denominator_q; + alu_operand_a_o = {32'h0 , 1'b1}; + alu_operand_b_o = {~op_b_i, 1'b1}; + div_valid = 1'b0; + div_hold = 1'b0; + div_by_zero_d = div_by_zero_q; + + unique case(md_state_q) + MD_IDLE: begin + if (operator_i == MD_OP_DIV) begin + // Check if the Denominator is 0 + // quotient for division by 0 is specified to be -1 + // Note with data-independent time option, the full divide operation will proceed as + // normal and will naturally return -1 + op_remainder_d = '1; + md_state_d = (!data_ind_timing_i && equal_to_zero_i) ? MD_FINISH : MD_ABS_A; + // Record that this is a div by zero to stop the sign change at the end of the + // division (in data_ind_timing mode). + div_by_zero_d = equal_to_zero_i; + end else begin + // Check if the Denominator is 0 + // remainder for division by 0 is specified to be the numerator (operand a) + // Note with data-independent time option, the full divide operation will proceed as + // normal and will naturally return operand a + op_remainder_d = {2'b0, op_a_i}; + md_state_d = (!data_ind_timing_i && equal_to_zero_i) ? MD_FINISH : MD_ABS_A; + end + // 0 - B = 0 iff B == 0 + alu_operand_a_o = {32'h0 , 1'b1}; + alu_operand_b_o = {~op_b_i, 1'b1}; + div_counter_d = 5'd31; + end + + MD_ABS_A: begin + // quotient + op_quotient_d = '0; + // A abs value + op_numerator_d = div_sign_a ? alu_adder_i : op_a_i; + md_state_d = MD_ABS_B; + div_counter_d = 5'd31; + // ABS(A) = 0 - A + alu_operand_a_o = {32'h0 , 1'b1}; + alu_operand_b_o = {~op_a_i, 1'b1}; + end + + MD_ABS_B: begin + // remainder + op_remainder_d = { 33'h0, op_numerator_q[31]}; + // B abs value + op_denominator_d = div_sign_b ? alu_adder_i : op_b_i; + md_state_d = MD_COMP; + div_counter_d = 5'd31; + // ABS(B) = 0 - B + alu_operand_a_o = {32'h0 , 1'b1}; + alu_operand_b_o = {~op_b_i, 1'b1}; + end + + MD_COMP: begin + op_remainder_d = {1'b0, next_remainder[31:0], op_numerator_q[div_counter_d]}; + op_quotient_d = next_quotient[31:0]; + md_state_d = (div_counter_q == 5'd1) ? MD_LAST : MD_COMP; + // Division + alu_operand_a_o = {imd_val_q_i[0][31:0], 1'b1}; // it contains the remainder + alu_operand_b_o = {~op_denominator_q[31:0], 1'b1}; // -denominator two's compliment + end + + MD_LAST: begin + if (operator_i == MD_OP_DIV) begin + // this time we save the quotient in op_remainder_d (i.e. imd_val_q_i[0]) since + // we do not need anymore the remainder + op_remainder_d = {1'b0, next_quotient}; + end else begin + // this time we do not save the quotient anymore since we need only the remainder + op_remainder_d = {2'b0, next_remainder[31:0]}; + end + // Division + alu_operand_a_o = {imd_val_q_i[0][31:0], 1'b1}; // it contains the remainder + alu_operand_b_o = {~op_denominator_q[31:0], 1'b1}; // -denominator two's compliment + + md_state_d = MD_CHANGE_SIGN; + end + + MD_CHANGE_SIGN: begin + md_state_d = MD_FINISH; + if (operator_i == MD_OP_DIV) begin + op_remainder_d = (div_change_sign) ? {2'h0, alu_adder_i} : imd_val_q_i[0]; + end else begin + op_remainder_d = (rem_change_sign) ? {2'h0, alu_adder_i} : imd_val_q_i[0]; + end + // ABS(Quotient) = 0 - Quotient (or Remainder) + alu_operand_a_o = {32'h0 , 1'b1}; + alu_operand_b_o = {~imd_val_q_i[0][31:0], 1'b1}; + end + + MD_FINISH: begin + // Hold result until ID stage is ready to accept it + // Note no state transition will occur if div_hold is set + md_state_d = MD_IDLE; + div_hold = ~multdiv_ready_id_i; + div_valid = 1'b1; + end + + default: begin + md_state_d = MD_IDLE; + end + endcase // md_state_q + end + + assign valid_o = mult_valid | div_valid; + + // States must be knwon/valid. + `ASSERT(IbexMultDivStateValid, md_state_q inside { + MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH}) + +`ifdef FORMAL + `ifdef YOSYS + `include "formal_tb_frag.svh" + `endif +`endif + +endmodule // ibex_mult diff --git a/flow/designs/src/ibex_sv/ibex_multdiv_slow.sv b/flow/designs/src/ibex_sv/ibex_multdiv_slow.sv new file mode 100644 index 0000000000..a8d60b4eae --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_multdiv_slow.sv @@ -0,0 +1,374 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Slow Multiplier and Division + * + * Baugh-Wooley multiplier and Long Division + */ + +`include "prim_assert.sv" + +module ibex_multdiv_slow +( + input logic clk_i, + input logic rst_ni, + input logic mult_en_i, // dynamic enable signal, for FSM control + input logic div_en_i, // dynamic enable signal, for FSM control + input logic mult_sel_i, // static decoder output, for data muxes + input logic div_sel_i, // static decoder output, for data muxes + input ibex_pkg::md_op_e operator_i, + input logic [1:0] signed_mode_i, + input logic [31:0] op_a_i, + input logic [31:0] op_b_i, + input logic [33:0] alu_adder_ext_i, + input logic [31:0] alu_adder_i, + input logic equal_to_zero_i, + input logic data_ind_timing_i, + + output logic [32:0] alu_operand_a_o, + output logic [32:0] alu_operand_b_o, + + input logic [33:0] imd_val_q_i[2], + output logic [33:0] imd_val_d_o[2], + output logic [1:0] imd_val_we_o, + + input logic multdiv_ready_id_i, + + output logic [31:0] multdiv_result_o, + + output logic valid_o +); + + import ibex_pkg::*; + + typedef enum logic [2:0] { + MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH + } md_fsm_e; + md_fsm_e md_state_q, md_state_d; + + logic [32:0] accum_window_q, accum_window_d; + logic unused_imd_val0; + logic [ 1:0] unused_imd_val1; + + logic [32:0] res_adder_l; + logic [32:0] res_adder_h; + + logic [ 4:0] multdiv_count_q, multdiv_count_d; + logic [32:0] op_b_shift_q, op_b_shift_d; + logic [32:0] op_a_shift_q, op_a_shift_d; + logic [32:0] op_a_ext, op_b_ext; + logic [32:0] one_shift; + logic [32:0] op_a_bw_pp, op_a_bw_last_pp; + logic [31:0] b_0; + logic sign_a, sign_b; + logic [32:0] next_quotient; + logic [31:0] next_remainder; + logic [31:0] op_numerator_q, op_numerator_d; + logic is_greater_equal; + logic div_change_sign, rem_change_sign; + logic div_by_zero_d, div_by_zero_q; + logic multdiv_hold; + logic multdiv_en; + + // (accum_window_q + op_a_shift_q) + assign res_adder_l = alu_adder_ext_i[32:0]; + // (accum_window_q + op_a_shift_q)>>1 + assign res_adder_h = alu_adder_ext_i[33:1]; + + ///////////////////// + // ALU Operand MUX // + ///////////////////// + + // Intermediate value register shared with ALU + assign imd_val_d_o[0] = {1'b0,accum_window_d}; + assign imd_val_we_o[0] = ~multdiv_hold; + assign accum_window_q = imd_val_q_i[0][32:0]; + assign unused_imd_val0 = imd_val_q_i[0][33]; + + assign imd_val_d_o[1] = {2'b00, op_numerator_d}; + assign imd_val_we_o[1] = multdiv_en; + assign op_numerator_q = imd_val_q_i[1][31:0]; + assign unused_imd_val1 = imd_val_q_i[1][33:32]; + + always_comb begin + alu_operand_a_o = accum_window_q; + + unique case(operator_i) + + MD_OP_MULL: begin + alu_operand_b_o = op_a_bw_pp; + end + + MD_OP_MULH: begin + alu_operand_b_o = (md_state_q == MD_LAST) ? op_a_bw_last_pp : op_a_bw_pp; + end + + MD_OP_DIV, + MD_OP_REM: begin + unique case(md_state_q) + MD_IDLE: begin + // 0 - B = 0 iff B == 0 + alu_operand_a_o = {32'h0 , 1'b1}; + alu_operand_b_o = {~op_b_i, 1'b1}; + end + MD_ABS_A: begin + // ABS(A) = 0 - A + alu_operand_a_o = {32'h0 , 1'b1}; + alu_operand_b_o = {~op_a_i, 1'b1}; + end + MD_ABS_B: begin + // ABS(B) = 0 - B + alu_operand_a_o = {32'h0 , 1'b1}; + alu_operand_b_o = {~op_b_i, 1'b1}; + end + MD_CHANGE_SIGN: begin + // ABS(Quotient) = 0 - Quotient (or Reminder) + alu_operand_a_o = {32'h0 , 1'b1}; + alu_operand_b_o = {~accum_window_q[31:0], 1'b1}; + end + default: begin + // Division + alu_operand_a_o = {accum_window_q[31:0], 1'b1}; // it contains the remainder + alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1}; // -denominator two's compliment + end + endcase + end + default: begin + alu_operand_a_o = accum_window_q; + alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1}; + end + endcase + end + + // Multiplier partial product calculation + assign b_0 = {32{op_b_shift_q[0]}}; + assign op_a_bw_pp = { ~(op_a_shift_q[32] & op_b_shift_q[0]), (op_a_shift_q[31:0] & b_0) }; + assign op_a_bw_last_pp = { (op_a_shift_q[32] & op_b_shift_q[0]), ~(op_a_shift_q[31:0] & b_0) }; + + // Sign extend the input operands + assign sign_a = op_a_i[31] & signed_mode_i[0]; + assign sign_b = op_b_i[31] & signed_mode_i[1]; + + assign op_a_ext = {sign_a, op_a_i}; + assign op_b_ext = {sign_b, op_b_i}; + + // Divider calculations + + // The adder in the ALU computes Remainder - Divisor. If Remainder - Divisor >= 0, + // is_greater_equal is true, the next Remainder is the subtraction result and the Quotient + // multdiv_count_q-th bit is set to 1. + assign is_greater_equal = (accum_window_q[31] == op_b_shift_q[31]) ? + ~res_adder_h[31] : accum_window_q[31]; + + assign one_shift = {32'b0, 1'b1} << multdiv_count_q; + + assign next_remainder = is_greater_equal ? res_adder_h[31:0] : accum_window_q[31:0]; + assign next_quotient = is_greater_equal ? op_a_shift_q | one_shift : op_a_shift_q; + + assign div_change_sign = (sign_a ^ sign_b) & ~div_by_zero_q; + assign rem_change_sign = sign_a; + + always_comb begin + multdiv_count_d = multdiv_count_q; + accum_window_d = accum_window_q; + op_b_shift_d = op_b_shift_q; + op_a_shift_d = op_a_shift_q; + op_numerator_d = op_numerator_q; + md_state_d = md_state_q; + multdiv_hold = 1'b0; + div_by_zero_d = div_by_zero_q; + if (mult_sel_i || div_sel_i) begin + unique case(md_state_q) + MD_IDLE: begin + unique case(operator_i) + MD_OP_MULL: begin + op_a_shift_d = op_a_ext << 1; + accum_window_d = { ~(op_a_ext[32] & op_b_i[0]), + op_a_ext[31:0] & {32{op_b_i[0]}} }; + op_b_shift_d = op_b_ext >> 1; + // Proceed with multiplication by 0/1 in data-independent time mode + md_state_d = (!data_ind_timing_i && ((op_b_ext >> 1) == 0)) ? MD_LAST : MD_COMP; + end + MD_OP_MULH: begin + op_a_shift_d = op_a_ext; + accum_window_d = { 1'b1, ~(op_a_ext[32] & op_b_i[0]), + op_a_ext[31:1] & {31{op_b_i[0]}} }; + op_b_shift_d = op_b_ext >> 1; + md_state_d = MD_COMP; + end + MD_OP_DIV: begin + // Check if the denominator is 0 + // quotient for division by 0 is specified to be -1 + // Note with data-independent time option, the full divide operation will proceed as + // normal and will naturally return -1 + accum_window_d = {33{1'b1}}; + md_state_d = (!data_ind_timing_i && equal_to_zero_i) ? MD_FINISH : MD_ABS_A; + // Record that this is a div by zero to stop the sign change at the end of the + // division (in data_ind_timing mode). + div_by_zero_d = equal_to_zero_i; + end + MD_OP_REM: begin + // Check if the denominator is 0 + // remainder for division by 0 is specified to be the numerator (operand a) + // Note with data-independent time option, the full divide operation will proceed as + // normal and will naturally return operand a + accum_window_d = op_a_ext; + md_state_d = (!data_ind_timing_i && equal_to_zero_i) ? MD_FINISH : MD_ABS_A; + end + default:; + endcase + multdiv_count_d = 5'd31; + end + + MD_ABS_A: begin + // quotient + op_a_shift_d = '0; + // A abs value + op_numerator_d = sign_a ? alu_adder_i : op_a_i; + md_state_d = MD_ABS_B; + end + + MD_ABS_B: begin + // remainder + accum_window_d = {32'h0,op_numerator_q[31]}; + // B abs value + op_b_shift_d = sign_b ? {1'b0,alu_adder_i} : {1'b0,op_b_i}; + md_state_d = MD_COMP; + end + + MD_COMP: begin + multdiv_count_d = multdiv_count_q - 5'h1; + unique case(operator_i) + MD_OP_MULL: begin + accum_window_d = res_adder_l; + op_a_shift_d = op_a_shift_q << 1; + op_b_shift_d = op_b_shift_q >> 1; + // Multiplication is complete once op_b is zero, unless in data_ind_timing mode where + // the maximum possible shift-add operations will be completed regardless of op_b + md_state_d = ((!data_ind_timing_i && (op_b_shift_d == 0)) || + (multdiv_count_q == 5'd1)) ? MD_LAST : MD_COMP; + end + MD_OP_MULH: begin + accum_window_d = res_adder_h; + op_a_shift_d = op_a_shift_q; + op_b_shift_d = op_b_shift_q >> 1; + md_state_d = (multdiv_count_q == 5'd1) ? MD_LAST : MD_COMP; + end + MD_OP_DIV, + MD_OP_REM: begin + accum_window_d = {next_remainder[31:0], op_numerator_q[multdiv_count_d]}; + op_a_shift_d = next_quotient; + md_state_d = (multdiv_count_q == 5'd1) ? MD_LAST : MD_COMP; + end + default: ; + endcase + end + + MD_LAST: begin + unique case(operator_i) + MD_OP_MULL: begin + accum_window_d = res_adder_l; + + // Note no state transition will occur if multdiv_hold is set + md_state_d = MD_IDLE; + multdiv_hold = ~multdiv_ready_id_i; + end + MD_OP_MULH: begin + accum_window_d = res_adder_l; + md_state_d = MD_IDLE; + + // Note no state transition will occur if multdiv_hold is set + md_state_d = MD_IDLE; + multdiv_hold = ~multdiv_ready_id_i; + end + MD_OP_DIV: begin + // this time we save the quotient in accum_window_q since we do not need anymore the + // remainder + accum_window_d = next_quotient; + md_state_d = MD_CHANGE_SIGN; + end + MD_OP_REM: begin + // this time we do not save the quotient anymore since we need only the remainder + accum_window_d = {1'b0, next_remainder[31:0]}; + md_state_d = MD_CHANGE_SIGN; + end + default: ; + endcase + end + + MD_CHANGE_SIGN: begin + md_state_d = MD_FINISH; + unique case(operator_i) + MD_OP_DIV: + accum_window_d = div_change_sign ? {1'b0,alu_adder_i} : accum_window_q; + MD_OP_REM: + accum_window_d = rem_change_sign ? {1'b0,alu_adder_i} : accum_window_q; + default: ; + endcase + end + + MD_FINISH: begin + // Note no state transition will occur if multdiv_hold is set + md_state_d = MD_IDLE; + multdiv_hold = ~multdiv_ready_id_i; + end + + default: begin + md_state_d = MD_IDLE; + end + endcase // md_state_q + end // (mult_sel_i || div_sel_i) + end + + ////////////////////////////////////////// + // Mutliplier / Divider state registers // + ////////////////////////////////////////// + + assign multdiv_en = (mult_en_i | div_en_i) & ~multdiv_hold; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + multdiv_count_q <= 5'h0; + op_b_shift_q <= 33'h0; + op_a_shift_q <= 33'h0; + md_state_q <= MD_IDLE; + div_by_zero_q <= 1'b0; + end else if (multdiv_en) begin + multdiv_count_q <= multdiv_count_d; + op_b_shift_q <= op_b_shift_d; + op_a_shift_q <= op_a_shift_d; + md_state_q <= md_state_d; + div_by_zero_q <= div_by_zero_d; + end + end + + ///////////// + // Outputs // + ///////////// + + assign valid_o = (md_state_q == MD_FINISH) | + (md_state_q == MD_LAST & + (operator_i == MD_OP_MULL | + operator_i == MD_OP_MULH)); + + assign multdiv_result_o = div_en_i ? accum_window_q[31:0] : res_adder_l[31:0]; + + //////////////// + // Assertions // + //////////////// + + // State must be valid. + `ASSERT(IbexMultDivStateValid, md_state_q inside { + MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH + }, clk_i, !rst_ni) + +`ifdef FORMAL + `ifdef YOSYS + `include "formal_tb_frag.svh" + `endif +`endif + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_pkg.sv b/flow/designs/src/ibex_sv/ibex_pkg.sv new file mode 100644 index 0000000000..42ac4863ca --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_pkg.sv @@ -0,0 +1,508 @@ +// Copyright lowRISC contributors. +// Copyright 2017 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Package with constants used by Ibex + */ +package ibex_pkg; + +///////////////////// +// Parameter Enums // +///////////////////// + +typedef enum integer { + RegFileFF = 0, + RegFileFPGA = 1, + RegFileLatch = 2 +} regfile_e; + +typedef enum integer { + RV32MNone = 0, + RV32MSlow = 1, + RV32MFast = 2, + RV32MSingleCycle = 3 +} rv32m_e; + +typedef enum integer { + RV32BNone = 0, + RV32BBalanced = 1, + RV32BFull = 2 +} rv32b_e; + +///////////// +// Opcodes // +///////////// + +typedef enum logic [6:0] { + OPCODE_LOAD = 7'h03, + OPCODE_MISC_MEM = 7'h0f, + OPCODE_OP_IMM = 7'h13, + OPCODE_AUIPC = 7'h17, + OPCODE_STORE = 7'h23, + OPCODE_OP = 7'h33, + OPCODE_LUI = 7'h37, + OPCODE_BRANCH = 7'h63, + OPCODE_JALR = 7'h67, + OPCODE_JAL = 7'h6f, + OPCODE_SYSTEM = 7'h73 +} opcode_e; + + +//////////////////// +// ALU operations // +//////////////////// + +typedef enum logic [5:0] { + // Arithmetics + ALU_ADD, + ALU_SUB, + + // Logics + ALU_XOR, + ALU_OR, + ALU_AND, + // RV32B + ALU_XNOR, + ALU_ORN, + ALU_ANDN, + + // Shifts + ALU_SRA, + ALU_SRL, + ALU_SLL, + // RV32B + ALU_SRO, + ALU_SLO, + ALU_ROR, + ALU_ROL, + ALU_GREV, + ALU_GORC, + ALU_SHFL, + ALU_UNSHFL, + + // Comparisons + ALU_LT, + ALU_LTU, + ALU_GE, + ALU_GEU, + ALU_EQ, + ALU_NE, + // RV32B + ALU_MIN, + ALU_MINU, + ALU_MAX, + ALU_MAXU, + + // Pack + // RV32B + ALU_PACK, + ALU_PACKU, + ALU_PACKH, + + // Sign-Extend + // RV32B + ALU_SEXTB, + ALU_SEXTH, + + // Bitcounting + // RV32B + ALU_CLZ, + ALU_CTZ, + ALU_PCNT, + + // Set lower than + ALU_SLT, + ALU_SLTU, + + // Ternary Bitmanip Operations + // RV32B + ALU_CMOV, + ALU_CMIX, + ALU_FSL, + ALU_FSR, + + // Single-Bit Operations + // RV32B + ALU_SBSET, + ALU_SBCLR, + ALU_SBINV, + ALU_SBEXT, + + // Bit Extract / Deposit + // RV32B + ALU_BEXT, + ALU_BDEP, + + // Bit Field Place + // RV32B + ALU_BFP, + + // Carry-less Multiply + // RV32B + ALU_CLMUL, + ALU_CLMULR, + ALU_CLMULH, + + // Cyclic Redundancy Check + ALU_CRC32_B, + ALU_CRC32C_B, + ALU_CRC32_H, + ALU_CRC32C_H, + ALU_CRC32_W, + ALU_CRC32C_W +} alu_op_e; + +typedef enum logic [1:0] { + // Multiplier/divider + MD_OP_MULL, + MD_OP_MULH, + MD_OP_DIV, + MD_OP_REM +} md_op_e; + + +////////////////////////////////// +// Control and status registers // +////////////////////////////////// + +// CSR operations +typedef enum logic [1:0] { + CSR_OP_READ, + CSR_OP_WRITE, + CSR_OP_SET, + CSR_OP_CLEAR +} csr_op_e; + +// Privileged mode +typedef enum logic[1:0] { + PRIV_LVL_M = 2'b11, + PRIV_LVL_H = 2'b10, + PRIV_LVL_S = 2'b01, + PRIV_LVL_U = 2'b00 +} priv_lvl_e; + +// Constants for the dcsr.xdebugver fields +typedef enum logic[3:0] { + XDEBUGVER_NO = 4'd0, // no external debug support + XDEBUGVER_STD = 4'd4, // external debug according to RISC-V debug spec + XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec +} x_debug_ver_e; + +////////////// +// WB stage // +////////////// + +// Type of instruction present in writeback stage +typedef enum logic[1:0] { + WB_INSTR_LOAD, // Instruction is awaiting load data + WB_INSTR_STORE, // Instruction is awaiting store response + WB_INSTR_OTHER // Instruction doesn't fit into above categories +} wb_instr_type_e; + +////////////// +// ID stage // +////////////// + +// Operand a selection +typedef enum logic[1:0] { + OP_A_REG_A, + OP_A_FWD, + OP_A_CURRPC, + OP_A_IMM +} op_a_sel_e; + +// Immediate a selection +typedef enum logic { + IMM_A_Z, + IMM_A_ZERO +} imm_a_sel_e; + +// Operand b selection +typedef enum logic { + OP_B_REG_B, + OP_B_IMM +} op_b_sel_e; + +// Immediate b selection +typedef enum logic [2:0] { + IMM_B_I, + IMM_B_S, + IMM_B_B, + IMM_B_U, + IMM_B_J, + IMM_B_INCR_PC, + IMM_B_INCR_ADDR +} imm_b_sel_e; + +// Regfile write data selection +typedef enum logic { + RF_WD_EX, + RF_WD_CSR +} rf_wd_sel_e; + +////////////// +// IF stage // +////////////// + +// PC mux selection +typedef enum logic [2:0] { + PC_BOOT, + PC_JUMP, + PC_EXC, + PC_ERET, + PC_DRET, + PC_BP +} pc_sel_e; + +// Exception PC mux selection +typedef enum logic [1:0] { + EXC_PC_EXC, + EXC_PC_IRQ, + EXC_PC_DBD, + EXC_PC_DBG_EXC // Exception while in debug mode +} exc_pc_sel_e; + +// Interrupt requests +typedef struct packed { + logic irq_software; + logic irq_timer; + logic irq_external; + logic [14:0] irq_fast; // 15 fast interrupts, + // one interrupt is reserved for NMI (not visible through mip/mie) +} irqs_t; + +// Exception cause +typedef enum logic [5:0] { + EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd03}, + EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd07}, + EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}, + // EXC_CAUSE_IRQ_FAST_0 = {1'b1, 5'd16}, + // EXC_CAUSE_IRQ_FAST_14 = {1'b1, 5'd30}, + EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}, // == EXC_CAUSE_IRQ_FAST_15 + EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd00}, + EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd01}, + EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd02}, + EXC_CAUSE_BREAKPOINT = {1'b0, 5'd03}, + EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd05}, + EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd07}, + EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd08}, + EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11} +} exc_cause_e; + +// Debug cause +typedef enum logic [2:0] { + DBG_CAUSE_NONE = 3'h0, + DBG_CAUSE_EBREAK = 3'h1, + DBG_CAUSE_TRIGGER = 3'h2, + DBG_CAUSE_HALTREQ = 3'h3, + DBG_CAUSE_STEP = 3'h4 +} dbg_cause_e; + +// PMP constants +parameter int unsigned PMP_MAX_REGIONS = 16; +parameter int unsigned PMP_CFG_W = 8; + +// PMP acces type +parameter int unsigned PMP_I = 0; +parameter int unsigned PMP_D = 1; + +typedef enum logic [1:0] { + PMP_ACC_EXEC = 2'b00, + PMP_ACC_WRITE = 2'b01, + PMP_ACC_READ = 2'b10 +} pmp_req_e; + +// PMP cfg structures +typedef enum logic [1:0] { + PMP_MODE_OFF = 2'b00, + PMP_MODE_TOR = 2'b01, + PMP_MODE_NA4 = 2'b10, + PMP_MODE_NAPOT = 2'b11 +} pmp_cfg_mode_e; + +typedef struct packed { + logic lock; + pmp_cfg_mode_e mode; + logic exec; + logic write; + logic read; +} pmp_cfg_t; + +// CSRs +typedef enum logic[11:0] { + // Machine information + CSR_MHARTID = 12'hF14, + + // Machine trap setup + CSR_MSTATUS = 12'h300, + CSR_MISA = 12'h301, + CSR_MIE = 12'h304, + CSR_MTVEC = 12'h305, + + // Machine trap handling + CSR_MSCRATCH = 12'h340, + CSR_MEPC = 12'h341, + CSR_MCAUSE = 12'h342, + CSR_MTVAL = 12'h343, + CSR_MIP = 12'h344, + + // Physical memory protection + CSR_PMPCFG0 = 12'h3A0, + CSR_PMPCFG1 = 12'h3A1, + CSR_PMPCFG2 = 12'h3A2, + CSR_PMPCFG3 = 12'h3A3, + CSR_PMPADDR0 = 12'h3B0, + CSR_PMPADDR1 = 12'h3B1, + CSR_PMPADDR2 = 12'h3B2, + CSR_PMPADDR3 = 12'h3B3, + CSR_PMPADDR4 = 12'h3B4, + CSR_PMPADDR5 = 12'h3B5, + CSR_PMPADDR6 = 12'h3B6, + CSR_PMPADDR7 = 12'h3B7, + CSR_PMPADDR8 = 12'h3B8, + CSR_PMPADDR9 = 12'h3B9, + CSR_PMPADDR10 = 12'h3BA, + CSR_PMPADDR11 = 12'h3BB, + CSR_PMPADDR12 = 12'h3BC, + CSR_PMPADDR13 = 12'h3BD, + CSR_PMPADDR14 = 12'h3BE, + CSR_PMPADDR15 = 12'h3BF, + + // Debug trigger + CSR_TSELECT = 12'h7A0, + CSR_TDATA1 = 12'h7A1, + CSR_TDATA2 = 12'h7A2, + CSR_TDATA3 = 12'h7A3, + CSR_MCONTEXT = 12'h7A8, + CSR_SCONTEXT = 12'h7AA, + + // Debug/trace + CSR_DCSR = 12'h7b0, + CSR_DPC = 12'h7b1, + + // Debug + CSR_DSCRATCH0 = 12'h7b2, // optional + CSR_DSCRATCH1 = 12'h7b3, // optional + + // Machine Counter/Timers + CSR_MCOUNTINHIBIT = 12'h320, + CSR_MHPMEVENT3 = 12'h323, + CSR_MHPMEVENT4 = 12'h324, + CSR_MHPMEVENT5 = 12'h325, + CSR_MHPMEVENT6 = 12'h326, + CSR_MHPMEVENT7 = 12'h327, + CSR_MHPMEVENT8 = 12'h328, + CSR_MHPMEVENT9 = 12'h329, + CSR_MHPMEVENT10 = 12'h32A, + CSR_MHPMEVENT11 = 12'h32B, + CSR_MHPMEVENT12 = 12'h32C, + CSR_MHPMEVENT13 = 12'h32D, + CSR_MHPMEVENT14 = 12'h32E, + CSR_MHPMEVENT15 = 12'h32F, + CSR_MHPMEVENT16 = 12'h330, + CSR_MHPMEVENT17 = 12'h331, + CSR_MHPMEVENT18 = 12'h332, + CSR_MHPMEVENT19 = 12'h333, + CSR_MHPMEVENT20 = 12'h334, + CSR_MHPMEVENT21 = 12'h335, + CSR_MHPMEVENT22 = 12'h336, + CSR_MHPMEVENT23 = 12'h337, + CSR_MHPMEVENT24 = 12'h338, + CSR_MHPMEVENT25 = 12'h339, + CSR_MHPMEVENT26 = 12'h33A, + CSR_MHPMEVENT27 = 12'h33B, + CSR_MHPMEVENT28 = 12'h33C, + CSR_MHPMEVENT29 = 12'h33D, + CSR_MHPMEVENT30 = 12'h33E, + CSR_MHPMEVENT31 = 12'h33F, + CSR_MCYCLE = 12'hB00, + CSR_MINSTRET = 12'hB02, + CSR_MHPMCOUNTER3 = 12'hB03, + CSR_MHPMCOUNTER4 = 12'hB04, + CSR_MHPMCOUNTER5 = 12'hB05, + CSR_MHPMCOUNTER6 = 12'hB06, + CSR_MHPMCOUNTER7 = 12'hB07, + CSR_MHPMCOUNTER8 = 12'hB08, + CSR_MHPMCOUNTER9 = 12'hB09, + CSR_MHPMCOUNTER10 = 12'hB0A, + CSR_MHPMCOUNTER11 = 12'hB0B, + CSR_MHPMCOUNTER12 = 12'hB0C, + CSR_MHPMCOUNTER13 = 12'hB0D, + CSR_MHPMCOUNTER14 = 12'hB0E, + CSR_MHPMCOUNTER15 = 12'hB0F, + CSR_MHPMCOUNTER16 = 12'hB10, + CSR_MHPMCOUNTER17 = 12'hB11, + CSR_MHPMCOUNTER18 = 12'hB12, + CSR_MHPMCOUNTER19 = 12'hB13, + CSR_MHPMCOUNTER20 = 12'hB14, + CSR_MHPMCOUNTER21 = 12'hB15, + CSR_MHPMCOUNTER22 = 12'hB16, + CSR_MHPMCOUNTER23 = 12'hB17, + CSR_MHPMCOUNTER24 = 12'hB18, + CSR_MHPMCOUNTER25 = 12'hB19, + CSR_MHPMCOUNTER26 = 12'hB1A, + CSR_MHPMCOUNTER27 = 12'hB1B, + CSR_MHPMCOUNTER28 = 12'hB1C, + CSR_MHPMCOUNTER29 = 12'hB1D, + CSR_MHPMCOUNTER30 = 12'hB1E, + CSR_MHPMCOUNTER31 = 12'hB1F, + CSR_MCYCLEH = 12'hB80, + CSR_MINSTRETH = 12'hB82, + CSR_MHPMCOUNTER3H = 12'hB83, + CSR_MHPMCOUNTER4H = 12'hB84, + CSR_MHPMCOUNTER5H = 12'hB85, + CSR_MHPMCOUNTER6H = 12'hB86, + CSR_MHPMCOUNTER7H = 12'hB87, + CSR_MHPMCOUNTER8H = 12'hB88, + CSR_MHPMCOUNTER9H = 12'hB89, + CSR_MHPMCOUNTER10H = 12'hB8A, + CSR_MHPMCOUNTER11H = 12'hB8B, + CSR_MHPMCOUNTER12H = 12'hB8C, + CSR_MHPMCOUNTER13H = 12'hB8D, + CSR_MHPMCOUNTER14H = 12'hB8E, + CSR_MHPMCOUNTER15H = 12'hB8F, + CSR_MHPMCOUNTER16H = 12'hB90, + CSR_MHPMCOUNTER17H = 12'hB91, + CSR_MHPMCOUNTER18H = 12'hB92, + CSR_MHPMCOUNTER19H = 12'hB93, + CSR_MHPMCOUNTER20H = 12'hB94, + CSR_MHPMCOUNTER21H = 12'hB95, + CSR_MHPMCOUNTER22H = 12'hB96, + CSR_MHPMCOUNTER23H = 12'hB97, + CSR_MHPMCOUNTER24H = 12'hB98, + CSR_MHPMCOUNTER25H = 12'hB99, + CSR_MHPMCOUNTER26H = 12'hB9A, + CSR_MHPMCOUNTER27H = 12'hB9B, + CSR_MHPMCOUNTER28H = 12'hB9C, + CSR_MHPMCOUNTER29H = 12'hB9D, + CSR_MHPMCOUNTER30H = 12'hB9E, + CSR_MHPMCOUNTER31H = 12'hB9F, + CSR_CPUCTRL = 12'h7C0, + CSR_SECURESEED = 12'h7C1 +} csr_num_e; + +// CSR pmp-related offsets +parameter logic [11:0] CSR_OFF_PMP_CFG = 12'h3A0; // pmp_cfg @ 12'h3a0 - 12'h3a3 +parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf + +// CSR status bits +parameter int unsigned CSR_MSTATUS_MIE_BIT = 3; +parameter int unsigned CSR_MSTATUS_MPIE_BIT = 7; +parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW = 11; +parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12; +parameter int unsigned CSR_MSTATUS_MPRV_BIT = 17; +parameter int unsigned CSR_MSTATUS_TW_BIT = 21; + +// CSR machine ISA +parameter logic [1:0] CSR_MISA_MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32 + +// CSR interrupt pending/enable bits +parameter int unsigned CSR_MSIX_BIT = 3; +parameter int unsigned CSR_MTIX_BIT = 7; +parameter int unsigned CSR_MEIX_BIT = 11; +parameter int unsigned CSR_MFIX_BIT_LOW = 16; +parameter int unsigned CSR_MFIX_BIT_HIGH = 30; + +endpackage diff --git a/flow/designs/src/ibex_sv/ibex_pmp.sv b/flow/designs/src/ibex_sv/ibex_pmp.sv new file mode 100644 index 0000000000..cbe2193310 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_pmp.sv @@ -0,0 +1,128 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module ibex_pmp #( + // Granularity of NAPOT access, + // 0 = No restriction, 1 = 8 byte, 2 = 16 byte, 3 = 32 byte, etc. + parameter int unsigned PMPGranularity = 0, + // Number of access channels (e.g. i-side + d-side) + parameter int unsigned PMPNumChan = 2, + // Number of implemented regions + parameter int unsigned PMPNumRegions = 4 +) ( + // Clock and Reset + input logic clk_i, + input logic rst_ni, + + // Interface to CSRs + input ibex_pkg::pmp_cfg_t csr_pmp_cfg_i [PMPNumRegions], + input logic [33:0] csr_pmp_addr_i [PMPNumRegions], + + input ibex_pkg::priv_lvl_e priv_mode_i [PMPNumChan], + // Access checking channels + input logic [33:0] pmp_req_addr_i [PMPNumChan], + input ibex_pkg::pmp_req_e pmp_req_type_i [PMPNumChan], + output logic pmp_req_err_o [PMPNumChan] + +); + + import ibex_pkg::*; + + // Access Checking Signals + logic [33:0] region_start_addr [PMPNumRegions]; + logic [33:PMPGranularity+2] region_addr_mask [PMPNumRegions]; + logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_gt; + logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_lt; + logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_eq; + logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_all; + logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_perm_check; + logic [PMPNumChan-1:0] access_fault; + + + // --------------- + // Access checking + // --------------- + + for (genvar r = 0; r < PMPNumRegions; r++) begin : g_addr_exp + // Start address for TOR matching + if (r == 0) begin : g_entry0 + assign region_start_addr[r] = (csr_pmp_cfg_i[r].mode == PMP_MODE_TOR) ? 34'h000000000 : + csr_pmp_addr_i[r]; + end else begin : g_oth + assign region_start_addr[r] = (csr_pmp_cfg_i[r].mode == PMP_MODE_TOR) ? csr_pmp_addr_i[r-1] : + csr_pmp_addr_i[r]; + end + // Address mask for NA matching + for (genvar b = PMPGranularity+2; b < 34; b++) begin : g_bitmask + if (b == 2) begin : g_bit0 + // Always mask bit 2 for NAPOT + assign region_addr_mask[r][b] = (csr_pmp_cfg_i[r].mode != PMP_MODE_NAPOT); + end else begin : g_others + // We will mask this bit if it is within the programmed granule + // i.e. addr = yyyy 0111 + // ^ + // | This bit pos is the top of the mask, all lower bits set + // thus mask = 1111 0000 + assign region_addr_mask[r][b] = (csr_pmp_cfg_i[r].mode != PMP_MODE_NAPOT) | + ~&csr_pmp_addr_i[r][b-1:PMPGranularity+1]; + end + end + end + + for (genvar c = 0; c < PMPNumChan; c++) begin : g_access_check + for (genvar r = 0; r < PMPNumRegions; r++) begin : g_regions + // Comparators are sized according to granularity + assign region_match_eq[c][r] = (pmp_req_addr_i[c][33:PMPGranularity+2] & + region_addr_mask[r]) == + (region_start_addr[r][33:PMPGranularity+2] & + region_addr_mask[r]); + assign region_match_gt[c][r] = pmp_req_addr_i[c][33:PMPGranularity+2] > + region_start_addr[r][33:PMPGranularity+2]; + assign region_match_lt[c][r] = pmp_req_addr_i[c][33:PMPGranularity+2] < + csr_pmp_addr_i[r][33:PMPGranularity+2]; + + always_comb begin + region_match_all[c][r] = 1'b0; + unique case (csr_pmp_cfg_i[r].mode) + PMP_MODE_OFF : region_match_all[c][r] = 1'b0; + PMP_MODE_NA4 : region_match_all[c][r] = region_match_eq[c][r]; + PMP_MODE_NAPOT : region_match_all[c][r] = region_match_eq[c][r]; + PMP_MODE_TOR : begin + region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) & + region_match_lt[c][r]; + end + default : region_match_all[c][r] = 1'b0; + endcase + end + + // Check specific required permissions + assign region_perm_check[c][r] = + ((pmp_req_type_i[c] == PMP_ACC_EXEC) & csr_pmp_cfg_i[r].exec) | + ((pmp_req_type_i[c] == PMP_ACC_WRITE) & csr_pmp_cfg_i[r].write) | + ((pmp_req_type_i[c] == PMP_ACC_READ) & csr_pmp_cfg_i[r].read); + end + + // Access fault determination / prioritization + always_comb begin + // Default is allow for M-mode, deny for other modes + access_fault[c] = (priv_mode_i[c] != PRIV_LVL_M); + + // PMP entries are statically prioritized, from 0 to N-1 + // The lowest-numbered PMP entry which matches an address determines accessability + for (int r = PMPNumRegions-1; r >= 0; r--) begin + if (region_match_all[c][r]) begin + access_fault[c] = (priv_mode_i[c] == PRIV_LVL_M) ? + // For M-mode, any region which matches with the L-bit clear, or with sufficient + // access permissions will be allowed + (csr_pmp_cfg_i[r].lock & ~region_perm_check[c][r]) : + // For other modes, the lock bit doesn't matter + ~region_perm_check[c][r]; + end + end + end + + assign pmp_req_err_o[c] = access_fault[c]; + end + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_prefetch_buffer.sv b/flow/designs/src/ibex_sv/ibex_prefetch_buffer.sv new file mode 100644 index 0000000000..f206b2ad6a --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_prefetch_buffer.sv @@ -0,0 +1,320 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Prefetcher Buffer for 32 bit memory interface + * + * Prefetch Buffer that caches instructions. This cuts overly long critical + * paths to the instruction cache. + */ +module ibex_prefetch_buffer #( + parameter bit BranchPredictor = 1'b0 +) ( + input logic clk_i, + input logic rst_ni, + + input logic req_i, + + input logic branch_i, + input logic branch_spec_i, + input logic predicted_branch_i, + input logic branch_mispredict_i, + input logic [31:0] addr_i, + + + input logic ready_i, + output logic valid_o, + output logic [31:0] rdata_o, + output logic [31:0] addr_o, + output logic err_o, + output logic err_plus2_o, + + + // goes to instruction memory / instruction cache + output logic instr_req_o, + input logic instr_gnt_i, + output logic [31:0] instr_addr_o, + input logic [31:0] instr_rdata_i, + input logic instr_err_i, + input logic instr_pmp_err_i, + input logic instr_rvalid_i, + + // Prefetch Buffer Status + output logic busy_o +); + + localparam int unsigned NUM_REQS = 2; + + logic branch_suppress; + logic valid_new_req, valid_req; + logic valid_req_d, valid_req_q; + logic discard_req_d, discard_req_q; + logic gnt_or_pmp_err, rvalid_or_pmp_err; + logic [NUM_REQS-1:0] rdata_outstanding_n, rdata_outstanding_s, rdata_outstanding_q; + logic [NUM_REQS-1:0] branch_discard_n, branch_discard_s, branch_discard_q; + logic [NUM_REQS-1:0] rdata_pmp_err_n, rdata_pmp_err_s, rdata_pmp_err_q; + logic [NUM_REQS-1:0] rdata_outstanding_rev; + + logic [31:0] stored_addr_d, stored_addr_q; + logic stored_addr_en; + logic [31:0] fetch_addr_d, fetch_addr_q; + logic fetch_addr_en; + logic [31:0] branch_mispredict_addr; + logic [31:0] instr_addr, instr_addr_w_aligned; + logic instr_or_pmp_err; + + logic fifo_valid; + logic [31:0] fifo_addr; + logic fifo_ready; + logic fifo_clear; + logic [NUM_REQS-1:0] fifo_busy; + + logic valid_raw; + + logic [31:0] addr_next; + + logic branch_or_mispredict; + + //////////////////////////// + // Prefetch buffer status // + //////////////////////////// + + assign busy_o = (|rdata_outstanding_q) | instr_req_o; + + assign branch_or_mispredict = branch_i | branch_mispredict_i; + + ////////////////////////////////////////////// + // Fetch fifo - consumes addresses and data // + ////////////////////////////////////////////// + + // Instruction fetch errors are valid on the data phase of a request + // PMP errors are generated in the address phase, and registered into a fake data phase + assign instr_or_pmp_err = instr_err_i | rdata_pmp_err_q[0]; + + // A branch will invalidate any previously fetched instructions. + // Note that the FENCE.I instruction relies on this flushing behaviour on branch. If it is + // altered the FENCE.I implementation may require changes. + assign fifo_clear = branch_or_mispredict; + + // Reversed version of rdata_outstanding_q which can be overlaid with fifo fill state + for (genvar i = 0; i < NUM_REQS; i++) begin : gen_rd_rev + assign rdata_outstanding_rev[i] = rdata_outstanding_q[NUM_REQS-1-i]; + end + + // The fifo is ready to accept a new request if it is not full - including space reserved for + // requests already outstanding. + // Overlay the fifo fill state with the outstanding requests to see if there is space. + assign fifo_ready = ~&(fifo_busy | rdata_outstanding_rev); + + ibex_fetch_fifo #( + .NUM_REQS (NUM_REQS) + ) fifo_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .clear_i ( fifo_clear ), + .busy_o ( fifo_busy ), + + .in_valid_i ( fifo_valid ), + .in_addr_i ( fifo_addr ), + .in_rdata_i ( instr_rdata_i ), + .in_err_i ( instr_or_pmp_err ), + + .out_valid_o ( valid_raw ), + .out_ready_i ( ready_i ), + .out_rdata_o ( rdata_o ), + .out_addr_o ( addr_o ), + .out_addr_next_o ( addr_next ), + .out_err_o ( err_o ), + .out_err_plus2_o ( err_plus2_o ) + ); + + ////////////// + // Requests // + ////////////// + + // Suppress a new request on a not-taken branch (as the external address will be incorrect) + assign branch_suppress = branch_spec_i & ~branch_i; + + // Make a new request any time there is space in the FIFO, and space in the request queue + assign valid_new_req = ~branch_suppress & req_i & (fifo_ready | branch_or_mispredict) & + ~rdata_outstanding_q[NUM_REQS-1]; + + assign valid_req = valid_req_q | valid_new_req; + + // If a request address triggers a PMP error, the external bus request is suppressed. We might + // therefore never receive a grant for such a request. The grant is faked in this case to make + // sure the request proceeds and the error is pushed to the FIFO. + assign gnt_or_pmp_err = instr_gnt_i | instr_pmp_err_i; + + // As with the grant, the rvalid must be faked for a PMP error, since the request was suppressed. + assign rvalid_or_pmp_err = rdata_outstanding_q[0] & (instr_rvalid_i | rdata_pmp_err_q[0]); + + // Hold the request stable for requests that didn't get granted + assign valid_req_d = valid_req & ~gnt_or_pmp_err; + + // Record whether an outstanding bus request is cancelled by a branch + assign discard_req_d = valid_req_q & (branch_or_mispredict | discard_req_q); + + //////////////// + // Fetch addr // + //////////////// + + // Two addresses are tracked in the prefetch buffer: + // 1. stored_addr_q - This is the address issued on the bus. It stays stable until + // the request is granted. + // 2. fetch_addr_q - This is our next address to fetch from. It is updated on branches to + // capture the new address, and then for each new request issued. + // A third address is tracked in the fetch FIFO itself: + // 3. instr_addr_q - This is the address at the head of the FIFO, efectively our oldest fetched + // address. This address is updated on branches, and does its own increment + // each time the FIFO is popped. + + // 1. stored_addr_q + + // Only update stored_addr_q for new ungranted requests + assign stored_addr_en = valid_new_req & ~valid_req_q & ~gnt_or_pmp_err; + + // Store whatever address was issued on the bus + assign stored_addr_d = instr_addr; + + // CPU resets with a branch, so no need to reset these addresses + always_ff @(posedge clk_i) begin + if (stored_addr_en) begin + stored_addr_q <= stored_addr_d; + end + end + + if (BranchPredictor) begin : g_branch_predictor + // Where the branch predictor is present record what address followed a predicted branch. If + // that branch is predicted taken but mispredicted (so not-taken) this is used to resume on + // the not-taken code path. + logic [31:0] branch_mispredict_addr_q; + logic branch_mispredict_addr_en; + + assign branch_mispredict_addr_en = branch_i & predicted_branch_i; + + always_ff @(posedge clk_i) begin + if (branch_mispredict_addr_en) begin + branch_mispredict_addr_q <= addr_next; + end + end + + assign branch_mispredict_addr = branch_mispredict_addr_q; + end else begin : g_no_branch_predictor + logic unused_predicted_branch; + logic [31:0] unused_addr_next; + + assign unused_predicted_branch = predicted_branch_i; + assign unused_addr_next = addr_next; + + assign branch_mispredict_addr = '0; + end + + // 2. fetch_addr_q + + // Update on a branch or as soon as a request is issued + assign fetch_addr_en = branch_or_mispredict | (valid_new_req & ~valid_req_q); + + assign fetch_addr_d = (branch_i ? addr_i : + branch_mispredict_i ? {branch_mispredict_addr[31:2], 2'b00} : + {fetch_addr_q[31:2], 2'b00}) + + // Current address + 4 + {{29{1'b0}},(valid_new_req & ~valid_req_q),2'b00}; + + always_ff @(posedge clk_i) begin + if (fetch_addr_en) begin + fetch_addr_q <= fetch_addr_d; + end + end + + // Address mux + assign instr_addr = valid_req_q ? stored_addr_q : + branch_spec_i ? addr_i : + branch_mispredict_i ? branch_mispredict_addr : + fetch_addr_q; + + assign instr_addr_w_aligned = {instr_addr[31:2], 2'b00}; + + /////////////////////////////// + // Request outstanding queue // + /////////////////////////////// + + for (genvar i = 0; i < NUM_REQS; i++) begin : g_outstanding_reqs + // Request 0 (always the oldest outstanding request) + if (i == 0) begin : g_req0 + // A request becomes outstanding once granted, and is cleared once the rvalid is received. + // Outstanding requests shift down the queue towards entry 0. + assign rdata_outstanding_n[i] = (valid_req & gnt_or_pmp_err) | + rdata_outstanding_q[i]; + // If a branch is received at any point while a request is outstanding, it must be tracked + // to ensure we discard the data once received + assign branch_discard_n[i] = (valid_req & gnt_or_pmp_err & discard_req_d) | + (branch_or_mispredict & rdata_outstanding_q[i]) | + branch_discard_q[i]; + // Record whether this request received a PMP error + assign rdata_pmp_err_n[i] = (valid_req & ~rdata_outstanding_q[i] & instr_pmp_err_i) | + rdata_pmp_err_q[i]; + + end else begin : g_reqtop + // Entries > 0 consider the FIFO fill state to calculate their next state (by checking + // whether the previous entry is valid) + + assign rdata_outstanding_n[i] = (valid_req & gnt_or_pmp_err & + rdata_outstanding_q[i-1]) | + rdata_outstanding_q[i]; + assign branch_discard_n[i] = (valid_req & gnt_or_pmp_err & discard_req_d & + rdata_outstanding_q[i-1]) | + (branch_or_mispredict & rdata_outstanding_q[i]) | + branch_discard_q[i]; + assign rdata_pmp_err_n[i] = (valid_req & ~rdata_outstanding_q[i] & instr_pmp_err_i & + rdata_outstanding_q[i-1]) | + rdata_pmp_err_q[i]; + end + end + + // Shift the entries down on each instr_rvalid_i + assign rdata_outstanding_s = rvalid_or_pmp_err ? {1'b0,rdata_outstanding_n[NUM_REQS-1:1]} : + rdata_outstanding_n; + assign branch_discard_s = rvalid_or_pmp_err ? {1'b0,branch_discard_n[NUM_REQS-1:1]} : + branch_discard_n; + assign rdata_pmp_err_s = rvalid_or_pmp_err ? {1'b0,rdata_pmp_err_n[NUM_REQS-1:1]} : + rdata_pmp_err_n; + + // Push a new entry to the FIFO once complete (and not cancelled by a branch) + assign fifo_valid = rvalid_or_pmp_err & ~branch_discard_q[0]; + + assign fifo_addr = branch_mispredict_i ? branch_mispredict_addr : addr_i; + + /////////////// + // Registers // + /////////////// + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + valid_req_q <= 1'b0; + discard_req_q <= 1'b0; + rdata_outstanding_q <= 'b0; + branch_discard_q <= 'b0; + rdata_pmp_err_q <= 'b0; + end else begin + valid_req_q <= valid_req_d; + discard_req_q <= discard_req_d; + rdata_outstanding_q <= rdata_outstanding_s; + branch_discard_q <= branch_discard_s; + rdata_pmp_err_q <= rdata_pmp_err_s; + end + end + + ///////////// + // Outputs // + ///////////// + + assign instr_req_o = valid_req; + assign instr_addr_o = instr_addr_w_aligned; + + assign valid_o = valid_raw & ~branch_mispredict_i; + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_register_file_ff.sv b/flow/designs/src/ibex_sv/ibex_register_file_ff.sv new file mode 100644 index 0000000000..3e887b1294 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_register_file_ff.sv @@ -0,0 +1,102 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * RISC-V register file + * + * Register file with 31 or 15x 32 bit wide registers. Register 0 is fixed to 0. + * This register file is based on flip flops. Use this register file when + * targeting FPGA synthesis or Verilator simulation. + */ +module ibex_register_file_ff #( + parameter bit RV32E = 0, + parameter int unsigned DataWidth = 32, + parameter bit DummyInstructions = 0 +) ( + // Clock and Reset + input logic clk_i, + input logic rst_ni, + + input logic test_en_i, + input logic dummy_instr_id_i, + + //Read port R1 + input logic [4:0] raddr_a_i, + output logic [DataWidth-1:0] rdata_a_o, + + //Read port R2 + input logic [4:0] raddr_b_i, + output logic [DataWidth-1:0] rdata_b_o, + + + // Write port W1 + input logic [4:0] waddr_a_i, + input logic [DataWidth-1:0] wdata_a_i, + input logic we_a_i + +); + + localparam int unsigned ADDR_WIDTH = RV32E ? 4 : 5; + localparam int unsigned NUM_WORDS = 2**ADDR_WIDTH; + + logic [NUM_WORDS-1:0][DataWidth-1:0] rf_reg; + logic [NUM_WORDS-1:1][DataWidth-1:0] rf_reg_q; + logic [NUM_WORDS-1:1] we_a_dec; + + always_comb begin : we_a_decoder + for (int unsigned i = 1; i < NUM_WORDS; i++) begin + we_a_dec[i] = (waddr_a_i == 5'(i)) ? we_a_i : 1'b0; + end + end + + // No flops for R0 as it's hard-wired to 0 + for (genvar i = 1; i < NUM_WORDS; i++) begin : g_rf_flops + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rf_reg_q[i] <= '0; + end else if(we_a_dec[i]) begin + rf_reg_q[i] <= wdata_a_i; + end + end + end + + // With dummy instructions enabled, R0 behaves as a real register but will always return 0 for + // real instructions. + if (DummyInstructions) begin : g_dummy_r0 + logic we_r0_dummy; + logic [DataWidth-1:0] rf_r0_q; + + // Write enable for dummy R0 register (waddr_a_i will always be 0 for dummy instructions) + assign we_r0_dummy = we_a_i & dummy_instr_id_i; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rf_r0_q <= '0; + end else if (we_r0_dummy) begin + rf_r0_q <= wdata_a_i; + end + end + + // Output the dummy data for dummy instructions, otherwise R0 reads as zero + assign rf_reg[0] = dummy_instr_id_i ? rf_r0_q : '0; + + end else begin : g_normal_r0 + logic unused_dummy_instr_id; + assign unused_dummy_instr_id = dummy_instr_id_i; + + // R0 is nil + assign rf_reg[0] = '0; + end + + assign rf_reg[NUM_WORDS-1:1] = rf_reg_q[NUM_WORDS-1:1]; + + assign rdata_a_o = rf_reg[raddr_a_i]; + assign rdata_b_o = rf_reg[raddr_b_i]; + + // Signal not used in FF register file + logic unused_test_en; + assign unused_test_en = test_en_i; + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_wb_stage.sv b/flow/designs/src/ibex_sv/ibex_wb_stage.sv new file mode 100644 index 0000000000..7299ad1151 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_wb_stage.sv @@ -0,0 +1,176 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Writeback Stage + * + * Writeback is an optional third pipeline stage. It writes data back to the register file that was + * produced in the ID/EX stage or awaits a response to a load/store (LSU writes direct to register + * file for load data). If the writeback stage is not present (WritebackStage == 0) this acts as + * a simple passthrough to write data direct to the register file. + */ + +`include "prim_assert.sv" + +module ibex_wb_stage #( + parameter bit WritebackStage = 1'b0 +) ( + input logic clk_i, + input logic rst_ni, + + input logic en_wb_i, + input ibex_pkg::wb_instr_type_e instr_type_wb_i, + input logic [31:0] pc_id_i, + input logic instr_is_compressed_id_i, + input logic instr_perf_count_id_i, + + output logic ready_wb_o, + output logic rf_write_wb_o, + output logic outstanding_load_wb_o, + output logic outstanding_store_wb_o, + output logic [31:0] pc_wb_o, + output logic perf_instr_ret_wb_o, + output logic perf_instr_ret_compressed_wb_o, + + input logic [4:0] rf_waddr_id_i, + input logic [31:0] rf_wdata_id_i, + input logic rf_we_id_i, + + input logic [31:0] rf_wdata_lsu_i, + input logic rf_we_lsu_i, + + output logic [31:0] rf_wdata_fwd_wb_o, + + output logic [4:0] rf_waddr_wb_o, + output logic [31:0] rf_wdata_wb_o, + output logic rf_we_wb_o, + + input logic lsu_resp_valid_i, + input logic lsu_resp_err_i, + + output logic instr_done_wb_o +); + + import ibex_pkg::*; + + // 0 == RF write from ID + // 1 == RF write from LSU + logic [31:0] rf_wdata_wb_mux [2]; + logic [1:0] rf_wdata_wb_mux_we; + + if(WritebackStage) begin : g_writeback_stage + logic [31:0] rf_wdata_wb_q; + logic rf_we_wb_q; + logic [4:0] rf_waddr_wb_q; + + logic wb_done; + + logic wb_valid_q; + logic [31:0] wb_pc_q; + logic wb_compressed_q; + logic wb_count_q; + wb_instr_type_e wb_instr_type_q; + + logic wb_valid_d; + + // Stage becomes valid if an instruction enters for ID/EX and valid is cleared when instruction + // is done + assign wb_valid_d = (en_wb_i & ready_wb_o) | (wb_valid_q & ~wb_done); + + // Writeback for non load/store instructions always completes in a cycle (so instantly done) + // Writeback for load/store must wait for response to be received by the LSU + // Signal only relevant if wb_valid_q set + assign wb_done = (wb_instr_type_q == WB_INSTR_OTHER) | lsu_resp_valid_i; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if(~rst_ni) begin + wb_valid_q <= 1'b0; + end else begin + wb_valid_q <= wb_valid_d; + end + end + + always_ff @(posedge clk_i) begin + if(en_wb_i) begin + rf_we_wb_q <= rf_we_id_i; + rf_waddr_wb_q <= rf_waddr_id_i; + rf_wdata_wb_q <= rf_wdata_id_i; + wb_instr_type_q <= instr_type_wb_i; + wb_pc_q <= pc_id_i; + wb_compressed_q <= instr_is_compressed_id_i; + wb_count_q <= instr_perf_count_id_i; + end + end + + assign rf_waddr_wb_o = rf_waddr_wb_q; + assign rf_wdata_wb_mux[0] = rf_wdata_wb_q; + assign rf_wdata_wb_mux_we[0] = rf_we_wb_q & wb_valid_q; + + assign ready_wb_o = ~wb_valid_q | wb_done; + + // Instruction in writeback will be writing to register file if either rf_we is set or writeback + // is awaiting load data. This is used for determining RF read hazards in ID/EX + assign rf_write_wb_o = wb_valid_q & (rf_we_wb_q | (wb_instr_type_q == WB_INSTR_LOAD)); + + assign outstanding_load_wb_o = wb_valid_q & (wb_instr_type_q == WB_INSTR_LOAD); + assign outstanding_store_wb_o = wb_valid_q & (wb_instr_type_q == WB_INSTR_STORE); + + assign pc_wb_o = wb_pc_q; + + assign instr_done_wb_o = wb_valid_q & wb_done; + + // Increment instruction retire counters for valid instructions which are not lsu errors + assign perf_instr_ret_wb_o = instr_done_wb_o & wb_count_q & + ~(lsu_resp_valid_i & lsu_resp_err_i); + assign perf_instr_ret_compressed_wb_o = perf_instr_ret_wb_o & wb_compressed_q; + + // Forward data that will be written to the RF back to ID to resolve data hazards. The flopped + // rf_wdata_wb_q is used rather than rf_wdata_wb_o as the latter includes read data from memory + // that returns too late to be used on the forwarding path. + assign rf_wdata_fwd_wb_o = rf_wdata_wb_q; + end else begin : g_bypass_wb + // without writeback stage just pass through register write signals + assign rf_waddr_wb_o = rf_waddr_id_i; + assign rf_wdata_wb_mux[0] = rf_wdata_id_i; + assign rf_wdata_wb_mux_we[0] = rf_we_id_i; + + // Increment instruction retire counters for valid instructions which are not lsu errors + assign perf_instr_ret_wb_o = instr_perf_count_id_i & en_wb_i & + ~(lsu_resp_valid_i & lsu_resp_err_i); + assign perf_instr_ret_compressed_wb_o = perf_instr_ret_wb_o & instr_is_compressed_id_i; + + // ready needs to be constant 1 without writeback stage (otherwise ID/EX stage will stall) + assign ready_wb_o = 1'b1; + + // Unused Writeback stage only IO & wiring + // Assign inputs and internal wiring to unused signals to satisfy lint checks + // Tie-off outputs to constant values + logic unused_clk; + logic unused_rst; + wb_instr_type_e unused_instr_type_wb; + logic [31:0] unused_pc_id; + + assign unused_clk = clk_i; + assign unused_rst = rst_ni; + assign unused_instr_type_wb = instr_type_wb_i; + assign unused_pc_id = pc_id_i; + + assign outstanding_load_wb_o = 1'b0; + assign outstanding_store_wb_o = 1'b0; + assign pc_wb_o = '0; + assign rf_write_wb_o = 1'b0; + assign rf_wdata_fwd_wb_o = 32'b0; + assign instr_done_wb_o = 1'b0; + end + + assign rf_wdata_wb_mux[1] = rf_wdata_lsu_i; + assign rf_wdata_wb_mux_we[1] = rf_we_lsu_i; + + // RF write data can come from ID results (all RF writes that aren't because of loads will come + // from here) or the LSU (RF writes for load data) + assign rf_wdata_wb_o = rf_wdata_wb_mux_we[0] ? rf_wdata_wb_mux[0] : rf_wdata_wb_mux[1]; + assign rf_we_wb_o = |rf_wdata_wb_mux_we; + + `ASSERT(RFWriteFromOneSourceOnly, $onehot0(rf_wdata_wb_mux_we)) +endmodule diff --git a/flow/designs/src/ibex/prim_clock_gating.v b/flow/designs/src/ibex_sv/syn/rtl/prim_clock_gating.v similarity index 100% rename from flow/designs/src/ibex/prim_clock_gating.v rename to flow/designs/src/ibex_sv/syn/rtl/prim_clock_gating.v diff --git a/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/prim_assert.sv b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/prim_assert.sv new file mode 100644 index 0000000000..ddfc76a680 --- /dev/null +++ b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/prim_assert.sv @@ -0,0 +1,129 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Macros and helper code for using assertions. +// - Provides default clk and rst options to simplify code +// - Provides boiler plate template for common assertions + +`ifndef PRIM_ASSERT_SV +`define PRIM_ASSERT_SV + +`ifdef UVM + // report assertion error with UVM if compiled + package assert_rpt_pkg; + import uvm_pkg::*; + `include "uvm_macros.svh" + function void assert_rpt(string msg); + `uvm_error("ASSERT FAILED", msg) + endfunction + endpackage +`endif + +/////////////////// +// Helper macros // +/////////////////// + +// Default clk and reset signals used by assertion macros below. +`define ASSERT_DEFAULT_CLK clk_i +`define ASSERT_DEFAULT_RST !rst_ni + +// Converts an arbitrary block of code into a Verilog string +`define PRIM_STRINGIFY(__x) `"__x`" + +// The basic helper macros are actually defined in "implementation headers". The macros should do +// the same thing in each case (except for the dummy flavour), but in a way that the respective +// tools support. +// +// If the tool supports assertions in some form, we also define INC_ASSERT (which can be used to +// hide signal definitions that are only used for assertions). +// +// The list of basic macros supported is: +// +// ASSERT_I: Immediate assertion. Note that immediate assertions are sensitive to simulation +// glitches. +// +// ASSERT_INIT: Assertion in initial block. Can be used for things like parameter checking. +// +// ASSERT_FINAL: Assertion in final block. Can be used for things like queues being empty at end of +// sim, all credits returned at end of sim, state machines in idle at end of sim. +// +// ASSERT: Assert a concurrent property directly. It can be called as a module (or +// interface) body item. +// +// Note: We use (__rst !== '0) in the disable iff statements instead of (__rst == +// '1). This properly disables the assertion in cases when reset is X at the +// beginning of a simulation. For that case, (reset == '1) does not disable the +// assertion. +// +// ASSERT_NEVER: Assert a concurrent property NEVER happens +// +// ASSERT_KNOWN: Assert that signal has a known value (each bit is either '0' or '1') after reset. +// It can be called as a module (or interface) body item. +// +// COVER: Cover a concurrent property +// +// ASSUME: Assume a concurrent property +// +// ASSUME_I: Assume an immediate property + +`ifdef VERILATOR + `include "prim_assert_dummy_macros.svh" +`elsif SYNTHESIS + `include "prim_assert_dummy_macros.svh" +`elsif YOSYS + `include "prim_assert_yosys_macros.svh" + `define INC_ASSERT +`else + `include "prim_assert_standard_macros.svh" + `define INC_ASSERT +`endif + +////////////////////////////// +// Complex assertion macros // +////////////////////////////// + +// Assert that signal is an active-high pulse with pulse length of 1 clock cycle +`define ASSERT_PULSE(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ + `ASSERT(__name, $rose(__sig) |=> !(__sig), __clk, __rst) + +// Assert that a property is true only when an enable signal is set. It can be called as a module +// (or interface) body item. +`define ASSERT_IF(__name, __prop, __enable, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ + `ASSERT(__name, (__enable) |-> (__prop), __clk, __rst) + +// Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is +// set. It can be called as a module (or interface) body item. +`define ASSERT_KNOWN_IF(__name, __sig, __enable, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ + `ASSERT_KNOWN(__name``KnownEnable, __enable, __clk, __rst) \ + `ASSERT_IF(__name, !$isunknown(__sig), __enable, __clk, __rst) + +////////////////////////////////// +// For formal verification only // +////////////////////////////////// + +// Note that the existing set of ASSERT macros specified above shall be used for FPV, +// thereby ensuring that the assertions are evaluated during DV simulations as well. + +// ASSUME_FPV +// Assume a concurrent property during formal verification only. +`define ASSUME_FPV(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +`ifdef FPV_ON \ + `ASSUME(__name, __prop, __clk, __rst) \ +`endif + +// ASSUME_I_FPV +// Assume a concurrent property during formal verification only. +`define ASSUME_I_FPV(__name, __prop) \ +`ifdef FPV_ON \ + `ASSUME_I(__name, __prop) \ +`endif + +// COVER_FPV +// Cover a concurrent property during formal verification +`define COVER_FPV(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +`ifdef FPV_ON \ + `COVER(__name, __prop, __clk, __rst) \ +`endif + +`endif // PRIM_ASSERT_SV diff --git a/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/prim_assert_dummy_macros.svh b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/prim_assert_dummy_macros.svh new file mode 100644 index 0000000000..4a0da70336 --- /dev/null +++ b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/prim_assert_dummy_macros.svh @@ -0,0 +1,16 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Macro bodies included by prim_assert.sv for tools that don't support assertions. See +// prim_assert.sv for documentation for each of the macros. + +`define ASSERT_I(__name, __prop) +`define ASSERT_INIT(__name, __prop) +`define ASSERT_FINAL(__name, __prop) +`define ASSERT(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) +`define ASSERT_NEVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) +`define ASSERT_KNOWN(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) +`define COVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) +`define ASSUME(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) +`define ASSUME_I(__name, __prop) diff --git a/flow/designs/src/mock-array/util.tcl b/flow/designs/src/mock-array/util.tcl index 960a3dffdb..a219929c6d 100644 --- a/flow/designs/src/mock-array/util.tcl +++ b/flow/designs/src/mock-array/util.tcl @@ -1,56 +1,56 @@ # Helper function to split a string into a list of strings and numbers -proc split_strings_and_numbers {str} { - set result {} - foreach {all letters numbers} [regexp -all -inline {(\D*)(\d*)} $str] { - if {$letters ne ""} { - lappend result $letters - } - if {$numbers ne ""} { - lappend result [expr {$numbers + 0}] ;# Convert to integer - } +proc split_strings_and_numbers { str } { + set result {} + foreach {all letters numbers} [regexp -all -inline {(\D*)(\d*)} $str] { + if { $letters ne "" } { + lappend result $letters } - return $result + if { $numbers ne "" } { + lappend result [expr { $numbers + 0 }] ;# Convert to integer + } + } + return $result } # Custom comparison function -proc natural_compare {str1 str2} { - set list1 [split_strings_and_numbers $str1] - set list2 [split_strings_and_numbers $str2] - set len [expr {min([llength $list1], [llength $list2])}] - for {set i 0} {$i < $len} {incr i} { - set part1 [lindex $list1 $i] - set part2 [lindex $list2 $i] - if {$part1 ne $part2} { - if {[string is integer -strict $part1] && [string is integer -strict $part2]} { - return [expr {$part1 - $part2}] - } else { - return [string compare $part1 $part2] - } - } +proc natural_compare { str1 str2 } { + set list1 [split_strings_and_numbers $str1] + set list2 [split_strings_and_numbers $str2] + set len [expr { min([llength $list1], [llength $list2]) }] + for { set i 0 } { $i < $len } { incr i } { + set part1 [lindex $list1 $i] + set part2 [lindex $list2 $i] + if { $part1 ne $part2 } { + if { [string is integer -strict $part1] && [string is integer -strict $part2] } { + return [expr { $part1 - $part2 }] + } else { + return [string compare $part1 $part2] + } } - return [expr {[llength $list1] - [llength $list2]}] ;# If all parts are equal, compare by length + } + return [expr { [llength $list1] - [llength $list2] }] ;# If all parts are equal, compare by length } -proc natural_sort {list} { - return [lsort -command natural_compare $list] +proc natural_sort { list } { + return [lsort -command natural_compare $list] } -proc match_pins { regex {direction .*} {is_clock 0}} { - set pins {} - # The regex for get_ports is not the tcl regex - foreach pin [get_ports -regex .*] { - set input [get_property $pin name] - # We want the Tcl regex - if {![regexp $regex $input]} { - continue - } - if {![regexp $direction [get_property $pin direction]]} { - continue - } - if {[expr $is_clock != [sta::is_clock_src [sta::get_port_pin $pin]]]} { - continue - } - lappend pins [get_property $pin name] +proc match_pins { regex { direction .* } { is_clock 0 } } { + set pins {} + # The regex for get_ports is not the tcl regex + foreach pin [get_ports -regex .*] { + set input [get_property $pin name] + # We want the Tcl regex + if { ![regexp $regex $input] } { + continue + } + if { ![regexp $direction [get_property $pin direction]] } { + continue + } + if { $is_clock != [sta::is_clock_src [sta::get_port_pin $pin]] } { + continue } - return [natural_sort $pins] + lappend pins [get_property $pin name] + } + return [natural_sort $pins] } diff --git a/flow/platforms/asap7/config.mk b/flow/platforms/asap7/config.mk index 73be68584f..2ecb360eb8 100644 --- a/flow/platforms/asap7/config.mk +++ b/flow/platforms/asap7/config.mk @@ -7,6 +7,8 @@ ifeq ($(LIB_MODEL),) endif export LIB_DIR ?= $(PLATFORM_DIR)/lib/$(LIB_MODEL) +export PLATFORM_TCL = $(PLATFORM_DIR)/liberty_suppressions.tcl + #Library Setup variable export TECH_LEF = $(PLATFORM_DIR)/lef/asap7_tech_1x_201209.lef @@ -63,9 +65,12 @@ export SET_RC_TCL = $(PLATFORM_DIR)/setRC.tcl # Route options export MIN_ROUTING_LAYER ?= M2 -#export MIN_CLOCK_ROUTING_LAYER = M4 +export MIN_CLK_ROUTING_LAYER ?= M4 export MAX_ROUTING_LAYER ?= M7 +# Define fastRoute tcl +export FASTROUTE_TCL ?= $(PLATFORM_DIR)/fastroute.tcl + # KLayout technology file export KLAYOUT_TECH_FILE = $(PLATFORM_DIR)/KLayout/asap7.lyt @@ -75,87 +80,91 @@ export KLAYOUT_DRC_FILE = $(PLATFORM_DIR)/drc/asap7.lydrc # OpenRCX extRules export RCX_RULES = $(PLATFORM_DIR)/rcx_patterns.rules -# XS - defining function for using LVT -ifeq ($(ASAP7_USE_VT), LVT) - export VT_TAG = L -else ifeq ($(ASAP7_USE_VT), SLVT) - export VT_TAG = SL -else - # Default to RVT - export VT_TAG = R -endif - +# PLACEHOLDER gets replaced with the appropriate VT tag in the following templates +export BC_NLDM_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_nldm_220123.lib +export BC_CCS_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_ccs_220123.lib +export WC_NLDM_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_SS_nldm_220123.lib +export TC_NLDM_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_TT_nldm_220123.lib +export BC_NLDM_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_FF_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_FF_nldm_220122.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_FF_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_FF_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_nldm_220123.lib +export BC_CCS_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_FF_ccs_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_FF_ccs_220122.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_FF_ccs_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_FF_ccs_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_ccs_220123.lib +export WC_NLDM_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_SS_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_SS_nldm_220122.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_SS_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_SS_nldm_220123.lib \ + $(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_SS_nldm_211120.lib.gz +export TC_NLDM_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_TT_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_TT_nldm_220122.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_TT_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_TT_nldm_220123.lib \ + $(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_TT_nldm_211120.lib.gz +export FILL_CELLS_T = FILLERxp5_ASAP7_75t_ \ + FILLER_ASAP7_75t_ \ + DECAPx1_ASAP7_75t_ \ + DECAPx2_ASAP7_75t_ \ + DECAPx4_ASAP7_75t_ \ + DECAPx6_ASAP7_75t_ \ + DECAPx10_ASAP7_75t_ + +# Default to RVT if unset +export VT_LIST = $(if $(strip $(ASAP7_USE_VT)), $(ASAP7_USE_VT), RVT) + +# # The first VT in the ASAP7_USE_VT list is the primary VT. The others get added to OTHER_VT +export PRIMARY_VT = $(word 1, $(VT_LIST)) +export PRIMARY_VT_TAG = $(strip $(patsubst %VT, %, $(PRIMARY_VT))) +export OTHER_VT = $(wordlist 2, $(words $(VT_LIST)), $(VT_LIST)) + +## Set cells based on the primary VT first # Set the TIEHI/TIELO cells # These are used in yosys synthesis to avoid logical 1/0's in the netlist -export TIEHI_CELL_AND_PORT ?= TIEHIx1_ASAP7_75t_$(VT_TAG) H -export TIELO_CELL_AND_PORT ?= TIELOx1_ASAP7_75t_$(VT_TAG) L +export TIEHI_CELL_AND_PORT ?= TIEHIx1_ASAP7_75t_$(PRIMARY_VT_TAG) H +export TIELO_CELL_AND_PORT ?= TIELOx1_ASAP7_75t_$(PRIMARY_VT_TAG) L # Used in synthesis -export MIN_BUF_CELL_AND_PORTS ?= BUFx2_ASAP7_75t_$(VT_TAG) A Y +export MIN_BUF_CELL_AND_PORTS ?= BUFx2_ASAP7_75t_$(PRIMARY_VT_TAG) A Y -export HOLD_BUF_CELL ?= BUFx2_ASAP7_75t_$(VT_TAG) +export HOLD_BUF_CELL ?= BUFx2_ASAP7_75t_$(PRIMARY_VT_TAG) -export ABC_DRIVER_CELL ?= BUFx2_ASAP7_75t_$(VT_TAG) +export ABC_DRIVER_CELL ?= BUFx2_ASAP7_75t_$(PRIMARY_VT_TAG) # Fill cells used in fill cell insertion -export FILL_CELLS ?= FILLERxp5_ASAP7_75t_$(VT_TAG) \ - FILLER_ASAP7_75t_$(VT_TAG) \ - DECAPx1_ASAP7_75t_$(VT_TAG) \ - DECAPx2_ASAP7_75t_$(VT_TAG) \ - DECAPx4_ASAP7_75t_$(VT_TAG) \ - DECAPx6_ASAP7_75t_$(VT_TAG) \ - DECAPx10_ASAP7_75t_$(VT_TAG) +export FILL_CELLS ?= $(addsuffix $(PRIMARY_VT_TAG), $(FILL_CELLS_T)) -export TAP_CELL_NAME ?= TAPCELL_ASAP7_75t_$(VT_TAG) +export TAP_CELL_NAME ?= TAPCELL_ASAP7_75t_$(PRIMARY_VT_TAG) # GDS_FILES has to be = vs. ?= because GDS_FILES gets set in the ORFS Makefile -export GDS_FILES = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_$(VT_TAG)_220121a.gds \ - $(ADDITIONAL_GDS) +export GDS_FILES = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_$(PRIMARY_VT_TAG)_220121a.gds -export SC_LEF ?= $(PLATFORM_DIR)/lef/asap7sc7p5t_28_$(VT_TAG)_1x_220121a.lef +export SC_LEF ?= $(PLATFORM_DIR)/lef/asap7sc7p5t_28_$(PRIMARY_VT_TAG)_1x_220121a.lef # Yosys mapping files -export LATCH_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_latch_$(VT_TAG).v -export CLKGATE_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_clkgate_$(VT_TAG).v -export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_adders_$(VT_TAG).v - -export BC_NLDM_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_nldm_220123.lib - -export BC_NLDM_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_FF_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_nldm_220123.lib - -export BC_CCS_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_FF_ccs_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_FF_ccs_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_FF_ccs_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_FF_ccs_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_ccs_220123.lib \ - $(BC_ADDITIONAL_LIBS) - -export BC_CCS_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_ccs_220123.lib - -export WC_NLDM_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_SS_nldm_220123.lib +export LATCH_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_latch_$(PRIMARY_VT_TAG).v +export CLKGATE_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_clkgate_$(PRIMARY_VT_TAG).v +export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_adders_$(PRIMARY_VT_TAG).v -export WC_NLDM_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_SS_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_SS_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_SS_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_SS_nldm_220123.lib \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_SS_nldm_211120.lib.gz +export BC_NLDM_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_NLDM_DFF_LIB_FILE_T)) +export BC_NLDM_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_NLDM_LIB_FILES_T)) +export BC_CCS_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_CCS_LIB_FILES_T)) \ + $(BC_ADDITIONAL_LIBS) +export BC_CCS_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_CCS_DFF_LIB_FILE_T)) -export TC_NLDM_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_TT_nldm_220123.lib +export WC_NLDM_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(WC_NLDM_DFF_LIB_FILE_T)) +export WC_NLDM_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(WC_NLDM_LIB_FILES_T)) -export TC_NLDM_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_TT_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_TT_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_TT_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_TT_nldm_220123.lib \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_TT_nldm_211120.lib.gz +export TC_NLDM_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(TC_NLDM_DFF_LIB_FILE_T)) +export TC_NLDM_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(TC_NLDM_LIB_FILES_T)) ifeq ($(CLUSTER_FLOPS),1) # Add the multi-bit FF for clustering. These are single corner libraries. - export ADDITIONAL_LIBS += $(LIB_DIR)/asap7sc7p5t_DFFHQNH2V2X_$(VT_TAG)VT_TT_nldm_FAKE.lib \ - $(LIB_DIR)/asap7sc7p5t_DFFHQNV2X_$(VT_TAG)VT_TT_nldm_FAKE.lib + export ADDITIONAL_LIBS += $(LIB_DIR)/asap7sc7p5t_DFFHQNH2V2X_$(PRIMARY_VT_TAG)VT_TT_nldm_FAKE.lib \ + $(LIB_DIR)/asap7sc7p5t_DFFHQNV2X_$(PRIMARY_VT_TAG)VT_TT_nldm_FAKE.lib export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/asap7sc7p5t_DFFHQNH2V2X.lef \ $(PLATFORM_DIR)/lef/asap7sc7p5t_DFFHQNV2X.lef @@ -163,6 +172,22 @@ ifeq ($(CLUSTER_FLOPS),1) export GDS_ALLOW_EMPTY ?= DFFHQN[VH][24].* endif +### Add additional files to the variables based on the OTHER_VT list +$(foreach vt_type,$(OTHER_VT),\ + $(eval OTHER_VT_TAG = $(strip $(patsubst %VT, %, $(vt_type)))) \ + $(eval ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/asap7sc7p5t_28_$(OTHER_VT_TAG)_1x_220121a.lef) \ + $(eval BC_NLDM_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_NLDM_DFF_LIB_FILE_T))) \ + $(eval BC_CCS_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_CCS_DFF_LIB_FILE_T))) \ + $(eval WC_NLDM_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(WC_NLDM_DFF_LIB_FILE_T))) \ + $(eval TC_NLDM_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(TC_NLDM_DFF_LIB_FILE_T))) \ + $(eval BC_NLDM_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_NLDM_LIB_FILES_T))) \ + $(eval BC_CCS_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_CCS_LIB_FILES_T))) \ + $(eval WC_NLDM_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(WC_NLDM_LIB_FILES_T))) \ + $(eval TC_NLDM_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(TC_NLDM_LIB_FILES_T))) \ + $(eval GDS_FILES += $(PLATFORM_DIR)/gds/asap7sc7p5t_28_$(OTHER_VT_TAG)_220121a.gds) \ + $(eval FILL_CELLS += $(addsuffix $(PRIMARY_VT_TAG), $(FILL_CELLS_T))) \ +) + # Dont use SC library based on CORNER selection # # BC - Best case, fastest @@ -171,6 +196,7 @@ endif export CORNER ?= BC export LIB_FILES += $($(CORNER)_$(LIB_MODEL)_LIB_FILES) export LIB_FILES += $(ADDITIONAL_LIBS) +export GDS_FILES += $(ADDITIONAL_GDS) export DB_FILES += $(realpath $($(CORNER)_DB_FILES)) export TEMPERATURE = $($(CORNER)_TEMPERATURE) export VOLTAGE = $($(CORNER)_VOLTAGE) diff --git a/flow/platforms/asap7/constraints.sdc b/flow/platforms/asap7/constraints.sdc index e7ca24cb2b..103986bbbc 100644 --- a/flow/platforms/asap7/constraints.sdc +++ b/flow/platforms/asap7/constraints.sdc @@ -1,6 +1,6 @@ # A minimal generic constraints.sdc for architectural exploration of macros # ------------------------------------------------------------------------- -# +# # Used in designs/asap7/mock-array, for example. # # From the following observations, all else follows: the only thing @@ -8,7 +8,7 @@ # other constraints give the flow an optimization target. Failure # to meet the timing constraint of an optimization target constraint # is not a timing closure failure. -# +# # Note that ORFS regression checks do not have the ability to distinguish # between timing closure failures(register to register paths) and # optimization constraints violations. @@ -17,26 +17,26 @@ # in mock-array Element, such as maximum transit time for a combinational path # through mock-array Element, may or may not cause timing # violations later on higher up in mock-array on register to register paths. -# +# # For the Element, the only register to register path # are within the Element and no lower level macros are # involved. Register to register paths within Element have to be checked # at the Element level as they are invisible higher up in mock-array. -# +# # As for the remaining optimization constraints for Element, they # should be for combinational through paths(io-io) and # from input pins to register(io-reg) and from register to output pins(reg-io): -# +# # This constraints.sdc file is designed such that the clock latency & tree # can be ignored as far constraints go; # it is not part of the optimization constraints. The clock tree latency # is accounted for in register to register paths and not visible outside # of the macro that use this constraints.sdc. -# +# # All non reg-reg paths in Element are part of reg-reg paths in mock-array # and timing closure in which those take part are checked at the mock-array # level. -# +# # With this in mind, the constraints.sdc file for the Element becomes # quite general and simple. set_max_delay is used exclusively for # optimization constraints and the clock period is used to check timing @@ -51,13 +51,13 @@ # the time at the clock pin for the macro, which makes it impossible to articulate # the number that is passed in to set_input/output_delay without taking # clock network insertion latency into account. -# +# # Since set_input_delay is not used and set_max_delay is used instead, then # no hold cells are inserted, which is what is desired here. # # Details such as clock uncertainty, max transition time, load, etc. # is beyond the scope of this generic constraints.sdc file. -# +# # Beware of [path segmentation](https://docs.xilinx.com/r/2020.2-English/ug906-vivado-design-analysis/TIMING-13-Timing-Paths-Ignored-Due-to-Path-Segmentation), which # can occur with OpenSTA. @@ -69,17 +69,19 @@ set sdc_version 2.0 set clk_port [get_ports $clk_port_name] create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port -set non_clk_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set all_register_outputs [get_pins -of_objects [all_registers] -filter {direction == output}] +set non_clk_inputs [all_inputs -no_clocks] # Optimization targets: overconstrain by default and # leave refinements to a more design specific constraints.sdc file. # # Minimum time for io-io, io-reg, reg-io paths in macro is on # the order of 80ps for a small macro on ASAP7. -set_max_delay [expr {[info exists in2reg_max] ? $in2reg_max : 80}] -from $non_clk_inputs -to [all_registers] -set_max_delay [expr {[info exists reg2out_max] ? $reg2out_max : 80}] -from $all_register_outputs -to [all_outputs] -set_max_delay [expr {[info exists in2out_max] ? $in2out_max : 80}] -from $non_clk_inputs -to [all_outputs] +set_max_delay [expr { [info exists in2reg_max] ? $in2reg_max : 80 }] -from $non_clk_inputs \ + -to [all_registers] +set_max_delay [expr { [info exists reg2out_max] ? $reg2out_max : 80 }] -from [all_registers] \ + -to [all_outputs] +set_max_delay [expr { [info exists in2out_max] ? $in2out_max : 80 }] -from $non_clk_inputs \ + -to [all_outputs] # This allows us to view the different groups # in the histogram in the GUI and also includes these diff --git a/flow/platforms/asap7/fastroute.tcl b/flow/platforms/asap7/fastroute.tcl new file mode 100644 index 0000000000..51c8403b1c --- /dev/null +++ b/flow/platforms/asap7/fastroute.tcl @@ -0,0 +1,3 @@ +set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.25 +set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) +set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) diff --git a/flow/platforms/asap7/lef/fakeram7_128x64.lef b/flow/platforms/asap7/lef/fakeram7_128x64.lef new file mode 100644 index 0000000000..8b0977f4b9 --- /dev/null +++ b/flow/platforms/asap7/lef/fakeram7_128x64.lef @@ -0,0 +1,1341 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO fakeram7_128x64 + PROPERTY width 64 ; + PROPERTY depth 128 ; + PROPERTY banks 2 ; + FOREIGN fakeram7_128x64 0 0 ; + SYMMETRY X Y R90 ; + SIZE 16.720 BY 21.600 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.192 0.024 0.216 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.024 0.360 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.480 0.024 0.504 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.024 0.648 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.768 0.024 0.792 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.024 0.936 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.056 0.024 1.080 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.024 1.224 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.344 0.024 1.368 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.024 1.512 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.632 0.024 1.656 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.776 0.024 1.800 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.920 0.024 1.944 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.064 0.024 2.088 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.208 0.024 2.232 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.024 2.376 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.024 2.520 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.640 0.024 2.664 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.024 2.808 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.024 2.952 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.024 3.096 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.024 3.240 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.024 3.384 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.504 0.024 3.528 ; + END + END rd_out[24] + PIN rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.648 0.024 3.672 ; + END + END rd_out[25] + PIN rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.792 0.024 3.816 ; + END + END rd_out[26] + PIN rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.936 0.024 3.960 ; + END + END rd_out[27] + PIN rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.080 0.024 4.104 ; + END + END rd_out[28] + PIN rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.224 0.024 4.248 ; + END + END rd_out[29] + PIN rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.368 0.024 4.392 ; + END + END rd_out[30] + PIN rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.512 0.024 4.536 ; + END + END rd_out[31] + PIN rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.656 0.024 4.680 ; + END + END rd_out[32] + PIN rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.024 4.824 ; + END + END rd_out[33] + PIN rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.944 0.024 4.968 ; + END + END rd_out[34] + PIN rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.088 0.024 5.112 ; + END + END rd_out[35] + PIN rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.232 0.024 5.256 ; + END + END rd_out[36] + PIN rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.376 0.024 5.400 ; + END + END rd_out[37] + PIN rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.520 0.024 5.544 ; + END + END rd_out[38] + PIN rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.664 0.024 5.688 ; + END + END rd_out[39] + PIN rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.024 5.832 ; + END + END rd_out[40] + PIN rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.952 0.024 5.976 ; + END + END rd_out[41] + PIN rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.096 0.024 6.120 ; + END + END rd_out[42] + PIN rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.240 0.024 6.264 ; + END + END rd_out[43] + PIN rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.384 0.024 6.408 ; + END + END rd_out[44] + PIN rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.528 0.024 6.552 ; + END + END rd_out[45] + PIN rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.672 0.024 6.696 ; + END + END rd_out[46] + PIN rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.816 0.024 6.840 ; + END + END rd_out[47] + PIN rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.960 0.024 6.984 ; + END + END rd_out[48] + PIN rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.104 0.024 7.128 ; + END + END rd_out[49] + PIN rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.248 0.024 7.272 ; + END + END rd_out[50] + PIN rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.392 0.024 7.416 ; + END + END rd_out[51] + PIN rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.536 0.024 7.560 ; + END + END rd_out[52] + PIN rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.680 0.024 7.704 ; + END + END rd_out[53] + PIN rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.824 0.024 7.848 ; + END + END rd_out[54] + PIN rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.968 0.024 7.992 ; + END + END rd_out[55] + PIN rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.112 0.024 8.136 ; + END + END rd_out[56] + PIN rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.256 0.024 8.280 ; + END + END rd_out[57] + PIN rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.400 0.024 8.424 ; + END + END rd_out[58] + PIN rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.544 0.024 8.568 ; + END + END rd_out[59] + PIN rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.688 0.024 8.712 ; + END + END rd_out[60] + PIN rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.832 0.024 8.856 ; + END + END rd_out[61] + PIN rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.976 0.024 9.000 ; + END + END rd_out[62] + PIN rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.120 0.024 9.144 ; + END + END rd_out[63] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.792 0.024 9.816 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.936 0.024 9.960 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.080 0.024 10.104 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.224 0.024 10.248 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.368 0.024 10.392 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.512 0.024 10.536 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.656 0.024 10.680 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.800 0.024 10.824 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.944 0.024 10.968 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.088 0.024 11.112 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.232 0.024 11.256 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.376 0.024 11.400 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.520 0.024 11.544 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.664 0.024 11.688 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.808 0.024 11.832 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.952 0.024 11.976 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.096 0.024 12.120 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.240 0.024 12.264 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.384 0.024 12.408 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.528 0.024 12.552 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.672 0.024 12.696 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.816 0.024 12.840 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.960 0.024 12.984 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.104 0.024 13.128 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.248 0.024 13.272 ; + END + END wd_in[24] + PIN wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.392 0.024 13.416 ; + END + END wd_in[25] + PIN wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.536 0.024 13.560 ; + END + END wd_in[26] + PIN wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.680 0.024 13.704 ; + END + END wd_in[27] + PIN wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.824 0.024 13.848 ; + END + END wd_in[28] + PIN wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.968 0.024 13.992 ; + END + END wd_in[29] + PIN wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.112 0.024 14.136 ; + END + END wd_in[30] + PIN wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.256 0.024 14.280 ; + END + END wd_in[31] + PIN wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.400 0.024 14.424 ; + END + END wd_in[32] + PIN wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.544 0.024 14.568 ; + END + END wd_in[33] + PIN wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.688 0.024 14.712 ; + END + END wd_in[34] + PIN wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.832 0.024 14.856 ; + END + END wd_in[35] + PIN wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.976 0.024 15.000 ; + END + END wd_in[36] + PIN wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.120 0.024 15.144 ; + END + END wd_in[37] + PIN wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.264 0.024 15.288 ; + END + END wd_in[38] + PIN wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.408 0.024 15.432 ; + END + END wd_in[39] + PIN wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.552 0.024 15.576 ; + END + END wd_in[40] + PIN wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.696 0.024 15.720 ; + END + END wd_in[41] + PIN wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.840 0.024 15.864 ; + END + END wd_in[42] + PIN wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.984 0.024 16.008 ; + END + END wd_in[43] + PIN wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.128 0.024 16.152 ; + END + END wd_in[44] + PIN wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.272 0.024 16.296 ; + END + END wd_in[45] + PIN wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.416 0.024 16.440 ; + END + END wd_in[46] + PIN wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.560 0.024 16.584 ; + END + END wd_in[47] + PIN wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.704 0.024 16.728 ; + END + END wd_in[48] + PIN wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.848 0.024 16.872 ; + END + END wd_in[49] + PIN wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.992 0.024 17.016 ; + END + END wd_in[50] + PIN wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.136 0.024 17.160 ; + END + END wd_in[51] + PIN wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.280 0.024 17.304 ; + END + END wd_in[52] + PIN wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.424 0.024 17.448 ; + END + END wd_in[53] + PIN wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.568 0.024 17.592 ; + END + END wd_in[54] + PIN wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.712 0.024 17.736 ; + END + END wd_in[55] + PIN wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.856 0.024 17.880 ; + END + END wd_in[56] + PIN wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.000 0.024 18.024 ; + END + END wd_in[57] + PIN wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.144 0.024 18.168 ; + END + END wd_in[58] + PIN wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.288 0.024 18.312 ; + END + END wd_in[59] + PIN wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.432 0.024 18.456 ; + END + END wd_in[60] + PIN wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.576 0.024 18.600 ; + END + END wd_in[61] + PIN wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.720 0.024 18.744 ; + END + END wd_in[62] + PIN wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.864 0.024 18.888 ; + END + END wd_in[63] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.536 0.024 19.560 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.680 0.024 19.704 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.824 0.024 19.848 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.968 0.024 19.992 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.112 0.024 20.136 ; + END + END addr_in[4] + PIN addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.256 0.024 20.280 ; + END + END addr_in[5] + PIN addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.400 0.024 20.424 ; + END + END addr_in[6] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.072 0.024 21.096 ; + END + END we_in + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.216 0.024 21.240 ; + END + END ce_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.360 0.024 21.384 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 16.672 0.096 ; + RECT 0.048 0.768 16.672 0.864 ; + RECT 0.048 1.536 16.672 1.632 ; + RECT 0.048 2.304 16.672 2.400 ; + RECT 0.048 3.072 16.672 3.168 ; + RECT 0.048 3.840 16.672 3.936 ; + RECT 0.048 4.608 16.672 4.704 ; + RECT 0.048 5.376 16.672 5.472 ; + RECT 0.048 6.144 16.672 6.240 ; + RECT 0.048 6.912 16.672 7.008 ; + RECT 0.048 7.680 16.672 7.776 ; + RECT 0.048 8.448 16.672 8.544 ; + RECT 0.048 9.216 16.672 9.312 ; + RECT 0.048 9.984 16.672 10.080 ; + RECT 0.048 10.752 16.672 10.848 ; + RECT 0.048 11.520 16.672 11.616 ; + RECT 0.048 12.288 16.672 12.384 ; + RECT 0.048 13.056 16.672 13.152 ; + RECT 0.048 13.824 16.672 13.920 ; + RECT 0.048 14.592 16.672 14.688 ; + RECT 0.048 15.360 16.672 15.456 ; + RECT 0.048 16.128 16.672 16.224 ; + RECT 0.048 16.896 16.672 16.992 ; + RECT 0.048 17.664 16.672 17.760 ; + RECT 0.048 18.432 16.672 18.528 ; + RECT 0.048 19.200 16.672 19.296 ; + RECT 0.048 19.968 16.672 20.064 ; + RECT 0.048 20.736 16.672 20.832 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 16.672 0.480 ; + RECT 0.048 1.152 16.672 1.248 ; + RECT 0.048 1.920 16.672 2.016 ; + RECT 0.048 2.688 16.672 2.784 ; + RECT 0.048 3.456 16.672 3.552 ; + RECT 0.048 4.224 16.672 4.320 ; + RECT 0.048 4.992 16.672 5.088 ; + RECT 0.048 5.760 16.672 5.856 ; + RECT 0.048 6.528 16.672 6.624 ; + RECT 0.048 7.296 16.672 7.392 ; + RECT 0.048 8.064 16.672 8.160 ; + RECT 0.048 8.832 16.672 8.928 ; + RECT 0.048 9.600 16.672 9.696 ; + RECT 0.048 10.368 16.672 10.464 ; + RECT 0.048 11.136 16.672 11.232 ; + RECT 0.048 11.904 16.672 12.000 ; + RECT 0.048 12.672 16.672 12.768 ; + RECT 0.048 13.440 16.672 13.536 ; + RECT 0.048 14.208 16.672 14.304 ; + RECT 0.048 14.976 16.672 15.072 ; + RECT 0.048 15.744 16.672 15.840 ; + RECT 0.048 16.512 16.672 16.608 ; + RECT 0.048 17.280 16.672 17.376 ; + RECT 0.048 18.048 16.672 18.144 ; + RECT 0.048 18.816 16.672 18.912 ; + RECT 0.048 19.584 16.672 19.680 ; + RECT 0.048 20.352 16.672 20.448 ; + RECT 0.048 21.120 16.672 21.216 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 16.720 21.600 ; + LAYER M2 ; + RECT 0 0 16.720 21.600 ; + LAYER M3 ; + RECT 0 0 16.720 21.600 ; + LAYER M4 ; + RECT 0 0 16.720 21.600 ; + END +END fakeram7_128x64 + +END LIBRARY diff --git a/flow/platforms/asap7/lef/fakeram7_256x256.lef b/flow/platforms/asap7/lef/fakeram7_256x256.lef new file mode 100644 index 0000000000..448fa36cef --- /dev/null +++ b/flow/platforms/asap7/lef/fakeram7_256x256.lef @@ -0,0 +1,4969 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO fakeram7_256x256 + PROPERTY width 256 ; + PROPERTY depth 256 ; + PROPERTY banks 1 ; + FOREIGN fakeram7_256x256 0 0 ; + SYMMETRY X Y R90 ; + SIZE 33.250 BY 84.000 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.192 0.024 0.216 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.024 0.360 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.480 0.024 0.504 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.024 0.648 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.768 0.024 0.792 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.024 0.936 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.056 0.024 1.080 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.024 1.224 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.344 0.024 1.368 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.024 1.512 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.632 0.024 1.656 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.776 0.024 1.800 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.920 0.024 1.944 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.064 0.024 2.088 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.208 0.024 2.232 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.024 2.376 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.024 2.520 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.640 0.024 2.664 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.024 2.808 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.024 2.952 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.024 3.096 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.024 3.240 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.024 3.384 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.504 0.024 3.528 ; + END + END rd_out[24] + PIN rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.648 0.024 3.672 ; + END + END rd_out[25] + PIN rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.792 0.024 3.816 ; + END + END rd_out[26] + PIN rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.936 0.024 3.960 ; + END + END rd_out[27] + PIN rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.080 0.024 4.104 ; + END + END rd_out[28] + PIN rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.224 0.024 4.248 ; + END + END rd_out[29] + PIN rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.368 0.024 4.392 ; + END + END rd_out[30] + PIN rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.512 0.024 4.536 ; + END + END rd_out[31] + PIN rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.656 0.024 4.680 ; + END + END rd_out[32] + PIN rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.024 4.824 ; + END + END rd_out[33] + PIN rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.944 0.024 4.968 ; + END + END rd_out[34] + PIN rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.088 0.024 5.112 ; + END + END rd_out[35] + PIN rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.232 0.024 5.256 ; + END + END rd_out[36] + PIN rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.376 0.024 5.400 ; + END + END rd_out[37] + PIN rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.520 0.024 5.544 ; + END + END rd_out[38] + PIN rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.664 0.024 5.688 ; + END + END rd_out[39] + PIN rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.024 5.832 ; + END + END rd_out[40] + PIN rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.952 0.024 5.976 ; + END + END rd_out[41] + PIN rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.096 0.024 6.120 ; + END + END rd_out[42] + PIN rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.240 0.024 6.264 ; + END + END rd_out[43] + PIN rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.384 0.024 6.408 ; + END + END rd_out[44] + PIN rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.528 0.024 6.552 ; + END + END rd_out[45] + PIN rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.672 0.024 6.696 ; + END + END rd_out[46] + PIN rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.816 0.024 6.840 ; + END + END rd_out[47] + PIN rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.960 0.024 6.984 ; + END + END rd_out[48] + PIN rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.104 0.024 7.128 ; + END + END rd_out[49] + PIN rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.248 0.024 7.272 ; + END + END rd_out[50] + PIN rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.392 0.024 7.416 ; + END + END rd_out[51] + PIN rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.536 0.024 7.560 ; + END + END rd_out[52] + PIN rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.680 0.024 7.704 ; + END + END rd_out[53] + PIN rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.824 0.024 7.848 ; + END + END rd_out[54] + PIN rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.968 0.024 7.992 ; + END + END rd_out[55] + PIN rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.112 0.024 8.136 ; + END + END rd_out[56] + PIN rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.256 0.024 8.280 ; + END + END rd_out[57] + PIN rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.400 0.024 8.424 ; + END + END rd_out[58] + PIN rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.544 0.024 8.568 ; + END + END rd_out[59] + PIN rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.688 0.024 8.712 ; + END + END rd_out[60] + PIN rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.832 0.024 8.856 ; + END + END rd_out[61] + PIN rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.976 0.024 9.000 ; + END + END rd_out[62] + PIN rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.120 0.024 9.144 ; + END + END rd_out[63] + PIN rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.264 0.024 9.288 ; + END + END rd_out[64] + PIN rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.408 0.024 9.432 ; + END + END rd_out[65] + PIN rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.552 0.024 9.576 ; + END + END rd_out[66] + PIN rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.696 0.024 9.720 ; + END + END rd_out[67] + PIN rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.840 0.024 9.864 ; + END + END rd_out[68] + PIN rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.984 0.024 10.008 ; + END + END rd_out[69] + PIN rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.128 0.024 10.152 ; + END + END rd_out[70] + PIN rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.272 0.024 10.296 ; + END + END rd_out[71] + PIN rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.416 0.024 10.440 ; + END + END rd_out[72] + PIN rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.560 0.024 10.584 ; + END + END rd_out[73] + PIN rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.704 0.024 10.728 ; + END + END rd_out[74] + PIN rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.848 0.024 10.872 ; + END + END rd_out[75] + PIN rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.992 0.024 11.016 ; + END + END rd_out[76] + PIN rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.136 0.024 11.160 ; + END + END rd_out[77] + PIN rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.280 0.024 11.304 ; + END + END rd_out[78] + PIN rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.424 0.024 11.448 ; + END + END rd_out[79] + PIN rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.568 0.024 11.592 ; + END + END rd_out[80] + PIN rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.712 0.024 11.736 ; + END + END rd_out[81] + PIN rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.856 0.024 11.880 ; + END + END rd_out[82] + PIN rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.000 0.024 12.024 ; + END + END rd_out[83] + PIN rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.144 0.024 12.168 ; + END + END rd_out[84] + PIN rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.288 0.024 12.312 ; + END + END rd_out[85] + PIN rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.432 0.024 12.456 ; + END + END rd_out[86] + PIN rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.576 0.024 12.600 ; + END + END rd_out[87] + PIN rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.720 0.024 12.744 ; + END + END rd_out[88] + PIN rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.864 0.024 12.888 ; + END + END rd_out[89] + PIN rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.008 0.024 13.032 ; + END + END rd_out[90] + PIN rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.152 0.024 13.176 ; + END + END rd_out[91] + PIN rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.296 0.024 13.320 ; + END + END rd_out[92] + PIN rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.440 0.024 13.464 ; + END + END rd_out[93] + PIN rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.584 0.024 13.608 ; + END + END rd_out[94] + PIN rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.728 0.024 13.752 ; + END + END rd_out[95] + PIN rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.872 0.024 13.896 ; + END + END rd_out[96] + PIN rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.016 0.024 14.040 ; + END + END rd_out[97] + PIN rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.160 0.024 14.184 ; + END + END rd_out[98] + PIN rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.304 0.024 14.328 ; + END + END rd_out[99] + PIN rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.448 0.024 14.472 ; + END + END rd_out[100] + PIN rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.592 0.024 14.616 ; + END + END rd_out[101] + PIN rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.736 0.024 14.760 ; + END + END rd_out[102] + PIN rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.880 0.024 14.904 ; + END + END rd_out[103] + PIN rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.024 0.024 15.048 ; + END + END rd_out[104] + PIN rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.168 0.024 15.192 ; + END + END rd_out[105] + PIN rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.312 0.024 15.336 ; + END + END rd_out[106] + PIN rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.456 0.024 15.480 ; + END + END rd_out[107] + PIN rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.600 0.024 15.624 ; + END + END rd_out[108] + PIN rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.744 0.024 15.768 ; + END + END rd_out[109] + PIN rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.888 0.024 15.912 ; + END + END rd_out[110] + PIN rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.032 0.024 16.056 ; + END + END rd_out[111] + PIN rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.176 0.024 16.200 ; + END + END rd_out[112] + PIN rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.320 0.024 16.344 ; + END + END rd_out[113] + PIN rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.464 0.024 16.488 ; + END + END rd_out[114] + PIN rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.608 0.024 16.632 ; + END + END rd_out[115] + PIN rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.752 0.024 16.776 ; + END + END rd_out[116] + PIN rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.896 0.024 16.920 ; + END + END rd_out[117] + PIN rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.040 0.024 17.064 ; + END + END rd_out[118] + PIN rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.184 0.024 17.208 ; + END + END rd_out[119] + PIN rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.328 0.024 17.352 ; + END + END rd_out[120] + PIN rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.472 0.024 17.496 ; + END + END rd_out[121] + PIN rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.616 0.024 17.640 ; + END + END rd_out[122] + PIN rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.760 0.024 17.784 ; + END + END rd_out[123] + PIN rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.904 0.024 17.928 ; + END + END rd_out[124] + PIN rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.048 0.024 18.072 ; + END + END rd_out[125] + PIN rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.192 0.024 18.216 ; + END + END rd_out[126] + PIN rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.336 0.024 18.360 ; + END + END rd_out[127] + PIN rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.480 0.024 18.504 ; + END + END rd_out[128] + PIN rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.624 0.024 18.648 ; + END + END rd_out[129] + PIN rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.768 0.024 18.792 ; + END + END rd_out[130] + PIN rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.912 0.024 18.936 ; + END + END rd_out[131] + PIN rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.056 0.024 19.080 ; + END + END rd_out[132] + PIN rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.200 0.024 19.224 ; + END + END rd_out[133] + PIN rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.344 0.024 19.368 ; + END + END rd_out[134] + PIN rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.488 0.024 19.512 ; + END + END rd_out[135] + PIN rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.632 0.024 19.656 ; + END + END rd_out[136] + PIN rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.776 0.024 19.800 ; + END + END rd_out[137] + PIN rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.920 0.024 19.944 ; + END + END rd_out[138] + PIN rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.064 0.024 20.088 ; + END + END rd_out[139] + PIN rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.208 0.024 20.232 ; + END + END rd_out[140] + PIN rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.352 0.024 20.376 ; + END + END rd_out[141] + PIN rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.496 0.024 20.520 ; + END + END rd_out[142] + PIN rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.640 0.024 20.664 ; + END + END rd_out[143] + PIN rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.784 0.024 20.808 ; + END + END rd_out[144] + PIN rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.928 0.024 20.952 ; + END + END rd_out[145] + PIN rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.072 0.024 21.096 ; + END + END rd_out[146] + PIN rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.216 0.024 21.240 ; + END + END rd_out[147] + PIN rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.360 0.024 21.384 ; + END + END rd_out[148] + PIN rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.504 0.024 21.528 ; + END + END rd_out[149] + PIN rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.648 0.024 21.672 ; + END + END rd_out[150] + PIN rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.792 0.024 21.816 ; + END + END rd_out[151] + PIN rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.936 0.024 21.960 ; + END + END rd_out[152] + PIN rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.080 0.024 22.104 ; + END + END rd_out[153] + PIN rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.224 0.024 22.248 ; + END + END rd_out[154] + PIN rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.368 0.024 22.392 ; + END + END rd_out[155] + PIN rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.512 0.024 22.536 ; + END + END rd_out[156] + PIN rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.656 0.024 22.680 ; + END + END rd_out[157] + PIN rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.800 0.024 22.824 ; + END + END rd_out[158] + PIN rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.944 0.024 22.968 ; + END + END rd_out[159] + PIN rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.088 0.024 23.112 ; + END + END rd_out[160] + PIN rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.232 0.024 23.256 ; + END + END rd_out[161] + PIN rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.376 0.024 23.400 ; + END + END rd_out[162] + PIN rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.520 0.024 23.544 ; + END + END rd_out[163] + PIN rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.664 0.024 23.688 ; + END + END rd_out[164] + PIN rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.808 0.024 23.832 ; + END + END rd_out[165] + PIN rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.952 0.024 23.976 ; + END + END rd_out[166] + PIN rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.096 0.024 24.120 ; + END + END rd_out[167] + PIN rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.240 0.024 24.264 ; + END + END rd_out[168] + PIN rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.384 0.024 24.408 ; + END + END rd_out[169] + PIN rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.528 0.024 24.552 ; + END + END rd_out[170] + PIN rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.672 0.024 24.696 ; + END + END rd_out[171] + PIN rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.816 0.024 24.840 ; + END + END rd_out[172] + PIN rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.960 0.024 24.984 ; + END + END rd_out[173] + PIN rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.104 0.024 25.128 ; + END + END rd_out[174] + PIN rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.248 0.024 25.272 ; + END + END rd_out[175] + PIN rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.392 0.024 25.416 ; + END + END rd_out[176] + PIN rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.536 0.024 25.560 ; + END + END rd_out[177] + PIN rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.680 0.024 25.704 ; + END + END rd_out[178] + PIN rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.824 0.024 25.848 ; + END + END rd_out[179] + PIN rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.968 0.024 25.992 ; + END + END rd_out[180] + PIN rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.112 0.024 26.136 ; + END + END rd_out[181] + PIN rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.256 0.024 26.280 ; + END + END rd_out[182] + PIN rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.400 0.024 26.424 ; + END + END rd_out[183] + PIN rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.544 0.024 26.568 ; + END + END rd_out[184] + PIN rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.688 0.024 26.712 ; + END + END rd_out[185] + PIN rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.832 0.024 26.856 ; + END + END rd_out[186] + PIN rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.976 0.024 27.000 ; + END + END rd_out[187] + PIN rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.120 0.024 27.144 ; + END + END rd_out[188] + PIN rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.264 0.024 27.288 ; + END + END rd_out[189] + PIN rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.408 0.024 27.432 ; + END + END rd_out[190] + PIN rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.552 0.024 27.576 ; + END + END rd_out[191] + PIN rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.696 0.024 27.720 ; + END + END rd_out[192] + PIN rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.840 0.024 27.864 ; + END + END rd_out[193] + PIN rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.984 0.024 28.008 ; + END + END rd_out[194] + PIN rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.128 0.024 28.152 ; + END + END rd_out[195] + PIN rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.272 0.024 28.296 ; + END + END rd_out[196] + PIN rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.416 0.024 28.440 ; + END + END rd_out[197] + PIN rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.560 0.024 28.584 ; + END + END rd_out[198] + PIN rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.704 0.024 28.728 ; + END + END rd_out[199] + PIN rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.848 0.024 28.872 ; + END + END rd_out[200] + PIN rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.992 0.024 29.016 ; + END + END rd_out[201] + PIN rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.136 0.024 29.160 ; + END + END rd_out[202] + PIN rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.280 0.024 29.304 ; + END + END rd_out[203] + PIN rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.424 0.024 29.448 ; + END + END rd_out[204] + PIN rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.568 0.024 29.592 ; + END + END rd_out[205] + PIN rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.712 0.024 29.736 ; + END + END rd_out[206] + PIN rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.856 0.024 29.880 ; + END + END rd_out[207] + PIN rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.000 0.024 30.024 ; + END + END rd_out[208] + PIN rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.144 0.024 30.168 ; + END + END rd_out[209] + PIN rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.288 0.024 30.312 ; + END + END rd_out[210] + PIN rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.432 0.024 30.456 ; + END + END rd_out[211] + PIN rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.576 0.024 30.600 ; + END + END rd_out[212] + PIN rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.720 0.024 30.744 ; + END + END rd_out[213] + PIN rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.864 0.024 30.888 ; + END + END rd_out[214] + PIN rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.008 0.024 31.032 ; + END + END rd_out[215] + PIN rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.152 0.024 31.176 ; + END + END rd_out[216] + PIN rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.296 0.024 31.320 ; + END + END rd_out[217] + PIN rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.440 0.024 31.464 ; + END + END rd_out[218] + PIN rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.584 0.024 31.608 ; + END + END rd_out[219] + PIN rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.728 0.024 31.752 ; + END + END rd_out[220] + PIN rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.872 0.024 31.896 ; + END + END rd_out[221] + PIN rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.016 0.024 32.040 ; + END + END rd_out[222] + PIN rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.160 0.024 32.184 ; + END + END rd_out[223] + PIN rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.304 0.024 32.328 ; + END + END rd_out[224] + PIN rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.448 0.024 32.472 ; + END + END rd_out[225] + PIN rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.592 0.024 32.616 ; + END + END rd_out[226] + PIN rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.736 0.024 32.760 ; + END + END rd_out[227] + PIN rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.880 0.024 32.904 ; + END + END rd_out[228] + PIN rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.024 0.024 33.048 ; + END + END rd_out[229] + PIN rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.168 0.024 33.192 ; + END + END rd_out[230] + PIN rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.312 0.024 33.336 ; + END + END rd_out[231] + PIN rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.456 0.024 33.480 ; + END + END rd_out[232] + PIN rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.600 0.024 33.624 ; + END + END rd_out[233] + PIN rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.744 0.024 33.768 ; + END + END rd_out[234] + PIN rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.888 0.024 33.912 ; + END + END rd_out[235] + PIN rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.032 0.024 34.056 ; + END + END rd_out[236] + PIN rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.176 0.024 34.200 ; + END + END rd_out[237] + PIN rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.320 0.024 34.344 ; + END + END rd_out[238] + PIN rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.464 0.024 34.488 ; + END + END rd_out[239] + PIN rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.608 0.024 34.632 ; + END + END rd_out[240] + PIN rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.752 0.024 34.776 ; + END + END rd_out[241] + PIN rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.896 0.024 34.920 ; + END + END rd_out[242] + PIN rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.040 0.024 35.064 ; + END + END rd_out[243] + PIN rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.184 0.024 35.208 ; + END + END rd_out[244] + PIN rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.328 0.024 35.352 ; + END + END rd_out[245] + PIN rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.472 0.024 35.496 ; + END + END rd_out[246] + PIN rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.616 0.024 35.640 ; + END + END rd_out[247] + PIN rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.760 0.024 35.784 ; + END + END rd_out[248] + PIN rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.904 0.024 35.928 ; + END + END rd_out[249] + PIN rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.048 0.024 36.072 ; + END + END rd_out[250] + PIN rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.192 0.024 36.216 ; + END + END rd_out[251] + PIN rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.336 0.024 36.360 ; + END + END rd_out[252] + PIN rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.480 0.024 36.504 ; + END + END rd_out[253] + PIN rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.624 0.024 36.648 ; + END + END rd_out[254] + PIN rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.768 0.024 36.792 ; + END + END rd_out[255] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.744 0.024 39.768 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.888 0.024 39.912 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.032 0.024 40.056 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.176 0.024 40.200 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.320 0.024 40.344 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.464 0.024 40.488 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.608 0.024 40.632 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.752 0.024 40.776 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.896 0.024 40.920 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.040 0.024 41.064 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.184 0.024 41.208 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.328 0.024 41.352 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.472 0.024 41.496 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.616 0.024 41.640 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.760 0.024 41.784 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.904 0.024 41.928 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.048 0.024 42.072 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.192 0.024 42.216 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.336 0.024 42.360 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.480 0.024 42.504 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.624 0.024 42.648 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.768 0.024 42.792 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.912 0.024 42.936 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.056 0.024 43.080 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.200 0.024 43.224 ; + END + END wd_in[24] + PIN wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.344 0.024 43.368 ; + END + END wd_in[25] + PIN wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.488 0.024 43.512 ; + END + END wd_in[26] + PIN wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.632 0.024 43.656 ; + END + END wd_in[27] + PIN wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.776 0.024 43.800 ; + END + END wd_in[28] + PIN wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.920 0.024 43.944 ; + END + END wd_in[29] + PIN wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.064 0.024 44.088 ; + END + END wd_in[30] + PIN wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.208 0.024 44.232 ; + END + END wd_in[31] + PIN wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.352 0.024 44.376 ; + END + END wd_in[32] + PIN wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.496 0.024 44.520 ; + END + END wd_in[33] + PIN wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.640 0.024 44.664 ; + END + END wd_in[34] + PIN wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.784 0.024 44.808 ; + END + END wd_in[35] + PIN wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.928 0.024 44.952 ; + END + END wd_in[36] + PIN wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.072 0.024 45.096 ; + END + END wd_in[37] + PIN wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.216 0.024 45.240 ; + END + END wd_in[38] + PIN wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.360 0.024 45.384 ; + END + END wd_in[39] + PIN wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.504 0.024 45.528 ; + END + END wd_in[40] + PIN wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.648 0.024 45.672 ; + END + END wd_in[41] + PIN wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.792 0.024 45.816 ; + END + END wd_in[42] + PIN wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.936 0.024 45.960 ; + END + END wd_in[43] + PIN wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.080 0.024 46.104 ; + END + END wd_in[44] + PIN wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.224 0.024 46.248 ; + END + END wd_in[45] + PIN wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.368 0.024 46.392 ; + END + END wd_in[46] + PIN wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.512 0.024 46.536 ; + END + END wd_in[47] + PIN wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.656 0.024 46.680 ; + END + END wd_in[48] + PIN wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.800 0.024 46.824 ; + END + END wd_in[49] + PIN wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.944 0.024 46.968 ; + END + END wd_in[50] + PIN wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.088 0.024 47.112 ; + END + END wd_in[51] + PIN wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.232 0.024 47.256 ; + END + END wd_in[52] + PIN wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.376 0.024 47.400 ; + END + END wd_in[53] + PIN wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.520 0.024 47.544 ; + END + END wd_in[54] + PIN wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.664 0.024 47.688 ; + END + END wd_in[55] + PIN wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.808 0.024 47.832 ; + END + END wd_in[56] + PIN wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.952 0.024 47.976 ; + END + END wd_in[57] + PIN wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.096 0.024 48.120 ; + END + END wd_in[58] + PIN wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.240 0.024 48.264 ; + END + END wd_in[59] + PIN wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.384 0.024 48.408 ; + END + END wd_in[60] + PIN wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.528 0.024 48.552 ; + END + END wd_in[61] + PIN wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.672 0.024 48.696 ; + END + END wd_in[62] + PIN wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.816 0.024 48.840 ; + END + END wd_in[63] + PIN wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.960 0.024 48.984 ; + END + END wd_in[64] + PIN wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.104 0.024 49.128 ; + END + END wd_in[65] + PIN wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.248 0.024 49.272 ; + END + END wd_in[66] + PIN wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.392 0.024 49.416 ; + END + END wd_in[67] + PIN wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.536 0.024 49.560 ; + END + END wd_in[68] + PIN wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.680 0.024 49.704 ; + END + END wd_in[69] + PIN wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.824 0.024 49.848 ; + END + END wd_in[70] + PIN wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.968 0.024 49.992 ; + END + END wd_in[71] + PIN wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.112 0.024 50.136 ; + END + END wd_in[72] + PIN wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.256 0.024 50.280 ; + END + END wd_in[73] + PIN wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.400 0.024 50.424 ; + END + END wd_in[74] + PIN wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.544 0.024 50.568 ; + END + END wd_in[75] + PIN wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.688 0.024 50.712 ; + END + END wd_in[76] + PIN wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.832 0.024 50.856 ; + END + END wd_in[77] + PIN wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.976 0.024 51.000 ; + END + END wd_in[78] + PIN wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.120 0.024 51.144 ; + END + END wd_in[79] + PIN wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.264 0.024 51.288 ; + END + END wd_in[80] + PIN wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.408 0.024 51.432 ; + END + END wd_in[81] + PIN wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.552 0.024 51.576 ; + END + END wd_in[82] + PIN wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.696 0.024 51.720 ; + END + END wd_in[83] + PIN wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.840 0.024 51.864 ; + END + END wd_in[84] + PIN wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.984 0.024 52.008 ; + END + END wd_in[85] + PIN wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.128 0.024 52.152 ; + END + END wd_in[86] + PIN wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.272 0.024 52.296 ; + END + END wd_in[87] + PIN wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.416 0.024 52.440 ; + END + END wd_in[88] + PIN wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.560 0.024 52.584 ; + END + END wd_in[89] + PIN wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.704 0.024 52.728 ; + END + END wd_in[90] + PIN wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.848 0.024 52.872 ; + END + END wd_in[91] + PIN wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.992 0.024 53.016 ; + END + END wd_in[92] + PIN wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.136 0.024 53.160 ; + END + END wd_in[93] + PIN wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.280 0.024 53.304 ; + END + END wd_in[94] + PIN wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.424 0.024 53.448 ; + END + END wd_in[95] + PIN wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.568 0.024 53.592 ; + END + END wd_in[96] + PIN wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.712 0.024 53.736 ; + END + END wd_in[97] + PIN wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.856 0.024 53.880 ; + END + END wd_in[98] + PIN wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.000 0.024 54.024 ; + END + END wd_in[99] + PIN wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.144 0.024 54.168 ; + END + END wd_in[100] + PIN wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.288 0.024 54.312 ; + END + END wd_in[101] + PIN wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.432 0.024 54.456 ; + END + END wd_in[102] + PIN wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.576 0.024 54.600 ; + END + END wd_in[103] + PIN wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.720 0.024 54.744 ; + END + END wd_in[104] + PIN wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.864 0.024 54.888 ; + END + END wd_in[105] + PIN wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.008 0.024 55.032 ; + END + END wd_in[106] + PIN wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.152 0.024 55.176 ; + END + END wd_in[107] + PIN wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.296 0.024 55.320 ; + END + END wd_in[108] + PIN wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.440 0.024 55.464 ; + END + END wd_in[109] + PIN wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.584 0.024 55.608 ; + END + END wd_in[110] + PIN wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.728 0.024 55.752 ; + END + END wd_in[111] + PIN wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.872 0.024 55.896 ; + END + END wd_in[112] + PIN wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.016 0.024 56.040 ; + END + END wd_in[113] + PIN wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.160 0.024 56.184 ; + END + END wd_in[114] + PIN wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.304 0.024 56.328 ; + END + END wd_in[115] + PIN wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.448 0.024 56.472 ; + END + END wd_in[116] + PIN wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.592 0.024 56.616 ; + END + END wd_in[117] + PIN wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.736 0.024 56.760 ; + END + END wd_in[118] + PIN wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.880 0.024 56.904 ; + END + END wd_in[119] + PIN wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.024 0.024 57.048 ; + END + END wd_in[120] + PIN wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.168 0.024 57.192 ; + END + END wd_in[121] + PIN wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.312 0.024 57.336 ; + END + END wd_in[122] + PIN wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.456 0.024 57.480 ; + END + END wd_in[123] + PIN wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.600 0.024 57.624 ; + END + END wd_in[124] + PIN wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.744 0.024 57.768 ; + END + END wd_in[125] + PIN wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.888 0.024 57.912 ; + END + END wd_in[126] + PIN wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.032 0.024 58.056 ; + END + END wd_in[127] + PIN wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.176 0.024 58.200 ; + END + END wd_in[128] + PIN wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.320 0.024 58.344 ; + END + END wd_in[129] + PIN wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.464 0.024 58.488 ; + END + END wd_in[130] + PIN wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.608 0.024 58.632 ; + END + END wd_in[131] + PIN wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.752 0.024 58.776 ; + END + END wd_in[132] + PIN wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.896 0.024 58.920 ; + END + END wd_in[133] + PIN wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.040 0.024 59.064 ; + END + END wd_in[134] + PIN wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.184 0.024 59.208 ; + END + END wd_in[135] + PIN wd_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.328 0.024 59.352 ; + END + END wd_in[136] + PIN wd_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.472 0.024 59.496 ; + END + END wd_in[137] + PIN wd_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.616 0.024 59.640 ; + END + END wd_in[138] + PIN wd_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.760 0.024 59.784 ; + END + END wd_in[139] + PIN wd_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.904 0.024 59.928 ; + END + END wd_in[140] + PIN wd_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.048 0.024 60.072 ; + END + END wd_in[141] + PIN wd_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.192 0.024 60.216 ; + END + END wd_in[142] + PIN wd_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.336 0.024 60.360 ; + END + END wd_in[143] + PIN wd_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.480 0.024 60.504 ; + END + END wd_in[144] + PIN wd_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.624 0.024 60.648 ; + END + END wd_in[145] + PIN wd_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.768 0.024 60.792 ; + END + END wd_in[146] + PIN wd_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.912 0.024 60.936 ; + END + END wd_in[147] + PIN wd_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.056 0.024 61.080 ; + END + END wd_in[148] + PIN wd_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.200 0.024 61.224 ; + END + END wd_in[149] + PIN wd_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.344 0.024 61.368 ; + END + END wd_in[150] + PIN wd_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.488 0.024 61.512 ; + END + END wd_in[151] + PIN wd_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.632 0.024 61.656 ; + END + END wd_in[152] + PIN wd_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.776 0.024 61.800 ; + END + END wd_in[153] + PIN wd_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.920 0.024 61.944 ; + END + END wd_in[154] + PIN wd_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.064 0.024 62.088 ; + END + END wd_in[155] + PIN wd_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.208 0.024 62.232 ; + END + END wd_in[156] + PIN wd_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.352 0.024 62.376 ; + END + END wd_in[157] + PIN wd_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.496 0.024 62.520 ; + END + END wd_in[158] + PIN wd_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.640 0.024 62.664 ; + END + END wd_in[159] + PIN wd_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.784 0.024 62.808 ; + END + END wd_in[160] + PIN wd_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.928 0.024 62.952 ; + END + END wd_in[161] + PIN wd_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.072 0.024 63.096 ; + END + END wd_in[162] + PIN wd_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.216 0.024 63.240 ; + END + END wd_in[163] + PIN wd_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.360 0.024 63.384 ; + END + END wd_in[164] + PIN wd_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.504 0.024 63.528 ; + END + END wd_in[165] + PIN wd_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.648 0.024 63.672 ; + END + END wd_in[166] + PIN wd_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.792 0.024 63.816 ; + END + END wd_in[167] + PIN wd_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.936 0.024 63.960 ; + END + END wd_in[168] + PIN wd_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.080 0.024 64.104 ; + END + END wd_in[169] + PIN wd_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.224 0.024 64.248 ; + END + END wd_in[170] + PIN wd_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.368 0.024 64.392 ; + END + END wd_in[171] + PIN wd_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.512 0.024 64.536 ; + END + END wd_in[172] + PIN wd_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.656 0.024 64.680 ; + END + END wd_in[173] + PIN wd_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.800 0.024 64.824 ; + END + END wd_in[174] + PIN wd_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.944 0.024 64.968 ; + END + END wd_in[175] + PIN wd_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.088 0.024 65.112 ; + END + END wd_in[176] + PIN wd_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.232 0.024 65.256 ; + END + END wd_in[177] + PIN wd_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.376 0.024 65.400 ; + END + END wd_in[178] + PIN wd_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.520 0.024 65.544 ; + END + END wd_in[179] + PIN wd_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.664 0.024 65.688 ; + END + END wd_in[180] + PIN wd_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.808 0.024 65.832 ; + END + END wd_in[181] + PIN wd_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.952 0.024 65.976 ; + END + END wd_in[182] + PIN wd_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.096 0.024 66.120 ; + END + END wd_in[183] + PIN wd_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.240 0.024 66.264 ; + END + END wd_in[184] + PIN wd_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.384 0.024 66.408 ; + END + END wd_in[185] + PIN wd_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.528 0.024 66.552 ; + END + END wd_in[186] + PIN wd_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.672 0.024 66.696 ; + END + END wd_in[187] + PIN wd_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.816 0.024 66.840 ; + END + END wd_in[188] + PIN wd_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.960 0.024 66.984 ; + END + END wd_in[189] + PIN wd_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.104 0.024 67.128 ; + END + END wd_in[190] + PIN wd_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.248 0.024 67.272 ; + END + END wd_in[191] + PIN wd_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.392 0.024 67.416 ; + END + END wd_in[192] + PIN wd_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.536 0.024 67.560 ; + END + END wd_in[193] + PIN wd_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.680 0.024 67.704 ; + END + END wd_in[194] + PIN wd_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.824 0.024 67.848 ; + END + END wd_in[195] + PIN wd_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.968 0.024 67.992 ; + END + END wd_in[196] + PIN wd_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.112 0.024 68.136 ; + END + END wd_in[197] + PIN wd_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.256 0.024 68.280 ; + END + END wd_in[198] + PIN wd_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.400 0.024 68.424 ; + END + END wd_in[199] + PIN wd_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.544 0.024 68.568 ; + END + END wd_in[200] + PIN wd_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.688 0.024 68.712 ; + END + END wd_in[201] + PIN wd_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.832 0.024 68.856 ; + END + END wd_in[202] + PIN wd_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.976 0.024 69.000 ; + END + END wd_in[203] + PIN wd_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.120 0.024 69.144 ; + END + END wd_in[204] + PIN wd_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.264 0.024 69.288 ; + END + END wd_in[205] + PIN wd_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.408 0.024 69.432 ; + END + END wd_in[206] + PIN wd_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.552 0.024 69.576 ; + END + END wd_in[207] + PIN wd_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.696 0.024 69.720 ; + END + END wd_in[208] + PIN wd_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.840 0.024 69.864 ; + END + END wd_in[209] + PIN wd_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.984 0.024 70.008 ; + END + END wd_in[210] + PIN wd_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.128 0.024 70.152 ; + END + END wd_in[211] + PIN wd_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.272 0.024 70.296 ; + END + END wd_in[212] + PIN wd_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.416 0.024 70.440 ; + END + END wd_in[213] + PIN wd_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.560 0.024 70.584 ; + END + END wd_in[214] + PIN wd_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.704 0.024 70.728 ; + END + END wd_in[215] + PIN wd_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.848 0.024 70.872 ; + END + END wd_in[216] + PIN wd_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.992 0.024 71.016 ; + END + END wd_in[217] + PIN wd_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.136 0.024 71.160 ; + END + END wd_in[218] + PIN wd_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.280 0.024 71.304 ; + END + END wd_in[219] + PIN wd_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.424 0.024 71.448 ; + END + END wd_in[220] + PIN wd_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.568 0.024 71.592 ; + END + END wd_in[221] + PIN wd_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.712 0.024 71.736 ; + END + END wd_in[222] + PIN wd_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.856 0.024 71.880 ; + END + END wd_in[223] + PIN wd_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.000 0.024 72.024 ; + END + END wd_in[224] + PIN wd_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.144 0.024 72.168 ; + END + END wd_in[225] + PIN wd_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.288 0.024 72.312 ; + END + END wd_in[226] + PIN wd_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.432 0.024 72.456 ; + END + END wd_in[227] + PIN wd_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.576 0.024 72.600 ; + END + END wd_in[228] + PIN wd_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.720 0.024 72.744 ; + END + END wd_in[229] + PIN wd_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.864 0.024 72.888 ; + END + END wd_in[230] + PIN wd_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.008 0.024 73.032 ; + END + END wd_in[231] + PIN wd_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.152 0.024 73.176 ; + END + END wd_in[232] + PIN wd_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.296 0.024 73.320 ; + END + END wd_in[233] + PIN wd_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.440 0.024 73.464 ; + END + END wd_in[234] + PIN wd_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.584 0.024 73.608 ; + END + END wd_in[235] + PIN wd_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.728 0.024 73.752 ; + END + END wd_in[236] + PIN wd_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.872 0.024 73.896 ; + END + END wd_in[237] + PIN wd_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.016 0.024 74.040 ; + END + END wd_in[238] + PIN wd_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.160 0.024 74.184 ; + END + END wd_in[239] + PIN wd_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.304 0.024 74.328 ; + END + END wd_in[240] + PIN wd_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.448 0.024 74.472 ; + END + END wd_in[241] + PIN wd_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.592 0.024 74.616 ; + END + END wd_in[242] + PIN wd_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.736 0.024 74.760 ; + END + END wd_in[243] + PIN wd_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.880 0.024 74.904 ; + END + END wd_in[244] + PIN wd_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.024 0.024 75.048 ; + END + END wd_in[245] + PIN wd_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.168 0.024 75.192 ; + END + END wd_in[246] + PIN wd_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.312 0.024 75.336 ; + END + END wd_in[247] + PIN wd_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.456 0.024 75.480 ; + END + END wd_in[248] + PIN wd_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.600 0.024 75.624 ; + END + END wd_in[249] + PIN wd_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.744 0.024 75.768 ; + END + END wd_in[250] + PIN wd_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.888 0.024 75.912 ; + END + END wd_in[251] + PIN wd_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.032 0.024 76.056 ; + END + END wd_in[252] + PIN wd_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.176 0.024 76.200 ; + END + END wd_in[253] + PIN wd_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.320 0.024 76.344 ; + END + END wd_in[254] + PIN wd_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.464 0.024 76.488 ; + END + END wd_in[255] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.440 0.024 79.464 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.584 0.024 79.608 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.728 0.024 79.752 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.872 0.024 79.896 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.016 0.024 80.040 ; + END + END addr_in[4] + PIN addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.160 0.024 80.184 ; + END + END addr_in[5] + PIN addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.304 0.024 80.328 ; + END + END addr_in[6] + PIN addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.448 0.024 80.472 ; + END + END addr_in[7] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.424 0.024 83.448 ; + END + END we_in + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.568 0.024 83.592 ; + END + END ce_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.712 0.024 83.736 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 33.202 0.096 ; + RECT 0.048 0.768 33.202 0.864 ; + RECT 0.048 1.536 33.202 1.632 ; + RECT 0.048 2.304 33.202 2.400 ; + RECT 0.048 3.072 33.202 3.168 ; + RECT 0.048 3.840 33.202 3.936 ; + RECT 0.048 4.608 33.202 4.704 ; + RECT 0.048 5.376 33.202 5.472 ; + RECT 0.048 6.144 33.202 6.240 ; + RECT 0.048 6.912 33.202 7.008 ; + RECT 0.048 7.680 33.202 7.776 ; + RECT 0.048 8.448 33.202 8.544 ; + RECT 0.048 9.216 33.202 9.312 ; + RECT 0.048 9.984 33.202 10.080 ; + RECT 0.048 10.752 33.202 10.848 ; + RECT 0.048 11.520 33.202 11.616 ; + RECT 0.048 12.288 33.202 12.384 ; + RECT 0.048 13.056 33.202 13.152 ; + RECT 0.048 13.824 33.202 13.920 ; + RECT 0.048 14.592 33.202 14.688 ; + RECT 0.048 15.360 33.202 15.456 ; + RECT 0.048 16.128 33.202 16.224 ; + RECT 0.048 16.896 33.202 16.992 ; + RECT 0.048 17.664 33.202 17.760 ; + RECT 0.048 18.432 33.202 18.528 ; + RECT 0.048 19.200 33.202 19.296 ; + RECT 0.048 19.968 33.202 20.064 ; + RECT 0.048 20.736 33.202 20.832 ; + RECT 0.048 21.504 33.202 21.600 ; + RECT 0.048 22.272 33.202 22.368 ; + RECT 0.048 23.040 33.202 23.136 ; + RECT 0.048 23.808 33.202 23.904 ; + RECT 0.048 24.576 33.202 24.672 ; + RECT 0.048 25.344 33.202 25.440 ; + RECT 0.048 26.112 33.202 26.208 ; + RECT 0.048 26.880 33.202 26.976 ; + RECT 0.048 27.648 33.202 27.744 ; + RECT 0.048 28.416 33.202 28.512 ; + RECT 0.048 29.184 33.202 29.280 ; + RECT 0.048 29.952 33.202 30.048 ; + RECT 0.048 30.720 33.202 30.816 ; + RECT 0.048 31.488 33.202 31.584 ; + RECT 0.048 32.256 33.202 32.352 ; + RECT 0.048 33.024 33.202 33.120 ; + RECT 0.048 33.792 33.202 33.888 ; + RECT 0.048 34.560 33.202 34.656 ; + RECT 0.048 35.328 33.202 35.424 ; + RECT 0.048 36.096 33.202 36.192 ; + RECT 0.048 36.864 33.202 36.960 ; + RECT 0.048 37.632 33.202 37.728 ; + RECT 0.048 38.400 33.202 38.496 ; + RECT 0.048 39.168 33.202 39.264 ; + RECT 0.048 39.936 33.202 40.032 ; + RECT 0.048 40.704 33.202 40.800 ; + RECT 0.048 41.472 33.202 41.568 ; + RECT 0.048 42.240 33.202 42.336 ; + RECT 0.048 43.008 33.202 43.104 ; + RECT 0.048 43.776 33.202 43.872 ; + RECT 0.048 44.544 33.202 44.640 ; + RECT 0.048 45.312 33.202 45.408 ; + RECT 0.048 46.080 33.202 46.176 ; + RECT 0.048 46.848 33.202 46.944 ; + RECT 0.048 47.616 33.202 47.712 ; + RECT 0.048 48.384 33.202 48.480 ; + RECT 0.048 49.152 33.202 49.248 ; + RECT 0.048 49.920 33.202 50.016 ; + RECT 0.048 50.688 33.202 50.784 ; + RECT 0.048 51.456 33.202 51.552 ; + RECT 0.048 52.224 33.202 52.320 ; + RECT 0.048 52.992 33.202 53.088 ; + RECT 0.048 53.760 33.202 53.856 ; + RECT 0.048 54.528 33.202 54.624 ; + RECT 0.048 55.296 33.202 55.392 ; + RECT 0.048 56.064 33.202 56.160 ; + RECT 0.048 56.832 33.202 56.928 ; + RECT 0.048 57.600 33.202 57.696 ; + RECT 0.048 58.368 33.202 58.464 ; + RECT 0.048 59.136 33.202 59.232 ; + RECT 0.048 59.904 33.202 60.000 ; + RECT 0.048 60.672 33.202 60.768 ; + RECT 0.048 61.440 33.202 61.536 ; + RECT 0.048 62.208 33.202 62.304 ; + RECT 0.048 62.976 33.202 63.072 ; + RECT 0.048 63.744 33.202 63.840 ; + RECT 0.048 64.512 33.202 64.608 ; + RECT 0.048 65.280 33.202 65.376 ; + RECT 0.048 66.048 33.202 66.144 ; + RECT 0.048 66.816 33.202 66.912 ; + RECT 0.048 67.584 33.202 67.680 ; + RECT 0.048 68.352 33.202 68.448 ; + RECT 0.048 69.120 33.202 69.216 ; + RECT 0.048 69.888 33.202 69.984 ; + RECT 0.048 70.656 33.202 70.752 ; + RECT 0.048 71.424 33.202 71.520 ; + RECT 0.048 72.192 33.202 72.288 ; + RECT 0.048 72.960 33.202 73.056 ; + RECT 0.048 73.728 33.202 73.824 ; + RECT 0.048 74.496 33.202 74.592 ; + RECT 0.048 75.264 33.202 75.360 ; + RECT 0.048 76.032 33.202 76.128 ; + RECT 0.048 76.800 33.202 76.896 ; + RECT 0.048 77.568 33.202 77.664 ; + RECT 0.048 78.336 33.202 78.432 ; + RECT 0.048 79.104 33.202 79.200 ; + RECT 0.048 79.872 33.202 79.968 ; + RECT 0.048 80.640 33.202 80.736 ; + RECT 0.048 81.408 33.202 81.504 ; + RECT 0.048 82.176 33.202 82.272 ; + RECT 0.048 82.944 33.202 83.040 ; + RECT 0.048 83.712 33.202 83.808 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 33.202 0.480 ; + RECT 0.048 1.152 33.202 1.248 ; + RECT 0.048 1.920 33.202 2.016 ; + RECT 0.048 2.688 33.202 2.784 ; + RECT 0.048 3.456 33.202 3.552 ; + RECT 0.048 4.224 33.202 4.320 ; + RECT 0.048 4.992 33.202 5.088 ; + RECT 0.048 5.760 33.202 5.856 ; + RECT 0.048 6.528 33.202 6.624 ; + RECT 0.048 7.296 33.202 7.392 ; + RECT 0.048 8.064 33.202 8.160 ; + RECT 0.048 8.832 33.202 8.928 ; + RECT 0.048 9.600 33.202 9.696 ; + RECT 0.048 10.368 33.202 10.464 ; + RECT 0.048 11.136 33.202 11.232 ; + RECT 0.048 11.904 33.202 12.000 ; + RECT 0.048 12.672 33.202 12.768 ; + RECT 0.048 13.440 33.202 13.536 ; + RECT 0.048 14.208 33.202 14.304 ; + RECT 0.048 14.976 33.202 15.072 ; + RECT 0.048 15.744 33.202 15.840 ; + RECT 0.048 16.512 33.202 16.608 ; + RECT 0.048 17.280 33.202 17.376 ; + RECT 0.048 18.048 33.202 18.144 ; + RECT 0.048 18.816 33.202 18.912 ; + RECT 0.048 19.584 33.202 19.680 ; + RECT 0.048 20.352 33.202 20.448 ; + RECT 0.048 21.120 33.202 21.216 ; + RECT 0.048 21.888 33.202 21.984 ; + RECT 0.048 22.656 33.202 22.752 ; + RECT 0.048 23.424 33.202 23.520 ; + RECT 0.048 24.192 33.202 24.288 ; + RECT 0.048 24.960 33.202 25.056 ; + RECT 0.048 25.728 33.202 25.824 ; + RECT 0.048 26.496 33.202 26.592 ; + RECT 0.048 27.264 33.202 27.360 ; + RECT 0.048 28.032 33.202 28.128 ; + RECT 0.048 28.800 33.202 28.896 ; + RECT 0.048 29.568 33.202 29.664 ; + RECT 0.048 30.336 33.202 30.432 ; + RECT 0.048 31.104 33.202 31.200 ; + RECT 0.048 31.872 33.202 31.968 ; + RECT 0.048 32.640 33.202 32.736 ; + RECT 0.048 33.408 33.202 33.504 ; + RECT 0.048 34.176 33.202 34.272 ; + RECT 0.048 34.944 33.202 35.040 ; + RECT 0.048 35.712 33.202 35.808 ; + RECT 0.048 36.480 33.202 36.576 ; + RECT 0.048 37.248 33.202 37.344 ; + RECT 0.048 38.016 33.202 38.112 ; + RECT 0.048 38.784 33.202 38.880 ; + RECT 0.048 39.552 33.202 39.648 ; + RECT 0.048 40.320 33.202 40.416 ; + RECT 0.048 41.088 33.202 41.184 ; + RECT 0.048 41.856 33.202 41.952 ; + RECT 0.048 42.624 33.202 42.720 ; + RECT 0.048 43.392 33.202 43.488 ; + RECT 0.048 44.160 33.202 44.256 ; + RECT 0.048 44.928 33.202 45.024 ; + RECT 0.048 45.696 33.202 45.792 ; + RECT 0.048 46.464 33.202 46.560 ; + RECT 0.048 47.232 33.202 47.328 ; + RECT 0.048 48.000 33.202 48.096 ; + RECT 0.048 48.768 33.202 48.864 ; + RECT 0.048 49.536 33.202 49.632 ; + RECT 0.048 50.304 33.202 50.400 ; + RECT 0.048 51.072 33.202 51.168 ; + RECT 0.048 51.840 33.202 51.936 ; + RECT 0.048 52.608 33.202 52.704 ; + RECT 0.048 53.376 33.202 53.472 ; + RECT 0.048 54.144 33.202 54.240 ; + RECT 0.048 54.912 33.202 55.008 ; + RECT 0.048 55.680 33.202 55.776 ; + RECT 0.048 56.448 33.202 56.544 ; + RECT 0.048 57.216 33.202 57.312 ; + RECT 0.048 57.984 33.202 58.080 ; + RECT 0.048 58.752 33.202 58.848 ; + RECT 0.048 59.520 33.202 59.616 ; + RECT 0.048 60.288 33.202 60.384 ; + RECT 0.048 61.056 33.202 61.152 ; + RECT 0.048 61.824 33.202 61.920 ; + RECT 0.048 62.592 33.202 62.688 ; + RECT 0.048 63.360 33.202 63.456 ; + RECT 0.048 64.128 33.202 64.224 ; + RECT 0.048 64.896 33.202 64.992 ; + RECT 0.048 65.664 33.202 65.760 ; + RECT 0.048 66.432 33.202 66.528 ; + RECT 0.048 67.200 33.202 67.296 ; + RECT 0.048 67.968 33.202 68.064 ; + RECT 0.048 68.736 33.202 68.832 ; + RECT 0.048 69.504 33.202 69.600 ; + RECT 0.048 70.272 33.202 70.368 ; + RECT 0.048 71.040 33.202 71.136 ; + RECT 0.048 71.808 33.202 71.904 ; + RECT 0.048 72.576 33.202 72.672 ; + RECT 0.048 73.344 33.202 73.440 ; + RECT 0.048 74.112 33.202 74.208 ; + RECT 0.048 74.880 33.202 74.976 ; + RECT 0.048 75.648 33.202 75.744 ; + RECT 0.048 76.416 33.202 76.512 ; + RECT 0.048 77.184 33.202 77.280 ; + RECT 0.048 77.952 33.202 78.048 ; + RECT 0.048 78.720 33.202 78.816 ; + RECT 0.048 79.488 33.202 79.584 ; + RECT 0.048 80.256 33.202 80.352 ; + RECT 0.048 81.024 33.202 81.120 ; + RECT 0.048 81.792 33.202 81.888 ; + RECT 0.048 82.560 33.202 82.656 ; + RECT 0.048 83.328 33.202 83.424 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 33.250 84.000 ; + LAYER M2 ; + RECT 0 0 33.250 84.000 ; + LAYER M3 ; + RECT 0 0 33.250 84.000 ; + LAYER M4 ; + RECT 0 0 33.250 84.000 ; + END +END fakeram7_256x256 + +END LIBRARY diff --git a/flow/platforms/asap7/lef/fakeram7_64x25.lef b/flow/platforms/asap7/lef/fakeram7_64x25.lef new file mode 100644 index 0000000000..70cb255428 --- /dev/null +++ b/flow/platforms/asap7/lef/fakeram7_64x25.lef @@ -0,0 +1,590 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO fakeram7_64x25 + PROPERTY width 25 ; + PROPERTY depth 64 ; + PROPERTY banks 4 ; + FOREIGN fakeram7_64x25 0 0 ; + SYMMETRY X Y R90 ; + SIZE 13.110 BY 6.000 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.144 0.024 0.168 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.240 0.024 0.264 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.024 0.360 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.432 0.024 0.456 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.528 0.024 0.552 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.024 0.648 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.720 0.024 0.744 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.816 0.024 0.840 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.024 0.936 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.008 0.024 1.032 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.104 0.024 1.128 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.024 1.224 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.296 0.024 1.320 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.392 0.024 1.416 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.024 1.512 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.584 0.024 1.608 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.680 0.024 1.704 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.776 0.024 1.800 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.872 0.024 1.896 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.968 0.024 1.992 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.064 0.024 2.088 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.160 0.024 2.184 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.256 0.024 2.280 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.024 2.376 ; + END + END rd_out[24] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.024 2.520 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.592 0.024 2.616 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.688 0.024 2.712 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.024 2.808 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.880 0.024 2.904 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.976 0.024 3.000 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.024 3.096 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.168 0.024 3.192 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.264 0.024 3.288 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.024 3.384 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.456 0.024 3.480 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.552 0.024 3.576 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.648 0.024 3.672 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.744 0.024 3.768 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.840 0.024 3.864 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.936 0.024 3.960 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.032 0.024 4.056 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.128 0.024 4.152 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.224 0.024 4.248 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.320 0.024 4.344 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.416 0.024 4.440 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.512 0.024 4.536 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.608 0.024 4.632 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.704 0.024 4.728 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.024 4.824 ; + END + END wd_in[24] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.944 0.024 4.968 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.040 0.024 5.064 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.136 0.024 5.160 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.232 0.024 5.256 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.328 0.024 5.352 ; + END + END addr_in[4] + PIN addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.424 0.024 5.448 ; + END + END addr_in[5] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.568 0.024 5.592 ; + END + END we_in + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.664 0.024 5.688 ; + END + END ce_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.760 0.024 5.784 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 13.062 0.096 ; + RECT 0.048 0.768 13.062 0.864 ; + RECT 0.048 1.536 13.062 1.632 ; + RECT 0.048 2.304 13.062 2.400 ; + RECT 0.048 3.072 13.062 3.168 ; + RECT 0.048 3.840 13.062 3.936 ; + RECT 0.048 4.608 13.062 4.704 ; + RECT 0.048 5.376 13.062 5.472 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 13.062 0.480 ; + RECT 0.048 1.152 13.062 1.248 ; + RECT 0.048 1.920 13.062 2.016 ; + RECT 0.048 2.688 13.062 2.784 ; + RECT 0.048 3.456 13.062 3.552 ; + RECT 0.048 4.224 13.062 4.320 ; + RECT 0.048 4.992 13.062 5.088 ; + RECT 0.048 5.760 13.062 5.856 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 13.110 6.000 ; + LAYER M2 ; + RECT 0 0 13.110 6.000 ; + LAYER M3 ; + RECT 0 0 13.110 6.000 ; + LAYER M4 ; + RECT 0 0 13.110 6.000 ; + END +END fakeram7_64x25 + +END LIBRARY diff --git a/flow/platforms/asap7/lef/fakeram7_64x256.lef b/flow/platforms/asap7/lef/fakeram7_64x256.lef new file mode 100644 index 0000000000..d1b8f95fee --- /dev/null +++ b/flow/platforms/asap7/lef/fakeram7_64x256.lef @@ -0,0 +1,4854 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO fakeram7_64x256 + PROPERTY width 256 ; + PROPERTY depth 64 ; + PROPERTY banks 1 ; + FOREIGN fakeram7_64x256 0 0 ; + SYMMETRY X Y R90 ; + SIZE 33.250 BY 46.800 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.036 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.096 0.036 0.120 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.144 0.036 0.168 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.192 0.036 0.216 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.240 0.036 0.264 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.288 0.036 0.312 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.036 0.360 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.384 0.036 0.408 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.432 0.036 0.456 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.480 0.036 0.504 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.528 0.036 0.552 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.576 0.036 0.600 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.036 0.648 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.672 0.036 0.696 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.720 0.036 0.744 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.768 0.036 0.792 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.816 0.036 0.840 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.864 0.036 0.888 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.036 0.936 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.960 0.036 0.984 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.008 0.036 1.032 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.056 0.036 1.080 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.104 0.036 1.128 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.152 0.036 1.176 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.036 1.224 ; + END + END rd_out[24] + PIN rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.248 0.036 1.272 ; + END + END rd_out[25] + PIN rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.296 0.036 1.320 ; + END + END rd_out[26] + PIN rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.344 0.036 1.368 ; + END + END rd_out[27] + PIN rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.392 0.036 1.416 ; + END + END rd_out[28] + PIN rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.440 0.036 1.464 ; + END + END rd_out[29] + PIN rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.036 1.512 ; + END + END rd_out[30] + PIN rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.536 0.036 1.560 ; + END + END rd_out[31] + PIN rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.584 0.036 1.608 ; + END + END rd_out[32] + PIN rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.632 0.036 1.656 ; + END + END rd_out[33] + PIN rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.680 0.036 1.704 ; + END + END rd_out[34] + PIN rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.728 0.036 1.752 ; + END + END rd_out[35] + PIN rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.776 0.036 1.800 ; + END + END rd_out[36] + PIN rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.824 0.036 1.848 ; + END + END rd_out[37] + PIN rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.872 0.036 1.896 ; + END + END rd_out[38] + PIN rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.920 0.036 1.944 ; + END + END rd_out[39] + PIN rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.968 0.036 1.992 ; + END + END rd_out[40] + PIN rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.016 0.036 2.040 ; + END + END rd_out[41] + PIN rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.064 0.036 2.088 ; + END + END rd_out[42] + PIN rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.112 0.036 2.136 ; + END + END rd_out[43] + PIN rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.160 0.036 2.184 ; + END + END rd_out[44] + PIN rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.208 0.036 2.232 ; + END + END rd_out[45] + PIN rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.256 0.036 2.280 ; + END + END rd_out[46] + PIN rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.304 0.036 2.328 ; + END + END rd_out[47] + PIN rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.036 2.376 ; + END + END rd_out[48] + PIN rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.400 0.036 2.424 ; + END + END rd_out[49] + PIN rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.448 0.036 2.472 ; + END + END rd_out[50] + PIN rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.036 2.520 ; + END + END rd_out[51] + PIN rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.544 0.036 2.568 ; + END + END rd_out[52] + PIN rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.592 0.036 2.616 ; + END + END rd_out[53] + PIN rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.640 0.036 2.664 ; + END + END rd_out[54] + PIN rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.688 0.036 2.712 ; + END + END rd_out[55] + PIN rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.736 0.036 2.760 ; + END + END rd_out[56] + PIN rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.036 2.808 ; + END + END rd_out[57] + PIN rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.832 0.036 2.856 ; + END + END rd_out[58] + PIN rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.880 0.036 2.904 ; + END + END rd_out[59] + PIN rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.036 2.952 ; + END + END rd_out[60] + PIN rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.976 0.036 3.000 ; + END + END rd_out[61] + PIN rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.024 0.036 3.048 ; + END + END rd_out[62] + PIN rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.036 3.096 ; + END + END rd_out[63] + PIN rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.120 0.036 3.144 ; + END + END rd_out[64] + PIN rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.168 0.036 3.192 ; + END + END rd_out[65] + PIN rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.036 3.240 ; + END + END rd_out[66] + PIN rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.264 0.036 3.288 ; + END + END rd_out[67] + PIN rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.312 0.036 3.336 ; + END + END rd_out[68] + PIN rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.036 3.384 ; + END + END rd_out[69] + PIN rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.408 0.036 3.432 ; + END + END rd_out[70] + PIN rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.456 0.036 3.480 ; + END + END rd_out[71] + PIN rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.504 0.036 3.528 ; + END + END rd_out[72] + PIN rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.552 0.036 3.576 ; + END + END rd_out[73] + PIN rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.600 0.036 3.624 ; + END + END rd_out[74] + PIN rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.648 0.036 3.672 ; + END + END rd_out[75] + PIN rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.696 0.036 3.720 ; + END + END rd_out[76] + PIN rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.744 0.036 3.768 ; + END + END rd_out[77] + PIN rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.792 0.036 3.816 ; + END + END rd_out[78] + PIN rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.840 0.036 3.864 ; + END + END rd_out[79] + PIN rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.888 0.036 3.912 ; + END + END rd_out[80] + PIN rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.936 0.036 3.960 ; + END + END rd_out[81] + PIN rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.984 0.036 4.008 ; + END + END rd_out[82] + PIN rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.032 0.036 4.056 ; + END + END rd_out[83] + PIN rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.080 0.036 4.104 ; + END + END rd_out[84] + PIN rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.128 0.036 4.152 ; + END + END rd_out[85] + PIN rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.176 0.036 4.200 ; + END + END rd_out[86] + PIN rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.224 0.036 4.248 ; + END + END rd_out[87] + PIN rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.272 0.036 4.296 ; + END + END rd_out[88] + PIN rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.320 0.036 4.344 ; + END + END rd_out[89] + PIN rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.368 0.036 4.392 ; + END + END rd_out[90] + PIN rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.416 0.036 4.440 ; + END + END rd_out[91] + PIN rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.464 0.036 4.488 ; + END + END rd_out[92] + PIN rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.512 0.036 4.536 ; + END + END rd_out[93] + PIN rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.560 0.036 4.584 ; + END + END rd_out[94] + PIN rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.608 0.036 4.632 ; + END + END rd_out[95] + PIN rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.656 0.036 4.680 ; + END + END rd_out[96] + PIN rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.704 0.036 4.728 ; + END + END rd_out[97] + PIN rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.752 0.036 4.776 ; + END + END rd_out[98] + PIN rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.036 4.824 ; + END + END rd_out[99] + PIN rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.848 0.036 4.872 ; + END + END rd_out[100] + PIN rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.896 0.036 4.920 ; + END + END rd_out[101] + PIN rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.944 0.036 4.968 ; + END + END rd_out[102] + PIN rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.992 0.036 5.016 ; + END + END rd_out[103] + PIN rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.040 0.036 5.064 ; + END + END rd_out[104] + PIN rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.088 0.036 5.112 ; + END + END rd_out[105] + PIN rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.136 0.036 5.160 ; + END + END rd_out[106] + PIN rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.184 0.036 5.208 ; + END + END rd_out[107] + PIN rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.232 0.036 5.256 ; + END + END rd_out[108] + PIN rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.280 0.036 5.304 ; + END + END rd_out[109] + PIN rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.328 0.036 5.352 ; + END + END rd_out[110] + PIN rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.376 0.036 5.400 ; + END + END rd_out[111] + PIN rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.424 0.036 5.448 ; + END + END rd_out[112] + PIN rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.472 0.036 5.496 ; + END + END rd_out[113] + PIN rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.520 0.036 5.544 ; + END + END rd_out[114] + PIN rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.568 0.036 5.592 ; + END + END rd_out[115] + PIN rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.616 0.036 5.640 ; + END + END rd_out[116] + PIN rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.664 0.036 5.688 ; + END + END rd_out[117] + PIN rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.712 0.036 5.736 ; + END + END rd_out[118] + PIN rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.760 0.036 5.784 ; + END + END rd_out[119] + PIN rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.036 5.832 ; + END + END rd_out[120] + PIN rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.856 0.036 5.880 ; + END + END rd_out[121] + PIN rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.904 0.036 5.928 ; + END + END rd_out[122] + PIN rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.952 0.036 5.976 ; + END + END rd_out[123] + PIN rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.000 0.036 6.024 ; + END + END rd_out[124] + PIN rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.048 0.036 6.072 ; + END + END rd_out[125] + PIN rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.096 0.036 6.120 ; + END + END rd_out[126] + PIN rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.144 0.036 6.168 ; + END + END rd_out[127] + PIN rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.192 0.036 6.216 ; + END + END rd_out[128] + PIN rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.240 0.036 6.264 ; + END + END rd_out[129] + PIN rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.288 0.036 6.312 ; + END + END rd_out[130] + PIN rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.336 0.036 6.360 ; + END + END rd_out[131] + PIN rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.384 0.036 6.408 ; + END + END rd_out[132] + PIN rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.432 0.036 6.456 ; + END + END rd_out[133] + PIN rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.480 0.036 6.504 ; + END + END rd_out[134] + PIN rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.528 0.036 6.552 ; + END + END rd_out[135] + PIN rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.576 0.036 6.600 ; + END + END rd_out[136] + PIN rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.624 0.036 6.648 ; + END + END rd_out[137] + PIN rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.672 0.036 6.696 ; + END + END rd_out[138] + PIN rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.720 0.036 6.744 ; + END + END rd_out[139] + PIN rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.768 0.036 6.792 ; + END + END rd_out[140] + PIN rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.816 0.036 6.840 ; + END + END rd_out[141] + PIN rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.864 0.036 6.888 ; + END + END rd_out[142] + PIN rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.912 0.036 6.936 ; + END + END rd_out[143] + PIN rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.960 0.036 6.984 ; + END + END rd_out[144] + PIN rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.008 0.036 7.032 ; + END + END rd_out[145] + PIN rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.056 0.036 7.080 ; + END + END rd_out[146] + PIN rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.104 0.036 7.128 ; + END + END rd_out[147] + PIN rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.152 0.036 7.176 ; + END + END rd_out[148] + PIN rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.200 0.036 7.224 ; + END + END rd_out[149] + PIN rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.248 0.036 7.272 ; + END + END rd_out[150] + PIN rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.296 0.036 7.320 ; + END + END rd_out[151] + PIN rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.344 0.036 7.368 ; + END + END rd_out[152] + PIN rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.392 0.036 7.416 ; + END + END rd_out[153] + PIN rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.440 0.036 7.464 ; + END + END rd_out[154] + PIN rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.488 0.036 7.512 ; + END + END rd_out[155] + PIN rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.536 0.036 7.560 ; + END + END rd_out[156] + PIN rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.584 0.036 7.608 ; + END + END rd_out[157] + PIN rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.632 0.036 7.656 ; + END + END rd_out[158] + PIN rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.680 0.036 7.704 ; + END + END rd_out[159] + PIN rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.728 0.036 7.752 ; + END + END rd_out[160] + PIN rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.776 0.036 7.800 ; + END + END rd_out[161] + PIN rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.824 0.036 7.848 ; + END + END rd_out[162] + PIN rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.872 0.036 7.896 ; + END + END rd_out[163] + PIN rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.920 0.036 7.944 ; + END + END rd_out[164] + PIN rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.968 0.036 7.992 ; + END + END rd_out[165] + PIN rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.016 0.036 8.040 ; + END + END rd_out[166] + PIN rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.064 0.036 8.088 ; + END + END rd_out[167] + PIN rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.112 0.036 8.136 ; + END + END rd_out[168] + PIN rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.160 0.036 8.184 ; + END + END rd_out[169] + PIN rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.208 0.036 8.232 ; + END + END rd_out[170] + PIN rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.256 0.036 8.280 ; + END + END rd_out[171] + PIN rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.304 0.036 8.328 ; + END + END rd_out[172] + PIN rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.352 0.036 8.376 ; + END + END rd_out[173] + PIN rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.400 0.036 8.424 ; + END + END rd_out[174] + PIN rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.448 0.036 8.472 ; + END + END rd_out[175] + PIN rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.496 0.036 8.520 ; + END + END rd_out[176] + PIN rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.544 0.036 8.568 ; + END + END rd_out[177] + PIN rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.592 0.036 8.616 ; + END + END rd_out[178] + PIN rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.640 0.036 8.664 ; + END + END rd_out[179] + PIN rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.688 0.036 8.712 ; + END + END rd_out[180] + PIN rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.736 0.036 8.760 ; + END + END rd_out[181] + PIN rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.784 0.036 8.808 ; + END + END rd_out[182] + PIN rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.832 0.036 8.856 ; + END + END rd_out[183] + PIN rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.880 0.036 8.904 ; + END + END rd_out[184] + PIN rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.928 0.036 8.952 ; + END + END rd_out[185] + PIN rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.976 0.036 9.000 ; + END + END rd_out[186] + PIN rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.024 0.036 9.048 ; + END + END rd_out[187] + PIN rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.072 0.036 9.096 ; + END + END rd_out[188] + PIN rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.120 0.036 9.144 ; + END + END rd_out[189] + PIN rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.168 0.036 9.192 ; + END + END rd_out[190] + PIN rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.216 0.036 9.240 ; + END + END rd_out[191] + PIN rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.264 0.036 9.288 ; + END + END rd_out[192] + PIN rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.312 0.036 9.336 ; + END + END rd_out[193] + PIN rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.360 0.036 9.384 ; + END + END rd_out[194] + PIN rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.408 0.036 9.432 ; + END + END rd_out[195] + PIN rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.456 0.036 9.480 ; + END + END rd_out[196] + PIN rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.504 0.036 9.528 ; + END + END rd_out[197] + PIN rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.552 0.036 9.576 ; + END + END rd_out[198] + PIN rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.600 0.036 9.624 ; + END + END rd_out[199] + PIN rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.648 0.036 9.672 ; + END + END rd_out[200] + PIN rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.696 0.036 9.720 ; + END + END rd_out[201] + PIN rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.744 0.036 9.768 ; + END + END rd_out[202] + PIN rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.792 0.036 9.816 ; + END + END rd_out[203] + PIN rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.840 0.036 9.864 ; + END + END rd_out[204] + PIN rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.888 0.036 9.912 ; + END + END rd_out[205] + PIN rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.936 0.036 9.960 ; + END + END rd_out[206] + PIN rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.984 0.036 10.008 ; + END + END rd_out[207] + PIN rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.032 0.036 10.056 ; + END + END rd_out[208] + PIN rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.080 0.036 10.104 ; + END + END rd_out[209] + PIN rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.128 0.036 10.152 ; + END + END rd_out[210] + PIN rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.176 0.036 10.200 ; + END + END rd_out[211] + PIN rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.224 0.036 10.248 ; + END + END rd_out[212] + PIN rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.272 0.036 10.296 ; + END + END rd_out[213] + PIN rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.320 0.036 10.344 ; + END + END rd_out[214] + PIN rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.368 0.036 10.392 ; + END + END rd_out[215] + PIN rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.416 0.036 10.440 ; + END + END rd_out[216] + PIN rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.464 0.036 10.488 ; + END + END rd_out[217] + PIN rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.512 0.036 10.536 ; + END + END rd_out[218] + PIN rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.560 0.036 10.584 ; + END + END rd_out[219] + PIN rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.608 0.036 10.632 ; + END + END rd_out[220] + PIN rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.656 0.036 10.680 ; + END + END rd_out[221] + PIN rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.704 0.036 10.728 ; + END + END rd_out[222] + PIN rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.752 0.036 10.776 ; + END + END rd_out[223] + PIN rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.800 0.036 10.824 ; + END + END rd_out[224] + PIN rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.848 0.036 10.872 ; + END + END rd_out[225] + PIN rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.896 0.036 10.920 ; + END + END rd_out[226] + PIN rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.944 0.036 10.968 ; + END + END rd_out[227] + PIN rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.992 0.036 11.016 ; + END + END rd_out[228] + PIN rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.040 0.036 11.064 ; + END + END rd_out[229] + PIN rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.088 0.036 11.112 ; + END + END rd_out[230] + PIN rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.136 0.036 11.160 ; + END + END rd_out[231] + PIN rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.184 0.036 11.208 ; + END + END rd_out[232] + PIN rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.232 0.036 11.256 ; + END + END rd_out[233] + PIN rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.280 0.036 11.304 ; + END + END rd_out[234] + PIN rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.328 0.036 11.352 ; + END + END rd_out[235] + PIN rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.376 0.036 11.400 ; + END + END rd_out[236] + PIN rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.424 0.036 11.448 ; + END + END rd_out[237] + PIN rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.472 0.036 11.496 ; + END + END rd_out[238] + PIN rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.520 0.036 11.544 ; + END + END rd_out[239] + PIN rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.568 0.036 11.592 ; + END + END rd_out[240] + PIN rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.616 0.036 11.640 ; + END + END rd_out[241] + PIN rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.664 0.036 11.688 ; + END + END rd_out[242] + PIN rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.712 0.036 11.736 ; + END + END rd_out[243] + PIN rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.760 0.036 11.784 ; + END + END rd_out[244] + PIN rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.808 0.036 11.832 ; + END + END rd_out[245] + PIN rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.856 0.036 11.880 ; + END + END rd_out[246] + PIN rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.904 0.036 11.928 ; + END + END rd_out[247] + PIN rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.952 0.036 11.976 ; + END + END rd_out[248] + PIN rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.000 0.036 12.024 ; + END + END rd_out[249] + PIN rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.048 0.036 12.072 ; + END + END rd_out[250] + PIN rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.096 0.036 12.120 ; + END + END rd_out[251] + PIN rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.144 0.036 12.168 ; + END + END rd_out[252] + PIN rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.192 0.036 12.216 ; + END + END rd_out[253] + PIN rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.240 0.036 12.264 ; + END + END rd_out[254] + PIN rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.288 0.036 12.312 ; + END + END rd_out[255] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.536 0.036 19.560 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.584 0.036 19.608 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.632 0.036 19.656 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.680 0.036 19.704 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.728 0.036 19.752 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.776 0.036 19.800 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.824 0.036 19.848 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.872 0.036 19.896 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.920 0.036 19.944 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.968 0.036 19.992 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.016 0.036 20.040 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.064 0.036 20.088 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.112 0.036 20.136 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.160 0.036 20.184 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.208 0.036 20.232 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.256 0.036 20.280 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.304 0.036 20.328 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.352 0.036 20.376 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.400 0.036 20.424 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.448 0.036 20.472 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.496 0.036 20.520 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.544 0.036 20.568 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.592 0.036 20.616 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.640 0.036 20.664 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.688 0.036 20.712 ; + END + END wd_in[24] + PIN wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.736 0.036 20.760 ; + END + END wd_in[25] + PIN wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.784 0.036 20.808 ; + END + END wd_in[26] + PIN wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.832 0.036 20.856 ; + END + END wd_in[27] + PIN wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.880 0.036 20.904 ; + END + END wd_in[28] + PIN wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.928 0.036 20.952 ; + END + END wd_in[29] + PIN wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.976 0.036 21.000 ; + END + END wd_in[30] + PIN wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.024 0.036 21.048 ; + END + END wd_in[31] + PIN wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.072 0.036 21.096 ; + END + END wd_in[32] + PIN wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.120 0.036 21.144 ; + END + END wd_in[33] + PIN wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.168 0.036 21.192 ; + END + END wd_in[34] + PIN wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.216 0.036 21.240 ; + END + END wd_in[35] + PIN wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.264 0.036 21.288 ; + END + END wd_in[36] + PIN wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.312 0.036 21.336 ; + END + END wd_in[37] + PIN wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.360 0.036 21.384 ; + END + END wd_in[38] + PIN wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.408 0.036 21.432 ; + END + END wd_in[39] + PIN wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.456 0.036 21.480 ; + END + END wd_in[40] + PIN wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.504 0.036 21.528 ; + END + END wd_in[41] + PIN wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.552 0.036 21.576 ; + END + END wd_in[42] + PIN wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.600 0.036 21.624 ; + END + END wd_in[43] + PIN wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.648 0.036 21.672 ; + END + END wd_in[44] + PIN wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.696 0.036 21.720 ; + END + END wd_in[45] + PIN wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.744 0.036 21.768 ; + END + END wd_in[46] + PIN wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.792 0.036 21.816 ; + END + END wd_in[47] + PIN wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.840 0.036 21.864 ; + END + END wd_in[48] + PIN wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.888 0.036 21.912 ; + END + END wd_in[49] + PIN wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.936 0.036 21.960 ; + END + END wd_in[50] + PIN wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.984 0.036 22.008 ; + END + END wd_in[51] + PIN wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.032 0.036 22.056 ; + END + END wd_in[52] + PIN wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.080 0.036 22.104 ; + END + END wd_in[53] + PIN wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.128 0.036 22.152 ; + END + END wd_in[54] + PIN wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.176 0.036 22.200 ; + END + END wd_in[55] + PIN wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.224 0.036 22.248 ; + END + END wd_in[56] + PIN wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.272 0.036 22.296 ; + END + END wd_in[57] + PIN wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.320 0.036 22.344 ; + END + END wd_in[58] + PIN wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.368 0.036 22.392 ; + END + END wd_in[59] + PIN wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.416 0.036 22.440 ; + END + END wd_in[60] + PIN wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.464 0.036 22.488 ; + END + END wd_in[61] + PIN wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.512 0.036 22.536 ; + END + END wd_in[62] + PIN wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.560 0.036 22.584 ; + END + END wd_in[63] + PIN wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.608 0.036 22.632 ; + END + END wd_in[64] + PIN wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.656 0.036 22.680 ; + END + END wd_in[65] + PIN wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.704 0.036 22.728 ; + END + END wd_in[66] + PIN wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.752 0.036 22.776 ; + END + END wd_in[67] + PIN wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.800 0.036 22.824 ; + END + END wd_in[68] + PIN wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.848 0.036 22.872 ; + END + END wd_in[69] + PIN wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.896 0.036 22.920 ; + END + END wd_in[70] + PIN wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.944 0.036 22.968 ; + END + END wd_in[71] + PIN wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.992 0.036 23.016 ; + END + END wd_in[72] + PIN wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.040 0.036 23.064 ; + END + END wd_in[73] + PIN wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.088 0.036 23.112 ; + END + END wd_in[74] + PIN wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.136 0.036 23.160 ; + END + END wd_in[75] + PIN wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.184 0.036 23.208 ; + END + END wd_in[76] + PIN wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.232 0.036 23.256 ; + END + END wd_in[77] + PIN wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.280 0.036 23.304 ; + END + END wd_in[78] + PIN wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.328 0.036 23.352 ; + END + END wd_in[79] + PIN wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.376 0.036 23.400 ; + END + END wd_in[80] + PIN wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.424 0.036 23.448 ; + END + END wd_in[81] + PIN wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.472 0.036 23.496 ; + END + END wd_in[82] + PIN wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.520 0.036 23.544 ; + END + END wd_in[83] + PIN wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.568 0.036 23.592 ; + END + END wd_in[84] + PIN wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.616 0.036 23.640 ; + END + END wd_in[85] + PIN wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.664 0.036 23.688 ; + END + END wd_in[86] + PIN wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.712 0.036 23.736 ; + END + END wd_in[87] + PIN wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.760 0.036 23.784 ; + END + END wd_in[88] + PIN wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.808 0.036 23.832 ; + END + END wd_in[89] + PIN wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.856 0.036 23.880 ; + END + END wd_in[90] + PIN wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.904 0.036 23.928 ; + END + END wd_in[91] + PIN wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.952 0.036 23.976 ; + END + END wd_in[92] + PIN wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.000 0.036 24.024 ; + END + END wd_in[93] + PIN wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.048 0.036 24.072 ; + END + END wd_in[94] + PIN wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.096 0.036 24.120 ; + END + END wd_in[95] + PIN wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.144 0.036 24.168 ; + END + END wd_in[96] + PIN wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.192 0.036 24.216 ; + END + END wd_in[97] + PIN wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.240 0.036 24.264 ; + END + END wd_in[98] + PIN wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.288 0.036 24.312 ; + END + END wd_in[99] + PIN wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.336 0.036 24.360 ; + END + END wd_in[100] + PIN wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.384 0.036 24.408 ; + END + END wd_in[101] + PIN wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.432 0.036 24.456 ; + END + END wd_in[102] + PIN wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.480 0.036 24.504 ; + END + END wd_in[103] + PIN wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.528 0.036 24.552 ; + END + END wd_in[104] + PIN wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.576 0.036 24.600 ; + END + END wd_in[105] + PIN wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.624 0.036 24.648 ; + END + END wd_in[106] + PIN wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.672 0.036 24.696 ; + END + END wd_in[107] + PIN wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.720 0.036 24.744 ; + END + END wd_in[108] + PIN wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.768 0.036 24.792 ; + END + END wd_in[109] + PIN wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.816 0.036 24.840 ; + END + END wd_in[110] + PIN wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.864 0.036 24.888 ; + END + END wd_in[111] + PIN wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.912 0.036 24.936 ; + END + END wd_in[112] + PIN wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.960 0.036 24.984 ; + END + END wd_in[113] + PIN wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.008 0.036 25.032 ; + END + END wd_in[114] + PIN wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.056 0.036 25.080 ; + END + END wd_in[115] + PIN wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.104 0.036 25.128 ; + END + END wd_in[116] + PIN wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.152 0.036 25.176 ; + END + END wd_in[117] + PIN wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.200 0.036 25.224 ; + END + END wd_in[118] + PIN wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.248 0.036 25.272 ; + END + END wd_in[119] + PIN wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.296 0.036 25.320 ; + END + END wd_in[120] + PIN wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.344 0.036 25.368 ; + END + END wd_in[121] + PIN wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.392 0.036 25.416 ; + END + END wd_in[122] + PIN wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.440 0.036 25.464 ; + END + END wd_in[123] + PIN wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.488 0.036 25.512 ; + END + END wd_in[124] + PIN wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.536 0.036 25.560 ; + END + END wd_in[125] + PIN wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.584 0.036 25.608 ; + END + END wd_in[126] + PIN wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.632 0.036 25.656 ; + END + END wd_in[127] + PIN wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.680 0.036 25.704 ; + END + END wd_in[128] + PIN wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.728 0.036 25.752 ; + END + END wd_in[129] + PIN wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.776 0.036 25.800 ; + END + END wd_in[130] + PIN wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.824 0.036 25.848 ; + END + END wd_in[131] + PIN wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.872 0.036 25.896 ; + END + END wd_in[132] + PIN wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.920 0.036 25.944 ; + END + END wd_in[133] + PIN wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.968 0.036 25.992 ; + END + END wd_in[134] + PIN wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.016 0.036 26.040 ; + END + END wd_in[135] + PIN wd_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.064 0.036 26.088 ; + END + END wd_in[136] + PIN wd_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.112 0.036 26.136 ; + END + END wd_in[137] + PIN wd_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.160 0.036 26.184 ; + END + END wd_in[138] + PIN wd_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.208 0.036 26.232 ; + END + END wd_in[139] + PIN wd_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.256 0.036 26.280 ; + END + END wd_in[140] + PIN wd_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.304 0.036 26.328 ; + END + END wd_in[141] + PIN wd_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.352 0.036 26.376 ; + END + END wd_in[142] + PIN wd_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.400 0.036 26.424 ; + END + END wd_in[143] + PIN wd_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.448 0.036 26.472 ; + END + END wd_in[144] + PIN wd_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.496 0.036 26.520 ; + END + END wd_in[145] + PIN wd_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.544 0.036 26.568 ; + END + END wd_in[146] + PIN wd_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.592 0.036 26.616 ; + END + END wd_in[147] + PIN wd_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.640 0.036 26.664 ; + END + END wd_in[148] + PIN wd_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.688 0.036 26.712 ; + END + END wd_in[149] + PIN wd_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.736 0.036 26.760 ; + END + END wd_in[150] + PIN wd_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.784 0.036 26.808 ; + END + END wd_in[151] + PIN wd_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.832 0.036 26.856 ; + END + END wd_in[152] + PIN wd_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.880 0.036 26.904 ; + END + END wd_in[153] + PIN wd_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.928 0.036 26.952 ; + END + END wd_in[154] + PIN wd_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.976 0.036 27.000 ; + END + END wd_in[155] + PIN wd_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.024 0.036 27.048 ; + END + END wd_in[156] + PIN wd_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.072 0.036 27.096 ; + END + END wd_in[157] + PIN wd_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.120 0.036 27.144 ; + END + END wd_in[158] + PIN wd_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.168 0.036 27.192 ; + END + END wd_in[159] + PIN wd_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.216 0.036 27.240 ; + END + END wd_in[160] + PIN wd_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.264 0.036 27.288 ; + END + END wd_in[161] + PIN wd_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.312 0.036 27.336 ; + END + END wd_in[162] + PIN wd_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.360 0.036 27.384 ; + END + END wd_in[163] + PIN wd_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.408 0.036 27.432 ; + END + END wd_in[164] + PIN wd_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.456 0.036 27.480 ; + END + END wd_in[165] + PIN wd_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.504 0.036 27.528 ; + END + END wd_in[166] + PIN wd_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.552 0.036 27.576 ; + END + END wd_in[167] + PIN wd_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.600 0.036 27.624 ; + END + END wd_in[168] + PIN wd_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.648 0.036 27.672 ; + END + END wd_in[169] + PIN wd_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.696 0.036 27.720 ; + END + END wd_in[170] + PIN wd_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.744 0.036 27.768 ; + END + END wd_in[171] + PIN wd_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.792 0.036 27.816 ; + END + END wd_in[172] + PIN wd_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.840 0.036 27.864 ; + END + END wd_in[173] + PIN wd_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.888 0.036 27.912 ; + END + END wd_in[174] + PIN wd_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.936 0.036 27.960 ; + END + END wd_in[175] + PIN wd_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.984 0.036 28.008 ; + END + END wd_in[176] + PIN wd_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.032 0.036 28.056 ; + END + END wd_in[177] + PIN wd_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.080 0.036 28.104 ; + END + END wd_in[178] + PIN wd_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.128 0.036 28.152 ; + END + END wd_in[179] + PIN wd_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.176 0.036 28.200 ; + END + END wd_in[180] + PIN wd_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.224 0.036 28.248 ; + END + END wd_in[181] + PIN wd_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.272 0.036 28.296 ; + END + END wd_in[182] + PIN wd_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.320 0.036 28.344 ; + END + END wd_in[183] + PIN wd_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.368 0.036 28.392 ; + END + END wd_in[184] + PIN wd_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.416 0.036 28.440 ; + END + END wd_in[185] + PIN wd_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.464 0.036 28.488 ; + END + END wd_in[186] + PIN wd_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.512 0.036 28.536 ; + END + END wd_in[187] + PIN wd_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.560 0.036 28.584 ; + END + END wd_in[188] + PIN wd_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.608 0.036 28.632 ; + END + END wd_in[189] + PIN wd_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.656 0.036 28.680 ; + END + END wd_in[190] + PIN wd_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.704 0.036 28.728 ; + END + END wd_in[191] + PIN wd_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.752 0.036 28.776 ; + END + END wd_in[192] + PIN wd_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.800 0.036 28.824 ; + END + END wd_in[193] + PIN wd_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.848 0.036 28.872 ; + END + END wd_in[194] + PIN wd_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.896 0.036 28.920 ; + END + END wd_in[195] + PIN wd_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.944 0.036 28.968 ; + END + END wd_in[196] + PIN wd_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.992 0.036 29.016 ; + END + END wd_in[197] + PIN wd_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.040 0.036 29.064 ; + END + END wd_in[198] + PIN wd_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.088 0.036 29.112 ; + END + END wd_in[199] + PIN wd_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.136 0.036 29.160 ; + END + END wd_in[200] + PIN wd_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.184 0.036 29.208 ; + END + END wd_in[201] + PIN wd_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.232 0.036 29.256 ; + END + END wd_in[202] + PIN wd_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.280 0.036 29.304 ; + END + END wd_in[203] + PIN wd_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.328 0.036 29.352 ; + END + END wd_in[204] + PIN wd_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.376 0.036 29.400 ; + END + END wd_in[205] + PIN wd_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.424 0.036 29.448 ; + END + END wd_in[206] + PIN wd_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.472 0.036 29.496 ; + END + END wd_in[207] + PIN wd_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.520 0.036 29.544 ; + END + END wd_in[208] + PIN wd_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.568 0.036 29.592 ; + END + END wd_in[209] + PIN wd_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.616 0.036 29.640 ; + END + END wd_in[210] + PIN wd_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.664 0.036 29.688 ; + END + END wd_in[211] + PIN wd_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.712 0.036 29.736 ; + END + END wd_in[212] + PIN wd_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.760 0.036 29.784 ; + END + END wd_in[213] + PIN wd_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.808 0.036 29.832 ; + END + END wd_in[214] + PIN wd_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.856 0.036 29.880 ; + END + END wd_in[215] + PIN wd_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.904 0.036 29.928 ; + END + END wd_in[216] + PIN wd_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.952 0.036 29.976 ; + END + END wd_in[217] + PIN wd_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.000 0.036 30.024 ; + END + END wd_in[218] + PIN wd_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.048 0.036 30.072 ; + END + END wd_in[219] + PIN wd_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.096 0.036 30.120 ; + END + END wd_in[220] + PIN wd_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.144 0.036 30.168 ; + END + END wd_in[221] + PIN wd_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.192 0.036 30.216 ; + END + END wd_in[222] + PIN wd_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.240 0.036 30.264 ; + END + END wd_in[223] + PIN wd_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.288 0.036 30.312 ; + END + END wd_in[224] + PIN wd_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.336 0.036 30.360 ; + END + END wd_in[225] + PIN wd_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.384 0.036 30.408 ; + END + END wd_in[226] + PIN wd_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.432 0.036 30.456 ; + END + END wd_in[227] + PIN wd_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.480 0.036 30.504 ; + END + END wd_in[228] + PIN wd_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.528 0.036 30.552 ; + END + END wd_in[229] + PIN wd_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.576 0.036 30.600 ; + END + END wd_in[230] + PIN wd_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.624 0.036 30.648 ; + END + END wd_in[231] + PIN wd_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.672 0.036 30.696 ; + END + END wd_in[232] + PIN wd_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.720 0.036 30.744 ; + END + END wd_in[233] + PIN wd_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.768 0.036 30.792 ; + END + END wd_in[234] + PIN wd_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.816 0.036 30.840 ; + END + END wd_in[235] + PIN wd_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.864 0.036 30.888 ; + END + END wd_in[236] + PIN wd_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.912 0.036 30.936 ; + END + END wd_in[237] + PIN wd_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.960 0.036 30.984 ; + END + END wd_in[238] + PIN wd_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.008 0.036 31.032 ; + END + END wd_in[239] + PIN wd_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.056 0.036 31.080 ; + END + END wd_in[240] + PIN wd_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.104 0.036 31.128 ; + END + END wd_in[241] + PIN wd_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.152 0.036 31.176 ; + END + END wd_in[242] + PIN wd_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.200 0.036 31.224 ; + END + END wd_in[243] + PIN wd_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.248 0.036 31.272 ; + END + END wd_in[244] + PIN wd_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.296 0.036 31.320 ; + END + END wd_in[245] + PIN wd_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.344 0.036 31.368 ; + END + END wd_in[246] + PIN wd_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.392 0.036 31.416 ; + END + END wd_in[247] + PIN wd_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.440 0.036 31.464 ; + END + END wd_in[248] + PIN wd_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.488 0.036 31.512 ; + END + END wd_in[249] + PIN wd_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.536 0.036 31.560 ; + END + END wd_in[250] + PIN wd_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.584 0.036 31.608 ; + END + END wd_in[251] + PIN wd_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.632 0.036 31.656 ; + END + END wd_in[252] + PIN wd_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.680 0.036 31.704 ; + END + END wd_in[253] + PIN wd_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.728 0.036 31.752 ; + END + END wd_in[254] + PIN wd_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.776 0.036 31.800 ; + END + END wd_in[255] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.024 0.036 39.048 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.072 0.036 39.096 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.120 0.036 39.144 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.168 0.036 39.192 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.216 0.036 39.240 ; + END + END addr_in[4] + PIN addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.264 0.036 39.288 ; + END + END addr_in[5] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.512 0.036 46.536 ; + END + END we_in + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.560 0.036 46.584 ; + END + END ce_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.608 0.036 46.632 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.096 0.000 33.154 0.096 ; + RECT 0.096 0.768 33.154 0.864 ; + RECT 0.096 1.536 33.154 1.632 ; + RECT 0.096 2.304 33.154 2.400 ; + RECT 0.096 3.072 33.154 3.168 ; + RECT 0.096 3.840 33.154 3.936 ; + RECT 0.096 4.608 33.154 4.704 ; + RECT 0.096 5.376 33.154 5.472 ; + RECT 0.096 6.144 33.154 6.240 ; + RECT 0.096 6.912 33.154 7.008 ; + RECT 0.096 7.680 33.154 7.776 ; + RECT 0.096 8.448 33.154 8.544 ; + RECT 0.096 9.216 33.154 9.312 ; + RECT 0.096 9.984 33.154 10.080 ; + RECT 0.096 10.752 33.154 10.848 ; + RECT 0.096 11.520 33.154 11.616 ; + RECT 0.096 12.288 33.154 12.384 ; + RECT 0.096 13.056 33.154 13.152 ; + RECT 0.096 13.824 33.154 13.920 ; + RECT 0.096 14.592 33.154 14.688 ; + RECT 0.096 15.360 33.154 15.456 ; + RECT 0.096 16.128 33.154 16.224 ; + RECT 0.096 16.896 33.154 16.992 ; + RECT 0.096 17.664 33.154 17.760 ; + RECT 0.096 18.432 33.154 18.528 ; + RECT 0.096 19.200 33.154 19.296 ; + RECT 0.096 19.968 33.154 20.064 ; + RECT 0.096 20.736 33.154 20.832 ; + RECT 0.096 21.504 33.154 21.600 ; + RECT 0.096 22.272 33.154 22.368 ; + RECT 0.096 23.040 33.154 23.136 ; + RECT 0.096 23.808 33.154 23.904 ; + RECT 0.096 24.576 33.154 24.672 ; + RECT 0.096 25.344 33.154 25.440 ; + RECT 0.096 26.112 33.154 26.208 ; + RECT 0.096 26.880 33.154 26.976 ; + RECT 0.096 27.648 33.154 27.744 ; + RECT 0.096 28.416 33.154 28.512 ; + RECT 0.096 29.184 33.154 29.280 ; + RECT 0.096 29.952 33.154 30.048 ; + RECT 0.096 30.720 33.154 30.816 ; + RECT 0.096 31.488 33.154 31.584 ; + RECT 0.096 32.256 33.154 32.352 ; + RECT 0.096 33.024 33.154 33.120 ; + RECT 0.096 33.792 33.154 33.888 ; + RECT 0.096 34.560 33.154 34.656 ; + RECT 0.096 35.328 33.154 35.424 ; + RECT 0.096 36.096 33.154 36.192 ; + RECT 0.096 36.864 33.154 36.960 ; + RECT 0.096 37.632 33.154 37.728 ; + RECT 0.096 38.400 33.154 38.496 ; + RECT 0.096 39.168 33.154 39.264 ; + RECT 0.096 39.936 33.154 40.032 ; + RECT 0.096 40.704 33.154 40.800 ; + RECT 0.096 41.472 33.154 41.568 ; + RECT 0.096 42.240 33.154 42.336 ; + RECT 0.096 43.008 33.154 43.104 ; + RECT 0.096 43.776 33.154 43.872 ; + RECT 0.096 44.544 33.154 44.640 ; + RECT 0.096 45.312 33.154 45.408 ; + RECT 0.096 46.080 33.154 46.176 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.096 0.384 33.154 0.480 ; + RECT 0.096 1.152 33.154 1.248 ; + RECT 0.096 1.920 33.154 2.016 ; + RECT 0.096 2.688 33.154 2.784 ; + RECT 0.096 3.456 33.154 3.552 ; + RECT 0.096 4.224 33.154 4.320 ; + RECT 0.096 4.992 33.154 5.088 ; + RECT 0.096 5.760 33.154 5.856 ; + RECT 0.096 6.528 33.154 6.624 ; + RECT 0.096 7.296 33.154 7.392 ; + RECT 0.096 8.064 33.154 8.160 ; + RECT 0.096 8.832 33.154 8.928 ; + RECT 0.096 9.600 33.154 9.696 ; + RECT 0.096 10.368 33.154 10.464 ; + RECT 0.096 11.136 33.154 11.232 ; + RECT 0.096 11.904 33.154 12.000 ; + RECT 0.096 12.672 33.154 12.768 ; + RECT 0.096 13.440 33.154 13.536 ; + RECT 0.096 14.208 33.154 14.304 ; + RECT 0.096 14.976 33.154 15.072 ; + RECT 0.096 15.744 33.154 15.840 ; + RECT 0.096 16.512 33.154 16.608 ; + RECT 0.096 17.280 33.154 17.376 ; + RECT 0.096 18.048 33.154 18.144 ; + RECT 0.096 18.816 33.154 18.912 ; + RECT 0.096 19.584 33.154 19.680 ; + RECT 0.096 20.352 33.154 20.448 ; + RECT 0.096 21.120 33.154 21.216 ; + RECT 0.096 21.888 33.154 21.984 ; + RECT 0.096 22.656 33.154 22.752 ; + RECT 0.096 23.424 33.154 23.520 ; + RECT 0.096 24.192 33.154 24.288 ; + RECT 0.096 24.960 33.154 25.056 ; + RECT 0.096 25.728 33.154 25.824 ; + RECT 0.096 26.496 33.154 26.592 ; + RECT 0.096 27.264 33.154 27.360 ; + RECT 0.096 28.032 33.154 28.128 ; + RECT 0.096 28.800 33.154 28.896 ; + RECT 0.096 29.568 33.154 29.664 ; + RECT 0.096 30.336 33.154 30.432 ; + RECT 0.096 31.104 33.154 31.200 ; + RECT 0.096 31.872 33.154 31.968 ; + RECT 0.096 32.640 33.154 32.736 ; + RECT 0.096 33.408 33.154 33.504 ; + RECT 0.096 34.176 33.154 34.272 ; + RECT 0.096 34.944 33.154 35.040 ; + RECT 0.096 35.712 33.154 35.808 ; + RECT 0.096 36.480 33.154 36.576 ; + RECT 0.096 37.248 33.154 37.344 ; + RECT 0.096 38.016 33.154 38.112 ; + RECT 0.096 38.784 33.154 38.880 ; + RECT 0.096 39.552 33.154 39.648 ; + RECT 0.096 40.320 33.154 40.416 ; + RECT 0.096 41.088 33.154 41.184 ; + RECT 0.096 41.856 33.154 41.952 ; + RECT 0.096 42.624 33.154 42.720 ; + RECT 0.096 43.392 33.154 43.488 ; + RECT 0.096 44.160 33.154 44.256 ; + RECT 0.096 44.928 33.154 45.024 ; + RECT 0.096 45.696 33.154 45.792 ; + RECT 0.096 46.464 33.154 46.560 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 33.250 46.800 ; + LAYER M2 ; + RECT 0 0 33.250 46.800 ; + LAYER M3 ; + RECT 0 0 33.250 46.800 ; + LAYER M4 ; + RECT 0 0 33.250 46.800 ; + END +END fakeram7_64x256 + +END LIBRARY diff --git a/flow/platforms/asap7/lef/fakeram7_64x28.lef b/flow/platforms/asap7/lef/fakeram7_64x28.lef new file mode 100644 index 0000000000..725ac02163 --- /dev/null +++ b/flow/platforms/asap7/lef/fakeram7_64x28.lef @@ -0,0 +1,644 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO fakeram7_64x28 + PROPERTY width 28 ; + PROPERTY depth 64 ; + PROPERTY banks 4 ; + FOREIGN fakeram7_64x28 0 0 ; + SYMMETRY X Y R90 ; + SIZE 14.630 BY 6.000 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.036 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.096 0.036 0.120 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.144 0.036 0.168 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.192 0.036 0.216 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.240 0.036 0.264 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.288 0.036 0.312 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.036 0.360 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.384 0.036 0.408 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.432 0.036 0.456 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.480 0.036 0.504 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.528 0.036 0.552 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.576 0.036 0.600 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.036 0.648 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.672 0.036 0.696 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.720 0.036 0.744 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.768 0.036 0.792 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.816 0.036 0.840 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.864 0.036 0.888 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.036 0.936 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.960 0.036 0.984 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.008 0.036 1.032 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.056 0.036 1.080 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.104 0.036 1.128 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.152 0.036 1.176 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.036 1.224 ; + END + END rd_out[24] + PIN rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.248 0.036 1.272 ; + END + END rd_out[25] + PIN rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.296 0.036 1.320 ; + END + END rd_out[26] + PIN rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.344 0.036 1.368 ; + END + END rd_out[27] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.304 0.036 2.328 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.036 2.376 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.400 0.036 2.424 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.448 0.036 2.472 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.036 2.520 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.544 0.036 2.568 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.592 0.036 2.616 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.640 0.036 2.664 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.688 0.036 2.712 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.736 0.036 2.760 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.036 2.808 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.832 0.036 2.856 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.880 0.036 2.904 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.036 2.952 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.976 0.036 3.000 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.024 0.036 3.048 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.036 3.096 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.120 0.036 3.144 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.168 0.036 3.192 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.036 3.240 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.264 0.036 3.288 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.312 0.036 3.336 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.036 3.384 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.408 0.036 3.432 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.456 0.036 3.480 ; + END + END wd_in[24] + PIN wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.504 0.036 3.528 ; + END + END wd_in[25] + PIN wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.552 0.036 3.576 ; + END + END wd_in[26] + PIN wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.600 0.036 3.624 ; + END + END wd_in[27] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.560 0.036 4.584 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.608 0.036 4.632 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.656 0.036 4.680 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.704 0.036 4.728 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.752 0.036 4.776 ; + END + END addr_in[4] + PIN addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.036 4.824 ; + END + END addr_in[5] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.760 0.036 5.784 ; + END + END we_in + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.036 5.832 ; + END + END ce_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.856 0.036 5.880 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.096 0.000 14.534 0.096 ; + RECT 0.096 0.768 14.534 0.864 ; + RECT 0.096 1.536 14.534 1.632 ; + RECT 0.096 2.304 14.534 2.400 ; + RECT 0.096 3.072 14.534 3.168 ; + RECT 0.096 3.840 14.534 3.936 ; + RECT 0.096 4.608 14.534 4.704 ; + RECT 0.096 5.376 14.534 5.472 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.096 0.384 14.534 0.480 ; + RECT 0.096 1.152 14.534 1.248 ; + RECT 0.096 1.920 14.534 2.016 ; + RECT 0.096 2.688 14.534 2.784 ; + RECT 0.096 3.456 14.534 3.552 ; + RECT 0.096 4.224 14.534 4.320 ; + RECT 0.096 4.992 14.534 5.088 ; + RECT 0.096 5.760 14.534 5.856 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 14.630 6.000 ; + LAYER M2 ; + RECT 0 0 14.630 6.000 ; + LAYER M3 ; + RECT 0 0 14.630 6.000 ; + LAYER M4 ; + RECT 0 0 14.630 6.000 ; + END +END fakeram7_64x28 + +END LIBRARY diff --git a/flow/platforms/asap7/lib/NLDM/fakeram7_128x64.lib b/flow/platforms/asap7/lib/NLDM/fakeram7_128x64.lib new file mode 100644 index 0000000000..8bcf2d6ae7 --- /dev/null +++ b/flow/platforms/asap7/lib/NLDM/fakeram7_128x64.lib @@ -0,0 +1,389 @@ +library(fakeram7_128x64) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2025-06-10 17:10:26Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram7_128x64_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram7_128x64_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram7_128x64_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram7_128x64_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram7_128x64_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram7_128x64_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } + type (fakeram7_128x64_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram7_128x64) { + area : 343.985; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 64; + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram7_128x64_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram7_128x64_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rd_out) { + bus_type : fakeram7_128x64_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram7_128x64_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram7_128x64_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram7_128x64_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram7_128x64_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(ce_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_in) { + bus_type : fakeram7_128x64_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(wd_in) { + bus_type : fakeram7_128x64_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/flow/platforms/asap7/lib/NLDM/fakeram7_256x256.lib b/flow/platforms/asap7/lib/NLDM/fakeram7_256x256.lib new file mode 100644 index 0000000000..c7cc1a8a94 --- /dev/null +++ b/flow/platforms/asap7/lib/NLDM/fakeram7_256x256.lib @@ -0,0 +1,389 @@ +library(fakeram7_256x256) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2025-05-22 17:24:46Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram7_256x256_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram7_256x256_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram7_256x256_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram7_256x256_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram7_256x256_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram7_256x256_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 256; + bit_from : 255; + bit_to : 0 ; + downto : true ; + } + type (fakeram7_256x256_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram7_256x256) { + area : 2751.883; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 256; + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram7_256x256_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram7_256x256_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rd_out) { + bus_type : fakeram7_256x256_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram7_256x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram7_256x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram7_256x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram7_256x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(ce_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_in) { + bus_type : fakeram7_256x256_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(wd_in) { + bus_type : fakeram7_256x256_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/flow/platforms/asap7/lib/NLDM/fakeram7_64x25.lib b/flow/platforms/asap7/lib/NLDM/fakeram7_64x25.lib new file mode 100644 index 0000000000..1afa95f09b --- /dev/null +++ b/flow/platforms/asap7/lib/NLDM/fakeram7_64x25.lib @@ -0,0 +1,389 @@ +library(fakeram7_64x25) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2025-06-10 17:10:26Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram7_64x25_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram7_64x25_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram7_64x25_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram7_64x25_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram7_64x25_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram7_64x25_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 25; + bit_from : 24; + bit_to : 0 ; + downto : true ; + } + type (fakeram7_64x25_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram7_64x25) { + area : 67.185; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 25; + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram7_64x25_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram7_64x25_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rd_out) { + bus_type : fakeram7_64x25_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram7_64x25_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram7_64x25_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram7_64x25_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram7_64x25_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(ce_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_in) { + bus_type : fakeram7_64x25_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(wd_in) { + bus_type : fakeram7_64x25_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/flow/platforms/asap7/lib/NLDM/fakeram7_64x256.lib b/flow/platforms/asap7/lib/NLDM/fakeram7_64x256.lib new file mode 100644 index 0000000000..8282373b44 --- /dev/null +++ b/flow/platforms/asap7/lib/NLDM/fakeram7_64x256.lib @@ -0,0 +1,389 @@ +library(fakeram7_64x256) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2025-06-12 00:08:06Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram7_64x256_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram7_64x256_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram7_64x256_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram7_64x256_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram7_64x256_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram7_64x256_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 256; + bit_from : 255; + bit_to : 0 ; + downto : true ; + } + type (fakeram7_64x256_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram7_64x256) { + area : 1517.411; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 256; + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram7_64x256_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram7_64x256_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rd_out) { + bus_type : fakeram7_64x256_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram7_64x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram7_64x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram7_64x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram7_64x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(ce_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_in) { + bus_type : fakeram7_64x256_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(wd_in) { + bus_type : fakeram7_64x256_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/flow/platforms/asap7/lib/NLDM/fakeram7_64x28.lib b/flow/platforms/asap7/lib/NLDM/fakeram7_64x28.lib new file mode 100644 index 0000000000..1681b2bf1f --- /dev/null +++ b/flow/platforms/asap7/lib/NLDM/fakeram7_64x28.lib @@ -0,0 +1,389 @@ +library(fakeram7_64x28) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2025-06-10 17:10:26Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram7_64x28_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram7_64x28_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram7_64x28_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram7_64x28_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram7_64x28_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram7_64x28_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 28; + bit_from : 27; + bit_to : 0 ; + downto : true ; + } + type (fakeram7_64x28_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram7_64x28) { + area : 75.247; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 28; + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram7_64x28_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram7_64x28_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rd_out) { + bus_type : fakeram7_64x28_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram7_64x28_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram7_64x28_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram7_64x28_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram7_64x28_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(ce_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_in) { + bus_type : fakeram7_64x28_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(wd_in) { + bus_type : fakeram7_64x28_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/flow/platforms/asap7/liberty_suppressions.tcl b/flow/platforms/asap7/liberty_suppressions.tcl new file mode 100644 index 0000000000..c1526671c0 --- /dev/null +++ b/flow/platforms/asap7/liberty_suppressions.tcl @@ -0,0 +1,5 @@ +# To remove [WARNING STA-1212] from the logs for ASAP7. +# /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz +# line 13178, timing group from output port. +# Added following suppress_message +suppress_message STA 1212 diff --git a/flow/platforms/asap7/openRoad/make_tracks.tcl b/flow/platforms/asap7/openRoad/make_tracks.tcl index f404ab2209..ffd85fc94b 100644 --- a/flow/platforms/asap7/openRoad/make_tracks.tcl +++ b/flow/platforms/asap7/openRoad/make_tracks.tcl @@ -1,18 +1,18 @@ make_tracks Pad -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080 -make_tracks M9 -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080 -make_tracks M8 -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080 -make_tracks M7 -x_offset 0.016 -x_pitch 0.064 -y_offset 0.016 -y_pitch 0.064 -make_tracks M6 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.016 -y_pitch 0.064 -make_tracks M5 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.012 -y_pitch 0.048 -make_tracks M4 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.012 -y_pitch 0.048 -make_tracks M3 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036 +make_tracks M9 -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080 +make_tracks M8 -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080 +make_tracks M7 -x_offset 0.016 -x_pitch 0.064 -y_offset 0.016 -y_pitch 0.064 +make_tracks M6 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.016 -y_pitch 0.064 +make_tracks M5 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.012 -y_pitch 0.048 +make_tracks M4 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.012 -y_pitch 0.048 +make_tracks M3 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.045 -y_pitch 0.270 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.081 -y_pitch 0.270 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.117 -y_pitch 0.270 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.153 -y_pitch 0.270 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.189 -y_pitch 0.270 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.225 -y_pitch 0.270 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.270 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.045 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.081 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.117 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.153 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.189 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.225 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.270 -y_pitch 0.270 -make_tracks M1 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036 +make_tracks M1 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036 diff --git a/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl b/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl index bd7977d717..d26c62c64b 100644 --- a/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl +++ b/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl @@ -18,10 +18,13 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} define_pdn_grid -name {top} -voltage_domains {CORE} add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins -add_pdn_ring -grid {top} -layers {M5 M6} -widths {0.504 0.544} -spacings {0.096} -core_offset {0.504} +add_pdn_ring -grid {top} -layers {M5 M6} -widths {0.504 0.544} -spacings {0.096} \ + -core_offset {0.504} -add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.16} -offset {1.50} -extend_to_core_ring -add_pdn_stripe -grid {top} -layer {M6} -width {0.288} -spacing {0.096} -pitch {4.32} -offset {1.504} -extend_to_core_ring +add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.16} \ + -offset {1.50} -extend_to_core_ring +add_pdn_stripe -grid {top} -layer {M6} -width {0.288} -spacing {0.096} -pitch {4.32} \ + -offset {1.504} -extend_to_core_ring add_pdn_connect -grid {top} -layers {M1 M2} add_pdn_connect -grid {top} -layers {M2 M5} @@ -40,8 +43,10 @@ foreach macro [find_macros] { } set macro_names [dict keys $macro_names] +set halo_x $::env(MACRO_ROWS_HALO_X) +set halo_y $::env(MACRO_ROWS_HALO_Y) define_pdn_grid -macro -cells $macro_names \ - -halo "$::env(MACRO_ROWS_HALO_X) $::env(MACRO_ROWS_HALO_Y) $::env(MACRO_ROWS_HALO_X) $::env(MACRO_ROWS_HALO_Y)" \ - -voltage_domains {CORE} -name ElementGrid + -halo "$halo_x $halo_y $halo_x $halo_y" \ + -voltage_domains {CORE} -name ElementGrid add_pdn_connect -grid {ElementGrid} -layers {M5 M6} diff --git a/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl b/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl index 26234aae64..a5cb2dd041 100644 --- a/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl +++ b/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl @@ -20,14 +20,14 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} #################################### define_pdn_grid -name {top} -voltage_domains {CORE} -add_pdn_ring -grid {top} -layers {M5 M4} -widths {0.12 0.12} -spacings {0.072} -core_offset {0.084} +add_pdn_ring -grid {top} -layers {M5 M4} -widths {0.12 0.12} -spacings {0.072} -core_offset {0.084} -add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins -add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins +add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins +add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins -add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.976} -offset {1.5} -extend_to_core_ring +add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.976} -offset {1.5} \ + -extend_to_core_ring add_pdn_connect -grid {top} -layers {M1 M2} add_pdn_connect -grid {top} -layers {M2 M5} add_pdn_connect -grid {top} -layers {M4 M5} - diff --git a/flow/platforms/asap7/openRoad/pdn/grid_strategy-M1-M2-M5-M6.tcl b/flow/platforms/asap7/openRoad/pdn/grid_strategy-M1-M2-M5-M6.tcl index 0b19e5d69a..d3bcfa8a67 100644 --- a/flow/platforms/asap7/openRoad/pdn/grid_strategy-M1-M2-M5-M6.tcl +++ b/flow/platforms/asap7/openRoad/pdn/grid_strategy-M1-M2-M5-M6.tcl @@ -28,10 +28,12 @@ add_pdn_connect -grid {top} -layers {M5 M6} #################################### # grid for: CORE_macro_grid_1 #################################### -define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -cells {.*} +define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro \ + -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -cells {.*} add_pdn_connect -grid {CORE_macro_grid_1} -layers {M4 M5} #################################### # grid for: CORE_macro_grid_2 #################################### -define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -cells {.*} +define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro \ + -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -cells {.*} add_pdn_connect -grid {CORE_macro_grid_2} -layers {M4 M5} diff --git a/flow/platforms/asap7/openRoad/tapcell.tcl b/flow/platforms/asap7/openRoad/tapcell.tcl index 9526ba83d0..809d6952aa 100644 --- a/flow/platforms/asap7/openRoad/tapcell.tcl +++ b/flow/platforms/asap7/openRoad/tapcell.tcl @@ -9,6 +9,6 @@ puts " TAP Cell Distance : 25" tapcell \ -distance 25 \ -tapcell_master "$::env(TAP_CELL_NAME)" \ - -endcap_master "$::env(TAP_CELL_NAME)" \ + -endcap_master "$::env(TAP_CELL_NAME)" \ -halo_width_x $::env(MACRO_ROWS_HALO_X) \ -halo_width_y $::env(MACRO_ROWS_HALO_Y) diff --git a/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl b/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl index 28c2da3eed..4751010d48 100644 --- a/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl +++ b/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl @@ -1,3 +1,5 @@ +# tclint-disable line-length + set current_folder [file dirname [file normalize [info script]]] # Technology lib @@ -11,9 +13,9 @@ set ::env(LIB_SLOWEST) "" set lib_path "$libs_ref/lib" foreach lib {"AO" "INVBUF" "OA" "SEQ" "SIMPLE"} { - append ::env(LIB_FASTEST) "$lib_path/asap7sc7p5t_${lib}_RVT_FF_nldm_201020.lib " - append ::env(LIB_TYPICAL) "$lib_path/asap7sc7p5t_${lib}_RVT_TT_nldm_201020.lib " - append ::env(LIB_SLOWEST) "$lib_path/asap7sc7p5t_${lib}_RVT_SS_nldm_201020.lib " + append ::env(LIB_FASTEST) "$lib_path/asap7sc7p5t_${lib}_RVT_FF_nldm_201020.lib " + append ::env(LIB_TYPICAL) "$lib_path/asap7sc7p5t_${lib}_RVT_TT_nldm_201020.lib " + append ::env(LIB_SLOWEST) "$lib_path/asap7sc7p5t_${lib}_RVT_SS_nldm_201020.lib " } set ::env(LIB_SYNTH) $::env(LIB_TYPICAL) @@ -36,7 +38,7 @@ set ::env(FP_ENDCAP_CELL) "TAPCELL_ASAP7_75t_R" # defaults (can be overridden by designs): set ::env(SYNTH_DRIVING_CELL) "BUFx2_ASAP7_75t_R" set ::env(SYNTH_DRIVING_CELL_PIN) "Y" -set ::env(SYNTH_CAP_LOAD) "4.61057" ; # femtofarad INVx8_ASAP7_75t_R pin A cap +set ::env(SYNTH_CAP_LOAD) "4.61057" ;# femtofarad INVx8_ASAP7_75t_R pin A cap set ::env(SYNTH_MIN_BUF_PORT) "BUFx2_ASAP7_75t_R A Y" set ::env(SYNTH_TIEHI_PORT) "TIEHIx1_ASAP7_75t_R H" set ::env(SYNTH_TIELO_PORT) "TIELOx1_ASAP7_75t_R L" diff --git a/flow/platforms/asap7/openlane/config.tcl b/flow/platforms/asap7/openlane/config.tcl index d7a4ee0bd1..8724cdef98 100755 --- a/flow/platforms/asap7/openlane/config.tcl +++ b/flow/platforms/asap7/openlane/config.tcl @@ -1,3 +1,5 @@ +# tclint-disable line-length + # Process node set ::env(PROCESS) 7 set ::env(DEF_UNITS_PER_MICRON) 1000 @@ -15,7 +17,7 @@ set ::env(STD_CELL_GROUND_PINS) "VSS" set ::env(TECH_LEF) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/techlef/asap7_tech_1x_201209.lef" set ::env(CELLS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*.lef"] set ::env(GDS_FILES) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/gds/*.gds"] -set ::env(STD_CELL_LIBRARY_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/cdl/$::env(STD_CELL_LIBRARY).cdl" +set ::env(STD_CELL_LIBRARY_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/cdl/$::env(STD_CELL_LIBRARY).cdl" set ::env(GPIO_PADS_LEF) "" @@ -25,7 +27,7 @@ set ::env(GPIO_PADS_VERILOG) "" set ::env(TECH_LEF_OPT) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/techlef/$::env(STD_CELL_LIBRARY_OPT).tlef" set ::env(CELLS_LEF_OPT) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/lef/*.lef"] set ::env(GDS_FILES_OPT) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/gds/*.gds"] -set ::env(STD_CELL_LIBRARY_OPT_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/cdl/$::env(STD_CELL_LIBRARY_OPT).cdl" +set ::env(STD_CELL_LIBRARY_OPT_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/cdl/$::env(STD_CELL_LIBRARY_OPT).cdl" # Optimization library slowest corner diff --git a/flow/platforms/asap7/ram/cva6.cfg b/flow/platforms/asap7/ram/cva6.cfg new file mode 100644 index 0000000000..a7d378fa0e --- /dev/null +++ b/flow/platforms/asap7/ram/cva6.cfg @@ -0,0 +1,50 @@ +#SAMPLE INPUT FILE; VALUES NOT REALISTIC +{ + # The process node. + "tech_nm": 7, + + # The operating voltage. + "voltage": 0.7, + + # String to add in front of every metal layer number for the layer name. + "metal_prefix": "M", + + # Horizontal Metal layer for macro pins + "metal_layer": "M4", + + # The pin width for signal pins. + "pin_width_nm": 24, + + # The minimum pin pitch for signal pins + "pin_pitch_nm": 48, + + # Metal track pitch + "metal_track_pitch_nm": 48, + + # Manufacturing Grid + "manufacturing_grid_nm": 1, + + # Contacted Poly Pitch + "contacted_poly_pitch_nm": 54, + + #column mux factor + "column_mux_factor": 1, + + # Fin pitch + "fin_pitch_nm" : 27, + + # Optional snap the width and height of the sram to a multiple value. + "snap_width_nm": 190, + "snap_height_nm": 1200, + + # List of SRAM configurations (name width depth and banks) + "srams": [ + {"name": "fakeram7_64x28", "width": 28, "depth": 64, "banks": 4}, + {"name": "fakeram7_128x64", "width": 64, "depth": 128, "banks": 2}, + {"name": "fakeram7_64x25", "width": 25, "depth": 64, "banks": 4}, + {"name": "fakeram7_64x256", "width": 256, "depth": 64, "banks": 1, + "additional_height": 25} + ] + + # TENTATIVE PARAMETERS +} diff --git a/flow/platforms/asap7/setRC.tcl b/flow/platforms/asap7/setRC.tcl index 2a741ef815..d1d988b362 100644 --- a/flow/platforms/asap7/setRC.tcl +++ b/flow/platforms/asap7/setRC.tcl @@ -1,13 +1,14 @@ -# Liberty units are fF,kOhm -set_layer_rc -layer M1 -capacitance 1.1368e-01 -resistance 1.3889e-01 -set_layer_rc -layer M2 -capacitance 1.3426e-01 -resistance 2.4222e-02 -set_layer_rc -layer M3 -capacitance 1.2918e-01 -resistance 2.4222e-02 -set_layer_rc -layer M4 -capacitance 1.1396e-01 -resistance 1.6778e-02 -set_layer_rc -layer M5 -capacitance 1.3323e-01 -resistance 1.4677e-02 -set_layer_rc -layer M6 -capacitance 1.1575e-01 -resistance 1.0371e-02 -set_layer_rc -layer M7 -capacitance 1.3293e-01 -resistance 9.6720e-03 -set_layer_rc -layer M8 -capacitance 1.1822e-01 -resistance 7.4310e-03 -set_layer_rc -layer M9 -capacitance 1.3497e-01 -resistance 6.8740e-03 +# correlation result (aes, cva6, ibex, riscv32i) +# M1 capacitance fixed up from -4.8e-02 to 1e-10 as a minuscule positive value +set_layer_rc -layer M1 -resistance 7.04175E-02 -capacitance 1e-10 +set_layer_rc -layer M2 -resistance 4.62311E-02 -capacitance 1.84542E-01 +set_layer_rc -layer M3 -resistance 3.63251E-02 -capacitance 1.53955E-01 +set_layer_rc -layer M4 -resistance 2.03083E-02 -capacitance 1.89434E-01 +set_layer_rc -layer M5 -resistance 1.93005E-02 -capacitance 1.71593E-01 +set_layer_rc -layer M6 -resistance 1.18619E-02 -capacitance 1.76146E-01 +set_layer_rc -layer M7 -resistance 1.25311E-02 -capacitance 1.47030E-01 +set_wire_rc -signal -resistance 3.23151E-02 -capacitance 1.73323E-01 +set_wire_rc -clock -resistance 5.13971E-02 -capacitance 1.44549E-01 set_layer_rc -via V1 -resistance 1.72E-02 set_layer_rc -via V2 -resistance 1.72E-02 @@ -17,5 +18,3 @@ set_layer_rc -via V5 -resistance 1.18E-02 set_layer_rc -via V6 -resistance 8.20E-03 set_layer_rc -via V7 -resistance 8.20E-03 set_layer_rc -via V8 -resistance 6.30E-03 - -set_wire_rc -layer M3 diff --git a/flow/platforms/asap7/verilog/fakeram7_128x64.sv b/flow/platforms/asap7/verilog/fakeram7_128x64.sv new file mode 100644 index 0000000000..d7353e1c65 --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram7_128x64.sv @@ -0,0 +1,10 @@ +(* blackbox *) +module fakeram7_128x64 ( + output reg [63:0] rd_out, + input [6:0] addr_in, + input we_in, + input [63:0] wd_in, + input clk, + input ce_in +); +endmodule diff --git a/flow/platforms/asap7/verilog/fakeram7_256x256.sv b/flow/platforms/asap7/verilog/fakeram7_256x256.sv new file mode 100644 index 0000000000..8f440cbf49 --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram7_256x256.sv @@ -0,0 +1,10 @@ +(* blackbox *) +module fakeram7_256x256 ( + output reg [255:0] rd_out, + input [7:0] addr_in, + input we_in, + input [255:0] wd_in, + input clk, + input ce_in +); +endmodule diff --git a/flow/platforms/asap7/verilog/fakeram7_256x256.v b/flow/platforms/asap7/verilog/fakeram7_256x256.v new file mode 100644 index 0000000000..864f474766 --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram7_256x256.v @@ -0,0 +1,70 @@ +module fakeram7_256x256 +( + rd_out, + addr_in, + we_in, + wd_in, + clk, + ce_in +); + parameter BITS = 256; + parameter WORD_DEPTH = 256; + parameter ADDR_WIDTH = 8; + parameter corrupt_mem_on_X_p = 1; + + output reg [BITS-1:0] rd_out; + input [ADDR_WIDTH-1:0] addr_in; + input we_in; + input [BITS-1:0] wd_in; + input clk; + input ce_in; + + reg [BITS-1:0] mem [0:WORD_DEPTH-1]; + + integer j; + + always @(posedge clk) + begin + if (ce_in) + begin + //if ((we_in !== 1'b1 && we_in !== 1'b0) && corrupt_mem_on_X_p) + if (corrupt_mem_on_X_p && + ((^we_in === 1'bx) || (^addr_in === 1'bx)) + ) + begin + // WEN or ADDR is unknown, so corrupt entire array (using unsynthesizeable for loop) + for (j = 0; j < WORD_DEPTH; j = j + 1) + mem[j] <= 'x; + $display("warning: ce_in=1, we_in is %b, addr_in = %x in fakeram7_256x256", we_in, addr_in); + end + else if (we_in) + begin + mem[addr_in] <= (wd_in) | (mem[addr_in]); + end + // read + rd_out <= mem[addr_in]; + end + else + begin + // Make sure read fails if ce_in is low + rd_out <= 'x; + end + end + + // Timing check placeholders (will be replaced during SDF back-annotation) + reg notifier; + specify + // Delay from clk to rd_out + (posedge clk *> rd_out) = (0, 0); + + // Timing checks + $width (posedge clk, 0, 0, notifier); + $width (negedge clk, 0, 0, notifier); + $period (posedge clk, 0, notifier); + $setuphold (posedge clk, we_in, 0, 0, notifier); + $setuphold (posedge clk, ce_in, 0, 0, notifier); + $setuphold (posedge clk, addr_in, 0, 0, notifier); + $setuphold (posedge clk, wd_in, 0, 0, notifier); + endspecify + +endmodule diff --git a/flow/platforms/asap7/verilog/fakeram7_64x25.sv b/flow/platforms/asap7/verilog/fakeram7_64x25.sv new file mode 100644 index 0000000000..4d2c60724d --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram7_64x25.sv @@ -0,0 +1,10 @@ +(* blackbox *) +module fakeram7_64x25 ( + output reg [24:0] rd_out, + input [5:0] addr_in, + input we_in, + input [24:0] wd_in, + input clk, + input ce_in +); +endmodule diff --git a/flow/platforms/asap7/verilog/fakeram7_64x256.sv b/flow/platforms/asap7/verilog/fakeram7_64x256.sv new file mode 100644 index 0000000000..b87ffae7d7 --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram7_64x256.sv @@ -0,0 +1,10 @@ +(* blackbox *) +module fakeram7_64x256 ( + output reg [255:0] rd_out, + input [5:0] addr_in, + input we_in, + input [255:0] wd_in, + input clk, + input ce_in +); +endmodule diff --git a/flow/platforms/asap7/verilog/fakeram7_64x28.sv b/flow/platforms/asap7/verilog/fakeram7_64x28.sv new file mode 100644 index 0000000000..7ed704addd --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram7_64x28.sv @@ -0,0 +1,10 @@ +(* blackbox *) +module fakeram7_64x28 ( + output reg [27:0] rd_out, + input [5:0] addr_in, + input we_in, + input [27:0] wd_in, + input clk, + input ce_in +); +endmodule diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_LVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_LVT_TT_201020.v new file mode 100644 index 0000000000..67002d6142 --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_LVT_TT_201020.v @@ -0,0 +1,3627 @@ +// BSD 3-Clause License +// +// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_AO_LVT_TT_201020 created by Liberate 18.1.0.293 on Sat Nov 28 03:36:02 MST 2020 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module A2O1A1Ixp33_ASAP7_75t_L (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar); + or (Y, int_fwire_1, int_fwire_0, C__bar); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module A2O1A1O1Ixp25_ASAP7_75t_L (Y, A1, A2, B, C, D); + output Y; + input A1, A2, B, C, D; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, D__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2; + + not (D__bar, D); + not (C__bar, C); + and (int_fwire_0, C__bar, D__bar); + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_1, A2__bar, B__bar, D__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B__bar, D__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO211x2_ASAP7_75t_L (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire int_fwire_0; + + and (int_fwire_0, A1, A2); + or (Y, int_fwire_0, B, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO21x1_ASAP7_75t_L (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire int_fwire_0; + + and (int_fwire_0, A1, A2); + or (Y, int_fwire_0, B); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO21x2_ASAP7_75t_L (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire int_fwire_0; + + and (int_fwire_0, A1, A2); + or (Y, int_fwire_0, B); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO221x1_ASAP7_75t_L (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2); + or (Y, int_fwire_1, int_fwire_0, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO221x2_ASAP7_75t_L (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2); + or (Y, int_fwire_1, int_fwire_0, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO222x2_ASAP7_75t_L (Y, A1, A2, B1, B2, C1, C2); + output Y; + input A1, A2, B1, B2, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2); + and (int_fwire_1, B1, B2); + and (int_fwire_2, A1, A2); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO22x1_ASAP7_75t_L (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2); + or (Y, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO22x2_ASAP7_75t_L (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2); + or (Y, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO31x2_ASAP7_75t_L (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire int_fwire_0; + + and (int_fwire_0, A1, A2, A3); + or (Y, int_fwire_0, B); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO322x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, C1, C2); + output Y; + input A1, A2, A3, B1, B2, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2); + and (int_fwire_1, B1, B2); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO32x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2); + output Y; + input A1, A2, A3, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO32x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2); + output Y; + input A1, A2, A3, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO331x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C); + output Y; + input A1, A2, A3, B1, B2, B3, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2, B3); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO331x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C); + output Y; + input A1, A2, A3, B1, B2, B3, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2, B3); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO332x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2); + and (int_fwire_1, B1, B2, B3); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO332x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2); + and (int_fwire_1, B1, B2, B3); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO333x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2, C3); + and (int_fwire_1, B1, B2, B3); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO333x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2, C3); + and (int_fwire_1, B1, B2, B3); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO33x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3); + output Y; + input A1, A2, A3, B1, B2, B3; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2, B3); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3) | (A2 & A3 & ~B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3) | (A1 & A3 & ~B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3) | (A1 & A2 & ~B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3) | (~A1 & ~A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3) | (~A1 & ~A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2) | (~A1 & ~A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI211x1_ASAP7_75t_L (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar, C__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~C)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI211xp5_ASAP7_75t_L (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar, C__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~C)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI21x1_ASAP7_75t_L (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0, int_fwire_1; + + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + if ((~A1 & ~A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI21xp33_ASAP7_75t_L (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0, int_fwire_1; + + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + if ((~A1 & ~A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI21xp5_ASAP7_75t_L (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0, int_fwire_1; + + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + if ((~A1 & ~A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI221x1_ASAP7_75t_L (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2, int_fwire_3; + + not (C__bar, C); + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar, C__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar, C__bar); + and (int_fwire_3, A1__bar, B1__bar, C__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & ~B2) | (~A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI221xp5_ASAP7_75t_L (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2, int_fwire_3; + + not (C__bar, C); + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar, C__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar, C__bar); + and (int_fwire_3, A1__bar, B1__bar, C__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI222xp33_ASAP7_75t_L (Y, A1, A2, B1, B2, C1, C2); + output Y; + input A1, A2, B1, B2, C1, C2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C1__bar, C2__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7; + + not (C2__bar, C2); + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar, C2__bar); + not (C1__bar, C1); + and (int_fwire_1, A2__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_2, A2__bar, B1__bar, C2__bar); + and (int_fwire_3, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_4, A1__bar, B2__bar, C2__bar); + and (int_fwire_5, A1__bar, B2__bar, C1__bar); + and (int_fwire_6, A1__bar, B1__bar, C2__bar); + and (int_fwire_7, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & B1 & ~B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & ~C1 & ~C2) | (A2 & ~B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & B1 & ~B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & ~C1 & ~C2) | (A1 & ~B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI22x1_ASAP7_75t_L (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3; + + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar); + and (int_fwire_3, A1__bar, B1__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI22xp33_ASAP7_75t_L (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3; + + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar); + and (int_fwire_3, A1__bar, B1__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI22xp5_ASAP7_75t_L (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3; + + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar); + and (int_fwire_3, A1__bar, B1__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI311xp33_ASAP7_75t_L (Y, A1, A2, A3, B, C); + output Y; + input A1, A2, A3, B, C; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, C__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2; + + not (C__bar, C); + not (B__bar, B); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B__bar, C__bar); + not (A2__bar, A2); + and (int_fwire_1, A2__bar, B__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B__bar, C__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & A3 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & A3 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3 & ~C) | (~A1 & ~A2 & A3 & ~C)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~C)) + (B => Y) = 0; + if ((A1 & A2 & ~A3 & ~B)) + (C => Y) = 0; + if ((A1 & ~A2 & A3 & ~B)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B) | (~A1 & ~A2 & A3 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI31xp33_ASAP7_75t_L (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2; + + not (B__bar, B); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B__bar); + not (A2__bar, A2); + and (int_fwire_1, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & ~A3)) + (B => Y) = 0; + if ((A1 & ~A2 & A3)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & A2 & A3)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3) | (~A1 & ~A2 & A3)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~A3)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI31xp67_ASAP7_75t_L (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2; + + not (B__bar, B); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B__bar); + not (A2__bar, A2); + and (int_fwire_1, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & ~A3)) + (B => Y) = 0; + if ((A1 & ~A2 & A3)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & A2 & A3)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3) | (~A1 & ~A2 & A3)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~A3)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI321xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, C); + output Y; + input A1, A2, A3, B1, B2, C; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, C__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + + not (C__bar, C); + not (B2__bar, B2); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B2__bar, C__bar); + not (B1__bar, B1); + and (int_fwire_1, A3__bar, B1__bar, C__bar); + not (A2__bar, A2); + and (int_fwire_2, A2__bar, B2__bar, C__bar); + and (int_fwire_3, A2__bar, B1__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_4, A1__bar, B2__bar, C__bar); + and (int_fwire_5, A1__bar, B1__bar, C__bar); + or (Y, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~C)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & ~C) | (~A1 & ~A2 & A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~C) | (~A1 & ~A2 & A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2) | (~A1 & ~A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2) | (~A1 & ~A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2) | (~A1 & ~A2 & A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI322xp5_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, C1, C2); + output Y; + input A1, A2, A3, B1, B2, C1, C2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, C1__bar; + wire C2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3, int_fwire_4; + wire int_fwire_5, int_fwire_6, int_fwire_7; + wire int_fwire_8, int_fwire_9, int_fwire_10; + wire int_fwire_11; + + not (C2__bar, C2); + not (B2__bar, B2); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B2__bar, C2__bar); + not (C1__bar, C1); + and (int_fwire_1, A3__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_2, A3__bar, B1__bar, C2__bar); + and (int_fwire_3, A3__bar, B1__bar, C1__bar); + not (A2__bar, A2); + and (int_fwire_4, A2__bar, B2__bar, C2__bar); + and (int_fwire_5, A2__bar, B2__bar, C1__bar); + and (int_fwire_6, A2__bar, B1__bar, C2__bar); + and (int_fwire_7, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_8, A1__bar, B2__bar, C2__bar); + and (int_fwire_9, A1__bar, B2__bar, C1__bar); + and (int_fwire_10, A1__bar, B1__bar, C2__bar); + and (int_fwire_11, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & ~C1 & C2) | (~A1 & ~A2 & A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI32xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2); + output Y; + input A1, A2, A3, B1, B2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2, int_fwire_3; + wire int_fwire_4, int_fwire_5; + + not (B2__bar, B2); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_1, A3__bar, B1__bar); + not (A2__bar, A2); + and (int_fwire_2, A2__bar, B2__bar); + and (int_fwire_3, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_4, A1__bar, B2__bar); + and (int_fwire_5, A1__bar, B1__bar); + or (Y, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & ~B2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2) | (~A1 & ~A2 & A3 & B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1) | (~A1 & ~A2 & A3 & B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI331xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1); + output Y; + input A1, A2, A3, B1, B2, B3, C1; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3, int_fwire_4; + wire int_fwire_5, int_fwire_6, int_fwire_7; + wire int_fwire_8; + + not (C1__bar, C1); + not (B3__bar, B3); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B3__bar, C1__bar); + not (B2__bar, B2); + and (int_fwire_1, A3__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_2, A3__bar, B1__bar, C1__bar); + not (A2__bar, A2); + and (int_fwire_3, A2__bar, B3__bar, C1__bar); + and (int_fwire_4, A2__bar, B2__bar, C1__bar); + and (int_fwire_5, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_6, A1__bar, B3__bar, C1__bar); + and (int_fwire_7, A1__bar, B2__bar, C1__bar); + and (int_fwire_8, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI332xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, C2__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2, int_fwire_3; + wire int_fwire_4, int_fwire_5, int_fwire_6; + wire int_fwire_7, int_fwire_8, int_fwire_9; + wire int_fwire_10, int_fwire_11, int_fwire_12; + wire int_fwire_13, int_fwire_14, int_fwire_15; + wire int_fwire_16, int_fwire_17; + + not (C2__bar, C2); + not (B3__bar, B3); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B3__bar, C2__bar); + not (C1__bar, C1); + and (int_fwire_1, A3__bar, B3__bar, C1__bar); + not (B2__bar, B2); + and (int_fwire_2, A3__bar, B2__bar, C2__bar); + and (int_fwire_3, A3__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_4, A3__bar, B1__bar, C2__bar); + and (int_fwire_5, A3__bar, B1__bar, C1__bar); + not (A2__bar, A2); + and (int_fwire_6, A2__bar, B3__bar, C2__bar); + and (int_fwire_7, A2__bar, B3__bar, C1__bar); + and (int_fwire_8, A2__bar, B2__bar, C2__bar); + and (int_fwire_9, A2__bar, B2__bar, C1__bar); + and (int_fwire_10, A2__bar, B1__bar, C2__bar); + and (int_fwire_11, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_12, A1__bar, B3__bar, C2__bar); + and (int_fwire_13, A1__bar, B3__bar, C1__bar); + and (int_fwire_14, A1__bar, B2__bar, C2__bar); + and (int_fwire_15, A1__bar, B2__bar, C1__bar); + and (int_fwire_16, A1__bar, B1__bar, C2__bar); + and (int_fwire_17, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI333xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, C2__bar, C3__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + wire int_fwire_18, int_fwire_19, int_fwire_20; + wire int_fwire_21, int_fwire_22, int_fwire_23; + wire int_fwire_24, int_fwire_25, int_fwire_26; + + not (C3__bar, C3); + not (B3__bar, B3); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B3__bar, C3__bar); + not (C2__bar, C2); + and (int_fwire_1, A3__bar, B3__bar, C2__bar); + not (C1__bar, C1); + and (int_fwire_2, A3__bar, B3__bar, C1__bar); + not (B2__bar, B2); + and (int_fwire_3, A3__bar, B2__bar, C3__bar); + and (int_fwire_4, A3__bar, B2__bar, C2__bar); + and (int_fwire_5, A3__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_6, A3__bar, B1__bar, C3__bar); + and (int_fwire_7, A3__bar, B1__bar, C2__bar); + and (int_fwire_8, A3__bar, B1__bar, C1__bar); + not (A2__bar, A2); + and (int_fwire_9, A2__bar, B3__bar, C3__bar); + and (int_fwire_10, A2__bar, B3__bar, C2__bar); + and (int_fwire_11, A2__bar, B3__bar, C1__bar); + and (int_fwire_12, A2__bar, B2__bar, C3__bar); + and (int_fwire_13, A2__bar, B2__bar, C2__bar); + and (int_fwire_14, A2__bar, B2__bar, C1__bar); + and (int_fwire_15, A2__bar, B1__bar, C3__bar); + and (int_fwire_16, A2__bar, B1__bar, C2__bar); + and (int_fwire_17, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_18, A1__bar, B3__bar, C3__bar); + and (int_fwire_19, A1__bar, B3__bar, C2__bar); + and (int_fwire_20, A1__bar, B3__bar, C1__bar); + and (int_fwire_21, A1__bar, B2__bar, C3__bar); + and (int_fwire_22, A1__bar, B2__bar, C2__bar); + and (int_fwire_23, A1__bar, B2__bar, C1__bar); + and (int_fwire_24, A1__bar, B1__bar, C3__bar); + and (int_fwire_25, A1__bar, B1__bar, C2__bar); + and (int_fwire_26, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI33xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3); + output Y; + input A1, A2, A3, B1, B2, B3; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + + not (B3__bar, B3); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B3__bar); + not (B2__bar, B2); + and (int_fwire_1, A3__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_2, A3__bar, B1__bar); + not (A2__bar, A2); + and (int_fwire_3, A2__bar, B3__bar); + and (int_fwire_4, A2__bar, B2__bar); + and (int_fwire_5, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_6, A1__bar, B3__bar); + and (int_fwire_7, A1__bar, B2__bar); + and (int_fwire_8, A1__bar, B1__bar); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3) | (A2 & A3 & ~B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3) | (A1 & A3 & ~B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3) | (A1 & A2 & ~B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3) | (~A1 & A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3) | (~A1 & A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2) | (~A1 & A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + endspecify +endmodule +`endcelldefine + diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_SLVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_SLVT_TT_201020.v new file mode 100644 index 0000000000..b33fb13e52 --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_SLVT_TT_201020.v @@ -0,0 +1,3627 @@ +// BSD 3-Clause License +// +// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_AO_SLVT_TT_201020 created by Liberate 18.1.0.293 on Sat Nov 28 03:36:02 MST 2020 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module A2O1A1Ixp33_ASAP7_75t_SL (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar); + or (Y, int_fwire_1, int_fwire_0, C__bar); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module A2O1A1O1Ixp25_ASAP7_75t_SL (Y, A1, A2, B, C, D); + output Y; + input A1, A2, B, C, D; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, D__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2; + + not (D__bar, D); + not (C__bar, C); + and (int_fwire_0, C__bar, D__bar); + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_1, A2__bar, B__bar, D__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B__bar, D__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO211x2_ASAP7_75t_SL (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire int_fwire_0; + + and (int_fwire_0, A1, A2); + or (Y, int_fwire_0, B, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO21x1_ASAP7_75t_SL (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire int_fwire_0; + + and (int_fwire_0, A1, A2); + or (Y, int_fwire_0, B); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO21x2_ASAP7_75t_SL (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire int_fwire_0; + + and (int_fwire_0, A1, A2); + or (Y, int_fwire_0, B); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO221x1_ASAP7_75t_SL (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2); + or (Y, int_fwire_1, int_fwire_0, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO221x2_ASAP7_75t_SL (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2); + or (Y, int_fwire_1, int_fwire_0, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO222x2_ASAP7_75t_SL (Y, A1, A2, B1, B2, C1, C2); + output Y; + input A1, A2, B1, B2, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2); + and (int_fwire_1, B1, B2); + and (int_fwire_2, A1, A2); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO22x1_ASAP7_75t_SL (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2); + or (Y, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO22x2_ASAP7_75t_SL (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2); + or (Y, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO31x2_ASAP7_75t_SL (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire int_fwire_0; + + and (int_fwire_0, A1, A2, A3); + or (Y, int_fwire_0, B); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO322x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, C1, C2); + output Y; + input A1, A2, A3, B1, B2, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2); + and (int_fwire_1, B1, B2); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO32x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2); + output Y; + input A1, A2, A3, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO32x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2); + output Y; + input A1, A2, A3, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO331x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C); + output Y; + input A1, A2, A3, B1, B2, B3, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2, B3); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO331x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C); + output Y; + input A1, A2, A3, B1, B2, B3, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2, B3); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO332x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2); + and (int_fwire_1, B1, B2, B3); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO332x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2); + and (int_fwire_1, B1, B2, B3); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO333x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2, C3); + and (int_fwire_1, B1, B2, B3); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO333x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2, C3); + and (int_fwire_1, B1, B2, B3); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO33x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3); + output Y; + input A1, A2, A3, B1, B2, B3; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2, B3); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3) | (A2 & A3 & ~B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3) | (A1 & A3 & ~B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3) | (A1 & A2 & ~B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3) | (~A1 & ~A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3) | (~A1 & ~A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2) | (~A1 & ~A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI211x1_ASAP7_75t_SL (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar, C__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~C)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI211xp5_ASAP7_75t_SL (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar, C__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~C)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI21x1_ASAP7_75t_SL (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0, int_fwire_1; + + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + if ((~A1 & ~A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI21xp33_ASAP7_75t_SL (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0, int_fwire_1; + + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + if ((~A1 & ~A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI21xp5_ASAP7_75t_SL (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0, int_fwire_1; + + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + if ((~A1 & ~A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI221x1_ASAP7_75t_SL (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2, int_fwire_3; + + not (C__bar, C); + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar, C__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar, C__bar); + and (int_fwire_3, A1__bar, B1__bar, C__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & ~B2) | (~A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI221xp5_ASAP7_75t_SL (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2, int_fwire_3; + + not (C__bar, C); + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar, C__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar, C__bar); + and (int_fwire_3, A1__bar, B1__bar, C__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI222xp33_ASAP7_75t_SL (Y, A1, A2, B1, B2, C1, C2); + output Y; + input A1, A2, B1, B2, C1, C2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C1__bar, C2__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7; + + not (C2__bar, C2); + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar, C2__bar); + not (C1__bar, C1); + and (int_fwire_1, A2__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_2, A2__bar, B1__bar, C2__bar); + and (int_fwire_3, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_4, A1__bar, B2__bar, C2__bar); + and (int_fwire_5, A1__bar, B2__bar, C1__bar); + and (int_fwire_6, A1__bar, B1__bar, C2__bar); + and (int_fwire_7, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & B1 & ~B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & ~C1 & ~C2) | (A2 & ~B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & B1 & ~B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & ~C1 & ~C2) | (A1 & ~B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI22x1_ASAP7_75t_SL (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3; + + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar); + and (int_fwire_3, A1__bar, B1__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI22xp33_ASAP7_75t_SL (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3; + + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar); + and (int_fwire_3, A1__bar, B1__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI22xp5_ASAP7_75t_SL (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3; + + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar); + and (int_fwire_3, A1__bar, B1__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI311xp33_ASAP7_75t_SL (Y, A1, A2, A3, B, C); + output Y; + input A1, A2, A3, B, C; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, C__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2; + + not (C__bar, C); + not (B__bar, B); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B__bar, C__bar); + not (A2__bar, A2); + and (int_fwire_1, A2__bar, B__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B__bar, C__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & A3 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & A3 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3 & ~C) | (~A1 & ~A2 & A3 & ~C)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~C)) + (B => Y) = 0; + if ((A1 & A2 & ~A3 & ~B)) + (C => Y) = 0; + if ((A1 & ~A2 & A3 & ~B)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B) | (~A1 & ~A2 & A3 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI31xp33_ASAP7_75t_SL (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2; + + not (B__bar, B); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B__bar); + not (A2__bar, A2); + and (int_fwire_1, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & ~A3)) + (B => Y) = 0; + if ((A1 & ~A2 & A3)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & A2 & A3)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3) | (~A1 & ~A2 & A3)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~A3)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI31xp67_ASAP7_75t_SL (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2; + + not (B__bar, B); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B__bar); + not (A2__bar, A2); + and (int_fwire_1, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & ~A3)) + (B => Y) = 0; + if ((A1 & ~A2 & A3)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & A2 & A3)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3) | (~A1 & ~A2 & A3)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~A3)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI321xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, C); + output Y; + input A1, A2, A3, B1, B2, C; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, C__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + + not (C__bar, C); + not (B2__bar, B2); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B2__bar, C__bar); + not (B1__bar, B1); + and (int_fwire_1, A3__bar, B1__bar, C__bar); + not (A2__bar, A2); + and (int_fwire_2, A2__bar, B2__bar, C__bar); + and (int_fwire_3, A2__bar, B1__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_4, A1__bar, B2__bar, C__bar); + and (int_fwire_5, A1__bar, B1__bar, C__bar); + or (Y, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~C)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & ~C) | (~A1 & ~A2 & A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~C) | (~A1 & ~A2 & A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2) | (~A1 & ~A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2) | (~A1 & ~A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2) | (~A1 & ~A2 & A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI322xp5_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, C1, C2); + output Y; + input A1, A2, A3, B1, B2, C1, C2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, C1__bar; + wire C2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3, int_fwire_4; + wire int_fwire_5, int_fwire_6, int_fwire_7; + wire int_fwire_8, int_fwire_9, int_fwire_10; + wire int_fwire_11; + + not (C2__bar, C2); + not (B2__bar, B2); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B2__bar, C2__bar); + not (C1__bar, C1); + and (int_fwire_1, A3__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_2, A3__bar, B1__bar, C2__bar); + and (int_fwire_3, A3__bar, B1__bar, C1__bar); + not (A2__bar, A2); + and (int_fwire_4, A2__bar, B2__bar, C2__bar); + and (int_fwire_5, A2__bar, B2__bar, C1__bar); + and (int_fwire_6, A2__bar, B1__bar, C2__bar); + and (int_fwire_7, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_8, A1__bar, B2__bar, C2__bar); + and (int_fwire_9, A1__bar, B2__bar, C1__bar); + and (int_fwire_10, A1__bar, B1__bar, C2__bar); + and (int_fwire_11, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & ~C1 & C2) | (~A1 & ~A2 & A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI32xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2); + output Y; + input A1, A2, A3, B1, B2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2, int_fwire_3; + wire int_fwire_4, int_fwire_5; + + not (B2__bar, B2); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_1, A3__bar, B1__bar); + not (A2__bar, A2); + and (int_fwire_2, A2__bar, B2__bar); + and (int_fwire_3, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_4, A1__bar, B2__bar); + and (int_fwire_5, A1__bar, B1__bar); + or (Y, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & ~B2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2) | (~A1 & ~A2 & A3 & B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1) | (~A1 & ~A2 & A3 & B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI331xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1); + output Y; + input A1, A2, A3, B1, B2, B3, C1; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3, int_fwire_4; + wire int_fwire_5, int_fwire_6, int_fwire_7; + wire int_fwire_8; + + not (C1__bar, C1); + not (B3__bar, B3); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B3__bar, C1__bar); + not (B2__bar, B2); + and (int_fwire_1, A3__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_2, A3__bar, B1__bar, C1__bar); + not (A2__bar, A2); + and (int_fwire_3, A2__bar, B3__bar, C1__bar); + and (int_fwire_4, A2__bar, B2__bar, C1__bar); + and (int_fwire_5, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_6, A1__bar, B3__bar, C1__bar); + and (int_fwire_7, A1__bar, B2__bar, C1__bar); + and (int_fwire_8, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI332xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, C2__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2, int_fwire_3; + wire int_fwire_4, int_fwire_5, int_fwire_6; + wire int_fwire_7, int_fwire_8, int_fwire_9; + wire int_fwire_10, int_fwire_11, int_fwire_12; + wire int_fwire_13, int_fwire_14, int_fwire_15; + wire int_fwire_16, int_fwire_17; + + not (C2__bar, C2); + not (B3__bar, B3); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B3__bar, C2__bar); + not (C1__bar, C1); + and (int_fwire_1, A3__bar, B3__bar, C1__bar); + not (B2__bar, B2); + and (int_fwire_2, A3__bar, B2__bar, C2__bar); + and (int_fwire_3, A3__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_4, A3__bar, B1__bar, C2__bar); + and (int_fwire_5, A3__bar, B1__bar, C1__bar); + not (A2__bar, A2); + and (int_fwire_6, A2__bar, B3__bar, C2__bar); + and (int_fwire_7, A2__bar, B3__bar, C1__bar); + and (int_fwire_8, A2__bar, B2__bar, C2__bar); + and (int_fwire_9, A2__bar, B2__bar, C1__bar); + and (int_fwire_10, A2__bar, B1__bar, C2__bar); + and (int_fwire_11, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_12, A1__bar, B3__bar, C2__bar); + and (int_fwire_13, A1__bar, B3__bar, C1__bar); + and (int_fwire_14, A1__bar, B2__bar, C2__bar); + and (int_fwire_15, A1__bar, B2__bar, C1__bar); + and (int_fwire_16, A1__bar, B1__bar, C2__bar); + and (int_fwire_17, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI333xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, C2__bar, C3__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + wire int_fwire_18, int_fwire_19, int_fwire_20; + wire int_fwire_21, int_fwire_22, int_fwire_23; + wire int_fwire_24, int_fwire_25, int_fwire_26; + + not (C3__bar, C3); + not (B3__bar, B3); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B3__bar, C3__bar); + not (C2__bar, C2); + and (int_fwire_1, A3__bar, B3__bar, C2__bar); + not (C1__bar, C1); + and (int_fwire_2, A3__bar, B3__bar, C1__bar); + not (B2__bar, B2); + and (int_fwire_3, A3__bar, B2__bar, C3__bar); + and (int_fwire_4, A3__bar, B2__bar, C2__bar); + and (int_fwire_5, A3__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_6, A3__bar, B1__bar, C3__bar); + and (int_fwire_7, A3__bar, B1__bar, C2__bar); + and (int_fwire_8, A3__bar, B1__bar, C1__bar); + not (A2__bar, A2); + and (int_fwire_9, A2__bar, B3__bar, C3__bar); + and (int_fwire_10, A2__bar, B3__bar, C2__bar); + and (int_fwire_11, A2__bar, B3__bar, C1__bar); + and (int_fwire_12, A2__bar, B2__bar, C3__bar); + and (int_fwire_13, A2__bar, B2__bar, C2__bar); + and (int_fwire_14, A2__bar, B2__bar, C1__bar); + and (int_fwire_15, A2__bar, B1__bar, C3__bar); + and (int_fwire_16, A2__bar, B1__bar, C2__bar); + and (int_fwire_17, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_18, A1__bar, B3__bar, C3__bar); + and (int_fwire_19, A1__bar, B3__bar, C2__bar); + and (int_fwire_20, A1__bar, B3__bar, C1__bar); + and (int_fwire_21, A1__bar, B2__bar, C3__bar); + and (int_fwire_22, A1__bar, B2__bar, C2__bar); + and (int_fwire_23, A1__bar, B2__bar, C1__bar); + and (int_fwire_24, A1__bar, B1__bar, C3__bar); + and (int_fwire_25, A1__bar, B1__bar, C2__bar); + and (int_fwire_26, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI33xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3); + output Y; + input A1, A2, A3, B1, B2, B3; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + + not (B3__bar, B3); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B3__bar); + not (B2__bar, B2); + and (int_fwire_1, A3__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_2, A3__bar, B1__bar); + not (A2__bar, A2); + and (int_fwire_3, A2__bar, B3__bar); + and (int_fwire_4, A2__bar, B2__bar); + and (int_fwire_5, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_6, A1__bar, B3__bar); + and (int_fwire_7, A1__bar, B2__bar); + and (int_fwire_8, A1__bar, B1__bar); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3) | (A2 & A3 & ~B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3) | (A1 & A3 & ~B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3) | (A1 & A2 & ~B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3) | (~A1 & A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3) | (~A1 & A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2) | (~A1 & A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + endspecify +endmodule +`endcelldefine + diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_LVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_LVT_TT_201020.v new file mode 100644 index 0000000000..8d929214e2 --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_LVT_TT_201020.v @@ -0,0 +1,663 @@ +// BSD 3-Clause License +// +// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_INVBUF_LVT_TT_201020 created by Liberate 18.1.0.293 on Mon Dec 7 13:57:05 MST 2020 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx10_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx12_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx12f_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx16f_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx24_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx2_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx3_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx4_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx4f_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx5_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx6f_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx8_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx10_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx11_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx12_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx14_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx16_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx20_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx5p33_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx6p67_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx8_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx9p33_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HB1xp67_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HB2xp67_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HB3xp67_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HB4xp67_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx11_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx13_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx1_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx2_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx3_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx4_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx5_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx6_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx8_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVxp33_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVxp67_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + + diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_SLVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_SLVT_TT_201020.v new file mode 100644 index 0000000000..7a29306535 --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_SLVT_TT_201020.v @@ -0,0 +1,664 @@ +// BSD 3-Clause License +// +// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_INVBUF_SLVT_TT_201020 created by Liberate 18.1.0.293 on Mon Dec 7 13:57:05 MST 2020 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx10_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx12_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx12f_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx16f_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx24_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx2_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx3_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx4_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx4f_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx5_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx6f_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx8_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx10_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx11_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx12_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx14_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx16_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx20_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx5p33_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx6p67_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx8_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx9p33_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HB1xp67_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HB2xp67_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HB3xp67_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HB4xp67_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx11_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx13_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx1_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx2_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx3_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx4_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx5_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx6_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx8_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVxp33_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVxp67_ASAP7_75t_SL + (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + + diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_LVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_LVT_TT_201020.v new file mode 100644 index 0000000000..65fc6836e8 --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_LVT_TT_201020.v @@ -0,0 +1,5243 @@ +// BSD 3-Clause License +// +// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_OA_LVT_TT_201020 created by Liberate 18.1.0.293 on Sat Nov 28 13:55:21 MST 2020 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module O2A1O1Ixp33_ASAP7_75t_L (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + and (int_fwire_0, B__bar, C__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, C__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~C)) + (B => Y) = 0; + if ((A1 & A2 & ~B)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module O2A1O1Ixp5_ASAP7_75t_L (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + and (int_fwire_0, B__bar, C__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, C__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~C)) + (B => Y) = 0; + if ((A2 & ~B)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA211x2_ASAP7_75t_L (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, A2, B, C); + and (int_fwire_1, A1, B, C); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2 & C)) + (B => Y) = 0; + if ((A1 & ~A2 & C)) + (B => Y) = 0; + if ((~A1 & A2 & C)) + (B => Y) = 0; + if ((A1 & A2 & B)) + (C => Y) = 0; + if ((A1 & ~A2 & B)) + (C => Y) = 0; + if ((~A1 & A2 & B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA21x2_ASAP7_75t_L (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, A2, B); + and (int_fwire_1, A1, B); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2)) + (B => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA221x2_ASAP7_75t_L (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3; + + and (int_fwire_0, A2, B2, C); + and (int_fwire_1, A2, B1, C); + and (int_fwire_2, A1, B2, C); + and (int_fwire_3, A1, B1, C); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & C)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2 & C)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & ~B1 & B2) | (~A1 & A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA222x2_ASAP7_75t_L (Y, A1, A2, B1, B2, C1, C2); + output Y; + input A1, A2, B1, B2, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7; + + and (int_fwire_0, A2, B2, C2); + and (int_fwire_1, A2, B2, C1); + and (int_fwire_2, A2, B1, C2); + and (int_fwire_3, A2, B1, C1); + and (int_fwire_4, A1, B2, C2); + and (int_fwire_5, A1, B2, C1); + and (int_fwire_6, A1, B1, C2); + and (int_fwire_7, A1, B1, C1); + or (Y, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & B2 & C1 & ~C2) | (~A2 & B1 & ~B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & B2 & C1 & ~C2) | (~A1 & B1 & ~B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA22x2_ASAP7_75t_L (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3; + + and (int_fwire_0, A2, B2); + and (int_fwire_1, A2, B1); + and (int_fwire_2, A1, B2); + and (int_fwire_3, A1, B1); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA31x2_ASAP7_75t_L (Y, A1, A2, A3, B1); + output Y; + input A1, A2, A3, B1; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, A3, B1); + and (int_fwire_1, A2, B1); + and (int_fwire_2, A1, B1); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & A3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3) | (~A1 & A2 & A3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3)) + (B1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA331x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1); + output Y; + input A1, A2, A3, B1, B2, B3, C1; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + + and (int_fwire_0, A3, B3, C1); + and (int_fwire_1, A3, B2, C1); + and (int_fwire_2, A3, B1, C1); + and (int_fwire_3, A2, B3, C1); + and (int_fwire_4, A2, B2, C1); + and (int_fwire_5, A2, B1, C1); + and (int_fwire_6, A1, B3, C1); + and (int_fwire_7, A1, B2, C1); + and (int_fwire_8, A1, B1, C1); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA331x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1); + output Y; + input A1, A2, A3, B1, B2, B3, C1; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + + and (int_fwire_0, A3, B3, C1); + and (int_fwire_1, A3, B2, C1); + and (int_fwire_2, A3, B1, C1); + and (int_fwire_3, A2, B3, C1); + and (int_fwire_4, A2, B2, C1); + and (int_fwire_5, A2, B1, C1); + and (int_fwire_6, A1, B3, C1); + and (int_fwire_7, A1, B2, C1); + and (int_fwire_8, A1, B1, C1); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA332x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + + and (int_fwire_0, A3, B3, C2); + and (int_fwire_1, A3, B3, C1); + and (int_fwire_2, A3, B2, C2); + and (int_fwire_3, A3, B2, C1); + and (int_fwire_4, A3, B1, C2); + and (int_fwire_5, A3, B1, C1); + and (int_fwire_6, A2, B3, C2); + and (int_fwire_7, A2, B3, C1); + and (int_fwire_8, A2, B2, C2); + and (int_fwire_9, A2, B2, C1); + and (int_fwire_10, A2, B1, C2); + and (int_fwire_11, A2, B1, C1); + and (int_fwire_12, A1, B3, C2); + and (int_fwire_13, A1, B3, C1); + and (int_fwire_14, A1, B2, C2); + and (int_fwire_15, A1, B2, C1); + and (int_fwire_16, A1, B1, C2); + and (int_fwire_17, A1, B1, C1); + or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA332x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + + and (int_fwire_0, A3, B3, C2); + and (int_fwire_1, A3, B3, C1); + and (int_fwire_2, A3, B2, C2); + and (int_fwire_3, A3, B2, C1); + and (int_fwire_4, A3, B1, C2); + and (int_fwire_5, A3, B1, C1); + and (int_fwire_6, A2, B3, C2); + and (int_fwire_7, A2, B3, C1); + and (int_fwire_8, A2, B2, C2); + and (int_fwire_9, A2, B2, C1); + and (int_fwire_10, A2, B1, C2); + and (int_fwire_11, A2, B1, C1); + and (int_fwire_12, A1, B3, C2); + and (int_fwire_13, A1, B3, C1); + and (int_fwire_14, A1, B2, C2); + and (int_fwire_15, A1, B2, C1); + and (int_fwire_16, A1, B1, C2); + and (int_fwire_17, A1, B1, C1); + or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA333x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + wire int_fwire_18, int_fwire_19, int_fwire_20; + wire int_fwire_21, int_fwire_22, int_fwire_23; + wire int_fwire_24, int_fwire_25, int_fwire_26; + + and (int_fwire_0, A3, B3, C3); + and (int_fwire_1, A3, B3, C2); + and (int_fwire_2, A3, B3, C1); + and (int_fwire_3, A3, B2, C3); + and (int_fwire_4, A3, B2, C2); + and (int_fwire_5, A3, B2, C1); + and (int_fwire_6, A3, B1, C3); + and (int_fwire_7, A3, B1, C2); + and (int_fwire_8, A3, B1, C1); + and (int_fwire_9, A2, B3, C3); + and (int_fwire_10, A2, B3, C2); + and (int_fwire_11, A2, B3, C1); + and (int_fwire_12, A2, B2, C3); + and (int_fwire_13, A2, B2, C2); + and (int_fwire_14, A2, B2, C1); + and (int_fwire_15, A2, B1, C3); + and (int_fwire_16, A2, B1, C2); + and (int_fwire_17, A2, B1, C1); + and (int_fwire_18, A1, B3, C3); + and (int_fwire_19, A1, B3, C2); + and (int_fwire_20, A1, B3, C1); + and (int_fwire_21, A1, B2, C3); + and (int_fwire_22, A1, B2, C2); + and (int_fwire_23, A1, B2, C1); + and (int_fwire_24, A1, B1, C3); + and (int_fwire_25, A1, B1, C2); + and (int_fwire_26, A1, B1, C1); + or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA333x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + wire int_fwire_18, int_fwire_19, int_fwire_20; + wire int_fwire_21, int_fwire_22, int_fwire_23; + wire int_fwire_24, int_fwire_25, int_fwire_26; + + and (int_fwire_0, A3, B3, C3); + and (int_fwire_1, A3, B3, C2); + and (int_fwire_2, A3, B3, C1); + and (int_fwire_3, A3, B2, C3); + and (int_fwire_4, A3, B2, C2); + and (int_fwire_5, A3, B2, C1); + and (int_fwire_6, A3, B1, C3); + and (int_fwire_7, A3, B1, C2); + and (int_fwire_8, A3, B1, C1); + and (int_fwire_9, A2, B3, C3); + and (int_fwire_10, A2, B3, C2); + and (int_fwire_11, A2, B3, C1); + and (int_fwire_12, A2, B2, C3); + and (int_fwire_13, A2, B2, C2); + and (int_fwire_14, A2, B2, C1); + and (int_fwire_15, A2, B1, C3); + and (int_fwire_16, A2, B1, C2); + and (int_fwire_17, A2, B1, C1); + and (int_fwire_18, A1, B3, C3); + and (int_fwire_19, A1, B3, C2); + and (int_fwire_20, A1, B3, C1); + and (int_fwire_21, A1, B2, C3); + and (int_fwire_22, A1, B2, C2); + and (int_fwire_23, A1, B2, C1); + and (int_fwire_24, A1, B1, C3); + and (int_fwire_25, A1, B1, C2); + and (int_fwire_26, A1, B1, C1); + or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA33x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3); + output Y; + input A1, A2, A3, B1, B2, B3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + + and (int_fwire_0, A3, B3); + and (int_fwire_1, A3, B2); + and (int_fwire_2, A3, B1); + and (int_fwire_3, A2, B3); + and (int_fwire_4, A2, B2); + and (int_fwire_5, A2, B1); + and (int_fwire_6, A1, B3); + and (int_fwire_7, A1, B2); + and (int_fwire_8, A1, B1); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & B3) | (~A2 & ~A3 & ~B1 & B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & B3) | (~A1 & ~A3 & ~B1 & B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & B3) | (~A1 & ~A2 & ~B1 & B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B2 & ~B3) | (~A1 & A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2) | (~A1 & A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI211xp5_ASAP7_75t_L (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0; + + not (C__bar, C); + not (B__bar, B); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar); + or (Y, int_fwire_0, B__bar, C__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2 & C)) + (B => Y) = 0; + if ((A1 & ~A2 & C)) + (B => Y) = 0; + if ((~A1 & A2 & C)) + (B => Y) = 0; + if ((A1 & A2 & B)) + (C => Y) = 0; + if ((A1 & ~A2 & B)) + (C => Y) = 0; + if ((~A1 & A2 & B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI21x1_ASAP7_75t_L (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0; + + not (B__bar, B); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2)) + (B => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI21xp33_ASAP7_75t_L (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0; + + not (B__bar, B); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2)) + (B => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI21xp5_ASAP7_75t_L (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0; + + not (B__bar, B); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2)) + (B => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI221xp5_ASAP7_75t_L (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C__bar, int_fwire_0; + wire int_fwire_1; + + not (C__bar, C); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar); + or (Y, int_fwire_1, int_fwire_0, C__bar); + + // Timing + specify + if ((~A2 & B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & C)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2 & C)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI222xp33_ASAP7_75t_L (Y, A1, A2, B1, B2, C1, C2); + output Y; + input A1, A2, B1, B2, C1, C2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C1__bar, C2__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + + not (C2__bar, C2); + not (C1__bar, C1); + and (int_fwire_0, C1__bar, C2__bar); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_1, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, A2__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & B2 & C1 & ~C2) | (~A2 & B1 & ~B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & B2 & C1 & ~C2) | (~A1 & B1 & ~B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI22x1_ASAP7_75t_L (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI22xp33_ASAP7_75t_L (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI22xp5_ASAP7_75t_L (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI311xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, C1); + output Y; + input A1, A2, A3, B1, C1; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, C1__bar, int_fwire_0; + + not (C1__bar, C1); + not (B1__bar, B1); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_0, B1__bar, C1__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & A3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & C1) | (A1 & ~A2 & A3 & C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & B1)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1) | (A1 & ~A2 & A3 & B1)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI31xp33_ASAP7_75t_L (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, int_fwire_0; + + not (B__bar, B); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & A3)) + (B => Y) = 0; + if ((A1 & A2 & ~A3) | (A1 & ~A2 & A3)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & A2 & A3)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & ~A2 & A3)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI31xp67_ASAP7_75t_L (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, int_fwire_0; + + not (B__bar, B); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & A3)) + (B => Y) = 0; + if ((A1 & A2 & ~A3) | (A1 & ~A2 & A3)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & A2 & A3)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & ~A2 & A3)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI321xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, C); + output Y; + input A1, A2, A3, B1, B2, C; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, C__bar; + wire int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_1, int_fwire_0, C__bar); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & C)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & C)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & C) | (A1 & ~A2 & A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & C) | (A1 & ~A2 & A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2) | (A1 & ~A2 & A3 & B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2) | (A1 & ~A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2) | (A1 & ~A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI322xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, C1, C2); + output Y; + input A1, A2, A3, B1, B2, C1, C2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, C1__bar; + wire C2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2; + + not (C2__bar, C2); + not (C1__bar, C1); + and (int_fwire_0, C1__bar, C2__bar); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_1, B1__bar, B2__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI32xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2); + output Y; + input A1, A2, A3, B1, B2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, int_fwire_0; + wire int_fwire_1; + + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2) | (A1 & ~A2 & A3 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1) | (A1 & ~A2 & A3 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI331xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1); + output Y; + input A1, A2, A3, B1, B2, B3, C1; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, int_fwire_0, int_fwire_1; + + not (C1__bar, C1); + not (B3__bar, B3); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar, B3__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_1, int_fwire_0, C1__bar); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI332xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, C2__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2; + + not (C2__bar, C2); + not (C1__bar, C1); + and (int_fwire_0, C1__bar, C2__bar); + not (B3__bar, B3); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_1, B1__bar, B2__bar, B3__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI333xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, C2__bar, C3__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + + not (C3__bar, C3); + not (C2__bar, C2); + not (C1__bar, C1); + and (int_fwire_0, C1__bar, C2__bar, C3__bar); + not (B3__bar, B3); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_1, B1__bar, B2__bar, B3__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI33xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3); + output Y; + input A1, A2, A3, B1, B2, B3; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire int_fwire_0, int_fwire_1; + + not (B3__bar, B3); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar, B3__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3) | (~A2 & ~A3 & B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3) | (~A1 & ~A3 & B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3) | (~A1 & ~A2 & B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B2 & ~B3) | (~A1 & A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2) | (~A1 & A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + endspecify +endmodule +`endcelldefine diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_SLVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_SLVT_TT_201020.v new file mode 100644 index 0000000000..c737d3b31c --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_SLVT_TT_201020.v @@ -0,0 +1,5243 @@ +// BSD 3-Clause License +// +// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_OA_SLVT_TT_201020 created by Liberate 18.1.0.293 on Sat Nov 28 13:55:21 MST 2020 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module O2A1O1Ixp33_ASAP7_75t_SL (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + and (int_fwire_0, B__bar, C__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, C__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~C)) + (B => Y) = 0; + if ((A1 & A2 & ~B)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module O2A1O1Ixp5_ASAP7_75t_SL (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + and (int_fwire_0, B__bar, C__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, C__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~C)) + (B => Y) = 0; + if ((A2 & ~B)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA211x2_ASAP7_75t_SL (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, A2, B, C); + and (int_fwire_1, A1, B, C); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2 & C)) + (B => Y) = 0; + if ((A1 & ~A2 & C)) + (B => Y) = 0; + if ((~A1 & A2 & C)) + (B => Y) = 0; + if ((A1 & A2 & B)) + (C => Y) = 0; + if ((A1 & ~A2 & B)) + (C => Y) = 0; + if ((~A1 & A2 & B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA21x2_ASAP7_75t_SL (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, A2, B); + and (int_fwire_1, A1, B); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2)) + (B => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA221x2_ASAP7_75t_SL (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3; + + and (int_fwire_0, A2, B2, C); + and (int_fwire_1, A2, B1, C); + and (int_fwire_2, A1, B2, C); + and (int_fwire_3, A1, B1, C); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & C)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2 & C)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & ~B1 & B2) | (~A1 & A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA222x2_ASAP7_75t_SL (Y, A1, A2, B1, B2, C1, C2); + output Y; + input A1, A2, B1, B2, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7; + + and (int_fwire_0, A2, B2, C2); + and (int_fwire_1, A2, B2, C1); + and (int_fwire_2, A2, B1, C2); + and (int_fwire_3, A2, B1, C1); + and (int_fwire_4, A1, B2, C2); + and (int_fwire_5, A1, B2, C1); + and (int_fwire_6, A1, B1, C2); + and (int_fwire_7, A1, B1, C1); + or (Y, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & B2 & C1 & ~C2) | (~A2 & B1 & ~B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & B2 & C1 & ~C2) | (~A1 & B1 & ~B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA22x2_ASAP7_75t_SL (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3; + + and (int_fwire_0, A2, B2); + and (int_fwire_1, A2, B1); + and (int_fwire_2, A1, B2); + and (int_fwire_3, A1, B1); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA31x2_ASAP7_75t_SL (Y, A1, A2, A3, B1); + output Y; + input A1, A2, A3, B1; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, A3, B1); + and (int_fwire_1, A2, B1); + and (int_fwire_2, A1, B1); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & A3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3) | (~A1 & A2 & A3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3)) + (B1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA331x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1); + output Y; + input A1, A2, A3, B1, B2, B3, C1; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + + and (int_fwire_0, A3, B3, C1); + and (int_fwire_1, A3, B2, C1); + and (int_fwire_2, A3, B1, C1); + and (int_fwire_3, A2, B3, C1); + and (int_fwire_4, A2, B2, C1); + and (int_fwire_5, A2, B1, C1); + and (int_fwire_6, A1, B3, C1); + and (int_fwire_7, A1, B2, C1); + and (int_fwire_8, A1, B1, C1); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA331x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1); + output Y; + input A1, A2, A3, B1, B2, B3, C1; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + + and (int_fwire_0, A3, B3, C1); + and (int_fwire_1, A3, B2, C1); + and (int_fwire_2, A3, B1, C1); + and (int_fwire_3, A2, B3, C1); + and (int_fwire_4, A2, B2, C1); + and (int_fwire_5, A2, B1, C1); + and (int_fwire_6, A1, B3, C1); + and (int_fwire_7, A1, B2, C1); + and (int_fwire_8, A1, B1, C1); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA332x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + + and (int_fwire_0, A3, B3, C2); + and (int_fwire_1, A3, B3, C1); + and (int_fwire_2, A3, B2, C2); + and (int_fwire_3, A3, B2, C1); + and (int_fwire_4, A3, B1, C2); + and (int_fwire_5, A3, B1, C1); + and (int_fwire_6, A2, B3, C2); + and (int_fwire_7, A2, B3, C1); + and (int_fwire_8, A2, B2, C2); + and (int_fwire_9, A2, B2, C1); + and (int_fwire_10, A2, B1, C2); + and (int_fwire_11, A2, B1, C1); + and (int_fwire_12, A1, B3, C2); + and (int_fwire_13, A1, B3, C1); + and (int_fwire_14, A1, B2, C2); + and (int_fwire_15, A1, B2, C1); + and (int_fwire_16, A1, B1, C2); + and (int_fwire_17, A1, B1, C1); + or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA332x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + + and (int_fwire_0, A3, B3, C2); + and (int_fwire_1, A3, B3, C1); + and (int_fwire_2, A3, B2, C2); + and (int_fwire_3, A3, B2, C1); + and (int_fwire_4, A3, B1, C2); + and (int_fwire_5, A3, B1, C1); + and (int_fwire_6, A2, B3, C2); + and (int_fwire_7, A2, B3, C1); + and (int_fwire_8, A2, B2, C2); + and (int_fwire_9, A2, B2, C1); + and (int_fwire_10, A2, B1, C2); + and (int_fwire_11, A2, B1, C1); + and (int_fwire_12, A1, B3, C2); + and (int_fwire_13, A1, B3, C1); + and (int_fwire_14, A1, B2, C2); + and (int_fwire_15, A1, B2, C1); + and (int_fwire_16, A1, B1, C2); + and (int_fwire_17, A1, B1, C1); + or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA333x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + wire int_fwire_18, int_fwire_19, int_fwire_20; + wire int_fwire_21, int_fwire_22, int_fwire_23; + wire int_fwire_24, int_fwire_25, int_fwire_26; + + and (int_fwire_0, A3, B3, C3); + and (int_fwire_1, A3, B3, C2); + and (int_fwire_2, A3, B3, C1); + and (int_fwire_3, A3, B2, C3); + and (int_fwire_4, A3, B2, C2); + and (int_fwire_5, A3, B2, C1); + and (int_fwire_6, A3, B1, C3); + and (int_fwire_7, A3, B1, C2); + and (int_fwire_8, A3, B1, C1); + and (int_fwire_9, A2, B3, C3); + and (int_fwire_10, A2, B3, C2); + and (int_fwire_11, A2, B3, C1); + and (int_fwire_12, A2, B2, C3); + and (int_fwire_13, A2, B2, C2); + and (int_fwire_14, A2, B2, C1); + and (int_fwire_15, A2, B1, C3); + and (int_fwire_16, A2, B1, C2); + and (int_fwire_17, A2, B1, C1); + and (int_fwire_18, A1, B3, C3); + and (int_fwire_19, A1, B3, C2); + and (int_fwire_20, A1, B3, C1); + and (int_fwire_21, A1, B2, C3); + and (int_fwire_22, A1, B2, C2); + and (int_fwire_23, A1, B2, C1); + and (int_fwire_24, A1, B1, C3); + and (int_fwire_25, A1, B1, C2); + and (int_fwire_26, A1, B1, C1); + or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA333x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + wire int_fwire_18, int_fwire_19, int_fwire_20; + wire int_fwire_21, int_fwire_22, int_fwire_23; + wire int_fwire_24, int_fwire_25, int_fwire_26; + + and (int_fwire_0, A3, B3, C3); + and (int_fwire_1, A3, B3, C2); + and (int_fwire_2, A3, B3, C1); + and (int_fwire_3, A3, B2, C3); + and (int_fwire_4, A3, B2, C2); + and (int_fwire_5, A3, B2, C1); + and (int_fwire_6, A3, B1, C3); + and (int_fwire_7, A3, B1, C2); + and (int_fwire_8, A3, B1, C1); + and (int_fwire_9, A2, B3, C3); + and (int_fwire_10, A2, B3, C2); + and (int_fwire_11, A2, B3, C1); + and (int_fwire_12, A2, B2, C3); + and (int_fwire_13, A2, B2, C2); + and (int_fwire_14, A2, B2, C1); + and (int_fwire_15, A2, B1, C3); + and (int_fwire_16, A2, B1, C2); + and (int_fwire_17, A2, B1, C1); + and (int_fwire_18, A1, B3, C3); + and (int_fwire_19, A1, B3, C2); + and (int_fwire_20, A1, B3, C1); + and (int_fwire_21, A1, B2, C3); + and (int_fwire_22, A1, B2, C2); + and (int_fwire_23, A1, B2, C1); + and (int_fwire_24, A1, B1, C3); + and (int_fwire_25, A1, B1, C2); + and (int_fwire_26, A1, B1, C1); + or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA33x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3); + output Y; + input A1, A2, A3, B1, B2, B3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + + and (int_fwire_0, A3, B3); + and (int_fwire_1, A3, B2); + and (int_fwire_2, A3, B1); + and (int_fwire_3, A2, B3); + and (int_fwire_4, A2, B2); + and (int_fwire_5, A2, B1); + and (int_fwire_6, A1, B3); + and (int_fwire_7, A1, B2); + and (int_fwire_8, A1, B1); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & B3) | (~A2 & ~A3 & ~B1 & B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & B3) | (~A1 & ~A3 & ~B1 & B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & B3) | (~A1 & ~A2 & ~B1 & B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B2 & ~B3) | (~A1 & A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2) | (~A1 & A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI211xp5_ASAP7_75t_SL (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0; + + not (C__bar, C); + not (B__bar, B); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar); + or (Y, int_fwire_0, B__bar, C__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2 & C)) + (B => Y) = 0; + if ((A1 & ~A2 & C)) + (B => Y) = 0; + if ((~A1 & A2 & C)) + (B => Y) = 0; + if ((A1 & A2 & B)) + (C => Y) = 0; + if ((A1 & ~A2 & B)) + (C => Y) = 0; + if ((~A1 & A2 & B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI21x1_ASAP7_75t_SL (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0; + + not (B__bar, B); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2)) + (B => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI21xp33_ASAP7_75t_SL (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0; + + not (B__bar, B); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2)) + (B => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI21xp5_ASAP7_75t_SL (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0; + + not (B__bar, B); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2)) + (B => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI221xp5_ASAP7_75t_SL (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C__bar, int_fwire_0; + wire int_fwire_1; + + not (C__bar, C); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar); + or (Y, int_fwire_1, int_fwire_0, C__bar); + + // Timing + specify + if ((~A2 & B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & C)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2 & C)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI222xp33_ASAP7_75t_SL (Y, A1, A2, B1, B2, C1, C2); + output Y; + input A1, A2, B1, B2, C1, C2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C1__bar, C2__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + + not (C2__bar, C2); + not (C1__bar, C1); + and (int_fwire_0, C1__bar, C2__bar); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_1, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, A2__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & B2 & C1 & ~C2) | (~A2 & B1 & ~B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & B2 & C1 & ~C2) | (~A1 & B1 & ~B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI22x1_ASAP7_75t_SL (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI22xp33_ASAP7_75t_SL (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI22xp5_ASAP7_75t_SL (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI311xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, C1); + output Y; + input A1, A2, A3, B1, C1; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, C1__bar, int_fwire_0; + + not (C1__bar, C1); + not (B1__bar, B1); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_0, B1__bar, C1__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & A3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & C1) | (A1 & ~A2 & A3 & C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & B1)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1) | (A1 & ~A2 & A3 & B1)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI31xp33_ASAP7_75t_SL (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, int_fwire_0; + + not (B__bar, B); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & A3)) + (B => Y) = 0; + if ((A1 & A2 & ~A3) | (A1 & ~A2 & A3)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & A2 & A3)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & ~A2 & A3)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI31xp67_ASAP7_75t_SL (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, int_fwire_0; + + not (B__bar, B); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & A3)) + (B => Y) = 0; + if ((A1 & A2 & ~A3) | (A1 & ~A2 & A3)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & A2 & A3)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & ~A2 & A3)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI321xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, C); + output Y; + input A1, A2, A3, B1, B2, C; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, C__bar; + wire int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_1, int_fwire_0, C__bar); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & C)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & C)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & C) | (A1 & ~A2 & A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & C) | (A1 & ~A2 & A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2) | (A1 & ~A2 & A3 & B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2) | (A1 & ~A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2) | (A1 & ~A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI322xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, C1, C2); + output Y; + input A1, A2, A3, B1, B2, C1, C2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, C1__bar; + wire C2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2; + + not (C2__bar, C2); + not (C1__bar, C1); + and (int_fwire_0, C1__bar, C2__bar); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_1, B1__bar, B2__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI32xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2); + output Y; + input A1, A2, A3, B1, B2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, int_fwire_0; + wire int_fwire_1; + + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2) | (A1 & ~A2 & A3 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1) | (A1 & ~A2 & A3 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI331xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1); + output Y; + input A1, A2, A3, B1, B2, B3, C1; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, int_fwire_0, int_fwire_1; + + not (C1__bar, C1); + not (B3__bar, B3); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar, B3__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_1, int_fwire_0, C1__bar); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI332xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, C2__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2; + + not (C2__bar, C2); + not (C1__bar, C1); + and (int_fwire_0, C1__bar, C2__bar); + not (B3__bar, B3); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_1, B1__bar, B2__bar, B3__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI333xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, C2__bar, C3__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + + not (C3__bar, C3); + not (C2__bar, C2); + not (C1__bar, C1); + and (int_fwire_0, C1__bar, C2__bar, C3__bar); + not (B3__bar, B3); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_1, B1__bar, B2__bar, B3__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI33xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3); + output Y; + input A1, A2, A3, B1, B2, B3; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire int_fwire_0, int_fwire_1; + + not (B3__bar, B3); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar, B3__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3) | (~A2 & ~A3 & B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3) | (~A1 & ~A3 & B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3) | (~A1 & ~A2 & B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B2 & ~B3) | (~A1 & A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2) | (~A1 & A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + endspecify +endmodule +`endcelldefine diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_LVT_TT_220101.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_LVT_TT_220101.v new file mode 100644 index 0000000000..a04bc82c17 --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_LVT_TT_220101.v @@ -0,0 +1,1173 @@ +// BSD 3-Clause License +// +// Copyright 2022 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/anolas19/Liberate/Verilog/asap7sc7p5t_SEQ_LVT_TT_211229_pex created by Liberate 18.1.0.293 on Fri Dec 31 22:59:44 MST 2021 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module DFFASRHQNx1_ASAP7_75t_L (QN, D, RESETN, SETN, CLK); + output QN; + input D, RESETN, SETN, CLK; + reg notifier; + wire delayed_D, delayed_LESETN, delayed_SETN, delayed_CLK; + + // Function + wire int_fwire_d, int_fwire_IQN, int_fwire_r; + wire int_fwire_s, xcr_0; + + not (int_fwire_d, delayed_D); + not (int_fwire_s, delayed_LESETN); + not (int_fwire_r, delayed_SETN); + //altos_dff_sr_err (xcr_0, delayed_CLK, int_fwire_d, int_fwire_s, int_fwire_r); + // altos_dff_sr_0 (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, int_fwire_s, int_fwire_r, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, adacond8; + wire CLK__bar, D__bar; + + + // Additional timing gates + and (adacond0, RESETN, SETN); + and (adacond1, D, SETN); + and (adacond2, CLK, SETN); + not (CLK__bar, CLK); + and (adacond3, CLK__bar, SETN); + not (D__bar, D); + and (adacond4, D__bar, RESETN); + and (adacond5, CLK, RESETN); + and (adacond6, CLK__bar, RESETN); + and (adacond7, D, RESETN, SETN); + and (adacond8, D__bar, RESETN, SETN); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFHQNx1_ASAP7_75t_L (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (int_fwire_d, delayed_D); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFHQNx2_ASAP7_75t_L (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (int_fwire_d, delayed_D); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFHQNx3_ASAP7_75t_L (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (int_fwire_d, delayed_D); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFHQx4_ASAP7_75t_L (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_IQ, xcr_0; + + //altos_dff_err (xcr_0, delayed_CLK, delayed_D); + //altos_dff (int_fwire_IQ, notifier, delayed_CLK, delayed_D, xcr_0); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFLQNx1_ASAP7_75t_L (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (int_fwire_d, delayed_D); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFLQNx2_ASAP7_75t_L (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (int_fwire_d, delayed_D); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFLQNx3_ASAP7_75t_L (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (int_fwire_d, delayed_D); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFLQx4_ASAP7_75t_L (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, xcr_0; + + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, delayed_D); + //altos_dff (int_fwire_IQ, notifier, int_fwire_clk, delayed_D, xcr_0); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DHLx1_ASAP7_75t_L (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_IQ; + + //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DHLx2_ASAP7_75t_L (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_IQ; + + //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DHLx3_ASAP7_75t_L (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_IQ; + + //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DLLx1_ASAP7_75t_L (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ; + + not (int_fwire_clk, delayed_CLK); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DLLx2_ASAP7_75t_L (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ; + + not (int_fwire_clk, delayed_CLK); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DLLx3_ASAP7_75t_L (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ; + + not (int_fwire_clk, delayed_CLK); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx1_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx2_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx2p67DC_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx3_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx4DC_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx4_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx5_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx5p33DC_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx6p67DC_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx8DC_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFHx1_ASAP7_75t_L (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFHx2_ASAP7_75t_L (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFHx3_ASAP7_75t_L (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFHx4_ASAP7_75t_L (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFLx1_ASAP7_75t_L (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFLx2_ASAP7_75t_L (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFLx3_ASAP7_75t_L (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFLx4_ASAP7_75t_L (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_SLVT_TT_220101.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_SLVT_TT_220101.v new file mode 100644 index 0000000000..86b817a386 --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_SLVT_TT_220101.v @@ -0,0 +1,1173 @@ +// BSD 3-Clause License +// +// Copyright 2022 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/anolas19/Liberate/Verilog/asap7sc7p5t_SEQ_SLVT_TT_211229_pex created by Liberate 18.1.0.293 on Fri Dec 31 22:59:44 MST 2021 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module DFFASRHQNx1_ASAP7_75t_SL (QN, D, RESETN, SETN, CLK); + output QN; + input D, RESETN, SETN, CLK; + reg notifier; + wire delayed_D, delayed_SLESETN, delayed_SETN, delayed_CLK; + + // Function + wire int_fwire_d, int_fwire_IQN, int_fwire_r; + wire int_fwire_s, xcr_0; + + not (int_fwire_d, delayed_D); + not (int_fwire_s, delayed_SLESETN); + not (int_fwire_r, delayed_SETN); + //altos_dff_sr_err (xcr_0, delayed_CLK, int_fwire_d, int_fwire_s, int_fwire_r); + // altos_dff_sr_0 (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, int_fwire_s, int_fwire_r, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, adacond8; + wire CLK__bar, D__bar; + + + // Additional timing gates + and (adacond0, RESETN, SETN); + and (adacond1, D, SETN); + and (adacond2, CLK, SETN); + not (CLK__bar, CLK); + and (adacond3, CLK__bar, SETN); + not (D__bar, D); + and (adacond4, D__bar, RESETN); + and (adacond5, CLK, RESETN); + and (adacond6, CLK__bar, RESETN); + and (adacond7, D, RESETN, SETN); + and (adacond8, D__bar, RESETN, SETN); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFHQNx1_ASAP7_75t_SL (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (int_fwire_d, delayed_D); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFHQNx2_ASAP7_75t_SL (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (int_fwire_d, delayed_D); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFHQNx3_ASAP7_75t_SL (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (int_fwire_d, delayed_D); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFHQx4_ASAP7_75t_SL (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_IQ, xcr_0; + + //altos_dff_err (xcr_0, delayed_CLK, delayed_D); + //altos_dff (int_fwire_IQ, notifier, delayed_CLK, delayed_D, xcr_0); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFLQNx1_ASAP7_75t_SL (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (int_fwire_d, delayed_D); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFLQNx2_ASAP7_75t_SL (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (int_fwire_d, delayed_D); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFLQNx3_ASAP7_75t_SL (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (int_fwire_d, delayed_D); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFLQx4_ASAP7_75t_SL (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, xcr_0; + + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, delayed_D); + //altos_dff (int_fwire_IQ, notifier, int_fwire_clk, delayed_D, xcr_0); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DHLx1_ASAP7_75t_SL (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_IQ; + + //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DHLx2_ASAP7_75t_SL (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_IQ; + + //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DHLx3_ASAP7_75t_SL (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_IQ; + + //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DLLx1_ASAP7_75t_SL (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ; + + not (int_fwire_clk, delayed_CLK); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DLLx2_ASAP7_75t_SL (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ; + + not (int_fwire_clk, delayed_CLK); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DLLx3_ASAP7_75t_SL (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ; + + not (int_fwire_clk, delayed_CLK); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx1_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx2_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx2p67DC_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx3_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx4DC_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx4_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx5_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx5p33DC_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx6p67DC_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx8DC_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFHx1_ASAP7_75t_SL (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFHx2_ASAP7_75t_SL (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFHx3_ASAP7_75t_SL (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFHx4_ASAP7_75t_SL (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFLx1_ASAP7_75t_SL (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFLx2_ASAP7_75t_SL (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFLx3_ASAP7_75t_SL (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFLx4_ASAP7_75t_SL (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_LVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_LVT_TT_201020.v new file mode 100644 index 0000000000..ce741d6cfa --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_LVT_TT_201020.v @@ -0,0 +1,1303 @@ +// BSD 3-Clause License +// +// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_SIMPLE_LVT_TT_201020 created by Liberate 18.1.0.293 on Fri Nov 27 12:35:46 MST 2020 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module AND2x2_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + and (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND2x4_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + and (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND2x6_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + and (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND3x1_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + and (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND3x2_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + and (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND3x4_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + and (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND4x1_ASAP7_75t_L (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + and (Y, A, B, C, D); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND4x2_ASAP7_75t_L (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + and (Y, A, B, C, D); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND5x1_ASAP7_75t_L (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + and (Y, A, B, C, D, E); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND5x2_ASAP7_75t_L (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + and (Y, A, B, C, D, E); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module FAx1_ASAP7_75t_L (CON, SN, A, B, CI); + output CON, SN; + input A, B, CI; + + // Function + wire A__bar, B__bar, CI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6; + + not (CI__bar, CI); + not (B__bar, B); + and (int_fwire_0, B__bar, CI__bar); + not (A__bar, A); + and (int_fwire_1, A__bar, CI__bar); + and (int_fwire_2, A__bar, B__bar); + or (CON, int_fwire_2, int_fwire_1, int_fwire_0); + and (int_fwire_3, A__bar, B__bar, CI__bar); + and (int_fwire_4, A__bar, B, CI); + and (int_fwire_5, A, B__bar, CI); + and (int_fwire_6, A, B, CI__bar); + or (SN, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HAxp5_ASAP7_75t_L (CON, SN, A, B); + output CON, SN; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (B__bar, B); + not (A__bar, A); + or (CON, A__bar, B__bar); + and (int_fwire_0, A__bar, B__bar); + and (int_fwire_1, A, B); + or (SN, int_fwire_1, int_fwire_0); + + // Timing + specify + (A => CON) = 0; + (B => CON) = 0; + if (B) + (A => SN) = 0; + if (~B) + (A => SN) = 0; + if (A) + (B => SN) = 0; + if (~A) + (B => SN) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module MAJIxp5_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + + not (C__bar, C); + not (B__bar, B); + and (int_fwire_0, B__bar, C__bar); + not (A__bar, A); + and (int_fwire_1, A__bar, C__bar); + and (int_fwire_2, A__bar, B__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module MAJx2_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, B, C); + and (int_fwire_1, A, C); + and (int_fwire_2, A, B); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module MAJx3_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, B, C); + and (int_fwire_1, A, C); + and (int_fwire_2, A, B); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2x1_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2x1p5_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2x2_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2xp33_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2xp5_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2xp67_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND3x1_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND3x2_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND3xp33_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND4xp25_ASAP7_75t_L (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar; + + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar, D__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND4xp75_ASAP7_75t_L (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar; + + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar, D__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND5xp2_ASAP7_75t_L (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar, E__bar; + + not (E__bar, E); + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar, D__bar, E__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2x1_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2x1p5_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2x2_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2xp33_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2xp67_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR3x1_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR3x2_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR3xp33_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR4xp25_ASAP7_75t_L (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar; + + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar, D__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR4xp75_ASAP7_75t_L (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar; + + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar, D__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR5xp2_ASAP7_75t_L (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar, E__bar; + + not (E__bar, E); + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar, D__bar, E__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR2x2_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + or (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR2x4_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + or (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR2x6_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + or (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR3x1_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + or (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR3x2_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + or (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR3x4_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + or (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR4x1_ASAP7_75t_L (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + or (Y, A, B, C, D); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR4x2_ASAP7_75t_L (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + or (Y, A, B, C, D); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR5x1_ASAP7_75t_L (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + or (Y, A, B, C, D, E); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR5x2_ASAP7_75t_L (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + or (Y, A, B, C, D, E); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module TIEHIx1_ASAP7_75t_L (H); + output H; + + // Function + buf (H, 1'b1); + + // Timing + specify + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module TIELOx1_ASAP7_75t_L (L); + output L; + + // Function + buf (L, 1'b0); + + // Timing + specify + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XNOR2x1_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (B__bar, B); + not (A__bar, A); + and (int_fwire_0, A__bar, B__bar); + and (int_fwire_1, A, B); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (B) + (A => Y) = 0; + if (~B) + (A => Y) = 0; + if (A) + (B => Y) = 0; + if (~A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XNOR2x2_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (B__bar, B); + not (A__bar, A); + and (int_fwire_0, A__bar, B__bar); + and (int_fwire_1, A, B); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (B) + (A => Y) = 0; + if (~B) + (A => Y) = 0; + if (A) + (B => Y) = 0; + if (~A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XNOR2xp5_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (B__bar, B); + not (A__bar, A); + and (int_fwire_0, A__bar, B__bar); + and (int_fwire_1, A, B); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (B) + (A => Y) = 0; + if (~B) + (A => Y) = 0; + if (A) + (B => Y) = 0; + if (~A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XOR2x1_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (A__bar, A); + and (int_fwire_0, A__bar, B); + not (B__bar, B); + and (int_fwire_1, A, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (~B) + (A => Y) = 0; + if (B) + (A => Y) = 0; + if (~A) + (B => Y) = 0; + if (A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XOR2x2_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (A__bar, A); + and (int_fwire_0, A__bar, B); + not (B__bar, B); + and (int_fwire_1, A, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (~B) + (A => Y) = 0; + if (B) + (A => Y) = 0; + if (~A) + (B => Y) = 0; + if (A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XOR2xp5_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (A__bar, A); + and (int_fwire_0, A__bar, B); + not (B__bar, B); + and (int_fwire_1, A, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (~B) + (A => Y) = 0; + if (B) + (A => Y) = 0; + if (~A) + (B => Y) = 0; + if (A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_SLVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_SLVT_TT_201020.v new file mode 100644 index 0000000000..abdd8249e8 --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_SLVT_TT_201020.v @@ -0,0 +1,1303 @@ +// BSD 3-Clause License +// +// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_SIMPLE_SLVT_TT_201020 created by Liberate 18.1.0.293 on Fri Nov 27 12:35:46 MST 2020 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module AND2x2_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + and (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND2x4_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + and (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND2x6_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + and (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND3x1_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + and (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND3x2_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + and (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND3x4_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + and (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND4x1_ASAP7_75t_SL (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + and (Y, A, B, C, D); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND4x2_ASAP7_75t_SL (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + and (Y, A, B, C, D); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND5x1_ASAP7_75t_SL (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + and (Y, A, B, C, D, E); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND5x2_ASAP7_75t_SL (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + and (Y, A, B, C, D, E); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module FAx1_ASAP7_75t_SL (CON, SN, A, B, CI); + output CON, SN; + input A, B, CI; + + // Function + wire A__bar, B__bar, CI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6; + + not (CI__bar, CI); + not (B__bar, B); + and (int_fwire_0, B__bar, CI__bar); + not (A__bar, A); + and (int_fwire_1, A__bar, CI__bar); + and (int_fwire_2, A__bar, B__bar); + or (CON, int_fwire_2, int_fwire_1, int_fwire_0); + and (int_fwire_3, A__bar, B__bar, CI__bar); + and (int_fwire_4, A__bar, B, CI); + and (int_fwire_5, A, B__bar, CI); + and (int_fwire_6, A, B, CI__bar); + or (SN, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HAxp5_ASAP7_75t_SL (CON, SN, A, B); + output CON, SN; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (B__bar, B); + not (A__bar, A); + or (CON, A__bar, B__bar); + and (int_fwire_0, A__bar, B__bar); + and (int_fwire_1, A, B); + or (SN, int_fwire_1, int_fwire_0); + + // Timing + specify + (A => CON) = 0; + (B => CON) = 0; + if (B) + (A => SN) = 0; + if (~B) + (A => SN) = 0; + if (A) + (B => SN) = 0; + if (~A) + (B => SN) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module MAJIxp5_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + + not (C__bar, C); + not (B__bar, B); + and (int_fwire_0, B__bar, C__bar); + not (A__bar, A); + and (int_fwire_1, A__bar, C__bar); + and (int_fwire_2, A__bar, B__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module MAJx2_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, B, C); + and (int_fwire_1, A, C); + and (int_fwire_2, A, B); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module MAJx3_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, B, C); + and (int_fwire_1, A, C); + and (int_fwire_2, A, B); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2x1_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2x1p5_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2x2_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2xp33_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2xp5_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2xp67_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND3x1_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND3x2_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND3xp33_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND4xp25_ASAP7_75t_SL (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar; + + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar, D__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND4xp75_ASAP7_75t_SL (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar; + + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar, D__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND5xp2_ASAP7_75t_SL (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar, E__bar; + + not (E__bar, E); + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar, D__bar, E__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2x1_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2x1p5_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2x2_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2xp33_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2xp67_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR3x1_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR3x2_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR3xp33_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR4xp25_ASAP7_75t_SL (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar; + + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar, D__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR4xp75_ASAP7_75t_SL (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar; + + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar, D__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR5xp2_ASAP7_75t_SL (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar, E__bar; + + not (E__bar, E); + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar, D__bar, E__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR2x2_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + or (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR2x4_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + or (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR2x6_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + or (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR3x1_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + or (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR3x2_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + or (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR3x4_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + or (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR4x1_ASAP7_75t_SL (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + or (Y, A, B, C, D); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR4x2_ASAP7_75t_SL (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + or (Y, A, B, C, D); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR5x1_ASAP7_75t_SL (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + or (Y, A, B, C, D, E); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR5x2_ASAP7_75t_SL (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + or (Y, A, B, C, D, E); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module TIEHIx1_ASAP7_75t_SL (H); + output H; + + // Function + buf (H, 1'b1); + + // Timing + specify + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module TIELOx1_ASAP7_75t_SL (L); + output L; + + // Function + buf (L, 1'b0); + + // Timing + specify + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XNOR2x1_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (B__bar, B); + not (A__bar, A); + and (int_fwire_0, A__bar, B__bar); + and (int_fwire_1, A, B); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (B) + (A => Y) = 0; + if (~B) + (A => Y) = 0; + if (A) + (B => Y) = 0; + if (~A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XNOR2x2_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (B__bar, B); + not (A__bar, A); + and (int_fwire_0, A__bar, B__bar); + and (int_fwire_1, A, B); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (B) + (A => Y) = 0; + if (~B) + (A => Y) = 0; + if (A) + (B => Y) = 0; + if (~A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XNOR2xp5_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (B__bar, B); + not (A__bar, A); + and (int_fwire_0, A__bar, B__bar); + and (int_fwire_1, A, B); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (B) + (A => Y) = 0; + if (~B) + (A => Y) = 0; + if (A) + (B => Y) = 0; + if (~A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XOR2x1_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (A__bar, A); + and (int_fwire_0, A__bar, B); + not (B__bar, B); + and (int_fwire_1, A, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (~B) + (A => Y) = 0; + if (B) + (A => Y) = 0; + if (~A) + (B => Y) = 0; + if (A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XOR2x2_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (A__bar, A); + and (int_fwire_0, A__bar, B); + not (B__bar, B); + and (int_fwire_1, A, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (~B) + (A => Y) = 0; + if (B) + (A => Y) = 0; + if (~A) + (B => Y) = 0; + if (A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XOR2xp5_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (A__bar, A); + and (int_fwire_0, A__bar, B); + not (B__bar, B); + and (int_fwire_1, A, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (~B) + (A => Y) = 0; + if (B) + (A => Y) = 0; + if (~A) + (B => Y) = 0; + if (A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine diff --git a/flow/platforms/gf180/fastroute.tcl b/flow/platforms/gf180/fastroute.tcl index d91e3b4dcc..42e6b5996b 100644 --- a/flow/platforms/gf180/fastroute.tcl +++ b/flow/platforms/gf180/fastroute.tcl @@ -1,3 +1,2 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.25 set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/platforms/gf180/openROAD/tapcell.tcl b/flow/platforms/gf180/openROAD/tapcell.tcl index fecbde985a..24ebce5587 100644 --- a/flow/platforms/gf180/openROAD/tapcell.tcl +++ b/flow/platforms/gf180/openROAD/tapcell.tcl @@ -1,5 +1,5 @@ - tapcell \ - -endcap_cpp "12" \ - -distance 100 \ - -tapcell_master $::env(TIE_CELL) \ - -endcap_master $::env(ENDCAP_CELL) +tapcell \ + -endcap_cpp "12" \ + -distance 100 \ + -tapcell_master $::env(TIE_CELL) \ + -endcap_master $::env(ENDCAP_CELL) diff --git a/flow/platforms/gf180/setRC.tcl b/flow/platforms/gf180/setRC.tcl index 7c6828b1de..33ae86856a 100644 --- a/flow/platforms/gf180/setRC.tcl +++ b/flow/platforms/gf180/setRC.tcl @@ -17,14 +17,12 @@ set_layer_rc -layer Metal5 -resistance 7.92778E-05 -capacitance 1.55595E-04 regexp {(\d+)} $::env(METAL_OPTION) metal if { $metal == "6" } { - set_wire_rc -signal -layer Metal2 - set_wire_rc -clock -layer Metal5 - -} elseif { $metal == "5" } { + set_wire_rc -clock -layer Metal5 +} elseif { $metal == "5" } { # TC matches LEF. These are the temperature adjusted values. # The other stacks are likely similar but I haven't checked yet. - if {$::env(CORNER) == "WC"} { + if { $::env(CORNER) == "WC" } { set_layer_rc -via Via1 -resistance 16.845 set_layer_rc -via Via2 -resistance 16.845 set_layer_rc -via Via3 -resistance 16.845 @@ -32,11 +30,11 @@ if { $metal == "6" } { set tech [ord::get_db_tech] foreach via [$tech getVias] { - if {[$via getResistance] == 4.5} { + if { [$via getResistance] == 4.5 } { $via setResistance 16.845 } } - } elseif {$::env(CORNER) == "BC"} { + } elseif { $::env(CORNER) == "BC" } { set_layer_rc -via Via1 -resistance 4.23 set_layer_rc -via Via2 -resistance 4.23 set_layer_rc -via Via3 -resistance 4.23 @@ -44,27 +42,21 @@ if { $metal == "6" } { set tech [ord::get_db_tech] foreach via [$tech getVias] { - if {[$via getResistance] == 4.5} { + if { [$via getResistance] == 4.5 } { $via setResistance 4.23 } } } - - set_wire_rc -signal -layer Metal2 - set_wire_rc -clock -layer Metal4 - -} elseif { $metal == "4" } { set_wire_rc -signal -layer Metal2 - set_wire_rc -clock -layer Metal3 - -} elseif { $metal == "3" } { - + set_wire_rc -clock -layer Metal4 +} elseif { $metal == "4" } { set_wire_rc -signal -layer Metal2 - set_wire_rc -clock -layer Metal2 - -} elseif { $metal == "2" } { - + set_wire_rc -clock -layer Metal3 +} elseif { $metal == "3" } { + set_wire_rc -signal -layer Metal2 + set_wire_rc -clock -layer Metal2 +} elseif { $metal == "2" } { set_wire_rc -signal -layer Metal2 - set_wire_rc -clock -layer Metal2 + set_wire_rc -clock -layer Metal2 } diff --git a/flow/platforms/ihp-sg13g2/config.mk b/flow/platforms/ihp-sg13g2/config.mk index 4341d43186..caea89b76c 100644 --- a/flow/platforms/ihp-sg13g2/config.mk +++ b/flow/platforms/ihp-sg13g2/config.mk @@ -6,21 +6,28 @@ export PROCESS = ihp-sg13g2 # ---------------------------------------------------- # Add IO related files when a TCL script is assigned to 'FOOTPRINT_TCL'. # This variable is used to pass IO information. -export LOAD_ADDITIONAL_FILES ?= yes -ifdef FOOTPRINT_TCL -ifdef LOAD_ADDITIONAL_FILES - export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/sg13g2_io.lef \ - $(PLATFORM_DIR)/lef/bondpad_70x70.lef - export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib - export ADDITIONAL_GDS += $(PLATFORM_DIR)/gds/sg13g2_io.gds \ - $(PLATFORM_DIR)/gds/bondpad_70x70.gds -endif +export LOAD_ADDITIONAL_FILES ?= 1 +ifneq ($(FOOTPRINT_TCL),) + ifeq ($(LOAD_ADDITIONAL_FILES),1) + export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/sg13g2_io.lef \ + $(PLATFORM_DIR)/lef/bondpad_70x70.lef + export ADDITIONAL_SLOW_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib + export ADDITIONAL_FAST_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib + export ADDITIONAL_TYP_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib + export ADDITIONAL_GDS += $(PLATFORM_DIR)/gds/sg13g2_io.gds \ + $(PLATFORM_DIR)/gds/bondpad_70x70.gds + endif endif export TECH_LEF ?= $(PLATFORM_DIR)/lef/sg13g2_tech.lef export SC_LEF ?= $(PLATFORM_DIR)/lef/sg13g2_stdcell.lef -export LIB_FILES ?= $(PLATFORM_DIR)/lib/sg13g2_stdcell_typ_1p20V_25C.lib \ - $(ADDITIONAL_LIBS) +export SLOW_LIB_FILES ?= $(PLATFORM_DIR)/lib/sg13g2_stdcell_slow_1p08V_125C.lib \ + $(ADDITIONAL_SLOW_LIBS) +export FAST_LIB_FILES ?= $(PLATFORM_DIR)/lib/sg13g2_stdcell_fast_1p32V_m40C.lib \ + $(ADDITIONAL_FAST_LIBS) +export TYP_LIB_FILES ?= $(PLATFORM_DIR)/lib/sg13g2_stdcell_typ_1p20V_25C.lib \ + $(ADDITIONAL_TYP_LIBS) +export LIB_FILES ?= $(TYP_LIB_FILES) export GDS_FILES ?= $(PLATFORM_DIR)/gds/sg13g2_stdcell.gds \ $(ADDITIONAL_GDS) @@ -57,8 +64,12 @@ export CLKGATE_MAP_FILE = $(PLATFORM_DIR)/cells_clkgate.v # Define ABC driver and load export ABC_DRIVER_CELL = sg13g2_buf_4 export ABC_LOAD_IN_FF = 6.0 -# Set yosys-abc clock period to first "clk_period" value or "-period" value found in sdc file -export ABC_CLOCK_PERIOD_IN_PS ?= $(shell sed -nE "s/^set clk_period (.+)|.* -period (.+) .*/\1\2/p" $(SDC_FILE) | head -1 | awk '{print $$1*1000}') +ifeq ($(origin ABC_CLOCK_PERIOD_IN_PS), undefined) + ifneq ($(wildcard $(SDC_FILE)),) + # Set yosys-abc clock period to first "clk_period" value or "-period" value found in sdc file + export ABC_CLOCK_PERIOD_IN_PS ?= $(shell sed -nE "s/^set clk_period (.+)|.* -period (.+) .*/\1\2/p" $(SDC_FILE) | head -1 | awk '{print $$1*1000}') + endif +endif # ----------------------------------------------------- # Sizing @@ -137,9 +148,6 @@ export KLAYOUT_DRC_FILE ?= $(PLATFORM_DIR)/drc/sg13g2_minimal.lydrc export CDL_FILE ?= $(PLATFORM_DIR)/cdl/sg13g2_stdcell.cdl #export KLAYOUT_LVS_FILE = $(PLATFORM_DIR)/lvs/$(PLATFORM).lylvs -#Temporary: skip post-DRT repair antennas -export SKIP_ANTENNA_REPAIR_POST_DRT = 1 - # --------------------------------------------------------- # Final # --------------------------------------------------------- diff --git a/flow/platforms/ihp-sg13g2/fastroute.tcl b/flow/platforms/ihp-sg13g2/fastroute.tcl index 079fa662e8..e386fefda4 100644 --- a/flow/platforms/ihp-sg13g2/fastroute.tcl +++ b/flow/platforms/ihp-sg13g2/fastroute.tcl @@ -1,4 +1,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.05 set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/platforms/ihp-sg13g2/make_tracks.tcl b/flow/platforms/ihp-sg13g2/make_tracks.tcl index 4b6c63fd52..b3380eb7ef 100644 --- a/flow/platforms/ihp-sg13g2/make_tracks.tcl +++ b/flow/platforms/ihp-sg13g2/make_tracks.tcl @@ -1,7 +1,7 @@ -make_tracks Metal1 -x_offset 0.0 -x_pitch 0.48 -y_offset 0.0 -y_pitch 0.48 -make_tracks Metal2 -x_offset 0.0 -x_pitch 0.42 -y_offset 0.0 -y_pitch 0.42 -make_tracks Metal3 -x_offset 0.0 -x_pitch 0.48 -y_offset 0.0 -y_pitch 0.48 -make_tracks Metal4 -x_offset 0.0 -x_pitch 0.42 -y_offset 0.0 -y_pitch 0.42 -make_tracks Metal5 -x_offset 0.0 -x_pitch 3.48 -y_offset 0.0 -y_pitch 0.48 +make_tracks Metal1 -x_offset 0.0 -x_pitch 0.48 -y_offset 0.0 -y_pitch 0.48 +make_tracks Metal2 -x_offset 0.0 -x_pitch 0.42 -y_offset 0.0 -y_pitch 0.42 +make_tracks Metal3 -x_offset 0.0 -x_pitch 0.48 -y_offset 0.0 -y_pitch 0.48 +make_tracks Metal4 -x_offset 0.0 -x_pitch 0.42 -y_offset 0.0 -y_pitch 0.42 +make_tracks Metal5 -x_offset 0.0 -x_pitch 3.48 -y_offset 0.0 -y_pitch 0.48 make_tracks TopMetal1 -x_offset 1.46 -x_pitch 2.28 -y_offset 1.46 -y_pitch 2.28 -make_tracks TopMetal2 -x_offset 2.0 -x_pitch 4.0 -y_offset 2.0 -y_pitch 4.0 +make_tracks TopMetal2 -x_offset 2.0 -x_pitch 4.0 -y_offset 2.0 -y_pitch 4.0 diff --git a/flow/platforms/ihp-sg13g2/pdn.tcl b/flow/platforms/ihp-sg13g2/pdn.tcl index 99d911feae..812bcab616 100644 --- a/flow/platforms/ihp-sg13g2/pdn.tcl +++ b/flow/platforms/ihp-sg13g2/pdn.tcl @@ -19,10 +19,14 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} # standard cell grid #################################### define_pdn_grid -name {grid} -voltage_domains {CORE} -add_pdn_ring -grid {grid} -layers {Metal5 TopMetal1} -widths {5.0} -spacings {2.0} -core_offsets {4.5} -connect_to_pads -add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins -extend_to_core_ring -add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {13.600} -extend_to_core_ring -add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {1.800} -pitch {75.6} -offset {13.570} -extend_to_core_ring +add_pdn_ring -grid {grid} -layers {Metal5 TopMetal1} -widths {5.0} -spacings {2.0} \ + -core_offsets {4.5} -connect_to_pads +add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins \ + -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {13.600} \ + -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {1.800} -pitch {75.6} -offset {13.570} \ + -extend_to_core_ring add_pdn_connect -grid {grid} -layers {Metal1 Metal5} add_pdn_connect -grid {grid} -layers {Metal5 TopMetal1} # I/O pads diff --git a/flow/platforms/ihp-sg13g2/setRC.tcl b/flow/platforms/ihp-sg13g2/setRC.tcl index ee17153aee..35bfff7693 100644 --- a/flow/platforms/ihp-sg13g2/setRC.tcl +++ b/flow/platforms/ihp-sg13g2/setRC.tcl @@ -1,20 +1,16 @@ -# correlateRC.py gcd,ibex,aes,jpeg,chameleon,riscv32i,chameleon_hier -# cap units pf/um -set_layer_rc -layer Metal1 -capacitance 3.49E-05 -resistance 0.135e-03 -set_layer_rc -layer Metal2 -capacitance 1.81E-05 -resistance 0.103e-03 -set_layer_rc -layer Metal3 -capacitance 2.14962E-04 -resistance 0.103e-03 -set_layer_rc -layer Metal4 -capacitance 1.48128E-04 -resistance 0.103e-03 -set_layer_rc -layer Metal5 -capacitance 1.54087E-04 -resistance 0.103e-03 -set_layer_rc -layer TopMetal1 -capacitance 1.54087E-04 -resistance 0.021e-03 -set_layer_rc -layer TopMetal2 -capacitance 1.54087E-04 -resistance 0.0145e-03 -# end correlate +# correlation result (aes, gcd, ibex, riscv32i, spi) +# Metal1 capacitance fixed up from -1.1e-05 to 1e-10 as a minuscule positive value +set_layer_rc -layer Metal1 -resistance 8.54576E-03 -capacitance 1e-10 +set_layer_rc -layer Metal2 -resistance 2.53519E-03 -capacitance 1.69121E-04 +set_layer_rc -layer Metal3 -resistance 1.54329E-03 -capacitance 1.82832E-04 +set_layer_rc -layer Metal4 -resistance 6.31424E-04 -capacitance 1.66454E-04 +set_layer_rc -layer Metal5 -resistance 6.84051E-04 -capacitance 8.57431E-05 +set_wire_rc -signal -resistance 2.07259E-03 -capacitance 1.73072E-04 +set_wire_rc -clock -resistance 2.48603E-03 -capacitance 1.44812E-04 -set_layer_rc -via Via1 -resistance 2.0E-3 -set_layer_rc -via Via2 -resistance 2.0E-3 -set_layer_rc -via Via3 -resistance 2.0E-3 -set_layer_rc -via Via4 -resistance 2.0E-3 +set_layer_rc -via Via1 -resistance 2.0E-3 +set_layer_rc -via Via2 -resistance 2.0E-3 +set_layer_rc -via Via3 -resistance 2.0E-3 +set_layer_rc -via Via4 -resistance 2.0E-3 set_layer_rc -via TopVia1 -resistance 0.4E-3 set_layer_rc -via TopVia2 -resistance 0.22E-3 - -set_wire_rc -signal -layer Metal2 -set_wire_rc -clock -layer Metal5 diff --git a/flow/platforms/ihp-sg13g2/sg13g2.map b/flow/platforms/ihp-sg13g2/sg13g2.map index 2614374122..fbb201c83d 100644 --- a/flow/platforms/ihp-sg13g2/sg13g2.map +++ b/flow/platforms/ihp-sg13g2/sg13g2.map @@ -29,13 +29,10 @@ #EDI Layer Name EDI Layer Type GDS Layer Number GDS Layer Type #============== ============== ================ ============== -Metal1 NET 8 0 -Metal1 SPNET 8 0 -Metal1 PIN 8 2 -Metal1 LEFPIN 8 2 -Metal1 FILL 8 22 -Metal1 LEFOBS 8 4 -Metal1 VIA 8 0 +Metal1 NET,SPNET,PIN,LEFPIN,VIA 8 0 +Metal1 PIN,LEFPIN 8 2 +Metal1 FILL 8 22 +Metal1 LEFOBS 8 4 #NAME Metal1/NET 20 0 #NAME Metal1/SPNET 20 0 @@ -46,13 +43,10 @@ Via1 PIN 19 0 Via1 LEFPIN 19 0 Via1 VIA 19 0 -Metal2 NET 10 0 -Metal2 SPNET 10 0 -Metal2 PIN 10 2 -Metal2 LEFPIN 10 2 -Metal2 FILL 10 22 -Metal2 VIA 10 0 -Metal2 LEFOBS 10 4 +Metal2 NET,SPNET,PIN,LEFPIN,VIA 10 0 +Metal2 PIN,LEFPIN 10 2 +Metal2 FILL 10 22 +Metal2 LEFOBS 10 4 #NAME Metal2/NET 21 0 #NAME Metal2/SPNET 21 0 @@ -64,13 +58,10 @@ Via2 LEFPIN 29 0 Via2 VIA 29 0 -Metal3 NET 30 0 -Metal3 SPNET 30 0 -Metal3 PIN 30 2 -Metal3 LEFPIN 30 2 -Metal3 FILL 30 22 -Metal3 VIA 30 0 -Metal3 LEFOBS 30 4 +Metal3 NET,SPNET,PIN,LEFPIN,VIA 30 0 +Metal3 PIN,LEFPIN 30 2 +Metal3 FILL 30 22 +Metal3 LEFOBS 30 4 #NAME Metal3/NET 22 0 #NAME Metal3/SPNET 22 0 @@ -82,13 +73,10 @@ Via3 LEFPIN 49 0 Via3 VIA 49 0 -Metal4 NET 50 0 -Metal4 SPNET 50 0 -Metal4 PIN 50 2 -Metal4 LEFPIN 50 2 -Metal4 FILL 50 22 -Metal4 VIA 50 0 -Metal4 LEFOBS 50 4 +Metal4 NET,SPNET,PIN,LEFPIN,VIA 50 0 +Metal4 PIN,LEFPIN 50 2 +Metal4 FILL 50 22 +Metal4 LEFOBS 50 4 #NAME Metal4/NET 23 0 #NAME Metal4/SPNET 23 0 @@ -100,13 +88,10 @@ Via4 LEFPIN 66 0 Via4 VIA 66 0 -Metal5 NET 67 0 -Metal5 SPNET 67 0 -Metal5 PIN 67 2 -Metal5 LEFPIN 67 2 -Metal5 FILL 67 22 -Metal5 VIA 67 0 -Metal5 LEFOBS 67 4 +Metal5 NET,SPNET,PIN,LEFPIN,VIA 67 0 +Metal5 PIN,LEFPIN 67 2 +Metal5 FILL 67 22 +Metal5 LEFOBS 67 4 #NAME Metal5/NET 70 0 #NAME Metal5/SPNET 70 0 @@ -117,13 +102,10 @@ TopVia1 PIN 125 0 TopVia1 LEFPIN 125 0 TopVia1 VIA 125 0 -TopMetal1 NET 126 0 -TopMetal1 SPNET 126 0 -TopMetal1 PIN 126 2 -TopMetal1 LEFPIN 126 2 -TopMetal1 FILL 126 22 -TopMetal1 VIA 126 0 -TopMetal1 LEFOBS 126 4 +TopMetal1 NET,SPNET,PIN,LEFPIN,VIA 126 0 +TopMetal1 PIN,LEFPIN 126 2 +TopMetal1 FILL 126 22 +TopMetal1 LEFOBS 126 4 #NAME TopMetal1/NET 130 0 #NAME TopMetal1/SPNET 130 0 @@ -134,13 +116,10 @@ TopVia2 PIN 133 0 TopVia2 LEFPIN 133 0 TopVia2 VIA 133 0 -TopMetal2 NET 134 0 -TopMetal2 SPNET 134 0 -TopMetal2 PIN 134 2 -TopMetal2 LEFPIN 134 2 -TopMetal2 FILL 134 22 -TopMetal2 VIA 134 0 -TopMetal2 LEFOBS 135 4 +TopMetal2 NET,SPNET,PIN,LEFPIN,VIA 134 0 +TopMetal2 PIN,LEFPIN 134 2 +TopMetal2 FILL 134 22 +TopMetal2 LEFOBS 134 4 #NAME TopMetal2/NET 137 0 #NAME TopMetal2/SPNET 137 0 @@ -149,6 +128,6 @@ NAME TopMetal2/PIN 134 25 NAME COMP 63 0 -COMP ALL 235 0 +COMP ALL 189 0 -DIEAREA ALL 235 4 +DIEAREA ALL 189 4 diff --git a/flow/platforms/nangate45/config.mk b/flow/platforms/nangate45/config.mk index da73f6a986..d8b60131f4 100644 --- a/flow/platforms/nangate45/config.mk +++ b/flow/platforms/nangate45/config.mk @@ -72,6 +72,7 @@ export PLACE_DENSITY ?= 0.30 # --------------------------------------------------------- # FastRoute options export MIN_ROUTING_LAYER = metal2 +export MIN_CLK_ROUTING_LAYER = metal4 export MAX_ROUTING_LAYER = metal10 # Define fastRoute tcl diff --git a/flow/platforms/nangate45/fakeram.tcl b/flow/platforms/nangate45/fakeram.tcl index 4c8f9997e6..68d548e689 100644 --- a/flow/platforms/nangate45/fakeram.tcl +++ b/flow/platforms/nangate45/fakeram.tcl @@ -1,4 +1,3 @@ - set design_rams { swerv {2048x39 256x34 64x21} bp_be_top {64x96 512x64 64x15} @@ -11,7 +10,7 @@ set design_rams { set results_dir "~/import/fakeram/results" set flow_dir "~/import/flow/flow/platforms/nangate45" -proc make_fakeram_links {} { +proc make_fakeram_links { } { global design_rams flow_dir foreach {design sizes} $design_rams { @@ -27,13 +26,15 @@ proc make_fakeram_links {} { } } -proc copy_fakeram_results {} { +proc copy_fakeram_results { } { global design_rams results_dir flow_dir foreach {design sizes} $design_rams { foreach size $sizes { - file copy -force $results_dir/fakeram45_$size/fakeram45_$size.lib $flow_dir/lib/fakeram45_$size.lib - file copy -force $results_dir/fakeram45_$size/fakeram45_$size.lef $flow_dir/lef/fakeram45_$size.lef + file copy -force \ + $results_dir/fakeram45_$size/fakeram45_$size.lib $flow_dir/lib/fakeram45_$size.lib + file copy -force \ + $results_dir/fakeram45_$size/fakeram45_$size.lef $flow_dir/lef/fakeram45_$size.lef } } } diff --git a/flow/platforms/nangate45/fastroute.tcl b/flow/platforms/nangate45/fastroute.tcl index 2ec285bd96..7f6d9a242f 100644 --- a/flow/platforms/nangate45/fastroute.tcl +++ b/flow/platforms/nangate45/fastroute.tcl @@ -1,4 +1,5 @@ set_global_routing_layer_adjustment metal2-metal3 0.5 set_global_routing_layer_adjustment metal4-$::env(MAX_ROUTING_LAYER) 0.25 +set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) diff --git a/flow/platforms/nangate45/grid_strategy-M1-M4-M7.tcl b/flow/platforms/nangate45/grid_strategy-M1-M4-M7.tcl index a124d25802..02af27999c 100644 --- a/flow/platforms/nangate45/grid_strategy-M1-M4-M7.tcl +++ b/flow/platforms/nangate45/grid_strategy-M1-M4-M7.tcl @@ -26,7 +26,8 @@ add_pdn_connect -grid {grid} -layers {metal4 metal7} #################################### # grid for: CORE_macro_grid_1 #################################### -define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -cells {.*} +define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro \ + -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -cells {.*} add_pdn_stripe -grid {CORE_macro_grid_1} -layer {metal5} -width {0.93} -pitch {10.0} -offset {2} add_pdn_stripe -grid {CORE_macro_grid_1} -layer {metal6} -width {0.93} -pitch {10.0} -offset {2} add_pdn_connect -grid {CORE_macro_grid_1} -layers {metal4 metal5} @@ -35,7 +36,8 @@ add_pdn_connect -grid {CORE_macro_grid_1} -layers {metal6 metal7} #################################### # grid for: CORE_macro_grid_2 #################################### -define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -cells {.*} +define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro \ + -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -cells {.*} add_pdn_stripe -grid {CORE_macro_grid_2} -layer {metal6} -width {0.93} -pitch {40.0} -offset {2} add_pdn_connect -grid {CORE_macro_grid_2} -layers {metal4 metal6} add_pdn_connect -grid {CORE_macro_grid_2} -layers {metal6 metal7} diff --git a/flow/platforms/nangate45/make_tracks.tcl b/flow/platforms/nangate45/make_tracks.tcl index 923d6a1fda..0411a74b72 100644 --- a/flow/platforms/nangate45/make_tracks.tcl +++ b/flow/platforms/nangate45/make_tracks.tcl @@ -1,10 +1,10 @@ make_tracks metal1 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14 -make_tracks metal2 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14 -make_tracks metal3 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14 -make_tracks metal4 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28 -make_tracks metal5 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28 -make_tracks metal6 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28 -make_tracks metal7 -x_offset 0.095 -x_pitch 0.8 -y_offset 0.07 -y_pitch 0.8 -make_tracks metal8 -x_offset 0.095 -x_pitch 0.8 -y_offset 0.07 -y_pitch 0.8 -make_tracks metal9 -x_offset 0.095 -x_pitch 1.6 -y_offset 0.07 -y_pitch 1.6 +make_tracks metal2 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14 +make_tracks metal3 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14 +make_tracks metal4 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28 +make_tracks metal5 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28 +make_tracks metal6 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28 +make_tracks metal7 -x_offset 0.095 -x_pitch 0.8 -y_offset 0.07 -y_pitch 0.8 +make_tracks metal8 -x_offset 0.095 -x_pitch 0.8 -y_offset 0.07 -y_pitch 0.8 +make_tracks metal9 -x_offset 0.095 -x_pitch 1.6 -y_offset 0.07 -y_pitch 1.6 make_tracks metal10 -x_offset 0.095 -x_pitch 1.6 -y_offset 0.07 -y_pitch 1.6 diff --git a/flow/platforms/nangate45/setRC.tcl b/flow/platforms/nangate45/setRC.tcl index d52baaa67d..f39d456de7 100644 --- a/flow/platforms/nangate45/setRC.tcl +++ b/flow/platforms/nangate45/setRC.tcl @@ -12,4 +12,4 @@ set_layer_rc -layer metal8 -resistance 1.8750e-04 -capacitance 9.69714E-02 #set_layer_rc -layer metal10 -resistance 3.7500e-05 -capacitance 2.8042e-02 set_wire_rc -signal -layer metal3 -set_wire_rc -clock -layer metal5 +set_wire_rc -clock -layer metal5 diff --git a/flow/platforms/nangate45/tapcell.tcl b/flow/platforms/nangate45/tapcell.tcl index 9057b795cd..edd4e1d15b 100644 --- a/flow/platforms/nangate45/tapcell.tcl +++ b/flow/platforms/nangate45/tapcell.tcl @@ -2,4 +2,3 @@ tapcell \ -distance 120 \ -tapcell_master "$::env(TAP_CELL_NAME)" \ -endcap_master "$::env(TAP_CELL_NAME)" - diff --git a/flow/platforms/sky130hd/fastroute.tcl b/flow/platforms/sky130hd/fastroute.tcl index 24af379c99..76f9321967 100644 --- a/flow/platforms/sky130hd/fastroute.tcl +++ b/flow/platforms/sky130hd/fastroute.tcl @@ -2,4 +2,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/platforms/sky130hd/pdn.tcl b/flow/platforms/sky130hd/pdn.tcl index 1901913015..cb158996c8 100644 --- a/flow/platforms/sky130hd/pdn.tcl +++ b/flow/platforms/sky130hd/pdn.tcl @@ -30,10 +30,12 @@ add_pdn_connect -grid {grid} -layers {met4 met5} #################################### # grid for: CORE_macro_grid_1 #################################### -define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary +define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro \ + -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary add_pdn_connect -grid {CORE_macro_grid_1} -layers {met4 met5} #################################### # grid for: CORE_macro_grid_2 #################################### -define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary +define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro \ + -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary add_pdn_connect -grid {CORE_macro_grid_2} -layers {met4 met5} diff --git a/flow/platforms/sky130hs/config.mk b/flow/platforms/sky130hs/config.mk index 73781e2512..5b66822431 100644 --- a/flow/platforms/sky130hs/config.mk +++ b/flow/platforms/sky130hs/config.mk @@ -77,6 +77,7 @@ export PLACE_DENSITY ?= 0.50 # --------------------------------------------------------- # FastRoute options export MIN_ROUTING_LAYER = met1 +export MIN_CLK_ROUTING_LAYER = met3 export MAX_ROUTING_LAYER = met5 # # Define fastRoute tcl diff --git a/flow/platforms/sky130hs/fastroute.tcl b/flow/platforms/sky130hs/fastroute.tcl index 06c2749720..76f9321967 100644 --- a/flow/platforms/sky130hs/fastroute.tcl +++ b/flow/platforms/sky130hs/fastroute.tcl @@ -1,3 +1,4 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.2 +set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) diff --git a/flow/platforms/sky130hs/pdn.tcl b/flow/platforms/sky130hs/pdn.tcl index 546a9a084f..8597d2a4bb 100644 --- a/flow/platforms/sky130hs/pdn.tcl +++ b/flow/platforms/sky130hs/pdn.tcl @@ -30,10 +30,12 @@ add_pdn_connect -grid {grid} -layers {met4 met5} #################################### # grid for: CORE_macro_grid_1 #################################### -define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary +define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro \ + -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary add_pdn_connect -grid {CORE_macro_grid_1} -layers {met4 met5} #################################### # grid for: CORE_macro_grid_2 #################################### -define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary +define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro \ + -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary add_pdn_connect -grid {CORE_macro_grid_2} -layers {met4 met5} diff --git a/flow/scripts/add_routing_blk.tcl b/flow/scripts/add_routing_blk.tcl index 7fc079f446..f4aadedbe7 100644 --- a/flow/scripts/add_routing_blk.tcl +++ b/flow/scripts/add_routing_blk.tcl @@ -22,19 +22,19 @@ foreach inst $allInsts { set loc_llx [lindex [$inst getLocation] 0] set loc_lly [lindex [$inst getLocation] 1] - if {[string match "*gf12*" $name]||[string match "IN12LP*" $name]} { + if { [string match "*gf12*" $name] || [string match "IN12LP*" $name] } { set w [$master getWidth] set h [$master getHeight] - set llx_Mx [expr $loc_llx - (128*$numTrack)] - set lly_Mx [expr $loc_lly - (128*$numTrack)] - set urx_Mx [expr $loc_llx + $w + (128*$numTrack)] - set ury_Mx [expr $loc_lly + $h + (128*$numTrack)] + set llx_Mx [expr $loc_llx - (128*$numTrack)] + set lly_Mx [expr $loc_lly - (128*$numTrack)] + set urx_Mx [expr $loc_llx + $w + (128*$numTrack)] + set ury_Mx [expr $loc_lly + $h + (128*$numTrack)] - set llx_Cx $loc_llx - set lly_Cx [expr $loc_lly - (160*$numTrack)] - set urx_Cx [expr $loc_llx + $w] - set ury_Cx [expr $loc_lly + $h + (160*$numTrack)] + set llx_Cx $loc_llx + set lly_Cx [expr $loc_lly - (160*$numTrack)] + set urx_Cx [expr $loc_llx + $w] + set ury_Cx [expr $loc_lly + $h + (160*$numTrack)] set obs_M2 [odb::dbObstruction_create $block $layer_M2 $llx_Mx $lly_Mx $urx_Mx $ury_Mx] set obs_M3 [odb::dbObstruction_create $block $layer_M3 $llx_Mx $lly_Mx $urx_Mx $ury_Mx] @@ -44,6 +44,6 @@ foreach inst $allInsts { } } -if {$cnt != 0} { +if { $cnt != 0 } { puts "Created $cnt routing blockages over macros" } diff --git a/flow/scripts/cts.tcl b/flow/scripts/cts.tcl index bd00159887..0fe80f63ad 100644 --- a/flow/scripts/cts.tcl +++ b/flow/scripts/cts.tcl @@ -7,7 +7,7 @@ load_design 3_place.odb 3_place.sdc # so cts does not try to buffer the inverted clocks. repair_clock_inverters -proc save_progress {stage} { +proc save_progress { stage } { puts "Run 'make gui_$stage.odb' to load progress snapshot" write_db $::env(RESULTS_DIR)/$stage.odb write_sdc -no_timestamp $::env(RESULTS_DIR)/$stage.sdc @@ -15,71 +15,56 @@ proc save_progress {stage} { # Run CTS set cts_args [list \ - -sink_clustering_enable \ - -balance_levels] - -# TODO: The first three are no-ops since the arg order is wrong, but hard to get -# through CI since nine designs change metrics and the PR is blocked -append_env_var cts_args -distance_between_buffers CTS_BUF_DISTANCE 1 -append_env_var cts_args -sink_clustering_size CTS_CLUSTER_SIZE 1 -append_env_var cts_args -sink_clustering_max_diameter CTS_CLUSTER_DIAMETER 1 -append_env_var cts_args CTS_BUF_LIST -buf_list 1 + -sink_clustering_enable \ + -balance_levels \ + -repair_clock_nets] -if {[env_var_exists_and_non_empty CTS_ARGS]} { - set cts_args $::env(CTS_ARGS) -} +append_env_var cts_args CTS_BUF_DISTANCE -distance_between_buffers 1 +append_env_var cts_args CTS_CLUSTER_SIZE -sink_clustering_size 1 +append_env_var cts_args CTS_CLUSTER_DIAMETER -sink_clustering_max_diameter 1 +append_env_var cts_args CTS_BUF_LIST -buf_list 1 +append_env_var cts_args CTS_LIB_NAME -library 1 -log_cmd clock_tree_synthesis {*}$cts_args -if {[env_var_equals CTS_SNAPSHOTS 1]} { - save_progress 4_1_pre_repair_clock_nets +if { [env_var_exists_and_non_empty CTS_ARGS] } { + set cts_args $::env(CTS_ARGS) } -set_propagated_clock [all_clocks] - set_dont_use $::env(DONT_USE_CELLS) -utl::push_metrics_stage "cts__{}__pre_repair" - -estimate_parasitics -placement -if { $::env(DETAILED_METRICS) } { - report_metrics 4 "cts pre-repair" -} -utl::pop_metrics_stage - -repair_clock_nets +log_cmd clock_tree_synthesis {*}$cts_args -utl::push_metrics_stage "cts__{}__post_repair" +utl::push_metrics_stage "cts__{}__pre_repair_timing" estimate_parasitics -placement if { $::env(DETAILED_METRICS) } { - report_metrics 4 "cts post-repair" + report_metrics 4 "cts pre-repair-timing" } utl::pop_metrics_stage set_placement_padding -global \ - -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ - -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) + -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ + -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) detailed_placement estimate_parasitics -placement -if {[env_var_equals CTS_SNAPSHOTS 1]} { +if { [env_var_equals CTS_SNAPSHOTS 1] } { save_progress 4_1_pre_repair_hold_setup } -if {![env_var_equals SKIP_CTS_REPAIR_TIMING 1]} { - if {$::env(EQUIVALENCE_CHECK)} { - write_eqy_verilog 4_before_rsz.v +if { ![env_var_equals SKIP_CTS_REPAIR_TIMING 1] } { + if { $::env(EQUIVALENCE_CHECK) } { + write_eqy_verilog 4_before_rsz.v } repair_timing_helper - if {$::env(EQUIVALENCE_CHECK)} { - run_equivalence_test + if { $::env(EQUIVALENCE_CHECK) } { + run_equivalence_test } - set result [catch {detailed_placement} msg] - if {$result != 0} { + set result [catch { detailed_placement } msg] + if { $result != 0 } { save_progress 4_1_error puts "Detailed placement failed in CTS: $msg" exit $result @@ -90,9 +75,7 @@ if {![env_var_equals SKIP_CTS_REPAIR_TIMING 1]} { report_metrics 4 "cts final" -if { [env_var_exists_and_non_empty POST_CTS_TCL] } { - source $::env(POST_CTS_TCL) -} +source_env_var_if_exists POST_CTS_TCL write_db $::env(RESULTS_DIR)/4_1_cts.odb write_sdc -no_timestamp $::env(RESULTS_DIR)/4_cts.sdc diff --git a/flow/scripts/deleteNonClkNets.tcl b/flow/scripts/deleteNonClkNets.tcl index 0a6e80bb3c..bad10a4772 100644 --- a/flow/scripts/deleteNonClkNets.tcl +++ b/flow/scripts/deleteNonClkNets.tcl @@ -1,6 +1,6 @@ read_lef $::env(TECH_LEF) read_lef $::env(SC_LEF) -if {[info exist ::env(ADDITIONAL_LEFS)]} { +if { [info exist ::env(ADDITIONAL_LEFS)] } { foreach lef $::env(ADDITIONAL_LEFS) { read_lef $lef } @@ -13,24 +13,26 @@ source $::env(SCRIPTS_DIR)/read_liberty.tcl read_def $::env(RESULTS_DIR)/6_final.def set block [[[ord::get_db] getChip] getBlock] -set nets [$block getNets] +set nets [$block getNets] set insts [$block getInsts] # Delete all non-clock nets foreach net $nets { set sigType [$net getSigType] set wire [$net getWire] - if {"$sigType" eq "SIGNAL" && "$wire" ne "NULL"} { + if { "$sigType" eq "SIGNAL" && "$wire" ne "NULL" } { odb::dbWire_destroy $wire - } elseif {"$sigType" eq "POWER" || - "$sigType" eq "GROUND"} { + } elseif { + "$sigType" eq "POWER" || + "$sigType" eq "GROUND" + } { $net destroySWires } } # Delete fill cells to clean up screenshot foreach inst $insts { - if {"[[$inst getMaster] getType]" eq "CORE_SPACER"} { + if { "[[$inst getMaster] getType]" eq "CORE_SPACER" } { odb::dbInst_destroy $inst } } diff --git a/flow/scripts/deletePowerNets.tcl b/flow/scripts/deletePowerNets.tcl index 74120d50b3..e1e6def4e1 100644 --- a/flow/scripts/deletePowerNets.tcl +++ b/flow/scripts/deletePowerNets.tcl @@ -1,6 +1,6 @@ read_lef $::env(TECH_LEF) read_lef $::env(SC_LEF) -if {[info exist ::env(ADDITIONAL_LEFS)]} { +if { [info exist ::env(ADDITIONAL_LEFS)] } { foreach lef $::env(ADDITIONAL_LEFS) { read_lef $lef } @@ -12,7 +12,7 @@ source $::env(SCRIPTS_DIR)/read_liberty.tcl # Read def and sdc read_def $::env(RESULTS_DIR)/6_final.def -proc deleteNetByName {name} { +proc deleteNetByName { name } { set db [ord::get_db] set chip [$db getChip] set block [$chip getBlock] diff --git a/flow/scripts/deleteRoutingObstructions.tcl b/flow/scripts/deleteRoutingObstructions.tcl index 5f78de4e06..2743009338 100644 --- a/flow/scripts/deleteRoutingObstructions.tcl +++ b/flow/scripts/deleteRoutingObstructions.tcl @@ -1,4 +1,4 @@ -proc deleteRoutingObstructions {} { +proc deleteRoutingObstructions { } { set db [ord::get_db] set chip [$db getChip] set block [$chip getBlock] diff --git a/flow/scripts/density_fill.tcl b/flow/scripts/density_fill.tcl index 3709a447d3..0c4e10585e 100644 --- a/flow/scripts/density_fill.tcl +++ b/flow/scripts/density_fill.tcl @@ -2,7 +2,7 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables final load_design 5_route.odb 5_route.sdc -if {[env_var_equals USE_FILL 1]} { +if { [env_var_equals USE_FILL 1] } { set_propagated_clock [all_clocks] density_fill -rules $::env(FILL_CONFIG) # The .v file is just for debugging purposes, not a result of diff --git a/flow/scripts/detail_place.tcl b/flow/scripts/detail_place.tcl index a92a5ae800..c093b162fe 100644 --- a/flow/scripts/detail_place.tcl +++ b/flow/scripts/detail_place.tcl @@ -5,19 +5,19 @@ load_design 3_4_place_resized.odb 2_floorplan.sdc source $::env(PLATFORM_DIR)/setRC.tcl -proc do_dpl {} { +proc do_dpl { } { # Only for use with hybrid rows - if {[env_var_equals BALANCE_ROWS 1]} { + if { [env_var_equals BALANCE_ROWS 1] } { balance_row_usage } - + set_placement_padding -global \ - -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ - -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) + -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ + -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) detailed_placement - - if {[env_var_equals ENABLE_DPO 1]} { - if {[env_var_exists_and_non_empty DPO_MAX_DISPLACEMENT]} { + + if { [env_var_equals ENABLE_DPO 1] } { + if { [env_var_exists_and_non_empty DPO_MAX_DISPLACEMENT] } { improve_placement -max_displacement $::env(DPO_MAX_DISPLACEMENT) } else { improve_placement @@ -26,12 +26,12 @@ proc do_dpl {} { optimize_mirroring utl::info FLW 12 "Placement violations [check_placement -verbose]." - + estimate_parasitics -placement } -set result [catch {do_dpl} errMsg] -if {$result != 0} { +set result [catch { do_dpl } errMsg] +if { $result != 0 } { write_db $::env(RESULTS_DIR)/3_5_place_dp-failed.odb error $errMsg } diff --git a/flow/scripts/detail_route.tcl b/flow/scripts/detail_route.tcl index 330b93b49c..28eccba75c 100644 --- a/flow/scripts/detail_route.tcl +++ b/flow/scripts/detail_route.tcl @@ -1,7 +1,7 @@ utl::set_metrics_stage "detailedroute__{}" source $::env(SCRIPTS_DIR)/load.tcl load_design 5_1_grt.odb 5_1_grt.sdc -if {![grt::have_routes]} { +if { ![grt::have_routes] } { error "Global routing failed, run `make gui_grt` and load $::global_route_congestion_report \ in DRC viewer to view congestion" } @@ -36,8 +36,10 @@ append additional_args " -verbose 1" # having to go spelunking in Tcl or modify configuration scripts, while # not having to wait too long or generating large useless reports. -set arguments [expr {[env_var_exists_and_non_empty DETAILED_ROUTE_ARGS] ? $::env(DETAILED_ROUTE_ARGS) : \ - [concat $additional_args {-drc_report_iter_step 5}]}] +set arguments [expr { + [env_var_exists_and_non_empty DETAILED_ROUTE_ARGS] ? $::env(DETAILED_ROUTE_ARGS) : + [concat $additional_args {-drc_report_iter_step 5}] +}] set all_args [concat [list \ -output_drc $::env(REPORTS_DIR)/5_route_drc.rpt \ @@ -46,14 +48,12 @@ set all_args [concat [list \ log_cmd detailed_route {*}$all_args -fast_route - -if {![env_var_equals SKIP_ANTENNA_REPAIR_POST_DRT 1]} { +if { ![env_var_equals SKIP_ANTENNA_REPAIR_POST_DRT 1] } { set repair_antennas_iters 1 - if {[repair_antennas]} { + if { [repair_antennas] } { detailed_route {*}$all_args } - while {[check_antennas] && $repair_antennas_iters < 5} { + while { [check_antennas] && $repair_antennas_iters < 5 } { repair_antennas detailed_route {*}$all_args incr repair_antennas_iters @@ -62,13 +62,11 @@ if {![env_var_equals SKIP_ANTENNA_REPAIR_POST_DRT 1]} { utl::metric_int "antenna_diodes_count" -1 } -if { [env_var_exists_and_non_empty POST_DETAIL_ROUTE_TCL] } { - source $::env(POST_DETAIL_ROUTE_TCL) -} +source_env_var_if_exists POST_DETAIL_ROUTE_TCL check_antennas -report_file $env(REPORTS_DIR)/drt_antennas.log -if {![design_is_routed]} { +if { ![design_is_routed] } { error "Design has unrouted nets." } diff --git a/flow/scripts/fillcell.tcl b/flow/scripts/fillcell.tcl index 293f69ac83..ea23e5b24f 100644 --- a/flow/scripts/fillcell.tcl +++ b/flow/scripts/fillcell.tcl @@ -1,6 +1,6 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables route -if {[env_var_exists_and_non_empty FILL_CELLS]} { +if { [env_var_exists_and_non_empty FILL_CELLS] } { load_design 5_2_route.odb 5_1_grt.sdc set_propagated_clock [all_clocks] diff --git a/flow/scripts/final_report.tcl b/flow/scripts/final_report.tcl index d5c8d98e6a..a843d6dad6 100644 --- a/flow/scripts/final_report.tcl +++ b/flow/scripts/final_report.tcl @@ -18,11 +18,10 @@ write_def $::env(RESULTS_DIR)/6_final.def write_verilog $::env(RESULTS_DIR)/6_final.v # Run extraction and STA -if {[env_var_exists_and_non_empty RCX_RULES]} { - +if { [env_var_exists_and_non_empty RCX_RULES] } { # Set RC corner for RCX # Set in config.mk - if {[env_var_exists_and_non_empty RCX_RC_CORNER]} { + if { [env_var_exists_and_non_empty RCX_RC_CORNER] } { set rc_corner $::env(RCX_RC_CORNER) } @@ -38,25 +37,24 @@ if {[env_var_exists_and_non_empty RCX_RULES]} { read_spef $::env(RESULTS_DIR)/6_final.spef # Static IR drop analysis - if {[env_var_exists_and_non_empty PWR_NETS_VOLTAGES]} { + if { [env_var_exists_and_non_empty PWR_NETS_VOLTAGES] } { dict for {pwrNetName pwrNetVoltage} $::env(PWR_NETS_VOLTAGES) { - set_pdnsim_net_voltage -net ${pwrNetName} -voltage ${pwrNetVoltage} - analyze_power_grid -net ${pwrNetName} \ - -error_file $::env(REPORTS_DIR)/${pwrNetName}.rpt + set_pdnsim_net_voltage -net ${pwrNetName} -voltage ${pwrNetVoltage} + analyze_power_grid -net ${pwrNetName} \ + -error_file $::env(REPORTS_DIR)/${pwrNetName}.rpt } } else { puts "IR drop analysis for power nets is skipped because PWR_NETS_VOLTAGES is undefined" } - if {[env_var_exists_and_non_empty GND_NETS_VOLTAGES]} { + if { [env_var_exists_and_non_empty GND_NETS_VOLTAGES] } { dict for {gndNetName gndNetVoltage} $::env(GND_NETS_VOLTAGES) { - set_pdnsim_net_voltage -net ${gndNetName} -voltage ${gndNetVoltage} - analyze_power_grid -net ${gndNetName} \ - -error_file $::env(REPORTS_DIR)/${gndNetName}.rpt + set_pdnsim_net_voltage -net ${gndNetName} -voltage ${gndNetVoltage} + analyze_power_grid -net ${gndNetName} \ + -error_file $::env(REPORTS_DIR)/${gndNetName}.rpt } } else { puts "IR drop analysis for ground nets is skipped because GND_NETS_VOLTAGES is undefined" } - } else { puts "OpenRCX is not enabled for this platform." } @@ -66,6 +64,6 @@ report_cell_usage report_metrics 6 "finish" # Save a final image if openroad is compiled with the gui -if {[ord::openroad_gui_compiled]} { - gui::show "source $::env(SCRIPTS_DIR)/save_images.tcl" false +if { [ord::openroad_gui_compiled] } { + gui::show "source $::env(SCRIPTS_DIR)/save_images.tcl" false } diff --git a/flow/scripts/floorplan.tcl b/flow/scripts/floorplan.tcl index 259e97d57f..5adda7dd99 100644 --- a/flow/scripts/floorplan.tcl +++ b/flow/scripts/floorplan.tcl @@ -3,14 +3,14 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables floorplan load_design 1_synth.v 1_synth.sdc -proc report_unused_masters {} { +proc report_unused_masters { } { set db [ord::get_db] set libs [$db getLibs] set masters "" foreach lib $libs { foreach master [$lib getMasters] { # filter out non-block masters, or you can remove this conditional to detect any unused master - if {[$master getType] == "BLOCK"} { + if { [$master getType] == "BLOCK" } { lappend masters $master } } @@ -45,157 +45,82 @@ append_env_var additional_args ADDITIONAL_SITES -additional_sites 1 set use_floorplan_def [env_var_exists_and_non_empty FLOORPLAN_DEF] set use_footprint [env_var_exists_and_non_empty FOOTPRINT] -set use_die_and_core_area [expr {[env_var_exists_and_non_empty DIE_AREA] && [env_var_exists_and_non_empty CORE_AREA]}] +set use_die_and_core_area \ + [expr { [env_var_exists_and_non_empty DIE_AREA] && [env_var_exists_and_non_empty CORE_AREA] }] set use_core_utilization [env_var_exists_and_non_empty CORE_UTILIZATION] -set methods_defined [expr {$use_floorplan_def + $use_footprint + $use_die_and_core_area + $use_core_utilization}] -if {$methods_defined > 1} { - puts "Error: Floorplan initialization methods are mutually exclusive, pick one." - exit 1 +set methods_defined \ + [expr { $use_floorplan_def + $use_footprint + $use_die_and_core_area + $use_core_utilization }] +if { $methods_defined > 1 } { + puts "Error: Floorplan initialization methods are mutually exclusive, pick one." + exit 1 } -if {$use_floorplan_def} { - # Initialize floorplan by reading in floorplan DEF - log_cmd read_def -floorplan_initialize $env(FLOORPLAN_DEF) -} elseif {$use_footprint} { - # Initialize floorplan using ICeWall FOOTPRINT - ICeWall load_footprint $env(FOOTPRINT) - - initialize_floorplan \ - -die_area [ICeWall get_die_area] \ - -core_area [ICeWall get_core_area] \ - -site $::env(PLACE_SITE) - - ICeWall init_footprint $env(SIG_MAP_FILE) -} elseif {$use_die_and_core_area} { - initialize_floorplan -die_area $::env(DIE_AREA) \ - -core_area $::env(CORE_AREA) \ - -site $::env(PLACE_SITE) \ - {*}$additional_args -} elseif {$use_core_utilization} { - set aspect_ratio 1.0 - if {[env_var_exists_and_non_empty "CORE_ASPECT_RATIO"]} { - set aspect_ratio $::env(CORE_ASPECT_RATIO) - } - set core_margin 1.0 - if {[env_var_exists_and_non_empty "CORE_MARGIN"]} { - set core_margin $::env(CORE_MARGIN) - } - initialize_floorplan -utilization $::env(CORE_UTILIZATION) \ - -aspect_ratio $aspect_ratio \ - -core_space $core_margin \ - -site $::env(PLACE_SITE) \ - {*}$additional_args +if { $use_floorplan_def } { + # Initialize floorplan by reading in floorplan DEF + log_cmd read_def -floorplan_initialize $env(FLOORPLAN_DEF) +} elseif { $use_footprint } { + # Initialize floorplan using ICeWall FOOTPRINT + ICeWall load_footprint $env(FOOTPRINT) + + initialize_floorplan \ + -die_area [ICeWall get_die_area] \ + -core_area [ICeWall get_core_area] \ + -site $::env(PLACE_SITE) + + ICeWall init_footprint $env(SIG_MAP_FILE) +} elseif { $use_die_and_core_area } { + initialize_floorplan -die_area $::env(DIE_AREA) \ + -core_area $::env(CORE_AREA) \ + -site $::env(PLACE_SITE) \ + {*}$additional_args +} elseif { $use_core_utilization } { + initialize_floorplan -utilization $::env(CORE_UTILIZATION) \ + -aspect_ratio $::env(CORE_ASPECT_RATIO) \ + -core_space $::env(CORE_MARGIN) \ + -site $::env(PLACE_SITE) \ + {*}$additional_args } else { - puts "Error: No floorplan initialization method specified" - exit 1 + puts "Error: No floorplan initialization method specified" + exit 1 } if { [env_var_exists_and_non_empty MAKE_TRACKS] } { log_cmd source $::env(MAKE_TRACKS) -} elseif {[file exists $::env(PLATFORM_DIR)/make_tracks.tcl]} { +} elseif { [file exists $::env(PLATFORM_DIR)/make_tracks.tcl] } { log_cmd source $::env(PLATFORM_DIR)/make_tracks.tcl } else { make_tracks } -if {[env_var_exists_and_non_empty FOOTPRINT_TCL]} { - log_cmd source $::env(FOOTPRINT_TCL) +source_env_var_if_exists FOOTPRINT_TCL + +# This needs to come before any call to remove_buffers. You could have one +# tie driving multiple buffers that drive multiple outputs. +repair_tie_fanout_helper + +if { [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] } { + estimate_parasitics -placement + replace_arith_modules } if { [env_var_equals REMOVE_ABC_BUFFERS 1] } { # remove buffers inserted by yosys/abc remove_buffers } else { - repair_timing_helper 0 + # Skip clone & split + set ::env(SETUP_MOVE_SEQUENCE) "unbuffer,sizeup,swap,buffer" + set ::env(SKIP_LAST_GASP) 1 + repair_timing_helper -setup } -##### Restructure for timing ######### -if { [env_var_equals RESYNTH_TIMING_RECOVER 1] } { - repair_design_helper - repair_timing_helper - # pre restructure area/timing report (ideal clocks) - puts "Post synth-opt area" - report_design_area - report_worst_slack -min -digits 3 - puts "Post synth-opt wns" - report_worst_slack -max -digits 3 - puts "Post synth-opt tns" - report_tns -digits 3 - - write_verilog $::env(RESULTS_DIR)/2_pre_abc_timing.v - - restructure -target timing -liberty_file $::env(DONT_USE_SC_LIB) \ - -work_dir $::env(RESULTS_DIR) - - write_verilog $::env(RESULTS_DIR)/2_post_abc_timing.v - - # post restructure area/timing report (ideal clocks) - remove_buffers - repair_design_helper - repair_timing_helper - - puts "Post restructure-opt wns" - report_worst_slack -max -digits 3 - puts "Post restructure-opt tns" - report_tns -digits 3 - - # remove buffers inserted by optimization - remove_buffers -} - - puts "Default units for flow" report_units report_units_metric report_metrics 2 "floorplan final" false false -if { [env_var_equals RESYNTH_AREA_RECOVER 1] } { - - utl::push_metrics_stage "floorplan__{}__pre_restruct" - set num_instances [llength [get_cells -hier *]] - puts "number instances before restructure is $num_instances" - puts "Design Area before restructure" - report_design_area - report_design_area_metrics - utl::pop_metrics_stage - - write_verilog $::env(RESULTS_DIR)/2_pre_abc.v - - set tielo_cell_name [lindex $env(TIELO_CELL_AND_PORT) 0] - set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]] - set tielo_port $tielo_lib_name/$tielo_cell_name/[lindex $env(TIELO_CELL_AND_PORT) 1] - - set tiehi_cell_name [lindex $env(TIEHI_CELL_AND_PORT) 0] - set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]] - set tiehi_port $tiehi_lib_name/$tiehi_cell_name/[lindex $env(TIEHI_CELL_AND_PORT) 1] - - restructure -liberty_file $::env(DONT_USE_SC_LIB) -target "area" \ - -tiehi_port $tiehi_port \ - -tielo_port $tielo_port \ - -work_dir $::env(RESULTS_DIR) - - # remove buffers inserted by abc - remove_buffers - - write_verilog $::env(RESULTS_DIR)/2_post_abc.v - utl::push_metrics_stage "floorplan__{}__post_restruct" - set num_instances [llength [get_cells -hier *]] - puts "number instances after restructure is $num_instances" - puts "Design Area after restructure" - report_design_area - report_design_area_metrics - utl::pop_metrics_stage -} - -if { [env_var_exists_and_non_empty POST_FLOORPLAN_TCL] } { - log_cmd source $::env(POST_FLOORPLAN_TCL) -} - - -if {[env_var_exists_and_non_empty IO_CONSTRAINTS]} { - log_cmd source $::env(IO_CONSTRAINTS) -} +source_env_var_if_exists POST_FLOORPLAN_TCL +source_env_var_if_exists IO_CONSTRAINTS write_db $::env(RESULTS_DIR)/2_1_floorplan.odb write_sdc -no_timestamp $::env(RESULTS_DIR)/2_1_floorplan.sdc diff --git a/flow/scripts/flow.sh b/flow/scripts/flow.sh index 2d2e037927..96ef5615e0 100755 --- a/flow/scripts/flow.sh +++ b/flow/scripts/flow.sh @@ -6,3 +6,6 @@ echo Running $2.tcl, stage $1 $OPENROAD_EXE $OPENROAD_ARGS -exit $SCRIPTS_DIR/noop.tcl 2>&1 >$LOG_DIR/$1.tmp.log; \ eval "$TIME_CMD $OPENROAD_CMD -no_splash $SCRIPTS_DIR/$2.tcl -metrics $LOG_DIR/$1.json" 2>&1 | \ tee -a $(realpath $LOG_DIR/$1.tmp.log)) +# Log the hash for this step. The summary "make elapsed" in "make finish", +# will not have all the .odb files for the bazel-orfs use-case. +$PYTHON_EXE $UTILS_DIR/genElapsedTime.py --match $1 -d $LOG_DIR | tee -a $(realpath $LOG_DIR/$1.log) diff --git a/flow/scripts/generate-variables-docs.py b/flow/scripts/generate-variables-docs.py index 241edeb245..75a38d6f4f 100755 --- a/flow/scripts/generate-variables-docs.py +++ b/flow/scripts/generate-variables-docs.py @@ -26,8 +26,8 @@ markdown_table += "## Variables in alphabetic order\n\n" table_header = """ -| Variable | Description | Default | Deprecated | -| --- | --- | --- | --- | +| Variable | Description | Default | +| --- | --- | --- | """ table_rows = "" for key in sorted(data): @@ -35,9 +35,9 @@ description = value.get("description", "").replace("\n", " ").strip() table_rows += ( f'| {key}' + + f'{" (deprecated)" if value.get("deprecated", 0) == 1 else ""}' + f"| {description}" + f'| {value.get("default", "")}' - + f'| {"yes" if value.get("deprecated", 0) == 1 else ""}' + "|\n" ) diff --git a/flow/scripts/generate_abstract.tcl b/flow/scripts/generate_abstract.tcl index 32364a3e4d..9940ad3660 100644 --- a/flow/scripts/generate_abstract.tcl +++ b/flow/scripts/generate_abstract.tcl @@ -1,7 +1,11 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables generate_abstract -set stem [expr {[env_var_exists_and_non_empty ABSTRACT_SOURCE] ? $::env(ABSTRACT_SOURCE) : "6_final"}] +set stem [expr { + [env_var_exists_and_non_empty ABSTRACT_SOURCE] ? + $::env(ABSTRACT_SOURCE) : + "6_final" +}] set result [find_sdc_file $stem.odb] set design_stage [lindex $result 0] @@ -9,22 +13,30 @@ set sdc_file [lindex $result 1] log_cmd load_design $stem.odb [file tail $sdc_file] -if {$design_stage >= 6 && [file exists $::env(RESULTS_DIR)/$stem.spef]} { +if { $design_stage >= 6 && [file exists $::env(RESULTS_DIR)/$stem.spef] } { log_cmd read_spef $::env(RESULTS_DIR)/$stem.spef -} elseif {$design_stage >= 3} { +} elseif { $design_stage >= 3 } { log_cmd estimate_parasitics -placement } -if {$design_stage >= 4} { +if { $design_stage >= 4 } { set_propagated_clock [all_clocks] } # write_timing_model includes the source latency in the model set_clock_latency -source 0 [all_clocks] puts "Generating abstract views" -log_cmd write_timing_model $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lib +if { [env_var_exists_and_non_empty CORNERS] } { + # corners + foreach corner $::env(CORNERS) { + log_cmd write_timing_model -corner $corner $::env(RESULTS_DIR)/$::env(DESIGN_NAME)_$corner.lib + } + unset corner +} else { + log_cmd write_timing_model $::env(RESULTS_DIR)/$::env(DESIGN_NAME)_typ.lib +} log_cmd write_abstract_lef -bloat_occupied_layers $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lef -if {[env_var_exists_and_non_empty CDL_FILES]} { +if { [env_var_exists_and_non_empty CDL_FILES] } { cdl read_masters $::env(CDL_FILES) cdl out $::env(RESULTS_DIR)/$stem.cdl } diff --git a/flow/scripts/global_place.tcl b/flow/scripts/global_place.tcl index 5969c9e9d8..ac9d5c6722 100644 --- a/flow/scripts/global_place.tcl +++ b/flow/scripts/global_place.tcl @@ -5,6 +5,19 @@ load_design 3_2_place_iop.odb 2_floorplan.sdc set_dont_use $::env(DONT_USE_CELLS) +remove_buffers + +# Do not buffer chip-level designs +# by default, IO ports will be buffered +# to not buffer IO ports, set environment variable +# DONT_BUFFER_PORT = 1 +if { ![env_var_exists_and_non_empty FOOTPRINT] } { + if { ![env_var_equals DONT_BUFFER_PORTS 1] } { + puts "Perform port buffering..." + buffer_ports + } +} + fast_route set global_placement_args {} @@ -13,33 +26,33 @@ set global_placement_args {} append_env_var global_placement_args GPL_ROUTABILITY_DRIVEN -routability_driven 0 # Parameters for timing driven mode in global placement -if {$::env(GPL_TIMING_DRIVEN)} { +if { $::env(GPL_TIMING_DRIVEN) } { lappend global_placement_args {-timing_driven} - if {[info exists ::env(GPL_KEEP_OVERFLOW)]} { + if { [info exists ::env(GPL_KEEP_OVERFLOW)] } { lappend global_placement_args -keep_resize_below_overflow $::env(GPL_KEEP_OVERFLOW) } } -proc do_placement {global_placement_args} { +proc do_placement { global_placement_args } { set all_args [concat [list -density [place_density_with_lb_addon] \ -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)] \ $global_placement_args] - lappend all_args {*}$::env(GLOBAL_PLACEMENT_ARGS) + lappend all_args {*}[env_var_or_empty GLOBAL_PLACEMENT_ARGS] log_cmd global_placement {*}$all_args } -set result [catch {do_placement $global_placement_args} errMsg] -if {$result != 0} { +set result [catch { do_placement $global_placement_args } errMsg] +if { $result != 0 } { write_db $::env(RESULTS_DIR)/3_3_place_gp-failed.odb error $errMsg } estimate_parasitics -placement -if {[env_var_equals CLUSTER_FLOPS 1]} { +if { [env_var_equals CLUSTER_FLOPS 1] } { cluster_flops estimate_parasitics -placement } diff --git a/flow/scripts/global_place_skip_io.tcl b/flow/scripts/global_place_skip_io.tcl index fa9a53d537..ff05f363f6 100644 --- a/flow/scripts/global_place_skip_io.tcl +++ b/flow/scripts/global_place_skip_io.tcl @@ -6,9 +6,9 @@ if { [env_var_exists_and_non_empty FLOORPLAN_DEF] } { puts "FLOORPLAN_DEF is set. Skipping global placement without IOs" } else { log_cmd global_placement -skip_io -density [place_density_with_lb_addon] \ - -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ - -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ - {*}$::env(GLOBAL_PLACEMENT_ARGS) + -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ + -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ + {*}[env_var_or_empty GLOBAL_PLACEMENT_ARGS] } write_db $::env(RESULTS_DIR)/3_1_place_gp_skip_io.odb diff --git a/flow/scripts/global_route.tcl b/flow/scripts/global_route.tcl index 32b33a0bb6..d0edcc993c 100644 --- a/flow/scripts/global_route.tcl +++ b/flow/scripts/global_route.tcl @@ -5,14 +5,10 @@ load_design 4_cts.odb 4_cts.sdc # This proc is here to allow us to use 'return' to return early from this # file which is sourced -proc global_route_helper {} { - if {[env_var_exists_and_non_empty PRE_GLOBAL_ROUTE]} { - source $::env(PRE_GLOBAL_ROUTE) - } - - fast_route +proc global_route_helper { } { + source_env_var_if_exists PRE_GLOBAL_ROUTE_TCL - proc do_global_route {} { + proc do_global_route { } { set all_args [concat [list \ -congestion_report_file $::global_route_congestion_report] \ $::env(GLOBAL_ROUTE_ARGS)] @@ -21,14 +17,16 @@ proc global_route_helper {} { } pin_access -bottom_routing_layer $::env(MIN_ROUTING_LAYER) \ - -top_routing_layer $::env(MAX_ROUTING_LAYER) + -top_routing_layer $::env(MAX_ROUTING_LAYER) - set result [catch {do_global_route} errMsg] + set result [catch { do_global_route } errMsg] - if {$result != 0} { - if {[expr !$::env(GENERATE_ARTIFACTS_ON_FAILURE) || \ + if { $result != 0 } { + if { + [!$::env(GENERATE_ARTIFACTS_ON_FAILURE) || \ ![file exists $::global_route_congestion_report] || \ - [file size $::global_route_congestion_report] == 0]} { + [file size $::global_route_congestion_report] == 0] + } { write_db $::env(RESULTS_DIR)/5_1_grt-failed.odb error $errMsg } @@ -38,13 +36,13 @@ proc global_route_helper {} { } set_placement_padding -global \ - -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ - -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) + -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ + -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) set_propagated_clock [all_clocks] estimate_parasitics -global_routing - if {[env_var_exists_and_non_empty DONT_USE_CELLS]} { + if { [env_var_exists_and_non_empty DONT_USE_CELLS] } { set_dont_use $::env(DONT_USE_CELLS) } @@ -64,7 +62,8 @@ proc global_route_helper {} { log_cmd global_route -start_incremental log_cmd detailed_placement # Route only the modified net by DPL - log_cmd global_route -end_incremental -congestion_report_file $::env(REPORTS_DIR)/congestion_post_repair_design.rpt + log_cmd global_route -end_incremental \ + -congestion_report_file $::env(REPORTS_DIR)/congestion_post_repair_design.rpt # Repair timing using global route parasitics puts "Repair setup and hold violations..." @@ -81,16 +80,18 @@ proc global_route_helper {} { log_cmd global_route -start_incremental log_cmd detailed_placement # Route only the modified net by DPL - log_cmd global_route -end_incremental -congestion_report_file $::env(REPORTS_DIR)/congestion_post_repair_timing.rpt + log_cmd global_route -end_incremental \ + -congestion_report_file $::env(REPORTS_DIR)/congestion_post_repair_timing.rpt } log_cmd global_route -start_incremental recover_power_helper # Route the modified nets by rsz journal restore - log_cmd global_route -end_incremental -congestion_report_file $::env(REPORTS_DIR)/congestion_post_recover_power.rpt + log_cmd global_route -end_incremental \ + -congestion_report_file $::env(REPORTS_DIR)/congestion_post_recover_power.rpt - if {![env_var_equals SKIP_ANTENNA_REPAIR 1]} { + if { ![env_var_equals SKIP_ANTENNA_REPAIR 1] } { puts "Repair antennas..." repair_antennas -iterations 5 check_placement -verbose diff --git a/flow/scripts/io_placement.tcl b/flow/scripts/io_placement.tcl index dc29acc671..e4f61e0983 100644 --- a/flow/scripts/io_placement.tcl +++ b/flow/scripts/io_placement.tcl @@ -1,14 +1,16 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables place -if {![env_var_exists_and_non_empty FLOORPLAN_DEF] && \ - ![env_var_exists_and_non_empty FOOTPRINT] && \ - ![env_var_exists_and_non_empty FOOTPRINT_TCL]} { +if { + ![env_var_exists_and_non_empty FLOORPLAN_DEF] && + ![env_var_exists_and_non_empty FOOTPRINT] && + ![env_var_exists_and_non_empty FOOTPRINT_TCL] +} { load_design 3_1_place_gp_skip_io.odb 2_floorplan.sdc log_cmd place_pins \ -hor_layers $::env(IO_PLACER_H) \ -ver_layers $::env(IO_PLACER_V) \ - {*}$::env(PLACE_PINS_ARGS) + {*}[env_var_or_empty PLACE_PINS_ARGS] write_db $::env(RESULTS_DIR)/3_2_place_iop.odb write_pin_placement $::env(RESULTS_DIR)/3_2_place_iop.tcl } else { diff --git a/flow/scripts/klayout.tcl b/flow/scripts/klayout.tcl index 56cc08ad6b..811902d6c7 100644 --- a/flow/scripts/klayout.tcl +++ b/flow/scripts/klayout.tcl @@ -1,20 +1,20 @@ -if {[env_var_exists_and_non_empty FILL_CONFIG]} { - set fill_config $::env(FILL_CONFIG) +if { [env_var_exists_and_non_empty FILL_CONFIG] } { + set fill_config $::env(FILL_CONFIG) } else { - set fill_config "" + set fill_config "" } -if {[env_var_exists_and_non_empty SEAL_GDS]} { - set seal_gds $::env(SEAL_GDS) +if { [env_var_exists_and_non_empty SEAL_GDS] } { + set seal_gds $::env(SEAL_GDS) } else { - set seal_gds "" + set seal_gds "" } exec klayout -zz -rd design_name=$::env(DESIGN_NAME) \ - -rd in_def=$::env(RESULTS_DIR)/6_final.def \ - -rd in_files="$::env(GDSOAS_FILES) $::env(WRAPPED_GDSOAS)" \ - -rd config_file=$fill_config \ - -rd seal_file=$seal_gds \ - -rd out_file=$::env(RESULTS_DIR)/6_final.$::env(STREAM_SYSTEM_EXT) \ - -rd tech_file=$::env(OBJECTS_DIR)/klayout.lyt \ - -rm $::env(UTILS_DIR)/def2stream.py + -rd in_def=$::env(RESULTS_DIR)/6_final.def \ + -rd in_files="$::env(GDSOAS_FILES) $::env(WRAPPED_GDSOAS)" \ + -rd config_file=$fill_config \ + -rd seal_file=$seal_gds \ + -rd out_file=$::env(RESULTS_DIR)/6_final.$::env(STREAM_SYSTEM_EXT) \ + -rd tech_file=$::env(OBJECTS_DIR)/klayout.lyt \ + -rm $::env(UTILS_DIR)/def2stream.py diff --git a/flow/scripts/load.tcl b/flow/scripts/load.tcl index 4259e8cf28..3631c706b6 100644 --- a/flow/scripts/load.tcl +++ b/flow/scripts/load.tcl @@ -2,24 +2,39 @@ source $::env(SCRIPTS_DIR)/util.tcl source $::env(SCRIPTS_DIR)/report_metrics.tcl -proc load_design {design_file sdc_file} { - # Read liberty files +proc load_design { design_file sdc_file } { + source_env_var_if_exists PLATFORM_TCL + source $::env(SCRIPTS_DIR)/read_liberty.tcl # Read design files set ext [file extension $design_file] - if {$ext == ".v"} { + if { $ext == ".v" } { read_lef $::env(TECH_LEF) read_lef $::env(SC_LEF) - if {[env_var_exists_and_non_empty ADDITIONAL_LEFS]} { + if { [env_var_exists_and_non_empty ADDITIONAL_LEFS] } { foreach lef $::env(ADDITIONAL_LEFS) { read_lef $lef } } read_verilog $::env(RESULTS_DIR)/$design_file - link_design $::env(DESIGN_NAME) - } elseif {$ext == ".odb"} { - read_db $::env(RESULTS_DIR)/$design_file + if { + [env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] || + [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] + } { + link_design -hier $::env(DESIGN_NAME) + } else { + link_design $::env(DESIGN_NAME) + } + } elseif { $ext == ".odb" } { + if { + [env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] || + [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] + } { + read_db -hier $::env(RESULTS_DIR)/$design_file + } else { + read_db $::env(RESULTS_DIR)/$design_file + } } else { error "Unrecognized input file $design_file" } @@ -27,11 +42,11 @@ proc load_design {design_file sdc_file} { # Read SDC file read_sdc $::env(RESULTS_DIR)/$sdc_file - if [file exists $::env(PLATFORM_DIR)/derate.tcl] { + if { [file exists $::env(PLATFORM_DIR)/derate.tcl] } { log_cmd source $::env(PLATFORM_DIR)/derate.tcl } - log_cmd source $::env(PLATFORM_DIR)/setRC.tcl + source $::env(PLATFORM_DIR)/setRC.tcl if { [env_var_equals LIB_MODEL CCS] } { puts "Using CCS delay calculation" @@ -40,92 +55,101 @@ proc load_design {design_file sdc_file} { } #=========================================================================================== -# Routines to run equivalence tests when they are enabled. +# Routines to run equivalence tests when they are enabled. proc get_verilog_cells_for_design { } { - set dir "$::env(PLATFORM_DIR)/work_around_yosys/" - set cell_files [glob $dir/*.v ] + set dir "$::env(PLATFORM_DIR)/work_around_yosys/" + set cell_files [glob $dir/*.v] } -proc write_eqy_verilog {filename} { +proc write_eqy_verilog { filename } { # Filter out cells with no verilog/not needed for equivalence such # as fillers and tap cells - if {[env_var_exists_and_non_empty REMOVE_CELLS_FOR_EQY]} { + if { [env_var_exists_and_non_empty REMOVE_CELLS_FOR_EQY] } { write_verilog -remove_cells $::env(REMOVE_CELLS_FOR_EQY) $::env(RESULTS_DIR)/$filename } else { - write_verilog $::env(RESULTS_DIR)/$filename + write_verilog $::env(RESULTS_DIR)/$filename } } -proc write_eqy_script_for_sky130hd {} { - error "this routine is not yet implemented" - #[gold] - #read_verilog -sv ./before.v ./formal_pdk.v +proc write_eqy_script_for_sky130hd { } { + error "this routine is not yet implemented" + #[gold] + #read_verilog -sv ./before.v ./formal_pdk.v - #[gate] - #read_verilog -sv ./after.v ./formal_pdk.v + #[gate] + #read_verilog -sv ./after.v ./formal_pdk.v - #[script] - #prep -top aes_cipher_top -flatten + #[script] + #prep -top aes_cipher_top -flatten - ## Using `rename -hide` is a better performing choice than nomatch if the signal names have no meaning at all - #rename -hide */_*_.* + ## Using `rename -hide` is a better performing choice than nomatch + ## if the signal names have no meaning at all + #rename -hide */_*_.* - ## This removes unused signals before partitioning so no partitions are created for them - #opt_clean -purge - #memory_map + ## This removes unused signals before partitioning so no partitions are created for them + #opt_clean -purge + #memory_map - #[collect *] - ## This groups signals like `some_signal[0]`, `some_signal[1]`, ... that only differ in the index - #group *[] \1[] + #[collect *] + ## This groups signals like `some_signal[0]`, `some_signal[1]`, ... that only differ in the index + #group *[] \1[] - #[strategy basic] - #use sat - #depth 2 + #[strategy basic] + #use sat + #depth 2 } proc write_eqy_script { } { - set top_cell [current_design] - set cell_files [get_verilog_cells_for_design] - set outfile [open "$::env(OBJECTS_DIR)/4_eqy_test.eqy" w] - # Gold netlist - puts $outfile "\[gold]\nread_verilog -sv $::env(RESULTS_DIR)/4_before_rsz.v $cell_files\n" - puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n" - # Modified netlist - puts $outfile "\[gate]\nread_verilog -sv $::env(RESULTS_DIR)/4_after_rsz.v $cell_files\n" - puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n" - - # Recommendation from eqy team on how to speed up a design - puts $outfile "\[match *]\ngate-nomatch _*_.*" - - # See issue OpenROAD#6545 "Equivalence check failure due to non-unique resizer nets" - puts $outfile "gate-nomatch net*" - - # Necessary to avoid false positive after Yosys 0.49 - puts $outfile "gate-nomatch clone*\n\n" - - # Equivalence check recipe 1 - puts $outfile "\[strategy basic]\nuse sat\ndepth 10\n\n" - # Equivalence check recipe 2 - puts $outfile "\[strategy sby]\nuse sby\ndepth 10\nengine smtbmc bitwuzla\n\n" - - close $outfile + set top_cell [current_design] + set cell_files [get_verilog_cells_for_design] + set outfile [open "$::env(OBJECTS_DIR)/4_eqy_test.eqy" w] + # Gold netlist + puts $outfile "\[gold]\nread_verilog -sv $::env(RESULTS_DIR)/4_before_rsz.v $cell_files\n" + puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n" + # Modified netlist + puts $outfile "\[gate]\nread_verilog -sv $::env(RESULTS_DIR)/4_after_rsz.v $cell_files\n" + puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n" + + # Recommendation from eqy team on how to speed up a design + puts $outfile "\[match *]\ngate-nomatch _*_.*" + + # See issue OpenROAD#6545 "Equivalence check failure due to non-unique resizer nets" + puts $outfile "gate-nomatch net*" + + # Forbid matching on buffer instances or cloned instances to make it less + # likely EQY will fail to prove equivalence because of its assuming structural + # similarity between gold and gate netlists. This doesn't remove coverage. + puts $outfile "gate-nomatch clone*" + puts $outfile "gate-nomatch place*" + puts $outfile "gate-nomatch rebuffer*" + puts $outfile "gate-nomatch wire*" + puts $outfile "gate-nomatch place*\n\n" + + # Equivalence check recipe 1 + puts $outfile "\[strategy basic]\nuse sat\ndepth 10\n\n" + # Equivalence check recipe 2 + puts $outfile "\[strategy sby]\nuse sby\ndepth 10\nengine smtbmc bitwuzla\n\n" + + close $outfile } -proc run_equivalence_test {} { - write_eqy_verilog 4_after_rsz.v - write_eqy_script - - eval exec eqy -d $::env(LOG_DIR)/4_eqy_output \ - --force \ - --jobs $::env(NUM_CORES) \ - $::env(OBJECTS_DIR)/4_eqy_test.eqy \ - > $::env(LOG_DIR)/4_equivalence_check.log - set count [exec grep -c "Successfully proved designs equivalent" $::env(LOG_DIR)/4_equivalence_check.log] - if { $count == 0 } { - error "Repair timing output failed equivalence test" - } else { - puts "Repair timing output passed equivalence test" - } +proc run_equivalence_test { } { + write_eqy_verilog 4_after_rsz.v + write_eqy_script + + # tclint-disable-next-line command-args + eval exec eqy -d $::env(LOG_DIR)/4_eqy_output \ + --force \ + --jobs $::env(NUM_CORES) \ + $::env(OBJECTS_DIR)/4_eqy_test.eqy \ + > $::env(LOG_DIR)/4_equivalence_check.log + set count \ + [exec grep -c "Successfully proved designs equivalent" $::env(LOG_DIR)/4_equivalence_check.log] + if { $count == 0 } { + error "Repair timing output failed equivalence test" + } else { + puts "Repair timing output passed equivalence test" + } } diff --git a/flow/scripts/macro_place_util.tcl b/flow/scripts/macro_place_util.tcl index de8c5ff99b..8aa9963ad0 100644 --- a/flow/scripts/macro_place_util.tcl +++ b/flow/scripts/macro_place_util.tcl @@ -1,16 +1,16 @@ -if {[find_macros] != ""} { - if {![env_var_exists_and_non_empty RTLMP_RPT_DIR]} { +if { [find_macros] != "" } { + if { ![env_var_exists_and_non_empty RTLMP_RPT_DIR] } { set ::env(RTLMP_RPT_DIR) "$::env(OBJECTS_DIR)/rtlmp" } - if {![env_var_exists_and_non_empty RTLMP_RPT_FILE]} { + if { ![env_var_exists_and_non_empty RTLMP_RPT_FILE] } { set ::env(RTLMP_RPT_FILE) "partition.txt" } - if {![env_var_exists_and_non_empty RTLMP_BLOCKAGE_FILE]} { + if { ![env_var_exists_and_non_empty RTLMP_BLOCKAGE_FILE] } { set ::env(RTLMP_BLOCKAGE_FILE) "$::env(OBJECTS_DIR)/rtlmp/partition.txt.blockage" } # If wrappers defined replace macros with their wrapped version - if {[env_var_exists_and_non_empty MACRO_WRAPPERS]} { + if { [env_var_exists_and_non_empty MACRO_WRAPPERS] } { source $::env(MACRO_WRAPPERS) set wrapped_macros [dict keys [dict get $wrapper around]] @@ -18,7 +18,7 @@ if {[find_macros] != ""} { set block [ord::get_db_block] foreach inst [$block getInsts] { - if {[lsearch -exact $wrapped_macros [[$inst getMaster] getName]] > -1} { + if { [lsearch -exact $wrapped_macros [[$inst getMaster] getName]] > -1 } { set new_master [dict get $wrapper around [[$inst getMaster] getName]] puts "Replacing [[$inst getMaster] getName] with $new_master for [$inst getName]" $inst swapMaster [$db findMaster $new_master] @@ -30,13 +30,13 @@ if {[find_macros] != ""} { set halo_max [expr max($halo_x, $halo_y)] set blockage_width $halo_max - if {[env_var_exists_and_non_empty MACRO_BLOCKAGE_HALO]} { + if { [env_var_exists_and_non_empty MACRO_BLOCKAGE_HALO] } { set blockage_width $::env(MACRO_BLOCKAGE_HALO) } - if {[env_var_exists_and_non_empty MACRO_PLACEMENT_TCL]} { + if { [env_var_exists_and_non_empty MACRO_PLACEMENT_TCL] } { log_cmd source $::env(MACRO_PLACEMENT_TCL) - } elseif {[env_var_exists_and_non_empty MACRO_PLACEMENT]} { + } elseif { [env_var_exists_and_non_empty MACRO_PLACEMENT] } { source $::env(SCRIPTS_DIR)/read_macro_placement.tcl log_cmd read_macro_placement $::env(MACRO_PLACEMENT) } else { @@ -74,7 +74,7 @@ if {[find_macros] != ""} { } source $::env(SCRIPTS_DIR)/placement_blockages.tcl - block_channels $blockage_width + block_channels $blockage_width } else { puts "No macros found: Skipping macro_placement" } diff --git a/flow/scripts/noop.tcl b/flow/scripts/noop.tcl index e69de29bb2..8b13789179 100644 --- a/flow/scripts/noop.tcl +++ b/flow/scripts/noop.tcl @@ -0,0 +1 @@ + diff --git a/flow/scripts/open.tcl b/flow/scripts/open.tcl index e2c411cfe1..8a1dcc0da4 100644 --- a/flow/scripts/open.tcl +++ b/flow/scripts/open.tcl @@ -1,53 +1,53 @@ source $::env(SCRIPTS_DIR)/util.tcl -# Read liberty files + +source_env_var_if_exists PLATFORM_TCL + source $::env(SCRIPTS_DIR)/read_liberty.tcl -# Read def -if {[env_var_exists_and_non_empty DEF_FILE]} { - # Read lef - log_cmd read_lef $::env(TECH_LEF) - log_cmd read_lef $::env(SC_LEF) - if {[env_var_exists_and_non_empty ADDITIONAL_LEFS]} { - foreach lef $::env(ADDITIONAL_LEFS) { - log_cmd read_lef $lef - } +if { [env_var_exists_and_non_empty DEF_FILE] } { + log_cmd read_lef $::env(TECH_LEF) + log_cmd read_lef $::env(SC_LEF) + if { [env_var_exists_and_non_empty ADDITIONAL_LEFS] } { + foreach lef $::env(ADDITIONAL_LEFS) { + log_cmd read_lef $lef } - set input_file $::env(DEF_FILE) - log_cmd read_def $input_file + } + set input_file $::env(DEF_FILE) + log_cmd read_def $input_file } else { - set input_file $::env(ODB_FILE) - log_cmd read_db $input_file + set input_file $::env(ODB_FILE) + log_cmd read_db $input_file } -proc read_timing {input_file} { +proc read_timing { input_file } { set result [find_sdc_file $input_file] set design_stage [lindex $result 0] set sdc_file [lindex $result 1] - if {$sdc_file == ""} { + if { $sdc_file == "" } { set sdc_file $::env(SDC_FILE) } log_cmd read_sdc $sdc_file - if [file exists $::env(PLATFORM_DIR)/derate.tcl] { + if { [file exists $::env(PLATFORM_DIR)/derate.tcl] } { source $::env(PLATFORM_DIR)/derate.tcl } - + source $::env(PLATFORM_DIR)/setRC.tcl - if {$design_stage >= 4} { + if { $design_stage >= 4 } { # CTS has run, so propagate clocks set_propagated_clock [all_clocks] } - - if {$design_stage >= 6 && [file exist $::env(RESULTS_DIR)/6_final.spef]} { + + if { $design_stage >= 6 && [file exist $::env(RESULTS_DIR)/6_final.spef] } { log_cmd read_spef $::env(RESULTS_DIR)/6_final.spef - } elseif {$design_stage >= 5} { + } elseif { $design_stage >= 5 } { if { [log_cmd grt::have_routes] } { log_cmd estimate_parasitics -global_routing } else { puts "No global routing results available, skipping estimate_parasitics" puts "Load $::global_route_congestion_report for details" } - } elseif {$design_stage >= 3} { + } elseif { $design_stage >= 3 } { log_cmd estimate_parasitics -placement } @@ -55,18 +55,17 @@ proc read_timing {input_file} { set _tmp [log_cmd find_timing_paths] } -if {[ord::openroad_gui_compiled]} { +if { [ord::openroad_gui_compiled] } { set db_basename [file rootname [file tail $input_file]] - gui::set_title "OpenROAD - $::env(PLATFORM)/$::env(DESIGN_NICKNAME)/$::env(FLOW_VARIANT) - ${db_basename}" + gui::set_title \ + "OpenROAD - $::env(PLATFORM)/$::env(DESIGN_NICKNAME)/$::env(FLOW_VARIANT) - ${db_basename}" } -if {[env_var_equals GUI_TIMING 1]} { +if { [env_var_equals GUI_TIMING 1] } { puts "GUI_TIMING=1 reading timing, takes a little while for large designs..." read_timing $input_file - if {[gui::enabled]} { + if { [gui::enabled] } { log_cmd gui::select_chart "Endpoint Slack" log_cmd gui::update_timing_report } } - -fast_route diff --git a/flow/scripts/pdn.tcl b/flow/scripts/pdn.tcl index ea3941177b..72d2c55c14 100644 --- a/flow/scripts/pdn.tcl +++ b/flow/scripts/pdn.tcl @@ -5,19 +5,17 @@ load_design 2_3_floorplan_tapcell.odb 2_1_floorplan.sdc source $::env(PDN_TCL) pdngen -if { [env_var_exists_and_non_empty POST_PDN_TCL] } { - source $::env(POST_PDN_TCL) -} +source_env_var_if_exists POST_PDN_TCL # Check all supply nets set block [ord::get_db_block] foreach net [$block getNets] { - set type [$net getSigType] - if {$type == "POWER" || $type == "GROUND"} { -# Temporarily disable due to CI issues -# puts "Check supply: [$net getName]" -# check_power_grid -net [$net getName] - } + set type [$net getSigType] + if { $type == "POWER" || $type == "GROUND" } { + # Temporarily disable due to CI issues + # puts "Check supply: [$net getName]" + # check_power_grid -net [$net getName] + } } write_db $::env(RESULTS_DIR)/2_4_floorplan_pdn.odb diff --git a/flow/scripts/placement_blockages.tcl b/flow/scripts/placement_blockages.tcl index 876a01f903..82c306474b 100644 --- a/flow/scripts/placement_blockages.tcl +++ b/flow/scripts/placement_blockages.tcl @@ -1,4 +1,4 @@ -proc block_channels {channel_width_in_microns} { +proc block_channels { channel_width_in_microns } { set tech [ord::get_db_tech] set units [$tech getDbUnitsPerMicron] set block [ord::get_db_block] @@ -8,7 +8,7 @@ proc block_channels {channel_width_in_microns} { # set shapes {} foreach inst [$block getInsts] { - if {[[$inst getMaster] getType] == "BLOCK"} { + if { [[$inst getMaster] getType] == "BLOCK" } { set box [$inst getBBox] lappend shapes [odb::newSetFromRect [$box xMin] [$box yMin] [$box xMax] [$box yMax]] } @@ -37,9 +37,8 @@ proc block_channels {channel_width_in_microns} { # set rects [odb::getRectangles $shapeSet] foreach rect $rects { - set b [odb::dbBlockage_create $block \ - [$rect xMin] [$rect yMin] [$rect xMax] [$rect yMax]] - $b setSoft + set b [odb::dbBlockage_create $block \ + [$rect xMin] [$rect yMin] [$rect xMax] [$rect yMax]] + $b setSoft } } - diff --git a/flow/scripts/read_liberty.tcl b/flow/scripts/read_liberty.tcl index 68f36e84a5..14f8f06e7a 100644 --- a/flow/scripts/read_liberty.tcl +++ b/flow/scripts/read_liberty.tcl @@ -1,18 +1,11 @@ -# To remove [WARNING STA-1212] from the logs for ASAP7. -# /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz line 13178, timing group from output port. -# Added following suppress_message -if {[env_var_equals PLATFORM asap7]} { - suppress_message STA 1212 -} - #Read Liberty -if {[env_var_exists_and_non_empty CORNERS]} { +if { [env_var_exists_and_non_empty CORNERS] } { # corners define_corners {*}$::env(CORNERS) foreach corner $::env(CORNERS) { set LIBKEY "[string toupper $corner]_LIB_FILES" foreach libFile $::env($LIBKEY) { - read_liberty -corner $corner $libFile + log_cmd read_liberty -corner $corner $libFile } unset LIBKEY } @@ -20,10 +13,6 @@ if {[env_var_exists_and_non_empty CORNERS]} { } else { ## no corner foreach libFile $::env(LIB_FILES) { - read_liberty $libFile + log_cmd read_liberty $libFile } } - -if {[env_var_equals PLATFORM asap7]} { - unsuppress_message STA 1212 -} diff --git a/flow/scripts/read_macro_placement.tcl b/flow/scripts/read_macro_placement.tcl index 68c08231a4..bc643c7734 100644 --- a/flow/scripts/read_macro_placement.tcl +++ b/flow/scripts/read_macro_placement.tcl @@ -1,19 +1,19 @@ -proc read_macro_placement {macro_placement_file} { +proc read_macro_placement { macro_placement_file } { set block [ord::get_db_block] set units [$block getDefUnits] set ch [open $macro_placement_file] - while {![eof $ch]} { + while { ![eof $ch] } { set line [gets $ch] - if {[llength $line] == 0} {continue} + if { [llength $line] == 0 } { continue } set inst_name [lindex $line 0] set orientation [lindex $line 1] set x [expr round([lindex $line 2] * $units)] set y [expr round([lindex $line 3] * $units)] - if {[set inst [$block findInst $inst_name]] == "NULL"} { + if { [set inst [$block findInst $inst_name]] == "NULL" } { error "Cannot find instance $inst_name" } diff --git a/flow/scripts/report_metrics.tcl b/flow/scripts/report_metrics.tcl index 340de7e629..b03cef6d63 100644 --- a/flow/scripts/report_metrics.tcl +++ b/flow/scripts/report_metrics.tcl @@ -1,13 +1,13 @@ proc report_puts { out } { - upvar 1 when when - upvar 1 filename filename - set fileId [open $filename a] - puts $fileId $out - close $fileId + upvar 1 when when + upvar 1 filename filename + set fileId [open $filename a] + puts $fileId $out + close $fileId } -proc report_metrics { stage when {include_erc true} {include_clock_skew true} } { - if {[env_var_equals SKIP_REPORT_METRICS 1]} { +proc report_metrics { stage when { include_erc true } { include_clock_skew true } } { + if { [env_var_equals SKIP_REPORT_METRICS 1] } { return } puts "Report metrics stage $stage, $when..." @@ -33,7 +33,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_worst_slack_metric >> $filename report_worst_slack_metric -hold >> $filename - if {$include_clock_skew && $::env(REPORT_CLOCK_SKEW)} { + if { $include_clock_skew && $::env(REPORT_CLOCK_SKEW) } { report_puts "\n==========================================================================" report_puts "$when report_clock_skew" report_puts "--------------------------------------------------------------------------" @@ -45,19 +45,22 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "\n==========================================================================" report_puts "$when report_checks -path_delay min" report_puts "--------------------------------------------------------------------------" - report_checks -path_delay min -fields {slew cap input net fanout} -format full_clock_expanded >> $filename + report_checks -path_delay min -fields {slew cap input net fanout} \ + -format full_clock_expanded >> $filename report_puts "\n==========================================================================" report_puts "$when report_checks -path_delay max" report_puts "--------------------------------------------------------------------------" - report_checks -path_delay max -fields {slew cap input net fanout} -format full_clock_expanded >> $filename + report_checks -path_delay max -fields {slew cap input net fanout} \ + -format full_clock_expanded >> $filename report_puts "\n==========================================================================" report_puts "$when report_checks -unconstrained" report_puts "--------------------------------------------------------------------------" - report_checks -unconstrained -fields {slew cap input net fanout} -format full_clock_expanded >> $filename + report_checks -unconstrained -fields {slew cap input net fanout} \ + -format full_clock_expanded >> $filename - if {$include_erc} { + if { $include_erc } { report_puts "\n==========================================================================" report_puts "$when report_check_types -max_slew -max_cap -max_fanout -violators" report_puts "--------------------------------------------------------------------------" @@ -75,7 +78,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "--------------------------------------------------------------------------" report_puts "[sta::max_slew_check_limit]" - if {[sta::max_slew_check_limit] < 1e30} { + if { [sta::max_slew_check_limit] < 1e30 } { report_puts "\n==========================================================================" report_puts "$when max_slew_check_slack_limit" report_puts "--------------------------------------------------------------------------" @@ -92,7 +95,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "--------------------------------------------------------------------------" report_puts "[sta::max_fanout_check_limit]" - if {[sta::max_fanout_check_limit] < 1e30} { + if { [sta::max_fanout_check_limit] < 1e30 } { report_puts "\n==========================================================================" report_puts "$when max_fanout_check_slack_limit" report_puts "--------------------------------------------------------------------------" @@ -109,7 +112,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "--------------------------------------------------------------------------" report_puts "[sta::max_capacitance_check_limit]" - if {[sta::max_capacitance_check_limit] < 1e30} { + if { [sta::max_capacitance_check_limit] < 1e30 } { report_puts "\n==========================================================================" report_puts "$when max_capacitance_check_slack_limit" report_puts "--------------------------------------------------------------------------" @@ -142,7 +145,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "hold violation count [sta::endpoint_violation_count min]" set critical_path [lindex [find_timing_paths -sort_by_slack] 0] - if {$critical_path != ""} { + if { $critical_path != "" } { set path_delay [sta::format_time [[$critical_path path] arrival] 4] set path_slack [sta::format_time [[$critical_path path] slack] 4] } else { @@ -150,52 +153,58 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } set path_slack 0 } - if { [llength [all_registers]] != 0} { - report_puts "\n==========================================================================" - report_puts "$when report_checks -path_delay max reg to reg" - report_puts "--------------------------------------------------------------------------" - report_checks -path_delay max -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename - report_puts "\n==========================================================================" - report_puts "$when report_checks -path_delay min reg to reg" - report_puts "--------------------------------------------------------------------------" - report_checks -path_delay min -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename - - set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay max -from [all_inputs] -to [all_registers]] 0] - if {$inp_to_reg_critical_path != ""} { - set target_clock_latency_max [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4] - } else { - set target_clock_latency_max 0 - } - + if { [llength [all_registers]] != 0 } { + report_puts "\n==========================================================================" + report_puts "$when report_checks -path_delay max reg to reg" + report_puts "--------------------------------------------------------------------------" + report_checks -path_delay max -from [all_registers] -to [all_registers] \ + -format full_clock_expanded >> $filename + report_puts "\n==========================================================================" + report_puts "$when report_checks -path_delay min reg to reg" + report_puts "--------------------------------------------------------------------------" + report_checks -path_delay min -from [all_registers] -to [all_registers] \ + -format full_clock_expanded >> $filename + + set inp_to_reg_critical_path \ + [lindex [find_timing_paths -path_delay max -from [all_inputs] -to [all_registers]] 0] + if { $inp_to_reg_critical_path != "" } { + set target_clock_latency_max \ + [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4] + } else { + set target_clock_latency_max 0 + } + + + set inp_to_reg_critical_path [lindex \ + [find_timing_paths -path_delay min -from [all_inputs] -to [all_registers]] 0] + if { $inp_to_reg_critical_path != "" } { + set target_clock_latency_min \ + [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4] + set source_clock_latency [sta::format_time [$inp_to_reg_critical_path source_clk_latency] 4] + } else { + set target_clock_latency_min 0 + set source_clock_latency 0 + } - set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay min -from [all_inputs] -to [all_registers]] 0] - if {$inp_to_reg_critical_path != ""} { - set target_clock_latency_min [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4] - set source_clock_latency [sta::format_time [$inp_to_reg_critical_path source_clk_latency] 4] - } else { - set target_clock_latency_min 0 - set source_clock_latency 0 - } - - report_puts "\n==========================================================================" - report_puts "$when critical path target clock latency max path" - report_puts "--------------------------------------------------------------------------" - report_puts "$target_clock_latency_max" + report_puts "\n==========================================================================" + report_puts "$when critical path target clock latency max path" + report_puts "--------------------------------------------------------------------------" + report_puts "$target_clock_latency_max" - report_puts "\n==========================================================================" - report_puts "$when critical path target clock latency min path" - report_puts "--------------------------------------------------------------------------" - report_puts "$target_clock_latency_min" + report_puts "\n==========================================================================" + report_puts "$when critical path target clock latency min path" + report_puts "--------------------------------------------------------------------------" + report_puts "$target_clock_latency_min" - report_puts "\n==========================================================================" - report_puts "$when critical path source clock latency min path" - report_puts "--------------------------------------------------------------------------" - report_puts "$source_clock_latency" + report_puts "\n==========================================================================" + report_puts "$when critical path source clock latency min path" + report_puts "--------------------------------------------------------------------------" + report_puts "$source_clock_latency" } else { - puts "No registers in design" + puts "No registers in design" } # end if all_registers - + report_puts "\n==========================================================================" report_puts "$when critical path delay" report_puts "--------------------------------------------------------------------------" @@ -215,7 +224,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "\n==========================================================================" report_puts "$when report_power" report_puts "--------------------------------------------------------------------------" - if {[env_var_exists_and_non_empty CORNERS]} { + if { [env_var_exists_and_non_empty CORNERS] } { foreach corner $::env(CORNERS) { report_puts "Corner: $corner" report_power -corner $corner >> $filename diff --git a/flow/scripts/resize.tcl b/flow/scripts/resize.tcl index cb38355043..50276a85ec 100644 --- a/flow/scripts/resize.tcl +++ b/flow/scripts/resize.tcl @@ -10,38 +10,15 @@ set pin_count_before [sta::network_leaf_pin_count] set_dont_use $::env(DONT_USE_CELLS) -# Do not buffer chip-level designs -# by default, IO ports will be buffered -# to not buffer IO ports, set environment variable -# DONT_BUFFER_PORT = 1 -if { ![env_var_exists_and_non_empty FOOTPRINT] } { - if { ![env_var_equals DONT_BUFFER_PORTS 1] } { - puts "Perform port buffering..." - buffer_ports - } +if { [env_var_exists_and_non_empty EARLY_SIZING_CAP_RATIO] } { + log_cmd set_opt_config -set_early_sizing_cap_ratio $env(EARLY_SIZING_CAP_RATIO) } -repair_design_helper - -if { [env_var_exists_and_non_empty TIE_SEPARATION] } { - set tie_separation $env(TIE_SEPARATION) -} else { - set tie_separation 0 +if { [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] } { + replace_arith_modules } -# Repair tie lo fanout -puts "Repair tie lo fanout..." -set tielo_cell_name [lindex $env(TIELO_CELL_AND_PORT) 0] -set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]] -set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $env(TIELO_CELL_AND_PORT) 1] -repair_tie_fanout -separation $tie_separation $tielo_pin - -# Repair tie hi fanout -puts "Repair tie hi fanout..." -set tiehi_cell_name [lindex $env(TIEHI_CELL_AND_PORT) 0] -set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]] -set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $env(TIEHI_CELL_AND_PORT) 1] -repair_tie_fanout -separation $tie_separation $tiehi_pin +repair_design_helper # hold violations are not repaired until after CTS diff --git a/flow/scripts/save_images.tcl b/flow/scripts/save_images.tcl index a6d3ca96a3..5dec935009 100644 --- a/flow/scripts/save_images.tcl +++ b/flow/scripts/save_images.tcl @@ -7,7 +7,7 @@ set height [ord::dbu_to_microns $height] set resolution [expr $height / 1000] set markerdb [[ord::get_db_block] findMarkerCategory DRC] -if {$markerdb != "NULL" && [$markerdb getMarkerCount] > 0} { +if { $markerdb != "NULL" && [$markerdb getMarkerCount] > 0 } { gui::select_marker_category $markerdb } @@ -22,8 +22,9 @@ gui::set_display_controls "Layers/*" visible true gui::set_display_controls "Nets/*" visible true gui::set_display_controls "Instances/*" visible true gui::set_display_controls "Shape Types/*" visible true -gui::set_display_controls "Misc/Instances/*" visible true -gui::set_display_controls "Misc/Instances/Pin Names" visible false +gui::set_display_controls "Misc/Instances/*" visible false +gui::set_display_controls "Misc/Instances/Pins" visible true +gui::set_display_controls "Misc/Instances/Blockages" visible true gui::set_display_controls "Misc/Scale bar" visible true gui::set_display_controls "Misc/Highlight selected" visible true gui::set_display_controls "Misc/Detailed view" visible true @@ -35,11 +36,12 @@ gui::set_display_controls "Nets/Ground" visible false save_image -resolution $resolution $::env(REPORTS_DIR)/final_routing.webp # The placement view without routing -gui::set_display_controls "Layers/*" visible false +gui::set_display_controls "Shape Types/Routing/*" visible false gui::set_display_controls "Instances/Physical/*" visible false +gui::set_display_controls "Misc/Instances/*" visible false save_image -resolution $resolution $::env(REPORTS_DIR)/final_placement.webp -if {[env_var_exists_and_non_empty PWR_NETS_VOLTAGES]} { +if { [env_var_exists_and_non_empty PWR_NETS_VOLTAGES] } { gui::set_display_controls "Heat Maps/IR Drop" visible true gui::set_heatmap IRDrop Layer $::env(IR_DROP_LAYER) gui::set_heatmap IRDrop ShowLegend 1 @@ -48,48 +50,60 @@ if {[env_var_exists_and_non_empty PWR_NETS_VOLTAGES]} { } # The clock view: all clock nets and buffers -gui::set_display_controls "Layers/*" visible true +gui::set_display_controls "Shape Types/Routing/*" visible true gui::set_display_controls "Nets/*" visible false gui::set_display_controls "Nets/Clock" visible true gui::set_display_controls "Instances/*" visible false gui::set_display_controls "Instances/StdCells/Clock tree/*" visible true gui::set_display_controls "Instances/StdCells/Sequential" visible true gui::set_display_controls "Instances/Macro" visible true -gui::set_display_controls "Misc/Instances/*" visible false select -name "clk*" -type Inst save_image -resolution $resolution $::env(REPORTS_DIR)/final_clocks.webp gui::clear_selections +gui::show_widget "Clock Tree Viewer" foreach clock [get_clocks *] { if { [llength [get_property $clock sources]] > 0 } { set clock_name [get_name $clock] save_clocktree_image -clock $clock_name \ - -width 1024 -height 1024 \ - $::env(REPORTS_DIR)/cts_$clock_name.webp + -width 1024 -height 1024 \ + $::env(REPORTS_DIR)/cts_$clock_name.webp gui::select_clockviewer_clock $clock_name save_image -resolution $resolution $::env(REPORTS_DIR)/cts_${clock_name}_layout.webp } } +gui::hide_widget "Clock Tree Viewer" # The resizer view: all instances created by the resizer grouped -gui::set_display_controls "Layers/*" visible false +gui::set_display_controls "Nets/*" visible true +gui::set_display_controls "Nets/Power" visible false +gui::set_display_controls "Nets/Ground" visible false +gui::set_display_controls "Shape Types/Routing/*" visible false gui::set_display_controls "Instances/*" visible true gui::set_display_controls "Instances/Physical/*" visible false -select -name "hold*" -type Inst -highlight 0 ;# green -select -name "input*" -type Inst -highlight 1 ;# yellow +select -name "hold*" -type Inst -highlight 0 ;# green +select -name "input*" -type Inst -highlight 1 ;# yellow select -name "output*" -type Inst -highlight 1 -select -name "repeater*" -type Inst -highlight 3 ;# magenta +select -name "repeater*" -type Inst -highlight 3 ;# magenta select -name "fanout*" -type Inst -highlight 3 select -name "load_slew*" -type Inst -highlight 3 select -name "max_cap*" -type Inst -highlight 3 select -name "max_length*" -type Inst -highlight 3 select -name "wire*" -type Inst -highlight 3 -select -name "rebuffer*" -type Inst -highlight 4 ;# red -select -name "split*" -type Inst -highlight 5 ;# dark green +select -name "rebuffer*" -type Inst -highlight 4 ;# red +select -name "split*" -type Inst -highlight 5 ;# dark green save_image -resolution $resolution $::env(REPORTS_DIR)/final_resizer.webp gui::clear_highlights -1 gui::clear_selections +# The routing congestion view +gui::set_display_controls "Instances/*" visible true +gui::set_display_controls "Instances/Physical/*" visible false +gui::set_display_controls "Nets/*" visible false +gui::set_display_controls "Heat Maps/Routing Congestion" visible true + +save_image -resolution $resolution $::env(REPORTS_DIR)/final_congestion.webp + gui::restore_display_controls diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl index e800802bed..eb31ed9355 100644 --- a/flow/scripts/synth.tcl +++ b/flow/scripts/synth.tcl @@ -1,6 +1,5 @@ -set ::env(VERILOG_FILES) $::env(RESULTS_DIR)/1_synth.rtlil - source $::env(SCRIPTS_DIR)/synth_preamble.tcl +read_checkpoint $::env(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil hierarchy -check -top $::env(DESIGN_NAME) @@ -10,7 +9,7 @@ if { [env_var_equals SYNTH_GUT 1] } { delete $::env(DESIGN_NAME)/c:* } -if {[env_var_exists_and_non_empty SYNTH_KEEP_MODULES]} { +if { [env_var_exists_and_non_empty SYNTH_KEEP_MODULES] } { foreach module $::env(SYNTH_KEEP_MODULES) { select -module $module setattr -mod -set keep_hierarchy 1 @@ -18,23 +17,27 @@ if {[env_var_exists_and_non_empty SYNTH_KEEP_MODULES]} { } } -set synth_full_args $::env(SYNTH_ARGS) -if {[env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS]} { +if { [env_var_exists_and_non_empty SYNTH_HIER_SEPARATOR] } { + scratchpad -set flatten.separator $::env(SYNTH_HIER_SEPARATOR) +} + +set synth_full_args [env_var_or_empty SYNTH_ARGS] +if { [env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS] } { set synth_full_args [concat $synth_full_args $::env(SYNTH_OPERATIONS_ARGS)] } else { - set synth_full_args [concat $synth_full_args "-extra-map $::env(FLOW_HOME)/platforms/common/lcu_kogge_stone.v"] + set synth_full_args [concat $synth_full_args \ + "-extra-map $::env(FLOW_HOME)/platforms/common/lcu_kogge_stone.v"] } -if {![env_var_equals SYNTH_HIERARCHICAL 1]} { +if { ![env_var_equals SYNTH_HIERARCHICAL 1] } { # Perform standard coarse-level synthesis script, flatten right away - # (-flatten part of $synth_args per default) - synth -run :fine {*}$synth_full_args + synth -flatten -run :fine {*}$synth_full_args } else { # Perform standard coarse-level synthesis script, # defer flattening until we have decided what hierarchy to keep synth -run :fine - if {[env_var_exists_and_non_empty SYNTH_MINIMUM_KEEP_SIZE]} { + if { [env_var_exists_and_non_empty SYNTH_MINIMUM_KEEP_SIZE] } { set ungroup_threshold $::env(SYNTH_MINIMUM_KEEP_SIZE) puts "Keep modules above estimated size of $ungroup_threshold gate equivalents" @@ -45,17 +48,21 @@ if {![env_var_equals SYNTH_HIERARCHICAL 1]} { } # Re-run coarse-level script, this time do pass -flatten - synth -run coarse:fine {*}$synth_full_args + synth -flatten -run coarse:fine {*}$synth_full_args } json -o $::env(RESULTS_DIR)/mem.json # Run report and check here so as to fail early if this synthesis run is doomed -exec -- python3 $::env(SCRIPTS_DIR)/mem_dump.py --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json +exec -- $::env(PYTHON_EXE) $::env(SCRIPTS_DIR)/mem_dump.py \ + --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json -if {![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS]} { - synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_full_args -} else { +if { + [env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] || + [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] +} { source $::env(SCRIPTS_DIR)/synth_wrap_operators.tcl +} else { + synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_full_args } # Get rid of indigestibles @@ -71,7 +78,7 @@ renames -wire opt -purge # Technology mapping of adders -if {[env_var_exists_and_non_empty ADDER_MAP_FILE]} { +if { [env_var_exists_and_non_empty ADDER_MAP_FILE] } { # extract the full adders extract_fa # map full adders @@ -82,7 +89,7 @@ if {[env_var_exists_and_non_empty ADDER_MAP_FILE]} { } # Technology mapping of latches -if {[env_var_exists_and_non_empty LATCH_MAP_FILE]} { +if { [env_var_exists_and_non_empty LATCH_MAP_FILE] } { techmap -map $::env(LATCH_MAP_FILE) } @@ -93,14 +100,14 @@ foreach cell $::env(DONT_USE_CELLS) { # Technology mapping of flip-flops # dfflibmap only supports one liberty file -if {[env_var_exists_and_non_empty DFF_LIB_FILE]} { +if { [env_var_exists_and_non_empty DFF_LIB_FILE] } { dfflibmap -liberty $::env(DFF_LIB_FILE) {*}$dfflibmap_args } else { dfflibmap -liberty $::env(DONT_USE_SC_LIB) {*}$dfflibmap_args } opt -if {![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS]} { +if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } { log_cmd abc {*}$abc_args } else { scratchpad -set abc9.script scripts/abc_speed_gia_only.script @@ -121,8 +128,8 @@ opt_clean -purge # Technology mapping of constant hi- and/or lo-drivers hilomap -singleton \ - -hicell {*}$::env(TIEHI_CELL_AND_PORT) \ - -locell {*}$::env(TIELO_CELL_AND_PORT) + -hicell {*}$::env(TIEHI_CELL_AND_PORT) \ + -locell {*}$::env(TIELO_CELL_AND_PORT) # Insert buffer cells for pass through wires insbuf -buf {*}$::env(MIN_BUF_CELL_AND_PORTS) @@ -133,7 +140,7 @@ tee -o $::env(REPORTS_DIR)/synth_check.txt check tee -o $::env(REPORTS_DIR)/synth_stat.txt stat {*}$stat_libs # check the design is composed exclusively of target cells, and check for other problems -if {![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS]} { +if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } { check -assert -mapped } else { # Wrapped operator synthesis leaves around $buf cells which `check -mapped` @@ -143,7 +150,7 @@ if {![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS]} { } # Write synthesized design -write_verilog -nohex -nodec $::env(RESULTS_DIR)/1_1_yosys.v +write_verilog -nohex -nodec $::env(RESULTS_DIR)/1_2_yosys.v # One day a more sophisticated synthesis will write out a modified # .sdc file after synthesis. For now, just copy the input .sdc file, # making synthesis more consistent with other stages. diff --git a/flow/scripts/synth_canonicalize.tcl b/flow/scripts/synth_canonicalize.tcl index ad16ddf210..f7d4c44657 100644 --- a/flow/scripts/synth_canonicalize.tcl +++ b/flow/scripts/synth_canonicalize.tcl @@ -1,12 +1,16 @@ source $::env(SCRIPTS_DIR)/synth_preamble.tcl +read_design_sources -dict for {key value} $::env(VERILOG_TOP_PARAMS) { +dict for {key value} [env_var_or_empty VERILOG_TOP_PARAMS] { # Apply toplevel parameters chparam -set $key $value $::env(DESIGN_NAME) } hierarchy -check -top $::env(DESIGN_NAME) + +source_env_var_if_exists SYNTH_CANONICALIZE_TCL + # Get rid of unused modules opt_clean -purge # The hash of this file will not change if files not part of synthesis do not change -write_rtlil $::env(RESULTS_DIR)/1_synth.rtlil +write_rtlil $::env(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil diff --git a/flow/scripts/synth_metrics.tcl b/flow/scripts/synth_metrics.tcl index f24a05e80e..d2fe0ab500 100644 --- a/flow/scripts/synth_metrics.tcl +++ b/flow/scripts/synth_metrics.tcl @@ -1,5 +1,5 @@ utl::set_metrics_stage "synth__{}" source $::env(SCRIPTS_DIR)/load.tcl -load_design 1_1_yosys.v 1_synth.sdc +load_design 1_2_yosys.v 1_synth.sdc report_metrics 1 "Post synthesis" false false diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl index d97f96638b..21cf176be5 100644 --- a/flow/scripts/synth_preamble.tcl +++ b/flow/scripts/synth_preamble.tcl @@ -6,57 +6,87 @@ erase_non_stage_variables synth # If using a cached, gate level netlist, then copy over to the results dir with # preserve timestamps flag set. If you don't, subsequent runs will cause the # floorplan step to be re-executed. -if {[env_var_exists_and_non_empty SYNTH_NETLIST_FILES]} { - if {[llength $::env(SYNTH_NETLIST_FILES)] == 1} { - log_cmd exec cp -p $::env(SYNTH_NETLIST_FILES) $::env(RESULTS_DIR)/1_1_yosys.v +if { [env_var_exists_and_non_empty SYNTH_NETLIST_FILES] } { + if { [llength $::env(SYNTH_NETLIST_FILES)] == 1 } { + log_cmd exec cp -p $::env(SYNTH_NETLIST_FILES) $::env(RESULTS_DIR)/1_2_yosys.v } else { # The date should be the most recent date of the files, but to # keep things simple we just use the creation date - log_cmd exec cat {*}$::env(SYNTH_NETLIST_FILES) > $::env(RESULTS_DIR)/1_1_yosys.v + log_cmd exec cat {*}$::env(SYNTH_NETLIST_FILES) > $::env(RESULTS_DIR)/1_2_yosys.v } log_cmd exec cp -p $::env(SDC_FILE) $::env(RESULTS_DIR)/1_synth.sdc - if {[env_var_exists_and_non_empty CACHED_REPORTS]} { + if { [env_var_exists_and_non_empty CACHED_REPORTS] } { log_cmd exec cp -p {*}$::env(CACHED_REPORTS) $::env(REPORTS_DIR)/. } exit } -# Setup verilog include directories -set vIdirsArgs "" -if {[env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS]} { - foreach dir $::env(VERILOG_INCLUDE_DIRS) { - lappend vIdirsArgs "-I$dir" +proc read_checkpoint { file } { + # We are reading a Yosys checkpoint + if { [file extension $file] == ".json" } { + read_json $file + } else { + read_rtlil $file } - set vIdirsArgs [join $vIdirsArgs] } +proc read_design_sources { } { + # We are reading Verilog sources + source $::env(SCRIPTS_DIR)/synth_stdcells.tcl -# Read verilog files -foreach file $::env(VERILOG_FILES) { - if {[file extension $file] == ".rtlil"} { - read_rtlil $file - } elseif {[file extension $file] == ".json"} { - read_json $file - } else { - read_verilog -defer -sv {*}$vIdirsArgs $file + # Setup verilog include directories + set vIdirsArgs "" + if { [env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS] } { + foreach dir $::env(VERILOG_INCLUDE_DIRS) { + lappend vIdirsArgs "-I$dir" + } + set vIdirsArgs [join $vIdirsArgs] } -} -source $::env(SCRIPTS_DIR)/synth_stdcells.tcl + if { [env_var_equals SYNTH_HDL_FRONTEND slang] } { + # slang requires all files at once + plugin -i slang + yosys read_slang -D SYNTHESIS --keep-hierarchy --compat=vcs \ + --ignore-assertions --top $::env(DESIGN_NAME) \ + {*}$vIdirsArgs {*}$::env(VERILOG_FILES) {*}[env_var_or_empty VERILOG_DEFINES] + # Workaround for yosys-slang#119 + setattr -unset init + } elseif { [env_var_equals SYNTH_HDL_FRONTEND verific] } { + if { [env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS] } { + verific -vlog-incdir {*}$::env(VERILOG_INCLUDE_DIRS) + } + if { [env_var_exists_and_non_empty VERILOG_DEFINES] } { + verific -vlog-define {*}$::env(VERILOG_DEFINES) + } + verific -sv2012 {*}$::env(VERILOG_FILES) + verific -import -no-split-complex-ports $::env(DESIGN_NAME) + } elseif { ![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND] } { + verilog_defaults -push + if { [env_var_exists_and_non_empty VERILOG_DEFINES] } { + verilog_defaults -add {*}$::env(VERILOG_DEFINES) + } + foreach file $::env(VERILOG_FILES) { + read_verilog -defer -sv {*}$vIdirsArgs $file + } + verilog_defaults -pop + } else { + error "Unrecognized HDL frontend: $::env(SYNTH_HDL_FRONTEND)" + } -# Read platform specific mapfile for OPENROAD_CLKGATE cells -if {[env_var_exists_and_non_empty CLKGATE_MAP_FILE]} { - read_verilog -defer $::env(CLKGATE_MAP_FILE) -} + # Read platform specific mapfile for OPENROAD_CLKGATE cells + if { [env_var_exists_and_non_empty CLKGATE_MAP_FILE] } { + read_verilog -defer $::env(CLKGATE_MAP_FILE) + } -if {[env_var_exists_and_non_empty SYNTH_BLACKBOXES]} { - hierarchy -check -top $::env(DESIGN_NAME) - foreach m $::env(SYNTH_BLACKBOXES) { - blackbox $m + if { [env_var_exists_and_non_empty SYNTH_BLACKBOXES] } { + hierarchy -check -top $::env(DESIGN_NAME) + foreach m $::env(SYNTH_BLACKBOXES) { + blackbox $m + } } } -if {$::env(ABC_AREA)} { +if { $::env(ABC_AREA) } { puts "Using ABC area script." set abc_script $::env(SCRIPTS_DIR)/abc_area.script } else { @@ -67,22 +97,22 @@ if {$::env(ABC_AREA)} { # Technology mapping for cells # ABC supports multiple liberty files, but the hook from Yosys to ABC doesn't set abc_args [list -script $abc_script \ - -liberty $::env(DONT_USE_SC_LIB) \ - -constr $::env(OBJECTS_DIR)/abc.constr] + -liberty $::env(DONT_USE_SC_LIB) \ + -constr $::env(OBJECTS_DIR)/abc.constr] # Exclude dont_use cells. This includes macros that are specified via # LIB_FILES and ADDITIONAL_LIBS that are included in LIB_FILES. -if {[env_var_exists_and_non_empty DONT_USE_CELLS]} { +if { [env_var_exists_and_non_empty DONT_USE_CELLS] } { foreach cell $::env(DONT_USE_CELLS) { lappend abc_args -dont_use $cell } } -if {[env_var_exists_and_non_empty SDC_FILE_CLOCK_PERIOD]} { +if { [env_var_exists_and_non_empty SDC_FILE_CLOCK_PERIOD] } { puts "Extracting clock period from SDC file: $::env(SDC_FILE_CLOCK_PERIOD)" set fp [open $::env(SDC_FILE_CLOCK_PERIOD) r] set clock_period [string trim [read $fp]] - if {$clock_period != ""} { + if { $clock_period != "" } { puts "Setting clock period to $clock_period" lappend abc_args -D $clock_period } @@ -100,24 +130,24 @@ puts $constr "set_driving_cell $::env(ABC_DRIVER_CELL)" puts $constr "set_load $::env(ABC_LOAD_IN_FF)" close $constr -proc convert_liberty_areas {} { +proc convert_liberty_areas { } { cellmatch -derive_luts =A:liberty_cell # find a reference nand2 gate set found_cell "" set found_cell_area "" # iterate over all cells with a nand2 signature foreach cell [tee -q -s result.string select -list-mod =*/a:lut=4'b0111 %m] { - if {! [rtlil::has_attr -mod $cell area]} { + if { ![rtlil::has_attr -mod $cell area] } { puts "Cell $cell missing area information" continue } set area [rtlil::get_attr -string -mod $cell area] - if {$found_cell == "" || [expr $area < $found_cell_area]} { + if { $found_cell == "" || $area < $found_cell_area } { set found_cell $cell set found_cell_area $area } } - if {$found_cell == ""} { + if { $found_cell == "" } { error "reference nand2 cell not found" } diff --git a/flow/scripts/synth_wrap_operators.tcl b/flow/scripts/synth_wrap_operators.tcl index c9b9ded629..a47dc60452 100644 --- a/flow/scripts/synth_wrap_operators.tcl +++ b/flow/scripts/synth_wrap_operators.tcl @@ -10,12 +10,12 @@ set deferred_cells { { \$macc MACC_{CONFIG}_{Y_WIDTH}{%unused} - {BASE -map +/choices/han-carlson.v} {BOOTH -max_iter 1 -map ../flow/scripts/synth_wrap_operators-booth.v} + {BASE -map +/choices/han-carlson.v} } } -techmap {*}[join [lmap cell $deferred_cells {string cat "-dont_map [lindex $cell 0]"}] " "] +techmap {*}[join [lmap cell $deferred_cells { string cat "-dont_map [lindex $cell 0]" }] " "] foreach info $deferred_cells { set type [lindex $info 0] @@ -37,7 +37,7 @@ foreach info $deferred_cells { t:$type r:A_WIDTH>=10 r:Y_WIDTH>=14 %i %i # make per-architecture copies of the unmapped module - foreach modname [tee -q -s result.string select -list-mod A:arithmetic_operator A:copy_pending %i] { + foreach modname [tee -q -s result.string select -list-mod A:arithmetic_operator A:copy_pending %i] { # tclint-disable-line line-length setattr -mod -unset copy_pending $modname # iterate over non-default architectures @@ -53,7 +53,7 @@ foreach info $deferred_cells { # iterate over all architectures, both the default and non-default foreach arch [lrange $info 2 end] { set suffix [lindex $arch 0] - set extra_map_args [lrange $arch 1 end] + set extra_map_args [lrange $arch 1 end] # map all operator copies which were selected to have this architecture techmap -map +/techmap.v {*}$extra_map_args A:source_cell=$type A:architecture=$suffix %i diff --git a/flow/scripts/tapcell.tcl b/flow/scripts/tapcell.tcl index 16c007c079..eb00d11e23 100644 --- a/flow/scripts/tapcell.tcl +++ b/flow/scripts/tapcell.tcl @@ -3,10 +3,10 @@ erase_non_stage_variables floorplan load_design 2_2_floorplan_macro.odb 2_1_floorplan.sdc -if {[env_var_exists_and_non_empty TAPCELL_TCL]} { - source $::env(TAPCELL_TCL) +if { [env_var_exists_and_non_empty TAPCELL_TCL] } { + source $::env(TAPCELL_TCL) } else { - cut_rows + cut_rows } write_db $::env(RESULTS_DIR)/2_3_floorplan_tapcell.odb diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl index 9f6c38fd4d..8c9689ddd0 100644 --- a/flow/scripts/util.tcl +++ b/flow/scripts/util.tcl @@ -1,11 +1,11 @@ -proc log_cmd {cmd args} { +proc log_cmd { cmd args } { # log the command, escape arguments with spaces - set log_cmd "$cmd[join [lmap arg $args {format " %s" [expr {[string match {* *} $arg] ? "\"$arg\"" : "$arg"}]}] ""]" + set log_cmd "$cmd[join [lmap arg $args { format " %s" [expr { [string match {* *} $arg] ? "\"$arg\"" : "$arg" }] }] ""]" ;# tclint-disable-line line-length puts $log_cmd set start [clock seconds] set result [uplevel 1 [list $cmd {*}$args]] - set time [expr {[clock seconds] - $start}] - if {$time >= 5} { + set time [expr { [clock seconds] - $start }] + if { $time >= 5 } { # Ideally we'd use a single line, but the command can output text # and we don't want to mix it with the log, so output the time it took afterwards. puts "Took $time seconds: $log_cmd" @@ -13,24 +13,46 @@ proc log_cmd {cmd args} { return $result } -proc fast_route {} { - if {[env_var_exists_and_non_empty FASTROUTE_TCL]} { - source $::env(FASTROUTE_TCL) +proc repair_tie_fanout_helper { } { + if { [env_var_exists_and_non_empty TIE_SEPARATION] } { + set tie_separation $env(TIE_SEPARATION) } else { - set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) $::env(ROUTING_LAYER_ADJUSTMENT) - set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - if {[env_var_exists_and_non_empty MACRO_EXTENSION]} { - set_macro_extension $::env(MACRO_EXTENSION) - } + set tie_separation 0 } + + # Repair tie lo fanout + puts "Repair tie lo fanout..." + set tielo_cell_name [lindex $::env(TIELO_CELL_AND_PORT) 0] + set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]] + set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $::env(TIELO_CELL_AND_PORT) 1] + repair_tie_fanout -separation $tie_separation $tielo_pin + + # Repair tie hi fanout + puts "Repair tie hi fanout..." + set tiehi_cell_name [lindex $::env(TIEHI_CELL_AND_PORT) 0] + set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]] + set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $::env(TIEHI_CELL_AND_PORT) 1] + repair_tie_fanout -separation $tie_separation $tiehi_pin } -proc repair_timing_helper { {hold_margin 1} } { - set additional_args "-verbose" +proc fast_route { } { + if { [env_var_exists_and_non_empty FASTROUTE_TCL] } { + log_cmd source $::env(FASTROUTE_TCL) + } else { + log_cmd \ + set_global_routing_layer_adjustment \ + $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) $::env(ROUTING_LAYER_ADJUSTMENT) + log_cmd set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) + } +} + +proc repair_timing_helper { args } { + set additional_args "$args -verbose" append_env_var additional_args SETUP_SLACK_MARGIN -setup_margin 1 - if {$hold_margin || $::env(HOLD_SLACK_MARGIN) < 0} { + if { $::env(HOLD_SLACK_MARGIN) < 0 } { append_env_var additional_args HOLD_SLACK_MARGIN -hold_margin 1 } + append_env_var additional_args SETUP_MOVE_SEQUENCE -sequence 1 append_env_var additional_args TNS_END_PERCENT -repair_tns 1 append_env_var additional_args SKIP_PIN_SWAP -skip_pin_swap 0 append_env_var additional_args SKIP_GATE_CLONING -skip_gate_cloning 0 @@ -40,7 +62,7 @@ proc repair_timing_helper { {hold_margin 1} } { log_cmd repair_timing {*}$additional_args } -proc repair_design_helper {} { +proc repair_design_helper { } { puts "Perform buffer insertion and gate resizing..." set additional_args "-verbose" @@ -50,7 +72,7 @@ proc repair_design_helper {} { log_cmd repair_design {*}$additional_args } -proc recover_power_helper {} { +proc recover_power_helper { } { if { $::env(RECOVER_POWER) == 0 } { return } @@ -68,20 +90,20 @@ proc recover_power_helper {} { report_power } -proc extract_stage {input_file} { - if {![regexp {/([0-9])_(([0-9])_)?} $input_file match num1 _ num2]} { +proc extract_stage { input_file } { + if { ![regexp {/([0-9])_(([0-9])_)?} $input_file match num1 _ num2] } { puts "Error: Could not determine design stage from $input_file" exit 1 } lappend number_groups $num1 - if {$num2!=""} { - lappend number_groups $num2 + if { $num2 != "" } { + lappend number_groups $num2 } else { lappend number_groups "0" } } -proc find_sdc_file {input_file} { +proc find_sdc_file { input_file } { # canonicalize input file, sometimes it is called with an input # file relative to $::env(RESULTS_DIR), other times with # an absolute path @@ -95,11 +117,12 @@ proc find_sdc_file {input_file} { set sdc_file "" set exact_sdc [string map {.odb .sdc} $input_file] - set sdc_files [glob -nocomplain -directory $::env(RESULTS_DIR) -types f "\[1-9+\]_\[1-9_A-Za-z\]*\.sdc"] + set sdc_files \ + [glob -nocomplain -directory $::env(RESULTS_DIR) -types f "\[1-9+\]_\[1-9_A-Za-z\]*\.sdc"] set sdc_files [lsort -decreasing -dictionary $sdc_files] - set sdc_files [lmap file $sdc_files {file normalize $file}] + set sdc_files [lmap file $sdc_files { file normalize $file }] foreach name $sdc_files { - if {[lindex [lsort -decreasing -dictionary [list $name $exact_sdc] ] 0] == $exact_sdc} { + if { [lindex [lsort -decreasing -dictionary [list $name $exact_sdc]] 0] == $exact_sdc } { set sdc_file $name break } @@ -107,26 +130,36 @@ proc find_sdc_file {input_file} { return [list $design_stage $sdc_file] } -proc env_var_equals {env_var value} { - return [expr {[info exists ::env($env_var)] && $::env($env_var) == $value}] +proc env_var_equals { env_var value } { + return [expr { [info exists ::env($env_var)] && $::env($env_var) == $value }] } -proc env_var_exists_and_non_empty {env_var} { - return [expr {[info exists ::env($env_var)] && ![string equal $::env($env_var) ""]}] +proc env_var_exists_and_non_empty { env_var } { + return [expr { [info exists ::env($env_var)] && ![string equal $::env($env_var) ""] }] } -proc append_env_var {list_name var_name prefix has_arg} { +proc append_env_var { list_name var_name prefix has_arg } { upvar $list_name list - if {(!$has_arg && [env_var_equals $var_name 1]) || - ($has_arg && [env_var_exists_and_non_empty $var_name])} { + if { + (!$has_arg && [env_var_equals $var_name 1]) || + ($has_arg && [env_var_exists_and_non_empty $var_name]) + } { lappend list $prefix - if {$has_arg} { + if { $has_arg } { lappend list $::env($var_name) } } } -proc find_macros {} { +# Non-empty defaults should go into variables.yaml, generally +proc env_var_or_empty { env_var } { + if { [env_var_exists_and_non_empty $env_var] } { + return $::env($env_var) + } + return "" +} + +proc find_macros { } { set macros "" set db [ord::get_db] @@ -142,16 +175,16 @@ proc find_macros {} { return $macros } -proc erase_non_stage_variables {stage_name} { +proc erase_non_stage_variables { stage_name } { # "$::env(SCRIPTS_DIR)/stage_variables.py stage_name" returns list of # variables to erase. - # + # # Tcl yaml package can't be imported in the sta/openroad environment: - # + # # https://github.com/The-OpenROAD-Project/OpenROAD/issues/5875 set variables [exec $::env(SCRIPTS_DIR)/non_stage_variables.py $stage_name] foreach var $variables { - if {[info exists ::env($var)]} { + if { [info exists ::env($var)] } { unset ::env($var) } } @@ -159,19 +192,30 @@ proc erase_non_stage_variables {stage_name} { set global_route_congestion_report $::env(REPORTS_DIR)/congestion.rpt -proc place_density_with_lb_addon {} { - if {[env_var_exists_and_non_empty PLACE_DENSITY_LB_ADDON]} { +proc place_density_with_lb_addon { } { + if { [env_var_exists_and_non_empty PLACE_DENSITY_LB_ADDON] } { # check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON set place_density_lb [gpl::get_global_placement_uniform_density \ - -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ - -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)] - set place_density [expr $place_density_lb + ((1.0 - $place_density_lb) * $::env(PLACE_DENSITY_LB_ADDON)) + 0.01] - if {$place_density > 1.0} { - utl::error FLW 24 "Place density exceeds 1.0 (current PLACE_DENSITY_LB_ADDON = $::env(PLACE_DENSITY_LB_ADDON)). Please check if the value of PLACE_DENSITY_LB_ADDON is between 0 and 0.99." + -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ + -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)] + set place_density \ + [expr $place_density_lb + ((1.0 - $place_density_lb) * $::env(PLACE_DENSITY_LB_ADDON)) + 0.01] + if { $place_density > 1.0 } { + utl::error FLW 24 \ + "Place density exceeds 1.0 (current PLACE_DENSITY_LB_ADDON = \ + $::env(PLACE_DENSITY_LB_ADDON)). Please check if the value of \ + PLACE_DENSITY_LB_ADDON is between 0 and 0.99." } - puts "Placement density is $place_density, computed from PLACE_DENSITY_LB_ADDON $::env(PLACE_DENSITY_LB_ADDON) and lower bound $place_density_lb" + puts "Placement density is $place_density, computed from PLACE_DENSITY_LB_ADDON \ + $::env(PLACE_DENSITY_LB_ADDON) and lower bound $place_density_lb" } else { set place_density $::env(PLACE_DENSITY) } return $place_density } + +proc source_env_var_if_exists { env_var } { + if { [env_var_exists_and_non_empty $env_var] } { + log_cmd source $::env($env_var) + } +} diff --git a/flow/scripts/variables.mk b/flow/scripts/variables.mk index 88f8b706fc..6cfd19517d 100644 --- a/flow/scripts/variables.mk +++ b/flow/scripts/variables.mk @@ -3,26 +3,15 @@ # lazy evaluation, conditional code, include statements, # etc. -# Setup variables to point to root / head of the OpenROAD directory -# - the following settings allowed user to point OpenROAD binaries to different -# location -# - default is current install / clone directory -ifeq ($(origin FLOW_HOME), undefined) -FLOW_HOME := $(abspath $(dir $(firstword $(MAKEFILE_LIST)))/..) -endif -export FLOW_HOME - export DESIGN_NICKNAME?=$(DESIGN_NAME) #------------------------------------------------------------------------------- # Setup variables to point to other location for the following sub directory # - designs - default is under current directory # - platforms - default is under current directory -# - work home - default is current directory # - utils, scripts, test - default is under current directory export DESIGN_HOME ?= $(FLOW_HOME)/designs export PLATFORM_HOME ?= $(FLOW_HOME)/platforms -export WORK_HOME ?= . export UTILS_DIR ?= $(FLOW_HOME)/util export SCRIPTS_DIR ?= $(FLOW_HOME)/scripts @@ -31,10 +20,10 @@ export TEST_DIR ?= $(FLOW_HOME)/test PUBLIC=nangate45 sky130hd sky130hs asap7 ihp-sg13g2 gf180 ifeq ($(origin PLATFORM), undefined) - $(error PLATFORM variable net set.) + $(error PLATFORM variable not set.) endif ifeq ($(origin DESIGN_NAME), undefined) - $(error DESIGN_NAME variable net set.) + $(error DESIGN_NAME variable not set.) endif ifneq ($(PLATFORM_DIR),) @@ -52,7 +41,7 @@ include $(PLATFORM_DIR)/config.mk # __SPACE__ is a workaround for whitespace hell in "foreach"; there # is no way to escape space in defaults.py and get "foreach" to work. -$(foreach line,$(shell $(SCRIPTS_DIR)/defaults.py),$(eval export $(subst __SPACE__, ,$(line)))) +$(foreach line,$(shell $(PYTHON_EXE) $(SCRIPTS_DIR)/defaults.py),$(eval export $(subst __SPACE__, ,$(line)))) export LOG_DIR = $(WORK_HOME)/logs/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT) export OBJECTS_DIR = $(WORK_HOME)/objects/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT) @@ -81,6 +70,8 @@ export NUM_CORES #------------------------------------------------------------------------------- # setup all commands used within this flow +export PYTHON_EXE ?= $(shell command -v python3) + export TIME_BIN ?= env time TIME_CMD = $(TIME_BIN) -f 'Elapsed time: %E[h:]min:sec. CPU time: user %U sys %S (%P). Peak memory: %MKB.' TIME_TEST = $(shell $(TIME_CMD) echo foo 2>/dev/null) @@ -223,4 +214,16 @@ vars: .PHONY: print-% # Print any variable, for instance: make print-DIE_AREA -print-% : ; @echo "$* = $($*)" +print-%: + # HERE BE DRAGONS! + # + # We have to use /tmp. $(OBJECTS_DIR) may not exist + # at $(file) expansion time, which is before commands are run + # here, so we can't mkdir -p $(OBJECTS_DIR) either + # + # We have to use $(file ...) because we want to be able + # to print variables that contain newlines. + $(file >/tmp/print_tmp$$,$($*)) + @echo -n "$* = " + @cat /tmp/print_tmp$$ + @rm /tmp/print_tmp$$ diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 5319e04cb3..c08dc7d458 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -95,6 +95,7 @@ CORE_UTILIZATION: stages: - floorplan tunable: 1 + type: float CORE_AREA: description: > The core area specified as a list of lower-left and upper-right corners in @@ -146,6 +147,9 @@ LIB_FILES: A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell. +PLATFORM_TCL: + description: | + Specifies a Tcl script with commands to run before loading design. DONT_USE_CELLS: description: | Dont use cells eases pin access in detailed routing. @@ -169,6 +173,13 @@ SYNTH_MEMORY_MAX_BITS: default: 4096 stages: - synth +SYNTH_HDL_FRONTEND: + description: > + Select an alternative language frontend to ingest the design. Available option + is "slang". If the variable is empty, design is read with the Yosys read_verilog + command. + stages: + - synth SYNTH_BLACKBOXES: description: > List of cells treated as a black box by Yosys. With Bazel, this can be used @@ -183,6 +194,12 @@ SYNTH_NETLIST_FILES: subsequent modules are silently ignored and only the first module is used. stages: - synth +SYNTH_CANONICALIZE_TCL: + description: > + Specifies a Tcl script with commands to run as part of the synth + canonicalize step. + stages: + - synth LATCH_MAP_FILE: description: | List of latches treated as a black box by Yosys. @@ -204,12 +221,22 @@ TIEHI_CELL_AND_PORT: Netlist. stages: - synth - - place + - floorplan TIELO_CELL_AND_PORT: description: | Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist. stages: - synth + - floorplan +TIE_SEPARATION: + description: | + Distance separating tie high/low instances from the load. + stages: + - place +EARLY_SIZING_CAP_RATIO: + description: | + Ratio between the input pin capacitance and the output pin load during initial gate sizing. + stages: - place MIN_BUF_CELL_AND_PORTS: description: | @@ -248,6 +275,13 @@ SYNTH_WRAPPED_OPERATORS: the flow. stages: - synth +SWAP_ARITH_OPERATORS: + description: > + Improve timing QoR by swapping ALU and MULT arithmetic operators. + stages: + - synth + - floorplan + - place FLOORPLAN_DEF: description: | Use the DEF file to initialize floorplan. @@ -318,13 +352,13 @@ IO_CONSTRAINTS: - place IO_PLACER_H: description: > - The metal layer on which to place the I/O pins horizontally (top and bottom + A list of metal layers on which the I/O pins are placed horizontally (top and bottom of the die). stages: - place IO_PLACER_V: description: > - The metal layer on which to place the I/O pins vertically (sides of the + A list of metal layers on which the I/O pins are placed vertically (sides of the die). stages: - place @@ -351,6 +385,7 @@ CELL_PAD_IN_SITES_GLOBAL_PLACEMENT: - place - floorplan default: 0 + type: int tunable: 1 CELL_PAD_IN_SITES_DETAIL_PLACEMENT: description: > @@ -361,17 +396,24 @@ CELL_PAD_IN_SITES_DETAIL_PLACEMENT: - cts - grt default: 0 + type: int tunable: 1 PLACE_PINS_ARGS: description: | Arguments to place_pins stages: - place - default: "" PLACE_DENSITY: description: > - The desired placement density of cells. It reflects how spread the cells - would be on the core area. 1.0 = closely dense. 0.0 = widely spread. + The desired average placement density of cells: 1.0 = dense, 0.0 = widely spread. + + The intended effort is also communicated by this parameter. Use a low value for faster builds and higher value for better quality of results. + + If a too low value is used, the placer will not be able to place all cells and a recommended minimum placement density can be found in the logs. + + A too high value can lead to excessive runtimes, even timeouts and subtle failures in the flow after placement, such as in CTS or global routing when timing repair fails. + + The default is platform specific. stages: - floorplan - place @@ -383,6 +425,7 @@ PLACE_DENSITY_LB_ADDON: - floorplan - place tunable: 1 + type: float REPAIR_PDN_VIA_LAYER: description: | Remove power grid vias which generate DRC violations after detailed routing. @@ -390,7 +433,6 @@ GLOBAL_PLACEMENT_ARGS: description: > Use additional tuning parameters during global placement other than default args defined in global_place.tcl. - default: "" ENABLE_DPO: description: | Enable detail placement with improve_placement feature. @@ -477,6 +519,15 @@ SETUP_SLACK_MARGIN: - floorplan - grt default: 0 +SETUP_REPAIR_SEQUENCE: + description: | + Specifies the sequence of moves to do in repair_timing -setup. This should be a string + of move keywords separated by commas such as the default when not used: + "unbuffer,sizedown,sizeup,swap,buffer,clone,split". + stages: + - cts + - floorplan + - grt SKIP_GATE_CLONING: description: > Do not use gate cloning transform to fix timing violations (default: use @@ -569,8 +620,14 @@ DESIGN_NAME: VERILOG_FILES: required: true description: > - The path to the design Verilog files or JSON files providing a description - of modules (check `yosys -h write_json` for more details). + The path to the design Verilog/SystemVerilog files providing a description + of modules. + stages: + - synth +VERILOG_DEFINES: + description: > + Preprocessor defines passed to the language frontend. + Example: `-D HPDCACHE_ASSERT_OFF` stages: - synth SDC_FILE: @@ -650,20 +707,24 @@ SYNTH_KEEP_MODULES: SYNTH_ARGS: description: | Optional synthesis variables for yosys. - default: -flatten +SYNTH_HIER_SEPARATOR: + description: | + Separator used for the synthesis flatten stage. + default: . VERILOG_TOP_PARAMS: description: | Apply toplevel params (if exist). stages: - synth - default: "" CORE_ASPECT_RATIO: description: > The core aspect ratio (height / width). This value is ignored if `CORE_UTILIZATION` is undefined. stages: - floorplan + default: 1.0 tunable: 1 + type: float CORE_MARGIN: description: > The margin between the core area and die area, specified in microns. @@ -673,7 +734,9 @@ CORE_MARGIN: is undefined. stages: - floorplan + default: 1.0 tunable: 1 + type: float DIE_AREA: description: > The die area specified as a list of lower-left and upper-right corners in @@ -682,18 +745,6 @@ DIE_AREA: stages: - floorplan tunable: 1 -RESYNTH_AREA_RECOVER: - description: | - Enable re-synthesis for area reclaim. - stages: - - floorplan - default: 0 -RESYNTH_TIMING_RECOVER: - description: | - Enable re-synthesis for timing optimization. - stages: - - floorplan - default: 0 MACRO_ROWS_HALO_X: description: > Horizontal distance between the edge of the macro and the beginning of the @@ -718,9 +769,11 @@ CTS_BUF_DISTANCE: Distance (in microns) between buffers. stages: - cts + tunable: 1 + type: float CTS_BUF_LIST: description: | - List of cells used to construct the clock tree. + List of cells used to construct the clock tree. Overrides buffer inference. stages: - cts CTS_CLUSTER_DIAMETER: @@ -730,6 +783,7 @@ CTS_CLUSTER_DIAMETER: stages: - cts tunable: 1 + type: float CTS_CLUSTER_SIZE: description: > Maximum number of sinks per cluster. @@ -737,6 +791,12 @@ CTS_CLUSTER_SIZE: stages: - cts tunable: 1 + type: int +CTS_LIB_NAME: + description: | + Name of the Liberty library to use in selecting the clock buffers. + stages: + - cts CTS_SNAPSHOT: description: | Creates ODB/SDC files prior to clock net and setup/hold repair. @@ -762,6 +822,11 @@ ABSTRACT_SOURCE: Which .odb file to use to create abstract stages: - generate_abstract +PRE_GLOBAL_ROUTE_TCL: + description: | + Specifies a Tcl script with commands to run before global route. + stages: + - grt GLOBAL_ROUTE_ARGS: description: > Replaces default arguments for global route. diff --git a/flow/scripts/view_cells.tcl b/flow/scripts/view_cells.tcl index d6bf433d9a..c7a4ca087c 100644 --- a/flow/scripts/view_cells.tcl +++ b/flow/scripts/view_cells.tcl @@ -2,7 +2,7 @@ read_lef $::env(TECH_LEF) read_lef $::env(SC_LEF) -if {[info exist ::env(ADDITIONAL_LEFS)]} { +if { [info exist ::env(ADDITIONAL_LEFS)] } { foreach lef $::env(ADDITIONAL_LEFS) { read_lef $lef } @@ -16,9 +16,9 @@ set block [odb::dbBlock_create $chip all_cells] # Get all the masters set masters {} foreach lib [$db getLibs] { - foreach master [$lib getMasters] { - lappend masters $master - } + foreach master [$lib getMasters] { + lappend masters $master + } } # Find the number of masters & the max width and height of any master @@ -26,9 +26,9 @@ set max_width 0 set max_height 0 set num_masters 0 foreach master $masters { - set max_width [expr max($max_width, [$master getWidth])] - set max_height [expr max($max_height, [$master getHeight])] - incr num_masters + set max_width [expr max($max_width, [$master getWidth])] + set max_height [expr max($max_height, [$master getHeight])] + incr num_masters } # The steps for laying out the cells @@ -42,15 +42,15 @@ set x_width [expr ceil(sqrt($num_masters * $y_step / $x_step))] set x 0 set y 0 foreach master $masters { - set inst [odb::dbInst_create $block $master [$master getName]] - $inst setPlacementStatus PLACED - $inst setLocation [expr $x * $x_step] [expr $y * $y_step] - - incr x - if {$x == $x_width} { - set x 0 - incr y - } + set inst [odb::dbInst_create $block $master [$master getName]] + $inst setPlacementStatus PLACED + $inst setLocation [expr $x * $x_step] [expr $y * $y_step] + + incr x + if { $x == $x_width } { + set x 0 + incr y + } } gui::design_created gui::fit diff --git a/flow/scripts/write_ref_sdc.tcl b/flow/scripts/write_ref_sdc.tcl index 5de57dc045..60c6bb7658 100644 --- a/flow/scripts/write_ref_sdc.tcl +++ b/flow/scripts/write_ref_sdc.tcl @@ -19,7 +19,7 @@ if { [llength $clks] == 0 } { set ref_period [expr ($period - $slack) * (1.0 - $margin/100.0)] utl::info "FLW" 8 "Clock $clk_name period [format %.3f $ref_period]" utl::info "FLW" 9 "Clock $clk_name slack [format %.3f $slack]" - + set sources [$clk sources] # Redefine clock with updated period. create_clock -name $clk_name -period $ref_period $sources diff --git a/flow/test/BUILD b/flow/test/BUILD deleted file mode 100644 index 63efeade7d..0000000000 --- a/flow/test/BUILD +++ /dev/null @@ -1,9 +0,0 @@ -sh_binary( - name = "openroad", - srcs = ["openroad.sh"], - data = [ - "@openroad", - "@openroad//:all", - ], - visibility = ["//visibility:public"], -) diff --git a/flow/test/test_autotuner.sh b/flow/test/test_autotuner.sh index afd4e6ed8d..03e9ddd005 100755 --- a/flow/test/test_autotuner.sh +++ b/flow/test/test_autotuner.sh @@ -27,7 +27,7 @@ python3 -m unittest tools.AutoTuner.test.smoke_test_algo_eval.${PLATFORM_WITHOUT if [ "$PLATFORM_WITHOUT_DASHES" == "asap7" ] && [ "$DESIGN_NAME" == "gcd" ]; then echo "Running Autotuner ref file test (only once)" - python3 -m unittest tools.AutoTuner.test.ref_file_check.RefFileCheck.test_files + python3 -m unittest tools.AutoTuner.test.ref_file_check.RefFileCheck echo "Running AutoTuner resume test (only once)" # Temporarily disable resume check test due to flakiness diff --git a/flow/test/test_genElapsedTime.py b/flow/test/test_genElapsedTime.py index e6108cb093..36da00209e 100755 --- a/flow/test/test_genElapsedTime.py +++ b/flow/test/test_genElapsedTime.py @@ -30,7 +30,7 @@ def test_elapsed_time(self, mock_stdout): genElapsedTime.scan_logs(["--logDir", str(self.tmp_dir.name), "--noHeader"]) # check if output is correct expected_output = ( - self.tmp_dir.name + "\n1_test 5400 9440\nTotal 5400 9440\n" + self.tmp_dir.name + "\n1_test 5400 9440 N/A\nTotal 5400 9440\n" ).split() actual_output = mock_stdout.getvalue().split() self.assertEqual(actual_output, expected_output) @@ -44,7 +44,7 @@ def test_zero_time(self, mock_stdout): # call the script with the test log file genElapsedTime.scan_logs(["--logDir", str(self.tmp_dir.name), "--noHeader"]) expected_output = ( - self.tmp_dir.name + "\n1_test 74 9440\nTotal 74 9440\n" + self.tmp_dir.name + "\n1_test 74 9440 N/A\nTotal 74 9440\n" ).split() actual_output = mock_stdout.getvalue().split() self.assertEqual(actual_output, expected_output) @@ -61,7 +61,7 @@ def test_elapsed_time_longer_duration(self, mock_stdout): genElapsedTime.scan_logs(["--logDir", str(self.tmp_dir.name), "--noHeader"]) # check if output is correct expected_output = ( - self.tmp_dir.name + "\n1_test 744 9440 Total 744 9440" + self.tmp_dir.name + "\n1_test 744 9440 N/A Total 744 9440" ).split() actual_output = mock_stdout.getvalue().split() self.assertEqual(actual_output, expected_output) diff --git a/flow/tutorials/scripts/drt/drc_fix.tcl b/flow/tutorials/scripts/drt/drc_fix.tcl index 16e8030c85..b54c0fe41d 100644 --- a/flow/tutorials/scripts/drt/drc_fix.tcl +++ b/flow/tutorials/scripts/drt/drc_fix.tcl @@ -8,10 +8,9 @@ read_sdc ./gcd/gcd.sdc # global_route set_global_routing_layer_adjustment met1-met5 0.5 set_routing_layers -signal met1-met5 -set_macro_extension 2 global_route -guide_file [make_result_file route.guide] \ - -congestion_iterations 100 \ - -verbose + -congestion_iterations 100 \ + -verbose source ../../../platforms/sky130hd/setRC.tcl set_propagated_clock [all_clocks] @@ -23,10 +22,10 @@ set_thread_count 2 set drc_rpt [make_result_file 5_route_drc.rpt] set maze_log [make_result_file maze.log] detailed_route -output_drc $drc_rpt \ - -output_maze $maze_log \ - -bottom_routing_layer met1 \ - -top_routing_layer met5 \ - -verbose 1 + -output_maze $maze_log \ + -bottom_routing_layer met1 \ + -top_routing_layer met5 \ + -verbose 1 set route_def [make_result_file 5_route.def] write_def $route_def puts "Number of DRC Violations = [detailed_route_num_drvs]" diff --git a/flow/tutorials/scripts/drt/drc_issue.tcl b/flow/tutorials/scripts/drt/drc_issue.tcl index 54a6427d45..8ddc41817e 100644 --- a/flow/tutorials/scripts/drt/drc_issue.tcl +++ b/flow/tutorials/scripts/drt/drc_issue.tcl @@ -8,10 +8,9 @@ read_sdc ./gcd/gcd.sdc # global_route set_global_routing_layer_adjustment met1-met5 0.5 set_routing_layers -signal met1-met5 -set_macro_extension 2 global_route -guide_file [make_result_file route.guide] \ - -congestion_iterations 100 \ - -verbose + -congestion_iterations 100 \ + -verbose source ../../../platforms/sky130hd/setRC.tcl set_propagated_clock [all_clocks] @@ -23,10 +22,10 @@ set_thread_count 2 set drc_rpt [make_result_file 5_route_drc.rpt] set maze_log [make_result_file maze.log] detailed_route -output_drc $drc_rpt \ - -output_maze $maze_log \ - -bottom_routing_layer met1 \ - -top_routing_layer met5 \ - -verbose 1 + -output_maze $maze_log \ + -bottom_routing_layer met1 \ + -top_routing_layer met5 \ + -verbose 1 set route_def [make_result_file 5_route.def] write_def $route_def puts "Number of DRC Violations = [detailed_route_num_drvs]" diff --git a/flow/tutorials/scripts/drt/helpers.tcl b/flow/tutorials/scripts/drt/helpers.tcl index be1af8e7c2..bfb1fe8386 100644 --- a/flow/tutorials/scripts/drt/helpers.tcl +++ b/flow/tutorials/scripts/drt/helpers.tcl @@ -14,7 +14,7 @@ proc make_result_file { filename } { # puts [exec cat $file] without forking. proc report_file { file } { set stream [open $file r] - + while { [gets $stream line] >= 0 } { puts $line } @@ -24,9 +24,9 @@ proc report_file { file } { proc diff_files { file1 file2 } { set stream1 [open $file1 r] set stream2 [open $file2 r] - + set line 1 - set diff_line 0; + set diff_line 0 while { [gets $stream1 line1] >= 0 && [gets $stream2 line2] >= 0 } { if { $line1 != $line2 } { set diff_line $line diff --git a/flow/tutorials/scripts/gui/load_lef.tcl b/flow/tutorials/scripts/gui/load_lef.tcl index 259bdb4c03..34d5760cb8 100644 --- a/flow/tutorials/scripts/gui/load_lef.tcl +++ b/flow/tutorials/scripts/gui/load_lef.tcl @@ -1,6 +1,6 @@ -proc load_lef_sky130 {} { - set FLOW_PATH [exec pwd] - read_lef $FLOW_PATH/../../../platforms/sky130hd/lef/sky130_fd_sc_hd.tlef - read_lef $FLOW_PATH/../../../platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef +proc load_lef_sky130 { } { + set FLOW_PATH [exec pwd] + read_lef $FLOW_PATH/../../../platforms/sky130hd/lef/sky130_fd_sc_hd.tlef + read_lef $FLOW_PATH/../../../platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef } create_toolbar_button -name "Load_LEF" -text "Load_LEF" -script {load_lef_sky130} -echo diff --git a/flow/util/BUILD.bazel b/flow/util/BUILD.bazel index 92641ed57b..b8892cbab6 100644 --- a/flow/util/BUILD.bazel +++ b/flow/util/BUILD.bazel @@ -25,7 +25,6 @@ MAKEFILE_SHARED = [ filegroup( name = "makefile", srcs = glob(MAKEFILE_SHARED + [ - "*.pl", "*.py", "*.sh", ]), @@ -36,7 +35,7 @@ filegroup( filegroup( name = "makefile_yosys", srcs = glob(MAKEFILE_SHARED) + [ - "mergeLib.pl", + "merge_lib.py", "preprocessLib.py", ], visibility = ["//visibility:public"], diff --git a/flow/util/cell-veneer/lefdef.tcl b/flow/util/cell-veneer/lefdef.tcl index 2507dd5fb9..901fd13706 100644 --- a/flow/util/cell-veneer/lefdef.tcl +++ b/flow/util/cell-veneer/lefdef.tcl @@ -1,20 +1,19 @@ -proc absolute_rectangle {rect offset} { - return [list \ - [expr [lindex $rect 0] + [lindex $offset 0]] \ - [expr [lindex $rect 1] + [lindex $offset 1]] \ - [expr [lindex $rect 2] + [lindex $offset 0]] \ - [expr [lindex $rect 3] + [lindex $offset 1]] \ - ] -} -proc relative_rectangle {rect offset} { - return [list \ - [expr [lindex $rect 0] - [lindex $offset 0]] \ - [expr [lindex $rect 1] - [lindex $offset 1]] \ - [expr [lindex $rect 2] - [lindex $offset 0]] \ - [expr [lindex $rect 3] - [lindex $offset 1]] \ - ] +proc absolute_rectangle { rect offset } { + return [list \ + [expr [lindex $rect 0] + [lindex $offset 0]] \ + [expr [lindex $rect 1] + [lindex $offset 1]] \ + [expr [lindex $rect 2] + [lindex $offset 0]] \ + [expr [lindex $rect 3] + [lindex $offset 1]]] +} +proc relative_rectangle { rect offset } { + return [list \ + [expr [lindex $rect 0] - [lindex $offset 0]] \ + [expr [lindex $rect 1] - [lindex $offset 1]] \ + [expr [lindex $rect 2] - [lindex $offset 0]] \ + [expr [lindex $rect 3] - [lindex $offset 1]]] } +# tclint-disable-next-line command-args if [package vcompare 8.6 $tcl_version] { proc lmap {_var list body} { upvar 1 $_var var @@ -25,919 +24,955 @@ if [package vcompare 8.6 $tcl_version] { } namespace eval lef { - variable lefOut stdout - variable def_units 2000 - - proc open {file_name} { - variable lefOut - set lefOut [::open $file_name w] - } - - proc close {} { - variable lefOut - if {$lefOut != "stdout"} { - ::close $lefOut - } - set lefOut stdout - } - - proc out {args} { - variable lefOut - - if {[llength $args] == 2} { - puts [lindex $args 0] $lefOut [lindex $args 1] - } else { - puts $lefOut [lindex $args 0] - } - } +variable lefOut stdout +variable def_units 2000 - variable cells - - proc get_cells {} { - variable cells - return $cells - } - - proc get_cell {cell_name} { - variable cells - return [dict get $cells $cell_name] - } - - proc get_width {cell} { - return [expr [lindex [dict get $cell die_area] 2] - [lindex [dict get $cell die_area] 0]] - } - - proc get_height {cell} { - return [expr [lindex [dict get $cell die_area] 3] - [lindex [dict get $cell die_area] 1]] - } - - proc read_macros {file_name} { - variable cells - variable def_units - - set ch [::open $file_name] - - set cells {} +# tclint-disable-next-line redefined-builtin +proc open { file_name } { + variable lefOut + set lefOut [::open $file_name w] +} - while {![eof $ch]} { - set line [gets $ch] +# tclint-disable-next-line redefined-builtin +proc close { } { + variable lefOut + if { $lefOut != "stdout" } { + ::close $lefOut + } + set lefOut stdout +} - if {[regexp {MACRO\s*([^\s]*)} $line - cell_name]} { - dict set cells $cell_name units $def_units - dict set cells $cell_name name $cell_name - while {![eof $ch]} { - set line [gets $ch] - if {[regexp {^\s*$} $line]} { - continue - } elseif {[regexp {CLASS\s+([^\s]*)} $line - cell_class]} { - dict set cells $cell_name cell_class $cell_class - } elseif {[regexp {ORIGIN\s+([^\s]*)\s+([^\s]*)} $line - origin_x origin_y]} { - dict set cells $cell_name origin [lmap x [list $origin_x $origin_y] {expr round($x * $def_units)}] - } elseif {[regexp {FOREIGN\s+([^\s]*)\s+([^\s]*)\s+([^\s]*)} $line - foreign x y]} { - dict set cells $cell_name foreign [list ref $foreign origin [lmap x [list $x $y] {expr round($x * $def_units)}]] - } elseif {[regexp {SIZE\s+([^\s]*)\s+BY\s+([^\s]*)} $line - width height]} { - dict set cells $cell_name die_area [list 0 0 [expr round($width * $def_units)] [expr round($height * $def_units)]] - } elseif {[regexp {SYMMETRY\s+(.*)\s;} $line - symmetry]} { - dict set cells $cell_name symmetry $symmetry - } elseif {[regexp {SITE\s+([^\s]*)} $line - site]} { - dict set cells $cell_name site $site - } elseif {[regexp {PIN\s*([^\s]*)} $line - pin_name]} { - set pin_pattern [regsub -all {([\[\]])} $pin_name {\\\1}] - if {[info vars antennamodel] != ""} { - unset antennamodel - } - while {![eof $ch]} { - set line [gets $ch] - if {[regexp {^\s*$} $line]} { - continue - } elseif {[regexp {DIRECTION\s+([^\s]*)} $line - direction]} { - dict set cells $cell_name pins $pin_name direction $direction - } elseif {[regexp {USE\s+([^\s]*)} $line - use]} { - dict set cells $cell_name pins $pin_name use $use - } elseif {[regexp {ANTENNAMODEL\s+([^\s]*)} $line - antennamodel]} { - continue - } elseif {[regexp {ANTENNAGATEAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - gate_area layer]} { - if {[info vars antennamodel] == ""} { - set antennamodel "default" - } - if {[dict exists $cells $cell_name pins $pin_name antenna_model $antennamodel]} { - set model [dict get $cells $cell_name pins $pin_name antenna_model $antennamodel] - } else { - set model {} - } - lappend model [list gate_area $gate_area layer $layer] - dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model - } elseif {[regexp {ANTENNAGATEAREA\s+([^\s]*)} $line - gate_area]} { - if {[info vars antennamodel] == ""} { - set antennamodel "default" - } - if {[dict exists $cells $cell_name pins $pin_name antenna_model $antennamodel]} { - set model [dict get $cells $cell_name pins $pin_name antenna_model $antennamodel] - } else { - set model {} - } - lappend model [list gate_area $gate_area] - dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model - } elseif {[regexp {ANTENNADIFFAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - antennadiffarea layer]} { - dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea - dict set cells $cell_name pins $pin_name antennadiffarea layer $antennadiffarea - } elseif {[regexp {ANTENNADIFFAREA\s+([^\s]*)\s} $line - antennadiffarea]} { - dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea - } elseif {[regexp {SHAPE\s+([^\s]*)\s+([^\s]*)} $line - shape]} { - dict set cells $cell_name pins $pin_name shape $shape - } elseif {[regexp {PORT} $line]} { - set port {} - dict set port orientation N - while {![eof $ch]} { - set line [gets $ch] - if {[regexp {^\s*$} $line]} { - continue - } elseif {[regexp {LAYER\s+([^\s]*)} $line - layer]} { - continue - } elseif {[regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2]} { - if {[dict exists $port layers $layer shapes]} { - set layer_shapes [dict get $port layers $layer shapes] - } else { - set layer_shapes {} - } - if {[dict exists $port fixed]} { - set offset [dict get $port fixed] - } else { - set offset [lmap x [list $x1 $y1] {expr round($x * $def_units)}] - dict set port fixed $offset - } - set new_shape [list \ - rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] {expr round($x * $def_units)}] $offset] \ - mask $mask \ - ] - lappend layer_shapes $new_shape - dict set port layers $layer shapes $layer_shapes - } elseif {[regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2]} { - if {[dict exists $port layers $layer shapes]} { - set layer_shapes [dict get $port layers $layer shapes] - } else { - set layer_shapes {} - } - if {[dict exists $port fixed]} { - set offset [dict get $port fixed] - } else { - set offset [lmap x [list $x1 $y1] {expr round($x * $def_units)}] - dict set port fixed $offset - } - set new_shape [list \ - rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] {expr round($x * $def_units)}] $offset] \ - ] - lappend layer_shapes $new_shape - dict set port layers $layer shapes $layer_shapes - } elseif {[regexp {END} $line]} { - if {[dict exists $cells $cell_name pins $pin_name ports]} { - set ports [dict get $cells $cell_name pins $pin_name ports] - } else { - set ports {} - } - lappend ports $port - dict set cells $cell_name pins $pin_name ports $ports - break - } else { - error "Parsing failure PORT:\n$line" - } - } - } elseif {[regexp "END\\s$pin_pattern" $line]} { - break - } else { - error "Parsing failure PIN:\n$line" - } - } - } elseif {[regexp {OBS} $line]} { - while {![eof $ch]} { - set line [gets $ch] - if {[regexp {^\s*$} $line]} { - continue - } elseif {[regexp {LAYER\s+([^\s]*)(\s+DESIGNRULEWIDTH\s+([0-9.]+))?} $line - layer - drw]} { - if {$drw != ""} { - dict set cells $cell_name layers $layer drw $drw - } - continue - } elseif {[regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2]} { - if {[dict exists $cells $cell_name obstructions $layer]} { - set obstructions [dict get $cells $cell_name obstructions $layer] - } else { - set obstructions {} - } - lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] {expr round($x * $def_units)}] mask $mask] - dict set cells $cell_name obstructions $layer $obstructions - } elseif {[regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2]} { - if {[dict exists $cells $cell_name obstructions $layer]} { - set obstructions [dict get $cells $cell_name obstructions $layer] - } else { - set obstructions {} - } - lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] {expr round($x * $def_units)}]] - dict set cells $cell_name obstructions $layer $obstructions - } elseif {[regexp {END} $line]} { - break - } else { - error "Parsing failure OBS:\n$line" - } - } - } elseif {[regexp "END\\s*$cell_name" $line]} { - break - } else { - error "Parsing failure MACRO\n$line" - } - } - } - } +proc out { args } { + variable lefOut - ::close $ch - } + if { [llength $args] == 2 } { + puts [lindex $args 0] $lefOut [lindex $args 1] + } else { + puts $lefOut [lindex $args 0] + } +} - proc get_blockage_layers {design} { - if {[dict exists $design blockage_layers]} { - return [dict get $design blockage_layers] - } +variable cells - set blocked_layers {} +proc get_cells { } { + variable cells + return $cells +} - dict for {layer_name obstructions} [dict get $design obstructions] { - lappend blocked_layers $layer_name - } - return $blocked_layers - } +proc get_cell { cell_name } { + variable cells + return [dict get $cells $cell_name] +} - proc write_header {} { - } - proc write_footer {} { - } - # Read a LEF from a file into a dictionary with the name of the cell as the key and the following entries - # - cell_class - # - origin - # - foreign - # - ref - # - origin - # - die_area - # - symmetry - # - site - # - pins: dict with the name of the pin as the key - # - antenna_model - # - gate_area - # - layer - # - antennadiffarea - # - layer - # - area - # - direction - # - use - # - shape - # - ports: a list of lists of shapes that make up a physical connection - # - layer - # - rect - # - mask? - # - obstructions - # - layer: a dictionaries with layer_name as the key - # - rect - # - mask? - # - proc write {design} { - set def_units [dict get $design units] - - out "MACRO [dict get $design name]" - out " CLASS [dict get $design cell_class] ;" - if {[dict exists $design origin]} { - out " ORIGIN [dict get $design origin] ;" - } else { - out " ORIGIN 0.0 0.0 ;" - } - out " FOREIGN [dict get $design foreign ref] [dict get $design foreign origin] ;" - out " SIZE [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units] BY [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units] ;" - out " SYMMETRY [dict get $design symmetry] ;" - if {[dict exists $design site]} { - out " SITE [dict get $design site] ;" - } +proc get_width { cell } { + return [expr [lindex [dict get $cell die_area] 2] - [lindex [dict get $cell die_area] 0]] +} - if {[dict exists $design pins]} { - dict for {pin_name pin} [dict get $design pins] { - out " PIN $pin_name" - out " DIRECTION [dict get $pin direction] ;" - if {[dict exists $pin use]} { - out " USE [dict get $pin use] ;" - } - foreach port [dict get $pin ports] { - out " PORT " - foreach layer_name [dict keys [dict get $port layers]] { - set shapes [dict get $port layers $layer_name shapes] - - out " LAYER $layer_name ;" - foreach shape $shapes { - if {[dict exists $port fixed]} { - set offset [dict get $port fixed] - } elseif {[dict exists $port placed]} { - set offset [dict get $port placed] - } else { - set offset [list 0 0] - } - set rect [absolute_rectangle [dict get $shape rect] $offset] - - if {[dict exists $shape mask]} { - out " RECT MASK [dict get $shape mask] [lmap x $rect {expr 1.0 * $x / $def_units}] ;" - } else { - out " RECT [lmap x $rect {expr 1.0 * $x / $def_units}] ;" - } - } - } - out " END " - } - out " END $pin_name" - } - } +proc get_height { cell } { + return [expr [lindex [dict get $cell die_area] 3] - [lindex [dict get $cell die_area] 1]] +} - if {[dict exists $design obstructions]} { - out " OBS" - if {[dict get $design use_sheet_obstructions]} { - dict for {layer_name obstructions} [dict get $design obstructions] { - lappend blocked_layers $layer_name +# tclint-disable line-length +proc read_macros { file_name } { + variable cells + variable def_units + + set ch [::open $file_name] + + set cells {} + + while { ![eof $ch] } { + set line [gets $ch] + + if { [regexp {MACRO\s*([^\s]*)} $line - cell_name] } { + dict set cells $cell_name units $def_units + dict set cells $cell_name name $cell_name + while { ![eof $ch] } { + set line [gets $ch] + if { [regexp {^\s*$} $line] } { + continue + } elseif { [regexp {CLASS\s+([^\s]*)} $line - cell_class] } { + dict set cells $cell_name cell_class $cell_class + } elseif { [regexp {ORIGIN\s+([^\s]*)\s+([^\s]*)} $line - origin_x origin_y] } { + dict set cells $cell_name origin [lmap x [list $origin_x $origin_y] { expr round($x * $def_units) }] + } elseif { [regexp {FOREIGN\s+([^\s]*)\s+([^\s]*)\s+([^\s]*)} $line - foreign x y] } { + dict set cells $cell_name foreign [list ref $foreign origin [lmap x [list $x $y] { expr round($x * $def_units) }]] + } elseif { [regexp {SIZE\s+([^\s]*)\s+BY\s+([^\s]*)} $line - width height] } { + dict set cells $cell_name die_area [list 0 0 [expr round($width * $def_units)] [expr round($height * $def_units)]] + } elseif { [regexp {SYMMETRY\s+(.*)\s;} $line - symmetry] } { + dict set cells $cell_name symmetry $symmetry + } elseif { [regexp {SITE\s+([^\s]*)} $line - site] } { + dict set cells $cell_name site $site + } elseif { [regexp {PIN\s*([^\s]*)} $line - pin_name] } { + set pin_pattern [regsub -all {([\[\]])} $pin_name {\\\1}] + if { [info vars antennamodel] != "" } { + unset antennamodel + } + while { ![eof $ch] } { + set line [gets $ch] + if { [regexp {^\s*$} $line] } { + continue + } elseif { [regexp {DIRECTION\s+([^\s]*)} $line - direction] } { + dict set cells $cell_name pins $pin_name direction $direction + } elseif { [regexp {USE\s+([^\s]*)} $line - use] } { + dict set cells $cell_name pins $pin_name use $use + } elseif { [regexp {ANTENNAMODEL\s+([^\s]*)} $line - antennamodel] } { + continue + } elseif { [regexp {ANTENNAGATEAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - gate_area layer] } { + if { [info vars antennamodel] == "" } { + set antennamodel "default" + } + if { [dict exists $cells $cell_name pins $pin_name antenna_model $antennamodel] } { + set model [dict get $cells $cell_name pins $pin_name antenna_model $antennamodel] + } else { + set model {} + } + lappend model [list gate_area $gate_area layer $layer] + dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model + } elseif { [regexp {ANTENNAGATEAREA\s+([^\s]*)} $line - gate_area] } { + if { [info vars antennamodel] == "" } { + set antennamodel "default" } - set sheet "0 0 [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units] [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units]" - foreach layer_name [get_blockage_layers $design] { - if {[dict exists $design layers $layer_name drw]} { - set drw "DESIGNRULEWIDTH [dict get $design layers $layer_name drw] " + if { [dict exists $cells $cell_name pins $pin_name antenna_model $antennamodel] } { + set model [dict get $cells $cell_name pins $pin_name antenna_model $antennamodel] + } else { + set model {} + } + lappend model [list gate_area $gate_area] + dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model + } elseif { [regexp {ANTENNADIFFAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - antennadiffarea layer] } { + dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea + dict set cells $cell_name pins $pin_name antennadiffarea layer $antennadiffarea + } elseif { [regexp {ANTENNADIFFAREA\s+([^\s]*)\s} $line - antennadiffarea] } { + dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea + } elseif { [regexp {SHAPE\s+([^\s]*)\s+([^\s]*)} $line - shape] } { + dict set cells $cell_name pins $pin_name shape $shape + } elseif { [regexp {PORT} $line] } { + set port {} + dict set port orientation N + while { ![eof $ch] } { + set line [gets $ch] + if { [regexp {^\s*$} $line] } { + continue + } elseif { [regexp {LAYER\s+([^\s]*)} $line - layer] } { + continue + } elseif { [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] } { + if { [dict exists $port layers $layer shapes] } { + set layer_shapes [dict get $port layers $layer shapes] + } else { + set layer_shapes {} + } + if { [dict exists $port fixed] } { + set offset [dict get $port fixed] + } else { + set offset [lmap x [list $x1 $y1] { expr round($x * $def_units) }] + dict set port fixed $offset + } + set new_shape [list \ + rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] $offset] \ + mask $mask] + lappend layer_shapes $new_shape + dict set port layers $layer shapes $layer_shapes + } elseif { [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] } { + if { [dict exists $port layers $layer shapes] } { + set layer_shapes [dict get $port layers $layer shapes] + } else { + set layer_shapes {} + } + if { [dict exists $port fixed] } { + set offset [dict get $port fixed] + } else { + set offset [lmap x [list $x1 $y1] { expr round($x * $def_units) }] + dict set port fixed $offset + } + set new_shape [list \ + rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] $offset]] + lappend layer_shapes $new_shape + dict set port layers $layer shapes $layer_shapes + } elseif { [regexp {END} $line] } { + if { [dict exists $cells $cell_name pins $pin_name ports] } { + set ports [dict get $cells $cell_name pins $pin_name ports] + } else { + set ports {} + } + lappend ports $port + dict set cells $cell_name pins $pin_name ports $ports + break } else { - set drw "" + error "Parsing failure PORT:\n$line" } - out " LAYER $layer_name $drw;" - out " RECT $sheet ;" } + } elseif { [regexp "END\\s$pin_pattern" $line] } { + break } else { - dict for {layer_name obstructions} [dict get $design obstructions] { - out " LAYER $layer_name ;" - foreach obs $obstructions { - if {[dict exists $obs mask]} { - out " RECT MASK [dict get $obs mask] [lmap x [dict get $obs rect] {expr 1.0 * $x / $def_units}] ;" - } else { - out " RECT [lmap x [dict get $obs rect] {expr 1.0 * $x / $def_units}] ;" - } - } + error "Parsing failure PIN:\n$line" + } + } + } elseif { [regexp {OBS} $line] } { + while { ![eof $ch] } { + set line [gets $ch] + if { [regexp {^\s*$} $line] } { + continue + } elseif { [regexp {LAYER\s+([^\s]*)(\s+DESIGNRULEWIDTH\s+([0-9.]+))?} $line - layer - drw] } { + if { $drw != "" } { + dict set cells $cell_name layers $layer drw $drw + } + continue + } elseif { [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] } { + if { [dict exists $cells $cell_name obstructions $layer] } { + set obstructions [dict get $cells $cell_name obstructions $layer] + } else { + set obstructions {} + } + lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] mask $mask] + dict set cells $cell_name obstructions $layer $obstructions + } elseif { [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] } { + if { [dict exists $cells $cell_name obstructions $layer] } { + set obstructions [dict get $cells $cell_name obstructions $layer] + } else { + set obstructions {} } + lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }]] + dict set cells $cell_name obstructions $layer $obstructions + } elseif { [regexp {END} $line] } { + break + } else { + error "Parsing failure OBS:\n$line" } - out " END" + } + } elseif { [regexp "END\\s*$cell_name" $line] } { + break + } else { + error "Parsing failure MACRO\n$line" } - out "END [dict get $design name]" - out "" + } } - - proc write_cells {file_name cells} { - lef open $file_name - - out "###############################################################" - out "# Created by cell-veneer" - out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]" - out "###############################################################" - out "" - out "VERSION 5.8 ;" - out "BUSBITCHARS \"\[\]\" ;" - out "DIVIDERCHAR \"/\" ;" - out "" - out "SITE sc10p5mcpp84_14lpp" - out " CLASS CORE ;" - out " SIZE 0.084 BY 0.672 ;" - out " SYMMETRY Y ;" - out "END sc10p5mcpp84_14lpp" - out "" - out "SITE sc10p5mcpp84_14lpp_pg" - out " CLASS CORE ;" - out " SIZE 0.084 BY 1.344 ;" - out " SYMMETRY Y ;" - out "END sc10p5mcpp84_14lpp_pg" - out "" + } - dict for {cell_name cell} $cells { - lef write $cell - } + ::close $ch +} +# tclint-enable line-length - out "END LIBRARY" - out "" - lef close - } +proc get_blockage_layers { design } { + if { [dict exists $design blockage_layers] } { + return [dict get $design blockage_layers] + } - proc write_macros {file_name cells} { - lef open $file_name + set blocked_layers {} - out "###############################################################" - out "# Created by cell-veneer" - out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]" - out "###############################################################" - out "" - out "VERSION 5.8 ;" - out "BUSBITCHARS \"\[\]\" ;" - out "DIVIDERCHAR \"/\" ;" - out "" + dict for {layer_name obstructions} [dict get $design obstructions] { + lappend blocked_layers $layer_name + } + return $blocked_layers +} - dict for {cell_name cell} $cells { - lef write $cell - } +proc write_header { } { - out "END LIBRARY" - out "" - lef close - } +} +proc write_footer { } { - namespace export read_macros get_width get_height - namespace export get_cell get_cells write write_cells write_macros - namespace export open close out - namespace ensemble create } +# tclint-disable-next-line line-length +# Read a LEF from a file into a dictionary with the name of the cell as the key and the following entries +# - cell_class +# - origin +# - foreign +# - ref +# - origin +# - die_area +# - symmetry +# - site +# - pins: dict with the name of the pin as the key +# - antenna_model +# - gate_area +# - layer +# - antennadiffarea +# - layer +# - area +# - direction +# - use +# - shape +# - ports: a list of lists of shapes that make up a physical connection +# - layer +# - rect +# - mask? +# - obstructions +# - layer: a dictionaries with layer_name as the key +# - rect +# - mask? +# +proc write { design } { + set def_units [dict get $design units] + + out "MACRO [dict get $design name]" + out " CLASS [dict get $design cell_class] ;" + if { [dict exists $design origin] } { + out " ORIGIN [dict get $design origin] ;" + } else { + out " ORIGIN 0.0 0.0 ;" + } + out " FOREIGN [dict get $design foreign ref] [dict get $design foreign origin] ;" + out " SIZE [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units]\ + BY [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units] ;" + out " SYMMETRY [dict get $design symmetry] ;" + if { [dict exists $design site] } { + out " SITE [dict get $design site] ;" + } + + if { [dict exists $design pins] } { + dict for {pin_name pin} [dict get $design pins] { + out " PIN $pin_name" + out " DIRECTION [dict get $pin direction] ;" + if { [dict exists $pin use] } { + out " USE [dict get $pin use] ;" + } + foreach port [dict get $pin ports] { + out " PORT " + foreach layer_name [dict keys [dict get $port layers]] { + set shapes [dict get $port layers $layer_name shapes] + + out " LAYER $layer_name ;" + foreach shape $shapes { + if { [dict exists $port fixed] } { + set offset [dict get $port fixed] + } elseif { [dict exists $port placed] } { + set offset [dict get $port placed] + } else { + set offset [list 0 0] + } + set rect [absolute_rectangle [dict get $shape rect] $offset] -namespace eval def { - variable def_units - variable defOut stdout - variable designs {} - - proc open {file_name} { - variable defOut - set defOut [::open $file_name w] - } - - proc close {} { - variable defOut - if {$defOut != "stdout"} { - ::close $defOut + if { [dict exists $shape mask] } { + out \ + " RECT MASK [dict get $shape mask]\ + [lmap x $rect { expr { 1.0 * $x / $def_units } }] \ + ;" + } else { + out " RECT [lmap x $rect { expr 1.0 * $x / $def_units }] ;" + } + } } - set defOut stdout + out " END " + } + out " END $pin_name" } - - proc out {args} { - variable defOut - - if {[llength $args] == 2} { - puts [lindex $args 0] $defOut [lindex $args 1] + } + + if { [dict exists $design obstructions] } { + out " OBS" + if { [dict get $design use_sheet_obstructions] } { + dict for {layer_name obstructions} [dict get $design obstructions] { + lappend blocked_layers $layer_name + } + set sheet [concat \ + 0 0 \ + [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units] \ + [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units]] + foreach layer_name [get_blockage_layers $design] { + if { [dict exists $design layers $layer_name drw] } { + set drw "DESIGNRULEWIDTH [dict get $design layers $layer_name drw] " } else { - puts $defOut [lindex $args 0] + set drw "" } + out " LAYER $layer_name $drw;" + out " RECT $sheet ;" + } + } else { + dict for {layer_name obstructions} [dict get $design obstructions] { + out " LAYER $layer_name ;" + foreach obs $obstructions { + if { [dict exists $obs mask] } { + out " RECT MASK [dict get $obs mask]\ + [lmap x [dict get $obs rect] { expr { 1.0 * $x / $def_units } }] + ;" + } else { + out " RECT [lmap x [dict get $obs rect] { expr 1.0 * $x / $def_units }] ;" + } + } + } } + out " END" + } + out "END [dict get $design name]" + out "" +} - # Write out DEF from a design structure which is a dictionary with the following keys - # - name - # - tool - # - units - # - die_area - # - core_area - # - rows: dict with the index of the row as the key - # - site - # - start - # - height - # - orientation - # - num_sites - # - site_width - # - pins: dict with the name of the pin as the key - # - net_name - # - direction - # - use - # - special - # - ports : a list of dictionaries, one per port - # - orientation - # - (placed|fixed) - # - layers - # - spacing - # - designrulewidth - # - shapes : list of rectangles (or polygons) - # - (rect|polygon) - # - physical_viarules: dict with the name of the viarule as the key - # - rule - # - cutsize - # - layers - # - cutspacing - # - enclosure - # - rowcol - # - components: dict with the instance name of the component as the key - # - inst_name - # - cell_name - # - (fixed|placed)? - # - orientation - # - nets: dict with the name of the net as the key - # - use: SIGNAL | POWER | GROUND - # - connections: list of instance pin pairs - # - routes: list of dictionaries - # - layer - # - points: list of points, where a point can be an XY location or the name of a VIA - # - special_nets: dict with the name of the net as the key - # - use: SIGNAL | POWER | GROUND - # - connections: list of instance pin pairs - # - routes: list of dictioaries - # - layer - # - width - # - shape - # - points: list of points, where a point can be an XY location or the name of a VIA - # - - proc shift_point {point x y} { - return [list [expr [lindex $point 0] + $x] [expr [lindex $point 1] + $y]] - } - - proc shift_rect {rect x y} { - return [list [expr [lindex $rect 0] + $x] [expr [lindex $rect 1] + $y] [expr [lindex $rect 2] + $x] [expr [lindex $rect 3] + $y]] - } +proc write_cells { file_name cells } { + lef open $file_name + + out "###############################################################" + out "# Created by cell-veneer" + out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]" + out "###############################################################" + out "" + out "VERSION 5.8 ;" + out "BUSBITCHARS \"\[\]\" ;" + out "DIVIDERCHAR \"/\" ;" + out "" + out "SITE sc10p5mcpp84_14lpp" + out " CLASS CORE ;" + out " SIZE 0.084 BY 0.672 ;" + out " SYMMETRY Y ;" + out "END sc10p5mcpp84_14lpp" + out "" + out "SITE sc10p5mcpp84_14lpp_pg" + out " CLASS CORE ;" + out " SIZE 0.084 BY 1.344 ;" + out " SYMMETRY Y ;" + out "END sc10p5mcpp84_14lpp_pg" + out "" + + dict for {cell_name cell} $cells { + lef write $cell + } + + out "END LIBRARY" + out "" + lef close +} - proc shift_origin {design x y} { - if {[dict exists $design die_area]} { - dict set design die_area [shift_rect [dict get $design die_area] $x $y] - } - if {[dict exists $design core_area]} { - dict set design core_area [shift_rect [dict get $design core_area] $x $y] - } - if {[dict exists $design rows]} { - } - if {[dict exists $design pins]} { - dict for {pin_name pin} [dict get $design pins] { - set ports {} - foreach port [dict get $pin ports] { - if {[dict exists $port fixed]} { - dict set port fixed [shift_point [dict get $port fixed] $x $y] - } elseif {[dict exists $port placed]} { - dict set port placed [shift_point [dict get $port placed] $x $y] - } - lappend ports $port - } - dict set design pins $pin_name ports $ports - } - } - if {[dict exists $design components]} { - dict for {inst_name inst} [dict get $design components] { - if {[dict exists $inst fixed]} { - dict set design components $inst_name fixed [shift_point [dict get $inst fixed] $x $y] - } elseif {[dict exists $inst placed]} { - dict set design components $inst_name placed [shift_point [dict get $inst placed] $x $y] - } - } - } - if {[dict exists $design nets]} { - dict for {net_name net} [dict get $design nets] { - if {[dict exists $net routes]} { - set routes {} - foreach route [dict get $net routes] { - set points {} - foreach point $points { - if {[llength $point] == 2} { - lappend points [shift_point $point $x $y] - } else { - lappend points $point - } - } - lappend routes $route - } - dict set design nets $net_name routes $routes - } - } - } - if {[dict exists $design special_nets]} { - dict for {net_name net} [dict get $design special_nets] { - set routes {} - if {[dict exists $net routes]} { - foreach route [dict get $net routes] { - set points {} - foreach point $points { - if {[llength $point] == 2} { - lappend points [shift_point $point $x $y] - } else { - lappend points $point - } - } - lappend routes $route - } - dict set design special_nets $net_name routes $routes - } - } - } - if {[dict exists $design obstructions]} { - dict for {layer_name obstructions} [dict get $design obstructions] { - set new_obs {} - foreach obs $obstructions { - dict set obs rect [def::shift_rect [dict get $obs rect] $x $y] - lappend new_obs $obs - } - dict set design obstructions $layer_name $new_obs - } - } +proc write_macros { file_name cells } { + lef open $file_name + + out "###############################################################" + out "# Created by cell-veneer" + out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]" + out "###############################################################" + out "" + out "VERSION 5.8 ;" + out "BUSBITCHARS \"\[\]\" ;" + out "DIVIDERCHAR \"/\" ;" + out "" + + dict for {cell_name cell} $cells { + lef write $cell + } + + out "END LIBRARY" + out "" + lef close +} - return $design - } +namespace export read_macros get_width get_height +namespace export get_cell get_cells write write_cells write_macros +namespace export open close out +namespace ensemble create +} - variable layer_info {} - proc set_layer_info {layer_name key value} { - variable layer_info +namespace eval def { +variable def_units +variable defOut stdout +variable designs {} + +# tclint-disable-next-line redefined-builtin +proc open { file_name } { + variable defOut + set defOut [::open $file_name w] +} - dict set layer_info layers $layer_name $key $value - } +# tclint-disable-next-line redefined-builtin +proc close { } { + variable defOut + if { $defOut != "stdout" } { + ::close $defOut + } + set defOut stdout +} - proc get_layer_width {layer_name} { - variable layer_info - return [dict get $layer_info layers $layer_name width] - } +proc out { args } { + variable defOut - proc get_layer_non_preferred_width {layer_name} { - variable layer_info - if {[dict exists $layer_info layers $layer_name non_preferred_width]} { - return [dict get $layer_info layers $layer_name non_preferred_width] - } - return [dict get $layer_info layers $layer_name width] - } + if { [llength $args] == 2 } { + puts [lindex $args 0] $defOut [lindex $args 1] + } else { + puts $defOut [lindex $args 0] + } +} - proc get_layer_direction {layer_name} { - variable layer_info - return [dict get $layer_info layers $layer_name direction] - } +# Write out DEF from a design structure which is a dictionary with the following keys +# - name +# - tool +# - units +# - die_area +# - core_area +# - rows: dict with the index of the row as the key +# - site +# - start +# - height +# - orientation +# - num_sites +# - site_width +# - pins: dict with the name of the pin as the key +# - net_name +# - direction +# - use +# - special +# - ports : a list of dictionaries, one per port +# - orientation +# - (placed|fixed) +# - layers +# - spacing +# - designrulewidth +# - shapes : list of rectangles (or polygons) +# - (rect|polygon) +# - physical_viarules: dict with the name of the viarule as the key +# - rule +# - cutsize +# - layers +# - cutspacing +# - enclosure +# - rowcol +# - components: dict with the instance name of the component as the key +# - inst_name +# - cell_name +# - (fixed|placed)? +# - orientation +# - nets: dict with the name of the net as the key +# - use: SIGNAL | POWER | GROUND +# - connections: list of instance pin pairs +# - routes: list of dictionaries +# - layer +# - points: list of points, where a point can be an XY location or the name of a VIA +# - special_nets: dict with the name of the net as the key +# - use: SIGNAL | POWER | GROUND +# - connections: list of instance pin pairs +# - routes: list of dictioaries +# - layer +# - width +# - shape +# - points: list of points, where a point can be an XY location or the name of a VIA +# + +proc shift_point { point x y } { + return [list [expr [lindex $point 0] + $x] [expr [lindex $point 1] + $y]] +} - proc get_line_direction {points} { - if {[lindex $points 0 0] == [lindex $points 1 0]} { - set direction "VERTICAL" - } elseif {[lindex $points 0 1] == [lindex $points 1 1]} { - set direction "HORIZONTAL" - } else { - error "Non orthogonal line $points" +proc shift_rect { rect x y } { + return [concat \ + [list [expr [lindex $rect 0] + $x] [expr [lindex $rect 1] + $y]] \ + [list [expr [lindex $rect 2] + $x] [expr [lindex $rect 3] + $y]]] +} + +proc shift_origin { design x y } { + if { [dict exists $design die_area] } { + dict set design die_area [shift_rect [dict get $design die_area] $x $y] + } + if { [dict exists $design core_area] } { + dict set design core_area [shift_rect [dict get $design core_area] $x $y] + } + if { [dict exists $design rows] } { + + } + if { [dict exists $design pins] } { + dict for {pin_name pin} [dict get $design pins] { + set ports {} + foreach port [dict get $pin ports] { + if { [dict exists $port fixed] } { + dict set port fixed [shift_point [dict get $port fixed] $x $y] + } elseif { [dict exists $port placed] } { + dict set port placed [shift_point [dict get $port placed] $x $y] + } + lappend ports $port + } + dict set design pins $pin_name ports $ports + } + } + if { [dict exists $design components] } { + dict for {inst_name inst} [dict get $design components] { + if { [dict exists $inst fixed] } { + dict set design components $inst_name fixed [shift_point [dict get $inst fixed] $x $y] + } elseif { [dict exists $inst placed] } { + dict set design components $inst_name placed [shift_point [dict get $inst placed] $x $y] + } + } + } + if { [dict exists $design nets] } { + dict for {net_name net} [dict get $design nets] { + if { [dict exists $net routes] } { + set routes {} + foreach route [dict get $net routes] { + set points {} + foreach point $points { + if { [llength $point] == 2 } { + lappend points [shift_point $point $x $y] + } else { + lappend points $point + } + } + lappend routes $route } - return $direction + dict set design nets $net_name routes $routes + } } - proc get_line_width {layer_name points} { - set direction [get_line_direction $points] - - if {[get_layer_direction $layer_name] == $direction} { - return [get_layer_width $layer_name] - } else { - return [get_layer_non_preferred_width $layer_name] + } + if { [dict exists $design special_nets] } { + dict for {net_name net} [dict get $design special_nets] { + set routes {} + if { [dict exists $net routes] } { + foreach route [dict get $net routes] { + set points {} + foreach point $points { + if { [llength $point] == 2 } { + lappend points [shift_point $point $x $y] + } else { + lappend points $point + } + } + lappend routes $route } + dict set design special_nets $net_name routes $routes + } + } + } + if { [dict exists $design obstructions] } { + dict for {layer_name obstructions} [dict get $design obstructions] { + set new_obs {} + foreach obs $obstructions { + dict set obs rect [def::shift_rect [dict get $obs rect] $x $y] + lappend new_obs $obs + } + dict set design obstructions $layer_name $new_obs } + } - proc get_extended_line {layer_name points} { - if {[llength [lindex $points 1]] == 1} { - return "( [lindex $points 0] ) [lindex $points 1]" - } + return $design +} - set direction [get_line_direction $points] +variable layer_info {} +proc set_layer_info { layer_name key value } { + variable layer_info - if {$direction == [get_layer_direction $layer_name]} { - set extension [expr [get_layer_non_preferred_width $layer_name] / 2] - } else { - set extension [expr [get_layer_width $layer_name] / 2] - } + dict set layer_info layers $layer_name $key $value +} - if {$direction == "VERTICAL"} { - set x_min [lindex $points 0 0] - set x_max [lindex $points 0 0] - set y_min [expr min([lindex $points 0 1], [lindex $points 1 1]) - $extension] - set y_max [expr max([lindex $points 0 1], [lindex $points 1 1]) + $extension] - } else { - set x_min [expr min([lindex $points 0 0], [lindex $points 1 0])] - set x_max [expr max([lindex $points 0 0], [lindex $points 1 0])] - set y_min [lindex $points 0 1] - set y_max [lindex $points 0 1] - } +proc get_layer_width { layer_name } { + variable layer_info + return [dict get $layer_info layers $layer_name width] +} - return "( $x_min $y_min ) ( $x_max $y_max )" - } +proc get_layer_non_preferred_width { layer_name } { + variable layer_info + if { [dict exists $layer_info layers $layer_name non_preferred_width] } { + return [dict get $layer_info layers $layer_name non_preferred_width] + } + return [dict get $layer_info layers $layer_name width] +} - proc write {design} { - out "###############################################################" - if {[dict exists $design tool]} { - out "# Created by [dict get $design tool]" - } - out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]" - out "###############################################################" - - out "VERSION 5.8 ;" - out "DIVIDERCHAR \"/\" ;" - out "BUSBITCHARS \"\[\]\" ;" - out "DESIGN [dict get $design name] ;" - out "UNITS DISTANCE MICRONS [dict get $design units] ;" - out "" +proc get_layer_direction { layer_name } { + variable layer_info + return [dict get $layer_info layers $layer_name direction] +} - if {[dict exists $design properties]} { - out "PROPERTYDEFINITIONS " - if {[dict exists $design properties core_area]} { - out "DESIGN FE_CORE_BOX_LL_X REAL [lindex [dict get $design properties core_area] 0] ;" - out "DESIGN FE_CORE_BOX_UR_X REAL [lindex [dict get $design properties core_area] 1] ;" - out "DESIGN FE_CORE_BOX_LL_Y REAL [lindex [dict get $design properties core_area] 2] ;" - out "DESIGN FE_CORE_BOX_UR_Y REAL [lindex [dict get $design properties core_area] 3] ;" - } - out "END PROPERTYDEFINITIONS" - } +proc get_line_direction { points } { + if { [lindex $points 0 0] == [lindex $points 1 0] } { + set direction "VERTICAL" + } elseif { [lindex $points 0 1] == [lindex $points 1 1] } { + set direction "HORIZONTAL" + } else { + error "Non orthogonal line $points" + } + return $direction +} +proc get_line_width { layer_name points } { + set direction [get_line_direction $points] + + if { [get_layer_direction $layer_name] == $direction } { + return [get_layer_width $layer_name] + } else { + return [get_layer_non_preferred_width $layer_name] + } +} - out "" - out "DIEAREA ( [lrange [dict get $design die_area] 0 1] ) ( [lrange [dict get $design die_area] 2 3] ) ;" +proc get_extended_line { layer_name points } { + if { [llength [lindex $points 1]] == 1 } { + return "( [lindex $points 0] ) [lindex $points 1]" + } + + set direction [get_line_direction $points] + + if { $direction == [get_layer_direction $layer_name] } { + set extension [expr [get_layer_non_preferred_width $layer_name] / 2] + } else { + set extension [expr [get_layer_width $layer_name] / 2] + } + + if { $direction == "VERTICAL" } { + set x_min [lindex $points 0 0] + set x_max [lindex $points 0 0] + set y_min [expr min([lindex $points 0 1], [lindex $points 1 1]) - $extension] + set y_max [expr max([lindex $points 0 1], [lindex $points 1 1]) + $extension] + } else { + set x_min [expr min([lindex $points 0 0], [lindex $points 1 0])] + set x_max [expr max([lindex $points 0 0], [lindex $points 1 0])] + set y_min [lindex $points 0 1] + set y_max [lindex $points 0 1] + } + + return "( $x_min $y_min ) ( $x_max $y_max )" +} - if {[dict exists $design tracks]} { - } - - if {[dict exists $design rows]} { - foreach idx [lsort -integer [dict keys $design rows]] { - out -nonewline "ROW ROW_$idx [dict keys $design rows $idx site] [dict keys $design rows $idx start] [dict keys $design rows $idx height] [dict keys $design rows $idx orientation]" - out " DO [dict keys $design rows $idx num_sites] BY 1 STEP [dict keys $design rows $idx site_width] 0 ;" +proc write { design } { + out "###############################################################" + if { [dict exists $design tool] } { + out "# Created by [dict get $design tool]" + } + out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]" + out "###############################################################" + + out "VERSION 5.8 ;" + out "DIVIDERCHAR \"/\" ;" + out "BUSBITCHARS \"\[\]\" ;" + out "DESIGN [dict get $design name] ;" + out "UNITS DISTANCE MICRONS [dict get $design units] ;" + out "" + + if { [dict exists $design properties] } { + out "PROPERTYDEFINITIONS " + if { [dict exists $design properties core_area] } { + out "DESIGN FE_CORE_BOX_LL_X REAL [lindex [dict get $design properties core_area] 0] ;" + out "DESIGN FE_CORE_BOX_UR_X REAL [lindex [dict get $design properties core_area] 1] ;" + out "DESIGN FE_CORE_BOX_LL_Y REAL [lindex [dict get $design properties core_area] 2] ;" + out "DESIGN FE_CORE_BOX_UR_Y REAL [lindex [dict get $design properties core_area] 3] ;" + } + out "END PROPERTYDEFINITIONS" + } + + out "" + out "DIEAREA ( [lrange [dict get $design die_area] 0 1] )\ + ( [lrange [dict get $design die_area] 2 3] ) ;" + + if { [dict exists $design tracks] } { + + } + + if { [dict exists $design rows] } { + foreach idx [lsort -integer [dict keys $design rows]] { + out -nonewline [concat \ + "ROW ROW_$idx" \ + [dict get $design rows $idx site] \ + [dict get $design rows $idx start] \ + [dict get $design rows $idx height] \ + [dict get $design rows $idx orientation]] + out " DO [dict get $design rows $idx num_sites] BY 1 STEP\ + [dict get $design rows $idx site_width] 0 ;" + } + } + + if { [dict exists $design pins] } { + out "" + out "PINS [dict size [dict get $design pins]] ;" + dict for {pin_name pin} [dict get $design pins] { + out -nonewline \ + "- $pin_name + NET [dict get $pin net_name]\ + + DIRECTION [dict get $pin direction]" + if { [dict exists $pin use] } { + out -nonewline " + USE [dict get $pin use]" + } + if { [dict exists $pin special] } { + out -nonewline " + SPECIAL" + } + out "" + if { [dict exists $pin ports] } { + foreach port [dict get $pin ports] { + if { [llength [dict get $design pins $pin_name ports]] > 1 } { + out " + PORT " + } + dict for {layer_name layer_info} [dict get $port layers] { + foreach shape [dict get $port layers $layer_name shapes] { + out -nonewline " + LAYER $layer_name " + if { [dict exists $port layers $layer_name spacing] } { + out "SPACING [dict get $port layers $layer_name spacing] " + } elseif { [dict exists $port layers $layer_name designrulewidth] } { + out "DESIGNRULEWIDTH [dict get $port layers $layer_name designrulewidth] " + } + out "( [lrange [dict get $shape rect] 0 1] ) ( [lrange [dict get $shape rect] 2 3] ) " } - } - - if {[dict exists $design pins]} { - out "" - out "PINS [dict size [dict get $design pins]] ;" - dict for {pin_name pin} [dict get $design pins] { - out -nonewline "- $pin_name + NET [dict get $pin net_name] + DIRECTION [dict get $pin direction] " - if {[dict exists $pin use]} { - out -nonewline "+ USE [dict get $pin use] " - } - if {[dict exists $pin special]} { - out -nonewline "+ SPECIAL " - } - out "" - if {[dict exists $pin ports]} { - foreach port [dict get $pin ports] { - if {[llength [dict get $design pins $pin_name ports]] > 1} { - out " + PORT " - } - dict for {layer_name layer_info} [dict get $port layers] { - foreach shape [dict get $port layers $layer_name shapes] { - out -nonewline " + LAYER $layer_name " - if {[dict exists $port layers $layer_name spacing]} { - out "SPACING [dict get $port layers $layer_name spacing] " - } elseif {[dict exists $port layers $layer_name designrulewidth]} { - out "DESIGNRULEWIDTH [dict get $port layers $layer_name designrulewidth] " - } - out "( [lrange [dict get $shape rect] 0 1] ) ( [lrange [dict get $shape rect] 2 3] ) " - } - } - if {[dict exists $port fixed]} { - out " + FIXED ( [dict get $port fixed] ) [dict get $port orientation] " - } elseif {[dict exists $shape placed]} { - out " + PLACED ( [dict get $port placed] ) [dict get $port orientation] " - } - } - out " ;" - } + } + if { [dict exists $port fixed] } { + out " + FIXED ( [dict get $port fixed] ) [dict get $port orientation] " + } elseif { [dict exists $shape placed] } { + out " + PLACED ( [dict get $port placed] ) [dict get $port orientation] " + } + } + out " ;" + } + } + out "END PINS" + } + + ##### Generating via rules + + if { [dict exists $design physical_viarules] } { + out "" + out "VIAS [dict size [dict get $design physical_viarules]] ;" + dict for {name rule} [dict get $design physical_viarules] { + out "- $name" + out " + VIARULE [dict get $rule rule]" + out " + CUTSIZE [dict get $rule cutsize]" + out " + LAYERS [dict get $rule layers]" + out " + CUTSPACING [dict get $rule cutspacing]" + out " + ENCLOSURE [dict get $rule enclosure]" + out " + ROWCOL [dict get $rule rowcol]" + out " ;" + } + out "END VIAS" + } + + if { [dict exists $design components] } { + out "" + out "COMPONENTS [dict size [dict get $design components]] ;" + dict for {inst_name inst} [dict get $design components] { + out -nonewline "- $inst_name [dict get $inst cell_name] " + if { [dict exists $inst fixed] } { + out -nonewline "+ FIXED ( [dict get $inst fixed] ) " + } elseif { [dict exists $inst placed] } { + out -nonewline "+ PLACED ( [dict get $inst placed] ) " + } + if { [dict exists $inst orientation] } { + out -nonewline "[dict get $inst orientation] " + } + out ";" + } + out "END COMPONENTS" + } + + if { [dict exists $design nets] } { + out "" + out "SPECIALNETS [dict size [dict get $design nets]] ;" + dict for {net_name net} [dict get $design nets] { + out -nonewline "- $net_name " + foreach connection [dict get $net connections] { + out " ( $connection )" + } + if { [dict exists $net routes] } { + set type "ROUTED" + foreach route [dict get $net routes] { + set first_point [lindex [dict get $route points] 0] + + foreach point [lrange [dict get $route points] 1 end] { + set points [get_extended_line [dict get $route layer] [list $first_point $point]] + if { [dict exists $route shape] } { + set shape " + SHAPE [dict get $route shape] " + } else { + set shape "" } - out "END PINS" - } - - ##### Generating via rules - - if {[dict exists $design physical_viarules]} { - out "" - out "VIAS [dict size [dict get $design physical_viarules]] ;" - dict for {name rule} [dict get $design physical_viarules] { - out "- $name" - out " + VIARULE [dict get $rule rule]" - out " + CUTSIZE [dict get $rule cutsize]" - out " + LAYERS [dict get $rule layers]" - out " + CUTSPACING [dict get $rule cutspacing]" - out " + ENCLOSURE [dict get $rule enclosure]" - out " + ROWCOL [dict get $rule rowcol]" - out " ;" + if { [dict exists $route mask] } { + set mask "MASK [dict get $route mask] " + } else { + set mask "" } - out "END VIAS" - } - - if {[dict exists $design components]} { - out "" - out "COMPONENTS [dict size [dict get $design components]] ;" - dict for {inst_name inst} [dict get $design components] { - out -nonewline "- $inst_name [dict get $inst cell_name] " - if {[dict exists $inst fixed]} { - out -nonewline "+ FIXED ( [dict get $inst fixed] ) " - } elseif {[dict exists $inst placed]} { - out -nonewline "+ PLACED ( [dict get $inst placed] ) " - } - if {[dict exists $inst orientation]} { - out -nonewline "[dict get $inst orientation] " - } - out ";" + if { [llength $point] == 2 } { + out -nonewline \ + " + $type [dict get $route layer]\ + [get_line_width [dict get $route layer] [list $first_point $point]] " + out -nonewline $shape + out -nonewline $points + out -nonewline $mask + } else { + out -nonewline " + $type [dict get $route layer] 0 " + out -nonewline $shape + out -nonewline $points + out -nonewline $mask } - out "END COMPONENTS" - } - - if {[dict exists $design nets]} { out "" - out "SPECIALNETS [dict size [dict get $design nets]] ;" - dict for {net_name net} [dict get $design nets] { - out -nonewline "- $net_name " - foreach connection [dict get $net connections] { - out " ( $connection )" - } - if {[dict exists $net routes]} { - set type "ROUTED" - foreach route [dict get $net routes] { - set first_point [lindex [dict get $route points] 0] - - foreach point [lrange [dict get $route points] 1 end] { - set points [get_extended_line [dict get $route layer] [list $first_point $point]] - if {[dict exists $route shape]} { - set shape " + SHAPE [dict get $route shape] " - } else { - set shape "" - } - if {[dict exists $route mask]} { - set mask "MASK [dict get $route mask] " - } else { - set mask "" - } - if {[llength $point] == 2} { - out -nonewline " + $type [dict get $route layer] [get_line_width [dict get $route layer] [list $first_point $point]] " - out -nonewline $shape - out -nonewline $points - out -nonewline $mask - } else { - out -nonewline " + $type [dict get $route layer] 0 " - out -nonewline $shape - out -nonewline $points - out -nonewline $mask - } - out "" - set first_point $point - set type "ROUTED" - } - } - } - out " + USE [dict get $net use]\n ;" - } - out "END SPECIALNETS" + set first_point $point + set type "ROUTED" + } } - - if {[dict exists $design special_nets]} { - out "" - out "SPECIALNETS [dict size [dict get $design special_nets]] ;" - dict for {net_name net} [dict get $design special_nets] { - out -nonewline "- $net_name " - foreach connection [dict get $net connections] { - out " ( $connection )" - } - if {[dict exists $net routes]} { - set route [lindex [dict get $net routes] 0] - out -nonewline " + ROUTED [dict get $route layer] [expr round([dict get $route width])] + SHAPE [dict get $route shape] " - foreach point [dict get $route points] { - out -nonewline " $point" - } - out "" - - foreach route [lrange [dict get $net routes] 1 end] { - out " NEW [dict get $route layer] [expr round([dict get $route width])] + SHAPE [dict get $route shape] " - foreach point [dict get $route points] { - out -nonewline " $point" - } - out "" - } - } - out " + USE [dict get $net use]\n ;" - } - out "\nEND SPECIALNETS" + } + out " + USE [dict get $net use]\n ;" + } + out "END SPECIALNETS" + } + + if { [dict exists $design special_nets] } { + out "" + out "SPECIALNETS [dict size [dict get $design special_nets]] ;" + dict for {net_name net} [dict get $design special_nets] { + out -nonewline "- $net_name " + foreach connection [dict get $net connections] { + out " ( $connection )" + } + if { [dict exists $net routes] } { + set route [lindex [dict get $net routes] 0] + out -nonewline \ + " + ROUTED [dict get $route layer]\ + [expr round([dict get $route width])]\ + + SHAPE [dict get $route shape] " + foreach point [dict get $route points] { + out -nonewline " $point" } - out "" - out "END DESIGN" + + foreach route [lrange [dict get $net routes] 1 end] { + out \ + " NEW [dict get $route layer] [expr round([dict get $route width])]\ + + SHAPE [dict get $route shape] " + foreach point [dict get $route points] { + out -nonewline " $point" + } + out "" + } + } + out " + USE [dict get $net use]\n ;" } + out "\nEND SPECIALNETS" + } - proc new_design {design_name units {die_area {0 0 0 0}}} { - variable designs - variable current_design - set current_design $design_name + out "" + out "END DESIGN" +} - dict set designs $current_design [list name $design_name units $units die_area $die_area] - } +proc new_design { design_name units { die_area {0 0 0 0} } } { + variable designs + variable current_design + set current_design $design_name - proc add_component {inst_name cell_name x y orientation status} { - variable designs - variable current_design + dict set designs $current_design [list name $design_name units $units die_area $die_area] +} - dict set designs $current_design components $inst_name inst_name $inst_name - dict set designs $current_design components $inst_name cell_name $cell_name - dict set designs $current_design components $inst_name $status [list $x $y] - dict set designs $current_design components $inst_name orientation $orientation - } - - proc get_current_design {} { - variable designs - variable current_design +proc add_component { inst_name cell_name x y orientation status } { + variable designs + variable current_design - return [dict get $designs $current_design] - } - - proc write_cells {cells} { - dict for {cell_name cell} $cells { - def open ${cell_name}.def - def write $cell - def close - } - } - - proc set_def_units {units} { - variable def_units - - set def_units $units - } - - proc get_def_units {} { - variable def_units - - return $def_units - } - - namespace export new_design add_component get_current_design - namespace export set_def_units get_def_units shift_origin shift_rect - namespace export open close out write write_cells - namespace export set_layer_info - namespace ensemble create + dict set designs $current_design components $inst_name inst_name $inst_name + dict set designs $current_design components $inst_name cell_name $cell_name + dict set designs $current_design components $inst_name $status [list $x $y] + dict set designs $current_design components $inst_name orientation $orientation +} + +proc get_current_design { } { + variable designs + variable current_design + + return [dict get $designs $current_design] +} + +proc write_cells { cells } { + dict for {cell_name cell} $cells { + def open ${cell_name}.def + def write $cell + def close + } +} + +proc set_def_units { units } { + variable def_units + + set def_units $units +} + +proc get_def_units { } { + variable def_units + + return $def_units +} + +namespace export new_design add_component get_current_design +namespace export set_def_units get_def_units shift_origin shift_rect +namespace export open close out write write_cells +namespace export set_layer_info +namespace ensemble create } package provide lefdef 1.0.0 diff --git a/flow/util/cell-veneer/pkgIndex.tcl b/flow/util/cell-veneer/pkgIndex.tcl index 806a34f75f..45719f8484 100644 --- a/flow/util/cell-veneer/pkgIndex.tcl +++ b/flow/util/cell-veneer/pkgIndex.tcl @@ -1,3 +1,3 @@ -package ifneeded lefdef 1.0.0 [list source [file join $dir lefdef.tcl]] +# tclint-disable command-args +package ifneeded lefdef 1.0.0 [list source [file join $dir lefdef.tcl]] package ifneeded wrapper 1.0.0 [list source [file join $dir wrap_stdcells.tcl]] - diff --git a/flow/util/cell-veneer/wrap.tcl b/flow/util/cell-veneer/wrap.tcl index 3ca893b8fd..8fa52113ab 100755 --- a/flow/util/cell-veneer/wrap.tcl +++ b/flow/util/cell-veneer/wrap.tcl @@ -5,7 +5,7 @@ exec tclsh "$0" ${1+"$@"} package require wrapper package require lefdef -if {[set idx [lsearch -exact $argv {-cfg}]] > -1} { +if { [set idx [lsearch -exact $argv {-cfg}]] > -1 } { set cfg_file [lindex $argv [expr $idx + 1]] set argv [lreplace $argv $idx [expr $idx + 1]] @@ -15,7 +15,7 @@ if {[set idx [lsearch -exact $argv {-cfg}]] > -1} { wrapper critical 2 "no configuration data loaded" } -if {[lindex $argv 0] == "-macro"} { +if { [lindex $argv 0] == "-macro" } { set lef_files [lrange $argv 1 end] set cells {} foreach file_name $lef_files { diff --git a/flow/util/cell-veneer/wrap_stdcells.tcl b/flow/util/cell-veneer/wrap_stdcells.tcl index f6abb4a674..f6ad587cc6 100644 --- a/flow/util/cell-veneer/wrap_stdcells.tcl +++ b/flow/util/cell-veneer/wrap_stdcells.tcl @@ -1,701 +1,732 @@ namespace eval wrapper { - variable wrapper_cfg - - proc set_message {level message} { - return "\[$level\] $message" - } +variable wrapper_cfg - proc debug {message} { - set state [info frame -1] - set str "" - if {[dict exists $state file]} { - set str "$str[dict get $state file]:" - } - if {[dict exists $state proc]} { - set str "$str[dict get $state proc]:" - } - if {[dict exists $state line]} { - set str "$str[dict get $state line]" - } - puts [set_message DEBUG "$str: $message"] - } +proc set_message { level message } { + return "\[$level\] $message" +} - proc information {id message} { - puts [set_message INFO [format "\[WRAP-%04d\] %s" $id $message]] +proc debug { message } { + set state [info frame -1] + set str "" + if { [dict exists $state file] } { + set str "$str[dict get $state file]:" } - - proc warning {id message} { - puts [set_message WARN [format "\[WRAP-%04d\] %s" $id $message]] + if { [dict exists $state proc] } { + set str "$str[dict get $state proc]:" } - - proc err {id message} { - puts [set_message ERROR [format "\[WRAP-%04d\] %s" $id $message]] + if { [dict exists $state line] } { + set str "$str[dict get $state line]" } + puts [set_message DEBUG "$str: $message"] +} - proc critical {id message} { - error [set_message CRIT [format "\[WRAP-%04d\] %s" $id $message]] - } +proc information { id message } { + puts [set_message INFO [format "\[WRAP-%04d\] %s" $id $message]] +} + +proc warning { id message } { + puts [set_message WARN [format "\[WRAP-%04d\] %s" $id $message]] +} + +proc err { id message } { + puts [set_message ERROR [format "\[WRAP-%04d\] %s" $id $message]] +} + +proc critical { id message } { + error [set_message CRIT [format "\[WRAP-%04d\] %s" $id $message]] +} + +proc find_cells_with_m2_pins { } { + set cells [lef get_cells] + set data {} + + dict for {cell_name cell} $cells { + dict for {pin_name pin} [dict get $cell pins] { + foreach port [dict get $pin ports] { + set offset [wrapper::get_port_offset $port] + set layer_name "M2" + if { [dict exists $port layers $layer_name] } { + foreach shape [dict get $port layers $layer_name shapes] { + set rect [absolute_rectangle [dict get $shape rect] $offset] + set x1 [lindex $rect 0] + set y1 [lindex $rect 1] + set x2 [lindex $rect 2] + set y2 [lindex $rect 3] - proc find_cells_with_m2_pins {} { - set cells [lef get_cells] - set data {} - - dict for {cell_name cell} $cells { - dict for {pin_name pin} [dict get $cell pins] { - foreach port [dict get $pin ports] { - set offset [wrapper::get_port_offset $port] - set layer_name "M2" - if {[dict exists $port layers $layer_name]} { - foreach shape [dict get $port layers $layer_name shapes] { - - set rect [absolute_rectangle [dict get $shape rect] $offset] - set x1 [lindex $rect 0] - set y1 [lindex $rect 1] - set x2 [lindex $rect 2] - set y2 [lindex $rect 3] - - if {[dict exists $data $cell_name pins $pin_name]} { - set pins [dict get $data $cell_name pins $pin_name] - } else { - set pins {} - } - if {round($y2 - $y1) > 64} { - error "cell $cell_name, pin: $pin_name, [expr $y2 - $y1] -> vertical M2 pin: $y2, $y1" - } - lappend pins [list track [expr round(($y2 + $y1) / 2 / 128)] from $x1 to $x2] - dict set data $cell_name pins $pin_name $pins + if { [dict exists $data $cell_name pins $pin_name] } { + set pins [dict get $data $cell_name pins $pin_name] + } else { + set pins {} + } + if { round($y2 - $y1) > 64 } { + error "cell $cell_name, pin: $pin_name, [expr $y2 - $y1] -> vertical M2 pin: $y2, $y1" } + lappend pins [list track [expr round(($y2 + $y1) / 2 / 128)] from $x1 to $x2] + dict set data $cell_name pins $pin_name $pins } } } + } - if {[dict exists $data $cell_name]} { - dict for {layer_name obstructions} [dict get $cell obstructions] { - if {$layer_name == "M2"} { - foreach obs $obstructions { - set rect [dict get $obs rect] - set x1 [lindex $rect 0] - set y1 [lindex $rect 1] - set x2 [lindex $rect 2] - set y2 [lindex $rect 3] - - if {round(($y2 - $y1)) > 64} { - error "cell $cell_name, blockage, [expr $y2 - $y1] -> vertical blockage: $y2, $y1" - } - if {[dict exists $data $cell_name blockages]} { - set blockages [dict get $data $cell_name blockages] - } else { - set blockages {} - } - - lappend blockages [list track [expr round(($y2 + $y1) / 2 / 128)] from $x1 to $x2] - dict set data $cell_name blockages $blockages + if { [dict exists $data $cell_name] } { + dict for {layer_name obstructions} [dict get $cell obstructions] { + if { $layer_name == "M2" } { + foreach obs $obstructions { + set rect [dict get $obs rect] + set x1 [lindex $rect 0] + set y1 [lindex $rect 1] + set x2 [lindex $rect 2] + set y2 [lindex $rect 3] + + if { round(($y2 - $y1)) > 64 } { + error "cell $cell_name, blockage, [expr $y2 - $y1] -> vertical blockage: $y2, $y1" + } + if { [dict exists $data $cell_name blockages] } { + set blockages [dict get $data $cell_name blockages] + } else { + set blockages {} } + + lappend blockages [list track [expr round(($y2 + $y1) / 2 / 128)] from $x1 to $x2] + dict set data $cell_name blockages $blockages } } } } - - return $data } - proc clear_left {physical_pin blockages} { - set track [dict get $physical_pin track] + return $data +} - foreach blockage $blockages { - if {[dict get $blockage track] == $track && [dict get $blockage to] < [dict get $physical_pin from]} { - return 0 - } +proc clear_left { physical_pin blockages } { + set track [dict get $physical_pin track] + + foreach blockage $blockages { + if { + [dict get $blockage track] == $track && + [dict get $blockage to] < [dict get $physical_pin from] + } { + return 0 } - return 1 } + return 1 +} - proc clear_right {physical_pin blockages} { - set track [dict get $physical_pin track] +proc clear_right { physical_pin blockages } { + set track [dict get $physical_pin track] - foreach blockage $blockages { - if {[dict get $blockage track] == $track && [dict get $blockage from] > [dict get $physical_pin to]} { - return 0 - } + foreach blockage $blockages { + if { + [dict get $blockage track] == $track && + [dict get $blockage from] > [dict get $physical_pin to] + } { + return 0 } - return 1 } + return 1 +} - proc create_def_wrapper {cell_name new_cell_name} { - variable tech - set orig_cell [lef get_cell $cell_name] - - set design $orig_cell - - dict set design name $new_cell_name - dict set design tool "cell-veneer" - dict set design units 2000 - dict set design use_sheet_obstructions 0 - if {[dict exists $tech use_sheet_obstructions]} { - dict set design use_sheet_obstructions [dict get $tech use_sheet_obstructions] - } - if {[dict exists $tech blockage_layers]} { - dict set design blockage_layers [dict get $tech blockage_layers] - } - dict set design die_area [dict get $orig_cell die_area] - - dict set design components u0 cell_name $cell_name - dict set design components u0 placed "0 0" - dict set design components u0 orientation "N" - - dict for {pin_name pin} [dict get $orig_cell pins] { - - dict set design pins $pin_name net_name $pin_name - if {[dict exists $pin use]} { - if {[dict get $pin use] == "POWER" || [dict get $pin use] == "GROUND"} { - dict set design special_nets $pin_name connections [list "PIN $pin_name" "* $pin_name"] - dict set design special_nets $pin_name use [dict get $pin use] - } else { - dict set design nets $pin_name connections [list "PIN $pin_name" "u0 $pin_name"] - dict set design nets $pin_name use [dict get $pin use] - } +proc create_def_wrapper { cell_name new_cell_name } { + variable tech + set orig_cell [lef get_cell $cell_name] + + set design $orig_cell + + dict set design name $new_cell_name + dict set design tool "cell-veneer" + dict set design units 2000 + dict set design use_sheet_obstructions 0 + if { [dict exists $tech use_sheet_obstructions] } { + dict set design use_sheet_obstructions [dict get $tech use_sheet_obstructions] + } + if { [dict exists $tech blockage_layers] } { + dict set design blockage_layers [dict get $tech blockage_layers] + } + dict set design die_area [dict get $orig_cell die_area] + + dict set design components u0 cell_name $cell_name + dict set design components u0 placed "0 0" + dict set design components u0 orientation "N" + + dict for {pin_name pin} [dict get $orig_cell pins] { + dict set design pins $pin_name net_name $pin_name + if { [dict exists $pin use] } { + if { [dict get $pin use] == "POWER" || [dict get $pin use] == "GROUND" } { + dict set design special_nets $pin_name connections [list "PIN $pin_name" "* $pin_name"] + dict set design special_nets $pin_name use [dict get $pin use] } else { dict set design nets $pin_name connections [list "PIN $pin_name" "u0 $pin_name"] + dict set design nets $pin_name use [dict get $pin use] } + } else { + dict set design nets $pin_name connections [list "PIN $pin_name" "u0 $pin_name"] } - - return $design } - - proc get_port_offset {port} { - if {[dict exists $port fixed]} { - return [dict get $port fixed] - } elseif {[dict exists $port placed]} { - return [dict get $port fixed] - } - return [list 0 0] + return $design +} + +proc get_port_offset { port } { + if { [dict exists $port fixed] } { + return [dict get $port fixed] + } elseif { [dict exists $port placed] } { + return [dict get $port fixed] } - proc move_m2_pins_to_edge {cell_name cell_data} { - variable wrapper_cfg - - set wrapper_cell [lef get_cell [dict get $wrapper_cfg padding_cell]] - set padding_cell_width [lindex [dict get $wrapper_cell die_area] 2] - set def_units [dict get $wrapper_cfg def_units] - set layer_name [dict get $wrapper_cfg remove_pins layer] - set layer_width [expr round([dict get $wrapper_cfg layer $layer_name width] * $def_units)] - set new_pin_layer_name [dict get $wrapper_cfg new_pins layer] - set new_pin_layer_width [expr round([dict get $wrapper_cfg layer $new_pin_layer_name width] * $def_units)] - set cell_width [lindex [dict get [lef get_cell $cell_name] die_area] 2] - set design [wrapper::create_def_wrapper $cell_name ${cell_name}_mod] - set lower_y [expr 2 * 128] - set upper_y [expr 8 * 128] - set via_overlap [expr round([dict get $wrapper_cfg via_overlap] * $def_units)] - - set right_padding 0 - set left_padding 0 - - # Determine which sides to route the M2 pins to and create a wire - dict for {pin_name pin} [dict get $cell_data pins] { - set wires {} - foreach physical_pin $pin { - if {[dict get $physical_pin to] >= [expr $cell_width / 2.0]} { - if {[dict exists $cell_data blockages]} { - if {[wrapper::clear_right $physical_pin [dict get $cell_data blockages]]} { - set direction right - } elseif {[wrapper::clear_left $physical_pin [dict get $cell_data blockages]]} { - set direction left - } else { - set direction blocked - } - } else { + return [list 0 0] +} + +proc move_m2_pins_to_edge { cell_name cell_data } { + variable wrapper_cfg + + set wrapper_cell [lef get_cell [dict get $wrapper_cfg padding_cell]] + set padding_cell_width [lindex [dict get $wrapper_cell die_area] 2] + set def_units [dict get $wrapper_cfg def_units] + set layer_name [dict get $wrapper_cfg remove_pins layer] + set layer_width [expr round([dict get $wrapper_cfg layer $layer_name width] * $def_units)] + set new_pin_layer_name [dict get $wrapper_cfg new_pins layer] + set new_pin_layer_width [expr round( \ + [dict get $wrapper_cfg layer $new_pin_layer_name width] * \ + $def_units \ + )] + set cell_width [lindex [dict get [lef get_cell $cell_name] die_area] 2] + set design [wrapper::create_def_wrapper $cell_name ${cell_name}_mod] + set lower_y [expr 2 * 128] + set upper_y [expr 8 * 128] + set via_overlap [expr round([dict get $wrapper_cfg via_overlap] * $def_units)] + + set right_padding 0 + set left_padding 0 + + # Determine which sides to route the M2 pins to and create a wire + dict for {pin_name pin} [dict get $cell_data pins] { + set wires {} + foreach physical_pin $pin { + if { [dict get $physical_pin to] >= ($cell_width / 2.0) } { + if { [dict exists $cell_data blockages] } { + if { [wrapper::clear_right $physical_pin [dict get $cell_data blockages]] } { set direction right + } elseif { [wrapper::clear_left $physical_pin [dict get $cell_data blockages]] } { + set direction left + } else { + set direction blocked } } else { - if {[dict exists $cell_data blockages]} { - if {[wrapper::clear_left $physical_pin [dict get $cell_data blockages]]} { - set direction left - } elseif {[wrapper::clear_right $physical_pin [dict get $cell_data blockages]]} { - set direction right - } else { - set direction blocked - } - } else { + set direction right + } + } else { + if { [dict exists $cell_data blockages] } { + if { [wrapper::clear_left $physical_pin [dict get $cell_data blockages]] } { set direction left + } elseif { [wrapper::clear_right $physical_pin [dict get $cell_data blockages]] } { + set direction right + } else { + set direction blocked } - } - - if {$direction == "blocked"} { - break - } - - set y [expr [dict get $physical_pin track] * 128] - if {$direction == "right"} { - set x1 [dict get $physical_pin to] - set x2 [expr $cell_width + ($padding_cell_width * ($right_padding + 1))] - set x3 [expr $cell_width + ($padding_cell_width * ($right_padding + 1)) + $via_overlap] - incr right_padding - } elseif {$direction == "left"} { - set x1 [dict get $physical_pin from] - set x2 [expr 0 - ($padding_cell_width * ($left_padding + 1))] - set x3 [expr 0 - ($padding_cell_width * ($left_padding + 1)) - $via_overlap] - incr left_padding - } - - # Route M2 out to the side of the block - lappend wires [list \ - layer $layer_name \ - points [list [list $x1 $y] [list $x3 $y] [dict get $wrapper_cfg via]] - ] - set new_wire [list \ - layer "M1" \ - points [list [list $x2 $lower_y] [list $x2 $upper_y]] \ - ] - if {[dict exists $wrapper_cfg new_pins mask]} { - dict set new_wire mask [dict get $wrapper_cfg new_pins mask] - } - lappend wires $new_wire - # Add the new M2 wire as an obstruction when writing the LEF of the cell - if {[dict exists $design obstructions $layer_name]} { - set obstructions [dict get $design obstructions $layer_name] } else { - set obstructions {} + set direction left } - lappend obstructions [list \ - rect [list \ - [expr min($x1, $x3)] [expr $y - round($layer_width / 2)] \ - [expr max($x1, $x3)] [expr $y + round($layer_width / 2)] \ - ] - ] - dict set design obstructions $layer_name $obstructions + } + if { $direction == "blocked" } { break } - if {$direction == "blocked"} { - break + set y [expr [dict get $physical_pin track] * 128] + if { $direction == "right" } { + set x1 [dict get $physical_pin to] + set x2 [expr $cell_width + ($padding_cell_width * ($right_padding + 1))] + set x3 [expr $cell_width + ($padding_cell_width * ($right_padding + 1)) + $via_overlap] + incr right_padding + } elseif { $direction == "left" } { + set x1 [dict get $physical_pin from] + set x2 [expr 0 - ($padding_cell_width * ($left_padding + 1))] + set x3 [expr 0 - ($padding_cell_width * ($left_padding + 1)) - $via_overlap] + incr left_padding } - set ports {} - foreach port [dict get $design pins $pin_name ports] { - if {[dict exists $port layers "M2"]} { - set offset [get_port_offset $port] - # Copy all M2 pins on instance to M2 obstructions - foreach shape [dict get $port layers "M2" shapes] { - set pin_rect [absolute_rectangle [dict get $shape rect] $offset] - - set m2_obstructions [dict get $design obstructions M2] - lappend m2_obstructions [list \ - rect $pin_rect \ - ] - dict set design obstructions M2 $m2_obstructions - } - # Replace the M2 port with an M1 port which is now at the side of the cells - set new_pin_rect [list [expr round($x2 - ($new_pin_layer_width / 2))] $lower_y [expr round($x2 + ($new_pin_layer_width / 2))] $upper_y] - if {[dict exists $port layers "M1" shapes]} { - set shapes [dict get $port layers "M1" shapes] - } else { - set shapes {} - } - set new_shape [list \ - rect [relative_rectangle $new_pin_rect $offset] \ - ] - if {[dict exists $wrapper_cfg new_pins mask]} { - dict set new_shape mask [dict get $wrapper_cfg new_pins mask] - } - lappend shapes $new_shape - dict set port layers M1 shapes $shapes - } - dict set port layers [dict remove [dict get $port layers] "M2"] - lappend ports $port + # Route M2 out to the side of the block + lappend wires [list \ + layer $layer_name \ + points [list [list $x1 $y] [list $x3 $y] [dict get $wrapper_cfg via]]] + set new_wire [list \ + layer "M1" \ + points [list [list $x2 $lower_y] [list $x2 $upper_y]]] + if { [dict exists $wrapper_cfg new_pins mask] } { + dict set new_wire mask [dict get $wrapper_cfg new_pins mask] } - dict set design pins $pin_name ports $ports - dict set design nets $pin_name routes $wires + lappend wires $new_wire + # Add the new M2 wire as an obstruction when writing the LEF of the cell + if { [dict exists $design obstructions $layer_name] } { + set obstructions [dict get $design obstructions $layer_name] + } else { + set obstructions {} + } + lappend obstructions [list \ + rect [list \ + [expr min($x1, $x3)] [expr $y - round($layer_width / 2)] \ + [expr max($x1, $x3)] [expr $y + round($layer_width / 2)]]] + dict set design obstructions $layer_name $obstructions + + break } - # Adjust the placement of the component if we have padding on the left - if {$left_padding > 0} { - dict set design components u0 placed [list [expr $padding_cell_width * ($left_padding + 1)] 0] + if { $direction == "blocked" } { + break } - # Add in the cell padding - set pad_idx 0 - if {$left_padding > 0} { - for {set i 0} {$i <= $left_padding} {incr i} { - set x [expr $padding_cell_width * ($i + 1) * -1] - set y 0 - dict set design components p$pad_idx inst_name p$pad_idx - dict set design components p$pad_idx cell_name [dict get $wrapper_cfg padding_cell] - dict set design components p$pad_idx placed [list $x $y] - dict set design components p$pad_idx orientation N - - # Add all obstructions of padding cell to obstructions of wrapper - dict for {layer_name obstructions} [dict get $wrapper_cell obstructions] { - if {[dict exists $design obstructions $layer_name]} { - set current_obstructions [dict get $design obstructions $layer_name] - } else { - set current_obstructions {} - } - foreach obs $obstructions { - dict set obs rect [def shift_rect [dict get $obs rect] $x $y] - lappend current_obstructions $obs - } - dict set design obstructions $layer_name $current_obstructions + set ports {} + foreach port [dict get $design pins $pin_name ports] { + if { [dict exists $port layers "M2"] } { + set offset [get_port_offset $port] + # Copy all M2 pins on instance to M2 obstructions + foreach shape [dict get $port layers "M2" shapes] { + set pin_rect [absolute_rectangle [dict get $shape rect] $offset] + + set m2_obstructions [dict get $design obstructions M2] + lappend m2_obstructions [list \ + rect $pin_rect] + dict set design obstructions M2 $m2_obstructions + } + # Replace the M2 port with an M1 port which is now at the side of the cells + set new_pin_rect [concat \ + [list \ + [expr round($x2 - ($new_pin_layer_width / 2))] \ + $lower_y \ + [expr round($x2 + ($new_pin_layer_width / 2))] \ + $upper_y]] + if { [dict exists $port layers "M1" shapes] } { + set shapes [dict get $port layers "M1" shapes] + } else { + set shapes {} + } + set new_shape [list \ + rect [relative_rectangle $new_pin_rect $offset]] + if { [dict exists $wrapper_cfg new_pins mask] } { + dict set new_shape mask [dict get $wrapper_cfg new_pins mask] } - incr pad_idx + lappend shapes $new_shape + dict set port layers M1 shapes $shapes } - } else { - set left_padding -1 + dict set port layers [dict remove [dict get $port layers] "M2"] + lappend ports $port } - if {$right_padding > 0} { - for {set i 0} {$i <= $right_padding} {incr i} { - set x [expr $padding_cell_width * $i + $cell_width] - set y 0 - dict set design components p$pad_idx inst_name p$pad_idx - dict set design components p$pad_idx cell_name [dict get $wrapper_cfg padding_cell] - dict set design components p$pad_idx placed [list $x $y] - dict set design components p$pad_idx orientation N - - # Add all obstructions of padding cell to obstructions of wrapper - dict for {layer_name obstructions} [dict get $wrapper_cell obstructions] { - if {[dict exists $design obstructions $layer_name]} { - set current_obstructions [dict get $design obstructions $layer_name] - } else { - set current_obstructions {} - } - foreach obs $obstructions { - dict set obs rect [def shift_rect [dict get $obs rect] $x $y] - lappend current_obstructions $obs - } - dict set design obstructions $layer_name $current_obstructions + dict set design pins $pin_name ports $ports + dict set design nets $pin_name routes $wires + } + + # Adjust the placement of the component if we have padding on the left + if { $left_padding > 0 } { + dict set design components u0 placed [list [expr $padding_cell_width * ($left_padding + 1)] 0] + } + + # Add in the cell padding + set pad_idx 0 + if { $left_padding > 0 } { + for { set i 0 } { $i <= $left_padding } { incr i } { + set x [expr $padding_cell_width * ($i + 1) * -1] + set y 0 + dict set design components p$pad_idx inst_name p$pad_idx + dict set design components p$pad_idx cell_name [dict get $wrapper_cfg padding_cell] + dict set design components p$pad_idx placed [list $x $y] + dict set design components p$pad_idx orientation N + + # Add all obstructions of padding cell to obstructions of wrapper + dict for {layer_name obstructions} [dict get $wrapper_cell obstructions] { + if { [dict exists $design obstructions $layer_name] } { + set current_obstructions [dict get $design obstructions $layer_name] + } else { + set current_obstructions {} + } + foreach obs $obstructions { + dict set obs rect [def shift_rect [dict get $obs rect] $x $y] + lappend current_obstructions $obs } - incr pad_idx + dict set design obstructions $layer_name $current_obstructions } + incr pad_idx } + } else { + set left_padding -1 + } + if { $right_padding > 0 } { + for { set i 0 } { $i <= $right_padding } { incr i } { + set x [expr $padding_cell_width * $i + $cell_width] + set y 0 + dict set design components p$pad_idx inst_name p$pad_idx + dict set design components p$pad_idx cell_name [dict get $wrapper_cfg padding_cell] + dict set design components p$pad_idx placed [list $x $y] + dict set design components p$pad_idx orientation N + + # Add all obstructions of padding cell to obstructions of wrapper + dict for {layer_name obstructions} [dict get $wrapper_cell obstructions] { + if { [dict exists $design obstructions $layer_name] } { + set current_obstructions [dict get $design obstructions $layer_name] + } else { + set current_obstructions {} + } + foreach obs $obstructions { + dict set obs rect [def shift_rect [dict get $obs rect] $x $y] + lappend current_obstructions $obs + } + dict set design obstructions $layer_name $current_obstructions + } + incr pad_idx + } + } - # Adjust origin so that 0,0 is the lowr left corner of the cell - set adjustment [expr $padding_cell_width * ($left_padding + 1)] - set design [def shift_origin $design $adjustment 0] - - dict set design die_area [list \ - 0 \ - 0 \ - [expr [lindex [dict get $design die_area] 2] + (($pad_idx - ($left_padding + 1)) * $padding_cell_width)] \ - [lindex [dict get $design die_area] 3] \ - ] - - # Extend VDD, VSS, VPW, VNW pins to be the width of the wrapper - # VDD overlaps by 0.009 on each side - # VSS overlaps by 0.009 on each side - # VNW overlaps the edges of the cell by 0.1 on both sides - set extend_ports { + # Adjust origin so that 0,0 is the lowr left corner of the cell + set adjustment [expr $padding_cell_width * ($left_padding + 1)] + set design [def shift_origin $design $adjustment 0] + + dict set design die_area [list \ + 0 \ + 0 \ + [concat \ + [expr [lindex [dict get $design die_area] 2] + \ + (($pad_idx - ($left_padding + 1)) * $padding_cell_width)]] \ + [lindex [dict get $design die_area] 3]] + + # Extend VDD, VSS, VPW, VNW pins to be the width of the wrapper + # VDD overlaps by 0.009 on each side + # VSS overlaps by 0.009 on each side + # VNW overlaps the edges of the cell by 0.1 on both sides + set extend_ports { VDD {layer M1 overlap 0.009} VSS {layer M1 overlap 0.009} VNW {layer NW overlap 0.1} VPW {layer SXCUT overlap 0} } - dict for {pin_name info} $extend_ports { - set layer [dict get $info layer] - set overlap [dict get $info overlap] - - set ports {} - foreach port [dict get $design pins $pin_name ports] { - if {[dict exists $port layers $layer]} { - set shapes {} - set offset [get_port_offset $port] - - foreach shape [dict get $port layers $layer shapes] { - set rect [absolute_rectangle [dict get $shape rect] $offset] - dict set shape rect [relative_rectangle \ - [list \ - [expr [lindex [dict get $design die_area] 0] - [expr round($overlap * $def_units)]] \ - [lindex $rect 1] \ - [expr [lindex [dict get $design die_area] 2] + [expr round($overlap * $def_units)]] \ - [lindex $rect 3] \ - ] \ - $offset \ - ] - lappend shapes $shape - } - dict set port layers $layer shapes $shapes + dict for {pin_name info} $extend_ports { + set layer [dict get $info layer] + set overlap [dict get $info overlap] + + set ports {} + foreach port [dict get $design pins $pin_name ports] { + if { [dict exists $port layers $layer] } { + set shapes {} + set offset [get_port_offset $port] + + foreach shape [dict get $port layers $layer shapes] { + set rect [absolute_rectangle [dict get $shape rect] $offset] + dict set shape rect [relative_rectangle \ + [list \ + [expr [lindex [dict get $design die_area] 0] - [expr round($overlap * $def_units)]] \ + [lindex $rect 1] \ + [expr [lindex [dict get $design die_area] 2] + [expr round($overlap * $def_units)]] \ + [lindex $rect 3]] \ + $offset] + lappend shapes $shape } - lappend ports $port + dict set port layers $layer shapes $shapes } - dict set design pins $pin_name ports $ports + lappend ports $port } - - return $design + dict set design pins $pin_name ports $ports } - proc build_wrappers {data} { - variable wrapper_cfg - - set designs {} + return $design +} - dict for {cell_name cell_data} $data { - set data [move_m2_pins_to_edge $cell_name $cell_data $wrapper_cfg] - dict set designs [dict get $data name] $data - } +proc build_wrappers { data } { + variable wrapper_cfg + + set designs {} - return $designs + dict for {cell_name cell_data} $data { + set data [move_m2_pins_to_edge $cell_name $cell_data $wrapper_cfg] + dict set designs [dict get $data name] $data } - proc get_pin_rect {port layer} { - if {[dict exists $port fixed]} { - set offset [dict get $port fixed] - } elseif {[dict exists $port placed]} { - set offset [dict get $port placed] - } else { - set offset [list 0 0] - } - - return [absolute_rectangle [dict get [lindex [dict get $port layers $layer shapes] 0] rect] $offset] + return $designs +} + +proc get_pin_rect { port layer } { + if { [dict exists $port fixed] } { + set offset [dict get $port fixed] + } elseif { [dict exists $port placed] } { + set offset [dict get $port placed] + } else { + set offset [list 0 0] } - - proc wrap_macro {cell_name} { - variable tech - set wrapper [wrapper::create_def_wrapper $cell_name ${cell_name}_mod] - debug "$tech" - debug "[dict get $wrapper use_sheet_obstructions]" - - set cell [lef get_cell $cell_name] - # debug "$cell_name" - - # Order the signal pins based on the y location of the pin - set pin_info {} - set net_info {} - set grid_pins {} - dict for {pin_name pin} [dict get $cell pins] { - if {[dict get $pin use] != "SIGNAL"} {continue} - - # CHEAT: Assume that there is only one port for each pin and one rectangle per layer - set port [lindex [dict get $pin ports] 0] - if {[dict exists $port layers C4]} { - set pin_rect [get_pin_rect $port C4] - dict set net_info $pin_name pin_layer "C4" - } elseif {[dict exists $port layers M3]} { - set pin_rect [get_pin_rect $port M3] - dict set net_info $pin_name pin_layer "M3" - } + return [absolute_rectangle \ + [dict get \ + [lindex \ + [dict get $port layers $layer shapes] 0] rect] $offset] +} - set macro_pin_y [expr ([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2] - set grid_y [expr round((floor(([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2 / [dict get $tech pitch horizontal_track]) - 1))] +proc wrap_macro { cell_name } { + variable tech + set wrapper [wrapper::create_def_wrapper $cell_name ${cell_name}_mod] + debug "$tech" + debug "[dict get $wrapper use_sheet_obstructions]" + + set cell [lef get_cell $cell_name] + # debug "$cell_name" + + # Order the signal pins based on the y location of the pin + set pin_info {} + set net_info {} + set grid_pins {} + + dict for {pin_name pin} [dict get $cell pins] { + if { [dict get $pin use] != "SIGNAL" } { continue } + + # CHEAT: Assume that there is only one port for each pin and one rectangle per layer + set port [lindex [dict get $pin ports] 0] + if { [dict exists $port layers C4] } { + set pin_rect [get_pin_rect $port C4] + dict set net_info $pin_name pin_layer "C4" + } elseif { [dict exists $port layers M3] } { + set pin_rect [get_pin_rect $port M3] + dict set net_info $pin_name pin_layer "M3" + } - # Need to check that the grid point we're trying to use is going to be accessible. - # If it is not, then try the point 2 grid points higher - if {[dict exists $grid_pins $grid_y]} { - if {[dict exists [expr $grid_y + 2]]} { - puts "Cell $cell_name" - puts "Problem assigning pin grid - requested and upper grid points for $pin_name at $grid_y already allocated to [dict get $grid_pins $grid_y] and [dict get $grid_pins [expr $grid_y + 2]]" - exit -1 - } - set grid_y [expr $grid_y + 2] + set macro_pin_y [expr ([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2] + set grid_y [expr round((floor( \ + ([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2 / \ + [dict get $tech pitch horizontal_track]) - 1))] + + # Need to check that the grid point we're trying to use is going to be accessible. + # If it is not, then try the point 2 grid points higher + if { [dict exists $grid_pins $grid_y] } { + if { [dict exists $grid_pins [expr $grid_y + 2]] } { + puts "Cell $cell_name" + puts [concat "Problem assigning pin grid - requested and upper grid points " \ + "for $pin_name at " \ + "$grid_y already allocated to [dict get $grid_pins $grid_y] and " \ + "[dict get $grid_pins [expr $grid_y + 2]]"] + exit -1 } - dict set grid_pins $grid_y $pin_name - - dict set net_info $pin_name grid_y $grid_y - dict set net_info $pin_name macro_pin_y $macro_pin_y + set grid_y [expr $grid_y + 2] } + dict set grid_pins $grid_y $pin_name - set order [lsort -integer [dict keys $grid_pins]] - set prev_pos [lindex $order 0] + dict set net_info $pin_name grid_y $grid_y + dict set net_info $pin_name macro_pin_y $macro_pin_y + } - # We will have a jog in the track, which needs to be on a vertical grid 3 units from the edge of the macro - # If there is another pin close by, the we will need to have the jog 3 grids further in - dict set net_info [dict get $grid_pins $prev_pos] h_offset 3 - foreach pin_pos [lrange $order 1 end] { - if {$pin_pos - $prev_pos > 3} { - dict set net_info [dict get $grid_pins $pin_pos] h_offset 3 - } else { - dict set net_info [dict get $grid_pins $pin_pos] h_offset [expr [dict get $net_info [dict get $grid_pins $prev_pos] h_offset] + 3] - } - set prev_pos $pin_pos + set order [lsort -integer [dict keys $grid_pins]] + set prev_pos [lindex $order 0] + + # tclint-disable-next-line line-length + # We will have a jog in the track, which needs to be on a vertical grid 3 units from the edge of the macro + # If there is another pin close by, the we will need to have the jog 3 grids further in + dict set net_info [dict get $grid_pins $prev_pos] h_offset 3 + foreach pin_pos [lrange $order 1 end] { + if { $pin_pos - $prev_pos > 3 } { + dict set net_info [dict get $grid_pins $pin_pos] h_offset 3 + } else { + dict set net_info [dict get $grid_pins $pin_pos] h_offset \ + [expr \ + [dict get $net_info [dict get $grid_pins $prev_pos] h_offset] \ + + 3] } + set prev_pos $pin_pos + } - # Work out where to place the instance based on the size of amount of jogging space needed - set wrapper_depth 0 - dict for {net_name net} [dict get $net_info] { - if {$wrapper_depth < [dict get $net h_offset]} { - set wrapper_depth [dict get $net h_offset] - } + # Work out where to place the instance based on the size of amount of jogging space needed + set wrapper_depth 0 + dict for {net_name net} [dict get $net_info] { + if { $wrapper_depth < [dict get $net h_offset] } { + set wrapper_depth [dict get $net h_offset] } - set wrapper_depth [expr $wrapper_depth + 3] - set macro_x [expr $wrapper_depth * [dict get $tech pitch vertical_track]] - set width [expr round((floor([lef get_width $cell] / [dict get $tech pitch vertical_track]) + 1) * [dict get $tech pitch vertical_track] )] - set height [expr round((floor([lef get_height $cell] / [dict get $tech pitch horizontal_track]) + 1) * [dict get $tech pitch horizontal_track])] - - # Now we know where the macro is placed, we know the size of the wrapper - dict set wrapper die_area [list [expr round(-1 * $macro_x)] 0 [expr $width] $height] - # debug "Set die area [dict get $wrapper die_area]" - # Now we know the maximum extent of the space needed for the job we can add in the pins the appropriate number of grids to the left of the RAM - - # Shift the wrapper so the lower left corner is at (0, 0) - set wrapper [def shift_origin $wrapper $macro_x 0] - # debug "Shifted die area [dict get $wrapper die_area]" - - # Add obstructions - foreach obs_layer {M3 J3 C4} { - set obstructions {} - if {[dict exists $wrapper obstructions $obs_layer]} { - set obstructions [dict get $wrapper obstructions $obs_layer] - } - # debug "[lindex [dict get $wrapper obstructions $obs_layer] 0]" - lappend obstructions [list rect [list 0 0 $macro_x $height]] - # debug "[lindex $obstructions 0]" - dict set wrapper obstructions $obs_layer $obstructions - # debug "Added wrapper obstruction [list 0 0 [expr $width + $macro_x] $height]" + } + set wrapper_depth [expr $wrapper_depth + 3] + set macro_x [expr $wrapper_depth * [dict get $tech pitch vertical_track]] + set width [expr round((floor([lef get_width $cell] / \ + [dict get $tech pitch vertical_track]) + 1) * \ + [dict get $tech pitch vertical_track])] + set height [expr round((floor([lef get_height $cell] / \ + [dict get $tech pitch horizontal_track]) + 1) * \ + [dict get $tech pitch horizontal_track])] + + # Now we know where the macro is placed, we know the size of the wrapper + dict set wrapper die_area [list [expr round(-1 * $macro_x)] 0 [expr $width] $height] + # debug "Set die area [dict get $wrapper die_area]" + + # tclint-disable-next-line line-length + # Now we know the maximum extent of the space needed for the job we can add in the pins the appropriate number of grids to the left of the RAM + + # Shift the wrapper so the lower left corner is at (0, 0) + set wrapper [def shift_origin $wrapper $macro_x 0] + # debug "Shifted die area [dict get $wrapper die_area]" + + # Add obstructions + foreach obs_layer {M3 J3 C4} { + set obstructions {} + if { [dict exists $wrapper obstructions $obs_layer] } { + set obstructions [dict get $wrapper obstructions $obs_layer] } - - - # Add wrapper pins and nets - dict for {net_name net} [dict get $net_info] { - set grid_y [dict get $net grid_y] - set y_position [expr $grid_y * [dict get $tech pitch horizontal_track]] - - set new_port [lindex [dict get $wrapper pins $net_name ports] 0] - dict set new_port layers {} - dict set new_port fixed [list 0 $y_position] - dict set new_port layers "C4" shapes [list \ - [list rect [list 0 [expr 0 - [dict get $tech layer C4 width] / 2] [dict get $tech layer C4 depth] [expr 0 + [dict get $tech layer C4 width] / 2]]] \ - ] - # debug "Replacing pin $net_name with $new_port" - dict set wrapper pins $net_name ports [list $new_port] - - set segments {} - - # First segment from RAM to jog location, to the y grid of the pin - set target_grid_point [expr ($wrapper_depth - [dict get $net h_offset]) * [dict get $tech pitch vertical_track]] - set width [dict get $tech layer [dict get $net pin_layer] width] + # debug "[lindex [dict get $wrapper obstructions $obs_layer] 0]" + lappend obstructions [list rect [list 0 0 $macro_x $height]] + # debug "[lindex $obstructions 0]" + dict set wrapper obstructions $obs_layer $obstructions + # debug "Added wrapper obstruction [list 0 0 [expr $width + $macro_x] $height]" + } + + + # Add wrapper pins and nets + dict for {net_name net} [dict get $net_info] { + set grid_y [dict get $net grid_y] + set y_position [expr $grid_y * [dict get $tech pitch horizontal_track]] + + set new_port [lindex [dict get $wrapper pins $net_name ports] 0] + dict set new_port layers {} + dict set new_port fixed [list 0 $y_position] + dict set new_port layers "C4" shapes [list \ + [list rect [concat \ + [list 0 \ + [expr 0 - [dict get $tech layer C4 width] / 2] \ + [dict get $tech layer C4 depth] \ + [expr 0 + [dict get $tech layer C4 width] / 2]]]]] + # debug "Replacing pin $net_name with $new_port" + dict set wrapper pins $net_name ports [list $new_port] + + set segments {} + + # First segment from RAM to jog location, to the y grid of the pin + set target_grid_point [expr \ + ($wrapper_depth - [dict get $net h_offset]) * \ + [dict get $tech pitch vertical_track]] + set width [dict get $tech layer [dict get $net pin_layer] width] + lappend segments [list \ + layer [dict get $net pin_layer] \ + points [list \ + "$macro_x [dict get $net macro_pin_y]" \ + "$target_grid_point [dict get $net macro_pin_y]" \ + "$target_grid_point $y_position"]] + if { [dict get $net pin_layer] != "C4" } { lappend segments [list \ layer [dict get $net pin_layer] \ - points [list \ - "$macro_x [dict get $net macro_pin_y]" \ - "$target_grid_point [dict get $net macro_pin_y]" \ - "$target_grid_point $y_position" \ - ] - ] - if {[dict get $net pin_layer] != "C4"} { - lappend segments [list \ - layer [dict get $net pin_layer] \ - points [list \ - "$target_grid_point $y_position" \ - [dict get $tech via] \ - ] \ - ] - } - lappend segments [list \ - layer C4 \ points [list \ "$target_grid_point $y_position" \ - "0 $y_position" \ - ] \ - ] - - dict set wrapper nets $net_name routes $segments + [dict get $tech via]]] } + lappend segments [list \ + layer C4 \ + points [list \ + "$target_grid_point $y_position" \ + "0 $y_position"]] - return $wrapper + dict set wrapper nets $net_name routes $segments } - proc test_harness {wrappers} { - variable wrapper_cfg - - set site_height [expr [dict get $wrapper_cfg site height] * [dict get $wrapper_cfg def_units]] - set site_width [expr [dict get $wrapper_cfg site width] * [dict get $wrapper_cfg def_units]] - set idx 0 - set num_cells [dict size $wrappers] - set num_grids [expr round(sqrt($num_cells)) + 1] - set max_cell_width 0 - dict for {cell_name cell} $wrappers { - set max_cell_width [expr max($max_cell_width,[lindex [dict get $cell die_area] 2])] - } - set grid_x_size [expr $max_cell_width + (2 * $site_width)] - set grid_y_size [expr 4 * $site_height] + return $wrapper +} - def new_design "test_harness" [dict get $wrapper_cfg def_units] [list 0 0 [expr round($grid_x_size * $num_grids)] [expr round($grid_y_size * $num_grids)]] +proc test_harness { wrappers } { + variable wrapper_cfg - foreach cell [dict keys $wrappers] { - set x [expr round(($idx % $num_grids) * $grid_x_size)] - set y [expr round(round($idx / $num_grids) * $grid_y_size)] + set site_height [expr [dict get $wrapper_cfg site height] * [dict get $wrapper_cfg def_units]] + set site_width [expr [dict get $wrapper_cfg site width] * [dict get $wrapper_cfg def_units]] + set idx 0 + set num_cells [dict size $wrappers] + set num_grids [expr round(sqrt($num_cells)) + 1] + set max_cell_width 0 + dict for {cell_name cell} $wrappers { + set max_cell_width [expr max($max_cell_width,[lindex [dict get $cell die_area] 2])] + } + set grid_x_size [expr $max_cell_width + (2 * $site_width)] + set grid_y_size [expr 4 * $site_height] - set orig_cell [regsub {_mod} $cell {}] - def add_component "w_$idx" $cell $x $y N placed - def add_component "o_$idx" $orig_cell $x [expr round($y + (2 * $site_height))] N placed + def new_design "test_harness" [dict get $wrapper_cfg def_units] \ + [concat [list 0 0] \ + [list [expr round($grid_x_size * $num_grids)] \ + [expr round($grid_y_size * $num_grids)]]] - incr idx - } + foreach cell [dict keys $wrappers] { + set x [expr round(($idx % $num_grids) * $grid_x_size)] + set y [expr round(round($idx / $num_grids) * $grid_y_size)] - def open test_harness.def - def write [set design [def get_current_design]] - def close + set orig_cell [regsub {_mod} $cell {}] + def add_component "w_$idx" $cell $x $y N placed + def add_component "o_$idx" $orig_cell $x [expr round($y + (2 * $site_height))] N placed - return $design + incr idx } - proc set_stdcell_config {config} { - variable wrapper_cfg - set wrapper_cfg $config - } + def open test_harness.def + def write [set design [def get_current_design]] + def close - proc run {} { - set file_name /projects/ssg/pj10000064_diphda/users/colhol01/openroad/library/arm/cp/14lpp/sc10p5mcpp84_base_lvt_c14/r2p1/lef/sc10p5mcpp84_14lpp_base_lvt_c14.lef + return $design +} - lef read_macros $file_name - set data [wrapper find_cells_with_m2_pins] +proc set_stdcell_config { config } { + variable wrapper_cfg + set wrapper_cfg $config +} - set wrappers [wrapper build_wrappers $data] +proc run { } { + # tclint-disable-next-line line-length + set file_name /projects/ssg/pj10000064_diphda/users/colhol01/openroad/library/arm/cp/14lpp/sc10p5mcpp84_base_lvt_c14/r2p1/lef/sc10p5mcpp84_14lpp_base_lvt_c14.lef - lef write_cells sc10p5mcpp84_14lpp_base_lvt_c14.mod.lef $wrappers - def write_cells $wrappers - } + lef read_macros $file_name + set data [wrapper find_cells_with_m2_pins] - proc convert_tech_to_def_units {tech} { - set def_units [dict get $tech units] - dict for {layer_name layer} [dict get $tech layer] { - foreach property {depth width non_preferred_width} { - if {[dict exists $layer $property]} { - dict set tech layer $layer_name $property [expr round([dict get $layer $property] * $def_units)] - } + set wrappers [wrapper build_wrappers $data] + + lef write_cells sc10p5mcpp84_14lpp_base_lvt_c14.mod.lef $wrappers + def write_cells $wrappers +} + +proc convert_tech_to_def_units { tech } { + set def_units [dict get $tech units] + dict for {layer_name layer} [dict get $tech layer] { + foreach property {depth width non_preferred_width} { + if { [dict exists $layer $property] } { + dict set tech layer $layer_name $property \ + [expr round( \ + [dict get $layer $property] * $def_units \ + )] } } - - foreach layer_name [dict keys [dict get $tech layer]] { - foreach property {direction width non_preferred_width} { - if {[dict exists $tech layer $layer_name $property]} { - def set_layer_info $layer_name $property [dict get $tech layer $layer_name $property] - } + } + + foreach layer_name [dict keys [dict get $tech layer]] { + foreach property {direction width non_preferred_width} { + if { [dict exists $tech layer $layer_name $property] } { + def set_layer_info $layer_name $property [dict get $tech layer $layer_name $property] } } + } - dict set tech pitch vertical_track [expr round([dict get $tech pitch vertical_track] * $def_units)] - dict set tech pitch horizontal_track [expr round([dict get $tech pitch horizontal_track] * $def_units)] + dict set tech pitch vertical_track [expr round( \ + [dict get $tech pitch vertical_track] * $def_units)] + dict set tech pitch horizontal_track [expr round( \ + [dict get $tech pitch horizontal_track] * $def_units)] - return $tech - } + return $tech +} - proc set_macro_config {lef_tech} { - variable tech - - set tech [convert_tech_to_def_units $lef_tech] - } - - proc macro {lef_file} { - lef read_macros $lef_file - set cells {} - - foreach cell_name [dict keys [lef get_cells]] { +proc set_macro_config { lef_tech } { + variable tech + + set tech [convert_tech_to_def_units $lef_tech] +} + +proc macro { lef_file } { + lef read_macros $lef_file + set cells {} + + foreach cell_name [dict keys [lef get_cells]] { # debug "$cell_name" - set designs [list ${cell_name}_mod [wrap_macro $cell_name]] - lef write_macros ${cell_name}_mod.lef $designs - def write_cells $designs - lappend cells $cell_name - } - - return $cells + set designs [list ${cell_name}_mod [wrap_macro $cell_name]] + lef write_macros ${cell_name}_mod.lef $designs + def write_cells $designs + lappend cells $cell_name } - namespace export find_cells_with_m2_pins macro set_stdcell_config set_macro_config - namespace export information warning err critical - namespace export build_wrappers - namespace export test_harness - namespace ensemble create + return $cells +} + +namespace export find_cells_with_m2_pins macro set_stdcell_config set_macro_config +namespace export information warning err critical +namespace export build_wrappers +namespace export test_harness +namespace ensemble create } package provide wrapper 1.0.0 diff --git a/flow/util/correlateRC.py b/flow/util/correlateRC.py index bc046e94d2..410f8e3144 100755 --- a/flow/util/correlateRC.py +++ b/flow/util/correlateRC.py @@ -5,9 +5,10 @@ # Use ORFS 'make write_net_rc' to write cap files. import os -from sys import exit +from sys import exit, stderr from collections import defaultdict +import traceback import collections import argparse import re @@ -15,6 +16,8 @@ from sklearn.linear_model import LinearRegression import matplotlib.pyplot as plt +LAYER_HEADER_RE = re.compile("^([^\\(]+)\\(([^\\)]+)\\)$") + # Parse and validate arguments # ============================================================================= @@ -81,6 +84,12 @@ def makeDict(): data = makeDict() +stack = [] +stack_line = None + +# indices of relevant layers (routable layers or via layers) +active_layers = set() + # Parse the cap CSV file generated by compare_rc_script.tcl for rc_file in args.rc_file: design = rc_file @@ -88,32 +97,64 @@ def makeDict(): with open(rc_file) as f: nonGrtNets = 0 for line in f: + if line.startswith("# stack: "): + if stack_line is not None and stack_line != line: + print(f"layer stack inconsistent", file=stderr) + exit(1) + elif stack_line is None: + for layer in line.removeprefix("# stack: ").strip().split(" "): + name = layer + is_routing = False + via_resist = 0.0 + if layer.endswith(")"): + # layer name has extra data + match = LAYER_HEADER_RE.match(layer) + assert match + name = match.group(1) + if match.group(2) == "routing": + is_routing = True + else: + via_resist = float(match.group(2)) + stack.append((name, is_routing, via_resist)) + stack_line = line + continue + tokens = line.strip().split(",") netName = tokens[0] - gpl_res = float(tokens[1]) - gpl_cap = float(tokens[2]) - grt_res = float(tokens[3]) - grt_cap = float(tokens[4]) - rcx_res = float(tokens[5]) - rcx_cap = float(tokens[6]) - - data[design][netName]["gpl_res"] = gpl_res - data[design][netName]["gpl_cap"] = gpl_cap - data[design][netName]["grt_res"] = grt_res - data[design][netName]["grt_cap"] = grt_cap - data[design][netName]["rcx_res"] = rcx_res - data[design][netName]["rcx_cap"] = rcx_cap - - layer_lengths = [] - layer_names = [] - wire_length = 0.0 - for i in range(7, len(tokens), 2): - layer_names.append(tokens[i]) - layer_length = float(tokens[i + 1]) - layer_lengths.append(layer_length) - wire_length += layer_length + + data[design][netName] = { + "type": tokens[1], + "gpl_res": float(tokens[2]), + "gpl_cap": float(tokens[3]), + "grt_res": float(tokens[4]), + "grt_cap": float(tokens[5]), + "rcx_res": float(tokens[6]), + "rcx_cap": float(tokens[7]), + } + + layer_lengths = [float(tok) for tok in tokens[8:]] + for i, length in enumerate(layer_lengths): + if length > 0: + active_layers.add(i) + data[design][netName]["layer_lengths"] = layer_lengths - data[design][netName]["wire_length"] = wire_length + data[design][netName]["routable_layer_lengths"] = [ + length + for i, length in enumerate(layer_lengths) + # ignore non-routable layers + if stack[i][1] + ] + data[design][netName]["wire_length"] = sum( + length + for i, length in enumerate(layer_lengths) + # ignore non-routable layers + if stack[i][1] + ) + data[design][netName]["grt_via_res"] = sum( + (length * stack[i][2]) + for i, length in enumerate(layer_lengths) + if not stack[i][1] + ) ################################################################ @@ -210,16 +251,15 @@ def makeDict(): for net in data[design]: rcx_res = data[design][net]["rcx_res"] if rcx_res > 0: - layer_lengths = data[design][net]["layer_lengths"] - x.append(layer_lengths) - y.append(rcx_res) + x.append(data[design][net]["routable_layer_lengths"]) + y.append(rcx_res - data[design][net]["grt_via_res"]) x = np.array(x) y = np.array(y) res_model = LinearRegression(fit_intercept=False).fit(x, y) r_sq = res_model.score(x, y) -print("Resistance coefficient of determination: {:.4f}".format(r_sq)) +print("# Resistance coefficient of determination: {:.4f}".format(r_sq)) ################################################################ @@ -229,8 +269,7 @@ def makeDict(): y = [] for design in data: for net in data[design]: - layer_lengths = data[design][net]["layer_lengths"] - x.append(layer_lengths) + x.append(data[design][net]["routable_layer_lengths"]) y.append(data[design][net]["rcx_cap"]) x = np.array(x) @@ -238,51 +277,62 @@ def makeDict(): cap_model = LinearRegression(fit_intercept=False).fit(x, y) r_sq = cap_model.score(x, y) -print("Capacitance coefficient of determination: {:.4f}".format(r_sq)) - -print("Updated layer resistance {}/um capacitance {}/um".format(res_unit, cap_unit)) -for layer, res_coeff, cap_coeff in zip(layer_names, res_model.coef_, cap_model.coef_): - if res_coeff > 0.0 or cap_coeff > 0.0: +print("# Capacitance coefficient of determination: {:.4f}".format(r_sq)) +print("# Updated layer resistance {}/um capacitance {}/um".format(res_unit, cap_unit)) + +routable_layers = [layer for layer in stack if layer[1]] +for i, layer in enumerate(routable_layers): + res_coeff = res_model.coef_[i] + cap_coeff = cap_model.coef_[i] + if res_coeff != 0.0 or cap_coeff != 0.0: print( "set_layer_rc -layer {} -resistance {:.5E} -capacitance {:.5E}".format( - layer, res_coeff / res_scale, cap_coeff / cap_scale + layer[0], res_coeff / res_scale, cap_coeff / cap_scale ) ) ################################################################ -x = [] -y = [] -for design in data: - for net in data[design]: - wire_res = data[design][net]["rcx_res"] - wire_length = data[design][net]["wire_length"] - if wire_res != 0.0: - x.append([wire_length]) - y.append(wire_res) - -x = np.array(x) -y = np.array(y) - -wire_res_model = LinearRegression(fit_intercept=False).fit(x, y) -wire_res = wire_res_model.coef_[0] -x = [] -y = [] -for design in data: - for net in data[design]: - wire_length = data[design][net]["wire_length"] - x.append([wire_length]) - y.append(data[design][net]["rcx_cap"]) +def generic_rc_fit(type_sieve): + x = [] + y = [] + for design in data: + for net in data[design]: + net_type = data[design][net]["type"] + wire_res = data[design][net]["rcx_res"] + wire_length = data[design][net]["wire_length"] + if net_type in type_sieve and wire_res != 0.0: + x.append([wire_length]) + y.append(wire_res) + x = np.array(x) + y = np.array(y) + wire_res_model = LinearRegression(fit_intercept=False).fit(x, y) + wire_res = wire_res_model.coef_[0] + + x = [] + y = [] + for design in data: + for net in data[design]: + net_type = data[design][net]["type"] + if net_type in type_sieve: + wire_length = data[design][net]["wire_length"] + wire_cap = data[design][net]["rcx_cap"] + x.append([wire_length]) + y.append(wire_cap) + x = np.array(x) + y = np.array(y) + wire_cap_model = LinearRegression(fit_intercept=False).fit(x, y) + wire_cap = wire_cap_model.coef_[0] + + return "-resistance {:.5E} -capacitance {:.5E}".format( + wire_res / res_scale, wire_cap / cap_scale + ) -x = np.array(x) -y = np.array(y) -wire_cap_model = LinearRegression(fit_intercept=False).fit(x, y) -wire_cap = wire_cap_model.coef_[0] +print("# Combined fit:") +print("set_wire_rc " + generic_rc_fit(["signal", "clock"])) -print( - "set_wire_rc -resistance {:.5E} -capacitance {:.5E}".format( - wire_res / res_scale, wire_cap / cap_scale - ) -) +print("# Split signal/clock fit:") +print("set_wire_rc -signal " + generic_rc_fit(["signal"])) +print("set_wire_rc -clock " + generic_rc_fit(["clock"])) diff --git a/flow/util/genElapsedTime.py b/flow/util/genElapsedTime.py index 4a1159d105..3d78e66455 100755 --- a/flow/util/genElapsedTime.py +++ b/flow/util/genElapsedTime.py @@ -4,26 +4,51 @@ # in the flow and prints it in a table # --------------------------------------------------------------------------- +import argparse +import hashlib import pathlib import os -import argparse # argument parsing import sys # Parse and validate arguments # ============================================================================== +def get_hash(f): + # content hash for the result file alongside .log file is useful to + # debug divergent results under what should be identical + # builds(such as local and CI builds) + for ext in [".odb", ".rtlil", ".v"]: + result_file = pathlib.Path( + str(f).replace("logs/", "results/").replace(".log", ext) + ) + if result_file.exists(): + hasher = hashlib.sha1() + with open(result_file, "rb") as odb_f: + while True: + chunk = odb_f.read(16 * 1024 * 1024) + if not chunk: + break + hasher.update(chunk) + return hasher.hexdigest() + return "N/A" + + def print_log_dir_times(logdir, args): first = True totalElapsed = 0 total_max_memory = 0 - print(logdir) + if not args.match: + print(logdir) # Loop on all log files in the directory for f in sorted(pathlib.Path(logdir).glob("**/*.log")): if "eqy_output" in str(f): continue # Extract Elapsed Time line from log file + stem = os.path.splitext(os.path.basename(str(f)))[0] + if args.match and args.match != stem: + continue with open(str(f)) as logfile: found = False for line in logfile: @@ -60,36 +85,49 @@ def print_log_dir_times(logdir, args): peak_memory = int( int(line.split("Peak memory: ")[1].split("KB")[0]) / 1024 ) + break + + odb_hash = get_hash(f) if not found: print("No elapsed time found in", str(f), file=sys.stderr) continue # Print the name of the step and the corresponding elapsed time - format_str = "%-25s %20s %14s" + format_str = "%-25s %10s %14s %20s" if elapsedTime is not None and peak_memory is not None: if first and not args.noHeader: - print(format_str % ("Log", "Elapsed seconds", "Peak Memory/MB")) + print( + format_str + % ("Log", "Elapsed/s", "Peak Memory/MB", "sha1sum .odb [0:20)") + ) first = False print( format_str % ( - os.path.splitext(os.path.basename(str(f)))[0], + stem, elapsedTime, peak_memory, + odb_hash[0:20], ) ) - totalElapsed += elapsedTime - total_max_memory = max(total_max_memory, int(peak_memory)) + if elapsedTime is not None: + totalElapsed += elapsedTime + if peak_memory is not None: + total_max_memory = max(total_max_memory, int(peak_memory)) - if totalElapsed != 0: - print(format_str % ("Total", totalElapsed, total_max_memory)) + if totalElapsed != 0 and not args.match: + print(format_str % ("Total", totalElapsed, total_max_memory, "")) def scan_logs(args): parser = argparse.ArgumentParser( description="Print elapsed time for every step in the flow" ) + parser.add_argument( + "--match", + help="Match this string in the log file names", + ) parser.add_argument( "--logDir", "-d", required=True, nargs="+", help="Log files directories" ) diff --git a/flow/util/genMetrics.py b/flow/util/genMetrics.py index b3a1080c3e..33261a7f8c 100755 --- a/flow/util/genMetrics.py +++ b/flow/util/genMetrics.py @@ -6,7 +6,6 @@ # ----------------------------------------------------------------------------- import os -from sys import exit from datetime import datetime, timedelta from collections import defaultdict from uuid import uuid4 as uuid @@ -14,7 +13,6 @@ import argparse import json -import pandas as pd import re from glob import glob @@ -26,8 +24,7 @@ def parse_args(): parser.add_argument( "--design", "-d", - required=False, - default="all_designs", + required=True, help="Design Name for metrics", ) parser.add_argument( @@ -51,17 +48,9 @@ def parse_args(): "--output", "-o", required=False, default="metadata.json", help="Output file" ) parser.add_argument("--hier", "-x", action="store_true", help="Hierarchical JSON") - parser.add_argument("--logs", help="Path to logs", default=None) - parser.add_argument( - "--reports", - help="Path to reports", - default=None, - ) - parser.add_argument( - "--results", - help="Path to results", - default=None, - ) + parser.add_argument("--logs", help="Path to logs") + parser.add_argument("--reports", help="Path to reports") + parser.add_argument("--results", help="Path to results") args = parser.parse_args() return args @@ -299,7 +288,7 @@ def extract_metrics( # Accumulate time # ========================================================================= - extractGnuTime("synth", metrics_dict, logPath + "/1_1_yosys.log") + extractGnuTime("synth", metrics_dict, logPath + "/1_2_yosys.log") extractGnuTime("floorplan", metrics_dict, logPath + "/2_1_floorplan.log") extractGnuTime("floorplan_io", metrics_dict, logPath + "/2_2_floorplan_io.log") extractGnuTime( @@ -356,10 +345,6 @@ def extract_metrics( else: metrics_dict["total_time"] = str(total) - metrics_df = pd.DataFrame(list(metrics_dict.items())) - col_index = metrics_df.iloc[0][1] + "__" + metrics_df.iloc[1][1] - metrics_df.columns = ["Metrics", col_index] - if hier_json: # Convert the Metrics dictionary to hierarchical format by stripping # the stage as a 'key' @@ -373,80 +358,18 @@ def extract_metrics( with open(output, "w") as resultSpecfile: json.dump(metrics_dict, resultSpecfile, indent=2, sort_keys=True) - return metrics_dict, metrics_df - args = parse_args() now = datetime.now() -flow_variants = args.flowVariant.split() -all_designs = True if args.design == "all_designs" else False -designs = args.design.split() -platforms = args.platform.split() - -if all_designs or len(designs) > 1 or len(flow_variants) > 1: - rootdir = "./logs" - - all_df = pd.DataFrame() - all_d = [] - cwd = os.getcwd() - for platform_it in os.scandir(rootdir): - if not platform_it.is_dir(): - continue - plt = platform_it.name - if not plt in platforms: - continue - for design_it in os.scandir(platform_it.path): - if not design_it.is_dir(): - continue - des = design_it.name - if not (all_designs or des in designs): - continue - for variant in flow_variants: - log_dir = os.path.join(cwd, "logs", plt, des, variant) - if not os.path.isdir(log_dir): - continue - if not os.path.isfile(os.path.join(log_dir, "6_report.json")): - print( - f"Skip extracting metrics for {plt}, {des}, {variant} as run did not complete" - ) - continue - print(f"Extract Metrics for {plt}, {des}, {variant}") - file = "/".join(["reports", plt, des, variant, "metrics.json"]) - logPath = os.path.join(cwd, "logs", plt, des, variant) - rptPath = os.path.join(cwd, "reports", plt, des, variant) - resultPath = os.path.join(cwd, "results", plt, des, variant) - metrics, df = extract_metrics( - cwd, - plt, - des, - variant, - file, - args.hier, - logPath, - rptPath, - resultPath, - ) - all_d.append(metrics) - if all_df.shape[0] == 0: - all_df = df - else: - all_df = all_df.merge(df, on="Metrics", how="inner") - - with open("metrics.json", "w") as outFile: - json.dump(all_d, outFile, indent=2) - - with open("metrics.html", "w") as f: - f.write(all_df.to_html()) -else: - metrics_dict, metrics_df = extract_metrics( - os.path.join(os.path.dirname(os.path.realpath(__file__)), "../"), - args.platform, - args.design, - args.flowVariant, - args.output, - args.hier, - args.logs, - args.reports, - args.results, - ) +extract_metrics( + os.path.join(os.path.dirname(os.path.realpath(__file__)), "../"), + args.platform, + args.design, + args.flowVariant, + args.output, + args.hier, + args.logs, + args.reports, + args.results, +) diff --git a/flow/util/genRuleFile.py b/flow/util/genRuleFile.py index 99866137f1..9162015ac4 100755 --- a/flow/util/genRuleFile.py +++ b/flow/util/genRuleFile.py @@ -21,8 +21,6 @@ def gen_rule_file( metrics_file=None, metrics_to_consider=[], ): - print(f"{os.path.normpath(rules_file)} updates:") - with open(metrics_file, "r") as f: metrics = json.load(f) if not isinstance(metrics, dict): @@ -296,6 +294,7 @@ def gen_rule_file( rules[field] = dict(value=rule_value, compare=option["compare"]) if len(change_str) > 0: + print(f"{os.path.normpath(rules_file)} updates:") print(format_str.format("Metric", "Old", "New", "Type"), end="") print(format_str.format("------", "---", "---", "----"), end="") print(change_str) diff --git a/flow/util/generate-vars.sh b/flow/util/generate-vars.sh index 0c5a04b5d5..a80c0d1312 100755 --- a/flow/util/generate-vars.sh +++ b/flow/util/generate-vars.sh @@ -22,7 +22,7 @@ while read -r VAR; do # they are invalid in shell continue fi - name="${VAR%=*}" + name="${VAR%%=*}" value="${VAR#*=}" if [[ "${name}" =~ ^[[:digit:]] ]] ; then # skip if the name starts with a number diff --git a/flow/util/makeIssue.sh b/flow/util/makeIssue.sh index b06b789567..9152294daa 100755 --- a/flow/util/makeIssue.sh +++ b/flow/util/makeIssue.sh @@ -32,7 +32,7 @@ ISSUE_CP_PLATFORM_FILE_VARS="LIB_FILES \ PDN_TCL \ POST_PDN_TCL \ POST_CTS_TCL \ - PRE_GLOBAL_ROUTE \ + PRE_GLOBAL_ROUTE_TCL \ FASTROUTE_TCL \ POST_DETAIL_ROUTE_TCL \ RCX_RULES \ diff --git a/flow/util/mergeLib.pl b/flow/util/mergeLib.pl deleted file mode 100755 index 146a75febf..0000000000 --- a/flow/util/mergeLib.pl +++ /dev/null @@ -1,61 +0,0 @@ -#!/usr/bin/env perl - -# This script is sourced from Brown (with slight modifications). It merges -# several timing libraries into one. -# ------------------------------------------------------------------------------ - -use strict; -use warnings; - -my $sclname = $ARGV[0]; -shift @ARGV; -my $cnt = @ARGV; - -if($cnt>0){ - process_header($ARGV[0]); - my $file; - foreach my $file (@ARGV) { - process_cells($file) - } - print "\n}\n"; -} else { - print "use: mergeLib.pl new_library_name lib1 lib2 lib3 ...."; -} - - -sub process_header { - my $filename = shift; - open(my $fh, '<', $filename) or die "Could not open file $filename $!"; - while (<$fh>) { - if(/library\s*\(/) { - print "library ($sclname) {\n"; - next; - } - last if(/^[\t\s]*cell\s*\(/); - print $_; - } - close($fh) -} - -sub process_cells { - my $filename = shift; - - open(my $fh, '<', $filename) or die "Could not open file $filename $!"; - - my $flag = 0; - # cut the cells - while (<$fh>) { - #chomp $_; - if(/^[\t\s]*cell\s*\(/) {#&& $flag==0){ - die "Error! new cell before finishing the previous one!\n" if($flag!=0); - print "\n$_"; - $flag=1; - } elsif($flag > 0){ - $flag++ if(/\{/); - $flag-- if(/\}/); - #print "...}\n" if($flag==0); - print "$_"; - } - } - close($fh) -} diff --git a/flow/util/merge_lib.py b/flow/util/merge_lib.py new file mode 100755 index 0000000000..961b5e2330 --- /dev/null +++ b/flow/util/merge_lib.py @@ -0,0 +1,56 @@ +#!/usr/bin/env python3 + +import re +import sys + + +def process_header(filename, sclname): + with open(filename, "r") as fh: + for line in fh: + if re.search(r"library\s*\(", line): + print(f"library ({sclname}) {{") + continue + if re.match(r"^[\t ]*cell\s*\(", line): + break + print(line, end="") + + +def process_cells(filename): + with open(filename, "r") as fh: + flag = 0 # brace depth + for line in fh: + # Match 'cell ( ... )' with optional whitespace + if re.match(r"^[\t ]*cell\s*\(", line): + if flag != 0: + raise RuntimeError( + "Error! new cell before finishing the previous one!" + ) + print() # print blank line like Perl + print(line, end="") + flag = 1 # entering a cell block + elif flag > 0: + # Increase/decrease brace depth + flag += line.count("{") + flag -= line.count("}") + print(line, end="") + + # Optionally: reset flag to 0 here if it's finished + # But not necessary unless you're adding post-processing + + +def main(): + if len(sys.argv) < 3: + print("use: mergeLib.py new_library_name lib1 lib2 lib3 ....") + sys.exit(1) + + sclname = sys.argv[1] + files = sys.argv[2:] + + process_header(files[0], sclname) + for file in files: + process_cells(file) + print("\n}") + + +if __name__ == "__main__": + main() diff --git a/flow/util/requirements_lock.txt b/flow/util/requirements_lock.txt index f47a529ab3..e6aa58ad02 100644 --- a/flow/util/requirements_lock.txt +++ b/flow/util/requirements_lock.txt @@ -1,8 +1,8 @@ # -# This file is autogenerated by pip-compile with Python 3.12 +# This file is autogenerated by pip-compile with Python 3.13 # by the following command: # -# bazel run //:requirements.update +# bazel run //flow/util:requirements.update # contourpy==1.3.1 \ --hash=sha256:041b640d4ec01922083645a94bb3b2e777e6b626788f4095cf21abbe266413c1 \ @@ -233,7 +233,7 @@ matplotlib==3.10.0 \ --hash=sha256:d44cb942af1693cced2604c33a9abcef6205601c445f6d0dc531d813af8a2f5a \ --hash=sha256:d907fddb39f923d011875452ff1eca29a9e7f21722b873e90db32e5d8ddff12e \ --hash=sha256:fd44fc75522f58612ec4a33958a7e5552562b7705b42ef1b4f8c0818e304a363 - # via -r util/requirements.in + # via -r flow/util/requirements.in numpy==2.2.2 \ --hash=sha256:02935e2c3c0c6cbe9c7955a8efa8908dd4221d7755644c59d1bba28b94fd334f \ --hash=sha256:0349b025e15ea9d05c3d63f9657707a4e1d471128a3b1d876c095f328f8ff7f0 \ @@ -432,7 +432,7 @@ pyyaml==6.0.2 \ --hash=sha256:efdca5630322a10774e8e98e1af481aad470dd62c3170801852d752aa7a783ba \ --hash=sha256:f753120cb8181e736c57ef7636e83f31b9c0d1722c516f7e86cf15b7aa57ff12 \ --hash=sha256:ff3824dc5261f50c9b0dfb3be22b4567a6f938ccce4587b38952d85fd9e9afe4 - # via -r util/requirements.in + # via -r flow/util/requirements.in six==1.17.0 \ --hash=sha256:4721f391ed90541fddacab5acf947aa0d3dc7d27b2e1e8eda2be8970586c3274 \ --hash=sha256:ff70335d468e7eb6ec65b95b99d3a2836546063f63acc5171de367e834932a81 diff --git a/flow/util/utils.mk b/flow/util/utils.mk index c7a5a79621..84f10aa11a 100644 --- a/flow/util/utils.mk +++ b/flow/util/utils.mk @@ -5,9 +5,9 @@ metadata: finish metadata-generate metadata-check .PHONY: metadata-generate metadata-generate: - @mkdir -p $(REPORTS_DIR) - @echo $(DESIGN_DIR) > $(REPORTS_DIR)/design-dir.txt - $(UTILS_DIR)/genMetrics.py -d $(DESIGN_NICKNAME) \ + mkdir -p $(REPORTS_DIR) + echo $(DESIGN_DIR) > $(REPORTS_DIR)/design-dir.txt + $(PYTHON_EXE) $(UTILS_DIR)/genMetrics.py -d $(DESIGN_NICKNAME) \ -p $(PLATFORM) \ -v $(FLOW_VARIANT) \ --logs $(LOG_DIR) \ @@ -20,7 +20,7 @@ export RULES_JSON ?= $(DESIGN_DIR)/rules-$(FLOW_VARIANT).json .PHONY: metadata-check metadata-check: - @$(UTILS_DIR)/checkMetadata.py \ + $(PYTHON_EXE) $(UTILS_DIR)/checkMetadata.py \ -m $(REPORTS_DIR)/metadata.json \ -r $(RULES_JSON) 2>&1 \ | tee $(abspath $(REPORTS_DIR)/metadata-check.log) @@ -40,8 +40,8 @@ update_metadata: .PHONY: do-update_rules do-update_rules: - @mkdir -p $(REPORTS_DIR) - $(UTILS_DIR)/genRuleFile.py \ + mkdir -p $(REPORTS_DIR) + $(PYTHON_EXE) $(UTILS_DIR)/genRuleFile.py \ --rules $(RULES_JSON) \ --new-rules $(REPORTS_DIR)/rules.json \ --reference $(REPORTS_DIR)/metadata.json \ @@ -59,7 +59,7 @@ update_rules: do-update_rules do-copy_update_rules .PHONY: do-update_rules_force do-update_rules_force: - @mkdir -p $(REPORTS_DIR) + mkdir -p $(REPORTS_DIR) $(UTILS_DIR)/genRuleFile.py \ --rules $(RULES_JSON) \ --new-rules $(REPORTS_DIR)/rules.json \ @@ -74,7 +74,7 @@ update_rules_force: do-update_rules_force .PHONY: update_metadata_autotuner update_metadata_autotuner: - @$(UTILS_DIR)/genMetrics.py -d $(DESIGN_NICKNAME) \ + $(PYTHON_EXE) $(UTILS_DIR)/genMetrics.py -d $(DESIGN_NICKNAME) \ -p $(PLATFORM) \ -v $(FLOW_VARIANT) \ --logs $(LOG_DIR) \ @@ -93,7 +93,7 @@ $(RESULTS_DIR)/6_net_rc.csv: .PHONY: correlate_rc correlate_rc: $(RESULTS_DIR)/6_net_rc.csv - $(UTILS_DIR)/correlateRC.py $(RESULTS_DIR)/6_net_rc.csv + $(PYTHON_EXE) $(UTILS_DIR)/correlateRC.py $(RESULTS_DIR)/6_net_rc.csv # TODO Make always wants to redo designs with this rule, regardless of which variations are tried. # $(MAKE) DESIGN_CONFIG=$$config write_net_rc; \ @@ -104,7 +104,7 @@ correlate_platform_rc: design=$$(basename $$(dirname $$config)); \ make DESIGN_CONFIG=./$$config results/$(PLATFORM)/$$design/base/6_net_rc.csv; \ done - $(UTILS_DIR)/correlateRC.py $$(find results/$(PLATFORM)/*/base -name 6_net_rc.csv) + $(PYTHON_EXE) $(UTILS_DIR)/correlateRC.py $$(find results/$(PLATFORM)/*/base -name 6_net_rc.csv) # Run test using gnu parallel #------------------------------------------------------------------------------- diff --git a/flow/util/write_net_rc.tcl b/flow/util/write_net_rc.tcl index 5b028f9417..9f6b5d2b49 100644 --- a/flow/util/write_net_rc.tcl +++ b/flow/util/write_net_rc.tcl @@ -37,25 +37,65 @@ proc write_rc_csv { filename } { upvar 1 grt rc_var2 upvar 1 rcx rc_var3 - set max_layer_name $::env(MAX_ROUTING_LAYER) - set max_layer [[[ord::get_db_tech] findLayer $max_layer_name] getRoutingLevel] - set min_layer_name $::env(MIN_ROUTING_LAYER) - set min_layer [[[ord::get_db_tech] findLayer $min_layer_name] getRoutingLevel] + set tech [ord::get_db_tech] set stream [open $filename "w"] + + puts -nonewline $stream "# stack:" + foreach layer [[ord::get_db_tech] getLayers] { + set routing [expr [$layer getRoutingLevel] != 0] + set is_routing([$layer getNumber]) $routing + set is_routing([$layer getNumber]) $routing + puts -nonewline $stream " [$layer getName]" + if { $routing } { + puts -nonewline $stream "(routing)" + } else { + # insert via resistance information + set via_resist [$layer getResistance] + if { $via_resist != 0.0 } { + puts -nonewline $stream "([format %.4e $via_resist])" + } + } + } + puts $stream "" + + set use_drt_data [env_var_exists_and_non_empty CORRELATE_DRT_WIRELENGTH] + foreach net [get_nets *] { - set net_name [get_full_name $net] - lassign $rc_var1($net_name) wire_res1 wire_cap1 - lassign $rc_var2($net_name) wire_res2 wire_cap2 - lassign $rc_var3($net_name) wire_res3 wire_cap3 - puts -nonewline $stream "[get_full_name $net],[format %.3e $wire_res1],[format %.3e $wire_cap1],[format %.3e $wire_res2],[format %.3e $wire_cap2],[format %.3e $wire_res3],[format %.3e $wire_cap3]" set db_net [sta::sta_to_db_net $net] - set layer_lengths [grt::route_layer_lengths $db_net] - for {set layer $min_layer} {$layer <= $max_layer} {incr layer} { - set layer_name [[[ord::get_db_tech] findRoutingLayer $layer] getName] - set length [lindex $layer_lengths $layer] - puts -nonewline $stream ",$layer_name,[ord::dbu_to_microns $length]" + set type [$db_net getSigType] + if { + ([string equal $type "CLOCK"] || [string equal $type "SIGNAL"]) && + (!$use_drt_data || [$db_net getWire] ne "NULL") + } { + set net_name [get_full_name $net] + lassign $rc_var1($net_name) wire_res1 wire_cap1 + lassign $rc_var2($net_name) wire_res2 wire_cap2 + lassign $rc_var3($net_name) wire_res3 wire_cap3 + set net_type [expr { [string equal $type "CLOCK"] ? "clock" : "signal" }] + puts -nonewline $stream "[get_full_name $net],$net_type," + puts -nonewline $stream [concat \ + [format "%.3e" $wire_res1] "," [format "%.3e" $wire_cap1] "," \ + [format "%.3e" $wire_res2] "," [format "%.3e" $wire_cap2] "," \ + [format "%.3e" $wire_res3] "," [format "%.3e" $wire_cap3]] + set db_net [sta::sta_to_db_net $net] + + if { $use_drt_data } { + set layer_lengths [drt::route_layer_lengths [$db_net getWire]] + } else { + set layer_lengths [grt::route_layer_lengths $db_net] + } + + for { set layer 0 } { $layer < [$tech getLayerCount] } { incr layer } { + set length [lindex $layer_lengths $layer] + if { $is_routing($layer) } { + puts -nonewline $stream ",[ord::dbu_to_microns $length]" + } else { + puts -nonewline $stream ",$length" + } + } + + puts $stream "" } - puts $stream "" } close $stream } @@ -73,19 +113,7 @@ proc record_wire_rc { var_name } { # Only works or makes sense for 2 pin nets. proc net_wire_res { net } { - set pins [get_pins -of_object $net] - if { [llength $pins] == 2 } { - lassign $pins pin1 pin2 - if { [$pin1 is_driver] } { - set drvr $pin1 - } else { - set drvr $pin2 - } - lassign [sta::find_pi_elmore $drvr rise max] c2 rpi c1 - return $rpi - } else { - return 0.0 - } + return [rsz::sum_parasitic_network_resist $net] } proc net_wire_cap { net } { @@ -118,7 +146,8 @@ proc compare_wire_rc { count var_name ref_var_name } { # implicit arg to net_var_cap_less set var_cap_less_name $ref_var_name set nets [lsort -command net_var_cap_less [get_nets *]] - puts "net fanout [format %5s $var_name] [format %5s $ref_var_name] wire total [format %5s $var_name] [format %5s $ref_var_name]" + puts "net fanout [format %4s $var_name] [format %5s $ref_var_name] \ + wire total [format %5s $var_name] [format %5s $ref_var_name]" puts " cap cap delta delta res res delta" set res_sum 0.0 set res_count 0 @@ -139,8 +168,11 @@ proc compare_wire_rc { count var_name ref_var_name } { set res_avg [expr $res_sum / $count] set cap_avg [expr $cap_sum / $count] set total_cap_avg [expr $total_cap_sum / $count] - puts " ----- ----- -----" - puts " [format %+4.0f $cap_avg]% [format %+4.0f $total_cap_avg]% [format %+4.0f $res_avg]%" + puts " \ + ----- ----- -----" + puts " \ + [format %+4.0f $cap_avg]% [format %+4.0f $total_cap_avg]%\ + [format %+4.0f $res_avg]%" } proc compare_net_wire_rc { net_name var_name ref_var_name } { @@ -148,7 +180,8 @@ proc compare_net_wire_rc { net_name var_name ref_var_name } { upvar 1 $ref_var_name ref_var global var_cap_less_name - puts "net fanout [format %5s $var_name] [format %5s $ref_var_name] wire total" + puts "net fanout [format %5s $var_name] [format %5s $ref_var_name] \ + wire total" puts " cap cap delta delta" compare_wire_rc1 [get_net $net_name] $var_name $ref_var_name } @@ -175,7 +208,7 @@ proc compare_wire_rc1 { net var_name ref_var_name } { } else { set cap_delta 0.0 } - + set total_cap [expr $pin_cap + $wire_cap] set total_cap_ref [expr $pin_cap + $wire_cap_ref] if { $total_cap_ref != 0.0 } { @@ -183,12 +216,21 @@ proc compare_wire_rc1 { net var_name ref_var_name } { } else { set total_delta 0.0 } - + set fanout [llength [get_pins -of $net -filter "direction == input"]] - puts -nonewline "[format %-20s $net_name] [format %5d $fanout] [format %8s [sta::format_capacitance $wire_cap 3]] [format %8s [sta::format_capacitance $wire_cap_ref 3]] [format %4.0f $cap_delta]% [format %4.0f $total_delta]%" + puts -nonewline [concat \ + [format "%-20s" $net_name] " " \ + [format "%5d" $fanout] " " \ + [format "%8s" [sta::format_capacitance $wire_cap 3]] " " \ + [format "%8s" [sta::format_capacitance $wire_cap_ref 3]] " " \ + [format "%4.0f" $cap_delta]% " " \ + [format "%4.0f" $total_delta]%] if { $res > 0.0 } { - puts "[format %8s [sta::format_resistance $res 3]] [format %8s [sta::format_resistance $res_ref 3]] [format %4.0f $res_delta]%" + puts [concat \ + [format "%8s" [sta::format_resistance $res 3]] " " \ + [format "%8s" [sta::format_resistance $res_ref 3]] " " \ + [format "%4.0f" $res_delta]%] } else { puts "" } @@ -207,8 +249,12 @@ proc write_layer_rc_cmds { adjustment } { set cap_edge [$layer getEdgeCapacitance] set cap_area [$layer getCapacitance] # Convert pF/um to F/um. - set cap [expr ($cap_edge * 2.0 + $wire_width * $cap_area) * 1e-12 / (1.0 + $adjustment / 100.0)] - puts "set_layer_rc -layer [$layer getConstName] -resistance [format %.4e [sta::resistance_sta_ui $res]] -capacitance [format %.4e [sta::capacitance_sta_ui $cap]]" + set cap [expr \ + ($cap_edge * 2.0 + $wire_width * $cap_area) * 1e-12 / (1.0 + $adjustment / 100.0)] + puts [concat \ + "set_layer_rc -layer [$layer getConstName] " \ + "-resistance [format %.4e [sta::resistance_sta_ui $res]] " \ + "-capacitance [format %.4e [sta::capacitance_sta_ui $cap]]"] } } } diff --git a/flow/util/write_net_rc_script.tcl b/flow/util/write_net_rc_script.tcl index afda93c270..a2815ce5a6 100644 --- a/flow/util/write_net_rc_script.tcl +++ b/flow/util/write_net_rc_script.tcl @@ -1,26 +1,15 @@ source $::env(SCRIPTS_DIR)/load.tcl -# Note 6_final.def has wires that prevent global routing. -load_design 4_1_cts.odb 4_cts.sdc +load_design 6_final.odb 6_final.sdc source $::env(UTILS_DIR)/write_net_rc.tcl estimate_parasitics -placement record_wire_rc gpl -if {[env_var_exists_and_non_empty FASTROUTE_TCL]} { - source $env(FASTROUTE_TCL) -} else { - set_global_routing_layer_adjustment $env(MIN_ROUTING_LAYER)-$env(MAX_ROUTING_LAYER) 0.5 - set_routing_layers -signal $env(MIN_ROUTING_LAYER)-$env(MAX_ROUTING_LAYER) - set_macro_extension 2 -} - -global_route -congestion_iterations 100 - estimate_parasitics -global_routing record_wire_rc grt -read_spef -quiet -reduce_to pi_elmore $::env(RESULTS_DIR)/6_final.spef +read_spef $::env(RESULTS_DIR)/6_final.spef record_wire_rc rcx #compare_wire_rc 50 grt rcx diff --git a/jenkins/public_nightly.Jenkinsfile b/jenkins/public_nightly.Jenkinsfile index 89198cd515..75fbdcfbeb 100644 --- a/jenkins/public_nightly.Jenkinsfile +++ b/jenkins/public_nightly.Jenkinsfile @@ -1,4 +1,4 @@ -@Library('utils@orfs-v2.3.1') _ +@Library('utils@orfs-v2.3.5') _ node { diff --git a/jenkins/public_tests_all.Jenkinsfile b/jenkins/public_tests_all.Jenkinsfile index 901e20c4b2..1239a279e3 100644 --- a/jenkins/public_tests_all.Jenkinsfile +++ b/jenkins/public_tests_all.Jenkinsfile @@ -1,8 +1,22 @@ -@Library('utils@orfs-v2.3.1') _ +@Library('utils@orfs-v2.3.5') _ node { + + def isDefaultBranch = (env.BRANCH_NAME == 'master') + def daysToKeep = '20'; + def numToKeep = (isDefaultBranch ? '-1' : '10'); - properties([copyArtifactPermission('${JOB_NAME},'+env.BRANCH_NAME)]); + properties([ + copyArtifactPermission('${JOB_NAME},'+env.BRANCH_NAME), + + buildDiscarder(logRotator( + daysToKeepStr: daysToKeep, + artifactDaysToKeepStr: daysToKeep, + + numToKeepStr: numToKeep, + artifactNumToKeepStr: numToKeep + )) + ]); stage('Checkout') { if (env.BRANCH_NAME && env.BRANCH_NAME == 'master') { diff --git a/tclint.toml b/tclint.toml new file mode 100644 index 0000000000..4a98b01c7c --- /dev/null +++ b/tclint.toml @@ -0,0 +1,21 @@ +# hardcoded list of paths to exclude while we incrementally lint codebase +# See issue #3268 for tracking +exclude = [ + "flow/results", + "flow/logs", + "flow/designs/asap7/cva6/constraint.sdc", + "tools/OpenROAD", + "tools/yosys", + "tools/yosys-slang", +] + +ignore = [ + "unbraced-expr", +] + +[style] +indent = 2 +line-length = 100 +allow-aligned-sets = true +indent-namespace-eval = false +spaces-in-braces = true \ No newline at end of file diff --git a/tools/AutoTuner/RAY_README.md b/tools/AutoTuner/RAY_README.md deleted file mode 100644 index 8c9fd33ad0..0000000000 --- a/tools/AutoTuner/RAY_README.md +++ /dev/null @@ -1,246 +0,0 @@ -# AutoTuner with Ray cluster at GCP - -This documentation shows how to create a Ray cluster on Google Cloud -Kubernetes Engine (i.e., GKE) and the required support infrastructure to -enable AutoTuner to work properly. The documentation is intended to users -with some familiarity with Google Cloud or other cloud services. For -more details on how to use AutoTuner see the main documentation page -[here](https://openroad-flow-scripts.readthedocs.io/en/latest/user/InstructionsForAutoTuner.html). - -## How to use this document - -If you want to create a new cluster, follow the document from begin to end. - -If you want to run experiments on an existing cluster, make sure you have -all the [Prerequisites](#prerequisites) and then you can jump to [Running -Ray programs with Ray Client](#running-ray-programs-with-ray-client). - -## Prerequisites - -- Google Cloud CLI installed, see instructions [here](https://cloud.google.com/sdk/docs/install). -- Access to an existing Google Cloud project with "Editor" permissions to - create the cluster. To use an existing cluster contact the person who - created the cluster. -- `kubectl` installed and available on your PATH. See instructions bellow. - - -Configure `gcloud` to use the Kubernetes credentials of the newly created -cluster. The credentials allow the use of `kubectl` locally. - -```bash -gcloud components install kubectl -``` - -## Enable GKE - -Follow the Google quickstart guide up to the section "Create a GKE cluster" -[here](https://cloud.google.com/kubernetes-engine/docs/quickstart). The -quickstart guide instructs how to enable GKE (Google's Kubernetes Engine) -start a CLI interface and get the settings for your project. - -## Create a Kubernetes cluster - -Create a GKE cluster using the following `gcloud` command as a guide. Note -that each argument defines a characteristic of the cluster. Furthermore, -the cluster and node pool allocate resources that cost money. Hence, be -mindful when choosing the configuration. For additional information see: - -```bash -gcloud beta container clusters create --help -gcloud beta container node-pools create --help -``` - -```bash -gcloud beta container clusters create "autotuner" \ - --machine-type "e2-standard-8" \ - --image-type "UBUNTU_CONTAINERD" \ - --disk-type "pd-standard" \ - --disk-size "100" \ - --num-nodes "1" \ - --enable-autoscaling \ - --min-nodes "1" \ - --max-nodes "10" -``` - -Configure `gcloud` to use the Kubernetes credentials of the newly created -cluster. The credentials allow the use of `kubectl` locally. - -```bash -gcloud container clusters get-credentials autotuner -``` - -Create a new node pool. This step is optional, however, recommended. The -new pool uses preemptive nodes which are not only cheaper, but also have -a more powerful CPU and have more disk space. - -```bash -gcloud beta container node-pools create "worker-pool" \ - --cluster "autotuner" \ - --machine-type "c2-standard-60" \ - --image-type "UBUNTU_CONTAINERD" \ - --disk-type "pd-standard" \ - --disk-size "2000" \ - --preemptible \ - --num-nodes "3" \ - --enable-autoscaling \ - --min-nodes "1" \ - --max-nodes "625" -``` - -## Create NFS and setup mount options - -NOTE: This tutorial requires a working NFS server. - -To access the NFS mount point in the Ray cluster, we use a NFS helm -chart. You need to modify the helm chart with the information about your -server IP and mount point path. - -### Install NFS Kubernetes provisioner - -```bash -helm repo add nfs-subdir-external-provisioner https://kubernetes-sigs.github.io/nfs-subdir-external-provisioner -helm repo update -``` - -Before installing the helm chart, double check the fields marked with -`TODO` on the file `./nfs/nfs-helm-values.yaml`. The `server` and `path` -need to match the NFS server IP and the path to the exposed folder. -The `nodeSelector` must match the non-preemptive Kubernetes pool. - -```bash -helm install nfs nfs-subdir-external-provisioner/nfs-subdir-external-provisioner -f nfs/nfs-helm-values.yaml -``` - -### Create a PVC - -Create the PVC: - -```bash -kubectl create -f nfs/nfs-pvc.yaml -``` - -## Ray cluster - -The two main files for the helm chart are: - -```bash -helm-chart/templates/raycluster.yaml -helm-chart/values.yaml -``` - -You can restrict the node pool your AutoTuner jobs will use. To create -this policy, replace POOL_NAME with the name of the pool you created on -the previous step. For this tutorial we use `worker-pool`. - -```yaml -nodeSelector: - cloud.google.com/gke-nodepool: POOL_NAME -``` - -### Deploy Ray cluster inside Kubernetes - -Use Helm to deploy a Ray cluster. - -```bash -helm install autotuner ./helm-chart -``` - -### Upgrade deployment - -After the initial deployment, if you change the values inside `./helm-chart` -you need to upgrade the configuration stored at the Kubernetes cluster. - -```bash -helm upgrade autotuner ./helm-chart -``` - -### Useful ways to observe - -Ray dashboard: - -```bash -kubectl port-forward service/autotuner-ray-head 8265 -``` - -Overall cluster status: - -```bash -kubectl get nodes,rayclusters,pods,services,replicaset,pvc,pv -``` - -Ray auto-scaler logs: - -```bash -kubectl logs \ - $(kubectl get pod -l cluster.ray.io/component=operator -o custom-columns=:metadata.name) \ - --tail=100 -f -``` - -### Remove - -First, delete the `RayCluster` custom resource. - -```bash -kubectl delete raycluster autotuner -``` - -Delete the Ray release. - -```bash -helm uninstall autotuner -``` - -## Running Ray programs with Ray Client - -Currently there are three different ways to launch a job on the GKE cluster. -All three methods depend on having `kubectl` installed and correctly setup. - -To configure `gcloud` to use the Kubernetes credentials of a existing cluster. - -```bash -gcloud components install kubectl -gcloud container clusters get-credentials autotuner -``` - -### Using port forwarding - -NOTE: Ray requires that the version of Python on the server and locally -match. The current `openroad/ray` image has Python 3.7.7, make sure your -local machine has at least Python 3.7.x before continuing. - -```bash -pip3 install -U --user 'ray[default,tune]==1.11.0' ax-platform hyperopt nevergrad optuna pandas -pip3 install -U --user colorama==0.4.4 bayesian-optimization==1.4.0 -``` - -Start the port forwarding: - -```bash -kubectl port-forward service/autotuner-ray-head 10001 -``` - -Run the test script locally: - -```bash -python3 kubernetes/run.py -``` - -### Connecting to head node - -Instead of depending on your local environment, you can connect to the head -node of the Ray cluster and run the scripts from there. - -```bash -kubectl exec -it $(kubectl get pod -l cluster.ray.io/component=autotuner-ray-head -o custom-columns=:metadata.name) -- bash -wget https://raw.githubusercontent.com/The-OpenROAD-Project/OpenROAD-flow-scripts/master/tools/AutoTuner/kubernetes/run.py -python run.py -``` - -### Using Kubernetes job submit - -Finally, if you do not wish to keep a terminal session open, you can submit -a Kubernetes job. - -```bash -kubectl create -f kubernetes/submit.yaml -``` diff --git a/tools/AutoTuner/helm-chart/.helmignore b/tools/AutoTuner/helm-chart/.helmignore deleted file mode 100644 index 0e8a0eb36f..0000000000 --- a/tools/AutoTuner/helm-chart/.helmignore +++ /dev/null @@ -1,23 +0,0 @@ -# Patterns to ignore when building packages. -# This supports shell glob matching, relative path matching, and -# negation (prefixed with !). Only one pattern per line. -.DS_Store -# Common VCS dirs -.git/ -.gitignore -.bzr/ -.bzrignore -.hg/ -.hgignore -.svn/ -# Common backup files -*.swp -*.bak -*.tmp -*.orig -*~ -# Various IDEs -.project -.idea/ -*.tmproj -.vscode/ diff --git a/tools/AutoTuner/helm-chart/Chart.yaml b/tools/AutoTuner/helm-chart/Chart.yaml deleted file mode 100644 index b2148b1ace..0000000000 --- a/tools/AutoTuner/helm-chart/Chart.yaml +++ /dev/null @@ -1,10 +0,0 @@ -apiVersion: v2 -name: ray -description: A Helm chart for deployments of Ray on Kubernetes. -type: application - -# Chart version. -version: 0.1.0 - -# Ray version. -appVersion: "latest" diff --git a/tools/AutoTuner/helm-chart/crds/cluster_crd.yaml b/tools/AutoTuner/helm-chart/crds/cluster_crd.yaml deleted file mode 100644 index 6db9d73a97..0000000000 --- a/tools/AutoTuner/helm-chart/crds/cluster_crd.yaml +++ /dev/null @@ -1,4321 +0,0 @@ -apiVersion: apiextensions.k8s.io/v1 -kind: CustomResourceDefinition -metadata: - name: rayclusters.cluster.ray.io -spec: - group: cluster.ray.io - scope: Namespaced - names: - plural: rayclusters - singular: raycluster - kind: RayCluster - versions: - - name: v1 - served: true - storage: true - subresources: - status: {} - additionalPrinterColumns: - - name: status - type: string - description: Updating, Running, Error, or AutoscalingExceptionRecovery - jsonPath: .status.phase - - name: restarts - type: integer - description: Number of Ray cluster restarts triggered by autoscaler failure. - jsonPath: .status.autoscalerRetries - - name: age - type: date - jsonPath: .metadata.creationTimestamp - schema: - openAPIV3Schema: - description: Ray cluster configuration - type: object - required: - - spec - properties: - status: - type: object - x-kubernetes-preserve-unknown-fields: true - properties: - phase: - description: Updating, Running, Error, or AutoscalingExceptionRecovery - type: string - autoscalerRetries: - description: Number of Ray cluster restarts triggered by autoscaler failure. - type: integer - spec: - type: object - required: - - podTypes - - headPodType - properties: - maxWorkers: - description: The maximum number of workers nodes to launch in addition to the - head node. - type: integer - minimum: 0 - upscalingSpeed: - description: The autoscaler will scale up the cluster faster with higher upscaling - speed. E.g., if the task requires adding more nodes then autoscaler will gradually - scale up the cluster in chunks of upscalingSpeed*currentlyRunningNodes. This - number should be > 0. - type: number - minimum: 0 - idleTimeoutMinutes: - description: If a node is idle for this many minutes, it will be removed. - type: integer - minimum: 0 - headServicePorts: - description: Optional list of ports to use for the Ray head service. - type: array - items: - type: object - required: - - name - - port - - targetPort - properties: - name: - type: string - port: - type: integer - targetPort: - x-kubernetes-int-or-string: true - podTypes: - description: A list of Pod types on which to run Ray nodes, for multi-node-type autoscaling. - type: array - items: - type: object - required: - - name - - podConfig - properties: - name: - type: string - description: Name of the Pod type. - minWorkers: - type: integer - description: Minimum number of Ray workers of this Pod type. - maxWorkers: - type: integer - description: Maximum number of Ray workers of this Pod type. - rayResources: - type: object - description: User-specified custom resources for use by Ray. Keys strings, values integers. - # TODO (dmitri): Validate that values are integers [patternProperties not supported by OpenAPI v3.0] - x-kubernetes-preserve-unknown-fields: true - setupCommands: - description: Alias for workerSetupCommands - type: array - items: - type: string - description: shell command - workerSetupCommands: - description: Commands to run before starting the Ray runtime for workers of this podType. - type: array - items: - type: string - description: shell command - podConfig: - type: object - description: Pod configuration. - x-kubernetes-embedded-resource: true - properties: - spec: - description: PodSpec is a description of a pod. - properties: - activeDeadlineSeconds: - description: Optional duration in seconds the pod may be active - on the node relative to StartTime before the system will actively - try to mark it failed and kill associated containers. Value - must be a positive integer. - format: int64 - type: integer - affinity: - description: If specified, the pod's scheduling constraints - properties: - nodeAffinity: - description: Describes node affinity scheduling rules for - the pod. - properties: - preferredDuringSchedulingIgnoredDuringExecution: - description: The scheduler will prefer to schedule pods - to nodes that satisfy the affinity expressions specified - by this field, but it may choose a node that violates - one or more of the expressions. The node that is most - preferred is the one with the greatest sum of weights, - i.e. for each node that meets all of the scheduling - requirements (resource request, requiredDuringScheduling - affinity expressions, etc.), compute a sum by iterating - through the elements of this field and adding "weight" - to the sum if the node matches the corresponding matchExpressions; - the node(s) with the highest sum are the most preferred. - items: - description: An empty preferred scheduling term matches - all objects with implicit weight 0 (i.e. it's a - no-op). A null preferred scheduling term matches - no objects (i.e. is also a no-op). - properties: - preference: - description: A node selector term, associated - with the corresponding weight. - properties: - matchExpressions: - description: A list of node selector requirements - by node's labels. - items: - description: A node selector requirement - is a selector that contains values, a - key, and an operator that relates the - key and values. - properties: - key: - description: The label key that the - selector applies to. - type: string - operator: - description: Represents a key's relationship - to a set of values. Valid operators - are In, NotIn, Exists, DoesNotExist. - Gt, and Lt. - type: string - values: - description: An array of string values. - If the operator is In or NotIn, the - values array must be non-empty. If - the operator is Exists or DoesNotExist, - the values array must be empty. If - the operator is Gt or Lt, the values - array must have a single element, - which will be interpreted as an integer. - This array is replaced during a strategic - merge patch. - items: - type: string - type: array - required: - - key - - operator - type: object - type: array - matchFields: - description: A list of node selector requirements - by node's fields. - items: - description: A node selector requirement - is a selector that contains values, a - key, and an operator that relates the - key and values. - properties: - key: - description: The label key that the - selector applies to. - type: string - operator: - description: Represents a key's relationship - to a set of values. Valid operators - are In, NotIn, Exists, DoesNotExist. - Gt, and Lt. - type: string - values: - description: An array of string values. - If the operator is In or NotIn, the - values array must be non-empty. If - the operator is Exists or DoesNotExist, - the values array must be empty. If - the operator is Gt or Lt, the values - array must have a single element, - which will be interpreted as an integer. - This array is replaced during a strategic - merge patch. - items: - type: string - type: array - required: - - key - - operator - type: object - type: array - type: object - weight: - description: Weight associated with matching the - corresponding nodeSelectorTerm, in the range - 1-100. - format: int32 - type: integer - required: - - preference - - weight - type: object - type: array - requiredDuringSchedulingIgnoredDuringExecution: - description: If the affinity requirements specified - by this field are not met at scheduling time, the - pod will not be scheduled onto the node. If the affinity - requirements specified by this field cease to be met - at some point during pod execution (e.g. due to an - update), the system may or may not try to eventually - evict the pod from its node. - properties: - nodeSelectorTerms: - description: Required. A list of node selector terms. - The terms are ORed. - items: - description: A null or empty node selector term - matches no objects. The requirements of them - are ANDed. The TopologySelectorTerm type implements - a subset of the NodeSelectorTerm. - properties: - matchExpressions: - description: A list of node selector requirements - by node's labels. - items: - description: A node selector requirement - is a selector that contains values, a - key, and an operator that relates the - key and values. - properties: - key: - description: The label key that the - selector applies to. - type: string - operator: - description: Represents a key's relationship - to a set of values. Valid operators - are In, NotIn, Exists, DoesNotExist. - Gt, and Lt. - type: string - values: - description: An array of string values. - If the operator is In or NotIn, the - values array must be non-empty. If - the operator is Exists or DoesNotExist, - the values array must be empty. If - the operator is Gt or Lt, the values - array must have a single element, - which will be interpreted as an integer. - This array is replaced during a strategic - merge patch. - items: - type: string - type: array - required: - - key - - operator - type: object - type: array - matchFields: - description: A list of node selector requirements - by node's fields. - items: - description: A node selector requirement - is a selector that contains values, a - key, and an operator that relates the - key and values. - properties: - key: - description: The label key that the - selector applies to. - type: string - operator: - description: Represents a key's relationship - to a set of values. Valid operators - are In, NotIn, Exists, DoesNotExist. - Gt, and Lt. - type: string - values: - description: An array of string values. - If the operator is In or NotIn, the - values array must be non-empty. If - the operator is Exists or DoesNotExist, - the values array must be empty. If - the operator is Gt or Lt, the values - array must have a single element, - which will be interpreted as an integer. - This array is replaced during a strategic - merge patch. - items: - type: string - type: array - required: - - key - - operator - type: object - type: array - type: object - type: array - required: - - nodeSelectorTerms - type: object - type: object - podAffinity: - description: Describes pod affinity scheduling rules (e.g. - co-locate this pod in the same node, zone, etc. as some - other pod(s)). - properties: - preferredDuringSchedulingIgnoredDuringExecution: - description: The scheduler will prefer to schedule pods - to nodes that satisfy the affinity expressions specified - by this field, but it may choose a node that violates - one or more of the expressions. The node that is most - preferred is the one with the greatest sum of weights, - i.e. for each node that meets all of the scheduling - requirements (resource request, requiredDuringScheduling - affinity expressions, etc.), compute a sum by iterating - through the elements of this field and adding "weight" - to the sum if the node has pods which matches the - corresponding podAffinityTerm; the node(s) with the - highest sum are the most preferred. - items: - description: The weights of all of the matched WeightedPodAffinityTerm - fields are added per-node to find the most preferred - node(s) - properties: - podAffinityTerm: - description: Required. A pod affinity term, associated - with the corresponding weight. - properties: - labelSelector: - description: A label query over a set of resources, - in this case pods. - properties: - matchExpressions: - description: matchExpressions is a list - of label selector requirements. The - requirements are ANDed. - items: - description: A label selector requirement - is a selector that contains values, - a key, and an operator that relates - the key and values. - properties: - key: - description: key is the label key - that the selector applies to. - type: string - operator: - description: operator represents - a key's relationship to a set - of values. Valid operators are - In, NotIn, Exists and DoesNotExist. - type: string - values: - description: values is an array - of string values. If the operator - is In or NotIn, the values array - must be non-empty. If the operator - is Exists or DoesNotExist, the - values array must be empty. This - array is replaced during a strategic - merge patch. - items: - type: string - type: array - required: - - key - - operator - type: object - type: array - matchLabels: - additionalProperties: - type: string - description: matchLabels is a map of {key,value} - pairs. A single {key,value} in the matchLabels - map is equivalent to an element of matchExpressions, - whose key field is "key", the operator - is "In", and the values array contains - only "value". The requirements are ANDed. - type: object - type: object - namespaces: - description: namespaces specifies which namespaces - the labelSelector applies to (matches against); - null or empty list means "this pod's namespace" - items: - type: string - type: array - topologyKey: - description: This pod should be co-located - (affinity) or not co-located (anti-affinity) - with the pods matching the labelSelector - in the specified namespaces, where co-located - is defined as running on a node whose value - of the label with key topologyKey matches - that of any node on which any of the selected - pods is running. Empty topologyKey is not - allowed. - type: string - required: - - topologyKey - type: object - weight: - description: weight associated with matching the - corresponding podAffinityTerm, in the range - 1-100. - format: int32 - type: integer - required: - - podAffinityTerm - - weight - type: object - type: array - requiredDuringSchedulingIgnoredDuringExecution: - description: If the affinity requirements specified - by this field are not met at scheduling time, the - pod will not be scheduled onto the node. If the affinity - requirements specified by this field cease to be met - at some point during pod execution (e.g. due to a - pod label update), the system may or may not try to - eventually evict the pod from its node. When there - are multiple elements, the lists of nodes corresponding - to each podAffinityTerm are intersected, i.e. all - terms must be satisfied. - items: - description: Defines a set of pods (namely those matching - the labelSelector relative to the given namespace(s)) - that this pod should be co-located (affinity) or - not co-located (anti-affinity) with, where co-located - is defined as running on a node whose value of the - label with key matches that of any - node on which a pod of the set of pods is running - properties: - labelSelector: - description: A label query over a set of resources, - in this case pods. - properties: - matchExpressions: - description: matchExpressions is a list of - label selector requirements. The requirements - are ANDed. - items: - description: A label selector requirement - is a selector that contains values, a - key, and an operator that relates the - key and values. - properties: - key: - description: key is the label key that - the selector applies to. - type: string - operator: - description: operator represents a key's - relationship to a set of values. Valid - operators are In, NotIn, Exists and - DoesNotExist. - type: string - values: - description: values is an array of string - values. If the operator is In or NotIn, - the values array must be non-empty. - If the operator is Exists or DoesNotExist, - the values array must be empty. This - array is replaced during a strategic - merge patch. - items: - type: string - type: array - required: - - key - - operator - type: object - type: array - matchLabels: - additionalProperties: - type: string - description: matchLabels is a map of {key,value} - pairs. A single {key,value} in the matchLabels - map is equivalent to an element of matchExpressions, - whose key field is "key", the operator is - "In", and the values array contains only - "value". The requirements are ANDed. - type: object - type: object - namespaces: - description: namespaces specifies which namespaces - the labelSelector applies to (matches against); - null or empty list means "this pod's namespace" - items: - type: string - type: array - topologyKey: - description: This pod should be co-located (affinity) - or not co-located (anti-affinity) with the pods - matching the labelSelector in the specified - namespaces, where co-located is defined as running - on a node whose value of the label with key - topologyKey matches that of any node on which - any of the selected pods is running. Empty topologyKey - is not allowed. - type: string - required: - - topologyKey - type: object - type: array - type: object - podAntiAffinity: - description: Describes pod anti-affinity scheduling rules - (e.g. avoid putting this pod in the same node, zone, etc. - as some other pod(s)). - properties: - preferredDuringSchedulingIgnoredDuringExecution: - description: The scheduler will prefer to schedule pods - to nodes that satisfy the anti-affinity expressions - specified by this field, but it may choose a node - that violates one or more of the expressions. The - node that is most preferred is the one with the greatest - sum of weights, i.e. for each node that meets all - of the scheduling requirements (resource request, - requiredDuringScheduling anti-affinity expressions, - etc.), compute a sum by iterating through the elements - of this field and adding "weight" to the sum if the - node has pods which matches the corresponding podAffinityTerm; - the node(s) with the highest sum are the most preferred. - items: - description: The weights of all of the matched WeightedPodAffinityTerm - fields are added per-node to find the most preferred - node(s) - properties: - podAffinityTerm: - description: Required. A pod affinity term, associated - with the corresponding weight. - properties: - labelSelector: - description: A label query over a set of resources, - in this case pods. - properties: - matchExpressions: - description: matchExpressions is a list - of label selector requirements. The - requirements are ANDed. - items: - description: A label selector requirement - is a selector that contains values, - a key, and an operator that relates - the key and values. - properties: - key: - description: key is the label key - that the selector applies to. - type: string - operator: - description: operator represents - a key's relationship to a set - of values. Valid operators are - In, NotIn, Exists and DoesNotExist. - type: string - values: - description: values is an array - of string values. If the operator - is In or NotIn, the values array - must be non-empty. If the operator - is Exists or DoesNotExist, the - values array must be empty. This - array is replaced during a strategic - merge patch. - items: - type: string - type: array - required: - - key - - operator - type: object - type: array - matchLabels: - additionalProperties: - type: string - description: matchLabels is a map of {key,value} - pairs. A single {key,value} in the matchLabels - map is equivalent to an element of matchExpressions, - whose key field is "key", the operator - is "In", and the values array contains - only "value". The requirements are ANDed. - type: object - type: object - namespaces: - description: namespaces specifies which namespaces - the labelSelector applies to (matches against); - null or empty list means "this pod's namespace" - items: - type: string - type: array - topologyKey: - description: This pod should be co-located - (affinity) or not co-located (anti-affinity) - with the pods matching the labelSelector - in the specified namespaces, where co-located - is defined as running on a node whose value - of the label with key topologyKey matches - that of any node on which any of the selected - pods is running. Empty topologyKey is not - allowed. - type: string - required: - - topologyKey - type: object - weight: - description: weight associated with matching the - corresponding podAffinityTerm, in the range - 1-100. - format: int32 - type: integer - required: - - podAffinityTerm - - weight - type: object - type: array - requiredDuringSchedulingIgnoredDuringExecution: - description: If the anti-affinity requirements specified - by this field are not met at scheduling time, the - pod will not be scheduled onto the node. If the anti-affinity - requirements specified by this field cease to be met - at some point during pod execution (e.g. due to a - pod label update), the system may or may not try to - eventually evict the pod from its node. When there - are multiple elements, the lists of nodes corresponding - to each podAffinityTerm are intersected, i.e. all - terms must be satisfied. - items: - description: Defines a set of pods (namely those matching - the labelSelector relative to the given namespace(s)) - that this pod should be co-located (affinity) or - not co-located (anti-affinity) with, where co-located - is defined as running on a node whose value of the - label with key matches that of any - node on which a pod of the set of pods is running - properties: - labelSelector: - description: A label query over a set of resources, - in this case pods. - properties: - matchExpressions: - description: matchExpressions is a list of - label selector requirements. The requirements - are ANDed. - items: - description: A label selector requirement - is a selector that contains values, a - key, and an operator that relates the - key and values. - properties: - key: - description: key is the label key that - the selector applies to. - type: string - operator: - description: operator represents a key's - relationship to a set of values. Valid - operators are In, NotIn, Exists and - DoesNotExist. - type: string - values: - description: values is an array of string - values. If the operator is In or NotIn, - the values array must be non-empty. - If the operator is Exists or DoesNotExist, - the values array must be empty. This - array is replaced during a strategic - merge patch. - items: - type: string - type: array - required: - - key - - operator - type: object - type: array - matchLabels: - additionalProperties: - type: string - description: matchLabels is a map of {key,value} - pairs. A single {key,value} in the matchLabels - map is equivalent to an element of matchExpressions, - whose key field is "key", the operator is - "In", and the values array contains only - "value". The requirements are ANDed. - type: object - type: object - namespaces: - description: namespaces specifies which namespaces - the labelSelector applies to (matches against); - null or empty list means "this pod's namespace" - items: - type: string - type: array - topologyKey: - description: This pod should be co-located (affinity) - or not co-located (anti-affinity) with the pods - matching the labelSelector in the specified - namespaces, where co-located is defined as running - on a node whose value of the label with key - topologyKey matches that of any node on which - any of the selected pods is running. Empty topologyKey - is not allowed. - type: string - required: - - topologyKey - type: object - type: array - type: object - type: object - automountServiceAccountToken: - description: AutomountServiceAccountToken indicates whether - a service account token should be automatically mounted. - type: boolean - containers: - description: List of containers belonging to the pod. Containers - cannot currently be added or removed. There must be at least - one container in a Pod. Cannot be updated. - items: - description: A single application container that you want - to run within a pod. - properties: - args: - description: 'Arguments to the entrypoint. The docker - image''s CMD is used if this is not provided. Variable - references $(VAR_NAME) are expanded using the container''s - environment. If a variable cannot be resolved, the reference - in the input string will be unchanged. The $(VAR_NAME) - syntax can be escaped with a double $$, ie: $$(VAR_NAME). - Escaped references will never be expanded, regardless - of whether the variable exists or not. Cannot be updated. - More info: https://kubernetes.io/docs/tasks/inject-data-application/define-command-argument-container/#running-a-command-in-a-shell' - items: - type: string - type: array - command: - description: 'Entrypoint array. Not executed within a - shell. The docker image''s ENTRYPOINT is used if this - is not provided. Variable references $(VAR_NAME) are - expanded using the container''s environment. If a variable - cannot be resolved, the reference in the input string - will be unchanged. The $(VAR_NAME) syntax can be escaped - with a double $$, ie: $$(VAR_NAME). Escaped references - will never be expanded, regardless of whether the variable - exists or not. Cannot be updated. More info: https://kubernetes.io/docs/tasks/inject-data-application/define-command-argument-container/#running-a-command-in-a-shell' - items: - type: string - type: array - env: - description: List of environment variables to set in the - container. Cannot be updated. - items: - description: EnvVar represents an environment variable - present in a Container. - properties: - name: - description: Name of the environment variable. Must - be a C_IDENTIFIER. - type: string - value: - description: 'Variable references $(VAR_NAME) are - expanded using the previous defined environment - variables in the container and any service environment - variables. If a variable cannot be resolved, the - reference in the input string will be unchanged. - The $(VAR_NAME) syntax can be escaped with a double - $$, ie: $$(VAR_NAME). Escaped references will - never be expanded, regardless of whether the variable - exists or not. Defaults to "".' - type: string - valueFrom: - description: Source for the environment variable's - value. Cannot be used if value is not empty. - properties: - configMapKeyRef: - description: Selects a key of a ConfigMap. - properties: - key: - description: The key to select. - type: string - name: - description: 'Name of the referent. More - info: https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the ConfigMap - or it's key must be defined - type: boolean - required: - - key - type: object - fieldRef: - description: 'Selects a field of the pod: supports - metadata.name, metadata.namespace, metadata.labels, - metadata.annotations, spec.nodeName, spec.serviceAccountName, - status.hostIP, status.podIP.' - properties: - apiVersion: - description: Version of the schema the FieldPath - is written in terms of, defaults to "v1". - type: string - fieldPath: - description: Path of the field to select - in the specified API version. - type: string - required: - - fieldPath - type: object - resourceFieldRef: - description: 'Selects a resource of the container: - only resources limits and requests (limits.cpu, - limits.memory, limits.ephemeral-storage, requests.cpu, - requests.memory and requests.ephemeral-storage) - are currently supported.' - properties: - containerName: - description: 'Container name: required for - volumes, optional for env vars' - type: string - divisor: - anyOf: - - type: integer - - type: string - description: Specifies the output format - of the exposed resources, defaults to - "1" - pattern: ^(\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))(([KMGTPE]i)|[numkMGTPE]|([eE](\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))))?$ - x-kubernetes-int-or-string: true - resource: - description: 'Required: resource to select' - type: string - required: - - resource - type: object - secretKeyRef: - description: Selects a key of a secret in the - pod's namespace - properties: - key: - description: The key of the secret to select - from. Must be a valid secret key. - type: string - name: - description: 'Name of the referent. More - info: https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the Secret - or it's key must be defined - type: boolean - required: - - key - type: object - type: object - required: - - name - type: object - type: array - envFrom: - description: List of sources to populate environment variables - in the container. The keys defined within a source must - be a C_IDENTIFIER. All invalid keys will be reported - as an event when the container is starting. When a key - exists in multiple sources, the value associated with - the last source will take precedence. Values defined - by an Env with a duplicate key will take precedence. - Cannot be updated. - items: - description: EnvFromSource represents the source of - a set of ConfigMaps - properties: - configMapRef: - description: The ConfigMap to select from - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the ConfigMap must - be defined - type: boolean - type: object - prefix: - description: An optional identifier to prepend to - each key in the ConfigMap. Must be a C_IDENTIFIER. - type: string - secretRef: - description: The Secret to select from - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the Secret must - be defined - type: boolean - type: object - type: object - type: array - image: - description: 'Docker image name. More info: https://kubernetes.io/docs/concepts/containers/images - This field is optional to allow higher level config - management to default or override container images in - workload controllers like Deployments and StatefulSets.' - type: string - imagePullPolicy: - description: 'Image pull policy. One of Always, Never, - IfNotPresent. Defaults to Always if :latest tag is specified, - or IfNotPresent otherwise. Cannot be updated. More info: - https://kubernetes.io/docs/concepts/containers/images#updating-images' - type: string - lifecycle: - description: Actions that the management system should - take in response to container lifecycle events. Cannot - be updated. - properties: - postStart: - description: 'PostStart is called immediately after - a container is created. If the handler fails, the - container is terminated and restarted according - to its restart policy. Other management of the container - blocks until the hook completes. More info: https://kubernetes.io/docs/concepts/containers/container-lifecycle-hooks/#container-hooks' - properties: - exec: - description: One and only one of the following - should be specified. Exec specifies the action - to take. - properties: - command: - description: Command is the command line to - execute inside the container, the working - directory for the command is root ('/') - in the container's filesystem. The command - is simply exec'd, it is not run inside a - shell, so traditional shell instructions - ('|', etc) won't work. To use a shell, you - need to explicitly call out to that shell. - Exit status of 0 is treated as live/healthy - and non-zero is unhealthy. - items: - type: string - type: array - type: object - httpGet: - description: HTTPGet specifies the http request - to perform. - properties: - host: - description: Host name to connect to, defaults - to the pod IP. You probably want to set - "Host" in httpHeaders instead. - type: string - httpHeaders: - description: Custom headers to set in the - request. HTTP allows repeated headers. - items: - description: HTTPHeader describes a custom - header to be used in HTTP probes - properties: - name: - description: The header field name - type: string - value: - description: The header field value - type: string - required: - - name - - value - type: object - type: array - path: - description: Path to access on the HTTP server. - type: string - port: - anyOf: - - type: integer - - type: string - description: Name or number of the port to - access on the container. Number must be - in the range 1 to 65535. Name must be an - IANA_SVC_NAME. - x-kubernetes-int-or-string: true - scheme: - description: Scheme to use for connecting - to the host. Defaults to HTTP. - type: string - required: - - port - type: object - tcpSocket: - description: 'TCPSocket specifies an action involving - a TCP port. TCP hooks not yet supported TODO: - implement a realistic TCP lifecycle hook' - properties: - host: - description: 'Optional: Host name to connect - to, defaults to the pod IP.' - type: string - port: - anyOf: - - type: integer - - type: string - description: Number or name of the port to - access on the container. Number must be - in the range 1 to 65535. Name must be an - IANA_SVC_NAME. - x-kubernetes-int-or-string: true - required: - - port - type: object - type: object - preStop: - description: 'PreStop is called immediately before - a container is terminated due to an API request - or management event such as liveness probe failure, - preemption, resource contention, etc. The handler - is not called if the container crashes or exits. - The reason for termination is passed to the handler. - The Pod''s termination grace period countdown begins - before the PreStop hooked is executed. Regardless - of the outcome of the handler, the container will - eventually terminate within the Pod''s termination - grace period. Other management of the container - blocks until the hook completes or until the termination - grace period is reached. More info: https://kubernetes.io/docs/concepts/containers/container-lifecycle-hooks/#container-hooks' - properties: - exec: - description: One and only one of the following - should be specified. Exec specifies the action - to take. - properties: - command: - description: Command is the command line to - execute inside the container, the working - directory for the command is root ('/') - in the container's filesystem. The command - is simply exec'd, it is not run inside a - shell, so traditional shell instructions - ('|', etc) won't work. To use a shell, you - need to explicitly call out to that shell. - Exit status of 0 is treated as live/healthy - and non-zero is unhealthy. - items: - type: string - type: array - type: object - httpGet: - description: HTTPGet specifies the http request - to perform. - properties: - host: - description: Host name to connect to, defaults - to the pod IP. You probably want to set - "Host" in httpHeaders instead. - type: string - httpHeaders: - description: Custom headers to set in the - request. HTTP allows repeated headers. - items: - description: HTTPHeader describes a custom - header to be used in HTTP probes - properties: - name: - description: The header field name - type: string - value: - description: The header field value - type: string - required: - - name - - value - type: object - type: array - path: - description: Path to access on the HTTP server. - type: string - port: - anyOf: - - type: integer - - type: string - description: Name or number of the port to - access on the container. Number must be - in the range 1 to 65535. Name must be an - IANA_SVC_NAME. - x-kubernetes-int-or-string: true - scheme: - description: Scheme to use for connecting - to the host. Defaults to HTTP. - type: string - required: - - port - type: object - tcpSocket: - description: 'TCPSocket specifies an action involving - a TCP port. TCP hooks not yet supported TODO: - implement a realistic TCP lifecycle hook' - properties: - host: - description: 'Optional: Host name to connect - to, defaults to the pod IP.' - type: string - port: - anyOf: - - type: integer - - type: string - description: Number or name of the port to - access on the container. Number must be - in the range 1 to 65535. Name must be an - IANA_SVC_NAME. - x-kubernetes-int-or-string: true - required: - - port - type: object - type: object - type: object - livenessProbe: - description: 'Periodic probe of container liveness. Container - will be restarted if the probe fails. Cannot be updated. - More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - properties: - exec: - description: One and only one of the following should - be specified. Exec specifies the action to take. - properties: - command: - description: Command is the command line to execute - inside the container, the working directory - for the command is root ('/') in the container's - filesystem. The command is simply exec'd, it - is not run inside a shell, so traditional shell - instructions ('|', etc) won't work. To use a - shell, you need to explicitly call out to that - shell. Exit status of 0 is treated as live/healthy - and non-zero is unhealthy. - items: - type: string - type: array - type: object - failureThreshold: - description: Minimum consecutive failures for the - probe to be considered failed after having succeeded. - Defaults to 3. Minimum value is 1. - format: int32 - type: integer - httpGet: - description: HTTPGet specifies the http request to - perform. - properties: - host: - description: Host name to connect to, defaults - to the pod IP. You probably want to set "Host" - in httpHeaders instead. - type: string - httpHeaders: - description: Custom headers to set in the request. - HTTP allows repeated headers. - items: - description: HTTPHeader describes a custom header - to be used in HTTP probes - properties: - name: - description: The header field name - type: string - value: - description: The header field value - type: string - required: - - name - - value - type: object - type: array - path: - description: Path to access on the HTTP server. - type: string - port: - anyOf: - - type: integer - - type: string - description: Name or number of the port to access - on the container. Number must be in the range - 1 to 65535. Name must be an IANA_SVC_NAME. - x-kubernetes-int-or-string: true - scheme: - description: Scheme to use for connecting to the - host. Defaults to HTTP. - type: string - required: - - port - type: object - initialDelaySeconds: - description: 'Number of seconds after the container - has started before liveness probes are initiated. - More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - format: int32 - type: integer - periodSeconds: - description: How often (in seconds) to perform the - probe. Default to 10 seconds. Minimum value is 1. - format: int32 - type: integer - successThreshold: - description: Minimum consecutive successes for the - probe to be considered successful after having failed. - Defaults to 1. Must be 1 for liveness. Minimum value - is 1. - format: int32 - type: integer - tcpSocket: - description: 'TCPSocket specifies an action involving - a TCP port. TCP hooks not yet supported TODO: implement - a realistic TCP lifecycle hook' - properties: - host: - description: 'Optional: Host name to connect to, - defaults to the pod IP.' - type: string - port: - anyOf: - - type: integer - - type: string - description: Number or name of the port to access - on the container. Number must be in the range - 1 to 65535. Name must be an IANA_SVC_NAME. - x-kubernetes-int-or-string: true - required: - - port - type: object - timeoutSeconds: - description: 'Number of seconds after which the probe - times out. Defaults to 1 second. Minimum value is - 1. More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - format: int32 - type: integer - type: object - name: - description: Name of the container specified as a DNS_LABEL. - Each container in a pod must have a unique name (DNS_LABEL). - Cannot be updated. - type: string - ports: - description: List of ports to expose from the container. - Exposing a port here gives the system additional information - about the network connections a container uses, but - is primarily informational. Not specifying a port here - DOES NOT prevent that port from being exposed. Any port - which is listening on the default "0.0.0.0" address - inside a container will be accessible from the network. - Cannot be updated. - items: - description: ContainerPort represents a network port - in a single container. - properties: - containerPort: - description: Number of port to expose on the pod's - IP address. This must be a valid port number, - 0 < x < 65536. - format: int32 - type: integer - hostIP: - description: What host IP to bind the external port - to. - type: string - hostPort: - description: Number of port to expose on the host. - If specified, this must be a valid port number, - 0 < x < 65536. If HostNetwork is specified, this - must match ContainerPort. Most containers do not - need this. - format: int32 - type: integer - name: - description: If specified, this must be an IANA_SVC_NAME - and unique within the pod. Each named port in - a pod must have a unique name. Name for the port - that can be referred to by services. - type: string - protocol: - description: Protocol for port. Must be UDP, TCP, - or SCTP. Defaults to "TCP". - type: string - default: TCP - required: - - containerPort - type: object - type: array - x-kubernetes-list-map-keys: - - containerPort - - protocol - x-kubernetes-list-type: map - readinessProbe: - description: 'Periodic probe of container service readiness. - Container will be removed from service endpoints if - the probe fails. Cannot be updated. More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - properties: - exec: - description: One and only one of the following should - be specified. Exec specifies the action to take. - properties: - command: - description: Command is the command line to execute - inside the container, the working directory - for the command is root ('/') in the container's - filesystem. The command is simply exec'd, it - is not run inside a shell, so traditional shell - instructions ('|', etc) won't work. To use a - shell, you need to explicitly call out to that - shell. Exit status of 0 is treated as live/healthy - and non-zero is unhealthy. - items: - type: string - type: array - type: object - failureThreshold: - description: Minimum consecutive failures for the - probe to be considered failed after having succeeded. - Defaults to 3. Minimum value is 1. - format: int32 - type: integer - httpGet: - description: HTTPGet specifies the http request to - perform. - properties: - host: - description: Host name to connect to, defaults - to the pod IP. You probably want to set "Host" - in httpHeaders instead. - type: string - httpHeaders: - description: Custom headers to set in the request. - HTTP allows repeated headers. - items: - description: HTTPHeader describes a custom header - to be used in HTTP probes - properties: - name: - description: The header field name - type: string - value: - description: The header field value - type: string - required: - - name - - value - type: object - type: array - path: - description: Path to access on the HTTP server. - type: string - port: - anyOf: - - type: integer - - type: string - description: Name or number of the port to access - on the container. Number must be in the range - 1 to 65535. Name must be an IANA_SVC_NAME. - x-kubernetes-int-or-string: true - scheme: - description: Scheme to use for connecting to the - host. Defaults to HTTP. - type: string - required: - - port - type: object - initialDelaySeconds: - description: 'Number of seconds after the container - has started before liveness probes are initiated. - More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - format: int32 - type: integer - periodSeconds: - description: How often (in seconds) to perform the - probe. Default to 10 seconds. Minimum value is 1. - format: int32 - type: integer - successThreshold: - description: Minimum consecutive successes for the - probe to be considered successful after having failed. - Defaults to 1. Must be 1 for liveness. Minimum value - is 1. - format: int32 - type: integer - tcpSocket: - description: 'TCPSocket specifies an action involving - a TCP port. TCP hooks not yet supported TODO: implement - a realistic TCP lifecycle hook' - properties: - host: - description: 'Optional: Host name to connect to, - defaults to the pod IP.' - type: string - port: - anyOf: - - type: integer - - type: string - description: Number or name of the port to access - on the container. Number must be in the range - 1 to 65535. Name must be an IANA_SVC_NAME. - x-kubernetes-int-or-string: true - required: - - port - type: object - timeoutSeconds: - description: 'Number of seconds after which the probe - times out. Defaults to 1 second. Minimum value is - 1. More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - format: int32 - type: integer - type: object - resources: - description: 'Compute Resources required by this container. - Cannot be updated. More info: https://kubernetes.io/docs/concepts/configuration/manage-compute-resources-container/' - properties: - limits: - additionalProperties: - anyOf: - - type: integer - - type: string - pattern: ^(\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))(([KMGTPE]i)|[numkMGTPE]|([eE](\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))))?$ - x-kubernetes-int-or-string: true - description: 'Limits describes the maximum amount - of compute resources allowed. More info: https://kubernetes.io/docs/concepts/configuration/manage-compute-resources-container/' - type: object - requests: - additionalProperties: - anyOf: - - type: integer - - type: string - pattern: ^(\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))(([KMGTPE]i)|[numkMGTPE]|([eE](\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))))?$ - x-kubernetes-int-or-string: true - description: 'Requests describes the minimum amount - of compute resources required. If Requests is omitted - for a container, it defaults to Limits if that is - explicitly specified, otherwise to an implementation-defined - value. More info: https://kubernetes.io/docs/concepts/configuration/manage-compute-resources-container/' - type: object - type: object - securityContext: - description: 'Security options the pod should run with. - More info: https://kubernetes.io/docs/concepts/policy/security-context/ - More info: https://kubernetes.io/docs/tasks/configure-pod-container/security-context/' - properties: - allowPrivilegeEscalation: - description: 'AllowPrivilegeEscalation controls whether - a process can gain more privileges than its parent - process. This bool directly controls if the no_new_privs - flag will be set on the container process. AllowPrivilegeEscalation - is true always when the container is: 1) run as - Privileged 2) has CAP_SYS_ADMIN' - type: boolean - capabilities: - description: The capabilities to add/drop when running - containers. Defaults to the default set of capabilities - granted by the container runtime. - properties: - add: - description: Added capabilities - items: - description: Capability represent POSIX capabilities - type - type: string - type: array - drop: - description: Removed capabilities - items: - description: Capability represent POSIX capabilities - type - type: string - type: array - type: object - privileged: - description: Run container in privileged mode. Processes - in privileged containers are essentially equivalent - to root on the host. Defaults to false. - type: boolean - procMount: - description: procMount denotes the type of proc mount - to use for the containers. The default is DefaultProcMount - which uses the container runtime defaults for readonly - paths and masked paths. This requires the ProcMountType - feature flag to be enabled. - type: string - readOnlyRootFilesystem: - description: Whether this container has a read-only - root filesystem. Default is false. - type: boolean - runAsGroup: - description: The GID to run the entrypoint of the - container process. Uses runtime default if unset. - May also be set in PodSecurityContext. If set in - both SecurityContext and PodSecurityContext, the - value specified in SecurityContext takes precedence. - format: int64 - type: integer - runAsNonRoot: - description: Indicates that the container must run - as a non-root user. If true, the Kubelet will validate - the image at runtime to ensure that it does not - run as UID 0 (root) and fail to start the container - if it does. If unset or false, no such validation - will be performed. May also be set in PodSecurityContext. If - set in both SecurityContext and PodSecurityContext, - the value specified in SecurityContext takes precedence. - type: boolean - runAsUser: - description: The UID to run the entrypoint of the - container process. Defaults to user specified in - image metadata if unspecified. May also be set in - PodSecurityContext. If set in both SecurityContext - and PodSecurityContext, the value specified in SecurityContext - takes precedence. - format: int64 - type: integer - seLinuxOptions: - description: The SELinux context to be applied to - the container. If unspecified, the container runtime - will allocate a random SELinux context for each - container. May also be set in PodSecurityContext. If - set in both SecurityContext and PodSecurityContext, - the value specified in SecurityContext takes precedence. - properties: - level: - description: Level is SELinux level label that - applies to the container. - type: string - role: - description: Role is a SELinux role label that - applies to the container. - type: string - type: - description: Type is a SELinux type label that - applies to the container. - type: string - user: - description: User is a SELinux user label that - applies to the container. - type: string - type: object - type: object - stdin: - description: Whether this container should allocate a - buffer for stdin in the container runtime. If this is - not set, reads from stdin in the container will always - result in EOF. Default is false. - type: boolean - stdinOnce: - description: Whether the container runtime should close - the stdin channel after it has been opened by a single - attach. When stdin is true the stdin stream will remain - open across multiple attach sessions. If stdinOnce is - set to true, stdin is opened on container start, is - empty until the first client attaches to stdin, and - then remains open and accepts data until the client - disconnects, at which time stdin is closed and remains - closed until the container is restarted. If this flag - is false, a container processes that reads from stdin - will never receive an EOF. Default is false - type: boolean - terminationMessagePath: - description: 'Optional: Path at which the file to which - the container''s termination message will be written - is mounted into the container''s filesystem. Message - written is intended to be brief final status, such as - an assertion failure message. Will be truncated by the - node if greater than 4096 bytes. The total message length - across all containers will be limited to 12kb. Defaults - to /dev/termination-log. Cannot be updated.' - type: string - terminationMessagePolicy: - description: Indicate how the termination message should - be populated. File will use the contents of terminationMessagePath - to populate the container status message on both success - and failure. FallbackToLogsOnError will use the last - chunk of container log output if the termination message - file is empty and the container exited with an error. - The log output is limited to 2048 bytes or 80 lines, - whichever is smaller. Defaults to File. Cannot be updated. - type: string - tty: - description: Whether this container should allocate a - TTY for itself, also requires 'stdin' to be true. Default - is false. - type: boolean - volumeDevices: - description: volumeDevices is the list of block devices - to be used by the container. This is a beta feature. - items: - description: volumeDevice describes a mapping of a raw - block device within a container. - properties: - devicePath: - description: devicePath is the path inside of the - container that the device will be mapped to. - type: string - name: - description: name must match the name of a persistentVolumeClaim - in the pod - type: string - required: - - devicePath - - name - type: object - type: array - volumeMounts: - description: Pod volumes to mount into the container's - filesystem. Cannot be updated. - items: - description: VolumeMount describes a mounting of a Volume - within a container. - properties: - mountPath: - description: Path within the container at which - the volume should be mounted. Must not contain - ':'. - type: string - mountPropagation: - description: mountPropagation determines how mounts - are propagated from the host to container and - the other way around. When not set, MountPropagationNone - is used. This field is beta in 1.10. - type: string - name: - description: This must match the Name of a Volume. - type: string - readOnly: - description: Mounted read-only if true, read-write - otherwise (false or unspecified). Defaults to - false. - type: boolean - subPath: - description: Path within the volume from which the - container's volume should be mounted. Defaults - to "" (volume's root). - type: string - subPathExpr: - description: Expanded path within the volume from - which the container's volume should be mounted. - Behaves similarly to SubPath but environment variable - references $(VAR_NAME) are expanded using the - container's environment. Defaults to "" (volume's - root). SubPathExpr and SubPath are mutually exclusive. - This field is alpha in 1.14. - type: string - required: - - mountPath - - name - type: object - type: array - workingDir: - description: Container's working directory. If not specified, - the container runtime's default will be used, which - might be configured in the container image. Cannot be - updated. - type: string - required: - - name - type: object - type: array - dnsConfig: - description: Specifies the DNS parameters of a pod. Parameters - specified here will be merged to the generated DNS configuration - based on DNSPolicy. - properties: - nameservers: - description: A list of DNS name server IP addresses. This - will be appended to the base nameservers generated from - DNSPolicy. Duplicated nameservers will be removed. - items: - type: string - type: array - options: - description: A list of DNS resolver options. This will be - merged with the base options generated from DNSPolicy. - Duplicated entries will be removed. Resolution options - given in Options will override those that appear in the - base DNSPolicy. - items: - description: PodDNSConfigOption defines DNS resolver options - of a pod. - properties: - name: - description: Required. - type: string - value: - type: string - type: object - type: array - searches: - description: A list of DNS search domains for host-name - lookup. This will be appended to the base search paths - generated from DNSPolicy. Duplicated search paths will - be removed. - items: - type: string - type: array - type: object - dnsPolicy: - description: Set DNS policy for the pod. Defaults to "ClusterFirst". - Valid values are 'ClusterFirstWithHostNet', 'ClusterFirst', - 'Default' or 'None'. DNS parameters given in DNSConfig will - be merged with the policy selected with DNSPolicy. To have - DNS options set along with hostNetwork, you have to specify - DNS policy explicitly to 'ClusterFirstWithHostNet'. - type: string - enableServiceLinks: - description: 'EnableServiceLinks indicates whether information - about services should be injected into pod''s environment - variables, matching the syntax of Docker links. Optional: - Defaults to true.' - type: boolean - hostAliases: - description: HostAliases is an optional list of hosts and IPs - that will be injected into the pod's hosts file if specified. - This is only valid for non-hostNetwork pods. - items: - description: HostAlias holds the mapping between IP and hostnames - that will be injected as an entry in the pod's hosts file. - properties: - hostnames: - description: Hostnames for the above IP address. - items: - type: string - type: array - ip: - description: IP address of the host file entry. - type: string - type: object - type: array - hostIPC: - description: 'Use the host''s ipc namespace. Optional: Default - to false.' - type: boolean - hostNetwork: - description: Host networking requested for this pod. Use the - host's network namespace. If this option is set, the ports - that will be used must be specified. Default to false. - type: boolean - hostPID: - description: 'Use the host''s pid namespace. Optional: Default - to false.' - type: boolean - hostname: - description: Specifies the hostname of the Pod If not specified, - the pod's hostname will be set to a system-defined value. - type: string - imagePullSecrets: - description: 'ImagePullSecrets is an optional list of references - to secrets in the same namespace to use for pulling any of - the images used by this PodSpec. If specified, these secrets - will be passed to individual puller implementations for them - to use. For example, in the case of docker, only DockerConfig - type secrets are honored. More info: https://kubernetes.io/docs/concepts/containers/images#specifying-imagepullsecrets-on-a-pod' - items: - description: LocalObjectReference contains enough information - to let you locate the referenced object inside the same - namespace. - properties: - name: - description: 'Name of the referent. More info: https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, uid?' - type: string - type: object - type: array - initContainers: - description: 'List of initialization containers belonging to - the pod. Init containers are executed in order prior to containers - being started. If any init container fails, the pod is considered - to have failed and is handled according to its restartPolicy. - The name for an init container or normal container must be - unique among all containers. Init containers may not have - Lifecycle actions, Readiness probes, or Liveness probes. The - resourceRequirements of an init container are taken into account - during scheduling by finding the highest request/limit for - each resource type, and then using the max of of that value - or the sum of the normal containers. Limits are applied to - init containers in a similar fashion. Init containers cannot - currently be added or removed. Cannot be updated. More info: - https://kubernetes.io/docs/concepts/workloads/pods/init-containers/' - items: - description: A single application container that you want - to run within a pod. - properties: - args: - description: 'Arguments to the entrypoint. The docker - image''s CMD is used if this is not provided. Variable - references $(VAR_NAME) are expanded using the container''s - environment. If a variable cannot be resolved, the reference - in the input string will be unchanged. The $(VAR_NAME) - syntax can be escaped with a double $$, ie: $$(VAR_NAME). - Escaped references will never be expanded, regardless - of whether the variable exists or not. Cannot be updated. - More info: https://kubernetes.io/docs/tasks/inject-data-application/define-command-argument-container/#running-a-command-in-a-shell' - items: - type: string - type: array - command: - description: 'Entrypoint array. Not executed within a - shell. The docker image''s ENTRYPOINT is used if this - is not provided. Variable references $(VAR_NAME) are - expanded using the container''s environment. If a variable - cannot be resolved, the reference in the input string - will be unchanged. The $(VAR_NAME) syntax can be escaped - with a double $$, ie: $$(VAR_NAME). Escaped references - will never be expanded, regardless of whether the variable - exists or not. Cannot be updated. More info: https://kubernetes.io/docs/tasks/inject-data-application/define-command-argument-container/#running-a-command-in-a-shell' - items: - type: string - type: array - env: - description: List of environment variables to set in the - container. Cannot be updated. - items: - description: EnvVar represents an environment variable - present in a Container. - properties: - name: - description: Name of the environment variable. Must - be a C_IDENTIFIER. - type: string - value: - description: 'Variable references $(VAR_NAME) are - expanded using the previous defined environment - variables in the container and any service environment - variables. If a variable cannot be resolved, the - reference in the input string will be unchanged. - The $(VAR_NAME) syntax can be escaped with a double - $$, ie: $$(VAR_NAME). Escaped references will - never be expanded, regardless of whether the variable - exists or not. Defaults to "".' - type: string - valueFrom: - description: Source for the environment variable's - value. Cannot be used if value is not empty. - properties: - configMapKeyRef: - description: Selects a key of a ConfigMap. - properties: - key: - description: The key to select. - type: string - name: - description: 'Name of the referent. More - info: https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the ConfigMap - or it's key must be defined - type: boolean - required: - - key - type: object - fieldRef: - description: 'Selects a field of the pod: supports - metadata.name, metadata.namespace, metadata.labels, - metadata.annotations, spec.nodeName, spec.serviceAccountName, - status.hostIP, status.podIP.' - properties: - apiVersion: - description: Version of the schema the FieldPath - is written in terms of, defaults to "v1". - type: string - fieldPath: - description: Path of the field to select - in the specified API version. - type: string - required: - - fieldPath - type: object - resourceFieldRef: - description: 'Selects a resource of the container: - only resources limits and requests (limits.cpu, - limits.memory, limits.ephemeral-storage, requests.cpu, - requests.memory and requests.ephemeral-storage) - are currently supported.' - properties: - containerName: - description: 'Container name: required for - volumes, optional for env vars' - type: string - divisor: - anyOf: - - type: integer - - type: string - description: Specifies the output format - of the exposed resources, defaults to - "1" - pattern: ^(\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))(([KMGTPE]i)|[numkMGTPE]|([eE](\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))))?$ - x-kubernetes-int-or-string: true - resource: - description: 'Required: resource to select' - type: string - required: - - resource - type: object - secretKeyRef: - description: Selects a key of a secret in the - pod's namespace - properties: - key: - description: The key of the secret to select - from. Must be a valid secret key. - type: string - name: - description: 'Name of the referent. More - info: https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the Secret - or it's key must be defined - type: boolean - required: - - key - type: object - type: object - required: - - name - type: object - type: array - envFrom: - description: List of sources to populate environment variables - in the container. The keys defined within a source must - be a C_IDENTIFIER. All invalid keys will be reported - as an event when the container is starting. When a key - exists in multiple sources, the value associated with - the last source will take precedence. Values defined - by an Env with a duplicate key will take precedence. - Cannot be updated. - items: - description: EnvFromSource represents the source of - a set of ConfigMaps - properties: - configMapRef: - description: The ConfigMap to select from - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the ConfigMap must - be defined - type: boolean - type: object - prefix: - description: An optional identifier to prepend to - each key in the ConfigMap. Must be a C_IDENTIFIER. - type: string - secretRef: - description: The Secret to select from - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the Secret must - be defined - type: boolean - type: object - type: object - type: array - image: - description: 'Docker image name. More info: https://kubernetes.io/docs/concepts/containers/images - This field is optional to allow higher level config - management to default or override container images in - workload controllers like Deployments and StatefulSets.' - type: string - imagePullPolicy: - description: 'Image pull policy. One of Always, Never, - IfNotPresent. Defaults to Always if :latest tag is specified, - or IfNotPresent otherwise. Cannot be updated. More info: - https://kubernetes.io/docs/concepts/containers/images#updating-images' - type: string - lifecycle: - description: Actions that the management system should - take in response to container lifecycle events. Cannot - be updated. - properties: - postStart: - description: 'PostStart is called immediately after - a container is created. If the handler fails, the - container is terminated and restarted according - to its restart policy. Other management of the container - blocks until the hook completes. More info: https://kubernetes.io/docs/concepts/containers/container-lifecycle-hooks/#container-hooks' - properties: - exec: - description: One and only one of the following - should be specified. Exec specifies the action - to take. - properties: - command: - description: Command is the command line to - execute inside the container, the working - directory for the command is root ('/') - in the container's filesystem. The command - is simply exec'd, it is not run inside a - shell, so traditional shell instructions - ('|', etc) won't work. To use a shell, you - need to explicitly call out to that shell. - Exit status of 0 is treated as live/healthy - and non-zero is unhealthy. - items: - type: string - type: array - type: object - httpGet: - description: HTTPGet specifies the http request - to perform. - properties: - host: - description: Host name to connect to, defaults - to the pod IP. You probably want to set - "Host" in httpHeaders instead. - type: string - httpHeaders: - description: Custom headers to set in the - request. HTTP allows repeated headers. - items: - description: HTTPHeader describes a custom - header to be used in HTTP probes - properties: - name: - description: The header field name - type: string - value: - description: The header field value - type: string - required: - - name - - value - type: object - type: array - path: - description: Path to access on the HTTP server. - type: string - port: - anyOf: - - type: integer - - type: string - description: Name or number of the port to - access on the container. Number must be - in the range 1 to 65535. Name must be an - IANA_SVC_NAME. - x-kubernetes-int-or-string: true - scheme: - description: Scheme to use for connecting - to the host. Defaults to HTTP. - type: string - required: - - port - type: object - tcpSocket: - description: 'TCPSocket specifies an action involving - a TCP port. TCP hooks not yet supported TODO: - implement a realistic TCP lifecycle hook' - properties: - host: - description: 'Optional: Host name to connect - to, defaults to the pod IP.' - type: string - port: - anyOf: - - type: integer - - type: string - description: Number or name of the port to - access on the container. Number must be - in the range 1 to 65535. Name must be an - IANA_SVC_NAME. - x-kubernetes-int-or-string: true - required: - - port - type: object - type: object - preStop: - description: 'PreStop is called immediately before - a container is terminated due to an API request - or management event such as liveness probe failure, - preemption, resource contention, etc. The handler - is not called if the container crashes or exits. - The reason for termination is passed to the handler. - The Pod''s termination grace period countdown begins - before the PreStop hooked is executed. Regardless - of the outcome of the handler, the container will - eventually terminate within the Pod''s termination - grace period. Other management of the container - blocks until the hook completes or until the termination - grace period is reached. More info: https://kubernetes.io/docs/concepts/containers/container-lifecycle-hooks/#container-hooks' - properties: - exec: - description: One and only one of the following - should be specified. Exec specifies the action - to take. - properties: - command: - description: Command is the command line to - execute inside the container, the working - directory for the command is root ('/') - in the container's filesystem. The command - is simply exec'd, it is not run inside a - shell, so traditional shell instructions - ('|', etc) won't work. To use a shell, you - need to explicitly call out to that shell. - Exit status of 0 is treated as live/healthy - and non-zero is unhealthy. - items: - type: string - type: array - type: object - httpGet: - description: HTTPGet specifies the http request - to perform. - properties: - host: - description: Host name to connect to, defaults - to the pod IP. You probably want to set - "Host" in httpHeaders instead. - type: string - httpHeaders: - description: Custom headers to set in the - request. HTTP allows repeated headers. - items: - description: HTTPHeader describes a custom - header to be used in HTTP probes - properties: - name: - description: The header field name - type: string - value: - description: The header field value - type: string - required: - - name - - value - type: object - type: array - path: - description: Path to access on the HTTP server. - type: string - port: - anyOf: - - type: integer - - type: string - description: Name or number of the port to - access on the container. Number must be - in the range 1 to 65535. Name must be an - IANA_SVC_NAME. - x-kubernetes-int-or-string: true - scheme: - description: Scheme to use for connecting - to the host. Defaults to HTTP. - type: string - required: - - port - type: object - tcpSocket: - description: 'TCPSocket specifies an action involving - a TCP port. TCP hooks not yet supported TODO: - implement a realistic TCP lifecycle hook' - properties: - host: - description: 'Optional: Host name to connect - to, defaults to the pod IP.' - type: string - port: - anyOf: - - type: integer - - type: string - description: Number or name of the port to - access on the container. Number must be - in the range 1 to 65535. Name must be an - IANA_SVC_NAME. - x-kubernetes-int-or-string: true - required: - - port - type: object - type: object - type: object - livenessProbe: - description: 'Periodic probe of container liveness. Container - will be restarted if the probe fails. Cannot be updated. - More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - properties: - exec: - description: One and only one of the following should - be specified. Exec specifies the action to take. - properties: - command: - description: Command is the command line to execute - inside the container, the working directory - for the command is root ('/') in the container's - filesystem. The command is simply exec'd, it - is not run inside a shell, so traditional shell - instructions ('|', etc) won't work. To use a - shell, you need to explicitly call out to that - shell. Exit status of 0 is treated as live/healthy - and non-zero is unhealthy. - items: - type: string - type: array - type: object - failureThreshold: - description: Minimum consecutive failures for the - probe to be considered failed after having succeeded. - Defaults to 3. Minimum value is 1. - format: int32 - type: integer - httpGet: - description: HTTPGet specifies the http request to - perform. - properties: - host: - description: Host name to connect to, defaults - to the pod IP. You probably want to set "Host" - in httpHeaders instead. - type: string - httpHeaders: - description: Custom headers to set in the request. - HTTP allows repeated headers. - items: - description: HTTPHeader describes a custom header - to be used in HTTP probes - properties: - name: - description: The header field name - type: string - value: - description: The header field value - type: string - required: - - name - - value - type: object - type: array - path: - description: Path to access on the HTTP server. - type: string - port: - anyOf: - - type: integer - - type: string - description: Name or number of the port to access - on the container. Number must be in the range - 1 to 65535. Name must be an IANA_SVC_NAME. - x-kubernetes-int-or-string: true - scheme: - description: Scheme to use for connecting to the - host. Defaults to HTTP. - type: string - required: - - port - type: object - initialDelaySeconds: - description: 'Number of seconds after the container - has started before liveness probes are initiated. - More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - format: int32 - type: integer - periodSeconds: - description: How often (in seconds) to perform the - probe. Default to 10 seconds. Minimum value is 1. - format: int32 - type: integer - successThreshold: - description: Minimum consecutive successes for the - probe to be considered successful after having failed. - Defaults to 1. Must be 1 for liveness. Minimum value - is 1. - format: int32 - type: integer - tcpSocket: - description: 'TCPSocket specifies an action involving - a TCP port. TCP hooks not yet supported TODO: implement - a realistic TCP lifecycle hook' - properties: - host: - description: 'Optional: Host name to connect to, - defaults to the pod IP.' - type: string - port: - anyOf: - - type: integer - - type: string - description: Number or name of the port to access - on the container. Number must be in the range - 1 to 65535. Name must be an IANA_SVC_NAME. - x-kubernetes-int-or-string: true - required: - - port - type: object - timeoutSeconds: - description: 'Number of seconds after which the probe - times out. Defaults to 1 second. Minimum value is - 1. More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - format: int32 - type: integer - type: object - name: - description: Name of the container specified as a DNS_LABEL. - Each container in a pod must have a unique name (DNS_LABEL). - Cannot be updated. - type: string - ports: - description: List of ports to expose from the container. - Exposing a port here gives the system additional information - about the network connections a container uses, but - is primarily informational. Not specifying a port here - DOES NOT prevent that port from being exposed. Any port - which is listening on the default "0.0.0.0" address - inside a container will be accessible from the network. - Cannot be updated. - items: - description: ContainerPort represents a network port - in a single container. - properties: - containerPort: - description: Number of port to expose on the pod's - IP address. This must be a valid port number, - 0 < x < 65536. - format: int32 - type: integer - hostIP: - description: What host IP to bind the external port - to. - type: string - hostPort: - description: Number of port to expose on the host. - If specified, this must be a valid port number, - 0 < x < 65536. If HostNetwork is specified, this - must match ContainerPort. Most containers do not - need this. - format: int32 - type: integer - name: - description: If specified, this must be an IANA_SVC_NAME - and unique within the pod. Each named port in - a pod must have a unique name. Name for the port - that can be referred to by services. - type: string - protocol: - description: Protocol for port. Must be UDP, TCP, - or SCTP. Defaults to "TCP". - type: string - default: TCP - required: - - containerPort - type: object - type: array - x-kubernetes-list-map-keys: - - containerPort - - protocol - x-kubernetes-list-type: map - readinessProbe: - description: 'Periodic probe of container service readiness. - Container will be removed from service endpoints if - the probe fails. Cannot be updated. More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - properties: - exec: - description: One and only one of the following should - be specified. Exec specifies the action to take. - properties: - command: - description: Command is the command line to execute - inside the container, the working directory - for the command is root ('/') in the container's - filesystem. The command is simply exec'd, it - is not run inside a shell, so traditional shell - instructions ('|', etc) won't work. To use a - shell, you need to explicitly call out to that - shell. Exit status of 0 is treated as live/healthy - and non-zero is unhealthy. - items: - type: string - type: array - type: object - failureThreshold: - description: Minimum consecutive failures for the - probe to be considered failed after having succeeded. - Defaults to 3. Minimum value is 1. - format: int32 - type: integer - httpGet: - description: HTTPGet specifies the http request to - perform. - properties: - host: - description: Host name to connect to, defaults - to the pod IP. You probably want to set "Host" - in httpHeaders instead. - type: string - httpHeaders: - description: Custom headers to set in the request. - HTTP allows repeated headers. - items: - description: HTTPHeader describes a custom header - to be used in HTTP probes - properties: - name: - description: The header field name - type: string - value: - description: The header field value - type: string - required: - - name - - value - type: object - type: array - path: - description: Path to access on the HTTP server. - type: string - port: - anyOf: - - type: integer - - type: string - description: Name or number of the port to access - on the container. Number must be in the range - 1 to 65535. Name must be an IANA_SVC_NAME. - x-kubernetes-int-or-string: true - scheme: - description: Scheme to use for connecting to the - host. Defaults to HTTP. - type: string - required: - - port - type: object - initialDelaySeconds: - description: 'Number of seconds after the container - has started before liveness probes are initiated. - More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - format: int32 - type: integer - periodSeconds: - description: How often (in seconds) to perform the - probe. Default to 10 seconds. Minimum value is 1. - format: int32 - type: integer - successThreshold: - description: Minimum consecutive successes for the - probe to be considered successful after having failed. - Defaults to 1. Must be 1 for liveness. Minimum value - is 1. - format: int32 - type: integer - tcpSocket: - description: 'TCPSocket specifies an action involving - a TCP port. TCP hooks not yet supported TODO: implement - a realistic TCP lifecycle hook' - properties: - host: - description: 'Optional: Host name to connect to, - defaults to the pod IP.' - type: string - port: - anyOf: - - type: integer - - type: string - description: Number or name of the port to access - on the container. Number must be in the range - 1 to 65535. Name must be an IANA_SVC_NAME. - x-kubernetes-int-or-string: true - required: - - port - type: object - timeoutSeconds: - description: 'Number of seconds after which the probe - times out. Defaults to 1 second. Minimum value is - 1. More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - format: int32 - type: integer - type: object - resources: - description: 'Compute Resources required by this container. - Cannot be updated. More info: https://kubernetes.io/docs/concepts/configuration/manage-compute-resources-container/' - properties: - limits: - additionalProperties: - anyOf: - - type: integer - - type: string - pattern: ^(\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))(([KMGTPE]i)|[numkMGTPE]|([eE](\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))))?$ - x-kubernetes-int-or-string: true - description: 'Limits describes the maximum amount - of compute resources allowed. More info: https://kubernetes.io/docs/concepts/configuration/manage-compute-resources-container/' - type: object - requests: - additionalProperties: - anyOf: - - type: integer - - type: string - pattern: ^(\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))(([KMGTPE]i)|[numkMGTPE]|([eE](\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))))?$ - x-kubernetes-int-or-string: true - description: 'Requests describes the minimum amount - of compute resources required. If Requests is omitted - for a container, it defaults to Limits if that is - explicitly specified, otherwise to an implementation-defined - value. More info: https://kubernetes.io/docs/concepts/configuration/manage-compute-resources-container/' - type: object - type: object - securityContext: - description: 'Security options the pod should run with. - More info: https://kubernetes.io/docs/concepts/policy/security-context/ - More info: https://kubernetes.io/docs/tasks/configure-pod-container/security-context/' - properties: - allowPrivilegeEscalation: - description: 'AllowPrivilegeEscalation controls whether - a process can gain more privileges than its parent - process. This bool directly controls if the no_new_privs - flag will be set on the container process. AllowPrivilegeEscalation - is true always when the container is: 1) run as - Privileged 2) has CAP_SYS_ADMIN' - type: boolean - capabilities: - description: The capabilities to add/drop when running - containers. Defaults to the default set of capabilities - granted by the container runtime. - properties: - add: - description: Added capabilities - items: - description: Capability represent POSIX capabilities - type - type: string - type: array - drop: - description: Removed capabilities - items: - description: Capability represent POSIX capabilities - type - type: string - type: array - type: object - privileged: - description: Run container in privileged mode. Processes - in privileged containers are essentially equivalent - to root on the host. Defaults to false. - type: boolean - procMount: - description: procMount denotes the type of proc mount - to use for the containers. The default is DefaultProcMount - which uses the container runtime defaults for readonly - paths and masked paths. This requires the ProcMountType - feature flag to be enabled. - type: string - readOnlyRootFilesystem: - description: Whether this container has a read-only - root filesystem. Default is false. - type: boolean - runAsGroup: - description: The GID to run the entrypoint of the - container process. Uses runtime default if unset. - May also be set in PodSecurityContext. If set in - both SecurityContext and PodSecurityContext, the - value specified in SecurityContext takes precedence. - format: int64 - type: integer - runAsNonRoot: - description: Indicates that the container must run - as a non-root user. If true, the Kubelet will validate - the image at runtime to ensure that it does not - run as UID 0 (root) and fail to start the container - if it does. If unset or false, no such validation - will be performed. May also be set in PodSecurityContext. If - set in both SecurityContext and PodSecurityContext, - the value specified in SecurityContext takes precedence. - type: boolean - runAsUser: - description: The UID to run the entrypoint of the - container process. Defaults to user specified in - image metadata if unspecified. May also be set in - PodSecurityContext. If set in both SecurityContext - and PodSecurityContext, the value specified in SecurityContext - takes precedence. - format: int64 - type: integer - seLinuxOptions: - description: The SELinux context to be applied to - the container. If unspecified, the container runtime - will allocate a random SELinux context for each - container. May also be set in PodSecurityContext. If - set in both SecurityContext and PodSecurityContext, - the value specified in SecurityContext takes precedence. - properties: - level: - description: Level is SELinux level label that - applies to the container. - type: string - role: - description: Role is a SELinux role label that - applies to the container. - type: string - type: - description: Type is a SELinux type label that - applies to the container. - type: string - user: - description: User is a SELinux user label that - applies to the container. - type: string - type: object - type: object - stdin: - description: Whether this container should allocate a - buffer for stdin in the container runtime. If this is - not set, reads from stdin in the container will always - result in EOF. Default is false. - type: boolean - stdinOnce: - description: Whether the container runtime should close - the stdin channel after it has been opened by a single - attach. When stdin is true the stdin stream will remain - open across multiple attach sessions. If stdinOnce is - set to true, stdin is opened on container start, is - empty until the first client attaches to stdin, and - then remains open and accepts data until the client - disconnects, at which time stdin is closed and remains - closed until the container is restarted. If this flag - is false, a container processes that reads from stdin - will never receive an EOF. Default is false - type: boolean - terminationMessagePath: - description: 'Optional: Path at which the file to which - the container''s termination message will be written - is mounted into the container''s filesystem. Message - written is intended to be brief final status, such as - an assertion failure message. Will be truncated by the - node if greater than 4096 bytes. The total message length - across all containers will be limited to 12kb. Defaults - to /dev/termination-log. Cannot be updated.' - type: string - terminationMessagePolicy: - description: Indicate how the termination message should - be populated. File will use the contents of terminationMessagePath - to populate the container status message on both success - and failure. FallbackToLogsOnError will use the last - chunk of container log output if the termination message - file is empty and the container exited with an error. - The log output is limited to 2048 bytes or 80 lines, - whichever is smaller. Defaults to File. Cannot be updated. - type: string - tty: - description: Whether this container should allocate a - TTY for itself, also requires 'stdin' to be true. Default - is false. - type: boolean - volumeDevices: - description: volumeDevices is the list of block devices - to be used by the container. This is a beta feature. - items: - description: volumeDevice describes a mapping of a raw - block device within a container. - properties: - devicePath: - description: devicePath is the path inside of the - container that the device will be mapped to. - type: string - name: - description: name must match the name of a persistentVolumeClaim - in the pod - type: string - required: - - devicePath - - name - type: object - type: array - volumeMounts: - description: Pod volumes to mount into the container's - filesystem. Cannot be updated. - items: - description: VolumeMount describes a mounting of a Volume - within a container. - properties: - mountPath: - description: Path within the container at which - the volume should be mounted. Must not contain - ':'. - type: string - mountPropagation: - description: mountPropagation determines how mounts - are propagated from the host to container and - the other way around. When not set, MountPropagationNone - is used. This field is beta in 1.10. - type: string - name: - description: This must match the Name of a Volume. - type: string - readOnly: - description: Mounted read-only if true, read-write - otherwise (false or unspecified). Defaults to - false. - type: boolean - subPath: - description: Path within the volume from which the - container's volume should be mounted. Defaults - to "" (volume's root). - type: string - subPathExpr: - description: Expanded path within the volume from - which the container's volume should be mounted. - Behaves similarly to SubPath but environment variable - references $(VAR_NAME) are expanded using the - container's environment. Defaults to "" (volume's - root). SubPathExpr and SubPath are mutually exclusive. - This field is alpha in 1.14. - type: string - required: - - mountPath - - name - type: object - type: array - workingDir: - description: Container's working directory. If not specified, - the container runtime's default will be used, which - might be configured in the container image. Cannot be - updated. - type: string - required: - - name - type: object - type: array - nodeName: - description: NodeName is a request to schedule this pod onto - a specific node. If it is non-empty, the scheduler simply - schedules this pod onto that node, assuming that it fits resource - requirements. - type: string - nodeSelector: - additionalProperties: - type: string - description: 'NodeSelector is a selector which must be true - for the pod to fit on a node. Selector which must match a - node''s labels for the pod to be scheduled on that node. More - info: https://kubernetes.io/docs/concepts/configuration/assign-pod-node/' - type: object - priority: - description: The priority value. Various system components use - this field to find the priority of the pod. When Priority - Admission Controller is enabled, it prevents users from setting - this field. The admission controller populates this field - from PriorityClassName. The higher the value, the higher the - priority. - format: int32 - type: integer - priorityClassName: - description: If specified, indicates the pod's priority. "system-node-critical" - and "system-cluster-critical" are two special keywords which - indicate the highest priorities with the former being the - highest priority. Any other name must be defined by creating - a PriorityClass object with that name. If not specified, the - pod priority will be default or zero if there is no default. - type: string - readinessGates: - description: 'If specified, all readiness gates will be evaluated - for pod readiness. A pod is ready when all its containers - are ready AND all conditions specified in the readiness gates - have status equal to "True" More info: https://git.k8s.io/enhancements/keps/sig-network/0007-pod-ready%2B%2B.md' - items: - description: PodReadinessGate contains the reference to a - pod condition - properties: - conditionType: - description: ConditionType refers to a condition in the - pod's condition list with matching type. - type: string - required: - - conditionType - type: object - type: array - restartPolicy: - description: 'Restart policy for all containers within the pod. - One of Always, OnFailure, Never. Default to Always. More info: - https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle/#restart-policy' - type: string - runtimeClassName: - description: 'RuntimeClassName refers to a RuntimeClass object - in the node.k8s.io group, which should be used to run this - pod. If no RuntimeClass resource matches the named class, - the pod will not be run. If unset or empty, the "legacy" RuntimeClass - will be used, which is an implicit class with an empty definition - that uses the default runtime handler. More info: https://git.k8s.io/enhancements/keps/sig-node/runtime-class.md - This is an alpha feature and may change in the future.' - type: string - schedulerName: - description: If specified, the pod will be dispatched by specified - scheduler. If not specified, the pod will be dispatched by - default scheduler. - type: string - securityContext: - description: 'SecurityContext holds pod-level security attributes - and common container settings. Optional: Defaults to empty. See - type description for default values of each field.' - properties: - fsGroup: - description: "A special supplemental group that applies - to all containers in a pod. Some volume types allow the - Kubelet to change the ownership of that volume to be owned - by the pod: \n 1. The owning GID will be the FSGroup 2. - The setgid bit is set (new files created in the volume - will be owned by FSGroup) 3. The permission bits are OR'd - with rw-rw---- \n If unset, the Kubelet will not modify - the ownership and permissions of any volume." - format: int64 - type: integer - runAsGroup: - description: The GID to run the entrypoint of the container - process. Uses runtime default if unset. May also be set - in SecurityContext. If set in both SecurityContext and - PodSecurityContext, the value specified in SecurityContext - takes precedence for that container. - format: int64 - type: integer - runAsNonRoot: - description: Indicates that the container must run as a - non-root user. If true, the Kubelet will validate the - image at runtime to ensure that it does not run as UID - 0 (root) and fail to start the container if it does. If - unset or false, no such validation will be performed. - May also be set in SecurityContext. If set in both SecurityContext - and PodSecurityContext, the value specified in SecurityContext - takes precedence. - type: boolean - runAsUser: - description: The UID to run the entrypoint of the container - process. Defaults to user specified in image metadata - if unspecified. May also be set in SecurityContext. If - set in both SecurityContext and PodSecurityContext, the - value specified in SecurityContext takes precedence for - that container. - format: int64 - type: integer - seLinuxOptions: - description: The SELinux context to be applied to all containers. - If unspecified, the container runtime will allocate a - random SELinux context for each container. May also be - set in SecurityContext. If set in both SecurityContext - and PodSecurityContext, the value specified in SecurityContext - takes precedence for that container. - properties: - level: - description: Level is SELinux level label that applies - to the container. - type: string - role: - description: Role is a SELinux role label that applies - to the container. - type: string - type: - description: Type is a SELinux type label that applies - to the container. - type: string - user: - description: User is a SELinux user label that applies - to the container. - type: string - type: object - supplementalGroups: - description: A list of groups applied to the first process - run in each container, in addition to the container's - primary GID. If unspecified, no groups will be added - to any container. - items: - format: int64 - type: integer - type: array - sysctls: - description: Sysctls hold a list of namespaced sysctls used - for the pod. Pods with unsupported sysctls (by the container - runtime) might fail to launch. - items: - description: Sysctl defines a kernel parameter to be set - properties: - name: - description: Name of a property to set - type: string - value: - description: Value of a property to set - type: string - required: - - name - - value - type: object - type: array - type: object - serviceAccount: - description: 'DeprecatedServiceAccount is a depreciated alias - for ServiceAccountName. Deprecated: Use serviceAccountName - instead.' - type: string - serviceAccountName: - description: 'ServiceAccountName is the name of the ServiceAccount - to use to run this pod. More info: https://kubernetes.io/docs/tasks/configure-pod-container/configure-service-account/' - type: string - shareProcessNamespace: - description: 'Share a single process namespace between all of - the containers in a pod. When this is set containers will - be able to view and signal processes from other containers - in the same pod, and the first process in each container will - not be assigned PID 1. HostPID and ShareProcessNamespace cannot - both be set. Optional: Default to false. This field is beta-level - and may be disabled with the PodShareProcessNamespace feature.' - type: boolean - subdomain: - description: If specified, the fully qualified Pod hostname - will be "...svc.". If not specified, the pod will not have a domainname - at all. - type: string - terminationGracePeriodSeconds: - description: Optional duration in seconds the pod needs to terminate - gracefully. May be decreased in delete request. Value must - be non-negative integer. The value zero indicates delete immediately. - If this value is nil, the default grace period will be used - instead. The grace period is the duration in seconds after - the processes running in the pod are sent a termination signal - and the time when the processes are forcibly halted with a - kill signal. Set this value longer than the expected cleanup - time for your process. Defaults to 30 seconds. - format: int64 - type: integer - tolerations: - description: If specified, the pod's tolerations. - items: - description: The pod this Toleration is attached to tolerates - any taint that matches the triple using - the matching operator . - properties: - effect: - description: Effect indicates the taint effect to match. - Empty means match all taint effects. When specified, - allowed values are NoSchedule, PreferNoSchedule and - NoExecute. - type: string - key: - description: Key is the taint key that the toleration - applies to. Empty means match all taint keys. If the - key is empty, operator must be Exists; this combination - means to match all values and all keys. - type: string - operator: - description: Operator represents a key's relationship - to the value. Valid operators are Exists and Equal. - Defaults to Equal. Exists is equivalent to wildcard - for value, so that a pod can tolerate all taints of - a particular category. - type: string - tolerationSeconds: - description: TolerationSeconds represents the period of - time the toleration (which must be of effect NoExecute, - otherwise this field is ignored) tolerates the taint. - By default, it is not set, which means tolerate the - taint forever (do not evict). Zero and negative values - will be treated as 0 (evict immediately) by the system. - format: int64 - type: integer - value: - description: Value is the taint value the toleration matches - to. If the operator is Exists, the value should be empty, - otherwise just a regular string. - type: string - type: object - type: array - volumes: - description: 'List of volumes that can be mounted by containers - belonging to the pod. More info: https://kubernetes.io/docs/concepts/storage/volumes' - items: - description: Volume represents a named volume in a pod that - may be accessed by any container in the pod. - properties: - awsElasticBlockStore: - description: 'AWSElasticBlockStore represents an AWS Disk - resource that is attached to a kubelet''s host machine - and then exposed to the pod. More info: https://kubernetes.io/docs/concepts/storage/volumes#awselasticblockstore' - properties: - fsType: - description: 'Filesystem type of the volume that you - want to mount. Tip: Ensure that the filesystem type - is supported by the host operating system. Examples: - "ext4", "xfs", "ntfs". Implicitly inferred to be - "ext4" if unspecified. More info: https://kubernetes.io/docs/concepts/storage/volumes#awselasticblockstore - TODO: how do we prevent errors in the filesystem - from compromising the machine' - type: string - partition: - description: 'The partition in the volume that you - want to mount. If omitted, the default is to mount - by volume name. Examples: For volume /dev/sda1, - you specify the partition as "1". Similarly, the - volume partition for /dev/sda is "0" (or you can - leave the property empty).' - format: int32 - type: integer - readOnly: - description: 'Specify "true" to force and set the - ReadOnly property in VolumeMounts to "true". If - omitted, the default is "false". More info: https://kubernetes.io/docs/concepts/storage/volumes#awselasticblockstore' - type: boolean - volumeID: - description: 'Unique ID of the persistent disk resource - in AWS (Amazon EBS volume). More info: https://kubernetes.io/docs/concepts/storage/volumes#awselasticblockstore' - type: string - required: - - volumeID - type: object - azureDisk: - description: AzureDisk represents an Azure Data Disk mount - on the host and bind mount to the pod. - properties: - cachingMode: - description: 'Host Caching mode: None, Read Only, - Read Write.' - type: string - diskName: - description: The Name of the data disk in the blob - storage - type: string - diskURI: - description: The URI the data disk in the blob storage - type: string - fsType: - description: Filesystem type to mount. Must be a filesystem - type supported by the host operating system. Ex. - "ext4", "xfs", "ntfs". Implicitly inferred to be - "ext4" if unspecified. - type: string - kind: - description: 'Expected values Shared: multiple blob - disks per storage account Dedicated: single blob - disk per storage account Managed: azure managed - data disk (only in managed availability set). defaults - to shared' - type: string - readOnly: - description: Defaults to false (read/write). ReadOnly - here will force the ReadOnly setting in VolumeMounts. - type: boolean - required: - - diskName - - diskURI - type: object - azureFile: - description: AzureFile represents an Azure File Service - mount on the host and bind mount to the pod. - properties: - readOnly: - description: Defaults to false (read/write). ReadOnly - here will force the ReadOnly setting in VolumeMounts. - type: boolean - secretName: - description: the name of secret that contains Azure - Storage Account Name and Key - type: string - shareName: - description: Share Name - type: string - required: - - secretName - - shareName - type: object - cephfs: - description: CephFS represents a Ceph FS mount on the - host that shares a pod's lifetime - properties: - monitors: - description: 'Required: Monitors is a collection of - Ceph monitors More info: https://releases.k8s.io/HEAD/examples/volumes/cephfs/README.md#how-to-use-it' - items: - type: string - type: array - path: - description: 'Optional: Used as the mounted root, - rather than the full Ceph tree, default is /' - type: string - readOnly: - description: 'Optional: Defaults to false (read/write). - ReadOnly here will force the ReadOnly setting in - VolumeMounts. More info: https://releases.k8s.io/HEAD/examples/volumes/cephfs/README.md#how-to-use-it' - type: boolean - secretFile: - description: 'Optional: SecretFile is the path to - key ring for User, default is /etc/ceph/user.secret - More info: https://releases.k8s.io/HEAD/examples/volumes/cephfs/README.md#how-to-use-it' - type: string - secretRef: - description: 'Optional: SecretRef is reference to - the authentication secret for User, default is empty. - More info: https://releases.k8s.io/HEAD/examples/volumes/cephfs/README.md#how-to-use-it' - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, - uid?' - type: string - type: object - user: - description: 'Optional: User is the rados user name, - default is admin More info: https://releases.k8s.io/HEAD/examples/volumes/cephfs/README.md#how-to-use-it' - type: string - required: - - monitors - type: object - cinder: - description: 'Cinder represents a cinder volume attached - and mounted on kubelets host machine More info: https://releases.k8s.io/HEAD/examples/mysql-cinder-pd/README.md' - properties: - fsType: - description: 'Filesystem type to mount. Must be a - filesystem type supported by the host operating - system. Examples: "ext4", "xfs", "ntfs". Implicitly - inferred to be "ext4" if unspecified. More info: - https://releases.k8s.io/HEAD/examples/mysql-cinder-pd/README.md' - type: string - readOnly: - description: 'Optional: Defaults to false (read/write). - ReadOnly here will force the ReadOnly setting in - VolumeMounts. More info: https://releases.k8s.io/HEAD/examples/mysql-cinder-pd/README.md' - type: boolean - secretRef: - description: 'Optional: points to a secret object - containing parameters used to connect to OpenStack.' - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, - uid?' - type: string - type: object - volumeID: - description: 'volume id used to identify the volume - in cinder More info: https://releases.k8s.io/HEAD/examples/mysql-cinder-pd/README.md' - type: string - required: - - volumeID - type: object - configMap: - description: ConfigMap represents a configMap that should - populate this volume - properties: - defaultMode: - description: 'Optional: mode bits to use on created - files by default. Must be a value between 0 and - 0777. Defaults to 0644. Directories within the path - are not affected by this setting. This might be - in conflict with other options that affect the file - mode, like fsGroup, and the result can be other - mode bits set.' - format: int32 - type: integer - items: - description: If unspecified, each key-value pair in - the Data field of the referenced ConfigMap will - be projected into the volume as a file whose name - is the key and content is the value. If specified, - the listed keys will be projected into the specified - paths, and unlisted keys will not be present. If - a key is specified which is not present in the ConfigMap, - the volume setup will error unless it is marked - optional. Paths must be relative and may not contain - the '..' path or start with '..'. - items: - description: Maps a string key to a path within - a volume. - properties: - key: - description: The key to project. - type: string - mode: - description: 'Optional: mode bits to use on - this file, must be a value between 0 and 0777. - If not specified, the volume defaultMode will - be used. This might be in conflict with other - options that affect the file mode, like fsGroup, - and the result can be other mode bits set.' - format: int32 - type: integer - path: - description: The relative path of the file to - map the key to. May not be an absolute path. - May not contain the path element '..'. May - not start with the string '..'. - type: string - required: - - key - - path - type: object - type: array - name: - description: 'Name of the referent. More info: https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, - uid?' - type: string - optional: - description: Specify whether the ConfigMap or it's - keys must be defined - type: boolean - type: object - csi: - description: CSI (Container Storage Interface) represents - storage that is handled by an external CSI driver (Alpha - feature). - properties: - driver: - description: Driver is the name of the CSI driver - that handles this volume. Consult with your admin - for the correct name as registered in the cluster. - type: string - fsType: - description: Filesystem type to mount. Ex. "ext4", - "xfs", "ntfs". If not provided, the empty value - is passed to the associated CSI driver which will - determine the default filesystem to apply. - type: string - nodePublishSecretRef: - description: NodePublishSecretRef is a reference to - the secret object containing sensitive information - to pass to the CSI driver to complete the CSI NodePublishVolume - and NodeUnpublishVolume calls. This field is optional, - and may be empty if no secret is required. If the - secret object contains more than one secret, all - secret references are passed. - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, - uid?' - type: string - type: object - readOnly: - description: Specifies a read-only configuration for - the volume. Defaults to false (read/write). - type: boolean - volumeAttributes: - additionalProperties: - type: string - description: VolumeAttributes stores driver-specific - properties that are passed to the CSI driver. Consult - your driver's documentation for supported values. - type: object - required: - - driver - type: object - downwardAPI: - description: DownwardAPI represents downward API about - the pod that should populate this volume - properties: - defaultMode: - description: 'Optional: mode bits to use on created - files by default. Must be a value between 0 and - 0777. Defaults to 0644. Directories within the path - are not affected by this setting. This might be - in conflict with other options that affect the file - mode, like fsGroup, and the result can be other - mode bits set.' - format: int32 - type: integer - items: - description: Items is a list of downward API volume - file - items: - description: DownwardAPIVolumeFile represents information - to create the file containing the pod field - properties: - fieldRef: - description: 'Required: Selects a field of the - pod: only annotations, labels, name and namespace - are supported.' - properties: - apiVersion: - description: Version of the schema the FieldPath - is written in terms of, defaults to "v1". - type: string - fieldPath: - description: Path of the field to select - in the specified API version. - type: string - required: - - fieldPath - type: object - mode: - description: 'Optional: mode bits to use on - this file, must be a value between 0 and 0777. - If not specified, the volume defaultMode will - be used. This might be in conflict with other - options that affect the file mode, like fsGroup, - and the result can be other mode bits set.' - format: int32 - type: integer - path: - description: 'Required: Path is the relative - path name of the file to be created. Must - not be absolute or contain the ''..'' path. - Must be utf-8 encoded. The first item of the - relative path must not start with ''..''' - type: string - resourceFieldRef: - description: 'Selects a resource of the container: - only resources limits and requests (limits.cpu, - limits.memory, requests.cpu and requests.memory) - are currently supported.' - properties: - containerName: - description: 'Container name: required for - volumes, optional for env vars' - type: string - divisor: - anyOf: - - type: integer - - type: string - description: Specifies the output format - of the exposed resources, defaults to - "1" - pattern: ^(\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))(([KMGTPE]i)|[numkMGTPE]|([eE](\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))))?$ - x-kubernetes-int-or-string: true - resource: - description: 'Required: resource to select' - type: string - required: - - resource - type: object - required: - - path - type: object - type: array - type: object - emptyDir: - description: 'EmptyDir represents a temporary directory - that shares a pod''s lifetime. More info: https://kubernetes.io/docs/concepts/storage/volumes#emptydir' - properties: - medium: - description: 'What type of storage medium should back - this directory. The default is "" which means to - use the node''s default medium. Must be an empty - string (default) or Memory. More info: https://kubernetes.io/docs/concepts/storage/volumes#emptydir' - type: string - sizeLimit: - anyOf: - - type: integer - - type: string - description: 'Total amount of local storage required - for this EmptyDir volume. The size limit is also - applicable for memory medium. The maximum usage - on memory medium EmptyDir would be the minimum value - between the SizeLimit specified here and the sum - of memory limits of all containers in a pod. The - default is nil which means that the limit is undefined. - More info: http://kubernetes.io/docs/user-guide/volumes#emptydir' - pattern: ^(\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))(([KMGTPE]i)|[numkMGTPE]|([eE](\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))))?$ - x-kubernetes-int-or-string: true - type: object - fc: - description: FC represents a Fibre Channel resource that - is attached to a kubelet's host machine and then exposed - to the pod. - properties: - fsType: - description: 'Filesystem type to mount. Must be a - filesystem type supported by the host operating - system. Ex. "ext4", "xfs", "ntfs". Implicitly inferred - to be "ext4" if unspecified. TODO: how do we prevent - errors in the filesystem from compromising the machine' - type: string - lun: - description: 'Optional: FC target lun number' - format: int32 - type: integer - readOnly: - description: 'Optional: Defaults to false (read/write). - ReadOnly here will force the ReadOnly setting in - VolumeMounts.' - type: boolean - targetWWNs: - description: 'Optional: FC target worldwide names - (WWNs)' - items: - type: string - type: array - wwids: - description: 'Optional: FC volume world wide identifiers - (wwids) Either wwids or combination of targetWWNs - and lun must be set, but not both simultaneously.' - items: - type: string - type: array - type: object - flexVolume: - description: FlexVolume represents a generic volume resource - that is provisioned/attached using an exec based plugin. - properties: - driver: - description: Driver is the name of the driver to use - for this volume. - type: string - fsType: - description: Filesystem type to mount. Must be a filesystem - type supported by the host operating system. Ex. - "ext4", "xfs", "ntfs". The default filesystem depends - on FlexVolume script. - type: string - options: - additionalProperties: - type: string - description: 'Optional: Extra command options if any.' - type: object - readOnly: - description: 'Optional: Defaults to false (read/write). - ReadOnly here will force the ReadOnly setting in - VolumeMounts.' - type: boolean - secretRef: - description: 'Optional: SecretRef is reference to - the secret object containing sensitive information - to pass to the plugin scripts. This may be empty - if no secret object is specified. If the secret - object contains more than one secret, all secrets - are passed to the plugin scripts.' - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, - uid?' - type: string - type: object - required: - - driver - type: object - flocker: - description: Flocker represents a Flocker volume attached - to a kubelet's host machine. This depends on the Flocker - control service being running - properties: - datasetName: - description: Name of the dataset stored as metadata - -> name on the dataset for Flocker should be considered - as deprecated - type: string - datasetUUID: - description: UUID of the dataset. This is unique identifier - of a Flocker dataset - type: string - type: object - gcePersistentDisk: - description: 'GCEPersistentDisk represents a GCE Disk - resource that is attached to a kubelet''s host machine - and then exposed to the pod. More info: https://kubernetes.io/docs/concepts/storage/volumes#gcepersistentdisk' - properties: - fsType: - description: 'Filesystem type of the volume that you - want to mount. Tip: Ensure that the filesystem type - is supported by the host operating system. Examples: - "ext4", "xfs", "ntfs". Implicitly inferred to be - "ext4" if unspecified. More info: https://kubernetes.io/docs/concepts/storage/volumes#gcepersistentdisk - TODO: how do we prevent errors in the filesystem - from compromising the machine' - type: string - partition: - description: 'The partition in the volume that you - want to mount. If omitted, the default is to mount - by volume name. Examples: For volume /dev/sda1, - you specify the partition as "1". Similarly, the - volume partition for /dev/sda is "0" (or you can - leave the property empty). More info: https://kubernetes.io/docs/concepts/storage/volumes#gcepersistentdisk' - format: int32 - type: integer - pdName: - description: 'Unique name of the PD resource in GCE. - Used to identify the disk in GCE. More info: https://kubernetes.io/docs/concepts/storage/volumes#gcepersistentdisk' - type: string - readOnly: - description: 'ReadOnly here will force the ReadOnly - setting in VolumeMounts. Defaults to false. More - info: https://kubernetes.io/docs/concepts/storage/volumes#gcepersistentdisk' - type: boolean - required: - - pdName - type: object - gitRepo: - description: 'GitRepo represents a git repository at a - particular revision. DEPRECATED: GitRepo is deprecated. - To provision a container with a git repo, mount an EmptyDir - into an InitContainer that clones the repo using git, - then mount the EmptyDir into the Pod''s container.' - properties: - directory: - description: Target directory name. Must not contain - or start with '..'. If '.' is supplied, the volume - directory will be the git repository. Otherwise, - if specified, the volume will contain the git repository - in the subdirectory with the given name. - type: string - repository: - description: Repository URL - type: string - revision: - description: Commit hash for the specified revision. - type: string - required: - - repository - type: object - glusterfs: - description: 'Glusterfs represents a Glusterfs mount on - the host that shares a pod''s lifetime. More info: https://releases.k8s.io/HEAD/examples/volumes/glusterfs/README.md' - properties: - endpoints: - description: 'EndpointsName is the endpoint name that - details Glusterfs topology. More info: https://releases.k8s.io/HEAD/examples/volumes/glusterfs/README.md#create-a-pod' - type: string - path: - description: 'Path is the Glusterfs volume path. More - info: https://releases.k8s.io/HEAD/examples/volumes/glusterfs/README.md#create-a-pod' - type: string - readOnly: - description: 'ReadOnly here will force the Glusterfs - volume to be mounted with read-only permissions. - Defaults to false. More info: https://releases.k8s.io/HEAD/examples/volumes/glusterfs/README.md#create-a-pod' - type: boolean - required: - - endpoints - - path - type: object - hostPath: - description: 'HostPath represents a pre-existing file - or directory on the host machine that is directly exposed - to the container. This is generally used for system - agents or other privileged things that are allowed to - see the host machine. Most containers will NOT need - this. More info: https://kubernetes.io/docs/concepts/storage/volumes#hostpath - --- TODO(jonesdl) We need to restrict who can use host - directory mounts and who can/can not mount host directories - as read/write.' - properties: - path: - description: 'Path of the directory on the host. If - the path is a symlink, it will follow the link to - the real path. More info: https://kubernetes.io/docs/concepts/storage/volumes#hostpath' - type: string - type: - description: 'Type for HostPath Volume Defaults to - "" More info: https://kubernetes.io/docs/concepts/storage/volumes#hostpath' - type: string - required: - - path - type: object - iscsi: - description: 'ISCSI represents an ISCSI Disk resource - that is attached to a kubelet''s host machine and then - exposed to the pod. More info: https://releases.k8s.io/HEAD/examples/volumes/iscsi/README.md' - properties: - chapAuthDiscovery: - description: whether support iSCSI Discovery CHAP - authentication - type: boolean - chapAuthSession: - description: whether support iSCSI Session CHAP authentication - type: boolean - fsType: - description: 'Filesystem type of the volume that you - want to mount. Tip: Ensure that the filesystem type - is supported by the host operating system. Examples: - "ext4", "xfs", "ntfs". Implicitly inferred to be - "ext4" if unspecified. More info: https://kubernetes.io/docs/concepts/storage/volumes#iscsi - TODO: how do we prevent errors in the filesystem - from compromising the machine' - type: string - initiatorName: - description: Custom iSCSI Initiator Name. If initiatorName - is specified with iscsiInterface simultaneously, - new iSCSI interface : - will be created for the connection. - type: string - iqn: - description: Target iSCSI Qualified Name. - type: string - iscsiInterface: - description: iSCSI Interface Name that uses an iSCSI - transport. Defaults to 'default' (tcp). - type: string - lun: - description: iSCSI Target Lun number. - format: int32 - type: integer - portals: - description: iSCSI Target Portal List. The portal - is either an IP or ip_addr:port if the port is other - than default (typically TCP ports 860 and 3260). - items: - type: string - type: array - readOnly: - description: ReadOnly here will force the ReadOnly - setting in VolumeMounts. Defaults to false. - type: boolean - secretRef: - description: CHAP Secret for iSCSI target and initiator - authentication - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, - uid?' - type: string - type: object - targetPortal: - description: iSCSI Target Portal. The Portal is either - an IP or ip_addr:port if the port is other than - default (typically TCP ports 860 and 3260). - type: string - required: - - iqn - - lun - - targetPortal - type: object - name: - description: 'Volume''s name. Must be a DNS_LABEL and - unique within the pod. More info: https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names' - type: string - nfs: - description: 'NFS represents an NFS mount on the host - that shares a pod''s lifetime More info: https://kubernetes.io/docs/concepts/storage/volumes#nfs' - properties: - path: - description: 'Path that is exported by the NFS server. - More info: https://kubernetes.io/docs/concepts/storage/volumes#nfs' - type: string - readOnly: - description: 'ReadOnly here will force the NFS export - to be mounted with read-only permissions. Defaults - to false. More info: https://kubernetes.io/docs/concepts/storage/volumes#nfs' - type: boolean - server: - description: 'Server is the hostname or IP address - of the NFS server. More info: https://kubernetes.io/docs/concepts/storage/volumes#nfs' - type: string - required: - - path - - server - type: object - persistentVolumeClaim: - description: 'PersistentVolumeClaimVolumeSource represents - a reference to a PersistentVolumeClaim in the same namespace. - More info: https://kubernetes.io/docs/concepts/storage/persistent-volumes#persistentvolumeclaims' - properties: - claimName: - description: 'ClaimName is the name of a PersistentVolumeClaim - in the same namespace as the pod using this volume. - More info: https://kubernetes.io/docs/concepts/storage/persistent-volumes#persistentvolumeclaims' - type: string - readOnly: - description: Will force the ReadOnly setting in VolumeMounts. - Default false. - type: boolean - required: - - claimName - type: object - photonPersistentDisk: - description: PhotonPersistentDisk represents a PhotonController - persistent disk attached and mounted on kubelets host - machine - properties: - fsType: - description: Filesystem type to mount. Must be a filesystem - type supported by the host operating system. Ex. - "ext4", "xfs", "ntfs". Implicitly inferred to be - "ext4" if unspecified. - type: string - pdID: - description: ID that identifies Photon Controller - persistent disk - type: string - required: - - pdID - type: object - portworxVolume: - description: PortworxVolume represents a portworx volume - attached and mounted on kubelets host machine - properties: - fsType: - description: FSType represents the filesystem type - to mount Must be a filesystem type supported by - the host operating system. Ex. "ext4", "xfs". Implicitly - inferred to be "ext4" if unspecified. - type: string - readOnly: - description: Defaults to false (read/write). ReadOnly - here will force the ReadOnly setting in VolumeMounts. - type: boolean - volumeID: - description: VolumeID uniquely identifies a Portworx - volume - type: string - required: - - volumeID - type: object - projected: - description: Items for all in one resources secrets, configmaps, - and downward API - properties: - defaultMode: - description: Mode bits to use on created files by - default. Must be a value between 0 and 0777. Directories - within the path are not affected by this setting. - This might be in conflict with other options that - affect the file mode, like fsGroup, and the result - can be other mode bits set. - format: int32 - type: integer - sources: - description: list of volume projections - items: - description: Projection that may be projected along - with other supported volume types - properties: - configMap: - description: information about the configMap - data to project - properties: - items: - description: If unspecified, each key-value - pair in the Data field of the referenced - ConfigMap will be projected into the volume - as a file whose name is the key and content - is the value. If specified, the listed - keys will be projected into the specified - paths, and unlisted keys will not be present. - If a key is specified which is not present - in the ConfigMap, the volume setup will - error unless it is marked optional. Paths - must be relative and may not contain the - '..' path or start with '..'. - items: - description: Maps a string key to a path - within a volume. - properties: - key: - description: The key to project. - type: string - mode: - description: 'Optional: mode bits - to use on this file, must be a value - between 0 and 0777. If not specified, - the volume defaultMode will be used. - This might be in conflict with other - options that affect the file mode, - like fsGroup, and the result can - be other mode bits set.' - format: int32 - type: integer - path: - description: The relative path of - the file to map the key to. May - not be an absolute path. May not - contain the path element '..'. May - not start with the string '..'. - type: string - required: - - key - - path - type: object - type: array - name: - description: 'Name of the referent. More - info: https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the ConfigMap - or it's keys must be defined - type: boolean - type: object - downwardAPI: - description: information about the downwardAPI - data to project - properties: - items: - description: Items is a list of DownwardAPIVolume - file - items: - description: DownwardAPIVolumeFile represents - information to create the file containing - the pod field - properties: - fieldRef: - description: 'Required: Selects a - field of the pod: only annotations, - labels, name and namespace are supported.' - properties: - apiVersion: - description: Version of the schema - the FieldPath is written in - terms of, defaults to "v1". - type: string - fieldPath: - description: Path of the field - to select in the specified API - version. - type: string - required: - - fieldPath - type: object - mode: - description: 'Optional: mode bits - to use on this file, must be a value - between 0 and 0777. If not specified, - the volume defaultMode will be used. - This might be in conflict with other - options that affect the file mode, - like fsGroup, and the result can - be other mode bits set.' - format: int32 - type: integer - path: - description: 'Required: Path is the - relative path name of the file to - be created. Must not be absolute - or contain the ''..'' path. Must - be utf-8 encoded. The first item - of the relative path must not start - with ''..''' - type: string - resourceFieldRef: - description: 'Selects a resource of - the container: only resources limits - and requests (limits.cpu, limits.memory, - requests.cpu and requests.memory) - are currently supported.' - properties: - containerName: - description: 'Container name: - required for volumes, optional - for env vars' - type: string - divisor: - anyOf: - - type: integer - - type: string - description: Specifies the output - format of the exposed resources, - defaults to "1" - pattern: ^(\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))(([KMGTPE]i)|[numkMGTPE]|([eE](\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))))?$ - x-kubernetes-int-or-string: true - resource: - description: 'Required: resource - to select' - type: string - required: - - resource - type: object - required: - - path - type: object - type: array - type: object - secret: - description: information about the secret data - to project - properties: - items: - description: If unspecified, each key-value - pair in the Data field of the referenced - Secret will be projected into the volume - as a file whose name is the key and content - is the value. If specified, the listed - keys will be projected into the specified - paths, and unlisted keys will not be present. - If a key is specified which is not present - in the Secret, the volume setup will error - unless it is marked optional. Paths must - be relative and may not contain the '..' - path or start with '..'. - items: - description: Maps a string key to a path - within a volume. - properties: - key: - description: The key to project. - type: string - mode: - description: 'Optional: mode bits - to use on this file, must be a value - between 0 and 0777. If not specified, - the volume defaultMode will be used. - This might be in conflict with other - options that affect the file mode, - like fsGroup, and the result can - be other mode bits set.' - format: int32 - type: integer - path: - description: The relative path of - the file to map the key to. May - not be an absolute path. May not - contain the path element '..'. May - not start with the string '..'. - type: string - required: - - key - - path - type: object - type: array - name: - description: 'Name of the referent. More - info: https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the Secret - or its key must be defined - type: boolean - type: object - serviceAccountToken: - description: information about the serviceAccountToken - data to project - properties: - audience: - description: Audience is the intended audience - of the token. A recipient of a token must - identify itself with an identifier specified - in the audience of the token, and otherwise - should reject the token. The audience - defaults to the identifier of the apiserver. - type: string - expirationSeconds: - description: ExpirationSeconds is the requested - duration of validity of the service account - token. As the token approaches expiration, - the kubelet volume plugin will proactively - rotate the service account token. The - kubelet will start trying to rotate the - token if the token is older than 80 percent - of its time to live or if the token is - older than 24 hours.Defaults to 1 hour - and must be at least 10 minutes. - format: int64 - type: integer - path: - description: Path is the path relative to - the mount point of the file to project - the token into. - type: string - required: - - path - type: object - type: object - type: array - required: - - sources - type: object - quobyte: - description: Quobyte represents a Quobyte mount on the - host that shares a pod's lifetime - properties: - group: - description: Group to map volume access to Default - is no group - type: string - readOnly: - description: ReadOnly here will force the Quobyte - volume to be mounted with read-only permissions. - Defaults to false. - type: boolean - registry: - description: Registry represents a single or multiple - Quobyte Registry services specified as a string - as host:port pair (multiple entries are separated - with commas) which acts as the central registry - for volumes - type: string - tenant: - description: Tenant owning the given Quobyte volume - in the Backend Used with dynamically provisioned - Quobyte volumes, value is set by the plugin - type: string - user: - description: User to map volume access to Defaults - to serivceaccount user - type: string - volume: - description: Volume is a string that references an - already created Quobyte volume by name. - type: string - required: - - registry - - volume - type: object - rbd: - description: 'RBD represents a Rados Block Device mount - on the host that shares a pod''s lifetime. More info: - https://releases.k8s.io/HEAD/examples/volumes/rbd/README.md' - properties: - fsType: - description: 'Filesystem type of the volume that you - want to mount. Tip: Ensure that the filesystem type - is supported by the host operating system. Examples: - "ext4", "xfs", "ntfs". Implicitly inferred to be - "ext4" if unspecified. More info: https://kubernetes.io/docs/concepts/storage/volumes#rbd - TODO: how do we prevent errors in the filesystem - from compromising the machine' - type: string - image: - description: 'The rados image name. More info: https://releases.k8s.io/HEAD/examples/volumes/rbd/README.md#how-to-use-it' - type: string - keyring: - description: 'Keyring is the path to key ring for - RBDUser. Default is /etc/ceph/keyring. More info: - https://releases.k8s.io/HEAD/examples/volumes/rbd/README.md#how-to-use-it' - type: string - monitors: - description: 'A collection of Ceph monitors. More - info: https://releases.k8s.io/HEAD/examples/volumes/rbd/README.md#how-to-use-it' - items: - type: string - type: array - pool: - description: 'The rados pool name. Default is rbd. - More info: https://releases.k8s.io/HEAD/examples/volumes/rbd/README.md#how-to-use-it' - type: string - readOnly: - description: 'ReadOnly here will force the ReadOnly - setting in VolumeMounts. Defaults to false. More - info: https://releases.k8s.io/HEAD/examples/volumes/rbd/README.md#how-to-use-it' - type: boolean - secretRef: - description: 'SecretRef is name of the authentication - secret for RBDUser. If provided overrides keyring. - Default is nil. More info: https://releases.k8s.io/HEAD/examples/volumes/rbd/README.md#how-to-use-it' - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, - uid?' - type: string - type: object - user: - description: 'The rados user name. Default is admin. - More info: https://releases.k8s.io/HEAD/examples/volumes/rbd/README.md#how-to-use-it' - type: string - required: - - image - - monitors - type: object - scaleIO: - description: ScaleIO represents a ScaleIO persistent volume - attached and mounted on Kubernetes nodes. - properties: - fsType: - description: Filesystem type to mount. Must be a filesystem - type supported by the host operating system. Ex. - "ext4", "xfs", "ntfs". Default is "xfs". - type: string - gateway: - description: The host address of the ScaleIO API Gateway. - type: string - protectionDomain: - description: The name of the ScaleIO Protection Domain - for the configured storage. - type: string - readOnly: - description: Defaults to false (read/write). ReadOnly - here will force the ReadOnly setting in VolumeMounts. - type: boolean - secretRef: - description: SecretRef references to the secret for - ScaleIO user and other sensitive information. If - this is not provided, Login operation will fail. - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, - uid?' - type: string - type: object - sslEnabled: - description: Flag to enable/disable SSL communication - with Gateway, default false - type: boolean - storageMode: - description: Indicates whether the storage for a volume - should be ThickProvisioned or ThinProvisioned. Default - is ThinProvisioned. - type: string - storagePool: - description: The ScaleIO Storage Pool associated with - the protection domain. - type: string - system: - description: The name of the storage system as configured - in ScaleIO. - type: string - volumeName: - description: The name of a volume already created - in the ScaleIO system that is associated with this - volume source. - type: string - required: - - gateway - - secretRef - - system - type: object - secret: - description: 'Secret represents a secret that should populate - this volume. More info: https://kubernetes.io/docs/concepts/storage/volumes#secret' - properties: - defaultMode: - description: 'Optional: mode bits to use on created - files by default. Must be a value between 0 and - 0777. Defaults to 0644. Directories within the path - are not affected by this setting. This might be - in conflict with other options that affect the file - mode, like fsGroup, and the result can be other - mode bits set.' - format: int32 - type: integer - items: - description: If unspecified, each key-value pair in - the Data field of the referenced Secret will be - projected into the volume as a file whose name is - the key and content is the value. If specified, - the listed keys will be projected into the specified - paths, and unlisted keys will not be present. If - a key is specified which is not present in the Secret, - the volume setup will error unless it is marked - optional. Paths must be relative and may not contain - the '..' path or start with '..'. - items: - description: Maps a string key to a path within - a volume. - properties: - key: - description: The key to project. - type: string - mode: - description: 'Optional: mode bits to use on - this file, must be a value between 0 and 0777. - If not specified, the volume defaultMode will - be used. This might be in conflict with other - options that affect the file mode, like fsGroup, - and the result can be other mode bits set.' - format: int32 - type: integer - path: - description: The relative path of the file to - map the key to. May not be an absolute path. - May not contain the path element '..'. May - not start with the string '..'. - type: string - required: - - key - - path - type: object - type: array - optional: - description: Specify whether the Secret or it's keys - must be defined - type: boolean - secretName: - description: 'Name of the secret in the pod''s namespace - to use. More info: https://kubernetes.io/docs/concepts/storage/volumes#secret' - type: string - type: object - storageos: - description: StorageOS represents a StorageOS volume attached - and mounted on Kubernetes nodes. - properties: - fsType: - description: Filesystem type to mount. Must be a filesystem - type supported by the host operating system. Ex. - "ext4", "xfs", "ntfs". Implicitly inferred to be - "ext4" if unspecified. - type: string - readOnly: - description: Defaults to false (read/write). ReadOnly - here will force the ReadOnly setting in VolumeMounts. - type: boolean - secretRef: - description: SecretRef specifies the secret to use - for obtaining the StorageOS API credentials. If - not specified, default values will be attempted. - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, - uid?' - type: string - type: object - volumeName: - description: VolumeName is the human-readable name - of the StorageOS volume. Volume names are only - unique within a namespace. - type: string - volumeNamespace: - description: VolumeNamespace specifies the scope of - the volume within StorageOS. If no namespace is - specified then the Pod's namespace will be used. This - allows the Kubernetes name scoping to be mirrored - within StorageOS for tighter integration. Set VolumeName - to any name to override the default behaviour. Set - to "default" if you are not using namespaces within - StorageOS. Namespaces that do not pre-exist within - StorageOS will be created. - type: string - type: object - vsphereVolume: - description: VsphereVolume represents a vSphere volume - attached and mounted on kubelets host machine - properties: - fsType: - description: Filesystem type to mount. Must be a filesystem - type supported by the host operating system. Ex. - "ext4", "xfs", "ntfs". Implicitly inferred to be - "ext4" if unspecified. - type: string - storagePolicyID: - description: Storage Policy Based Management (SPBM) - profile ID associated with the StoragePolicyName. - type: string - storagePolicyName: - description: Storage Policy Based Management (SPBM) - profile name. - type: string - volumePath: - description: Path that identifies vSphere volume vmdk - type: string - required: - - volumePath - type: object - required: - - name - type: object - type: array - required: - - containers - type: object - headPodType: - description: Specifies the head node type. - type: string - headStartRayCommands: - description: Commands to start Ray on the head node. - type: array - items: - type: string - description: shell command - workerStartRayCommands: - description: Commands to start Ray on worker nodes. - type: array - items: - type: string - description: shell command diff --git a/tools/AutoTuner/helm-chart/templates/_helpers.tpl b/tools/AutoTuner/helm-chart/templates/_helpers.tpl deleted file mode 100644 index 615d4e36d3..0000000000 --- a/tools/AutoTuner/helm-chart/templates/_helpers.tpl +++ /dev/null @@ -1,10 +0,0 @@ -{{/* -Compute clusterMaxWorkers as the sum of per-pod-type max workers. -*/}} -{{- define "ray.clusterMaxWorkers" -}} -{{- $total := 0 }} -{{- range .Values.podTypes }} -{{- $total = add $total .maxWorkers }} -{{- end }} -{{- $total }} -{{- end }} diff --git a/tools/AutoTuner/helm-chart/templates/operator_cluster_scoped.yaml b/tools/AutoTuner/helm-chart/templates/operator_cluster_scoped.yaml deleted file mode 100644 index 5e0221a444..0000000000 --- a/tools/AutoTuner/helm-chart/templates/operator_cluster_scoped.yaml +++ /dev/null @@ -1,66 +0,0 @@ -{{- if and (not .Values.namespacedOperator) (not .Values.clusterOnly) }} ---- -apiVersion: v1 -kind: ServiceAccount -metadata: - name: ray-operator-serviceaccount - namespace: {{ .Values.operatorNamespace }} ---- -kind: ClusterRole -apiVersion: rbac.authorization.k8s.io/v1 -metadata: - name: ray-operator-clusterrole -rules: -- apiGroups: ["", "cluster.ray.io"] - resources: ["rayclusters", "rayclusters/finalizers", "rayclusters/status", "pods", "pods/exec", "services"] - verbs: ["get", "watch", "list", "create", "delete", "patch", "update"] -- apiGroups: [""] - resources: [events] - verbs: [create] ---- -apiVersion: rbac.authorization.k8s.io/v1 -kind: ClusterRoleBinding -metadata: - name: ray-operator-clusterrolebinding -subjects: -- kind: ServiceAccount - name: ray-operator-serviceaccount - namespace: {{ .Values.operatorNamespace }} -roleRef: - kind: ClusterRole - name: ray-operator-clusterrole - apiGroup: rbac.authorization.k8s.io ---- -apiVersion: apps/v1 -kind: Deployment -metadata: - name: ray-operator - namespace: {{ .Values.operatorNamespace }} -spec: - replicas: 1 - selector: - matchLabels: - cluster.ray.io/component: operator - template: - metadata: - labels: - cluster.ray.io/component: operator - spec: - serviceAccountName: ray-operator-serviceaccount - containers: - - name: ray - imagePullPolicy: Always - image: {{ .Values.operatorImage }} - command: ["ray-operator"] - env: - - name: AUTOSCALER_MAX_NUM_FAILURES - value: "inf" - resources: - requests: - cpu: 1 - memory: 1Gi - ephemeral-storage: 1Gi - limits: - memory: 2Gi - cpu: 1 -{{- end }} diff --git a/tools/AutoTuner/helm-chart/templates/operator_namespaced.yaml b/tools/AutoTuner/helm-chart/templates/operator_namespaced.yaml deleted file mode 100644 index 4458b63059..0000000000 --- a/tools/AutoTuner/helm-chart/templates/operator_namespaced.yaml +++ /dev/null @@ -1,67 +0,0 @@ -{{- if and (.Values.namespacedOperator) (not .Values.clusterOnly) }} ---- -apiVersion: v1 -kind: ServiceAccount -metadata: - name: ray-operator-serviceaccount ---- -kind: Role -apiVersion: rbac.authorization.k8s.io/v1 -metadata: - name: ray-operator-role -rules: -- apiGroups: ["", "cluster.ray.io"] - resources: ["rayclusters", "rayclusters/finalizers", "rayclusters/status", "pods", "pods/exec", "services"] - verbs: ["get", "watch", "list", "create", "delete", "patch", "update"] -- apiGroups: [""] - resources: [events] - verbs: [create] ---- -apiVersion: rbac.authorization.k8s.io/v1 -kind: RoleBinding -metadata: - name: ray-operator-rolebinding -subjects: -- kind: ServiceAccount - name: ray-operator-serviceaccount -roleRef: - kind: Role - name: ray-operator-role - apiGroup: rbac.authorization.k8s.io ---- -apiVersion: apps/v1 -kind: Deployment -metadata: - name: ray-operator -spec: - replicas: 1 - selector: - matchLabels: - cluster.ray.io/component: operator - template: - metadata: - labels: - cluster.ray.io/component: operator - spec: - serviceAccountName: ray-operator-serviceaccount - containers: - - name: ray - imagePullPolicy: Always - image: {{ .Values.operatorImage }} - command: ["ray-operator"] - env: - - name: RAY_OPERATOR_POD_NAMESPACE - valueFrom: - fieldRef: - fieldPath: metadata.namespace - - name: AUTOSCALER_MAX_NUM_FAILURES - value: "inf" - resources: - requests: - cpu: 1 - memory: 1Gi - ephemeral-storage: 1Gi - limits: - memory: 2Gi - cpu: 1 -{{- end }} diff --git a/tools/AutoTuner/helm-chart/templates/raycluster.yaml b/tools/AutoTuner/helm-chart/templates/raycluster.yaml deleted file mode 100644 index 51c703fadf..0000000000 --- a/tools/AutoTuner/helm-chart/templates/raycluster.yaml +++ /dev/null @@ -1,107 +0,0 @@ -{{- if not .Values.operatorOnly }} -apiVersion: cluster.ray.io/v1 -kind: RayCluster -metadata: - name: {{ .Release.Name }} -spec: - # The maximum number of workers nodes to launch in addition to the head node. - maxWorkers: {{ include "ray.clusterMaxWorkers" . }} - # The autoscaler will scale up the cluster faster with higher upscaling speed. - # E.g., if the task requires adding more nodes then autoscaler will gradually - # scale up the cluster in chunks of upscaling_speed*currently_running_nodes. - # This number should be > 0. - upscalingSpeed: 1.0 - # If a node is idle for this many minutes, it will be removed. - idleTimeoutMinutes: 5 - # Specify the pod type for the ray head node (as configured below). - headPodType: {{ .Values.headPodType }} - # Specify the allowed pod types for this ray cluster and the resources they provide. - podTypes: - {{- range $key, $val := .Values.podTypes }} - - name: {{ $key }} - minWorkers: {{ $val.minWorkers | default 0}} - maxWorkers: {{ $val.maxWorkers | default 0}} - {{- if $val.rayResources }} - rayResources: - {{- toYaml $val.rayResources | nindent 8 }} - {{- end }} - podConfig: - apiVersion: v1 - kind: Pod - metadata: - generateName: {{ kebabcase $key }}- - spec: - restartPolicy: Never - # This volume allocates shared memory for Ray to use for its plasma - # object store. If you do not provide this, Ray will fall back to - # /tmp which cause slowdowns if is not a shared memory volume. - volumes: - - name: dshm - emptyDir: - medium: Memory - - name: nfs-share - persistentVolumeClaim: - claimName: nfs-dynamic-pvc - readOnly: false - - containers: - - name: ray-node - imagePullPolicy: Always - image: {{ $.Values.image }} - # Do not change this command - it keeps the pod alive until it is - # explicitly killed. - command: ["/bin/bash", "-c", "--"] - args: ['trap : TERM INT; sleep infinity & wait;'] - env: - - name: RAY_gcs_server_rpc_server_thread_num - value: "1" - ports: - - containerPort: 6379 # Redis port for Ray <= 1.10.0. GCS server port for Ray >= 1.11.0. - - containerPort: 10001 # Used by Ray Client - - containerPort: 8265 # Used by Ray Dashboard - - containerPort: 8000 # Used by Ray Serve - - # This volume allocates shared memory for Ray to use for its plasma - # object store. If you do not provide this, Ray will fall back to - # /tmp which cause slowdowns if is not a shared memory volume. - volumeMounts: - - mountPath: /dev/shm - name: dshm - - mountPath: /shared-data - name: nfs-share - resources: - requests: - cpu: {{ .CPU }} - memory: {{ .memory }} - limits: - cpu: {{ .CPU }} - # The maximum memory that this pod is allowed to use. The - # limit will be detected by ray and split to use 10% for - # redis, 30% for the shared memory object store, and the - # rest for application memory. If this limit is not set and - # the object store size is not set manually, ray will - # allocate a very large object store in each pod that may - # cause problems for other pods. - memory: {{ .memory }} - {{- if .GPU }} - nvidia.com/gpu: {{ .GPU }} - {{- end }} - {{- if .nodeSelector }} - nodeSelector: - {{- toYaml $val.nodeSelector | nindent 12 }} - {{- end }} - {{- if $val.tolerations }} - tolerations: - {{- toYaml $val.tolerations | nindent 10 }} - {{- end }} - {{- end }} - # Commands to start Ray on the head node. You don't need to change this. - # Note dashboard-host is set to 0.0.0.0 so that Kubernetes can port forward. - headStartRayCommands: - - ray stop - - ulimit -n 65536; ray start --head --port=6379 --no-monitor --dashboard-host 0.0.0.0 - # Commands to start Ray on worker nodes. You don't need to change this. - workerStartRayCommands: - - ray stop - - ulimit -n 65536; ray start --address=$RAY_HEAD_IP:6379 -{{- end }} diff --git a/tools/AutoTuner/helm-chart/values.yaml b/tools/AutoTuner/helm-chart/values.yaml deleted file mode 100644 index c420c5ffd0..0000000000 --- a/tools/AutoTuner/helm-chart/values.yaml +++ /dev/null @@ -1,107 +0,0 @@ -# Default values for Ray. - -# RayCluster settings: - -# image is Ray image to use for the head and workers of this Ray cluster. -# It's recommended to build custom dependencies for your workload into this image, -# taking one of the offical `rayproject/ray` images as base. -image: openroad/ray:latest -# headPodType is the podType used for the Ray head node (as configured below). -headPodType: rayHeadType -# podTypes is the list of pod configurations available for use as Ray nodes. -podTypes: - # The key for each podType is a user-defined string. - # Since we set headPodType: rayHeadType, the Ray head pod will use the configuration - # defined in this entry of podTypes: - rayHeadType: - # CPU is the number of CPUs used by this pod type. - # (Used for both requests and limits. Must be an integer, as Ray does not support fractional CPUs.) - CPU: 7 - # memory is the memory used by this Pod type. - # (Used for both requests and limits.) - memory: 24Gi - # GPU is the number of NVIDIA GPUs used by this pod type. - # (Optional, requires GPU nodes with appropriate setup. See https://docs.ray.io/en/master/cluster/kubernetes-gpu.html) - GPU: 0 - # rayResources is an optional string-int mapping signalling additional resources to Ray. - # "CPU", "GPU", and "memory" are filled automatically based on the above settings, but can be overriden; - # For example, rayResources: {"CPU": 0} can be used in the head podType to prevent Ray from scheduling tasks on the head. - # See https://docs.ray.io/en/master/advanced.html#dynamic-remote-parameters for an example of usage of custom resources in a Ray task. - rayResources: {"CPU": 0} - # Optionally, set a node selector for this podType: https://kubernetes.io/docs/concepts/scheduling-eviction/assign-pod-node/#nodeselector - nodeSelector: - cloud.google.com/gke-nodepool: default-pool - - # tolerations for Ray pods of this podType (the head's podType in this case) - # ref: https://kubernetes.io/docs/concepts/configuration/taint-and-toleration/ - # Note that it is often not necessary to manually specify tolerations for GPU - # usage on managed platforms such as AKS, EKS, and GKE. - # ref: https://docs.ray.io/en/master/cluster/kubernetes-gpu.html - tolerations: [] - # - key: "nvidia.com/gpu" - # operator: Exists - # effect: NoSchedule - - # The key for each podType is a user-defined string. - rayWorkerType: - # minWorkers is the minimum number of Ray workers of this pod type to keep running. - minWorkers: 2 - # maxWorkers is the maximum number of Ray workers of this pod type to which Ray will scale. - maxWorkers: 30 - # memory is the memory used by this Pod type. - # (Used for both requests and limits.) - memory: 100Gi - # CPU is the number of CPUs used by this pod type. - # (Used for both requests and limits. Must be an integer, as Ray does not support fractional CPUs.) - CPU: 28 - # GPU is the number of NVIDIA GPUs used by this pod type. - # (Optional, requires GPU nodes with appropriate setup. See https://docs.ray.io/en/master/cluster/kubernetes-gpu.html) - GPU: 0 - # rayResources is an optional string-int mapping signalling additional resources to Ray. - # "CPU", "GPU", and "memory" are filled automatically based on the above settings, but can be overriden; - # For example, rayResources: {"CPU": 0} can be used in the head podType to prevent Ray from scheduling tasks on the head. - # See https://docs.ray.io/en/master/advanced.html#dynamic-remote-parameters for an example of usage of custom resources in a Ray task. - rayResources: {} - # Optionally, set a node selector for this Pod type. See https://kubernetes.io/docs/concepts/scheduling-eviction/assign-pod-node/#nodeselector - nodeSelector: - cloud.google.com/gke-nodepool: worker-pool - - # tolerations for Ray pods of this podType - # ref: https://kubernetes.io/docs/concepts/configuration/taint-and-toleration/ - # Note that it is often not necessary to manually specify tolerations for GPU - # usage on managed platforms such as AKS, EKS, and GKE. - # ref: https://docs.ray.io/en/master/cluster/kubernetes-gpu.html - tolerations: [] - # - key: nvidia.com/gpu - # operator: Exists - # effect: NoSchedule - - # Optionally, define more worker podTypes - # rayWorkerType2: - # minWorkers: 0 - # maxWorkers: 10 - # memory: ... - - -# Operator settings: - -# operatorOnly - If true, will only set up the Operator with this release, -# without launching a Ray cluster. -operatorOnly: false -# clusterOnly - If true, will only create a RayCluster resource with this release, -# without setting up the Operator. -# (Useful when launching multiple Ray clusters.) -clusterOnly: false -# namespacedOperator - If true, the operator is scoped to the Release namespace -# and only manages RayClusters in that namespace. -# By default, the operator is cluster-scoped and runs in the default namespace. -namespacedOperator: false -# operatorNamepsace - If using a cluster-scoped operator (namespacedOperator: false), set the namespace -# in which to launch the operator. -operatorNamespace: default -# operatorImage - The image used in the operator deployment. -# It is recommended to use one of the official `rayproject/ray` images for the operator. -# It is recommended to use the same Ray version in the operator as in the Ray clusters managed -# by the operator. In other words, the images specified under the fields `operatorImage` and `image` -# should carry matching Ray versions. -operatorImage: rayproject/ray:latest diff --git a/tools/AutoTuner/kubernetes/Dockerfile b/tools/AutoTuner/kubernetes/Dockerfile deleted file mode 100644 index 8253aa52e1..0000000000 --- a/tools/AutoTuner/kubernetes/Dockerfile +++ /dev/null @@ -1,14 +0,0 @@ -FROM rayproject/ray:1.11.0 - -RUN pip install -U ax-platform hyperopt nevergrad optuna pandas - -RUN sudo apt-get update -y \ - && sudo apt-get install -y vim htop gcc time libffi-dev \ - && wget https://www.klayout.org/downloads/Ubuntu-20/klayout_0.27.1-1_amd64.deb \ - && sudo apt-get install -y --fix-broken ./klayout_0.27.1-1_amd64.deb \ - && rm ./klayout_0.27.1-1_amd64.deb - -RUN wget https://raw.githubusercontent.com/The-OpenROAD-Project/OpenROAD/master/etc/DependencyInstaller.sh \ - && sudo bash ./DependencyInstaller.sh -base \ - && sudo bash ./DependencyInstaller.sh -common \ - && rm DependencyInstaller.sh diff --git a/tools/AutoTuner/kubernetes/distributed-job-example.yaml b/tools/AutoTuner/kubernetes/distributed-job-example.yaml deleted file mode 100644 index 728e35c235..0000000000 --- a/tools/AutoTuner/kubernetes/distributed-job-example.yaml +++ /dev/null @@ -1,20 +0,0 @@ -# Job to submit a Ray program from a pod outside a running Ray cluster. -apiVersion: batch/v1 -kind: Job -metadata: - name: ray-test-job -spec: - template: - spec: - restartPolicy: Never - containers: - - name: ray - image: gcr.io/foss-fpga-tools-ext-openroad/ray - imagePullPolicy: Always - command: [ "/bin/bash", "-c", "--" ] - args: - - "echo " - resources: - requests: - cpu: 100m - memory: 512Mi diff --git a/tools/AutoTuner/kubernetes/run.py b/tools/AutoTuner/kubernetes/run.py deleted file mode 100644 index 186d72bf92..0000000000 --- a/tools/AutoTuner/kubernetes/run.py +++ /dev/null @@ -1,33 +0,0 @@ -"""This script is meant to be run from a pod in the same Kubernetes namespace -as your Ray cluster. -""" - -from collections import Counter -import sys -import time -import ray - - -@ray.remote -def gethostname(x): - import platform - - time.sleep(2) - return x + (platform.node(),) - - -def main(): - """ - Check that objects can be transferred from each node to each other node. - """ - results = [gethostname.remote(gethostname.remote(())) for _ in range(10)] - print(Counter(ray.get(results))) - sys.stdout.flush() - - print("Success!") - sys.stdout.flush() - - -if __name__ == "__main__": - ray.init("ray://127.0.0.1:10001") - main() diff --git a/tools/AutoTuner/kubernetes/submit.yaml b/tools/AutoTuner/kubernetes/submit.yaml deleted file mode 100644 index 10cb632e4b..0000000000 --- a/tools/AutoTuner/kubernetes/submit.yaml +++ /dev/null @@ -1,20 +0,0 @@ -# Job to submit a Ray program from a pod outside a running Ray cluster. -apiVersion: batch/v1 -kind: Job -metadata: - name: ray-test-job -spec: - template: - spec: - restartPolicy: Never - containers: - - name: ray - image: openroad/ray - imagePullPolicy: Always - command: [ "/bin/bash", "-c", "--" ] - args: - - "wget https://raw.githubusercontent.com/The-OpenROAD-Project/OpenROAD-flow-scripts/master/tools/AutoTuner/kubernetes/run.py && python run.py" - resources: - requests: - cpu: 100m - memory: 512Mi diff --git a/tools/AutoTuner/nfs/nfs-helm-values.yaml b/tools/AutoTuner/nfs/nfs-helm-values.yaml deleted file mode 100644 index 04b2fb41f1..0000000000 --- a/tools/AutoTuner/nfs/nfs-helm-values.yaml +++ /dev/null @@ -1,108 +0,0 @@ -replicaCount: 1 -strategyType: Recreate - -image: - # from https://github.com/kubernetes-sigs/nfs-subdir-external-provisioner - repository: k8s.gcr.io/sig-storage/nfs-subdir-external-provisioner - tag: v4.0.2 - pullPolicy: IfNotPresent -imagePullSecrets: [] - -nfs: - # TODO: check before deploying the chart - server: - # TODO: check before deploying the chart - path: - mountOptions: - volumeName: nfs-provisioner - # Reclaim policy for the main nfs volume - reclaimPolicy: Retain - -# For creating the StorageClass automatically: -storageClass: - create: true - - # Set a provisioner name. If unset, a name will be generated. - # provisionerName: - - # Set StorageClass as the default StorageClass - # Ignored if storageClass.create is false - defaultClass: false - - # Set a StorageClass name - # Ignored if storageClass.create is false - name: nfs-client - - # Allow volume to be expanded dynamically - allowVolumeExpansion: true - - # Method used to reclaim an obsoleted volume - reclaimPolicy: Delete - - # When set to false your PVs will not be archived by the provisioner upon deletion of the PVC. - archiveOnDelete: false - - # If it exists and has 'delete' value, delete the directory. If it exists and has 'retain' value, save the directory. - # Overrides archiveOnDelete. - # Ignored if value not set. - onDelete: - - # Specifies a template for creating a directory path via PVC metadata's such as labels, annotations, name or namespace. - # Ignored if value not set. - pathPattern: - - # Set access mode - ReadWriteOnce, ReadOnlyMany or ReadWriteMany - accessModes: ReadWriteOnce - - # Storage class annotations - annotations: {} - -leaderElection: - # When set to false leader election will be disabled - enabled: true - -## For RBAC support: -rbac: - # Specifies whether RBAC resources should be created - create: true - -# If true, create & use Pod Security Policy resources -# https://kubernetes.io/docs/concepts/policy/pod-security-policy/ -podSecurityPolicy: - enabled: false - -# Deployment pod annotations -podAnnotations: {} - -## Set pod priorityClassName -# priorityClassName: "" - -serviceAccount: - # Specifies whether a ServiceAccount should be created - create: true - - # Annotations to add to the service account - annotations: {} - - # The name of the ServiceAccount to use. - # If not set and create is true, a name is generated using the fullname template - name: - -resources: {} - # limits: - # cpu: 100m - # memory: 128Mi - # requests: - # cpu: 100m - # memory: 128Mi - -# TODO: check before deploying the chart -nodeSelector: - cloud.google.com/gke-nodepool: default-pool - -tolerations: [] - -affinity: {} - -# Additional labels for any resource created -labels: {} diff --git a/tools/AutoTuner/nfs/nfs-pvc.yaml b/tools/AutoTuner/nfs/nfs-pvc.yaml deleted file mode 100644 index eac3a60343..0000000000 --- a/tools/AutoTuner/nfs/nfs-pvc.yaml +++ /dev/null @@ -1,11 +0,0 @@ -apiVersion: v1 -kind: PersistentVolumeClaim -metadata: - name: nfs-dynamic-pvc -spec: - storageClassName: nfs-client - accessModes: - - ReadWriteMany - resources: - requests: - storage: 1000Gi diff --git a/tools/AutoTuner/requirements.txt b/tools/AutoTuner/requirements.txt index 42a0c73e91..d4a4dbe5ff 100644 --- a/tools/AutoTuner/requirements.txt +++ b/tools/AutoTuner/requirements.txt @@ -5,7 +5,7 @@ optuna==3.6.0 pandas>=2.0,<=2.2.1 bayesian-optimization==1.4.0 colorama==0.4.6 -tensorboard>=2.14.0,<=2.16.2 +tensorboard>=2.17.0 protobuf>=5.26.1 SQLAlchemy==1.4.17 urllib3>=1.26.17 diff --git a/tools/AutoTuner/src/autotuner/distributed.py b/tools/AutoTuner/src/autotuner/distributed.py index 577d368ab8..2d87b710ac 100644 --- a/tools/AutoTuner/src/autotuner/distributed.py +++ b/tools/AutoTuner/src/autotuner/distributed.py @@ -104,8 +104,6 @@ ORFS_FLOW_DIR = os.path.abspath( os.path.join(os.path.dirname(__file__), "../../../../flow") ) -# URL to ORFS GitHub repository -ORFS_URL = "https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts" # Global variable for args args = None @@ -156,8 +154,8 @@ def step(self): install_path=INSTALL_PATH, ) self.step_ += 1 - (score, effective_clk_period, num_drc) = self.evaluate( - read_metrics(metrics_file) + (score, effective_clk_period, num_drc, die_area) = self.evaluate( + read_metrics(metrics_file, args.stop_stage) ) # Feed the score back to Tune. # return must match 'metric' used in tune.run() @@ -165,6 +163,7 @@ def step(self): METRIC: score, "effective_clk_period": effective_clk_period, "num_drc": num_drc, + "die_area": die_area, } def evaluate(self, metrics): @@ -176,13 +175,13 @@ def evaluate(self, metrics): error = "ERR" in metrics.values() not_found = "N/A" in metrics.values() if error or not_found: - return (ERROR_METRIC, "-", "-") + return (ERROR_METRIC, "-", "-", "-") effective_clk_period = metrics["clk_period"] - metrics["worst_slack"] num_drc = metrics["num_drc"] gamma = effective_clk_period / 10 score = effective_clk_period score = score * (100 / self.step_) + gamma * num_drc - return (score, effective_clk_period, num_drc) + return (score, effective_clk_period, num_drc, metrics["die_area"]) def _is_valid_config(self, config): """ @@ -249,13 +248,13 @@ def evaluate(self, metrics): error = "ERR" in metrics.values() or "ERR" in reference.values() not_found = "N/A" in metrics.values() or "N/A" in reference.values() if error or not_found: - return (ERROR_METRIC, "-", "-") + return (ERROR_METRIC, "-", "-", "-") ppa = self.get_ppa(metrics) gamma = ppa / 10 score = ppa * (self.step_ / 100) ** (-1) + (gamma * metrics["num_drc"]) effective_clk_period = metrics["clk_period"] - metrics["worst_slack"] num_drc = metrics["num_drc"] - return (score, effective_clk_period, num_drc) + return (score, effective_clk_period, num_drc, metrics["die_area"]) def parse_arguments(): @@ -309,6 +308,14 @@ def parse_arguments(): default=None, help="Time limit (in hours) for each trial run. Default is no limit.", ) + parser.add_argument( + "--stop_stage", + type=str, + metavar="", + choices=["floorplan", "place", "cts", "globalroute", "route", "finish"], + default="finish", + help="Name of the stage to stop after. Default is finish.", + ) tune_parser.add_argument( "--resume", action="store_true", @@ -316,60 +323,6 @@ def parse_arguments(): name identifier via `--experiment NAME` to be able to resume.", ) - # Setup - parser.add_argument( - "--git_clean", - action="store_true", - help="Clean binaries and build files." - " WARNING: may lose previous data." - " Use carefully.", - ) - parser.add_argument( - "--git_clone", - action="store_true", - help="Force new git clone." - " WARNING: may lose previous data." - " Use carefully.", - ) - parser.add_argument( - "--git_clone_args", - type=str, - metavar="", - default="", - help="Additional git clone arguments.", - ) - parser.add_argument( - "--git_latest", action="store_true", help="Use latest version of OpenROAD app." - ) - parser.add_argument( - "--git_or_branch", - type=str, - metavar="", - default="", - help="OpenROAD app branch to use.", - ) - parser.add_argument( - "--git_orfs_branch", - type=str, - metavar="", - default="master", - help="OpenROAD-flow-scripts branch to use.", - ) - parser.add_argument( - "--git_url", - type=str, - metavar="", - default=ORFS_URL, - help="OpenROAD-flow-scripts repo URL to use.", - ) - parser.add_argument( - "--build_args", - type=str, - metavar="", - default="", - help="Additional arguments given to ./build_openroad.sh.", - ) - # ML tune_parser.add_argument( "--algorithm", @@ -621,9 +574,7 @@ def sweep(): temp = dict() for value in parameter: temp.update(value) - queue.put( - [args, repo_dir, temp, LOCAL_DIR, SDC_ORIGINAL, FR_ORIGINAL, INSTALL_PATH] - ) + queue.put([args, repo_dir, temp, SDC_ORIGINAL, FR_ORIGINAL, INSTALL_PATH]) workers = [consumer.remote(queue) for _ in range(args.jobs)] print("[INFO TUN-0009] Waiting for results.") ray.get(workers) @@ -656,7 +607,7 @@ def main(): TrainClass = set_training_class(args.eval) # PPAImprov requires a reference file to compute training scores. if args.eval == "ppa-improv": - reference = read_metrics(args.reference) + reference = read_metrics(args.reference, args.stop_stage) tune_args = dict( name=args.experiment, @@ -689,7 +640,7 @@ def main(): # if all runs have failed if analysis.best_result[METRIC] == ERROR_METRIC: print("[ERROR TUN-0016] No successful runs found.") - sys.exit(1) + sys.exit(16) elif args.mode == "sweep": sweep() diff --git a/tools/AutoTuner/src/autotuner/utils.py b/tools/AutoTuner/src/autotuner/utils.py index 7c6e999653..61aebb3390 100644 --- a/tools/AutoTuner/src/autotuner/utils.py +++ b/tools/AutoTuner/src/autotuner/utils.py @@ -40,10 +40,10 @@ import yaml import subprocess import sys +import uuid +import time from multiprocessing import cpu_count from datetime import datetime -from uuid import uuid4 as uuid -from time import time import numpy as np import ray @@ -307,8 +307,14 @@ def openroad( base_dir, f"flow/reports/{args.platform}/{args.design}", flow_variant ) ) + results_path = os.path.abspath( + os.path.join( + base_dir, f"flow/results/{args.platform}/{args.design}", flow_variant + ) + ) os.makedirs(log_path, exist_ok=True) os.makedirs(report_path, exist_ok=True) + os.makedirs(results_path, exist_ok=True) if install_path is None: install_path = os.path.join(base_dir, "tools/install") @@ -324,6 +330,8 @@ def openroad( make_command += f" FLOW_VARIANT={flow_variant} {parameters}" make_command += " EQUIVALENCE_CHECK=0" make_command += f" NUM_CORES={args.openroad_threads} SHELL=bash" + if args.stop_stage != "finish": + make_command += f" {args.stop_stage}" run_command( args, make_command, @@ -338,6 +346,9 @@ def openroad( metrics_command += f" -v {flow_variant}" metrics_command += f" -d {args.design}" metrics_command += f" -p {args.platform}" + metrics_command += f" --logs {log_path}" + metrics_command += f" --reports {report_path}" + metrics_command += f" --results {results_path}" metrics_command += f" -o {metrics_file}" run_command( args, @@ -349,22 +360,29 @@ def openroad( return metrics_file -def read_metrics(file_name): +def read_metrics(file_name, stop_stage): """ Collects metrics to evaluate the user-defined objective function. + + stop_stage indicates the last stage executed, so get most of the metrics + from that stage. The default stop stage is "finish". But if the run stops + before "finish", then no need to extract the metrics from the route stage, + so set them to 0 """ with open(file_name) as file: data = json.load(file) clk_period = 9999999 worst_slack = "ERR" - wirelength = "ERR" - num_drc = "ERR" total_power = "ERR" core_util = "ERR" final_util = "ERR" design_area = "ERR" die_area = "ERR" core_area = "ERR" + if stop_stage != "finish": + num_drc = wirelength = 0 + else: + num_drc = wirelength = "ERR" for stage_name, value in data.items(): if stage_name == "constraints" and len(value["clocks__details"]) > 0: clk_period = float(value["clocks__details"][0].split()[1]) @@ -374,17 +392,17 @@ def read_metrics(file_name): num_drc = value["route__drc_errors"] if stage_name == "detailedroute" and "route__wirelength" in value: wirelength = value["route__wirelength"] - if stage_name == "finish" and "timing__setup__ws" in value: + if stage_name == stop_stage and "timing__setup__ws" in value: worst_slack = value["timing__setup__ws"] - if stage_name == "finish" and "power__total" in value: + if stage_name == stop_stage and "power__total" in value: total_power = value["power__total"] - if stage_name == "finish" and "design__instance__utilization" in value: + if stage_name == stop_stage and "design__instance__utilization" in value: final_util = value["design__instance__utilization"] - if stage_name == "finish" and "design__instance__area" in value: + if stage_name == stop_stage and "design__instance__area" in value: design_area = value["design__instance__area"] - if stage_name == "finish" and "design__core__area" in value: + if stage_name == stop_stage and "design__core__area" in value: core_area = value["design__core__area"] - if stage_name == "finish" and "design__die__area" in value: + if stage_name == stop_stage and "design__die__area" in value: die_area = value["design__die__area"] ret = { "clk_period": clk_period, @@ -571,91 +589,25 @@ def read_tune_pbt(name, this): return config, sdc_file, fr_file -def clone(args, path): - """ - Clone base repo in the remote machine. Only used for Kubernetes at GCP. - """ - if args.git_clone: - run_command(args, f"rm -rf {path}") - if not os.path.isdir(f"{path}/.git"): - git_command = "git clone --depth 1 --recursive --single-branch" - git_command += f" {args.git_clone_args}" - git_command += f" --branch {args.git_orfs_branch}" - git_command += f" {args.git_url} {path}" - run_command(args, git_command) - - -def build(args, base, install): - """ - Build OpenROAD, Yosys and other dependencies. - """ - build_command = f'cd "{base}"' - if args.git_clean: - build_command += " && git clean -xdf tools" - build_command += " && git submodule foreach --recursive git clean -xdf" - if ( - args.git_clean - or not os.path.isfile(f"{install}/OpenROAD/bin/openroad") - or not os.path.isfile(f"{install}/yosys/bin/yosys") - ): - build_command += ' && bash -ic "./build_openroad.sh' - # Some GCP machines have 200+ cores. Let's be reasonable... - build_command += f" --local --nice --threads {min(32, cpu_count())}" - if args.git_latest: - build_command += " --latest" - build_command += f' {args.build_args}"' - run_command(args, build_command) - - -@ray.remote -def setup_repo(args, base): - """ - Clone ORFS repository and compile binaries. - """ - print(f"[INFO TUN-0000] Remote folder: {base}") - install = f"{base}/tools/install" - if args.server is not None: - clone(base) - build(base, install) - return install - - def prepare_ray_server(args): """ Prepares Ray server and returns basic directories. """ # Connect to remote Ray server if any, otherwise will run locally if args.server is not None: - # At GCP we have a NFS folder that is present for all worker nodes. - # This allows to build required binaries once. We clone, build and - # store intermediate files at LOCAL_DIR. - with open(args.config) as config_file: - local_dir = "/shared-data/autotuner" - local_dir += f"-orfs-{args.git_orfs_branch}" - if args.git_or_branch != "": - local_dir += f"-or-{args.git_or_branch}" - if args.git_latest: - local_dir += "-or-latest" # Connect to ray server before first remote execution. ray.init(f"ray://{args.server}:{args.port}") - # Remote functions return a task id and are non-blocking. Since we - # need the setup repo before continuing, we call ray.get() to wait - # for its completion. - install_path = ray.get(setup_repo.remote(local_dir)) - orfs_flow_dir = os.path.join(local_dir, "flow") - local_dir += f"/flow/logs/{args.platform}/{args.design}" - print("[INFO TUN-0001] NFS setup completed.") - else: - orfs_dir = getattr(args, "orfs", None) - # For local runs, use the same folder as other ORFS utilities. - orfs_flow_dir = os.path.abspath( - os.path.join(orfs_dir, "flow") - if orfs_dir - else os.path.join(os.path.dirname(__file__), "../../../../flow") - ) - local_dir = f"logs/{args.platform}/{args.design}" - local_dir = os.path.join(orfs_flow_dir, local_dir) - install_path = os.path.abspath(os.path.join(orfs_flow_dir, "../tools/install")) + print("[INFO TUN-0001] Connected to Ray server.") + # Common variables used for local and remote runs. + orfs_dir = getattr(args, "orfs", None) + orfs_flow_dir = os.path.abspath( + os.path.join(orfs_dir, "flow") + if orfs_dir + else os.path.join(os.path.dirname(__file__), "../../../../flow") + ) + local_dir = f"logs/{args.platform}/{args.design}" + local_dir = os.path.join(orfs_flow_dir, local_dir) + install_path = os.path.abspath(os.path.join(orfs_flow_dir, "../tools/install")) return local_dir, orfs_flow_dir, install_path @@ -681,15 +633,15 @@ def openroad_distributed( ) if variant is None: variant = config.replace(" ", "_").replace("=", "_") - t = time() + t = time.time() metric_file = openroad( args=args, base_dir=repo_dir, parameters=config, - flow_variant=f"{uuid()}-{variant}", + flow_variant=f"{uuid.uuid4()}-{variant}" if variant else f"{uuid.uuid4()}", install_path=install_path, ) - duration = time() - t + duration = time.time() - t return metric_file, duration diff --git a/tools/AutoTuner/test/autotuner_test_utils.py b/tools/AutoTuner/test/autotuner_test_utils.py index e52b2606ff..3058bb6c4a 100644 --- a/tools/AutoTuner/test/autotuner_test_utils.py +++ b/tools/AutoTuner/test/autotuner_test_utils.py @@ -35,6 +35,9 @@ import os +# Accepted RC: success and failed with no valid results. +accepted_rc = [0, 16] + class AutoTunerTestUtils: @staticmethod diff --git a/tools/AutoTuner/test/ref_file_check.py b/tools/AutoTuner/test/ref_file_check.py index ea58651bb5..bb02a868cd 100644 --- a/tools/AutoTuner/test/ref_file_check.py +++ b/tools/AutoTuner/test/ref_file_check.py @@ -44,31 +44,66 @@ class RefFileCheck(unittest.TestCase): - # only test 1 platform/design. - platform = "asap7" - design = "gcd" + """ + Tests situations where a referenced file (SDC or FastRoute) is not + defined in the AutoTuner config + """ def setUp(self): - configs = [ - "../../test/files/no_sdc_ref.json", - "../../test/files/no_fr_ref.json", - ] - self.exec = AutoTunerTestUtils.get_exec_cmd() - self.commands = [ - f"{self.exec}" - f" --design {self.design}" - f" --platform {self.platform}" - f" --config {c}" - f" tune --samples 1" - for c in configs - ] - - # Make this a test case - def test_files(self): - for c in self.commands: - out = subprocess.run(c, shell=True) - failed = out.returncode != 0 - self.assertTrue(failed) + self._cur_dir = os.path.dirname(os.path.abspath(__file__)) + src_dir = os.path.join(self._cur_dir, "../src") + os.chdir(src_dir) + + self._exec = AutoTunerTestUtils.get_exec_cmd() + + def _execute_autotuner(self, platform, design, config_file, error_code=None): + full_path = os.path.abspath(os.path.join(self._cur_dir, config_file)) + + cmd = f"{self._exec} --design {design} --platform {platform} --config {full_path} tune --samples 1" + + out = subprocess.run(cmd, shell=True, text=True, capture_output=True) + failed = out.returncode != 0 + self.assertTrue(failed, f"AT run with {config_file} passed") + if error_code: + self.assertTrue( + error_code in out.stdout, + f"Didn't find error code {error_code} in output '{out.stdout}'", + ) + + def test_asap_gcd_no_sdc(self): + """ + Tests when SDC file is not defined, which is an error for all + platforms and designs + """ + + platform = "asap7" + design = "gcd" + config_file = "files/no_sdc_ref.json" + error_code = "[ERROR TUN-0020] No SDC reference" + self._execute_autotuner(platform, design, config_file, error_code) + + def test_asap_gcd_no_fr(self): + """ + Tests when FastRoute file is not defined, which is not an error for + asap platform. This test fails anyway + """ + + platform = "asap7" + design = "gcd" + config_file = "files/no_fr_ref.json" + self._execute_autotuner(platform, design, config_file) + + def test_ihp_gcd_no_fr(self): + """ + Tests when FastRoute file is not defined, which is not an error for + any non-asap7 platform. + """ + + platform = "ihp-sg13g2" + design = "gcd" + config_file = "files/no_fr_ref.json" + error_code = "[ERROR TUN-0021] No FastRoute Tcl" + self._execute_autotuner(platform, design, config_file, error_code) if __name__ == "__main__": diff --git a/tools/AutoTuner/test/resume_check.py b/tools/AutoTuner/test/resume_check.py index ea1a511ab0..69eaec1f24 100644 --- a/tools/AutoTuner/test/resume_check.py +++ b/tools/AutoTuner/test/resume_check.py @@ -36,7 +36,7 @@ import subprocess import os import time -from .autotuner_test_utils import AutoTunerTestUtils +from .autotuner_test_utils import AutoTunerTestUtils, accepted_rc from contextlib import contextmanager @@ -108,7 +108,7 @@ def test_tune_resume(self): proc = subprocess.run("ray status", shell=True) no_nodes = proc.returncode != 0 proc = subprocess.run("ray stop", shell=True) - successful = proc.returncode == 0 + successful = proc.returncode in accepted_rc if no_nodes and successful: break @@ -117,7 +117,7 @@ def test_tune_resume(self): # Run the second config to completion print("Running the second config") proc = subprocess.run(self.commands[1], shell=True) - successful = proc.returncode == 0 + successful = proc.returncode in accepted_rc self.assertTrue(successful) diff --git a/tools/AutoTuner/test/smoke_test_algo_eval.py b/tools/AutoTuner/test/smoke_test_algo_eval.py index 89b3890669..01fdc95403 100644 --- a/tools/AutoTuner/test/smoke_test_algo_eval.py +++ b/tools/AutoTuner/test/smoke_test_algo_eval.py @@ -35,7 +35,7 @@ import unittest import subprocess import os -from .autotuner_test_utils import AutoTunerTestUtils +from .autotuner_test_utils import AutoTunerTestUtils, accepted_rc cur_dir = os.path.dirname(os.path.abspath(__file__)) orfs_dir = os.path.join(cur_dir, "../../../flow") @@ -74,8 +74,8 @@ def make_base(self): f"make -C {orfs_dir} DESIGN_CONFIG=./designs/{self.platform}/{self.design}/config.mk update_metadata_autotuner", ] for command in commands: - out = subprocess.run(command, shell=True, check=True) - self.assertTrue(out.returncode == 0) + out = subprocess.run(command, shell=True) + self.assertTrue(out.returncode in accepted_rc) def test_algo_eval(self): if not (self.platform and self.design): @@ -84,8 +84,8 @@ def test_algo_eval(self): self.make_base() for command in self.commands: print(command) - out = subprocess.run(command, shell=True, check=True) - successful = out.returncode == 0 + out = subprocess.run(command, shell=True) + successful = out.returncode in accepted_rc self.assertTrue(successful) diff --git a/tools/AutoTuner/test/smoke_test_sample_iteration.py b/tools/AutoTuner/test/smoke_test_sample_iteration.py index 03ab1a434a..8e3a6843d1 100644 --- a/tools/AutoTuner/test/smoke_test_sample_iteration.py +++ b/tools/AutoTuner/test/smoke_test_sample_iteration.py @@ -35,7 +35,7 @@ import unittest import subprocess import os -from .autotuner_test_utils import AutoTunerTestUtils +from .autotuner_test_utils import AutoTunerTestUtils, accepted_rc cur_dir = os.path.dirname(os.path.abspath(__file__)) @@ -67,8 +67,8 @@ def test_sample_iteration(self): raise unittest.SkipTest("Platform and design have to be defined") for command in self.commands: print(command) - out = subprocess.run(command, shell=True, check=True) - successful = out.returncode == 0 + out = subprocess.run(command, shell=True) + successful = out.returncode in accepted_rc self.assertTrue(successful) diff --git a/tools/AutoTuner/test/smoke_test_sweep.py b/tools/AutoTuner/test/smoke_test_sweep.py index 54e7d3a151..eb790441ff 100644 --- a/tools/AutoTuner/test/smoke_test_sweep.py +++ b/tools/AutoTuner/test/smoke_test_sweep.py @@ -36,7 +36,7 @@ import subprocess import os import json -from .autotuner_test_utils import AutoTunerTestUtils +from .autotuner_test_utils import AutoTunerTestUtils, accepted_rc cur_dir = os.path.dirname(os.path.abspath(__file__)) @@ -79,8 +79,8 @@ def setUp(self): def test_sweep(self): if not (self.platform and self.design): raise unittest.SkipTest("Platform and design have to be defined") - out = subprocess.run(self.command, shell=True, check=True) - successful = out.returncode == 0 + out = subprocess.run(self.command, shell=True) + successful = out.returncode in accepted_rc self.assertTrue(successful) diff --git a/tools/AutoTuner/test/smoke_test_tune.py b/tools/AutoTuner/test/smoke_test_tune.py index f8de878612..89cc83bf8b 100644 --- a/tools/AutoTuner/test/smoke_test_tune.py +++ b/tools/AutoTuner/test/smoke_test_tune.py @@ -35,7 +35,7 @@ import unittest import subprocess import os -from .autotuner_test_utils import AutoTunerTestUtils +from .autotuner_test_utils import AutoTunerTestUtils, accepted_rc cur_dir = os.path.dirname(os.path.abspath(__file__)) @@ -63,8 +63,8 @@ def setUp(self): def test_tune(self): if not (self.platform and self.design): raise unittest.SkipTest("Platform and design have to be defined") - out = subprocess.run(self.command, shell=True, check=True) - successful = out.returncode == 0 + out = subprocess.run(self.command, shell=True) + successful = out.returncode in accepted_rc self.assertTrue(successful) diff --git a/tools/OpenROAD b/tools/OpenROAD index a8ef34ce24..3ed3271270 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit a8ef34ce24825135f8f76d6fcc13094d19d460d2 +Subproject commit 3ed3271270f98a349fb6005755e91155fa3a755c diff --git a/tools/yosys b/tools/yosys index c4b5190229..9ed031ddd5 160000 --- a/tools/yosys +++ b/tools/yosys @@ -1 +1 @@ -Subproject commit c4b5190229616f7ebf8197f43990b4429de3e420 +Subproject commit 9ed031ddd588442f22be13ce608547a5809b62f0 diff --git a/tools/yosys-slang b/tools/yosys-slang new file mode 160000 index 0000000000..9d9ce7b767 --- /dev/null +++ b/tools/yosys-slang @@ -0,0 +1 @@ +Subproject commit 9d9ce7b767d2ea776e2dee0ef636a84512e6b229