From 01f6610a535e8c37e3bfe004e5d4e1bee6e2aaac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 28 Apr 2025 18:18:47 +0200 Subject: [PATCH 001/198] util: Update and enhance correlateRC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use `6_final.odb` guides as the basis for correlation. Make changes to the `6_net_rc.csv` format: * include information about the layer stack * include via count * include net classification (signal/clock) Change the method of obtaining the ground truth resistance from STA parasitic network. Include vias in correlation. Signed-off-by: Martin Povišer --- flow/util/correlateRC.py | 166 ++++++++++++++++++------------ flow/util/write_net_rc.tcl | 71 ++++++++----- flow/util/write_net_rc_script.tcl | 15 +-- 3 files changed, 148 insertions(+), 104 deletions(-) diff --git a/flow/util/correlateRC.py b/flow/util/correlateRC.py index bc046e94d2..9af693563d 100755 --- a/flow/util/correlateRC.py +++ b/flow/util/correlateRC.py @@ -5,9 +5,10 @@ # Use ORFS 'make write_net_rc' to write cap files. import os -from sys import exit +from sys import exit, stderr from collections import defaultdict +import traceback import collections import argparse import re @@ -81,6 +82,12 @@ def makeDict(): data = makeDict() +stack = [] +stack_line = None + +# indices of relevant layers (routable layers or via layers) +active_layers = set() + # Parse the cap CSV file generated by compare_rc_script.tcl for rc_file in args.rc_file: design = rc_file @@ -88,32 +95,42 @@ def makeDict(): with open(rc_file) as f: nonGrtNets = 0 for line in f: + if line.startswith("# stack: "): + if stack_line is not None and stack_line != line: + print(f"layer stack inconsistent", file=stderr) + exit(1) + elif stack_line is None: + for layer in line.removeprefix("# stack: ").strip().split(" "): + name = layer.removesuffix("(routing)") + is_routing = layer.endswith("(routing)") + stack.append((name, is_routing)) + continue + tokens = line.strip().split(",") netName = tokens[0] - gpl_res = float(tokens[1]) - gpl_cap = float(tokens[2]) - grt_res = float(tokens[3]) - grt_cap = float(tokens[4]) - rcx_res = float(tokens[5]) - rcx_cap = float(tokens[6]) - - data[design][netName]["gpl_res"] = gpl_res - data[design][netName]["gpl_cap"] = gpl_cap - data[design][netName]["grt_res"] = grt_res - data[design][netName]["grt_cap"] = grt_cap - data[design][netName]["rcx_res"] = rcx_res - data[design][netName]["rcx_cap"] = rcx_cap - - layer_lengths = [] - layer_names = [] - wire_length = 0.0 - for i in range(7, len(tokens), 2): - layer_names.append(tokens[i]) - layer_length = float(tokens[i + 1]) - layer_lengths.append(layer_length) - wire_length += layer_length + + data[design][netName] = { + "type": tokens[1], + "gpl_res": float(tokens[2]), + "gpl_cap": float(tokens[3]), + "grt_res": float(tokens[4]), + "grt_cap": float(tokens[5]), + "rcx_res": float(tokens[6]), + "rcx_cap": float(tokens[7]), + } + + layer_lengths = [float(tok) for tok in tokens[8:]] + for i, length in enumerate(layer_lengths): + if length > 0: + active_layers.add(i) + data[design][netName]["layer_lengths"] = layer_lengths - data[design][netName]["wire_length"] = wire_length + data[design][netName]["wire_length"] = sum( + length + for i, length in enumerate(layer_lengths) + # ignore contribution from via layers + if stack[i][1] + ) ################################################################ @@ -210,8 +227,7 @@ def makeDict(): for net in data[design]: rcx_res = data[design][net]["rcx_res"] if rcx_res > 0: - layer_lengths = data[design][net]["layer_lengths"] - x.append(layer_lengths) + x.append(data[design][net]["layer_lengths"]) y.append(rcx_res) x = np.array(x) @@ -229,8 +245,8 @@ def makeDict(): y = [] for design in data: for net in data[design]: - layer_lengths = data[design][net]["layer_lengths"] - x.append(layer_lengths) + lengths = data[design][net]["layer_lengths"] + x.append([length for length, layer in zip(lengths, stack) if layer[1]]) y.append(data[design][net]["rcx_cap"]) x = np.array(x) @@ -241,48 +257,72 @@ def makeDict(): print("Capacitance coefficient of determination: {:.4f}".format(r_sq)) print("Updated layer resistance {}/um capacitance {}/um".format(res_unit, cap_unit)) -for layer, res_coeff, cap_coeff in zip(layer_names, res_model.coef_, cap_model.coef_): - if res_coeff > 0.0 or cap_coeff > 0.0: +routable_layer_no = 0 +for i, layer, res_coeff in zip(range(len(stack)), stack, res_model.coef_): + if not layer[1] or i not in active_layers: + # skip non-routable and non-active layers + continue + cap_coeff = cap_model.coef_[routable_layer_no] + print( + "set_layer_rc -layer {} -resistance {:.5E} -capacitance {:.5E}".format( + layer[0], res_coeff / res_scale, cap_coeff / cap_scale + ) + ) + routable_layer_no += 1 + +for i, layer, res_coeff in zip(range(len(stack)), stack, res_model.coef_): + if layer[1] or i not in active_layers: + # skip routable and non-active layers + continue + if res_coeff != 0.0: print( - "set_layer_rc -layer {} -resistance {:.5E} -capacitance {:.5E}".format( - layer, res_coeff / res_scale, cap_coeff / cap_scale + "set_layer_rc -via {} -resistance {:.5E}".format( + layer[0], res_coeff / res_scale ) ) ################################################################ -x = [] -y = [] -for design in data: - for net in data[design]: - wire_res = data[design][net]["rcx_res"] - wire_length = data[design][net]["wire_length"] - if wire_res != 0.0: - x.append([wire_length]) - y.append(wire_res) - -x = np.array(x) -y = np.array(y) - -wire_res_model = LinearRegression(fit_intercept=False).fit(x, y) -wire_res = wire_res_model.coef_[0] -x = [] -y = [] -for design in data: - for net in data[design]: - wire_length = data[design][net]["wire_length"] - x.append([wire_length]) - y.append(data[design][net]["rcx_cap"]) +def generic_rc_fit(type_sieve): + x = [] + y = [] + for design in data: + for net in data[design]: + net_type = data[design][net]["type"] + wire_res = data[design][net]["rcx_res"] + wire_length = data[design][net]["wire_length"] + if net_type in type_sieve and wire_res != 0.0: + x.append([wire_length]) + y.append(wire_res) + x = np.array(x) + y = np.array(y) + wire_res_model = LinearRegression(fit_intercept=False).fit(x, y) + wire_res = wire_res_model.coef_[0] + + x = [] + y = [] + for design in data: + for net in data[design]: + net_type = data[design][net]["type"] + if net_type in type_sieve: + wire_length = data[design][net]["wire_length"] + wire_cap = data[design][net]["rcx_cap"] + x.append([wire_length]) + y.append(wire_cap) + x = np.array(x) + y = np.array(y) + wire_cap_model = LinearRegression(fit_intercept=False).fit(x, y) + wire_cap = wire_cap_model.coef_[0] + + return "-resistance {:.5E} -capacitance {:.5E}".format( + wire_res / res_scale, wire_cap / cap_scale + ) -x = np.array(x) -y = np.array(y) -wire_cap_model = LinearRegression(fit_intercept=False).fit(x, y) -wire_cap = wire_cap_model.coef_[0] +print("# Combined fit:") +print("set_wire_rc " + generic_rc_fit(["signal", "clock"])) -print( - "set_wire_rc -resistance {:.5E} -capacitance {:.5E}".format( - wire_res / res_scale, wire_cap / cap_scale - ) -) +print("# Split signal/clock fit:") +print("set_wire_rc -signal " + generic_rc_fit(["signal"])) +print("set_wire_rc -clock " + generic_rc_fit(["clock"])) diff --git a/flow/util/write_net_rc.tcl b/flow/util/write_net_rc.tcl index 5b028f9417..75f91af3fa 100644 --- a/flow/util/write_net_rc.tcl +++ b/flow/util/write_net_rc.tcl @@ -37,25 +37,52 @@ proc write_rc_csv { filename } { upvar 1 grt rc_var2 upvar 1 rcx rc_var3 - set max_layer_name $::env(MAX_ROUTING_LAYER) - set max_layer [[[ord::get_db_tech] findLayer $max_layer_name] getRoutingLevel] - set min_layer_name $::env(MIN_ROUTING_LAYER) - set min_layer [[[ord::get_db_tech] findLayer $min_layer_name] getRoutingLevel] + set tech [ord::get_db_tech] set stream [open $filename "w"] + + puts -nonewline $stream "# stack:" + foreach layer [[ord::get_db_tech] getLayers] { + set routing [expr [$layer getRoutingLevel] != 0] + set is_routing([$layer getNumber]) $routing + puts -nonewline $stream " [$layer getName]" + if $routing { + puts -nonewline $stream "(routing)" + } + } + puts $stream "" + + set use_drt_data [env_var_exists_and_non_empty CORRELATE_DRT_WIRELENGTH] + foreach net [get_nets *] { - set net_name [get_full_name $net] - lassign $rc_var1($net_name) wire_res1 wire_cap1 - lassign $rc_var2($net_name) wire_res2 wire_cap2 - lassign $rc_var3($net_name) wire_res3 wire_cap3 - puts -nonewline $stream "[get_full_name $net],[format %.3e $wire_res1],[format %.3e $wire_cap1],[format %.3e $wire_res2],[format %.3e $wire_cap2],[format %.3e $wire_res3],[format %.3e $wire_cap3]" set db_net [sta::sta_to_db_net $net] - set layer_lengths [grt::route_layer_lengths $db_net] - for {set layer $min_layer} {$layer <= $max_layer} {incr layer} { - set layer_name [[[ord::get_db_tech] findRoutingLayer $layer] getName] - set length [lindex $layer_lengths $layer] - puts -nonewline $stream ",$layer_name,[ord::dbu_to_microns $length]" + set type [$db_net getSigType] + if {([string equal $type "CLOCK"] || [string equal $type "SIGNAL"]) && + (!$use_drt_data || [$db_net getWire] ne "NULL")} { + set net_name [get_full_name $net] + lassign $rc_var1($net_name) wire_res1 wire_cap1 + lassign $rc_var2($net_name) wire_res2 wire_cap2 + lassign $rc_var3($net_name) wire_res3 wire_cap3 + puts -nonewline $stream "[get_full_name $net],[expr {[string equal $type "CLOCK"] ? "clock" : "signal"}]," + puts -nonewline $stream "[format %.3e $wire_res1],[format %.3e $wire_cap1],[format %.3e $wire_res2],[format %.3e $wire_cap2],[format %.3e $wire_res3],[format %.3e $wire_cap3]" + set db_net [sta::sta_to_db_net $net] + + if $use_drt_data { + set layer_lengths [drt::route_layer_lengths [$db_net getWire]] + } else { + set layer_lengths [grt::route_layer_lengths $db_net] + } + + for {set layer 0} {$layer < [$tech getLayerCount]} {incr layer} { + set length [lindex $layer_lengths $layer] + if $is_routing($layer) { + puts -nonewline $stream ",[ord::dbu_to_microns $length]" + } else { + puts -nonewline $stream ",$length" + } + } + + puts $stream "" } - puts $stream "" } close $stream } @@ -73,19 +100,7 @@ proc record_wire_rc { var_name } { # Only works or makes sense for 2 pin nets. proc net_wire_res { net } { - set pins [get_pins -of_object $net] - if { [llength $pins] == 2 } { - lassign $pins pin1 pin2 - if { [$pin1 is_driver] } { - set drvr $pin1 - } else { - set drvr $pin2 - } - lassign [sta::find_pi_elmore $drvr rise max] c2 rpi c1 - return $rpi - } else { - return 0.0 - } + return [rsz::sum_parasitic_network_resist $net] } proc net_wire_cap { net } { diff --git a/flow/util/write_net_rc_script.tcl b/flow/util/write_net_rc_script.tcl index afda93c270..a2815ce5a6 100644 --- a/flow/util/write_net_rc_script.tcl +++ b/flow/util/write_net_rc_script.tcl @@ -1,26 +1,15 @@ source $::env(SCRIPTS_DIR)/load.tcl -# Note 6_final.def has wires that prevent global routing. -load_design 4_1_cts.odb 4_cts.sdc +load_design 6_final.odb 6_final.sdc source $::env(UTILS_DIR)/write_net_rc.tcl estimate_parasitics -placement record_wire_rc gpl -if {[env_var_exists_and_non_empty FASTROUTE_TCL]} { - source $env(FASTROUTE_TCL) -} else { - set_global_routing_layer_adjustment $env(MIN_ROUTING_LAYER)-$env(MAX_ROUTING_LAYER) 0.5 - set_routing_layers -signal $env(MIN_ROUTING_LAYER)-$env(MAX_ROUTING_LAYER) - set_macro_extension 2 -} - -global_route -congestion_iterations 100 - estimate_parasitics -global_routing record_wire_rc grt -read_spef -quiet -reduce_to pi_elmore $::env(RESULTS_DIR)/6_final.spef +read_spef $::env(RESULTS_DIR)/6_final.spef record_wire_rc rcx #compare_wire_rc 50 grt rcx From cd8df931a2efaf89e2c796b44acb2efdc351d139 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Wed, 7 May 2025 14:00:45 -0700 Subject: [PATCH 002/198] Add variable for move sequence selection. Signed-off-by: Matthew Guthaus --- flow/scripts/util.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl index 9f6c38fd4d..7c153b6fd5 100644 --- a/flow/scripts/util.tcl +++ b/flow/scripts/util.tcl @@ -31,6 +31,7 @@ proc repair_timing_helper { {hold_margin 1} } { if {$hold_margin || $::env(HOLD_SLACK_MARGIN) < 0} { append_env_var additional_args HOLD_SLACK_MARGIN -hold_margin 1 } + append_env_var additional_args SETUP_MOVE_SEQUENCE -sequence 1 append_env_var additional_args TNS_END_PERCENT -repair_tns 1 append_env_var additional_args SKIP_PIN_SWAP -skip_pin_swap 0 append_env_var additional_args SKIP_GATE_CLONING -skip_gate_cloning 0 From 4e8c6ed1961b98ed8cd4fc8cf5839d8fa78cf783 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Mon, 19 May 2025 17:49:02 -0300 Subject: [PATCH 003/198] add clock layer range for sky130hs Signed-off-by: Eder Monteiro --- flow/platforms/sky130hs/config.mk | 1 + flow/platforms/sky130hs/fastroute.tcl | 1 + 2 files changed, 2 insertions(+) diff --git a/flow/platforms/sky130hs/config.mk b/flow/platforms/sky130hs/config.mk index 73781e2512..5b66822431 100644 --- a/flow/platforms/sky130hs/config.mk +++ b/flow/platforms/sky130hs/config.mk @@ -77,6 +77,7 @@ export PLACE_DENSITY ?= 0.50 # --------------------------------------------------------- # FastRoute options export MIN_ROUTING_LAYER = met1 +export MIN_CLK_ROUTING_LAYER = met3 export MAX_ROUTING_LAYER = met5 # # Define fastRoute tcl diff --git a/flow/platforms/sky130hs/fastroute.tcl b/flow/platforms/sky130hs/fastroute.tcl index 06c2749720..76f9321967 100644 --- a/flow/platforms/sky130hs/fastroute.tcl +++ b/flow/platforms/sky130hs/fastroute.tcl @@ -1,3 +1,4 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.2 +set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) From f08ddb6693d887efb8a215dd57d50c6e4f9425a2 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Mon, 19 May 2025 17:55:44 -0300 Subject: [PATCH 004/198] add clock layer range for nangate45 Signed-off-by: Eder Monteiro --- flow/platforms/nangate45/config.mk | 1 + flow/platforms/nangate45/fastroute.tcl | 1 + 2 files changed, 2 insertions(+) diff --git a/flow/platforms/nangate45/config.mk b/flow/platforms/nangate45/config.mk index da73f6a986..d8b60131f4 100644 --- a/flow/platforms/nangate45/config.mk +++ b/flow/platforms/nangate45/config.mk @@ -72,6 +72,7 @@ export PLACE_DENSITY ?= 0.30 # --------------------------------------------------------- # FastRoute options export MIN_ROUTING_LAYER = metal2 +export MIN_CLK_ROUTING_LAYER = metal4 export MAX_ROUTING_LAYER = metal10 # Define fastRoute tcl diff --git a/flow/platforms/nangate45/fastroute.tcl b/flow/platforms/nangate45/fastroute.tcl index 2ec285bd96..7f6d9a242f 100644 --- a/flow/platforms/nangate45/fastroute.tcl +++ b/flow/platforms/nangate45/fastroute.tcl @@ -1,4 +1,5 @@ set_global_routing_layer_adjustment metal2-metal3 0.5 set_global_routing_layer_adjustment metal4-$::env(MAX_ROUTING_LAYER) 0.25 +set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) From d1c66b8731092f3838f728a38c064d0e3e0719f5 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Sat, 24 May 2025 16:33:58 -0700 Subject: [PATCH 005/198] Document SETUP_MOVE_SEQUENCE option Signed-off-by: Matthew Guthaus --- flow/scripts/variables.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 86d15317fb..cc620be517 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -484,6 +484,15 @@ SETUP_SLACK_MARGIN: - floorplan - grt default: 0 +SETUP_MOVE_SEQUENCE: + description: | + Specifies the sequence of moves to do in repair_timing -setup. This should be a string + of move keywords separated by commas such as the default when not used: + "unbuffer,sizedown,sizeup,swap,buffer,clone,split". + stages: + - cts + - floorplan + - grt SKIP_GATE_CLONING: description: > Do not use gate cloning transform to fix timing violations (default: use From 04090ad4342dbbc124567e7ed27572233b838be5 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Mon, 26 May 2025 14:18:11 -0300 Subject: [PATCH 006/198] use latest or master Signed-off-by: Eder Monteiro --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index 5e7c8c4f45..519227d1a0 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 5e7c8c4f45b21ff3e550cd9dc27070dd48ff4498 +Subproject commit 519227d1a0926e865af5887465991bc3c456e8aa From 6da7ffd398e888c15f031ccefa0d93dc3b02fb9b Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Wed, 28 May 2025 16:06:42 -0300 Subject: [PATCH 007/198] remove redundant fast_route calls Signed-off-by: Eder Monteiro --- flow/scripts/detail_route.tcl | 2 -- flow/scripts/global_route.tcl | 2 -- flow/scripts/open.tcl | 1 - 3 files changed, 5 deletions(-) diff --git a/flow/scripts/detail_route.tcl b/flow/scripts/detail_route.tcl index 330b93b49c..df1bdc1999 100644 --- a/flow/scripts/detail_route.tcl +++ b/flow/scripts/detail_route.tcl @@ -46,8 +46,6 @@ set all_args [concat [list \ log_cmd detailed_route {*}$all_args -fast_route - if {![env_var_equals SKIP_ANTENNA_REPAIR_POST_DRT 1]} { set repair_antennas_iters 1 if {[repair_antennas]} { diff --git a/flow/scripts/global_route.tcl b/flow/scripts/global_route.tcl index 32b33a0bb6..ecbf18109f 100644 --- a/flow/scripts/global_route.tcl +++ b/flow/scripts/global_route.tcl @@ -10,8 +10,6 @@ proc global_route_helper {} { source $::env(PRE_GLOBAL_ROUTE) } - fast_route - proc do_global_route {} { set all_args [concat [list \ -congestion_report_file $::global_route_congestion_report] \ diff --git a/flow/scripts/open.tcl b/flow/scripts/open.tcl index e2c411cfe1..79b8322dfe 100644 --- a/flow/scripts/open.tcl +++ b/flow/scripts/open.tcl @@ -69,4 +69,3 @@ if {[env_var_equals GUI_TIMING 1]} { } } -fast_route From 1d1c91a7b39b4633df77be496b1c810f895a9b12 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Wed, 28 May 2025 16:06:58 -0300 Subject: [PATCH 008/198] use latest openroad Signed-off-by: Eder Monteiro --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index 5e7c8c4f45..6c13d24b28 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 5e7c8c4f45b21ff3e550cd9dc27070dd48ff4498 +Subproject commit 6c13d24b282c9f8f46975ea18f1762c056486f89 From 41a62e33ede590b2caa79f1b5d9987180b4f3f84 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Wed, 28 May 2025 16:16:08 -0300 Subject: [PATCH 009/198] remove macro extensions Signed-off-by: Eder Monteiro --- flow/designs/gf12/bp_single/fastroute.tcl | 2 -- flow/designs/gf12/ca53/fastroute.tcl | 2 +- flow/scripts/util.tcl | 3 --- flow/tutorials/scripts/drt/drc_fix.tcl | 1 - flow/tutorials/scripts/drt/drc_issue.tcl | 1 - flow/util/write_net_rc_script.tcl | 1 - 6 files changed, 1 insertion(+), 9 deletions(-) diff --git a/flow/designs/gf12/bp_single/fastroute.tcl b/flow/designs/gf12/bp_single/fastroute.tcl index 91d3b4162f..24379738d7 100644 --- a/flow/designs/gf12/bp_single/fastroute.tcl +++ b/flow/designs/gf12/bp_single/fastroute.tcl @@ -5,5 +5,3 @@ set_global_routing_layer_adjustment K1-K4 0.45 set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) -clock K1-$::env(MAX_ROUTING_LAYER) -set_macro_extension 1 - diff --git a/flow/designs/gf12/ca53/fastroute.tcl b/flow/designs/gf12/ca53/fastroute.tcl index 78b39516da..177a36a3e5 100644 --- a/flow/designs/gf12/ca53/fastroute.tcl +++ b/flow/designs/gf12/ca53/fastroute.tcl @@ -4,4 +4,4 @@ set_global_routing_layer_adjustment C4-K4 0.5 #set_global_routing_layer_adjustment H1-H2 0.5 set_routing_layers -signal M2-$::env(MAX_ROUTING_LAYER) -clock K1-$::env(MAX_ROUTING_LAYER) -set_macro_extension 2 + diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl index 0123aaab6d..1230a98b7c 100644 --- a/flow/scripts/util.tcl +++ b/flow/scripts/util.tcl @@ -19,9 +19,6 @@ proc fast_route {} { } else { log_cmd set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) $::env(ROUTING_LAYER_ADJUSTMENT) log_cmd set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - if {[env_var_exists_and_non_empty MACRO_EXTENSION]} { - log_cmd set_macro_extension $::env(MACRO_EXTENSION) - } } } diff --git a/flow/tutorials/scripts/drt/drc_fix.tcl b/flow/tutorials/scripts/drt/drc_fix.tcl index 16e8030c85..e62042582a 100644 --- a/flow/tutorials/scripts/drt/drc_fix.tcl +++ b/flow/tutorials/scripts/drt/drc_fix.tcl @@ -8,7 +8,6 @@ read_sdc ./gcd/gcd.sdc # global_route set_global_routing_layer_adjustment met1-met5 0.5 set_routing_layers -signal met1-met5 -set_macro_extension 2 global_route -guide_file [make_result_file route.guide] \ -congestion_iterations 100 \ -verbose diff --git a/flow/tutorials/scripts/drt/drc_issue.tcl b/flow/tutorials/scripts/drt/drc_issue.tcl index 54a6427d45..0ea32dce63 100644 --- a/flow/tutorials/scripts/drt/drc_issue.tcl +++ b/flow/tutorials/scripts/drt/drc_issue.tcl @@ -8,7 +8,6 @@ read_sdc ./gcd/gcd.sdc # global_route set_global_routing_layer_adjustment met1-met5 0.5 set_routing_layers -signal met1-met5 -set_macro_extension 2 global_route -guide_file [make_result_file route.guide] \ -congestion_iterations 100 \ -verbose diff --git a/flow/util/write_net_rc_script.tcl b/flow/util/write_net_rc_script.tcl index afda93c270..5ac53c1c50 100644 --- a/flow/util/write_net_rc_script.tcl +++ b/flow/util/write_net_rc_script.tcl @@ -12,7 +12,6 @@ if {[env_var_exists_and_non_empty FASTROUTE_TCL]} { } else { set_global_routing_layer_adjustment $env(MIN_ROUTING_LAYER)-$env(MAX_ROUTING_LAYER) 0.5 set_routing_layers -signal $env(MIN_ROUTING_LAYER)-$env(MAX_ROUTING_LAYER) - set_macro_extension 2 } global_route -congestion_iterations 100 From 5af6310d377fb13ed9ab662ecf3887897006e930 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Wed, 28 May 2025 15:58:45 -0700 Subject: [PATCH 010/198] Change variable to SETUP_REPAIR_SEQUENCE Signed-off-by: Matthew Guthaus --- docs/user/FlowVariables.md | 4 ++++ flow/scripts/variables.yaml | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 3f1b488e51..a3dccce7a3 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -171,6 +171,7 @@ configuration file. | SDC_FILE| The path to design constraint (SDC) file.| | | | SDC_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | | | SEAL_GDS| Seal macro to place around the design.| | | +| SETUP_REPAIR_SEQUENCE| Specifies the sequence of moves to do in repair_timing -setup. This should be a string of move keywords separated by commas such as the default when not used: "unbuffer,sizedown,sizeup,swap,buffer,clone,split".| | | | SETUP_SLACK_MARGIN| Specifies a time margin for the slack when fixing setup violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). See HOLD_SLACK_MARGIN for more details.| 0| | | SET_RC_TCL| Metal & Via RC definition file path.| | | | SKIP_CTS_REPAIR_TIMING| Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running.| | | @@ -277,6 +278,7 @@ configuration file. - [RTLMP_RPT_DIR](#RTLMP_RPT_DIR) - [RTLMP_SIGNATURE_NET_THRESHOLD](#RTLMP_SIGNATURE_NET_THRESHOLD) - [RTLMP_WIRELENGTH_WT](#RTLMP_WIRELENGTH_WT) +- [SETUP_REPAIR_SEQUENCE](#SETUP_REPAIR_SEQUENCE) - [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SKIP_GATE_CLONING](#SKIP_GATE_CLONING) - [SKIP_LAST_GASP](#SKIP_LAST_GASP) @@ -323,6 +325,7 @@ configuration file. - [POST_CTS_TCL](#POST_CTS_TCL) - [REMOVE_CELLS_FOR_EQY](#REMOVE_CELLS_FOR_EQY) - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) +- [SETUP_REPAIR_SEQUENCE](#SETUP_REPAIR_SEQUENCE) - [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SKIP_CTS_REPAIR_TIMING](#SKIP_CTS_REPAIR_TIMING) - [SKIP_GATE_CLONING](#SKIP_GATE_CLONING) @@ -341,6 +344,7 @@ configuration file. - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) +- [SETUP_REPAIR_SEQUENCE](#SETUP_REPAIR_SEQUENCE) - [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SKIP_GATE_CLONING](#SKIP_GATE_CLONING) - [SKIP_INCREMENTAL_REPAIR](#SKIP_INCREMENTAL_REPAIR) diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index cc620be517..c6f8ab90f4 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -484,7 +484,7 @@ SETUP_SLACK_MARGIN: - floorplan - grt default: 0 -SETUP_MOVE_SEQUENCE: +SETUP_REPAIR_SEQUENCE: description: | Specifies the sequence of moves to do in repair_timing -setup. This should be a string of move keywords separated by commas such as the default when not used: From 982dcc9c85cc0746fb0bc2d62d4ab3fcf35a42ad Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Thu, 29 May 2025 16:44:04 -0300 Subject: [PATCH 011/198] use latest openroad Signed-off-by: Eder Monteiro --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index 6c13d24b28..d51df1dea5 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 6c13d24b282c9f8f46975ea18f1762c056486f89 +Subproject commit d51df1dea57f1bc70b25f46fef5ce7c396d26e99 From 25ba8fddd268874b3373b77af9afef754d372924 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Thu, 29 May 2025 16:44:55 -0300 Subject: [PATCH 012/198] enable post-drt repair antennas for ihp-sg13g2 designs Signed-off-by: Eder Monteiro --- flow/platforms/ihp-sg13g2/config.mk | 3 --- 1 file changed, 3 deletions(-) diff --git a/flow/platforms/ihp-sg13g2/config.mk b/flow/platforms/ihp-sg13g2/config.mk index 300626bfca..4f2440675c 100644 --- a/flow/platforms/ihp-sg13g2/config.mk +++ b/flow/platforms/ihp-sg13g2/config.mk @@ -143,9 +143,6 @@ export KLAYOUT_DRC_FILE ?= $(PLATFORM_DIR)/drc/sg13g2_minimal.lydrc export CDL_FILE ?= $(PLATFORM_DIR)/cdl/sg13g2_stdcell.cdl #export KLAYOUT_LVS_FILE = $(PLATFORM_DIR)/lvs/$(PLATFORM).lylvs -#Temporary: skip post-DRT repair antennas -export SKIP_ANTENNA_REPAIR_POST_DRT = 1 - # --------------------------------------------------------- # Final # --------------------------------------------------------- From 4f5b794cd4698d562c9970597374f2ece3ae12c8 Mon Sep 17 00:00:00 2001 From: Faholan <62927863+Faholan@users.noreply.github.com> Date: Thu, 29 May 2025 14:06:34 -0700 Subject: [PATCH 013/198] Fix jet set typo Signed-off-by: Faholan <62927863+Faholan@users.noreply.github.com> --- flow/scripts/variables.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/flow/scripts/variables.mk b/flow/scripts/variables.mk index 88f8b706fc..0292bf9f2d 100644 --- a/flow/scripts/variables.mk +++ b/flow/scripts/variables.mk @@ -31,10 +31,10 @@ export TEST_DIR ?= $(FLOW_HOME)/test PUBLIC=nangate45 sky130hd sky130hs asap7 ihp-sg13g2 gf180 ifeq ($(origin PLATFORM), undefined) - $(error PLATFORM variable net set.) + $(error PLATFORM variable not set.) endif ifeq ($(origin DESIGN_NAME), undefined) - $(error DESIGN_NAME variable net set.) + $(error DESIGN_NAME variable not set.) endif ifneq ($(PLATFORM_DIR),) From d5df06b030ed99319c82ebfb51899adec7e467f8 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Thu, 29 May 2025 18:39:52 -0300 Subject: [PATCH 014/198] update ihp-sg13g2 metrics Signed-off-by: Eder Monteiro --- flow/designs/ihp-sg13g2/aes/rules-base.json | 8 ++++---- flow/designs/ihp-sg13g2/gcd/rules-base.json | 2 +- .../i2c-gpio-expander/rules-base.json | 6 +++--- flow/designs/ihp-sg13g2/ibex/rules-base.json | 6 +++--- flow/designs/ihp-sg13g2/jpeg/rules-base.json | 18 +++++++++--------- .../ihp-sg13g2/riscv32i/rules-base.json | 10 +++++----- flow/designs/ihp-sg13g2/spi/rules-base.json | 4 ++-- 7 files changed, 27 insertions(+), 27 deletions(-) diff --git a/flow/designs/ihp-sg13g2/aes/rules-base.json b/flow/designs/ihp-sg13g2/aes/rules-base.json index 375f76391d..af921bedec 100644 --- a/flow/designs/ihp-sg13g2/aes/rules-base.json +++ b/flow/designs/ihp-sg13g2/aes/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 282, + "value": 0, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -40,15 +40,15 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 38, + "value": 0, "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 5, + "value": 24, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.28, + "value": -0.13, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/ihp-sg13g2/gcd/rules-base.json b/flow/designs/ihp-sg13g2/gcd/rules-base.json index 61cbba865c..bc7b71a86d 100644 --- a/flow/designs/ihp-sg13g2/gcd/rules-base.json +++ b/flow/designs/ihp-sg13g2/gcd/rules-base.json @@ -52,7 +52,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 27357, + "value": 27303, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json index d5d48973d5..f99d92ecec 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 22, + "value": 0, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -40,7 +40,7 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 1, + "value": 0, "compare": "<=" }, "detailedroute__antenna_diodes_count": { @@ -52,7 +52,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 44306, + "value": 44275, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { diff --git a/flow/designs/ihp-sg13g2/ibex/rules-base.json b/flow/designs/ihp-sg13g2/ibex/rules-base.json index 5aa0254e32..c4c1270db1 100644 --- a/flow/designs/ihp-sg13g2/ibex/rules-base.json +++ b/flow/designs/ihp-sg13g2/ibex/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 1178, + "value": 12, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -40,11 +40,11 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 55, + "value": 0, "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 5, + "value": 26, "compare": "<=" }, "finish__timing__setup__ws": { diff --git a/flow/designs/ihp-sg13g2/jpeg/rules-base.json b/flow/designs/ihp-sg13g2/jpeg/rules-base.json index 8ce13b60b2..bf2a834c15 100644 --- a/flow/designs/ihp-sg13g2/jpeg/rules-base.json +++ b/flow/designs/ihp-sg13g2/jpeg/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 1512439.93, + "value": 1507968.61, "compare": "<=" }, "constraints__clocks__count": { @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 88060, + "value": 87671, "compare": "<=" }, "detailedplace__design__violations": { @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 1714, + "value": 27, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -40,23 +40,23 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 110, + "value": 0, "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 5, + "value": 160, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -2.18, + "value": 0.0, "compare": ">=" }, "finish__design__instance__area": { - "value": 2610834, + "value": 2605152, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 3829, + "value": 3812, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -30.54, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/riscv32i/rules-base.json b/flow/designs/ihp-sg13g2/riscv32i/rules-base.json index 90b3c7852c..d782c9d2ef 100644 --- a/flow/designs/ihp-sg13g2/riscv32i/rules-base.json +++ b/flow/designs/ihp-sg13g2/riscv32i/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 362, + "value": 4, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -40,15 +40,15 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 20, + "value": 0, "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 5, + "value": 33, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.65, + "value": -0.4, "compare": ">=" }, "finish__design__instance__area": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -18.36, + "value": -12.48, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/spi/rules-base.json b/flow/designs/ihp-sg13g2/spi/rules-base.json index d51052ebb0..9650412b04 100644 --- a/flow/designs/ihp-sg13g2/spi/rules-base.json +++ b/flow/designs/ihp-sg13g2/spi/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.3, + "value": -0.25, "compare": ">=" }, "finish__design__instance__area": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 20, + "value": 17, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { From eb61a27899678e2129ea0c82733f01536b8c1e37 Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Fri, 30 May 2025 16:53:07 -0700 Subject: [PATCH 015/198] added desired grouping for demo - hier synthesis Signed-off-by: Jeff Ng --- flow/designs/asap7/cva6/config.mk | 3 +++ 1 file changed, 3 insertions(+) diff --git a/flow/designs/asap7/cva6/config.mk b/flow/designs/asap7/cva6/config.mk index 31a7366678..f22d8f8005 100644 --- a/flow/designs/asap7/cva6/config.mk +++ b/flow/designs/asap7/cva6/config.mk @@ -88,5 +88,8 @@ export MACRO_HALO = 5 5 # few last gasp iterations export SKIP_LAST_GASP ?= 1 +ifeq ($(SYNTH_HIERARCHICAL),1) + export SYNTH_MINIMUM_KEEP_SIZE ?= 40000 +endif export SYNTH_HDL_FRONTEND = slang From b6ed9354981c2f282743e0bf5dcda891a81bde56 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 4 Jun 2025 16:58:27 +0200 Subject: [PATCH 016/198] util: Take via resistances for fixed in RC correlation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit OR has single per-layer via resistance setting (`set_layer_rc -via`) which applies to both estimation and final parasitics extraction. Given this the via resistances must enter the RC fit as constants, not variables. Signed-off-by: Martin Povišer --- flow/util/correlateRC.py | 73 +++++++++++++++++++++----------------- flow/util/write_net_rc.tcl | 7 ++++ 2 files changed, 48 insertions(+), 32 deletions(-) diff --git a/flow/util/correlateRC.py b/flow/util/correlateRC.py index 9af693563d..7426e84b1b 100755 --- a/flow/util/correlateRC.py +++ b/flow/util/correlateRC.py @@ -16,6 +16,8 @@ from sklearn.linear_model import LinearRegression import matplotlib.pyplot as plt +LAYER_HEADER_RE = re.compile("^([^\\(]+)\\(([^\\)]+)\\)$") + # Parse and validate arguments # ============================================================================= @@ -101,9 +103,19 @@ def makeDict(): exit(1) elif stack_line is None: for layer in line.removeprefix("# stack: ").strip().split(" "): - name = layer.removesuffix("(routing)") - is_routing = layer.endswith("(routing)") - stack.append((name, is_routing)) + name = layer + is_routing = False + via_resist = 0.0 + if layer.endswith(")"): + # layer name has extra data + match = LAYER_HEADER_RE.match(layer) + assert match + name = match.group(1) + if match.group(2) == "routing": + is_routing = True + else: + via_resist = float(match.group(2)) + stack.append((name, is_routing, via_resist)) continue tokens = line.strip().split(",") @@ -125,12 +137,23 @@ def makeDict(): active_layers.add(i) data[design][netName]["layer_lengths"] = layer_lengths + data[design][netName]["routable_layer_lengths"] = [ + length + for i, length in enumerate(layer_lengths) + # ignore non-routable layers + if stack[i][1] + ] data[design][netName]["wire_length"] = sum( length for i, length in enumerate(layer_lengths) - # ignore contribution from via layers + # ignore non-routable layers if stack[i][1] ) + data[design][netName]["grt_via_res"] = sum( + (length * stack[i][2]) + for i, length in enumerate(layer_lengths) + if not stack[i][1] + ) ################################################################ @@ -227,15 +250,15 @@ def makeDict(): for net in data[design]: rcx_res = data[design][net]["rcx_res"] if rcx_res > 0: - x.append(data[design][net]["layer_lengths"]) - y.append(rcx_res) + x.append(data[design][net]["routable_layer_lengths"]) + y.append(rcx_res - data[design][net]["grt_via_res"]) x = np.array(x) y = np.array(y) res_model = LinearRegression(fit_intercept=False).fit(x, y) r_sq = res_model.score(x, y) -print("Resistance coefficient of determination: {:.4f}".format(r_sq)) +print("# Resistance coefficient of determination: {:.4f}".format(r_sq)) ################################################################ @@ -245,8 +268,7 @@ def makeDict(): y = [] for design in data: for net in data[design]: - lengths = data[design][net]["layer_lengths"] - x.append([length for length, layer in zip(lengths, stack) if layer[1]]) + x.append(data[design][net]["routable_layer_lengths"]) y.append(data[design][net]["rcx_cap"]) x = np.array(x) @@ -254,30 +276,17 @@ def makeDict(): cap_model = LinearRegression(fit_intercept=False).fit(x, y) r_sq = cap_model.score(x, y) -print("Capacitance coefficient of determination: {:.4f}".format(r_sq)) - -print("Updated layer resistance {}/um capacitance {}/um".format(res_unit, cap_unit)) -routable_layer_no = 0 -for i, layer, res_coeff in zip(range(len(stack)), stack, res_model.coef_): - if not layer[1] or i not in active_layers: - # skip non-routable and non-active layers - continue - cap_coeff = cap_model.coef_[routable_layer_no] - print( - "set_layer_rc -layer {} -resistance {:.5E} -capacitance {:.5E}".format( - layer[0], res_coeff / res_scale, cap_coeff / cap_scale - ) - ) - routable_layer_no += 1 - -for i, layer, res_coeff in zip(range(len(stack)), stack, res_model.coef_): - if layer[1] or i not in active_layers: - # skip routable and non-active layers - continue - if res_coeff != 0.0: +print("# Capacitance coefficient of determination: {:.4f}".format(r_sq)) +print("# Updated layer resistance {}/um capacitance {}/um".format(res_unit, cap_unit)) + +routable_layers = [layer for layer in stack if layer[1]] +for i, layer in enumerate(routable_layers): + res_coeff = res_model.coef_[i] + cap_coeff = cap_model.coef_[i] + if res_coeff != 0.0 or cap_coeff != 0.0: print( - "set_layer_rc -via {} -resistance {:.5E}".format( - layer[0], res_coeff / res_scale + "set_layer_rc -layer {} -resistance {:.5E} -capacitance {:.5E}".format( + layer[0], res_coeff / res_scale, cap_coeff / cap_scale ) ) diff --git a/flow/util/write_net_rc.tcl b/flow/util/write_net_rc.tcl index 75f91af3fa..9e5dd99b58 100644 --- a/flow/util/write_net_rc.tcl +++ b/flow/util/write_net_rc.tcl @@ -44,9 +44,16 @@ proc write_rc_csv { filename } { foreach layer [[ord::get_db_tech] getLayers] { set routing [expr [$layer getRoutingLevel] != 0] set is_routing([$layer getNumber]) $routing + set is_routing([$layer getNumber]) $routing puts -nonewline $stream " [$layer getName]" if $routing { puts -nonewline $stream "(routing)" + } else { + # insert via resistance information + set via_resist [$layer getResistance] + if { $via_resist != 0.0 } { + puts -nonewline $stream "([format %.4e $via_resist])" + } } } puts $stream "" From 071bf4fa857794fbbf77b7be4104ebabf8c5f05a Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Wed, 4 Jun 2025 14:52:57 -0300 Subject: [PATCH 017/198] use latest openroad Signed-off-by: Eder Monteiro --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index d51df1dea5..66559c8bcf 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit d51df1dea57f1bc70b25f46fef5ce7c396d26e99 +Subproject commit 66559c8bcf6782e2f68ccf4a01a80ee8cc8c499e From 8b94bfb91873ac26cfeb100ea4015729fdd4e733 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 4 Jun 2025 21:56:12 +0200 Subject: [PATCH 018/198] util: Fix repeated header handling in csv read-in MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- flow/util/correlateRC.py | 1 + 1 file changed, 1 insertion(+) diff --git a/flow/util/correlateRC.py b/flow/util/correlateRC.py index 7426e84b1b..410f8e3144 100755 --- a/flow/util/correlateRC.py +++ b/flow/util/correlateRC.py @@ -116,6 +116,7 @@ def makeDict(): else: via_resist = float(match.group(2)) stack.append((name, is_routing, via_resist)) + stack_line = line continue tokens = line.strip().split(",") From a3ea4d0a4c10cb65a5314ed541dfc1bc42979f8d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 4 Jun 2025 21:53:58 +0200 Subject: [PATCH 019/198] asap7, ihp-sg13g2: Insert fresh RC fit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Log from asap7 fit: $ util/correlateRC.py -cap_unit ff results/asap7/*/base/6_net_rc.csv reading results/asap7/aes/base/6_net_rc.csv reading results/asap7/cva6/base/6_net_rc.csv reading results/asap7/ibex/base/6_net_rc.csv reading results/asap7/riscv32i/base/6_net_rc.csv # Resistance coefficient of determination: 0.9736 # Capacitance coefficient of determination: 0.9632 # Updated layer resistance kohm/um capacitance ff/um set_layer_rc -layer M1 -resistance 7.04175E-02 -capacitance -4.85208E-02 set_layer_rc -layer M2 -resistance 4.62311E-02 -capacitance 1.84542E-01 set_layer_rc -layer M3 -resistance 3.63251E-02 -capacitance 1.53955E-01 set_layer_rc -layer M4 -resistance 2.03083E-02 -capacitance 1.89434E-01 set_layer_rc -layer M5 -resistance 1.93005E-02 -capacitance 1.71593E-01 set_layer_rc -layer M6 -resistance 1.18619E-02 -capacitance 1.76146E-01 set_layer_rc -layer M7 -resistance 1.25311E-02 -capacitance 1.47030E-01 # Combined fit: set_wire_rc -resistance 3.26320E-02 -capacitance 1.72845E-01 # Split signal/clock fit: set_wire_rc -signal -resistance 3.23151E-02 -capacitance 1.73323E-01 set_wire_rc -clock -resistance 5.13971E-02 -capacitance 1.44549E-01 Log from ihp-sg13g2 fit: $ util/correlateRC.py results/ihp-sg13g2/*/base/6_net_rc.csv reading results/ihp-sg13g2/aes/base/6_net_rc.csv reading results/ihp-sg13g2/gcd/base/6_net_rc.csv reading results/ihp-sg13g2/ibex/base/6_net_rc.csv reading results/ihp-sg13g2/riscv32i/base/6_net_rc.csv reading results/ihp-sg13g2/spi/base/6_net_rc.csv # Resistance coefficient of determination: 0.7364 # Capacitance coefficient of determination: 0.9689 # Updated layer resistance kohm/um capacitance pf/um set_layer_rc -layer Metal1 -resistance 8.54576E-03 -capacitance -1.05290E-05 set_layer_rc -layer Metal2 -resistance 2.53519E-03 -capacitance 1.69121E-04 set_layer_rc -layer Metal3 -resistance 1.54329E-03 -capacitance 1.82832E-04 set_layer_rc -layer Metal4 -resistance 6.31424E-04 -capacitance 1.66454E-04 set_layer_rc -layer Metal5 -resistance 6.84051E-04 -capacitance 8.57431E-05 # Combined fit: set_wire_rc -resistance 2.08008E-03 -capacitance 1.72560E-04 # Split signal/clock fit: set_wire_rc -signal -resistance 2.07259E-03 -capacitance 1.73072E-04 set_wire_rc -clock -resistance 2.48603E-03 -capacitance 1.44812E-04 Signed-off-by: Martin Povišer --- flow/platforms/asap7/setRC.tcl | 23 +++++++++++------------ flow/platforms/ihp-sg13g2/setRC.tcl | 22 +++++++++------------- 2 files changed, 20 insertions(+), 25 deletions(-) diff --git a/flow/platforms/asap7/setRC.tcl b/flow/platforms/asap7/setRC.tcl index 2a741ef815..d1d988b362 100644 --- a/flow/platforms/asap7/setRC.tcl +++ b/flow/platforms/asap7/setRC.tcl @@ -1,13 +1,14 @@ -# Liberty units are fF,kOhm -set_layer_rc -layer M1 -capacitance 1.1368e-01 -resistance 1.3889e-01 -set_layer_rc -layer M2 -capacitance 1.3426e-01 -resistance 2.4222e-02 -set_layer_rc -layer M3 -capacitance 1.2918e-01 -resistance 2.4222e-02 -set_layer_rc -layer M4 -capacitance 1.1396e-01 -resistance 1.6778e-02 -set_layer_rc -layer M5 -capacitance 1.3323e-01 -resistance 1.4677e-02 -set_layer_rc -layer M6 -capacitance 1.1575e-01 -resistance 1.0371e-02 -set_layer_rc -layer M7 -capacitance 1.3293e-01 -resistance 9.6720e-03 -set_layer_rc -layer M8 -capacitance 1.1822e-01 -resistance 7.4310e-03 -set_layer_rc -layer M9 -capacitance 1.3497e-01 -resistance 6.8740e-03 +# correlation result (aes, cva6, ibex, riscv32i) +# M1 capacitance fixed up from -4.8e-02 to 1e-10 as a minuscule positive value +set_layer_rc -layer M1 -resistance 7.04175E-02 -capacitance 1e-10 +set_layer_rc -layer M2 -resistance 4.62311E-02 -capacitance 1.84542E-01 +set_layer_rc -layer M3 -resistance 3.63251E-02 -capacitance 1.53955E-01 +set_layer_rc -layer M4 -resistance 2.03083E-02 -capacitance 1.89434E-01 +set_layer_rc -layer M5 -resistance 1.93005E-02 -capacitance 1.71593E-01 +set_layer_rc -layer M6 -resistance 1.18619E-02 -capacitance 1.76146E-01 +set_layer_rc -layer M7 -resistance 1.25311E-02 -capacitance 1.47030E-01 +set_wire_rc -signal -resistance 3.23151E-02 -capacitance 1.73323E-01 +set_wire_rc -clock -resistance 5.13971E-02 -capacitance 1.44549E-01 set_layer_rc -via V1 -resistance 1.72E-02 set_layer_rc -via V2 -resistance 1.72E-02 @@ -17,5 +18,3 @@ set_layer_rc -via V5 -resistance 1.18E-02 set_layer_rc -via V6 -resistance 8.20E-03 set_layer_rc -via V7 -resistance 8.20E-03 set_layer_rc -via V8 -resistance 6.30E-03 - -set_wire_rc -layer M3 diff --git a/flow/platforms/ihp-sg13g2/setRC.tcl b/flow/platforms/ihp-sg13g2/setRC.tcl index ee17153aee..65ea6cc833 100644 --- a/flow/platforms/ihp-sg13g2/setRC.tcl +++ b/flow/platforms/ihp-sg13g2/setRC.tcl @@ -1,13 +1,12 @@ -# correlateRC.py gcd,ibex,aes,jpeg,chameleon,riscv32i,chameleon_hier -# cap units pf/um -set_layer_rc -layer Metal1 -capacitance 3.49E-05 -resistance 0.135e-03 -set_layer_rc -layer Metal2 -capacitance 1.81E-05 -resistance 0.103e-03 -set_layer_rc -layer Metal3 -capacitance 2.14962E-04 -resistance 0.103e-03 -set_layer_rc -layer Metal4 -capacitance 1.48128E-04 -resistance 0.103e-03 -set_layer_rc -layer Metal5 -capacitance 1.54087E-04 -resistance 0.103e-03 -set_layer_rc -layer TopMetal1 -capacitance 1.54087E-04 -resistance 0.021e-03 -set_layer_rc -layer TopMetal2 -capacitance 1.54087E-04 -resistance 0.0145e-03 -# end correlate +# correlation result (aes, gcd, ibex, riscv32i, spi) +# Metal1 capacitance fixed up from -1.1e-05 to 1e-10 as a minuscule positive value +set_layer_rc -layer Metal1 -resistance 8.54576E-03 -capacitance 1e-10 +set_layer_rc -layer Metal2 -resistance 2.53519E-03 -capacitance 1.69121E-04 +set_layer_rc -layer Metal3 -resistance 1.54329E-03 -capacitance 1.82832E-04 +set_layer_rc -layer Metal4 -resistance 6.31424E-04 -capacitance 1.66454E-04 +set_layer_rc -layer Metal5 -resistance 6.84051E-04 -capacitance 8.57431E-05 +set_wire_rc -signal -resistance 2.07259E-03 -capacitance 1.73072E-04 +set_wire_rc -clock -resistance 2.48603E-03 -capacitance 1.44812E-04 set_layer_rc -via Via1 -resistance 2.0E-3 set_layer_rc -via Via2 -resistance 2.0E-3 @@ -15,6 +14,3 @@ set_layer_rc -via Via3 -resistance 2.0E-3 set_layer_rc -via Via4 -resistance 2.0E-3 set_layer_rc -via TopVia1 -resistance 0.4E-3 set_layer_rc -via TopVia2 -resistance 0.22E-3 - -set_wire_rc -signal -layer Metal2 -set_wire_rc -clock -layer Metal5 From 588311278e585b44d9b31652646cdafc3dd6625a Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Wed, 4 Jun 2025 18:48:01 -0300 Subject: [PATCH 020/198] update n45/gcd metrics Signed-off-by: Eder Monteiro --- flow/designs/nangate45/gcd/rules-base.json | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/flow/designs/nangate45/gcd/rules-base.json b/flow/designs/nangate45/gcd/rules-base.json index 8e797c1842..94f99b2fc3 100644 --- a/flow/designs/nangate45/gcd/rules-base.json +++ b/flow/designs/nangate45/gcd/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 5558, + "value": 6853, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,11 +48,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.07, + "value": -0.09, "compare": ">=" }, "finish__design__instance__area": { - "value": 909, + "value": 1069, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { From 7e92a3e6020f44eb3b32f35be9ffeec68d67eeb6 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Wed, 4 Jun 2025 21:25:22 -0300 Subject: [PATCH 021/198] update metrics for remaining designs Signed-off-by: Eder Monteiro --- flow/designs/nangate45/aes/rules-base.json | 4 ++-- flow/designs/nangate45/ariane133/rules-base.json | 2 +- flow/designs/nangate45/ariane136/rules-base.json | 2 +- .../designs/nangate45/black_parrot/rules-base.json | 14 +++++++------- flow/designs/nangate45/bp_be_top/rules-base.json | 4 ++-- flow/designs/nangate45/bp_fe_top/rules-base.json | 2 +- .../designs/nangate45/bp_multi_top/rules-base.json | 6 +++--- .../designs/nangate45/dynamic_node/rules-base.json | 14 +++++++------- flow/designs/nangate45/ibex/rules-base.json | 6 +++--- flow/designs/nangate45/jpeg/rules-base.json | 2 +- flow/designs/nangate45/swerv/rules-base.json | 2 +- .../nangate45/swerv_wrapper/rules-base.json | 4 ++-- flow/designs/nangate45/tinyRocket/rules-base.json | 4 ++-- flow/designs/sky130hs/aes/rules-base.json | 8 ++++---- flow/designs/sky130hs/jpeg/rules-base.json | 10 +++++----- flow/designs/sky130hs/riscv32i/rules-base.json | 8 ++++---- 16 files changed, 46 insertions(+), 46 deletions(-) diff --git a/flow/designs/nangate45/aes/rules-base.json b/flow/designs/nangate45/aes/rules-base.json index 2c0aede758..a927b19b33 100644 --- a/flow/designs/nangate45/aes/rules-base.json +++ b/flow/designs/nangate45/aes/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.14, + "value": -0.11, "compare": ">=" }, "finish__design__instance__area": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -21.31, + "value": -18.58, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/ariane133/rules-base.json b/flow/designs/nangate45/ariane133/rules-base.json index 199ee80fd2..4c7ede902a 100644 --- a/flow/designs/nangate45/ariane133/rules-base.json +++ b/flow/designs/nangate45/ariane133/rules-base.json @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -11.66, + "value": -11.6, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/ariane136/rules-base.json b/flow/designs/nangate45/ariane136/rules-base.json index d01b224f5d..15c6bdf6f2 100644 --- a/flow/designs/nangate45/ariane136/rules-base.json +++ b/flow/designs/nangate45/ariane136/rules-base.json @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 509, + "value": 178, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/nangate45/black_parrot/rules-base.json b/flow/designs/nangate45/black_parrot/rules-base.json index 6a7a83aedf..525c71aac8 100644 --- a/flow/designs/nangate45/black_parrot/rules-base.json +++ b/flow/designs/nangate45/black_parrot/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 778508.16, + "value": 778458.91, "compare": "<=" }, "constraints__clocks__count": { @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 299688, + "value": 299499, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 26060, + "value": 26043, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 26060, + "value": 26043, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 10420028, + "value": 8591633, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -56,11 +56,11 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 13030, + "value": 13022, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 429, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/nangate45/bp_be_top/rules-base.json b/flow/designs/nangate45/bp_be_top/rules-base.json index 7db8d96863..f69d95f09a 100644 --- a/flow/designs/nangate45/bp_be_top/rules-base.json +++ b/flow/designs/nangate45/bp_be_top/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.76, + "value": -0.51, "compare": ">=" }, "finish__design__instance__area": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -33.25, + "value": -29.19, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/bp_fe_top/rules-base.json b/flow/designs/nangate45/bp_fe_top/rules-base.json index fbafe3b3c2..aff5af09fd 100644 --- a/flow/designs/nangate45/bp_fe_top/rules-base.json +++ b/flow/designs/nangate45/bp_fe_top/rules-base.json @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 1931, + "value": 860, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/nangate45/bp_multi_top/rules-base.json b/flow/designs/nangate45/bp_multi_top/rules-base.json index 4db33fb5f6..0d705fc6c7 100644 --- a/flow/designs/nangate45/bp_multi_top/rules-base.json +++ b/flow/designs/nangate45/bp_multi_top/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 4890576, + "value": 4806328, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -4.36, + "value": -4.29, "compare": ">=" }, "finish__design__instance__area": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 1026, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/nangate45/dynamic_node/rules-base.json b/flow/designs/nangate45/dynamic_node/rules-base.json index 186181dc5f..bf896023ad 100644 --- a/flow/designs/nangate45/dynamic_node/rules-base.json +++ b/flow/designs/nangate45/dynamic_node/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 25608.42, + "value": 25515.12, "compare": "<=" }, "constraints__clocks__count": { @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 13598, + "value": 13523, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1182, + "value": 1176, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1182, + "value": 1176, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.51, + "value": -0.49, "compare": ">=" }, "finish__design__instance__area": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 591, + "value": 588, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -33.08, + "value": -31.32, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/ibex/rules-base.json b/flow/designs/nangate45/ibex/rules-base.json index 00e8486948..6a0b8c87f1 100644 --- a/flow/designs/nangate45/ibex/rules-base.json +++ b/flow/designs/nangate45/ibex/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.26, + "value": -0.19, "compare": ">=" }, "finish__design__instance__area": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 832, + "value": 825, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -18.58, + "value": -15.31, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/jpeg/rules-base.json b/flow/designs/nangate45/jpeg/rules-base.json index 78373adb41..4f11d20d1f 100644 --- a/flow/designs/nangate45/jpeg/rules-base.json +++ b/flow/designs/nangate45/jpeg/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 103107.27, + "value": 103045.48, "compare": "<=" }, "constraints__clocks__count": { diff --git a/flow/designs/nangate45/swerv/rules-base.json b/flow/designs/nangate45/swerv/rules-base.json index c209812067..4f5b5a19c9 100644 --- a/flow/designs/nangate45/swerv/rules-base.json +++ b/flow/designs/nangate45/swerv/rules-base.json @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 408, + "value": 185, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/nangate45/swerv_wrapper/rules-base.json b/flow/designs/nangate45/swerv_wrapper/rules-base.json index f11829c516..885af20f86 100644 --- a/flow/designs/nangate45/swerv_wrapper/rules-base.json +++ b/flow/designs/nangate45/swerv_wrapper/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 5922536, + "value": 5508164, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.63, + "value": -0.52, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/nangate45/tinyRocket/rules-base.json b/flow/designs/nangate45/tinyRocket/rules-base.json index e0e394095c..480d0b66c4 100644 --- a/flow/designs/nangate45/tinyRocket/rules-base.json +++ b/flow/designs/nangate45/tinyRocket/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.31, + "value": -0.21, "compare": ">=" }, "finish__design__instance__area": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -27.52, + "value": -20.85, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/sky130hs/aes/rules-base.json b/flow/designs/sky130hs/aes/rules-base.json index e6c5b80408..2155ca377d 100644 --- a/flow/designs/sky130hs/aes/rules-base.json +++ b/flow/designs/sky130hs/aes/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 177040, + "value": 176428, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 53, + "value": 9, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -44,11 +44,11 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 45, + "value": 24, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.47, + "value": -0.18, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/sky130hs/jpeg/rules-base.json b/flow/designs/sky130hs/jpeg/rules-base.json index ac0c8a220e..ce7d4fa25d 100644 --- a/flow/designs/sky130hs/jpeg/rules-base.json +++ b/flow/designs/sky130hs/jpeg/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 654669.88, + "value": 653350.08, "compare": "<=" }, "constraints__clocks__count": { @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 750737, + "value": 749317, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 910, + "value": 712, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -40,11 +40,11 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 3, + "value": 1, "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 810, + "value": 699, "compare": "<=" }, "finish__timing__setup__ws": { diff --git a/flow/designs/sky130hs/riscv32i/rules-base.json b/flow/designs/sky130hs/riscv32i/rules-base.json index da811f9399..c5fe338cb5 100644 --- a/flow/designs/sky130hs/riscv32i/rules-base.json +++ b/flow/designs/sky130hs/riscv32i/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 411975, + "value": 378010, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,15 +44,15 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 12, + "value": 9, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.32, + "value": -0.21, "compare": ">=" }, "finish__design__instance__area": { - "value": 149394, + "value": 141659, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { From 17392c13295116cac8ed30e6987bf4cf3103e6e4 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Tue, 27 May 2025 22:00:08 +0200 Subject: [PATCH 022/198] flow: Makefile: Don't export GDS_FILES Do not export GDS_FILES with GDS files for macro blocks. This variable should be set in the platform specific config.mk file via ADDITIONAL_GDS_FILES, which has the additional macro GDS files included. Signed-off-by: Daniel Schultz --- flow/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/flow/Makefile b/flow/Makefile index ff85238846..5d6bddb902 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -105,7 +105,6 @@ ifneq ($(BLOCKS),) export ADDITIONAL_LEFS += $(BLOCK_LEFS) export ADDITIONAL_LIBS += $(BLOCK_LIBS) export ADDITIONAL_GDS += $(BLOCK_GDS) - export GDS_FILES += $(BLOCK_GDS) ifneq ($(CDL_FILES),) export CDL_FILES += $(BLOCK_CDL) endif From 0f8a38a7fceccb7efde76ca05cf17a3221c954bd Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Tue, 27 May 2025 22:04:45 +0200 Subject: [PATCH 023/198] flow: Makefile Use WORK_HOME Use WORK_HOME instead of relative paths to result, logs, reports and objects. Signed-off-by: Daniel Schultz --- flow/Makefile | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/flow/Makefile b/flow/Makefile index 5d6bddb902..15334a6ce5 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -97,11 +97,11 @@ export FLOW_VARIANT?=base ifneq ($(BLOCKS),) # Normally this comes from variables.yaml, but we need it here to set up these variables # which are part of the DESIGN_CONFIG. BLOCKS is a Makefile specific concept. - $(foreach block,$(BLOCKS),$(eval BLOCK_LEFS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef)) - $(foreach block,$(BLOCKS),$(eval BLOCK_LIBS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lib)) - $(foreach block,$(BLOCKS),$(eval BLOCK_GDS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds)) - $(foreach block,$(BLOCKS),$(eval BLOCK_CDL += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.cdl)) - $(foreach block,$(BLOCKS),$(eval BLOCK_LOG_FOLDERS += ./logs/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/)) + $(foreach block,$(BLOCKS),$(eval BLOCK_LEFS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef)) + $(foreach block,$(BLOCKS),$(eval BLOCK_LIBS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lib)) + $(foreach block,$(BLOCKS),$(eval BLOCK_GDS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds)) + $(foreach block,$(BLOCKS),$(eval BLOCK_CDL += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.cdl)) + $(foreach block,$(BLOCKS),$(eval BLOCK_LOG_FOLDERS += $(WORK_HOME)/logs/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/)) export ADDITIONAL_LEFS += $(BLOCK_LEFS) export ADDITIONAL_LIBS += $(BLOCK_LIBS) export ADDITIONAL_GDS += $(BLOCK_GDS) @@ -169,8 +169,8 @@ endef .PHONY: build_macros build_macros: $(BLOCK_LEFS) $(BLOCK_LIBS) -$(foreach block,$(BLOCKS),$(eval $(call GENERATE_ABSTRACT_RULE,./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef,./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lib,$(shell dirname $(DESIGN_CONFIG))/${block}/config.mk))) -$(foreach block,$(BLOCKS),$(eval ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds: ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef)) +$(foreach block,$(BLOCKS),$(eval $(call GENERATE_ABSTRACT_RULE,$(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef,$(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lib,$(shell dirname $(DESIGN_CONFIG))/${block}/config.mk))) +$(foreach block,$(BLOCKS),$(eval $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds: $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef)) # Utility to print tool version information #------------------------------------------------------------------------------- @@ -764,7 +764,7 @@ clean_all: clean_synth clean_floorplan clean_place clean_cts clean_route clean_f .PHONY: nuke nuke: clean_test clean_issues - rm -rf ./results ./logs ./reports ./objects + rm -rf $(WORK_HOME)/results $(WORK_HOME)/logs $(WORK_HOME)/reports $(WORK_HOME)/objects rm -rf layer_*.mps macrocell.list *best.plt *_pdn.def rm -rf *.rpt *.rpt.old *.def.v pin_dumper.log rm -f $(OBJECTS_DIR)/versions.txt $(OBJECTS_DIR)/copyright.txt dummy.guide From 503efecff7aafbb57076c7be6fcc5cfe4099c84a Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Tue, 27 May 2025 22:08:29 +0200 Subject: [PATCH 024/198] flow: Makefile: Add slow, typ, fast libs for BLOCKS Also provide ADDITIONAL_LIB variables for SLOW and FAST corners to allow generating blocks with Multi Corner analysis enabled. Add an additional ADDITIONAL_TYP_LIB variable as default for typical timings. Typical timings is required to generate a lib file for Yosys to replace the actual Verilog module. Signed-off-by: Daniel Schultz --- flow/Makefile | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/flow/Makefile b/flow/Makefile index 15334a6ce5..335d3a87f3 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -98,12 +98,17 @@ ifneq ($(BLOCKS),) # Normally this comes from variables.yaml, but we need it here to set up these variables # which are part of the DESIGN_CONFIG. BLOCKS is a Makefile specific concept. $(foreach block,$(BLOCKS),$(eval BLOCK_LEFS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef)) - $(foreach block,$(BLOCKS),$(eval BLOCK_LIBS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lib)) + $(foreach block,$(BLOCKS),$(eval BLOCK_TYP_LIBS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_typ.lib)) + $(foreach block,$(BLOCKS),$(eval BLOCK_FAST_LIBS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_fast.lib)) + $(foreach block,$(BLOCKS),$(eval BLOCK_SLOW_LIBS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_slow.lib)) $(foreach block,$(BLOCKS),$(eval BLOCK_GDS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds)) $(foreach block,$(BLOCKS),$(eval BLOCK_CDL += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.cdl)) $(foreach block,$(BLOCKS),$(eval BLOCK_LOG_FOLDERS += $(WORK_HOME)/logs/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/)) export ADDITIONAL_LEFS += $(BLOCK_LEFS) - export ADDITIONAL_LIBS += $(BLOCK_LIBS) + export ADDITIONAL_LIBS += $(BLOCK_TYP_LIBS) + export ADDITIONAL_TYP_LIBS += $(BLOCK_TYP_LIBS) + export ADDITIONAL_FAST_LIBS += $(BLOCK_FAST_LIBS) + export ADDITIONAL_SLOW_LIBS += $(BLOCK_SLOW_LIBS) export ADDITIONAL_GDS += $(BLOCK_GDS) ifneq ($(CDL_FILES),) export CDL_FILES += $(BLOCK_CDL) @@ -167,9 +172,9 @@ endef # Targets to harden Blocks in case of hierarchical flow is triggered .PHONY: build_macros -build_macros: $(BLOCK_LEFS) $(BLOCK_LIBS) +build_macros: $(BLOCK_LEFS) $(BLOCK_TYP_LIBS) -$(foreach block,$(BLOCKS),$(eval $(call GENERATE_ABSTRACT_RULE,$(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef,$(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lib,$(shell dirname $(DESIGN_CONFIG))/${block}/config.mk))) +$(foreach block,$(BLOCKS),$(eval $(call GENERATE_ABSTRACT_RULE,$(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef,$(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_typ.lib,$(shell dirname $(DESIGN_CONFIG))/${block}/config.mk))) $(foreach block,$(BLOCKS),$(eval $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds: $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef)) # Utility to print tool version information From 9c59cec622217be83a92f1a15cfea4415f65f76d Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Tue, 27 May 2025 21:59:02 +0200 Subject: [PATCH 025/198] flow: scripts: generate_abstract: Generate libs with timing corners Also generate all .lib files when timing corners are enabled in a design. Signed-off-by: Daniel Schultz --- flow/scripts/generate_abstract.tcl | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/flow/scripts/generate_abstract.tcl b/flow/scripts/generate_abstract.tcl index 32364a3e4d..8ba73b46f5 100644 --- a/flow/scripts/generate_abstract.tcl +++ b/flow/scripts/generate_abstract.tcl @@ -21,7 +21,15 @@ if {$design_stage >= 4} { # write_timing_model includes the source latency in the model set_clock_latency -source 0 [all_clocks] puts "Generating abstract views" -log_cmd write_timing_model $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lib +if {[env_var_exists_and_non_empty CORNERS]} { + # corners + foreach corner $::env(CORNERS) { + log_cmd write_timing_model -corner $corner $::env(RESULTS_DIR)/$::env(DESIGN_NAME)_$corner.lib + } + unset corner +} else { + log_cmd write_timing_model $::env(RESULTS_DIR)/$::env(DESIGN_NAME)_typ.lib +} log_cmd write_abstract_lef -bloat_occupied_layers $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lef if {[env_var_exists_and_non_empty CDL_FILES]} { From c7135aff689c3c2663e57c95b055416620a8531b Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" Date: Thu, 5 Jun 2025 18:03:14 +0000 Subject: [PATCH 026/198] flow: update rules Signed-off-by: github-actions[bot] --- flow/designs/asap7/riscv32i-mock-sram/rules-base.json | 2 +- flow/designs/ihp-sg13g2/aes/rules-base.json | 4 ++-- flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json | 4 ++-- flow/designs/ihp-sg13g2/ibex/rules-base.json | 2 +- flow/designs/ihp-sg13g2/spi/rules-base.json | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/flow/designs/asap7/riscv32i-mock-sram/rules-base.json b/flow/designs/asap7/riscv32i-mock-sram/rules-base.json index 9318031c71..0c8bd5dfeb 100644 --- a/flow/designs/asap7/riscv32i-mock-sram/rules-base.json +++ b/flow/designs/asap7/riscv32i-mock-sram/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2269, + "value": 2616, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { diff --git a/flow/designs/ihp-sg13g2/aes/rules-base.json b/flow/designs/ihp-sg13g2/aes/rules-base.json index af921bedec..ce2965075c 100644 --- a/flow/designs/ihp-sg13g2/aes/rules-base.json +++ b/flow/designs/ihp-sg13g2/aes/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 210460, + "value": 253595, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 0, + "value": 3, "compare": "<=" }, "detailedroute__route__wirelength": { diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json index f99d92ecec..e3879ba092 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 0, + "value": 2, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 49751, + "value": 60953, "compare": "<=" }, "detailedroute__route__drc_errors": { diff --git a/flow/designs/ihp-sg13g2/ibex/rules-base.json b/flow/designs/ihp-sg13g2/ibex/rules-base.json index c4c1270db1..9c1509e822 100644 --- a/flow/designs/ihp-sg13g2/ibex/rules-base.json +++ b/flow/designs/ihp-sg13g2/ibex/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 305593, + "value": 371258, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { diff --git a/flow/designs/ihp-sg13g2/spi/rules-base.json b/flow/designs/ihp-sg13g2/spi/rules-base.json index 9650412b04..cd53421bf4 100644 --- a/flow/designs/ihp-sg13g2/spi/rules-base.json +++ b/flow/designs/ihp-sg13g2/spi/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 4391, + "value": 5088, "compare": "<=" }, "detailedroute__route__drc_errors": { From 08e25d93804ba008864d12b2b1e224c7a5488537 Mon Sep 17 00:00:00 2001 From: Vitor Bandeira Date: Thu, 5 Jun 2025 18:17:27 +0000 Subject: [PATCH 027/198] util: only print message on updates Signed-off-by: Vitor Bandeira --- flow/util/genRuleFile.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/flow/util/genRuleFile.py b/flow/util/genRuleFile.py index 99866137f1..9162015ac4 100755 --- a/flow/util/genRuleFile.py +++ b/flow/util/genRuleFile.py @@ -21,8 +21,6 @@ def gen_rule_file( metrics_file=None, metrics_to_consider=[], ): - print(f"{os.path.normpath(rules_file)} updates:") - with open(metrics_file, "r") as f: metrics = json.load(f) if not isinstance(metrics, dict): @@ -296,6 +294,7 @@ def gen_rule_file( rules[field] = dict(value=rule_value, compare=option["compare"]) if len(change_str) > 0: + print(f"{os.path.normpath(rules_file)} updates:") print(format_str.format("Metric", "Old", "New", "Type"), end="") print(format_str.format("------", "---", "---", "----"), end="") print(change_str) From 213e0b9b7b1d5b6ca3cd9b2be37e99905215cea8 Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Thu, 5 Jun 2025 13:20:34 -0700 Subject: [PATCH 028/198] removed ifeq since keep size only applies with SYNTH_HIERARCHIAL=1 Signed-off-by: Jeff Ng --- flow/designs/asap7/cva6/config.mk | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/flow/designs/asap7/cva6/config.mk b/flow/designs/asap7/cva6/config.mk index f22d8f8005..98fbc02499 100644 --- a/flow/designs/asap7/cva6/config.mk +++ b/flow/designs/asap7/cva6/config.mk @@ -88,8 +88,7 @@ export MACRO_HALO = 5 5 # few last gasp iterations export SKIP_LAST_GASP ?= 1 -ifeq ($(SYNTH_HIERARCHICAL),1) - export SYNTH_MINIMUM_KEEP_SIZE ?= 40000 -endif +# For use with SYNTH_HIERARCHICAL +export SYNTH_MINIMUM_KEEP_SIZE ?= 40000 export SYNTH_HDL_FRONTEND = slang From f81d3402bf52d8e32ea672e13b26ec513d378d20 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 6 Jun 2025 07:50:52 +0200 Subject: [PATCH 029/198] cleanup: old cruft from 2020 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/designs/harness.mk | 22 ---------------------- flow/designs/src/harness/.gitignore | 4 ---- flow/designs/src/harness/design.sdc | 12 ------------ 3 files changed, 38 deletions(-) delete mode 100644 flow/designs/harness.mk delete mode 100644 flow/designs/src/harness/.gitignore delete mode 100644 flow/designs/src/harness/design.sdc diff --git a/flow/designs/harness.mk b/flow/designs/harness.mk deleted file mode 100644 index 39db272b06..0000000000 --- a/flow/designs/harness.mk +++ /dev/null @@ -1,22 +0,0 @@ -export DESIGN_NAME ?= SPECIFY_DESIGN_NAME -export PLATFORM = nangate45 - -export VERILOG_FILES = ./designs/src/harness/*.v -export SDC_FILE = ./designs/src/harness/design.sdc - -export MERGED_LEF = $(PLATFORM_DIR)/NangateOpenCellLibrary.mod.lef -export LIB_FILES = $(PLATFORM_DIR)/NangateOpenCellLibrary_typical.lib -export GDS_FILES = $(sort $(wildcard $(PLATFORM_DIR)/gds/*)) - -# Automatically pick a reasonable area and utilization - -# Core utilization in % -export CORE_UTILIZATION = 10.0 -# Core height / core width -export CORE_ASPECT_RATIO = 1.0 -# Core margin in um -export CORE_MARGIN = 2.0 - -# Start with 250MHz for nangate45, relatively conservative -export CLOCK_PERIOD = 4 -export CLOCK_PORT = clock diff --git a/flow/designs/src/harness/.gitignore b/flow/designs/src/harness/.gitignore deleted file mode 100644 index 7f2238d06e..0000000000 --- a/flow/designs/src/harness/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -*.v -*.fir -*.json -*.v diff --git a/flow/designs/src/harness/design.sdc b/flow/designs/src/harness/design.sdc deleted file mode 100644 index b0fe5c6ab4..0000000000 --- a/flow/designs/src/harness/design.sdc +++ /dev/null @@ -1,12 +0,0 @@ -################################################################### - -# Created by write_sdc on Mon Jun 17 07:26:34 2019 - -################################################################### -set sdc_version 2.0 - -set_units -time ns -resistance kOhm -capacitance pF -voltage V -current mA -# Start with 250MHz for nangate45, relatively conservative -create_clock [get_ports clock] -period 4 -waveform {0 2} -set_clock_uncertainty 0 [get_clocks clock] -set_input_delay -clock clock -max 0 [get_ports clock] From 0d503befe8183a2aa676c1af4e778553a24181ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 6 Jun 2025 13:01:24 +0200 Subject: [PATCH 030/198] util: remove unused pandas dependency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Helpful in CI where minimal python installations are used, no need to add pandas Signed-off-by: Øyvind Harboe --- flow/util/genMetrics.py | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/flow/util/genMetrics.py b/flow/util/genMetrics.py index fab6256e2a..0b5ebee993 100755 --- a/flow/util/genMetrics.py +++ b/flow/util/genMetrics.py @@ -13,7 +13,6 @@ import argparse import json -import pandas as pd import re from glob import glob @@ -346,10 +345,6 @@ def extract_metrics( else: metrics_dict["total_time"] = str(total) - metrics_df = pd.DataFrame(list(metrics_dict.items())) - col_index = metrics_df.iloc[0][1] + "__" + metrics_df.iloc[1][1] - metrics_df.columns = ["Metrics", col_index] - if hier_json: # Convert the Metrics dictionary to hierarchical format by stripping # the stage as a 'key' @@ -363,13 +358,11 @@ def extract_metrics( with open(output, "w") as resultSpecfile: json.dump(metrics_dict, resultSpecfile, indent=2, sort_keys=True) - return metrics_dict, metrics_df - args = parse_args() now = datetime.now() -metrics_dict, metrics_df = extract_metrics( +extract_metrics( os.path.join(os.path.dirname(os.path.realpath(__file__)), "../"), args.platform, args.design, From 4263f0d9d24ce0fd0b278f81066d3a73c49877ef Mon Sep 17 00:00:00 2001 From: Jan Bylicki Date: Fri, 6 Jun 2025 13:22:01 +0200 Subject: [PATCH 031/198] platforms: asap7: Fixed set/reset signals for DFFASRHQNx1_ASAP7_75t_R Signed-off-by: Jan Bylicki --- .../asap7/lib/CCS/asap7sc7p5t_SEQ_RVT_FF_ccs_220123.lib | 4 ++-- .../asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib | 4 ++-- .../asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib | 4 ++-- .../asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_TT_nldm_220123.lib | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/flow/platforms/asap7/lib/CCS/asap7sc7p5t_SEQ_RVT_FF_ccs_220123.lib b/flow/platforms/asap7/lib/CCS/asap7sc7p5t_SEQ_RVT_FF_ccs_220123.lib index f9b44d302c..cee7cfbb10 100644 --- a/flow/platforms/asap7/lib/CCS/asap7sc7p5t_SEQ_RVT_FF_ccs_220123.lib +++ b/flow/platforms/asap7/lib/CCS/asap7sc7p5t_SEQ_RVT_FF_ccs_220123.lib @@ -11588,13 +11588,13 @@ library (asap7sc7p5t_SEQ_RVT_FF_ccs_220123) { } } ff (IQN,IQNN) { - clear : "!SETN"; + clear : "!RESETN"; clear_preset_var1 : L; clear_preset_var2 : L; clocked_on : "CLK"; next_state : "!D"; power_down_function : "(!VDD) + (VSS)"; - preset : "!RESETN"; + preset : "!SETN"; } } cell (DFFHQNx1_ASAP7_75t_R) { diff --git a/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib b/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib index f335d59f8b..c785513677 100755 --- a/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib +++ b/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib @@ -2688,13 +2688,13 @@ library (asap7sc7p5t_SEQ_RVT_FF_nldm_220123) { } } ff (IQN,IQNN) { - clear : "!SETN"; + clear : "!RESETN"; clear_preset_var1 : L; clear_preset_var2 : L; clocked_on : "CLK"; next_state : "!D"; power_down_function : "(!VDD) + (VSS)"; - preset : "!RESETN"; + preset : "!SETN"; } } diff --git a/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib b/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib index a004888814..0db82e8bf2 100755 --- a/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib +++ b/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib @@ -2688,13 +2688,13 @@ library (asap7sc7p5t_SEQ_RVT_SS_nldm_220123) { } } ff (IQN,IQNN) { - clear : "!SETN"; + clear : "!RESETN"; clear_preset_var1 : L; clear_preset_var2 : L; clocked_on : "CLK"; next_state : "!D"; power_down_function : "(!VDD) + (VSS)"; - preset : "!RESETN"; + preset : "!SETN"; } } diff --git a/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_TT_nldm_220123.lib b/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_TT_nldm_220123.lib index a2a257c944..20863d8381 100755 --- a/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_TT_nldm_220123.lib +++ b/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_TT_nldm_220123.lib @@ -2688,13 +2688,13 @@ library (asap7sc7p5t_SEQ_RVT_TT_nldm_220123) { } } ff (IQN,IQNN) { - clear : "!SETN"; + clear : "!RESETN"; clear_preset_var1 : L; clear_preset_var2 : L; clocked_on : "CLK"; next_state : "!D"; power_down_function : "(!VDD) + (VSS)"; - preset : "!RESETN"; + preset : "!SETN"; } } From 284749a2eed5be8ae3cbc8861285d173e22e0ac2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 6 Jun 2025 07:58:03 +0200 Subject: [PATCH 032/198] bazel: simplify, use OpenROAD from docker image MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- MODULE.bazel | 39 --------------------------------------- 1 file changed, 39 deletions(-) diff --git a/MODULE.bazel b/MODULE.bazel index 25bcc90e4b..cb5f6d832d 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -31,53 +31,14 @@ pip.parse( ) use_repo(pip, "orfs-pip") -# HACK! While we're waiting for OpenROAD to switch to bzlmod -new_local_repository = use_repo_rule("@bazel_tools//tools/build_defs/repo:local.bzl", "new_local_repository") - -new_local_repository( - name = "openroad", - build_file_content = """ -exports_files(["openroad"], -visibility = ["//visibility:public"], -) -filegroup( - name = "all", - data = glob(["openroad.runfiles/**/*"]), - visibility = ["//visibility:public"], -) -""", - path = "tools/OpenROAD/bazel-out/k8-opt/bin", -) - orfs = use_extension("@bazel-orfs//:extension.bzl", "orfs_repositories") # To bump version, run: bazelisk run @bazel-orfs//:bump orfs.default( - # Check out the version you want to test and make any modifications locally: - # - # ./build_openroad.sh --no_init - # - # Comment out "sha256" below, not available for local docker images - # and update "image" to point to the local image. - - # Official image https://hub.docker.com/r/openroad/orfs/tags image = "docker.io/openroad/orfs:v3.0-2888-g38f93c61", # Use local files instead of docker image makefile = "//flow:makefile", makefile_yosys = "//flow:makefile_yosys", - # TODO once openroad is switched to MODULE.bazel, use - # local_path_override(module_name = "openroad", path = "../tools/OpenROAD") - # to point to the local openroad Bazel module instead of - # getting the openroad binary from the docker image, supports GUI. - # - # openroad = "@docker_orfs//:openroad", - - # Use locally built OpenROAD while we're waiting for OpenROAD - # to bzlmod, no GUI for now. - # - # cd ../tools/OpenROAD - # bazelisk build -c opt :openroad - openroad = "//flow/test:openroad", pdk = "//flow:asap7", sha256 = "173581fc6ca74ece349150866ddce96534c5e9d855a25ca8ae509a45fcaefc0d", ) From b74f97662f0e47eee0d1b0d6ae27269e1d9b3174 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 6 Jun 2025 13:59:43 +0200 Subject: [PATCH 033/198] bazel-orfs: bump MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- MODULE.bazel | 6 +++--- MODULE.bazel.lock | 8 ++++---- flow/test/BUILD | 9 --------- flow/util/requirements_lock.txt | 6 +++--- 4 files changed, 10 insertions(+), 19 deletions(-) delete mode 100644 flow/test/BUILD diff --git a/MODULE.bazel b/MODULE.bazel index cb5f6d832d..86dc8624e4 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -11,7 +11,7 @@ bazel_dep(name = "bazel-orfs") # To bump version, run: bazelisk run @bazel-orfs//:bump git_override( module_name = "bazel-orfs", - commit = "4a67015d0165e14466b89cc7ce1e92688f393093", + commit = "9a3778bdbe63106a894a03e865335a31ebc860d1", remote = "https://github.com/The-OpenROAD-Project/bazel-orfs.git", ) @@ -35,12 +35,12 @@ orfs = use_extension("@bazel-orfs//:extension.bzl", "orfs_repositories") # To bump version, run: bazelisk run @bazel-orfs//:bump orfs.default( - image = "docker.io/openroad/orfs:v3.0-2888-g38f93c61", + image = "docker.io/openroad/orfs:v3.0-3190-g5ac9869c", # Use local files instead of docker image makefile = "//flow:makefile", makefile_yosys = "//flow:makefile_yosys", pdk = "//flow:asap7", - sha256 = "173581fc6ca74ece349150866ddce96534c5e9d855a25ca8ae509a45fcaefc0d", + sha256 = "2ca999699bc91144074b7f23f42da9330d7279437c386a1413fba4a6a7520916", ) use_repo(orfs, "com_github_nixos_patchelf_download") use_repo(orfs, "docker_orfs") diff --git a/MODULE.bazel.lock b/MODULE.bazel.lock index 2e7263fada..92f3178152 100644 --- a/MODULE.bazel.lock +++ b/MODULE.bazel.lock @@ -638,7 +638,7 @@ "@@bazel-orfs~//:extension.bzl%orfs_repositories": { "general": { "bzlTransitiveDigest": "opZMguyG+UPmDQ6vhzXe/u0WnKyao2m9IAQt+JWkhcA=", - "usagesDigest": "DOOJ9+vsihVM2cEr/ckxKDoJuGmICP6rKX1uYMN3cd4=", + "usagesDigest": "2NcMguz4FONad7PT2HxaMW3QgfrJL+IvDGhrVn5dQhU=", "recordedFileInputs": {}, "recordedDirentsInputs": {}, "envVariables": {}, @@ -658,8 +658,8 @@ "bzlFile": "@@bazel-orfs~//:docker.bzl", "ruleClassName": "docker_pkg", "attributes": { - "image": "docker.io/openroad/orfs:v3.0-2888-g38f93c61", - "sha256": "173581fc6ca74ece349150866ddce96534c5e9d855a25ca8ae509a45fcaefc0d", + "image": "docker.io/openroad/orfs:v3.0-3190-g5ac9869c", + "sha256": "2ca999699bc91144074b7f23f42da9330d7279437c386a1413fba4a6a7520916", "build_file": "@@bazel-orfs~//:docker.BUILD.bazel", "timeout": 3600, "patch_cmds": [ @@ -674,7 +674,7 @@ "makefile": "@@//flow:makefile", "pdk": "@@//flow:asap7", "makefile_yosys": "@@//flow:makefile_yosys", - "openroad": "@@//flow/test:openroad", + "openroad": "@@bazel-orfs~~orfs_repositories~docker_orfs//:openroad", "yosys": "@@bazel-orfs~~orfs_repositories~docker_orfs//:yosys", "yosys_abc": "@@bazel-orfs~~orfs_repositories~docker_orfs//:yosys-abc" } diff --git a/flow/test/BUILD b/flow/test/BUILD deleted file mode 100644 index 63efeade7d..0000000000 --- a/flow/test/BUILD +++ /dev/null @@ -1,9 +0,0 @@ -sh_binary( - name = "openroad", - srcs = ["openroad.sh"], - data = [ - "@openroad", - "@openroad//:all", - ], - visibility = ["//visibility:public"], -) diff --git a/flow/util/requirements_lock.txt b/flow/util/requirements_lock.txt index f47a529ab3..17d4824261 100644 --- a/flow/util/requirements_lock.txt +++ b/flow/util/requirements_lock.txt @@ -2,7 +2,7 @@ # This file is autogenerated by pip-compile with Python 3.12 # by the following command: # -# bazel run //:requirements.update +# bazel run //flow/util:requirements.update # contourpy==1.3.1 \ --hash=sha256:041b640d4ec01922083645a94bb3b2e777e6b626788f4095cf21abbe266413c1 \ @@ -233,7 +233,7 @@ matplotlib==3.10.0 \ --hash=sha256:d44cb942af1693cced2604c33a9abcef6205601c445f6d0dc531d813af8a2f5a \ --hash=sha256:d907fddb39f923d011875452ff1eca29a9e7f21722b873e90db32e5d8ddff12e \ --hash=sha256:fd44fc75522f58612ec4a33958a7e5552562b7705b42ef1b4f8c0818e304a363 - # via -r util/requirements.in + # via -r flow/util/requirements.in numpy==2.2.2 \ --hash=sha256:02935e2c3c0c6cbe9c7955a8efa8908dd4221d7755644c59d1bba28b94fd334f \ --hash=sha256:0349b025e15ea9d05c3d63f9657707a4e1d471128a3b1d876c095f328f8ff7f0 \ @@ -432,7 +432,7 @@ pyyaml==6.0.2 \ --hash=sha256:efdca5630322a10774e8e98e1af481aad470dd62c3170801852d752aa7a783ba \ --hash=sha256:f753120cb8181e736c57ef7636e83f31b9c0d1722c516f7e86cf15b7aa57ff12 \ --hash=sha256:ff3824dc5261f50c9b0dfb3be22b4567a6f938ccce4587b38952d85fd9e9afe4 - # via -r util/requirements.in + # via -r flow/util/requirements.in six==1.17.0 \ --hash=sha256:4721f391ed90541fddacab5acf947aa0d3dc7d27b2e1e8eda2be8970586c3274 \ --hash=sha256:ff70335d468e7eb6ec65b95b99d3a2836546063f63acc5171de367e834932a81 From 44525923bce32a1a94b54cb35c1ede5546d2cbfc Mon Sep 17 00:00:00 2001 From: arthurjolo Date: Fri, 6 Jun 2025 14:50:51 -0300 Subject: [PATCH 034/198] move the reapir_clk_nets to be called inside cts Signed-off-by: arthurjolo --- flow/scripts/cts.tcl | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/flow/scripts/cts.tcl b/flow/scripts/cts.tcl index 2d54b831c3..ab8e531229 100644 --- a/flow/scripts/cts.tcl +++ b/flow/scripts/cts.tcl @@ -16,7 +16,8 @@ proc save_progress {stage} { # Run CTS set cts_args [list \ -sink_clustering_enable \ - -balance_levels] + -balance_levels \ + -repair_clock_nets] append_env_var cts_args CTS_BUF_DISTANCE -distance_between_buffers 1 append_env_var cts_args CTS_CLUSTER_SIZE -sink_clustering_size 1 @@ -29,6 +30,8 @@ if {[env_var_exists_and_non_empty CTS_ARGS]} { set cts_args $::env(CTS_ARGS) } +set_dont_use $::env(DONT_USE_CELLS) + log_cmd clock_tree_synthesis {*}$cts_args if {[env_var_equals CTS_SNAPSHOTS 1]} { @@ -37,8 +40,6 @@ if {[env_var_equals CTS_SNAPSHOTS 1]} { set_propagated_clock [all_clocks] -set_dont_use $::env(DONT_USE_CELLS) - utl::push_metrics_stage "cts__{}__pre_repair" estimate_parasitics -placement From deb41954f3a68a774ebf89c2401af39d02f8db39 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Thu, 5 Jun 2025 13:47:50 +0200 Subject: [PATCH 035/198] flow: Makefile: Add WORK_HOME default value earlier We need this variable in the BLOCKS flow before variables.mk gets included. Copy the same export to have this variable set in case WORK_HOME is not set. Signed-off-by: Daniel Schultz --- flow/Makefile | 4 +++- flow/scripts/variables.mk | 3 +-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/flow/Makefile b/flow/Makefile index 335d3a87f3..ff50e84654 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -89,10 +89,12 @@ include $(DESIGN_CONFIG) export DESIGN_DIR ?= $(dir $(DESIGN_CONFIG)) -# default value "base" is duplicated from variables.yaml because we need it +# default value "base" for FLOW_VARIANT and "." for WORK_HOME are duplicated +# from variables.yaml and variables.mk because we need it # earlier in the flow for BLOCKS. BLOCKS is a feature specific to the # ORFS Makefile. export FLOW_VARIANT?=base +export WORK_HOME?=. # BLOCKS is a ORFS make flow specific feature. ifneq ($(BLOCKS),) # Normally this comes from variables.yaml, but we need it here to set up these variables diff --git a/flow/scripts/variables.mk b/flow/scripts/variables.mk index 0292bf9f2d..8d0ae89cd4 100644 --- a/flow/scripts/variables.mk +++ b/flow/scripts/variables.mk @@ -18,11 +18,10 @@ export DESIGN_NICKNAME?=$(DESIGN_NAME) # Setup variables to point to other location for the following sub directory # - designs - default is under current directory # - platforms - default is under current directory -# - work home - default is current directory # - utils, scripts, test - default is under current directory export DESIGN_HOME ?= $(FLOW_HOME)/designs export PLATFORM_HOME ?= $(FLOW_HOME)/platforms -export WORK_HOME ?= . +# WORK_HOME is set up in flow/Makefile export UTILS_DIR ?= $(FLOW_HOME)/util export SCRIPTS_DIR ?= $(FLOW_HOME)/scripts From 540f48938d96a45147d28ef46c001a37a5dbe78d Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Mon, 9 Jun 2025 10:46:24 -0300 Subject: [PATCH 036/198] use latest openroad Signed-off-by: Eder Monteiro --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index 66559c8bcf..8986d631fc 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 66559c8bcf6782e2f68ccf4a01a80ee8cc8c499e +Subproject commit 8986d631fcd126f4cd8a2dea05ec015f04d86df5 From fb6d6507df0de1eceddb4e489174cf889b6b499f Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Mon, 9 Jun 2025 10:46:41 -0300 Subject: [PATCH 037/198] use Yosys 0.54 Signed-off-by: Eder Monteiro --- tools/yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/yosys b/tools/yosys index 53c22ab7c0..db72ec3bde 160000 --- a/tools/yosys +++ b/tools/yosys @@ -1 +1 @@ -Subproject commit 53c22ab7c0ced80861c7536c5dae682c30fb5834 +Subproject commit db72ec3bde296a9512b2d1e6fabf81cfb07c2c1b From ecafa97ca484d56fe0d53cf4dcbd7963d7c1c4cb Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Mon, 9 Jun 2025 18:19:49 -0300 Subject: [PATCH 038/198] update public designs metrics Signed-off-by: Eder Monteiro --- flow/designs/asap7/aes-block/rules-base.json | 10 +++++----- flow/designs/ihp-sg13g2/ibex/rules-base.json | 10 +++++----- flow/designs/nangate45/swerv/rules-base.json | 4 ++-- flow/designs/nangate45/swerv_wrapper/rules-base.json | 12 ++++++------ flow/designs/nangate45/tinyRocket/rules-base.json | 4 ++-- flow/designs/sky130hd/microwatt/rules-base.json | 4 ++-- flow/designs/sky130hs/ibex/rules-base.json | 12 ++++++------ 7 files changed, 28 insertions(+), 28 deletions(-) diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json index 9412b6aec5..817f066d5b 100644 --- a/flow/designs/asap7/aes-block/rules-base.json +++ b/flow/designs/asap7/aes-block/rules-base.json @@ -24,7 +24,7 @@ "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1059, + "value": 1244, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 82802, + "value": 77091, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -100.58, + "value": -68.19, "compare": ">=" }, "finish__design__instance__area": { @@ -60,11 +60,11 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 335, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -21.42, + "value": -18.47, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/ibex/rules-base.json b/flow/designs/ihp-sg13g2/ibex/rules-base.json index 9c1509e822..8b520ea9ec 100644 --- a/flow/designs/ihp-sg13g2/ibex/rules-base.json +++ b/flow/designs/ihp-sg13g2/ibex/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 371258, + "value": 365471, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 12, + "value": 0, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -44,11 +44,11 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 26, + "value": 51, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.83, + "value": -0.17, "compare": ">=" }, "finish__design__instance__area": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -14.76, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/swerv/rules-base.json b/flow/designs/nangate45/swerv/rules-base.json index 4f5b5a19c9..7a4e713281 100644 --- a/flow/designs/nangate45/swerv/rules-base.json +++ b/flow/designs/nangate45/swerv/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 3342843, + "value": 3900533, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 185, + "value": 1165, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/nangate45/swerv_wrapper/rules-base.json b/flow/designs/nangate45/swerv_wrapper/rules-base.json index 885af20f86..5fe8593bb9 100644 --- a/flow/designs/nangate45/swerv_wrapper/rules-base.json +++ b/flow/designs/nangate45/swerv_wrapper/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 755529, + "value": 755158, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 5508164, + "value": 5096058, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,11 +48,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.52, + "value": -0.33, "compare": ">=" }, "finish__design__instance__area": { - "value": 763024, + "value": 762884, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -60,11 +60,11 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 399, + "value": 656, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -21.69, + "value": -20.07, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/tinyRocket/rules-base.json b/flow/designs/nangate45/tinyRocket/rules-base.json index 480d0b66c4..eaaba9cf90 100644 --- a/flow/designs/nangate45/tinyRocket/rules-base.json +++ b/flow/designs/nangate45/tinyRocket/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 833444, + "value": 822134, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.21, + "value": -0.32, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/sky130hd/microwatt/rules-base.json b/flow/designs/sky130hd/microwatt/rules-base.json index f01cf57848..c9c30f9494 100644 --- a/flow/designs/sky130hd/microwatt/rules-base.json +++ b/flow/designs/sky130hd/microwatt/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 10055574, + "value": 11745555, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -40,7 +40,7 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 6, + "value": 9, "compare": "<=" }, "detailedroute__antenna_diodes_count": { diff --git a/flow/designs/sky130hs/ibex/rules-base.json b/flow/designs/sky130hs/ibex/rules-base.json index 3e5c82bbc9..d55bd63edf 100644 --- a/flow/designs/sky130hs/ibex/rules-base.json +++ b/flow/designs/sky130hs/ibex/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 261504, + "value": 261133, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 19444, + "value": 19436, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1691, + "value": 1690, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1691, + "value": 1690, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 787855, + "value": 911447, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 34, + "value": 33, "compare": "<=" }, "finish__timing__setup__ws": { From 0d713107f5265f800504412ae02d94714689f186 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 7 May 2025 13:01:33 +0200 Subject: [PATCH 039/198] Prepare flow for new placement buffering MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- flow/scripts/global_place.tcl | 13 +++++++++++++ flow/scripts/resize.tcl | 11 ----------- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/flow/scripts/global_place.tcl b/flow/scripts/global_place.tcl index 5969c9e9d8..ea7448311f 100644 --- a/flow/scripts/global_place.tcl +++ b/flow/scripts/global_place.tcl @@ -5,6 +5,19 @@ load_design 3_2_place_iop.odb 2_floorplan.sdc set_dont_use $::env(DONT_USE_CELLS) +remove_buffers + +# Do not buffer chip-level designs +# by default, IO ports will be buffered +# to not buffer IO ports, set environment variable +# DONT_BUFFER_PORT = 1 +if { ![env_var_exists_and_non_empty FOOTPRINT] } { + if { ![env_var_equals DONT_BUFFER_PORTS 1] } { + puts "Perform port buffering..." + buffer_ports + } +} + fast_route set global_placement_args {} diff --git a/flow/scripts/resize.tcl b/flow/scripts/resize.tcl index cb38355043..1982f9b9aa 100644 --- a/flow/scripts/resize.tcl +++ b/flow/scripts/resize.tcl @@ -10,17 +10,6 @@ set pin_count_before [sta::network_leaf_pin_count] set_dont_use $::env(DONT_USE_CELLS) -# Do not buffer chip-level designs -# by default, IO ports will be buffered -# to not buffer IO ports, set environment variable -# DONT_BUFFER_PORT = 1 -if { ![env_var_exists_and_non_empty FOOTPRINT] } { - if { ![env_var_equals DONT_BUFFER_PORTS 1] } { - puts "Perform port buffering..." - buffer_ports - } -} - repair_design_helper if { [env_var_exists_and_non_empty TIE_SEPARATION] } { From ae58ff29ebb4ca0121fd15336454342152cbd0a2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 10 Jun 2025 12:44:18 +0200 Subject: [PATCH 040/198] Pull OR change for "Rebuffering in TD global placement" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- .gitmodules | 2 +- tools/OpenROAD | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index ec90369ba8..4afc70f8bb 100644 --- a/.gitmodules +++ b/.gitmodules @@ -3,7 +3,7 @@ url = ../../The-OpenROAD-Project/yosys.git [submodule "tools/OpenROAD"] path = tools/OpenROAD - url = ../OpenROAD.git + url = ../../The-OpenROAD-Project-staging/OpenROAD.git [submodule "tools/yosys-slang"] path = tools/yosys-slang url = https://github.com/povik/yosys-slang.git diff --git a/tools/OpenROAD b/tools/OpenROAD index 66559c8bcf..9f2a3e6b42 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 66559c8bcf6782e2f68ccf4a01a80ee8cc8c499e +Subproject commit 9f2a3e6b42440ce2357e44151f8749ad11c0067d From 2ecea0dba1afefffb122f6814fb7d5493c88bcf1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 10 Jun 2025 16:35:20 +0200 Subject: [PATCH 041/198] Release virtual TD overrides MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- flow/designs/gf12/ariane/config.mk | 3 --- flow/designs/nangate45/swerv_wrapper/config.mk | 2 -- 2 files changed, 5 deletions(-) diff --git a/flow/designs/gf12/ariane/config.mk b/flow/designs/gf12/ariane/config.mk index cfb21ab138..28194633ef 100644 --- a/flow/designs/gf12/ariane/config.mk +++ b/flow/designs/gf12/ariane/config.mk @@ -24,9 +24,6 @@ export PLACE_DENSITY ?= 0.50 export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/io.tcl -# to be removed once gpl is fixed for "corner buffers" issue -export GPL_KEEP_OVERFLOW = 0 - export MACRO_PLACE_HALO = 7 7 export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl diff --git a/flow/designs/nangate45/swerv_wrapper/config.mk b/flow/designs/nangate45/swerv_wrapper/config.mk index 6d45062af7..2ce3c88234 100644 --- a/flow/designs/nangate45/swerv_wrapper/config.mk +++ b/flow/designs/nangate45/swerv_wrapper/config.mk @@ -23,5 +23,3 @@ export PLACE_DENSITY_LB_ADDON = 0.08 export TNS_END_PERCENT = 100 export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl - -export GPL_KEEP_OVERFLOW = 0 From 497d64967c560994c4fe9d245a0567dbe32419b4 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Tue, 10 Jun 2025 12:24:38 -0300 Subject: [PATCH 042/198] update sky130hd/ibex configs and metrics Signed-off-by: Eder Monteiro --- flow/designs/sky130hd/ibex/config.mk | 2 +- flow/designs/sky130hd/ibex/rules-base.json | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/flow/designs/sky130hd/ibex/config.mk b/flow/designs/sky130hd/ibex/config.mk index c0c930cc3e..5f03b5aae7 100644 --- a/flow/designs/sky130hd/ibex/config.mk +++ b/flow/designs/sky130hd/ibex/config.mk @@ -16,7 +16,7 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint. export ADDER_MAP_FILE := export CORE_UTILIZATION = 45 -export PLACE_DENSITY_LB_ADDON = 0.2 +export PLACE_DENSITY_LB_ADDON = 0.25 export TNS_END_PERCENT = 100 export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl diff --git a/flow/designs/sky130hd/ibex/rules-base.json b/flow/designs/sky130hd/ibex/rules-base.json index 19ca204614..a3e84be8d1 100644 --- a/flow/designs/sky130hd/ibex/rules-base.json +++ b/flow/designs/sky130hd/ibex/rules-base.json @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 64, + "value": 24, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 808993, + "value": 801898, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,15 +44,15 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 70, + "value": 57, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.45, + "value": -0.94, "compare": ">=" }, "finish__design__instance__area": { - "value": 205228, + "value": 204248, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -19.68, + "value": -16.35, "compare": ">=" } } \ No newline at end of file From 9ceb44e051fa454a5d27f690e16fa3e8135a9b06 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" Date: Tue, 10 Jun 2025 18:59:46 +0000 Subject: [PATCH 043/198] flow: update rules Signed-off-by: github-actions[bot] --- flow/designs/asap7/aes-block/rules-base.json | 8 ++++---- flow/designs/asap7/aes-mbff/rules-base.json | 20 +++++++++---------- flow/designs/asap7/aes/rules-base.json | 20 +++++++++---------- flow/designs/asap7/aes_lvt/rules-base.json | 8 ++++---- flow/designs/asap7/ethmac/rules-base.json | 18 ++++++++--------- flow/designs/asap7/ethmac_lvt/rules-base.json | 18 ++++++++--------- flow/designs/asap7/gcd-ccs/rules-base.json | 10 +++++----- flow/designs/asap7/gcd/rules-base.json | 8 ++++---- flow/designs/asap7/ibex/rules-base.json | 20 +++++++++---------- flow/designs/asap7/jpeg/rules-base.json | 16 +++++++-------- flow/designs/asap7/jpeg_lvt/rules-base.json | 16 +++++++-------- flow/designs/asap7/mock-alu/rules-base.json | 6 +++--- flow/designs/asap7/mock-array/rules-base.json | 4 ++-- flow/designs/asap7/mock-cpu/rules-base.json | 8 ++++---- .../asap7/riscv32i-mock-sram/rules-base.json | 10 +++++----- flow/designs/asap7/riscv32i/rules-base.json | 18 ++++++++--------- .../asap7/swerv_wrapper/rules-base.json | 4 ++-- flow/designs/asap7/uart/rules-base.json | 4 ++-- flow/designs/gf180/aes-hybrid/rules-base.json | 10 +++++----- flow/designs/gf180/aes/rules-base.json | 10 +++++----- flow/designs/gf180/ibex/rules-base.json | 18 ++++++++--------- flow/designs/gf180/jpeg/rules-base.json | 20 +++++++++---------- flow/designs/gf180/riscv32i/rules-base.json | 14 ++++++------- .../designs/gf180/uart-blocks/rules-base.json | 6 +++--- flow/designs/ihp-sg13g2/aes/rules-base.json | 12 +++++------ flow/designs/ihp-sg13g2/gcd/rules-base.json | 4 ++-- .../i2c-gpio-expander/rules-base.json | 12 +++++------ flow/designs/ihp-sg13g2/ibex/rules-base.json | 16 +++++++-------- flow/designs/ihp-sg13g2/jpeg/rules-base.json | 10 +++++----- .../ihp-sg13g2/riscv32i/rules-base.json | 12 +++++------ flow/designs/ihp-sg13g2/spi/rules-base.json | 8 ++++---- flow/designs/nangate45/aes/rules-base.json | 10 +++++----- .../nangate45/ariane133/rules-base.json | 8 ++++---- .../nangate45/ariane136/rules-base.json | 8 ++++---- .../nangate45/black_parrot/rules-base.json | 16 +++++++-------- .../nangate45/bp_be_top/rules-base.json | 16 +++++++-------- .../nangate45/bp_fe_top/rules-base.json | 14 ++++++------- .../nangate45/bp_multi_top/rules-base.json | 16 +++++++-------- .../nangate45/dynamic_node/rules-base.json | 14 ++++++------- flow/designs/nangate45/gcd/rules-base.json | 8 ++++---- flow/designs/nangate45/ibex/rules-base.json | 18 ++++++++--------- flow/designs/nangate45/jpeg/rules-base.json | 16 +++++++-------- flow/designs/nangate45/swerv/rules-base.json | 20 +++++++++---------- .../nangate45/swerv_wrapper/rules-base.json | 14 ++++++------- .../nangate45/tinyRocket/rules-base.json | 10 +++++----- flow/designs/sky130hd/aes/rules-base.json | 4 ++-- .../sky130hd/chameleon/rules-base.json | 12 +++++------ flow/designs/sky130hd/gcd/rules-base.json | 6 +++--- flow/designs/sky130hd/ibex/rules-base.json | 12 +++++------ flow/designs/sky130hd/jpeg/rules-base.json | 4 ++-- .../sky130hd/microwatt/rules-base.json | 14 ++++++------- .../designs/sky130hd/riscv32i/rules-base.json | 14 ++++++------- flow/designs/sky130hs/aes/rules-base.json | 8 ++++---- flow/designs/sky130hs/gcd/rules-base.json | 10 +++++----- flow/designs/sky130hs/ibex/rules-base.json | 8 ++++---- flow/designs/sky130hs/jpeg/rules-base.json | 20 +++++++++---------- .../designs/sky130hs/riscv32i/rules-base.json | 18 ++++++++--------- 57 files changed, 343 insertions(+), 343 deletions(-) diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json index 9412b6aec5..8e28aaadab 100644 --- a/flow/designs/asap7/aes-block/rules-base.json +++ b/flow/designs/asap7/aes-block/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 2293.17, + "value": 2131.37, "compare": "<=" }, "constraints__clocks__count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 82802, + "value": 75603, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -100.58, + "value": -83.73, "compare": ">=" }, "finish__design__instance__area": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 335, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/asap7/aes-mbff/rules-base.json b/flow/designs/asap7/aes-mbff/rules-base.json index a55c9a0b72..5b87e6a78e 100644 --- a/flow/designs/asap7/aes-mbff/rules-base.json +++ b/flow/designs/asap7/aes-mbff/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 1972.31, + "value": 1928.39, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2273, + "value": 2214, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 19686, + "value": 19594, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1712, + "value": 1704, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1712, + "value": 1704, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 89339, + "value": 76679, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -68.71, + "value": -42.46, "compare": ">=" }, "finish__design__instance__area": { - "value": 2359, + "value": 2272, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 856, + "value": 852, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -21.4, + "value": -15.57, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/aes/rules-base.json b/flow/designs/asap7/aes/rules-base.json index 47f49f188b..6038bda668 100644 --- a/flow/designs/asap7/aes/rules-base.json +++ b/flow/designs/asap7/aes/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 1972.31, + "value": 1928.39, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2273, + "value": 2214, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 19686, + "value": 19594, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1712, + "value": 1704, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1712, + "value": 1704, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 86627, + "value": 74787, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -70.11, + "value": -34.79, "compare": ">=" }, "finish__design__instance__area": { - "value": 2350, + "value": 2278, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 856, + "value": 852, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -19.6, + "value": -13.72, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/aes_lvt/rules-base.json b/flow/designs/asap7/aes_lvt/rules-base.json index 051ab64450..2b534e1efd 100644 --- a/flow/designs/asap7/aes_lvt/rules-base.json +++ b/flow/designs/asap7/aes_lvt/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 77902, + "value": 72549, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,11 +48,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -29.62, + "value": -16.32, "compare": ">=" }, "finish__design__instance__area": { - "value": 2142, + "value": 2103, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -12.43, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/ethmac/rules-base.json b/flow/designs/asap7/ethmac/rules-base.json index ad4a2c2eca..c6e93e2063 100644 --- a/flow/designs/asap7/ethmac/rules-base.json +++ b/flow/designs/asap7/ethmac/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 9662, + "value": 9343, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 71326, + "value": 71068, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 6202, + "value": 6180, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 6202, + "value": 6180, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 559393, + "value": 232938, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -187.76, + "value": -144.87, "compare": ">=" }, "finish__design__instance__area": { - "value": 10048, + "value": 9507, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 3101, + "value": 3090, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -44.05, + "value": -42.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/ethmac_lvt/rules-base.json b/flow/designs/asap7/ethmac_lvt/rules-base.json index e6752b88b5..36f0d0a851 100644 --- a/flow/designs/asap7/ethmac_lvt/rules-base.json +++ b/flow/designs/asap7/ethmac_lvt/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 9583, + "value": 8660, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 69566, + "value": 66074, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 6049, + "value": 5746, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 6049, + "value": 5746, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 653875, + "value": 250591, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -225.06, + "value": -55.18, "compare": ">=" }, "finish__design__instance__area": { - "value": 9943, + "value": 8806, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 3025, + "value": 2873, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -22.89, + "value": -22.5, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/gcd-ccs/rules-base.json b/flow/designs/asap7/gcd-ccs/rules-base.json index 8b4b672953..3b2e302854 100644 --- a/flow/designs/asap7/gcd-ccs/rules-base.json +++ b/flow/designs/asap7/gcd-ccs/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 543, + "value": 540, "compare": "<=" }, "detailedplace__design__violations": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1357, + "value": 1224, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -96.02, + "value": -94.0, "compare": ">=" }, "finish__design__instance__area": { - "value": 57, + "value": 56, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 43, + "value": 24, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/asap7/gcd/rules-base.json b/flow/designs/asap7/gcd/rules-base.json index b335dc0836..186b37c73d 100644 --- a/flow/designs/asap7/gcd/rules-base.json +++ b/flow/designs/asap7/gcd/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1410, + "value": 1286, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,11 +48,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -74.47, + "value": -73.56, "compare": ">=" }, "finish__design__instance__area": { - "value": 60, + "value": 59, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -33.05, + "value": -32.76, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/ibex/rules-base.json b/flow/designs/asap7/ibex/rules-base.json index 7e13390189..ab9f3184ac 100644 --- a/flow/designs/asap7/ibex/rules-base.json +++ b/flow/designs/asap7/ibex/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 2616.39, + "value": 2612.72, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2950, + "value": 2805, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 24427, + "value": 22941, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 2124, + "value": 1995, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 2124, + "value": 1995, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 132532, + "value": 106483, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -108.44, + "value": -75.22, "compare": ">=" }, "finish__design__instance__area": { - "value": 3035, + "value": 2867, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 1062, + "value": 997, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -15.17, + "value": -11.43, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/jpeg/rules-base.json b/flow/designs/asap7/jpeg/rules-base.json index aa8d38a509..37cf7724de 100644 --- a/flow/designs/asap7/jpeg/rules-base.json +++ b/flow/designs/asap7/jpeg/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 7648, + "value": 7287, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 65384, + "value": 63593, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 5686, + "value": 5530, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 5686, + "value": 5530, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 317533, + "value": 181528, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -54.68, + "value": 0.0, "compare": ">=" }, "finish__design__instance__area": { - "value": 7738, + "value": 7375, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 2843, + "value": 2765, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/asap7/jpeg_lvt/rules-base.json b/flow/designs/asap7/jpeg_lvt/rules-base.json index 37a1f60261..8f6bc56ba2 100644 --- a/flow/designs/asap7/jpeg_lvt/rules-base.json +++ b/flow/designs/asap7/jpeg_lvt/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 7707, + "value": 7477, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 67276, + "value": 66675, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 5850, + "value": 5798, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 5850, + "value": 5798, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 315524, + "value": 187616, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -67.87, + "value": 0.0, "compare": ">=" }, "finish__design__instance__area": { - "value": 7778, + "value": 7543, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 2925, + "value": 2899, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/asap7/mock-alu/rules-base.json b/flow/designs/asap7/mock-alu/rules-base.json index 350a675995..bbec5f551f 100644 --- a/flow/designs/asap7/mock-alu/rules-base.json +++ b/flow/designs/asap7/mock-alu/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 61395, + "value": 59049, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -521.3, + "value": -506.14, "compare": ">=" }, "finish__design__instance__area": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 116, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/asap7/mock-array/rules-base.json b/flow/designs/asap7/mock-array/rules-base.json index e9501321df..f11664d7bf 100644 --- a/flow/designs/asap7/mock-array/rules-base.json +++ b/flow/designs/asap7/mock-array/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -92.28, + "value": 0.0, "compare": ">=" }, "finish__design__instance__area": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -25.4, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/mock-cpu/rules-base.json b/flow/designs/asap7/mock-cpu/rules-base.json index d299f58c15..4cd178023b 100644 --- a/flow/designs/asap7/mock-cpu/rules-base.json +++ b/flow/designs/asap7/mock-cpu/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 7398, + "value": 7389, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 53867, + "value": 52446, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -52,7 +52,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 7961, + "value": 7638, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 101, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/asap7/riscv32i-mock-sram/rules-base.json b/flow/designs/asap7/riscv32i-mock-sram/rules-base.json index 0c8bd5dfeb..e38e846845 100644 --- a/flow/designs/asap7/riscv32i-mock-sram/rules-base.json +++ b/flow/designs/asap7/riscv32i-mock-sram/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2616, + "value": 2395, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 148204, + "value": 95161, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,11 +48,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -187.67, + "value": -79.2, "compare": ">=" }, "finish__design__instance__area": { - "value": 2667, + "value": 2464, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -22.19, + "value": -11.73, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/riscv32i/rules-base.json b/flow/designs/asap7/riscv32i/rules-base.json index abf9096660..ce0d33577c 100644 --- a/flow/designs/asap7/riscv32i/rules-base.json +++ b/flow/designs/asap7/riscv32i/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 3191, + "value": 3109, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 12507, + "value": 11777, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1088, + "value": 1024, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1088, + "value": 1024, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 137800, + "value": 83651, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -113.89, + "value": -44.21, "compare": ">=" }, "finish__design__instance__area": { - "value": 3234, + "value": 3180, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 827, + "value": 512, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -14.39, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/swerv_wrapper/rules-base.json b/flow/designs/asap7/swerv_wrapper/rules-base.json index 6f5045049c..e1ce5d7c25 100644 --- a/flow/designs/asap7/swerv_wrapper/rules-base.json +++ b/flow/designs/asap7/swerv_wrapper/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1919981, + "value": 1867701, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 950, + "value": 286, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/asap7/uart/rules-base.json b/flow/designs/asap7/uart/rules-base.json index 220aa64156..80006ed54c 100644 --- a/flow/designs/asap7/uart/rules-base.json +++ b/flow/designs/asap7/uart/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -24.54, + "value": -20.24, "compare": ">=" }, "finish__design__instance__area": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -13.14, + "value": -11.75, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf180/aes-hybrid/rules-base.json b/flow/designs/gf180/aes-hybrid/rules-base.json index 171d847296..1478ea051c 100644 --- a/flow/designs/gf180/aes-hybrid/rules-base.json +++ b/flow/designs/gf180/aes-hybrid/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 21061, + "value": 26088, "compare": "<=" }, "detailedplace__design__violations": { @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 2, + "value": 84, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1815251, + "value": 1799784, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,11 +48,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.2, + "value": -1.43, "compare": ">=" }, "finish__design__instance__area": { - "value": 685668, + "value": 803898, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { diff --git a/flow/designs/gf180/aes/rules-base.json b/flow/designs/gf180/aes/rules-base.json index 7b11b18d98..9de3ce5b90 100644 --- a/flow/designs/gf180/aes/rules-base.json +++ b/flow/designs/gf180/aes/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 21792, + "value": 25876, "compare": "<=" }, "detailedplace__design__violations": { @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 0, + "value": 72, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1512295, + "value": 1477421, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,11 +48,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.28, + "value": -1.25, "compare": ">=" }, "finish__design__instance__area": { - "value": 762481, + "value": 905336, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { diff --git a/flow/designs/gf180/ibex/rules-base.json b/flow/designs/gf180/ibex/rules-base.json index aaaa3c0bf8..9f50f9890d 100644 --- a/flow/designs/gf180/ibex/rules-base.json +++ b/flow/designs/gf180/ibex/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 738423.39, + "value": 731295.7, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 845748, + "value": 813057, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 17828, + "value": 17103, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1550, + "value": 1487, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1550, + "value": 1487, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,11 +32,11 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1753283, + "value": 1544585, "compare": "<=" }, "detailedroute__route__drc_errors": { - "value": 1, + "value": 0, "compare": "<=" }, "detailedroute__antenna__violating__nets": { @@ -52,11 +52,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 1067423, + "value": 985974, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 785, + "value": 744, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/gf180/jpeg/rules-base.json b/flow/designs/gf180/jpeg/rules-base.json index 7e687cf3b3..87365b1740 100644 --- a/flow/designs/gf180/jpeg/rules-base.json +++ b/flow/designs/gf180/jpeg/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2383064, + "value": 2366631, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 54888, + "value": 53829, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 4773, + "value": 4681, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 4773, + "value": 4681, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 4, + "value": 0, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 4344677, + "value": 2985307, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 16, + "value": 6, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.47, + "value": 0.0, "compare": ">=" }, "finish__design__instance__area": { - "value": 2842064, + "value": 2695462, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 2386, + "value": 2340, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/gf180/riscv32i/rules-base.json b/flow/designs/gf180/riscv32i/rules-base.json index 0f614f7f60..50900a70fd 100644 --- a/flow/designs/gf180/riscv32i/rules-base.json +++ b/flow/designs/gf180/riscv32i/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 414808, + "value": 383765, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 8511, + "value": 8224, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 740, + "value": 715, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 740, + "value": 715, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 891236, + "value": 754102, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -52,11 +52,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 521614, + "value": 475666, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 370, + "value": 358, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/gf180/uart-blocks/rules-base.json b/flow/designs/gf180/uart-blocks/rules-base.json index eaea660e58..e54080e043 100644 --- a/flow/designs/gf180/uart-blocks/rules-base.json +++ b/flow/designs/gf180/uart-blocks/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 731, + "value": 726, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 64, + "value": 63, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 64, + "value": 63, "compare": "<=" }, "globalroute__antenna_diodes_count": { diff --git a/flow/designs/ihp-sg13g2/aes/rules-base.json b/flow/designs/ihp-sg13g2/aes/rules-base.json index ce2965075c..c0dbd17b30 100644 --- a/flow/designs/ihp-sg13g2/aes/rules-base.json +++ b/flow/designs/ihp-sg13g2/aes/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 253595, + "value": 229478, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 19280, + "value": 18996, "compare": "<=" }, "detailedplace__design__violations": { @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 3, + "value": 166, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -44,11 +44,11 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 24, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.13, + "value": 0.0, "compare": ">=" }, "finish__design__instance__area": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 841, + "value": 826, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/ihp-sg13g2/gcd/rules-base.json b/flow/designs/ihp-sg13g2/gcd/rules-base.json index bc7b71a86d..e8f4653148 100644 --- a/flow/designs/ihp-sg13g2/gcd/rules-base.json +++ b/flow/designs/ihp-sg13g2/gcd/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 505, + "value": 494, "compare": "<=" }, "detailedplace__design__violations": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.16, + "value": 0.0, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json index e3879ba092..3116dcc040 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 1601, + "value": 1539, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 139, + "value": 134, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 139, + "value": 134, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 2, + "value": 0, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 60953, + "value": 47873, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 70, + "value": 67, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/ihp-sg13g2/ibex/rules-base.json b/flow/designs/ihp-sg13g2/ibex/rules-base.json index 9c1509e822..4f9791c95a 100644 --- a/flow/designs/ihp-sg13g2/ibex/rules-base.json +++ b/flow/designs/ihp-sg13g2/ibex/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 371258, + "value": 325866, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 21142, + "value": 20844, "compare": "<=" }, "detailedplace__design__violations": { @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 12, + "value": 3, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1194089, + "value": 1072557, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,11 +44,11 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 26, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.83, + "value": -0.34, "compare": ">=" }, "finish__design__instance__area": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 986, + "value": 906, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -14.76, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/jpeg/rules-base.json b/flow/designs/ihp-sg13g2/jpeg/rules-base.json index bf2a834c15..913c3fa3c8 100644 --- a/flow/designs/ihp-sg13g2/jpeg/rules-base.json +++ b/flow/designs/ihp-sg13g2/jpeg/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 87671, + "value": 86736, "compare": "<=" }, "detailedplace__design__violations": { @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 27, + "value": 4, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 3188482, + "value": 3140459, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 160, + "value": 134, "compare": "<=" }, "finish__timing__setup__ws": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 3812, + "value": 3771, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/ihp-sg13g2/riscv32i/rules-base.json b/flow/designs/ihp-sg13g2/riscv32i/rules-base.json index d782c9d2ef..4a5905cd8e 100644 --- a/flow/designs/ihp-sg13g2/riscv32i/rules-base.json +++ b/flow/designs/ihp-sg13g2/riscv32i/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 177178, + "value": 171401, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 770173, + "value": 534072, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,11 +44,11 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 33, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.4, + "value": 0.0, "compare": ">=" }, "finish__design__instance__area": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 523, + "value": 478, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -12.48, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/spi/rules-base.json b/flow/designs/ihp-sg13g2/spi/rules-base.json index cd53421bf4..d2611dfd68 100644 --- a/flow/designs/ihp-sg13g2/spi/rules-base.json +++ b/flow/designs/ihp-sg13g2/spi/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 5088, + "value": 4888, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.25, + "value": -0.09, "compare": ">=" }, "finish__design__instance__area": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 17, + "value": 8, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -21.65, + "value": -15.74, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/aes/rules-base.json b/flow/designs/nangate45/aes/rules-base.json index a927b19b33..65c5fac049 100644 --- a/flow/designs/nangate45/aes/rules-base.json +++ b/flow/designs/nangate45/aes/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 27558, + "value": 26514, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 351027, + "value": 298800, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,11 +48,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.11, + "value": -0.06, "compare": ">=" }, "finish__design__instance__area": { - "value": 30793, + "value": 27064, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -18.58, + "value": -13.22, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/ariane133/rules-base.json b/flow/designs/nangate45/ariane133/rules-base.json index 4c7ede902a..00369c0887 100644 --- a/flow/designs/nangate45/ariane133/rules-base.json +++ b/flow/designs/nangate45/ariane133/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 872735, + "value": 871517, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - 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"value": 26043, + "value": 24426, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 8591633, + "value": 7165555, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -3.63, + "value": -3.58, "compare": ">=" }, "finish__design__instance__area": { - "value": 870913, + "value": 832384, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 13022, + "value": 12213, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/nangate45/bp_be_top/rules-base.json b/flow/designs/nangate45/bp_be_top/rules-base.json index f69d95f09a..f886e74244 100644 --- a/flow/designs/nangate45/bp_be_top/rules-base.json +++ b/flow/designs/nangate45/bp_be_top/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 298541, + "value": 288926, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - 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"value": 185, + "value": 131, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -22.51, + "value": -21.98, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/swerv_wrapper/rules-base.json b/flow/designs/nangate45/swerv_wrapper/rules-base.json index 885af20f86..a182da906e 100644 --- a/flow/designs/nangate45/swerv_wrapper/rules-base.json +++ b/flow/designs/nangate45/swerv_wrapper/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 115300, + "value": 113069, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 10026, + "value": 9832, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 10026, + "value": 9832, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 5508164, + "value": 5365759, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - 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"value": 69796, + "value": 69712, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,15 +20,15 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 6069, + "value": 6062, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 6069, + "value": 6062, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 200, + "value": 72, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 189, + "value": 174, "compare": "<=" }, "finish__timing__setup__ws": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 3035, + "value": 3031, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/sky130hd/gcd/rules-base.json b/flow/designs/sky130hd/gcd/rules-base.json index 3e70838254..2660611f36 100644 --- a/flow/designs/sky130hd/gcd/rules-base.json +++ b/flow/designs/sky130hd/gcd/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 481, + "value": 581, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,7 +20,7 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 65, + "value": 50, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 81, + "value": 72, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/sky130hd/ibex/rules-base.json b/flow/designs/sky130hd/ibex/rules-base.json index 19ca204614..956355b3f1 100644 --- a/flow/designs/sky130hd/ibex/rules-base.json +++ b/flow/designs/sky130hd/ibex/rules-base.json @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 64, + "value": 62, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 808993, + "value": 800712, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,15 +44,15 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 70, + "value": 64, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.45, + "value": -0.98, "compare": ">=" }, "finish__design__instance__area": { - "value": 205228, + "value": 204569, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -19.68, + "value": -16.91, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/sky130hd/jpeg/rules-base.json b/flow/designs/sky130hd/jpeg/rules-base.json index c6f18384b8..780a6ec5bd 100644 --- a/flow/designs/sky130hd/jpeg/rules-base.json +++ b/flow/designs/sky130hd/jpeg/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 268, + "value": 220, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.42, + "value": -0.25, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/sky130hd/microwatt/rules-base.json b/flow/designs/sky130hd/microwatt/rules-base.json index f01cf57848..dd410c50df 100644 --- a/flow/designs/sky130hd/microwatt/rules-base.json +++ b/flow/designs/sky130hd/microwatt/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 5627882, + "value": 5621142, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 3606, + "value": 933, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 10055574, + "value": 8866556, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -40,15 +40,15 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 6, + "value": 0, "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 3412, + "value": 1618, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -2.11, + "value": -1.96, "compare": ">=" }, "finish__design__instance__area": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -18.62, + "value": -17.68, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/sky130hd/riscv32i/rules-base.json b/flow/designs/sky130hd/riscv32i/rules-base.json index 6fc2d11613..38a3907180 100644 --- a/flow/designs/sky130hd/riscv32i/rules-base.json +++ b/flow/designs/sky130hd/riscv32i/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 70856.21, + "value": 70778.51, "compare": "<=" }, "constraints__clocks__count": { @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 83236, + "value": 82077, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 36, + "value": 21, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 309557, + "value": 303859, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,11 +48,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.36, + "value": -1.17, "compare": ">=" }, "finish__design__instance__area": { - "value": 103720, + "value": 95514, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -30.94, + "value": -28.53, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/sky130hs/aes/rules-base.json b/flow/designs/sky130hs/aes/rules-base.json index 2155ca377d..27ade127bb 100644 --- a/flow/designs/sky130hs/aes/rules-base.json +++ b/flow/designs/sky130hs/aes/rules-base.json @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 9, + "value": 182, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 737983, + "value": 722796, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 24, + "value": 54, "compare": "<=" }, "finish__timing__setup__ws": { @@ -52,7 +52,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 193310, + "value": 184400, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { diff --git a/flow/designs/sky130hs/gcd/rules-base.json b/flow/designs/sky130hs/gcd/rules-base.json index 6e33b6ad11..f8939b236d 100644 --- a/flow/designs/sky130hs/gcd/rules-base.json +++ b/flow/designs/sky130hs/gcd/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 5424, + "value": 5423, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 631, + "value": 622, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 55, + "value": 54, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 55, + "value": 54, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 10496, + "value": 12530, "compare": "<=" }, "detailedroute__route__drc_errors": { diff --git a/flow/designs/sky130hs/ibex/rules-base.json b/flow/designs/sky130hs/ibex/rules-base.json index 3e5c82bbc9..3ec988005c 100644 --- a/flow/designs/sky130hs/ibex/rules-base.json +++ b/flow/designs/sky130hs/ibex/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 261504, + "value": 259271, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 12, + "value": 45, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -44,11 +44,11 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 34, + "value": 22, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.34, + "value": -0.19, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/sky130hs/jpeg/rules-base.json b/flow/designs/sky130hs/jpeg/rules-base.json index ce7d4fa25d..06033c035a 100644 --- a/flow/designs/sky130hs/jpeg/rules-base.json +++ b/flow/designs/sky130hs/jpeg/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 749317, + "value": 723127, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 63909, + "value": 63375, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 5557, + "value": 5511, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 5557, + "value": 5511, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 712, + "value": 112, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 2481556, + "value": 1630300, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -40,11 +40,11 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 1, + "value": 0, "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 699, + "value": 66, "compare": "<=" }, "finish__timing__setup__ws": { @@ -52,11 +52,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 779230, + "value": 760037, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 2779, + "value": 2755, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/sky130hs/riscv32i/rules-base.json b/flow/designs/sky130hs/riscv32i/rules-base.json index c5fe338cb5..0b81614fcc 100644 --- a/flow/designs/sky130hs/riscv32i/rules-base.json +++ b/flow/designs/sky130hs/riscv32i/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 118571, + "value": 116710, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 7591, + "value": 7538, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 660, + "value": 656, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 660, + "value": 656, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 3, + "value": 26, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 378010, + "value": 369598, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 9, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { @@ -52,11 +52,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 141659, + "value": 134164, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 330, + "value": 328, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { From dda0b04ccf439d305f126c7c85e923c761388999 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Tue, 10 Jun 2025 15:51:21 -0700 Subject: [PATCH 044/198] Revert "platforms: asap7: Fixed set/reset signals for DFFASRHQNx1_ASAP7_75t_R" --- .../asap7/lib/CCS/asap7sc7p5t_SEQ_RVT_FF_ccs_220123.lib | 4 ++-- .../asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib | 4 ++-- .../asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib | 4 ++-- .../asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_TT_nldm_220123.lib | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/flow/platforms/asap7/lib/CCS/asap7sc7p5t_SEQ_RVT_FF_ccs_220123.lib b/flow/platforms/asap7/lib/CCS/asap7sc7p5t_SEQ_RVT_FF_ccs_220123.lib index cee7cfbb10..f9b44d302c 100644 --- a/flow/platforms/asap7/lib/CCS/asap7sc7p5t_SEQ_RVT_FF_ccs_220123.lib +++ b/flow/platforms/asap7/lib/CCS/asap7sc7p5t_SEQ_RVT_FF_ccs_220123.lib @@ -11588,13 +11588,13 @@ library (asap7sc7p5t_SEQ_RVT_FF_ccs_220123) { } } ff (IQN,IQNN) { - clear : "!RESETN"; + clear : "!SETN"; clear_preset_var1 : L; clear_preset_var2 : L; clocked_on : "CLK"; next_state : "!D"; power_down_function : "(!VDD) + (VSS)"; - preset : "!SETN"; + preset : "!RESETN"; } } cell (DFFHQNx1_ASAP7_75t_R) { diff --git a/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib b/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib index c785513677..f335d59f8b 100755 --- a/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib +++ b/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib @@ -2688,13 +2688,13 @@ library (asap7sc7p5t_SEQ_RVT_FF_nldm_220123) { } } ff (IQN,IQNN) { - clear : "!RESETN"; + clear : "!SETN"; clear_preset_var1 : L; clear_preset_var2 : L; clocked_on : "CLK"; next_state : "!D"; power_down_function : "(!VDD) + (VSS)"; - preset : "!SETN"; + preset : "!RESETN"; } } diff --git a/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib b/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib index 0db82e8bf2..a004888814 100755 --- a/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib +++ b/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib @@ -2688,13 +2688,13 @@ library (asap7sc7p5t_SEQ_RVT_SS_nldm_220123) { } } ff (IQN,IQNN) { - clear : "!RESETN"; + clear : "!SETN"; clear_preset_var1 : L; clear_preset_var2 : L; clocked_on : "CLK"; next_state : "!D"; power_down_function : "(!VDD) + (VSS)"; - preset : "!SETN"; + preset : "!RESETN"; } } diff --git a/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_TT_nldm_220123.lib b/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_TT_nldm_220123.lib index 20863d8381..a2a257c944 100755 --- a/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_TT_nldm_220123.lib +++ b/flow/platforms/asap7/lib/NLDM/asap7sc7p5t_SEQ_RVT_TT_nldm_220123.lib @@ -2688,13 +2688,13 @@ library (asap7sc7p5t_SEQ_RVT_TT_nldm_220123) { } } ff (IQN,IQNN) { - clear : "!RESETN"; + clear : "!SETN"; clear_preset_var1 : L; clear_preset_var2 : L; clocked_on : "CLK"; next_state : "!D"; power_down_function : "(!VDD) + (VSS)"; - preset : "!SETN"; + preset : "!RESETN"; } } From aa603fc1260f2a42e6e8b3ee960479781db4f82a Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Tue, 10 Jun 2025 15:57:37 -0700 Subject: [PATCH 045/198] Show pin shapes in save_images Signed-off-by: Matt Liberty --- flow/scripts/save_images.tcl | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/flow/scripts/save_images.tcl b/flow/scripts/save_images.tcl index d0f2bbeeea..67017a90f9 100644 --- a/flow/scripts/save_images.tcl +++ b/flow/scripts/save_images.tcl @@ -22,8 +22,9 @@ gui::set_display_controls "Layers/*" visible true gui::set_display_controls "Nets/*" visible true gui::set_display_controls "Instances/*" visible true gui::set_display_controls "Shape Types/*" visible true -gui::set_display_controls "Misc/Instances/*" visible true -gui::set_display_controls "Misc/Instances/Pin Names" visible false +gui::set_display_controls "Misc/Instances/*" visible false +gui::set_display_controls "Misc/Instances/Pins" visible true +gui::set_display_controls "Misc/Instances/Blockages" visible true gui::set_display_controls "Misc/Scale bar" visible true gui::set_display_controls "Misc/Highlight selected" visible true gui::set_display_controls "Misc/Detailed view" visible true @@ -35,8 +36,9 @@ gui::set_display_controls "Nets/Ground" visible false save_image -resolution $resolution $::env(REPORTS_DIR)/final_routing.webp # The placement view without routing -gui::set_display_controls "Layers/*" visible false +gui::set_display_controls "Shape Types/Routing/*" visible false gui::set_display_controls "Instances/Physical/*" visible false +gui::set_display_controls "Misc/Instances/*" visible false save_image -resolution $resolution $::env(REPORTS_DIR)/final_placement.webp if {[env_var_exists_and_non_empty PWR_NETS_VOLTAGES]} { @@ -48,14 +50,13 @@ if {[env_var_exists_and_non_empty PWR_NETS_VOLTAGES]} { } # The clock view: all clock nets and buffers -gui::set_display_controls "Layers/*" visible true +gui::set_display_controls "Shape Types/Routing/*" visible true gui::set_display_controls "Nets/*" visible false gui::set_display_controls "Nets/Clock" visible true gui::set_display_controls "Instances/*" visible false gui::set_display_controls "Instances/StdCells/Clock tree/*" visible true gui::set_display_controls "Instances/StdCells/Sequential" visible true gui::set_display_controls "Instances/Macro" visible true -gui::set_display_controls "Misc/Instances/*" visible false select -name "clk*" -type Inst save_image -resolution $resolution $::env(REPORTS_DIR)/final_clocks.webp gui::clear_selections @@ -74,7 +75,10 @@ foreach clock [get_clocks *] { gui::hide_widget "Clock Tree Viewer" # The resizer view: all instances created by the resizer grouped -gui::set_display_controls "Layers/*" visible false +gui::set_display_controls "Nets/*" visible true +gui::set_display_controls "Nets/Power" visible false +gui::set_display_controls "Nets/Ground" visible false +gui::set_display_controls "Shape Types/Routing/*" visible false gui::set_display_controls "Instances/*" visible true gui::set_display_controls "Instances/Physical/*" visible false select -name "hold*" -type Inst -highlight 0 ;# green From ad25dbedf5569cd1b1b6237100f83c2fdfdf6dfb Mon Sep 17 00:00:00 2001 From: arthurjolo Date: Wed, 11 Jun 2025 11:06:33 -0300 Subject: [PATCH 046/198] remove call to repair timing from cts.tcl Signed-off-by: arthurjolo --- flow/scripts/cts.tcl | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/flow/scripts/cts.tcl b/flow/scripts/cts.tcl index ab8e531229..5350eaa3eb 100644 --- a/flow/scripts/cts.tcl +++ b/flow/scripts/cts.tcl @@ -34,26 +34,10 @@ set_dont_use $::env(DONT_USE_CELLS) log_cmd clock_tree_synthesis {*}$cts_args -if {[env_var_equals CTS_SNAPSHOTS 1]} { - save_progress 4_1_pre_repair_clock_nets -} - -set_propagated_clock [all_clocks] - -utl::push_metrics_stage "cts__{}__pre_repair" - -estimate_parasitics -placement -if { $::env(DETAILED_METRICS) } { - report_metrics 4 "cts pre-repair" -} -utl::pop_metrics_stage - -repair_clock_nets - -utl::push_metrics_stage "cts__{}__post_repair" +utl::push_metrics_stage "cts__{}__pre_repair_timing" estimate_parasitics -placement if { $::env(DETAILED_METRICS) } { - report_metrics 4 "cts post-repair" + report_metrics 4 "cts pre-repair-timing" } utl::pop_metrics_stage From 78a1bb1d828038782bc427de5a4322b7456037b9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 11 Jun 2025 18:59:04 +0200 Subject: [PATCH 047/198] Pull updated OR branch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index 9f2a3e6b42..94bdb1b137 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 9f2a3e6b42440ce2357e44151f8749ad11c0067d +Subproject commit 94bdb1b137e080979dbcfa06d5cac05358975e81 From 26fc0f7390a5830b48f485275cd5b6e39a474979 Mon Sep 17 00:00:00 2001 From: arthurjolo Date: Wed, 11 Jun 2025 15:51:22 -0300 Subject: [PATCH 048/198] sync with OR master Signed-off-by: arthurjolo --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index 66559c8bcf..663c42b140 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 66559c8bcf6782e2f68ccf4a01a80ee8cc8c499e +Subproject commit 663c42b140b136003c556c8dc386d3e982e0b586 From 2d082ef1d3f7ca53b0c9d74b0d6bfa2c5b040346 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Wed, 11 Jun 2025 20:32:29 +0000 Subject: [PATCH 049/198] update OR Signed-off-by: Matt Liberty --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index 663c42b140..12f1f5da60 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 663c42b140b136003c556c8dc386d3e982e0b586 +Subproject commit 12f1f5da604b995b5b36a8f3b61618c583e191db From 60ee99fd00a3c9c2a6a47377fc0ab241c93fb1d3 Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Mon, 9 Jun 2025 20:50:52 -0700 Subject: [PATCH 050/198] switched asap7 cva6 from die/core area to utilization with margin fix for stray typo reduced util to 40 to get past GRT updated rules Signed-off-by: Jeff Ng --- flow/designs/asap7/cva6/config.mk | 6 +++--- flow/designs/asap7/cva6/rules-base.json | 16 ++++++++-------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/flow/designs/asap7/cva6/config.mk b/flow/designs/asap7/cva6/config.mk index 98fbc02499..255fb80ebf 100644 --- a/flow/designs/asap7/cva6/config.mk +++ b/flow/designs/asap7/cva6/config.mk @@ -79,10 +79,10 @@ export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_256x256.lib export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc -export DIE_AREA = 0 0 350 350 -export CORE_AREA = 1.08 1.08 340 340 +export CORE_UTILIZATION = 40 +export CORE_MARGIN = 2 +export MACRO_HALO = 5 export PLACE_DENSITY = 0.50 -export MACRO_HALO = 5 5 # a smoketest for this option, there are a # few last gasp iterations diff --git a/flow/designs/asap7/cva6/rules-base.json b/flow/designs/asap7/cva6/rules-base.json index 238d98daaa..7096cba6f1 100644 --- a/flow/designs/asap7/cva6/rules-base.json +++ b/flow/designs/asap7/cva6/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 40692.1, + "value": 40631.65, "compare": "<=" }, "constraints__clocks__count": { @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 164118, + "value": 163049, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 14271, + "value": 14178, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 14271, + "value": 14178, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1618999, + "value": 1884562, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -56,15 +56,15 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 7136, + "value": 7089, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 105, + "value": 101, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -20.43, + "value": -20.3, "compare": ">=" } } \ No newline at end of file From 074b1f7b5e79561d4e0197878c2b6db5e9116b98 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 12 Jun 2025 01:43:10 +0200 Subject: [PATCH 051/198] Update OR branch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index 94bdb1b137..8861232570 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 94bdb1b137e080979dbcfa06d5cac05358975e81 +Subproject commit 8861232570bb2c0c2184c9eaf07d1e7e734b796f From e6b0c991e0dc9b56672a44ed5981b1433d073147 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Wed, 11 Jun 2025 23:10:30 -0300 Subject: [PATCH 052/198] update documentation on metal layers for pin placement Signed-off-by: Eder Monteiro --- flow/scripts/variables.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 433085f635..7bfd250035 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -328,13 +328,13 @@ IO_CONSTRAINTS: - place IO_PLACER_H: description: > - The metal layer on which to place the I/O pins horizontally (top and bottom + A list of metal layers on which the I/O pins are placed horizontally (top and bottom of the die). stages: - place IO_PLACER_V: description: > - The metal layer on which to place the I/O pins vertically (sides of the + A list of metal layers on which the I/O pins are placed vertically (sides of the die). stages: - place From 0b4ef3882d2996693d1557cb4e9aeb83f6ea148a Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Wed, 11 Jun 2025 23:33:18 -0300 Subject: [PATCH 053/198] update public metrics Signed-off-by: Eder Monteiro --- flow/designs/ihp-sg13g2/ibex/rules-base.json | 4 ++-- flow/designs/sky130hd/microwatt/rules-base.json | 4 ++-- flow/designs/sky130hs/ibex/rules-base.json | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/flow/designs/ihp-sg13g2/ibex/rules-base.json b/flow/designs/ihp-sg13g2/ibex/rules-base.json index 8b520ea9ec..6cf5488019 100644 --- a/flow/designs/ihp-sg13g2/ibex/rules-base.json +++ b/flow/designs/ihp-sg13g2/ibex/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 0, + "value": 2, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 51, + "value": 32, "compare": "<=" }, "finish__timing__setup__ws": { diff --git a/flow/designs/sky130hd/microwatt/rules-base.json b/flow/designs/sky130hd/microwatt/rules-base.json index c9c30f9494..6edb6c679e 100644 --- a/flow/designs/sky130hd/microwatt/rules-base.json +++ b/flow/designs/sky130hd/microwatt/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 3606, + "value": 5426, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -40,7 +40,7 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 9, + "value": 0, "compare": "<=" }, "detailedroute__antenna_diodes_count": { diff --git a/flow/designs/sky130hs/ibex/rules-base.json b/flow/designs/sky130hs/ibex/rules-base.json index d55bd63edf..5491f62374 100644 --- a/flow/designs/sky130hs/ibex/rules-base.json +++ b/flow/designs/sky130hs/ibex/rules-base.json @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 12, + "value": 30, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 911447, + "value": 908310, "compare": "<=" }, "detailedroute__route__drc_errors": { From 97dc7be6dbc5447796112bc8a1a0b0a43bd7f8bb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Thu, 12 Jun 2025 08:37:12 +0200 Subject: [PATCH 054/198] makefile: minor cleanups MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Deleted duplicated code in variables.mk that must be in Makefile Signed-off-by: Øyvind Harboe --- flow/Makefile | 2 +- flow/scripts/variables.mk | 10 ---------- 2 files changed, 1 insertion(+), 11 deletions(-) diff --git a/flow/Makefile b/flow/Makefile index ff50e84654..a1f8e09e76 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -146,7 +146,7 @@ SHELL := /usr/bin/env bash # location # - default is current install / clone directory ifeq ($(origin FLOW_HOME), undefined) -FLOW_HOME := $(abspath $(dir $(firstword $(MAKEFILE_LIST)))) + FLOW_HOME := $(abspath $(dir $(firstword $(MAKEFILE_LIST)))) endif export FLOW_HOME diff --git a/flow/scripts/variables.mk b/flow/scripts/variables.mk index 8d0ae89cd4..75f5766f19 100644 --- a/flow/scripts/variables.mk +++ b/flow/scripts/variables.mk @@ -3,15 +3,6 @@ # lazy evaluation, conditional code, include statements, # etc. -# Setup variables to point to root / head of the OpenROAD directory -# - the following settings allowed user to point OpenROAD binaries to different -# location -# - default is current install / clone directory -ifeq ($(origin FLOW_HOME), undefined) -FLOW_HOME := $(abspath $(dir $(firstword $(MAKEFILE_LIST)))/..) -endif -export FLOW_HOME - export DESIGN_NICKNAME?=$(DESIGN_NAME) #------------------------------------------------------------------------------- @@ -21,7 +12,6 @@ export DESIGN_NICKNAME?=$(DESIGN_NAME) # - utils, scripts, test - default is under current directory export DESIGN_HOME ?= $(FLOW_HOME)/designs export PLATFORM_HOME ?= $(FLOW_HOME)/platforms -# WORK_HOME is set up in flow/Makefile export UTILS_DIR ?= $(FLOW_HOME)/util export SCRIPTS_DIR ?= $(FLOW_HOME)/scripts From 0e4b1011e73e0d4a42d668034fcb9b6430319f33 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Thu, 12 Jun 2025 10:15:57 -0300 Subject: [PATCH 055/198] use latest master Signed-off-by: Eder Monteiro --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index 663c42b140..341650e72d 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 663c42b140b136003c556c8dc386d3e982e0b586 +Subproject commit 341650e72dad0dc8571822ff8c5d9c5e365327f7 From 66f2c25ea42db107016cb44710169833580574a4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Thu, 12 Jun 2025 15:50:14 +0200 Subject: [PATCH 056/198] ihp-sg13g2: more consistent MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/platforms/ihp-sg13g2/config.mk | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/flow/platforms/ihp-sg13g2/config.mk b/flow/platforms/ihp-sg13g2/config.mk index 4f2440675c..74151881af 100644 --- a/flow/platforms/ihp-sg13g2/config.mk +++ b/flow/platforms/ihp-sg13g2/config.mk @@ -6,17 +6,17 @@ export PROCESS = ihp-sg13g2 # ---------------------------------------------------- # Add IO related files when a TCL script is assigned to 'FOOTPRINT_TCL'. # This variable is used to pass IO information. -export LOAD_ADDITIONAL_FILES ?= yes -ifdef FOOTPRINT_TCL -ifdef LOAD_ADDITIONAL_FILES - export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/sg13g2_io.lef \ - $(PLATFORM_DIR)/lef/bondpad_70x70.lef - export ADDITIONAL_SLOW_LIBS = $(ADDITIONAL_LIBS) $(PLATFORM_DIR)/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib - export ADDITIONAL_FAST_LIBS = $(ADDITIONAL_LIBS) $(PLATFORM_DIR)/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib - export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib - export ADDITIONAL_GDS += $(PLATFORM_DIR)/gds/sg13g2_io.gds \ - $(PLATFORM_DIR)/gds/bondpad_70x70.gds -endif +export LOAD_ADDITIONAL_FILES ?= 1 +ifneq ($(FOOTPRINT_TCL),) + ifeq ($(LOAD_ADDITIONAL_FILES),1) + export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/sg13g2_io.lef \ + $(PLATFORM_DIR)/lef/bondpad_70x70.lef + export ADDITIONAL_SLOW_LIBS = $(ADDITIONAL_LIBS) $(PLATFORM_DIR)/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib + export ADDITIONAL_FAST_LIBS = $(ADDITIONAL_LIBS) $(PLATFORM_DIR)/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib + export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib + export ADDITIONAL_GDS += $(PLATFORM_DIR)/gds/sg13g2_io.gds \ + $(PLATFORM_DIR)/gds/bondpad_70x70.gds + endif endif export TECH_LEF ?= $(PLATFORM_DIR)/lef/sg13g2_tech.lef export SC_LEF ?= $(PLATFORM_DIR)/lef/sg13g2_stdcell.lef From a52f068ee8ee7550584db6f8107e5fd2311e26e4 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Thu, 12 Jun 2025 16:12:43 +0000 Subject: [PATCH 057/198] update or Signed-off-by: Matt Liberty --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index 341650e72d..7bbccf752a 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 341650e72dad0dc8571822ff8c5d9c5e365327f7 +Subproject commit 7bbccf752ac80615a6759617be909479f25a1dcc From 053177a55f8453c286aaab1c402859362bca2f00 Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Thu, 12 Jun 2025 00:42:10 +0000 Subject: [PATCH 058/198] updated asap7 platform config.mk to support multi vt Signed-off-by: Jeff Ng --- flow/designs/asap7/jpeg_lvt/config.mk | 12 +- flow/platforms/asap7/config.mk | 143 +- .../asap7sc7p5t_AO_LVT_TT_201020.v | 3627 ++++++++++++ .../asap7sc7p5t_AO_SLVT_TT_201020.v | 3627 ++++++++++++ .../asap7sc7p5t_INVBUF_LVT_TT_201020.v | 663 +++ .../asap7sc7p5t_INVBUF_SLVT_TT_201020.v | 664 +++ .../asap7sc7p5t_OA_LVT_TT_201020.v | 5243 +++++++++++++++++ .../asap7sc7p5t_OA_SLVT_TT_201020.v | 5243 +++++++++++++++++ .../asap7sc7p5t_SEQ_LVT_TT_220101.v | 1173 ++++ .../asap7sc7p5t_SEQ_SLVT_TT_220101.v | 1173 ++++ .../asap7sc7p5t_SIMPLE_LVT_TT_201020.v | 1303 ++++ .../asap7sc7p5t_SIMPLE_SLVT_TT_201020.v | 1303 ++++ 12 files changed, 24104 insertions(+), 70 deletions(-) create mode 100644 flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_LVT_TT_201020.v create mode 100644 flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_SLVT_TT_201020.v create mode 100644 flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_LVT_TT_201020.v create mode 100644 flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_SLVT_TT_201020.v create mode 100644 flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_LVT_TT_201020.v create mode 100644 flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_SLVT_TT_201020.v create mode 100644 flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_LVT_TT_220101.v create mode 100644 flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_SLVT_TT_220101.v create mode 100644 flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_LVT_TT_201020.v create mode 100644 flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_SLVT_TT_201020.v diff --git a/flow/designs/asap7/jpeg_lvt/config.mk b/flow/designs/asap7/jpeg_lvt/config.mk index 975596c3a4..4b77c09e67 100644 --- a/flow/designs/asap7/jpeg_lvt/config.mk +++ b/flow/designs/asap7/jpeg_lvt/config.mk @@ -8,15 +8,6 @@ export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc export ABC_AREA = 1 -export ADDITIONAL_LIBS = $(LIB_DIR)/asap7sc7p5t_AO_LVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_LVT_FF_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_LVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_LVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_LVT_FF_nldm_220123.lib - -export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_L_220121a.gds -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/asap7sc7p5t_28_L_1x_220121a.lef - export CORE_UTILIZATION = 30 export CORE_ASPECT_RATIO = 1 export CORE_MARGIN = 2 @@ -25,3 +16,6 @@ export PLACE_DENSITY = 0.60 export TNS_END_PERCENT = 100 export RECOVER_POWER = 100 +export ASAP7_USE_VT = LVT + + diff --git a/flow/platforms/asap7/config.mk b/flow/platforms/asap7/config.mk index 7e89ec9638..2ecb360eb8 100644 --- a/flow/platforms/asap7/config.mk +++ b/flow/platforms/asap7/config.mk @@ -80,87 +80,91 @@ export KLAYOUT_DRC_FILE = $(PLATFORM_DIR)/drc/asap7.lydrc # OpenRCX extRules export RCX_RULES = $(PLATFORM_DIR)/rcx_patterns.rules -# XS - defining function for using LVT -ifeq ($(ASAP7_USE_VT), LVT) - export VT_TAG = L -else ifeq ($(ASAP7_USE_VT), SLVT) - export VT_TAG = SL -else - # Default to RVT - export VT_TAG = R -endif - +# PLACEHOLDER gets replaced with the appropriate VT tag in the following templates +export BC_NLDM_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_nldm_220123.lib +export BC_CCS_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_ccs_220123.lib +export WC_NLDM_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_SS_nldm_220123.lib +export TC_NLDM_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_TT_nldm_220123.lib +export BC_NLDM_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_FF_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_FF_nldm_220122.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_FF_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_FF_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_nldm_220123.lib +export BC_CCS_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_FF_ccs_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_FF_ccs_220122.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_FF_ccs_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_FF_ccs_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_ccs_220123.lib +export WC_NLDM_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_SS_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_SS_nldm_220122.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_SS_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_SS_nldm_220123.lib \ + $(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_SS_nldm_211120.lib.gz +export TC_NLDM_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_TT_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_TT_nldm_220122.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_TT_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_TT_nldm_220123.lib \ + $(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_TT_nldm_211120.lib.gz +export FILL_CELLS_T = FILLERxp5_ASAP7_75t_ \ + FILLER_ASAP7_75t_ \ + DECAPx1_ASAP7_75t_ \ + DECAPx2_ASAP7_75t_ \ + DECAPx4_ASAP7_75t_ \ + DECAPx6_ASAP7_75t_ \ + DECAPx10_ASAP7_75t_ + +# Default to RVT if unset +export VT_LIST = $(if $(strip $(ASAP7_USE_VT)), $(ASAP7_USE_VT), RVT) + +# # The first VT in the ASAP7_USE_VT list is the primary VT. The others get added to OTHER_VT +export PRIMARY_VT = $(word 1, $(VT_LIST)) +export PRIMARY_VT_TAG = $(strip $(patsubst %VT, %, $(PRIMARY_VT))) +export OTHER_VT = $(wordlist 2, $(words $(VT_LIST)), $(VT_LIST)) + +## Set cells based on the primary VT first # Set the TIEHI/TIELO cells # These are used in yosys synthesis to avoid logical 1/0's in the netlist -export TIEHI_CELL_AND_PORT ?= TIEHIx1_ASAP7_75t_$(VT_TAG) H -export TIELO_CELL_AND_PORT ?= TIELOx1_ASAP7_75t_$(VT_TAG) L +export TIEHI_CELL_AND_PORT ?= TIEHIx1_ASAP7_75t_$(PRIMARY_VT_TAG) H +export TIELO_CELL_AND_PORT ?= TIELOx1_ASAP7_75t_$(PRIMARY_VT_TAG) L # Used in synthesis -export MIN_BUF_CELL_AND_PORTS ?= BUFx2_ASAP7_75t_$(VT_TAG) A Y +export MIN_BUF_CELL_AND_PORTS ?= BUFx2_ASAP7_75t_$(PRIMARY_VT_TAG) A Y -export HOLD_BUF_CELL ?= BUFx2_ASAP7_75t_$(VT_TAG) +export HOLD_BUF_CELL ?= BUFx2_ASAP7_75t_$(PRIMARY_VT_TAG) -export ABC_DRIVER_CELL ?= BUFx2_ASAP7_75t_$(VT_TAG) +export ABC_DRIVER_CELL ?= BUFx2_ASAP7_75t_$(PRIMARY_VT_TAG) # Fill cells used in fill cell insertion -export FILL_CELLS ?= FILLERxp5_ASAP7_75t_$(VT_TAG) \ - FILLER_ASAP7_75t_$(VT_TAG) \ - DECAPx1_ASAP7_75t_$(VT_TAG) \ - DECAPx2_ASAP7_75t_$(VT_TAG) \ - DECAPx4_ASAP7_75t_$(VT_TAG) \ - DECAPx6_ASAP7_75t_$(VT_TAG) \ - DECAPx10_ASAP7_75t_$(VT_TAG) +export FILL_CELLS ?= $(addsuffix $(PRIMARY_VT_TAG), $(FILL_CELLS_T)) -export TAP_CELL_NAME ?= TAPCELL_ASAP7_75t_$(VT_TAG) +export TAP_CELL_NAME ?= TAPCELL_ASAP7_75t_$(PRIMARY_VT_TAG) # GDS_FILES has to be = vs. ?= because GDS_FILES gets set in the ORFS Makefile -export GDS_FILES = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_$(VT_TAG)_220121a.gds \ - $(ADDITIONAL_GDS) +export GDS_FILES = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_$(PRIMARY_VT_TAG)_220121a.gds -export SC_LEF ?= $(PLATFORM_DIR)/lef/asap7sc7p5t_28_$(VT_TAG)_1x_220121a.lef +export SC_LEF ?= $(PLATFORM_DIR)/lef/asap7sc7p5t_28_$(PRIMARY_VT_TAG)_1x_220121a.lef # Yosys mapping files -export LATCH_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_latch_$(VT_TAG).v -export CLKGATE_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_clkgate_$(VT_TAG).v -export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_adders_$(VT_TAG).v - -export BC_NLDM_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_nldm_220123.lib - -export BC_NLDM_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_FF_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_nldm_220123.lib - -export BC_CCS_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_FF_ccs_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_FF_ccs_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_FF_ccs_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_FF_ccs_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_ccs_220123.lib \ - $(BC_ADDITIONAL_LIBS) +export LATCH_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_latch_$(PRIMARY_VT_TAG).v +export CLKGATE_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_clkgate_$(PRIMARY_VT_TAG).v +export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_adders_$(PRIMARY_VT_TAG).v -export BC_CCS_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_ccs_220123.lib - -export WC_NLDM_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_SS_nldm_220123.lib - -export WC_NLDM_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_SS_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_SS_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_SS_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_SS_nldm_220123.lib \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_SS_nldm_211120.lib.gz +export BC_NLDM_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_NLDM_DFF_LIB_FILE_T)) +export BC_NLDM_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_NLDM_LIB_FILES_T)) +export BC_CCS_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_CCS_LIB_FILES_T)) \ + $(BC_ADDITIONAL_LIBS) +export BC_CCS_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_CCS_DFF_LIB_FILE_T)) -export TC_NLDM_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_TT_nldm_220123.lib +export WC_NLDM_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(WC_NLDM_DFF_LIB_FILE_T)) +export WC_NLDM_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(WC_NLDM_LIB_FILES_T)) -export TC_NLDM_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_TT_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_TT_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_TT_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_TT_nldm_220123.lib \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_TT_nldm_211120.lib.gz +export TC_NLDM_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(TC_NLDM_DFF_LIB_FILE_T)) +export TC_NLDM_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(TC_NLDM_LIB_FILES_T)) ifeq ($(CLUSTER_FLOPS),1) # Add the multi-bit FF for clustering. These are single corner libraries. - export ADDITIONAL_LIBS += $(LIB_DIR)/asap7sc7p5t_DFFHQNH2V2X_$(VT_TAG)VT_TT_nldm_FAKE.lib \ - $(LIB_DIR)/asap7sc7p5t_DFFHQNV2X_$(VT_TAG)VT_TT_nldm_FAKE.lib + export ADDITIONAL_LIBS += $(LIB_DIR)/asap7sc7p5t_DFFHQNH2V2X_$(PRIMARY_VT_TAG)VT_TT_nldm_FAKE.lib \ + $(LIB_DIR)/asap7sc7p5t_DFFHQNV2X_$(PRIMARY_VT_TAG)VT_TT_nldm_FAKE.lib export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/asap7sc7p5t_DFFHQNH2V2X.lef \ $(PLATFORM_DIR)/lef/asap7sc7p5t_DFFHQNV2X.lef @@ -168,6 +172,22 @@ ifeq ($(CLUSTER_FLOPS),1) export GDS_ALLOW_EMPTY ?= DFFHQN[VH][24].* endif +### Add additional files to the variables based on the OTHER_VT list +$(foreach vt_type,$(OTHER_VT),\ + $(eval OTHER_VT_TAG = $(strip $(patsubst %VT, %, $(vt_type)))) \ + $(eval ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/asap7sc7p5t_28_$(OTHER_VT_TAG)_1x_220121a.lef) \ + $(eval BC_NLDM_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_NLDM_DFF_LIB_FILE_T))) \ + $(eval BC_CCS_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_CCS_DFF_LIB_FILE_T))) \ + $(eval WC_NLDM_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(WC_NLDM_DFF_LIB_FILE_T))) \ + $(eval TC_NLDM_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(TC_NLDM_DFF_LIB_FILE_T))) \ + $(eval BC_NLDM_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_NLDM_LIB_FILES_T))) \ + $(eval BC_CCS_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_CCS_LIB_FILES_T))) \ + $(eval WC_NLDM_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(WC_NLDM_LIB_FILES_T))) \ + $(eval TC_NLDM_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(TC_NLDM_LIB_FILES_T))) \ + $(eval GDS_FILES += $(PLATFORM_DIR)/gds/asap7sc7p5t_28_$(OTHER_VT_TAG)_220121a.gds) \ + $(eval FILL_CELLS += $(addsuffix $(PRIMARY_VT_TAG), $(FILL_CELLS_T))) \ +) + # Dont use SC library based on CORNER selection # # BC - Best case, fastest @@ -176,6 +196,7 @@ endif export CORNER ?= BC export LIB_FILES += $($(CORNER)_$(LIB_MODEL)_LIB_FILES) export LIB_FILES += $(ADDITIONAL_LIBS) +export GDS_FILES += $(ADDITIONAL_GDS) export DB_FILES += $(realpath $($(CORNER)_DB_FILES)) export TEMPERATURE = $($(CORNER)_TEMPERATURE) export VOLTAGE = $($(CORNER)_VOLTAGE) diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_LVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_LVT_TT_201020.v new file mode 100644 index 0000000000..67002d6142 --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_LVT_TT_201020.v @@ -0,0 +1,3627 @@ +// BSD 3-Clause License +// +// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_AO_LVT_TT_201020 created by Liberate 18.1.0.293 on Sat Nov 28 03:36:02 MST 2020 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module A2O1A1Ixp33_ASAP7_75t_L (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar); + or (Y, int_fwire_1, int_fwire_0, C__bar); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module A2O1A1O1Ixp25_ASAP7_75t_L (Y, A1, A2, B, C, D); + output Y; + input A1, A2, B, C, D; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, D__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2; + + not (D__bar, D); + not (C__bar, C); + and (int_fwire_0, C__bar, D__bar); + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_1, A2__bar, B__bar, D__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B__bar, D__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO211x2_ASAP7_75t_L (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire int_fwire_0; + + and (int_fwire_0, A1, A2); + or (Y, int_fwire_0, B, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO21x1_ASAP7_75t_L (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire int_fwire_0; + + and (int_fwire_0, A1, A2); + or (Y, int_fwire_0, B); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO21x2_ASAP7_75t_L (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire int_fwire_0; + + and (int_fwire_0, A1, A2); + or (Y, int_fwire_0, B); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO221x1_ASAP7_75t_L (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2); + or (Y, int_fwire_1, int_fwire_0, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO221x2_ASAP7_75t_L (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2); + or (Y, int_fwire_1, int_fwire_0, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO222x2_ASAP7_75t_L (Y, A1, A2, B1, B2, C1, C2); + output Y; + input A1, A2, B1, B2, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2); + and (int_fwire_1, B1, B2); + and (int_fwire_2, A1, A2); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO22x1_ASAP7_75t_L (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2); + or (Y, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO22x2_ASAP7_75t_L (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2); + or (Y, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO31x2_ASAP7_75t_L (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire int_fwire_0; + + and (int_fwire_0, A1, A2, A3); + or (Y, int_fwire_0, B); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO322x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, C1, C2); + output Y; + input A1, A2, A3, B1, B2, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2); + and (int_fwire_1, B1, B2); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO32x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2); + output Y; + input A1, A2, A3, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO32x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2); + output Y; + input A1, A2, A3, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO331x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C); + output Y; + input A1, A2, A3, B1, B2, B3, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2, B3); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO331x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C); + output Y; + input A1, A2, A3, B1, B2, B3, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2, B3); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO332x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2); + and (int_fwire_1, B1, B2, B3); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO332x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2); + and (int_fwire_1, B1, B2, B3); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO333x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2, C3); + and (int_fwire_1, B1, B2, B3); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO333x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2, C3); + and (int_fwire_1, B1, B2, B3); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO33x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3); + output Y; + input A1, A2, A3, B1, B2, B3; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2, B3); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3) | (A2 & A3 & ~B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3) | (A1 & A3 & ~B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3) | (A1 & A2 & ~B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3) | (~A1 & ~A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3) | (~A1 & ~A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2) | (~A1 & ~A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI211x1_ASAP7_75t_L (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar, C__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~C)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI211xp5_ASAP7_75t_L (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar, C__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~C)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI21x1_ASAP7_75t_L (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0, int_fwire_1; + + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + if ((~A1 & ~A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI21xp33_ASAP7_75t_L (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0, int_fwire_1; + + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + if ((~A1 & ~A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI21xp5_ASAP7_75t_L (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0, int_fwire_1; + + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + if ((~A1 & ~A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI221x1_ASAP7_75t_L (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2, int_fwire_3; + + not (C__bar, C); + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar, C__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar, C__bar); + and (int_fwire_3, A1__bar, B1__bar, C__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & ~B2) | (~A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI221xp5_ASAP7_75t_L (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2, int_fwire_3; + + not (C__bar, C); + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar, C__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar, C__bar); + and (int_fwire_3, A1__bar, B1__bar, C__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI222xp33_ASAP7_75t_L (Y, A1, A2, B1, B2, C1, C2); + output Y; + input A1, A2, B1, B2, C1, C2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C1__bar, C2__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7; + + not (C2__bar, C2); + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar, C2__bar); + not (C1__bar, C1); + and (int_fwire_1, A2__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_2, A2__bar, B1__bar, C2__bar); + and (int_fwire_3, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_4, A1__bar, B2__bar, C2__bar); + and (int_fwire_5, A1__bar, B2__bar, C1__bar); + and (int_fwire_6, A1__bar, B1__bar, C2__bar); + and (int_fwire_7, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & B1 & ~B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & ~C1 & ~C2) | (A2 & ~B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & B1 & ~B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & ~C1 & ~C2) | (A1 & ~B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI22x1_ASAP7_75t_L (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3; + + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar); + and (int_fwire_3, A1__bar, B1__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI22xp33_ASAP7_75t_L (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3; + + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar); + and (int_fwire_3, A1__bar, B1__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI22xp5_ASAP7_75t_L (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3; + + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar); + and (int_fwire_3, A1__bar, B1__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI311xp33_ASAP7_75t_L (Y, A1, A2, A3, B, C); + output Y; + input A1, A2, A3, B, C; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, C__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2; + + not (C__bar, C); + not (B__bar, B); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B__bar, C__bar); + not (A2__bar, A2); + and (int_fwire_1, A2__bar, B__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B__bar, C__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & A3 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & A3 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3 & ~C) | (~A1 & ~A2 & A3 & ~C)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~C)) + (B => Y) = 0; + if ((A1 & A2 & ~A3 & ~B)) + (C => Y) = 0; + if ((A1 & ~A2 & A3 & ~B)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B) | (~A1 & ~A2 & A3 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI31xp33_ASAP7_75t_L (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2; + + not (B__bar, B); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B__bar); + not (A2__bar, A2); + and (int_fwire_1, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & ~A3)) + (B => Y) = 0; + if ((A1 & ~A2 & A3)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & A2 & A3)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3) | (~A1 & ~A2 & A3)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~A3)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI31xp67_ASAP7_75t_L (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2; + + not (B__bar, B); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B__bar); + not (A2__bar, A2); + and (int_fwire_1, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & ~A3)) + (B => Y) = 0; + if ((A1 & ~A2 & A3)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & A2 & A3)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3) | (~A1 & ~A2 & A3)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~A3)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI321xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, C); + output Y; + input A1, A2, A3, B1, B2, C; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, C__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + + not (C__bar, C); + not (B2__bar, B2); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B2__bar, C__bar); + not (B1__bar, B1); + and (int_fwire_1, A3__bar, B1__bar, C__bar); + not (A2__bar, A2); + and (int_fwire_2, A2__bar, B2__bar, C__bar); + and (int_fwire_3, A2__bar, B1__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_4, A1__bar, B2__bar, C__bar); + and (int_fwire_5, A1__bar, B1__bar, C__bar); + or (Y, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~C)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & ~C) | (~A1 & ~A2 & A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~C) | (~A1 & ~A2 & A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2) | (~A1 & ~A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2) | (~A1 & ~A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2) | (~A1 & ~A2 & A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI322xp5_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, C1, C2); + output Y; + input A1, A2, A3, B1, B2, C1, C2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, C1__bar; + wire C2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3, int_fwire_4; + wire int_fwire_5, int_fwire_6, int_fwire_7; + wire int_fwire_8, int_fwire_9, int_fwire_10; + wire int_fwire_11; + + not (C2__bar, C2); + not (B2__bar, B2); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B2__bar, C2__bar); + not (C1__bar, C1); + and (int_fwire_1, A3__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_2, A3__bar, B1__bar, C2__bar); + and (int_fwire_3, A3__bar, B1__bar, C1__bar); + not (A2__bar, A2); + and (int_fwire_4, A2__bar, B2__bar, C2__bar); + and (int_fwire_5, A2__bar, B2__bar, C1__bar); + and (int_fwire_6, A2__bar, B1__bar, C2__bar); + and (int_fwire_7, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_8, A1__bar, B2__bar, C2__bar); + and (int_fwire_9, A1__bar, B2__bar, C1__bar); + and (int_fwire_10, A1__bar, B1__bar, C2__bar); + and (int_fwire_11, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & ~C1 & C2) | (~A1 & ~A2 & A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI32xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2); + output Y; + input A1, A2, A3, B1, B2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2, int_fwire_3; + wire int_fwire_4, int_fwire_5; + + not (B2__bar, B2); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_1, A3__bar, B1__bar); + not (A2__bar, A2); + and (int_fwire_2, A2__bar, B2__bar); + and (int_fwire_3, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_4, A1__bar, B2__bar); + and (int_fwire_5, A1__bar, B1__bar); + or (Y, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & ~B2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2) | (~A1 & ~A2 & A3 & B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1) | (~A1 & ~A2 & A3 & B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI331xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1); + output Y; + input A1, A2, A3, B1, B2, B3, C1; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3, int_fwire_4; + wire int_fwire_5, int_fwire_6, int_fwire_7; + wire int_fwire_8; + + not (C1__bar, C1); + not (B3__bar, B3); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B3__bar, C1__bar); + not (B2__bar, B2); + and (int_fwire_1, A3__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_2, A3__bar, B1__bar, C1__bar); + not (A2__bar, A2); + and (int_fwire_3, A2__bar, B3__bar, C1__bar); + and (int_fwire_4, A2__bar, B2__bar, C1__bar); + and (int_fwire_5, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_6, A1__bar, B3__bar, C1__bar); + and (int_fwire_7, A1__bar, B2__bar, C1__bar); + and (int_fwire_8, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI332xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, C2__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2, int_fwire_3; + wire int_fwire_4, int_fwire_5, int_fwire_6; + wire int_fwire_7, int_fwire_8, int_fwire_9; + wire int_fwire_10, int_fwire_11, int_fwire_12; + wire int_fwire_13, int_fwire_14, int_fwire_15; + wire int_fwire_16, int_fwire_17; + + not (C2__bar, C2); + not (B3__bar, B3); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B3__bar, C2__bar); + not (C1__bar, C1); + and (int_fwire_1, A3__bar, B3__bar, C1__bar); + not (B2__bar, B2); + and (int_fwire_2, A3__bar, B2__bar, C2__bar); + and (int_fwire_3, A3__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_4, A3__bar, B1__bar, C2__bar); + and (int_fwire_5, A3__bar, B1__bar, C1__bar); + not (A2__bar, A2); + and (int_fwire_6, A2__bar, B3__bar, C2__bar); + and (int_fwire_7, A2__bar, B3__bar, C1__bar); + and (int_fwire_8, A2__bar, B2__bar, C2__bar); + and (int_fwire_9, A2__bar, B2__bar, C1__bar); + and (int_fwire_10, A2__bar, B1__bar, C2__bar); + and (int_fwire_11, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_12, A1__bar, B3__bar, C2__bar); + and (int_fwire_13, A1__bar, B3__bar, C1__bar); + and (int_fwire_14, A1__bar, B2__bar, C2__bar); + and (int_fwire_15, A1__bar, B2__bar, C1__bar); + and (int_fwire_16, A1__bar, B1__bar, C2__bar); + and (int_fwire_17, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI333xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, C2__bar, C3__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + wire int_fwire_18, int_fwire_19, int_fwire_20; + wire int_fwire_21, int_fwire_22, int_fwire_23; + wire int_fwire_24, int_fwire_25, int_fwire_26; + + not (C3__bar, C3); + not (B3__bar, B3); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B3__bar, C3__bar); + not (C2__bar, C2); + and (int_fwire_1, A3__bar, B3__bar, C2__bar); + not (C1__bar, C1); + and (int_fwire_2, A3__bar, B3__bar, C1__bar); + not (B2__bar, B2); + and (int_fwire_3, A3__bar, B2__bar, C3__bar); + and (int_fwire_4, A3__bar, B2__bar, C2__bar); + and (int_fwire_5, A3__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_6, A3__bar, B1__bar, C3__bar); + and (int_fwire_7, A3__bar, B1__bar, C2__bar); + and (int_fwire_8, A3__bar, B1__bar, C1__bar); + not (A2__bar, A2); + and (int_fwire_9, A2__bar, B3__bar, C3__bar); + and (int_fwire_10, A2__bar, B3__bar, C2__bar); + and (int_fwire_11, A2__bar, B3__bar, C1__bar); + and (int_fwire_12, A2__bar, B2__bar, C3__bar); + and (int_fwire_13, A2__bar, B2__bar, C2__bar); + and (int_fwire_14, A2__bar, B2__bar, C1__bar); + and (int_fwire_15, A2__bar, B1__bar, C3__bar); + and (int_fwire_16, A2__bar, B1__bar, C2__bar); + and (int_fwire_17, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_18, A1__bar, B3__bar, C3__bar); + and (int_fwire_19, A1__bar, B3__bar, C2__bar); + and (int_fwire_20, A1__bar, B3__bar, C1__bar); + and (int_fwire_21, A1__bar, B2__bar, C3__bar); + and (int_fwire_22, A1__bar, B2__bar, C2__bar); + and (int_fwire_23, A1__bar, B2__bar, C1__bar); + and (int_fwire_24, A1__bar, B1__bar, C3__bar); + and (int_fwire_25, A1__bar, B1__bar, C2__bar); + and (int_fwire_26, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI33xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3); + output Y; + input A1, A2, A3, B1, B2, B3; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + + not (B3__bar, B3); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B3__bar); + not (B2__bar, B2); + and (int_fwire_1, A3__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_2, A3__bar, B1__bar); + not (A2__bar, A2); + and (int_fwire_3, A2__bar, B3__bar); + and (int_fwire_4, A2__bar, B2__bar); + and (int_fwire_5, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_6, A1__bar, B3__bar); + and (int_fwire_7, A1__bar, B2__bar); + and (int_fwire_8, A1__bar, B1__bar); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3) | (A2 & A3 & ~B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3) | (A1 & A3 & ~B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3) | (A1 & A2 & ~B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3) | (~A1 & A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3) | (~A1 & A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2) | (~A1 & A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + endspecify +endmodule +`endcelldefine + diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_SLVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_SLVT_TT_201020.v new file mode 100644 index 0000000000..b33fb13e52 --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_SLVT_TT_201020.v @@ -0,0 +1,3627 @@ +// BSD 3-Clause License +// +// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_AO_SLVT_TT_201020 created by Liberate 18.1.0.293 on Sat Nov 28 03:36:02 MST 2020 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module A2O1A1Ixp33_ASAP7_75t_SL (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar); + or (Y, int_fwire_1, int_fwire_0, C__bar); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module A2O1A1O1Ixp25_ASAP7_75t_SL (Y, A1, A2, B, C, D); + output Y; + input A1, A2, B, C, D; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, D__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2; + + not (D__bar, D); + not (C__bar, C); + and (int_fwire_0, C__bar, D__bar); + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_1, A2__bar, B__bar, D__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B__bar, D__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO211x2_ASAP7_75t_SL (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire int_fwire_0; + + and (int_fwire_0, A1, A2); + or (Y, int_fwire_0, B, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO21x1_ASAP7_75t_SL (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire int_fwire_0; + + and (int_fwire_0, A1, A2); + or (Y, int_fwire_0, B); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO21x2_ASAP7_75t_SL (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire int_fwire_0; + + and (int_fwire_0, A1, A2); + or (Y, int_fwire_0, B); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO221x1_ASAP7_75t_SL (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2); + or (Y, int_fwire_1, int_fwire_0, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO221x2_ASAP7_75t_SL (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2); + or (Y, int_fwire_1, int_fwire_0, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO222x2_ASAP7_75t_SL (Y, A1, A2, B1, B2, C1, C2); + output Y; + input A1, A2, B1, B2, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2); + and (int_fwire_1, B1, B2); + and (int_fwire_2, A1, A2); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO22x1_ASAP7_75t_SL (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2); + or (Y, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO22x2_ASAP7_75t_SL (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2); + or (Y, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO31x2_ASAP7_75t_SL (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire int_fwire_0; + + and (int_fwire_0, A1, A2, A3); + or (Y, int_fwire_0, B); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO322x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, C1, C2); + output Y; + input A1, A2, A3, B1, B2, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2); + and (int_fwire_1, B1, B2); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO32x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2); + output Y; + input A1, A2, A3, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO32x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2); + output Y; + input A1, A2, A3, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO331x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C); + output Y; + input A1, A2, A3, B1, B2, B3, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2, B3); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO331x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C); + output Y; + input A1, A2, A3, B1, B2, B3, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2, B3); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0, C); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO332x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2); + and (int_fwire_1, B1, B2, B3); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO332x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2); + and (int_fwire_1, B1, B2, B3); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO333x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2, C3); + and (int_fwire_1, B1, B2, B3); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO333x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, C1, C2, C3); + and (int_fwire_1, B1, B2, B3); + and (int_fwire_2, A1, A2, A3); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AO33x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3); + output Y; + input A1, A2, A3, B1, B2, B3; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, B1, B2, B3); + and (int_fwire_1, A1, A2, A3); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3) | (A2 & A3 & ~B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3) | (A1 & A3 & ~B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3) | (A1 & A2 & ~B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3) | (~A1 & ~A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3) | (~A1 & ~A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2) | (~A1 & ~A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI211x1_ASAP7_75t_SL (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar, C__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~C)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI211xp5_ASAP7_75t_SL (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar, C__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~C)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI21x1_ASAP7_75t_SL (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0, int_fwire_1; + + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + if ((~A1 & ~A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI21xp33_ASAP7_75t_SL (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0, int_fwire_1; + + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + if ((~A1 & ~A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI21xp5_ASAP7_75t_SL (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0, int_fwire_1; + + not (B__bar, B); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + if ((~A1 & ~A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI221x1_ASAP7_75t_SL (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2, int_fwire_3; + + not (C__bar, C); + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar, C__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar, C__bar); + and (int_fwire_3, A1__bar, B1__bar, C__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & ~B2) | (~A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI221xp5_ASAP7_75t_SL (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2, int_fwire_3; + + not (C__bar, C); + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar, C__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar, C__bar); + and (int_fwire_3, A1__bar, B1__bar, C__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI222xp33_ASAP7_75t_SL (Y, A1, A2, B1, B2, C1, C2); + output Y; + input A1, A2, B1, B2, C1, C2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C1__bar, C2__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7; + + not (C2__bar, C2); + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar, C2__bar); + not (C1__bar, C1); + and (int_fwire_1, A2__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_2, A2__bar, B1__bar, C2__bar); + and (int_fwire_3, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_4, A1__bar, B2__bar, C2__bar); + and (int_fwire_5, A1__bar, B2__bar, C1__bar); + and (int_fwire_6, A1__bar, B1__bar, C2__bar); + and (int_fwire_7, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & B1 & ~B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2 & ~C1 & ~C2) | (A2 & ~B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & B1 & ~B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2 & ~C1 & ~C2) | (A1 & ~B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI22x1_ASAP7_75t_SL (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3; + + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar); + and (int_fwire_3, A1__bar, B1__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI22xp33_ASAP7_75t_SL (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3; + + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar); + and (int_fwire_3, A1__bar, B1__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI22xp5_ASAP7_75t_SL (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3; + + not (B2__bar, B2); + not (A2__bar, A2); + and (int_fwire_0, A2__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_1, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B2__bar); + and (int_fwire_3, A1__bar, B1__bar); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((A2 & ~B1 & ~B2)) + (A1 => Y) = 0; + if ((A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & ~B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI311xp33_ASAP7_75t_SL (Y, A1, A2, A3, B, C); + output Y; + input A1, A2, A3, B, C; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, C__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2; + + not (C__bar, C); + not (B__bar, B); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B__bar, C__bar); + not (A2__bar, A2); + and (int_fwire_1, A2__bar, B__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B__bar, C__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & A3 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & A3 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3 & ~C) | (~A1 & ~A2 & A3 & ~C)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~C)) + (B => Y) = 0; + if ((A1 & A2 & ~A3 & ~B)) + (C => Y) = 0; + if ((A1 & ~A2 & A3 & ~B)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B) | (~A1 & ~A2 & A3 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI31xp33_ASAP7_75t_SL (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2; + + not (B__bar, B); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B__bar); + not (A2__bar, A2); + and (int_fwire_1, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & ~A3)) + (B => Y) = 0; + if ((A1 & ~A2 & A3)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & A2 & A3)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3) | (~A1 & ~A2 & A3)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~A3)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI31xp67_ASAP7_75t_SL (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2; + + not (B__bar, B); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B__bar); + not (A2__bar, A2); + and (int_fwire_1, A2__bar, B__bar); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, B__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & ~A3)) + (B => Y) = 0; + if ((A1 & ~A2 & A3)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & A2 & A3)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3) | (~A1 & ~A2 & A3)) + (B => Y) = 0; + if ((~A1 & ~A2 & ~A3)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI321xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, C); + output Y; + input A1, A2, A3, B1, B2, C; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, C__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + + not (C__bar, C); + not (B2__bar, B2); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B2__bar, C__bar); + not (B1__bar, B1); + and (int_fwire_1, A3__bar, B1__bar, C__bar); + not (A2__bar, A2); + and (int_fwire_2, A2__bar, B2__bar, C__bar); + and (int_fwire_3, A2__bar, B1__bar, C__bar); + not (A1__bar, A1); + and (int_fwire_4, A1__bar, B2__bar, C__bar); + and (int_fwire_5, A1__bar, B1__bar, C__bar); + or (Y, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~C)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~C)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~C)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~C)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & ~C) | (~A1 & ~A2 & A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & ~C)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~C) | (~A1 & ~A2 & A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~C)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2) | (~A1 & ~A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2) | (~A1 & ~A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2) | (~A1 & ~A2 & A3 & ~B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI322xp5_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, C1, C2); + output Y; + input A1, A2, A3, B1, B2, C1, C2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, C1__bar; + wire C2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3, int_fwire_4; + wire int_fwire_5, int_fwire_6, int_fwire_7; + wire int_fwire_8, int_fwire_9, int_fwire_10; + wire int_fwire_11; + + not (C2__bar, C2); + not (B2__bar, B2); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B2__bar, C2__bar); + not (C1__bar, C1); + and (int_fwire_1, A3__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_2, A3__bar, B1__bar, C2__bar); + and (int_fwire_3, A3__bar, B1__bar, C1__bar); + not (A2__bar, A2); + and (int_fwire_4, A2__bar, B2__bar, C2__bar); + and (int_fwire_5, A2__bar, B2__bar, C1__bar); + and (int_fwire_6, A2__bar, B1__bar, C2__bar); + and (int_fwire_7, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_8, A1__bar, B2__bar, C2__bar); + and (int_fwire_9, A1__bar, B2__bar, C1__bar); + and (int_fwire_10, A1__bar, B1__bar, C2__bar); + and (int_fwire_11, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & ~C1 & C2) | (~A1 & ~A2 & A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI32xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2); + output Y; + input A1, A2, A3, B1, B2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2, int_fwire_3; + wire int_fwire_4, int_fwire_5; + + not (B2__bar, B2); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_1, A3__bar, B1__bar); + not (A2__bar, A2); + and (int_fwire_2, A2__bar, B2__bar); + and (int_fwire_3, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_4, A1__bar, B2__bar); + and (int_fwire_5, A1__bar, B1__bar); + or (Y, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & ~B2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2) | (~A1 & ~A2 & A3 & B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1) | (~A1 & ~A2 & A3 & B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI331xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1); + output Y; + input A1, A2, A3, B1, B2, B3, C1; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2, int_fwire_3, int_fwire_4; + wire int_fwire_5, int_fwire_6, int_fwire_7; + wire int_fwire_8; + + not (C1__bar, C1); + not (B3__bar, B3); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B3__bar, C1__bar); + not (B2__bar, B2); + and (int_fwire_1, A3__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_2, A3__bar, B1__bar, C1__bar); + not (A2__bar, A2); + and (int_fwire_3, A2__bar, B3__bar, C1__bar); + and (int_fwire_4, A2__bar, B2__bar, C1__bar); + and (int_fwire_5, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_6, A1__bar, B3__bar, C1__bar); + and (int_fwire_7, A1__bar, B2__bar, C1__bar); + and (int_fwire_8, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI332xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, C2__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2, int_fwire_3; + wire int_fwire_4, int_fwire_5, int_fwire_6; + wire int_fwire_7, int_fwire_8, int_fwire_9; + wire int_fwire_10, int_fwire_11, int_fwire_12; + wire int_fwire_13, int_fwire_14, int_fwire_15; + wire int_fwire_16, int_fwire_17; + + not (C2__bar, C2); + not (B3__bar, B3); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B3__bar, C2__bar); + not (C1__bar, C1); + and (int_fwire_1, A3__bar, B3__bar, C1__bar); + not (B2__bar, B2); + and (int_fwire_2, A3__bar, B2__bar, C2__bar); + and (int_fwire_3, A3__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_4, A3__bar, B1__bar, C2__bar); + and (int_fwire_5, A3__bar, B1__bar, C1__bar); + not (A2__bar, A2); + and (int_fwire_6, A2__bar, B3__bar, C2__bar); + and (int_fwire_7, A2__bar, B3__bar, C1__bar); + and (int_fwire_8, A2__bar, B2__bar, C2__bar); + and (int_fwire_9, A2__bar, B2__bar, C1__bar); + and (int_fwire_10, A2__bar, B1__bar, C2__bar); + and (int_fwire_11, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_12, A1__bar, B3__bar, C2__bar); + and (int_fwire_13, A1__bar, B3__bar, C1__bar); + and (int_fwire_14, A1__bar, B2__bar, C2__bar); + and (int_fwire_15, A1__bar, B2__bar, C1__bar); + and (int_fwire_16, A1__bar, B1__bar, C2__bar); + and (int_fwire_17, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI333xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, C2__bar, C3__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + wire int_fwire_18, int_fwire_19, int_fwire_20; + wire int_fwire_21, int_fwire_22, int_fwire_23; + wire int_fwire_24, int_fwire_25, int_fwire_26; + + not (C3__bar, C3); + not (B3__bar, B3); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B3__bar, C3__bar); + not (C2__bar, C2); + and (int_fwire_1, A3__bar, B3__bar, C2__bar); + not (C1__bar, C1); + and (int_fwire_2, A3__bar, B3__bar, C1__bar); + not (B2__bar, B2); + and (int_fwire_3, A3__bar, B2__bar, C3__bar); + and (int_fwire_4, A3__bar, B2__bar, C2__bar); + and (int_fwire_5, A3__bar, B2__bar, C1__bar); + not (B1__bar, B1); + and (int_fwire_6, A3__bar, B1__bar, C3__bar); + and (int_fwire_7, A3__bar, B1__bar, C2__bar); + and (int_fwire_8, A3__bar, B1__bar, C1__bar); + not (A2__bar, A2); + and (int_fwire_9, A2__bar, B3__bar, C3__bar); + and (int_fwire_10, A2__bar, B3__bar, C2__bar); + and (int_fwire_11, A2__bar, B3__bar, C1__bar); + and (int_fwire_12, A2__bar, B2__bar, C3__bar); + and (int_fwire_13, A2__bar, B2__bar, C2__bar); + and (int_fwire_14, A2__bar, B2__bar, C1__bar); + and (int_fwire_15, A2__bar, B1__bar, C3__bar); + and (int_fwire_16, A2__bar, B1__bar, C2__bar); + and (int_fwire_17, A2__bar, B1__bar, C1__bar); + not (A1__bar, A1); + and (int_fwire_18, A1__bar, B3__bar, C3__bar); + and (int_fwire_19, A1__bar, B3__bar, C2__bar); + and (int_fwire_20, A1__bar, B3__bar, C1__bar); + and (int_fwire_21, A1__bar, B2__bar, C3__bar); + and (int_fwire_22, A1__bar, B2__bar, C2__bar); + and (int_fwire_23, A1__bar, B2__bar, C1__bar); + and (int_fwire_24, A1__bar, B1__bar, C3__bar); + and (int_fwire_25, A1__bar, B1__bar, C2__bar); + and (int_fwire_26, A1__bar, B1__bar, C1__bar); + or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AOI33xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3); + output Y; + input A1, A2, A3, B1, B2, B3; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + + not (B3__bar, B3); + not (A3__bar, A3); + and (int_fwire_0, A3__bar, B3__bar); + not (B2__bar, B2); + and (int_fwire_1, A3__bar, B2__bar); + not (B1__bar, B1); + and (int_fwire_2, A3__bar, B1__bar); + not (A2__bar, A2); + and (int_fwire_3, A2__bar, B3__bar); + and (int_fwire_4, A2__bar, B2__bar); + and (int_fwire_5, A2__bar, B1__bar); + not (A1__bar, A1); + and (int_fwire_6, A1__bar, B3__bar); + and (int_fwire_7, A1__bar, B2__bar); + and (int_fwire_8, A1__bar, B1__bar); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((A2 & A3 & B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & B2 & ~B3) | (A2 & A3 & ~B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((A2 & A3 & ~B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((A1 & A3 & B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & B2 & ~B3) | (A1 & A3 & ~B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((A1 & A3 & ~B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~B3) | (A1 & A2 & ~B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((A1 & A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B2 & B3) | (~A1 & A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B2 & B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B2 & B3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B3) | (~A1 & A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2) | (~A1 & A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & ~A3 & B1 & B2)) + (B3 => Y) = 0; + endspecify +endmodule +`endcelldefine + diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_LVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_LVT_TT_201020.v new file mode 100644 index 0000000000..8d929214e2 --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_LVT_TT_201020.v @@ -0,0 +1,663 @@ +// BSD 3-Clause License +// +// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_INVBUF_LVT_TT_201020 created by Liberate 18.1.0.293 on Mon Dec 7 13:57:05 MST 2020 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx10_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx12_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx12f_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx16f_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx24_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx2_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx3_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx4_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx4f_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx5_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx6f_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx8_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx10_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx11_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx12_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx14_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx16_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx20_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx5p33_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx6p67_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx8_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx9p33_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HB1xp67_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HB2xp67_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HB3xp67_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HB4xp67_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx11_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx13_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx1_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx2_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx3_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx4_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx5_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx6_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx8_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVxp33_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVxp67_ASAP7_75t_L (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + + diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_SLVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_SLVT_TT_201020.v new file mode 100644 index 0000000000..7a29306535 --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_SLVT_TT_201020.v @@ -0,0 +1,664 @@ +// BSD 3-Clause License +// +// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_INVBUF_SLVT_TT_201020 created by Liberate 18.1.0.293 on Mon Dec 7 13:57:05 MST 2020 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx10_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx12_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx12f_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx16f_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx24_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx2_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx3_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx4_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx4f_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx5_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx6f_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module BUFx8_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx10_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx11_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx12_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx14_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx16_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx20_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx5p33_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx6p67_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx8_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module CKINVDCx9p33_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HB1xp67_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HB2xp67_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HB3xp67_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HB4xp67_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + buf (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx11_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx13_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx1_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx2_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx3_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx4_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx5_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx6_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVx8_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVxp33_ASAP7_75t_SL (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module INVxp67_ASAP7_75t_SL + (Y, A); + output Y; + input A; + + // Function + not (Y, A); + + // Timing + specify + (A => Y) = 0; + endspecify +endmodule +`endcelldefine + + diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_LVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_LVT_TT_201020.v new file mode 100644 index 0000000000..65fc6836e8 --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_LVT_TT_201020.v @@ -0,0 +1,5243 @@ +// BSD 3-Clause License +// +// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_OA_LVT_TT_201020 created by Liberate 18.1.0.293 on Sat Nov 28 13:55:21 MST 2020 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module O2A1O1Ixp33_ASAP7_75t_L (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + and (int_fwire_0, B__bar, C__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, C__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~C)) + (B => Y) = 0; + if ((A1 & A2 & ~B)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module O2A1O1Ixp5_ASAP7_75t_L (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + and (int_fwire_0, B__bar, C__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, C__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~C)) + (B => Y) = 0; + if ((A2 & ~B)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA211x2_ASAP7_75t_L (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, A2, B, C); + and (int_fwire_1, A1, B, C); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2 & C)) + (B => Y) = 0; + if ((A1 & ~A2 & C)) + (B => Y) = 0; + if ((~A1 & A2 & C)) + (B => Y) = 0; + if ((A1 & A2 & B)) + (C => Y) = 0; + if ((A1 & ~A2 & B)) + (C => Y) = 0; + if ((~A1 & A2 & B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA21x2_ASAP7_75t_L (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, A2, B); + and (int_fwire_1, A1, B); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2)) + (B => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA221x2_ASAP7_75t_L (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3; + + and (int_fwire_0, A2, B2, C); + and (int_fwire_1, A2, B1, C); + and (int_fwire_2, A1, B2, C); + and (int_fwire_3, A1, B1, C); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & C)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2 & C)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & ~B1 & B2) | (~A1 & A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA222x2_ASAP7_75t_L (Y, A1, A2, B1, B2, C1, C2); + output Y; + input A1, A2, B1, B2, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7; + + and (int_fwire_0, A2, B2, C2); + and (int_fwire_1, A2, B2, C1); + and (int_fwire_2, A2, B1, C2); + and (int_fwire_3, A2, B1, C1); + and (int_fwire_4, A1, B2, C2); + and (int_fwire_5, A1, B2, C1); + and (int_fwire_6, A1, B1, C2); + and (int_fwire_7, A1, B1, C1); + or (Y, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & B2 & C1 & ~C2) | (~A2 & B1 & ~B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & B2 & C1 & ~C2) | (~A1 & B1 & ~B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA22x2_ASAP7_75t_L (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3; + + and (int_fwire_0, A2, B2); + and (int_fwire_1, A2, B1); + and (int_fwire_2, A1, B2); + and (int_fwire_3, A1, B1); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA31x2_ASAP7_75t_L (Y, A1, A2, A3, B1); + output Y; + input A1, A2, A3, B1; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, A3, B1); + and (int_fwire_1, A2, B1); + and (int_fwire_2, A1, B1); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & A3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3) | (~A1 & A2 & A3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3)) + (B1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA331x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1); + output Y; + input A1, A2, A3, B1, B2, B3, C1; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + + and (int_fwire_0, A3, B3, C1); + and (int_fwire_1, A3, B2, C1); + and (int_fwire_2, A3, B1, C1); + and (int_fwire_3, A2, B3, C1); + and (int_fwire_4, A2, B2, C1); + and (int_fwire_5, A2, B1, C1); + and (int_fwire_6, A1, B3, C1); + and (int_fwire_7, A1, B2, C1); + and (int_fwire_8, A1, B1, C1); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA331x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1); + output Y; + input A1, A2, A3, B1, B2, B3, C1; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + + and (int_fwire_0, A3, B3, C1); + and (int_fwire_1, A3, B2, C1); + and (int_fwire_2, A3, B1, C1); + and (int_fwire_3, A2, B3, C1); + and (int_fwire_4, A2, B2, C1); + and (int_fwire_5, A2, B1, C1); + and (int_fwire_6, A1, B3, C1); + and (int_fwire_7, A1, B2, C1); + and (int_fwire_8, A1, B1, C1); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA332x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + + and (int_fwire_0, A3, B3, C2); + and (int_fwire_1, A3, B3, C1); + and (int_fwire_2, A3, B2, C2); + and (int_fwire_3, A3, B2, C1); + and (int_fwire_4, A3, B1, C2); + and (int_fwire_5, A3, B1, C1); + and (int_fwire_6, A2, B3, C2); + and (int_fwire_7, A2, B3, C1); + and (int_fwire_8, A2, B2, C2); + and (int_fwire_9, A2, B2, C1); + and (int_fwire_10, A2, B1, C2); + and (int_fwire_11, A2, B1, C1); + and (int_fwire_12, A1, B3, C2); + and (int_fwire_13, A1, B3, C1); + and (int_fwire_14, A1, B2, C2); + and (int_fwire_15, A1, B2, C1); + and (int_fwire_16, A1, B1, C2); + and (int_fwire_17, A1, B1, C1); + or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA332x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + + and (int_fwire_0, A3, B3, C2); + and (int_fwire_1, A3, B3, C1); + and (int_fwire_2, A3, B2, C2); + and (int_fwire_3, A3, B2, C1); + and (int_fwire_4, A3, B1, C2); + and (int_fwire_5, A3, B1, C1); + and (int_fwire_6, A2, B3, C2); + and (int_fwire_7, A2, B3, C1); + and (int_fwire_8, A2, B2, C2); + and (int_fwire_9, A2, B2, C1); + and (int_fwire_10, A2, B1, C2); + and (int_fwire_11, A2, B1, C1); + and (int_fwire_12, A1, B3, C2); + and (int_fwire_13, A1, B3, C1); + and (int_fwire_14, A1, B2, C2); + and (int_fwire_15, A1, B2, C1); + and (int_fwire_16, A1, B1, C2); + and (int_fwire_17, A1, B1, C1); + or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA333x1_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + wire int_fwire_18, int_fwire_19, int_fwire_20; + wire int_fwire_21, int_fwire_22, int_fwire_23; + wire int_fwire_24, int_fwire_25, int_fwire_26; + + and (int_fwire_0, A3, B3, C3); + and (int_fwire_1, A3, B3, C2); + and (int_fwire_2, A3, B3, C1); + and (int_fwire_3, A3, B2, C3); + and (int_fwire_4, A3, B2, C2); + and (int_fwire_5, A3, B2, C1); + and (int_fwire_6, A3, B1, C3); + and (int_fwire_7, A3, B1, C2); + and (int_fwire_8, A3, B1, C1); + and (int_fwire_9, A2, B3, C3); + and (int_fwire_10, A2, B3, C2); + and (int_fwire_11, A2, B3, C1); + and (int_fwire_12, A2, B2, C3); + and (int_fwire_13, A2, B2, C2); + and (int_fwire_14, A2, B2, C1); + and (int_fwire_15, A2, B1, C3); + and (int_fwire_16, A2, B1, C2); + and (int_fwire_17, A2, B1, C1); + and (int_fwire_18, A1, B3, C3); + and (int_fwire_19, A1, B3, C2); + and (int_fwire_20, A1, B3, C1); + and (int_fwire_21, A1, B2, C3); + and (int_fwire_22, A1, B2, C2); + and (int_fwire_23, A1, B2, C1); + and (int_fwire_24, A1, B1, C3); + and (int_fwire_25, A1, B1, C2); + and (int_fwire_26, A1, B1, C1); + or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA333x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + wire int_fwire_18, int_fwire_19, int_fwire_20; + wire int_fwire_21, int_fwire_22, int_fwire_23; + wire int_fwire_24, int_fwire_25, int_fwire_26; + + and (int_fwire_0, A3, B3, C3); + and (int_fwire_1, A3, B3, C2); + and (int_fwire_2, A3, B3, C1); + and (int_fwire_3, A3, B2, C3); + and (int_fwire_4, A3, B2, C2); + and (int_fwire_5, A3, B2, C1); + and (int_fwire_6, A3, B1, C3); + and (int_fwire_7, A3, B1, C2); + and (int_fwire_8, A3, B1, C1); + and (int_fwire_9, A2, B3, C3); + and (int_fwire_10, A2, B3, C2); + and (int_fwire_11, A2, B3, C1); + and (int_fwire_12, A2, B2, C3); + and (int_fwire_13, A2, B2, C2); + and (int_fwire_14, A2, B2, C1); + and (int_fwire_15, A2, B1, C3); + and (int_fwire_16, A2, B1, C2); + and (int_fwire_17, A2, B1, C1); + and (int_fwire_18, A1, B3, C3); + and (int_fwire_19, A1, B3, C2); + and (int_fwire_20, A1, B3, C1); + and (int_fwire_21, A1, B2, C3); + and (int_fwire_22, A1, B2, C2); + and (int_fwire_23, A1, B2, C1); + and (int_fwire_24, A1, B1, C3); + and (int_fwire_25, A1, B1, C2); + and (int_fwire_26, A1, B1, C1); + or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA33x2_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3); + output Y; + input A1, A2, A3, B1, B2, B3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + + and (int_fwire_0, A3, B3); + and (int_fwire_1, A3, B2); + and (int_fwire_2, A3, B1); + and (int_fwire_3, A2, B3); + and (int_fwire_4, A2, B2); + and (int_fwire_5, A2, B1); + and (int_fwire_6, A1, B3); + and (int_fwire_7, A1, B2); + and (int_fwire_8, A1, B1); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & B3) | (~A2 & ~A3 & ~B1 & B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & B3) | (~A1 & ~A3 & ~B1 & B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & B3) | (~A1 & ~A2 & ~B1 & B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B2 & ~B3) | (~A1 & A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2) | (~A1 & A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI211xp5_ASAP7_75t_L (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0; + + not (C__bar, C); + not (B__bar, B); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar); + or (Y, int_fwire_0, B__bar, C__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2 & C)) + (B => Y) = 0; + if ((A1 & ~A2 & C)) + (B => Y) = 0; + if ((~A1 & A2 & C)) + (B => Y) = 0; + if ((A1 & A2 & B)) + (C => Y) = 0; + if ((A1 & ~A2 & B)) + (C => Y) = 0; + if ((~A1 & A2 & B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI21x1_ASAP7_75t_L (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0; + + not (B__bar, B); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2)) + (B => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI21xp33_ASAP7_75t_L (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0; + + not (B__bar, B); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2)) + (B => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI21xp5_ASAP7_75t_L (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0; + + not (B__bar, B); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2)) + (B => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI221xp5_ASAP7_75t_L (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C__bar, int_fwire_0; + wire int_fwire_1; + + not (C__bar, C); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar); + or (Y, int_fwire_1, int_fwire_0, C__bar); + + // Timing + specify + if ((~A2 & B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & C)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2 & C)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI222xp33_ASAP7_75t_L (Y, A1, A2, B1, B2, C1, C2); + output Y; + input A1, A2, B1, B2, C1, C2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C1__bar, C2__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + + not (C2__bar, C2); + not (C1__bar, C1); + and (int_fwire_0, C1__bar, C2__bar); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_1, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, A2__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & B2 & C1 & ~C2) | (~A2 & B1 & ~B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & B2 & C1 & ~C2) | (~A1 & B1 & ~B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI22x1_ASAP7_75t_L (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI22xp33_ASAP7_75t_L (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI22xp5_ASAP7_75t_L (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI311xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, C1); + output Y; + input A1, A2, A3, B1, C1; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, C1__bar, int_fwire_0; + + not (C1__bar, C1); + not (B1__bar, B1); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_0, B1__bar, C1__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & A3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & C1) | (A1 & ~A2 & A3 & C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & B1)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1) | (A1 & ~A2 & A3 & B1)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI31xp33_ASAP7_75t_L (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, int_fwire_0; + + not (B__bar, B); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & A3)) + (B => Y) = 0; + if ((A1 & A2 & ~A3) | (A1 & ~A2 & A3)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & A2 & A3)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & ~A2 & A3)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI31xp67_ASAP7_75t_L (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, int_fwire_0; + + not (B__bar, B); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & A3)) + (B => Y) = 0; + if ((A1 & A2 & ~A3) | (A1 & ~A2 & A3)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & A2 & A3)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & ~A2 & A3)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI321xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, C); + output Y; + input A1, A2, A3, B1, B2, C; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, C__bar; + wire int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_1, int_fwire_0, C__bar); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & C)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & C)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & C) | (A1 & ~A2 & A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & C) | (A1 & ~A2 & A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2) | (A1 & ~A2 & A3 & B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2) | (A1 & ~A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2) | (A1 & ~A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI322xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, C1, C2); + output Y; + input A1, A2, A3, B1, B2, C1, C2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, C1__bar; + wire C2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2; + + not (C2__bar, C2); + not (C1__bar, C1); + and (int_fwire_0, C1__bar, C2__bar); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_1, B1__bar, B2__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI32xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2); + output Y; + input A1, A2, A3, B1, B2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, int_fwire_0; + wire int_fwire_1; + + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2) | (A1 & ~A2 & A3 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1) | (A1 & ~A2 & A3 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI331xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1); + output Y; + input A1, A2, A3, B1, B2, B3, C1; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, int_fwire_0, int_fwire_1; + + not (C1__bar, C1); + not (B3__bar, B3); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar, B3__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_1, int_fwire_0, C1__bar); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI332xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, C2__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2; + + not (C2__bar, C2); + not (C1__bar, C1); + and (int_fwire_0, C1__bar, C2__bar); + not (B3__bar, B3); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_1, B1__bar, B2__bar, B3__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI333xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, C2__bar, C3__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + + not (C3__bar, C3); + not (C2__bar, C2); + not (C1__bar, C1); + and (int_fwire_0, C1__bar, C2__bar, C3__bar); + not (B3__bar, B3); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_1, B1__bar, B2__bar, B3__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI33xp33_ASAP7_75t_L (Y, A1, A2, A3, B1, B2, B3); + output Y; + input A1, A2, A3, B1, B2, B3; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire int_fwire_0, int_fwire_1; + + not (B3__bar, B3); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar, B3__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3) | (~A2 & ~A3 & B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3) | (~A1 & ~A3 & B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3) | (~A1 & ~A2 & B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B2 & ~B3) | (~A1 & A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2) | (~A1 & A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + endspecify +endmodule +`endcelldefine diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_SLVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_SLVT_TT_201020.v new file mode 100644 index 0000000000..c737d3b31c --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_SLVT_TT_201020.v @@ -0,0 +1,5243 @@ +// BSD 3-Clause License +// +// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_OA_SLVT_TT_201020 created by Liberate 18.1.0.293 on Sat Nov 28 13:55:21 MST 2020 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module O2A1O1Ixp33_ASAP7_75t_SL (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + and (int_fwire_0, B__bar, C__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, C__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~C)) + (B => Y) = 0; + if ((A1 & A2 & ~B)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B)) + (C => Y) = 0; + if ((~A1 & A2 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module O2A1O1Ixp5_ASAP7_75t_SL (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B__bar, B); + and (int_fwire_0, B__bar, C__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, C__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2 & ~C)) + (B => Y) = 0; + if ((A1 & ~A2 & ~C)) + (B => Y) = 0; + if ((~A1 & A2 & ~C)) + (B => Y) = 0; + if ((A2 & ~B)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B)) + (C => Y) = 0; + if ((~A1 & ~A2 & B)) + (C => Y) = 0; + if ((~A1 & ~A2 & ~B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA211x2_ASAP7_75t_SL (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, A2, B, C); + and (int_fwire_1, A1, B, C); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2 & C)) + (B => Y) = 0; + if ((A1 & ~A2 & C)) + (B => Y) = 0; + if ((~A1 & A2 & C)) + (B => Y) = 0; + if ((A1 & A2 & B)) + (C => Y) = 0; + if ((A1 & ~A2 & B)) + (C => Y) = 0; + if ((~A1 & A2 & B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA21x2_ASAP7_75t_SL (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire int_fwire_0, int_fwire_1; + + and (int_fwire_0, A2, B); + and (int_fwire_1, A1, B); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2)) + (B => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA221x2_ASAP7_75t_SL (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3; + + and (int_fwire_0, A2, B2, C); + and (int_fwire_1, A2, B1, C); + and (int_fwire_2, A1, B2, C); + and (int_fwire_3, A1, B1, C); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & C)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2 & C)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & ~B1 & B2) | (~A1 & A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA222x2_ASAP7_75t_SL (Y, A1, A2, B1, B2, C1, C2); + output Y; + input A1, A2, B1, B2, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7; + + and (int_fwire_0, A2, B2, C2); + and (int_fwire_1, A2, B2, C1); + and (int_fwire_2, A2, B1, C2); + and (int_fwire_3, A2, B1, C1); + and (int_fwire_4, A1, B2, C2); + and (int_fwire_5, A1, B2, C1); + and (int_fwire_6, A1, B1, C2); + and (int_fwire_7, A1, B1, C1); + or (Y, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & B2 & C1 & ~C2) | (~A2 & B1 & ~B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & B2 & C1 & ~C2) | (~A1 & B1 & ~B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA22x2_ASAP7_75t_SL (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3; + + and (int_fwire_0, A2, B2); + and (int_fwire_1, A2, B1); + and (int_fwire_2, A1, B2); + and (int_fwire_3, A1, B1); + or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA31x2_ASAP7_75t_SL (Y, A1, A2, A3, B1); + output Y; + input A1, A2, A3, B1; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, A3, B1); + and (int_fwire_1, A2, B1); + and (int_fwire_2, A1, B1); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & A3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3) | (~A1 & A2 & A3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3)) + (B1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA331x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1); + output Y; + input A1, A2, A3, B1, B2, B3, C1; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + + and (int_fwire_0, A3, B3, C1); + and (int_fwire_1, A3, B2, C1); + and (int_fwire_2, A3, B1, C1); + and (int_fwire_3, A2, B3, C1); + and (int_fwire_4, A2, B2, C1); + and (int_fwire_5, A2, B1, C1); + and (int_fwire_6, A1, B3, C1); + and (int_fwire_7, A1, B2, C1); + and (int_fwire_8, A1, B1, C1); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA331x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1); + output Y; + input A1, A2, A3, B1, B2, B3, C1; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + + and (int_fwire_0, A3, B3, C1); + and (int_fwire_1, A3, B2, C1); + and (int_fwire_2, A3, B1, C1); + and (int_fwire_3, A2, B3, C1); + and (int_fwire_4, A2, B2, C1); + and (int_fwire_5, A2, B1, C1); + and (int_fwire_6, A1, B3, C1); + and (int_fwire_7, A1, B2, C1); + and (int_fwire_8, A1, B1, C1); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA332x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + + and (int_fwire_0, A3, B3, C2); + and (int_fwire_1, A3, B3, C1); + and (int_fwire_2, A3, B2, C2); + and (int_fwire_3, A3, B2, C1); + and (int_fwire_4, A3, B1, C2); + and (int_fwire_5, A3, B1, C1); + and (int_fwire_6, A2, B3, C2); + and (int_fwire_7, A2, B3, C1); + and (int_fwire_8, A2, B2, C2); + and (int_fwire_9, A2, B2, C1); + and (int_fwire_10, A2, B1, C2); + and (int_fwire_11, A2, B1, C1); + and (int_fwire_12, A1, B3, C2); + and (int_fwire_13, A1, B3, C1); + and (int_fwire_14, A1, B2, C2); + and (int_fwire_15, A1, B2, C1); + and (int_fwire_16, A1, B1, C2); + and (int_fwire_17, A1, B1, C1); + or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA332x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + + and (int_fwire_0, A3, B3, C2); + and (int_fwire_1, A3, B3, C1); + and (int_fwire_2, A3, B2, C2); + and (int_fwire_3, A3, B2, C1); + and (int_fwire_4, A3, B1, C2); + and (int_fwire_5, A3, B1, C1); + and (int_fwire_6, A2, B3, C2); + and (int_fwire_7, A2, B3, C1); + and (int_fwire_8, A2, B2, C2); + and (int_fwire_9, A2, B2, C1); + and (int_fwire_10, A2, B1, C2); + and (int_fwire_11, A2, B1, C1); + and (int_fwire_12, A1, B3, C2); + and (int_fwire_13, A1, B3, C1); + and (int_fwire_14, A1, B2, C2); + and (int_fwire_15, A1, B2, C1); + and (int_fwire_16, A1, B1, C2); + and (int_fwire_17, A1, B1, C1); + or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA333x1_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + wire int_fwire_18, int_fwire_19, int_fwire_20; + wire int_fwire_21, int_fwire_22, int_fwire_23; + wire int_fwire_24, int_fwire_25, int_fwire_26; + + and (int_fwire_0, A3, B3, C3); + and (int_fwire_1, A3, B3, C2); + and (int_fwire_2, A3, B3, C1); + and (int_fwire_3, A3, B2, C3); + and (int_fwire_4, A3, B2, C2); + and (int_fwire_5, A3, B2, C1); + and (int_fwire_6, A3, B1, C3); + and (int_fwire_7, A3, B1, C2); + and (int_fwire_8, A3, B1, C1); + and (int_fwire_9, A2, B3, C3); + and (int_fwire_10, A2, B3, C2); + and (int_fwire_11, A2, B3, C1); + and (int_fwire_12, A2, B2, C3); + and (int_fwire_13, A2, B2, C2); + and (int_fwire_14, A2, B2, C1); + and (int_fwire_15, A2, B1, C3); + and (int_fwire_16, A2, B1, C2); + and (int_fwire_17, A2, B1, C1); + and (int_fwire_18, A1, B3, C3); + and (int_fwire_19, A1, B3, C2); + and (int_fwire_20, A1, B3, C1); + and (int_fwire_21, A1, B2, C3); + and (int_fwire_22, A1, B2, C2); + and (int_fwire_23, A1, B2, C1); + and (int_fwire_24, A1, B1, C3); + and (int_fwire_25, A1, B1, C2); + and (int_fwire_26, A1, B1, C1); + or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA333x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + wire int_fwire_9, int_fwire_10, int_fwire_11; + wire int_fwire_12, int_fwire_13, int_fwire_14; + wire int_fwire_15, int_fwire_16, int_fwire_17; + wire int_fwire_18, int_fwire_19, int_fwire_20; + wire int_fwire_21, int_fwire_22, int_fwire_23; + wire int_fwire_24, int_fwire_25, int_fwire_26; + + and (int_fwire_0, A3, B3, C3); + and (int_fwire_1, A3, B3, C2); + and (int_fwire_2, A3, B3, C1); + and (int_fwire_3, A3, B2, C3); + and (int_fwire_4, A3, B2, C2); + and (int_fwire_5, A3, B2, C1); + and (int_fwire_6, A3, B1, C3); + and (int_fwire_7, A3, B1, C2); + and (int_fwire_8, A3, B1, C1); + and (int_fwire_9, A2, B3, C3); + and (int_fwire_10, A2, B3, C2); + and (int_fwire_11, A2, B3, C1); + and (int_fwire_12, A2, B2, C3); + and (int_fwire_13, A2, B2, C2); + and (int_fwire_14, A2, B2, C1); + and (int_fwire_15, A2, B1, C3); + and (int_fwire_16, A2, B1, C2); + and (int_fwire_17, A2, B1, C1); + and (int_fwire_18, A1, B3, C3); + and (int_fwire_19, A1, B3, C2); + and (int_fwire_20, A1, B3, C1); + and (int_fwire_21, A1, B2, C3); + and (int_fwire_22, A1, B2, C2); + and (int_fwire_23, A1, B2, C1); + and (int_fwire_24, A1, B1, C3); + and (int_fwire_25, A1, B1, C2); + and (int_fwire_26, A1, B1, C1); + or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OA33x2_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3); + output Y; + input A1, A2, A3, B1, B2, B3; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6, int_fwire_7, int_fwire_8; + + and (int_fwire_0, A3, B3); + and (int_fwire_1, A3, B2); + and (int_fwire_2, A3, B1); + and (int_fwire_3, A2, B3); + and (int_fwire_4, A2, B2); + and (int_fwire_5, A2, B1); + and (int_fwire_6, A1, B3); + and (int_fwire_7, A1, B2); + and (int_fwire_8, A1, B1); + or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & B3) | (~A2 & ~A3 & ~B1 & B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & B3) | (~A1 & ~A3 & ~B1 & B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & B3) | (~A1 & ~A2 & ~B1 & B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B2 & ~B3) | (~A1 & A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2) | (~A1 & A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI211xp5_ASAP7_75t_SL (Y, A1, A2, B, C); + output Y; + input A1, A2, B, C; + + // Function + wire A1__bar, A2__bar, B__bar; + wire C__bar, int_fwire_0; + + not (C__bar, C); + not (B__bar, B); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar); + or (Y, int_fwire_0, B__bar, C__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2 & C)) + (B => Y) = 0; + if ((A1 & ~A2 & C)) + (B => Y) = 0; + if ((~A1 & A2 & C)) + (B => Y) = 0; + if ((A1 & A2 & B)) + (C => Y) = 0; + if ((A1 & ~A2 & B)) + (C => Y) = 0; + if ((~A1 & A2 & B)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI21x1_ASAP7_75t_SL (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0; + + not (B__bar, B); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2)) + (B => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI21xp33_ASAP7_75t_SL (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0; + + not (B__bar, B); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2)) + (B => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI21xp5_ASAP7_75t_SL (Y, A1, A2, B); + output Y; + input A1, A2, B; + + // Function + wire A1__bar, A2__bar, B__bar; + wire int_fwire_0; + + not (B__bar, B); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + if ((A1 & A2)) + (B => Y) = 0; + if ((A1 & ~A2)) + (B => Y) = 0; + if ((~A1 & A2)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI221xp5_ASAP7_75t_SL (Y, A1, A2, B1, B2, C); + output Y; + input A1, A2, B1, B2, C; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C__bar, int_fwire_0; + wire int_fwire_1; + + not (C__bar, C); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar); + or (Y, int_fwire_1, int_fwire_0, C__bar); + + // Timing + specify + if ((~A2 & B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & C)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2 & C)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~B1 & B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI222xp33_ASAP7_75t_SL (Y, A1, A2, B1, B2, C1, C2); + output Y; + input A1, A2, B1, B2, C1, C2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, C1__bar, C2__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + + not (C2__bar, C2); + not (C1__bar, C1); + and (int_fwire_0, C1__bar, C2__bar); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_1, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, A2__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & B2 & C1 & ~C2) | (~A2 & B1 & ~B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & B2 & C1 & ~C2) | (~A1 & B1 & ~B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI22x1_ASAP7_75t_SL (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI22xp33_ASAP7_75t_SL (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI22xp5_ASAP7_75t_SL (Y, A1, A2, B1, B2); + output Y; + input A1, A2, B1, B2; + + // Function + wire A1__bar, A2__bar, B1__bar; + wire B2__bar, int_fwire_0, int_fwire_1; + + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~B1 & B2)) + (A2 => Y) = 0; + if ((A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI311xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, C1); + output Y; + input A1, A2, A3, B1, C1; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, C1__bar, int_fwire_0; + + not (C1__bar, C1); + not (B1__bar, B1); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_0, B1__bar, C1__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & A3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & C1) | (A1 & ~A2 & A3 & C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & B1)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1) | (A1 & ~A2 & A3 & B1)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI31xp33_ASAP7_75t_SL (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, int_fwire_0; + + not (B__bar, B); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & A3)) + (B => Y) = 0; + if ((A1 & A2 & ~A3) | (A1 & ~A2 & A3)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & A2 & A3)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & ~A2 & A3)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI31xp67_ASAP7_75t_SL (Y, A1, A2, A3, B); + output Y; + input A1, A2, A3, B; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B__bar, int_fwire_0; + + not (B__bar, B); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_0, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_0, B__bar); + + // Timing + specify + (A1 => Y) = 0; + (A2 => Y) = 0; + (A3 => Y) = 0; + if ((A1 & A2 & A3)) + (B => Y) = 0; + if ((A1 & A2 & ~A3) | (A1 & ~A2 & A3)) + (B => Y) = 0; + if ((A1 & ~A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & A2 & A3)) + (B => Y) = 0; + if ((~A1 & A2 & ~A3)) + (B => Y) = 0; + if ((~A1 & ~A2 & A3)) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI321xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, C); + output Y; + input A1, A2, A3, B1, B2, C; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, C__bar; + wire int_fwire_0, int_fwire_1; + + not (C__bar, C); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_1, int_fwire_0, C__bar); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & C)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & C)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & C)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & C)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & C) | (A1 & ~A2 & A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & C)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & C) | (A1 & ~A2 & A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & C)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2) | (A1 & ~A2 & A3 & B1 & B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2) | (A1 & ~A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2) | (A1 & ~A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2)) + (C => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2)) + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI322xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, C1, C2); + output Y; + input A1, A2, A3, B1, B2, C1, C2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, C1__bar; + wire C2__bar, int_fwire_0, int_fwire_1; + wire int_fwire_2; + + not (C2__bar, C2); + not (C1__bar, C1); + and (int_fwire_0, C1__bar, C2__bar); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_1, B1__bar, B2__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI32xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2); + output Y; + input A1, A2, A3, B1, B2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, int_fwire_0; + wire int_fwire_1; + + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2) | (A1 & ~A2 & A3 & ~B2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1) | (A1 & ~A2 & A3 & ~B1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1)) + (B2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI331xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1); + output Y; + input A1, A2, A3, B1, B2, B3, C1; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, int_fwire_0, int_fwire_1; + + not (C1__bar, C1); + not (B3__bar, B3); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar, B3__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_1, int_fwire_0, C1__bar); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) + (C1 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI332xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, C2__bar, int_fwire_0; + wire int_fwire_1, int_fwire_2; + + not (C2__bar, C2); + not (C1__bar, C1); + and (int_fwire_0, C1__bar, C2__bar); + not (B3__bar, B3); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_1, B1__bar, B2__bar, B3__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) + (C2 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI333xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); + output Y; + input A1, A2, A3, B1, B2, B3, C1, C2, C3; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire C1__bar, C2__bar, C3__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + + not (C3__bar, C3); + not (C2__bar, C2); + not (C1__bar, C1); + and (int_fwire_0, C1__bar, C2__bar, C3__bar); + not (B3__bar, B3); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_1, B1__bar, B2__bar, B3__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_2, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) + (B3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) + (C1 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) + (C2 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) + (C3 => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OAI33xp33_ASAP7_75t_SL (Y, A1, A2, A3, B1, B2, B3); + output Y; + input A1, A2, A3, B1, B2, B3; + + // Function + wire A1__bar, A2__bar, A3__bar; + wire B1__bar, B2__bar, B3__bar; + wire int_fwire_0, int_fwire_1; + + not (B3__bar, B3); + not (B2__bar, B2); + not (B1__bar, B1); + and (int_fwire_0, B1__bar, B2__bar, B3__bar); + not (A3__bar, A3); + not (A2__bar, A2); + not (A1__bar, A1); + and (int_fwire_1, A1__bar, A2__bar, A3__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if ((~A2 & ~A3 & B1 & B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & B2 & ~B3) | (~A2 & ~A3 & B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & B1 & ~B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & B2 & ~B3)) + (A1 => Y) = 0; + if ((~A2 & ~A3 & ~B1 & ~B2 & B3)) + (A1 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & B2 & ~B3) | (~A1 & ~A3 & B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & B1 & ~B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & B2 & ~B3)) + (A2 => Y) = 0; + if ((~A1 & ~A3 & ~B1 & ~B2 & B3)) + (A2 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & B2 & ~B3) | (~A1 & ~A2 & B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & B1 & ~B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & B2 & ~B3)) + (A3 => Y) = 0; + if ((~A1 & ~A2 & ~B1 & ~B2 & B3)) + (A3 => Y) = 0; + if ((A1 & A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B2 & ~B3) | (~A1 & A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B2 & ~B3)) + (B1 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B3)) + (B2 => Y) = 0; + if ((A1 & A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & A3 & ~B1 & ~B2) | (~A1 & A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((A1 & ~A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((~A1 & A2 & ~A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + if ((~A1 & ~A2 & A3 & ~B1 & ~B2)) + (B3 => Y) = 0; + endspecify +endmodule +`endcelldefine diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_LVT_TT_220101.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_LVT_TT_220101.v new file mode 100644 index 0000000000..a04bc82c17 --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_LVT_TT_220101.v @@ -0,0 +1,1173 @@ +// BSD 3-Clause License +// +// Copyright 2022 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/anolas19/Liberate/Verilog/asap7sc7p5t_SEQ_LVT_TT_211229_pex created by Liberate 18.1.0.293 on Fri Dec 31 22:59:44 MST 2021 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module DFFASRHQNx1_ASAP7_75t_L (QN, D, RESETN, SETN, CLK); + output QN; + input D, RESETN, SETN, CLK; + reg notifier; + wire delayed_D, delayed_LESETN, delayed_SETN, delayed_CLK; + + // Function + wire int_fwire_d, int_fwire_IQN, int_fwire_r; + wire int_fwire_s, xcr_0; + + not (int_fwire_d, delayed_D); + not (int_fwire_s, delayed_LESETN); + not (int_fwire_r, delayed_SETN); + //altos_dff_sr_err (xcr_0, delayed_CLK, int_fwire_d, int_fwire_s, int_fwire_r); + // altos_dff_sr_0 (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, int_fwire_s, int_fwire_r, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, adacond8; + wire CLK__bar, D__bar; + + + // Additional timing gates + and (adacond0, RESETN, SETN); + and (adacond1, D, SETN); + and (adacond2, CLK, SETN); + not (CLK__bar, CLK); + and (adacond3, CLK__bar, SETN); + not (D__bar, D); + and (adacond4, D__bar, RESETN); + and (adacond5, CLK, RESETN); + and (adacond6, CLK__bar, RESETN); + and (adacond7, D, RESETN, SETN); + and (adacond8, D__bar, RESETN, SETN); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFHQNx1_ASAP7_75t_L (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (int_fwire_d, delayed_D); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFHQNx2_ASAP7_75t_L (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (int_fwire_d, delayed_D); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFHQNx3_ASAP7_75t_L (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (int_fwire_d, delayed_D); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFHQx4_ASAP7_75t_L (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_IQ, xcr_0; + + //altos_dff_err (xcr_0, delayed_CLK, delayed_D); + //altos_dff (int_fwire_IQ, notifier, delayed_CLK, delayed_D, xcr_0); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFLQNx1_ASAP7_75t_L (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (int_fwire_d, delayed_D); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFLQNx2_ASAP7_75t_L (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (int_fwire_d, delayed_D); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFLQNx3_ASAP7_75t_L (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (int_fwire_d, delayed_D); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFLQx4_ASAP7_75t_L (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, xcr_0; + + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, delayed_D); + //altos_dff (int_fwire_IQ, notifier, int_fwire_clk, delayed_D, xcr_0); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DHLx1_ASAP7_75t_L (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_IQ; + + //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DHLx2_ASAP7_75t_L (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_IQ; + + //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DHLx3_ASAP7_75t_L (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_IQ; + + //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DLLx1_ASAP7_75t_L (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ; + + not (int_fwire_clk, delayed_CLK); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DLLx2_ASAP7_75t_L (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ; + + not (int_fwire_clk, delayed_CLK); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DLLx3_ASAP7_75t_L (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ; + + not (int_fwire_clk, delayed_CLK); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx1_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx2_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx2p67DC_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx3_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx4DC_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx4_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx5_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx5p33DC_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx6p67DC_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx8DC_ASAP7_75t_L (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFHx1_ASAP7_75t_L (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFHx2_ASAP7_75t_L (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFHx3_ASAP7_75t_L (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFHx4_ASAP7_75t_L (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFLx1_ASAP7_75t_L (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFLx2_ASAP7_75t_L (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFLx3_ASAP7_75t_L (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFLx4_ASAP7_75t_L (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_SLVT_TT_220101.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_SLVT_TT_220101.v new file mode 100644 index 0000000000..86b817a386 --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_SLVT_TT_220101.v @@ -0,0 +1,1173 @@ +// BSD 3-Clause License +// +// Copyright 2022 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/anolas19/Liberate/Verilog/asap7sc7p5t_SEQ_SLVT_TT_211229_pex created by Liberate 18.1.0.293 on Fri Dec 31 22:59:44 MST 2021 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module DFFASRHQNx1_ASAP7_75t_SL (QN, D, RESETN, SETN, CLK); + output QN; + input D, RESETN, SETN, CLK; + reg notifier; + wire delayed_D, delayed_SLESETN, delayed_SETN, delayed_CLK; + + // Function + wire int_fwire_d, int_fwire_IQN, int_fwire_r; + wire int_fwire_s, xcr_0; + + not (int_fwire_d, delayed_D); + not (int_fwire_s, delayed_SLESETN); + not (int_fwire_r, delayed_SETN); + //altos_dff_sr_err (xcr_0, delayed_CLK, int_fwire_d, int_fwire_s, int_fwire_r); + // altos_dff_sr_0 (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, int_fwire_s, int_fwire_r, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, adacond8; + wire CLK__bar, D__bar; + + + // Additional timing gates + and (adacond0, RESETN, SETN); + and (adacond1, D, SETN); + and (adacond2, CLK, SETN); + not (CLK__bar, CLK); + and (adacond3, CLK__bar, SETN); + not (D__bar, D); + and (adacond4, D__bar, RESETN); + and (adacond5, CLK, RESETN); + and (adacond6, CLK__bar, RESETN); + and (adacond7, D, RESETN, SETN); + and (adacond8, D__bar, RESETN, SETN); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFHQNx1_ASAP7_75t_SL (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (int_fwire_d, delayed_D); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFHQNx2_ASAP7_75t_SL (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (int_fwire_d, delayed_D); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFHQNx3_ASAP7_75t_SL (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (int_fwire_d, delayed_D); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFHQx4_ASAP7_75t_SL (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_IQ, xcr_0; + + //altos_dff_err (xcr_0, delayed_CLK, delayed_D); + //altos_dff (int_fwire_IQ, notifier, delayed_CLK, delayed_D, xcr_0); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFLQNx1_ASAP7_75t_SL (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (int_fwire_d, delayed_D); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFLQNx2_ASAP7_75t_SL (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (int_fwire_d, delayed_D); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFLQNx3_ASAP7_75t_SL (QN, D, CLK); + output QN; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (int_fwire_d, delayed_D); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DFFLQx4_ASAP7_75t_SL (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, xcr_0; + + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, delayed_D); + //altos_dff (int_fwire_IQ, notifier, int_fwire_clk, delayed_D, xcr_0); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DHLx1_ASAP7_75t_SL (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_IQ; + + //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DHLx2_ASAP7_75t_SL (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_IQ; + + //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DHLx3_ASAP7_75t_SL (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_IQ; + + //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DLLx1_ASAP7_75t_SL (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ; + + not (int_fwire_clk, delayed_CLK); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DLLx2_ASAP7_75t_SL (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ; + + not (int_fwire_clk, delayed_CLK); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module DLLx3_ASAP7_75t_SL (Q, D, CLK); + output Q; + input D, CLK; + reg notifier; + wire delayed_D, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ; + + not (int_fwire_clk, delayed_CLK); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D); + buf (Q, int_fwire_IQ); + + // Timing +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx1_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx2_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx2p67DC_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx3_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx4DC_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx4_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx5_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx5p33DC_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx6p67DC_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module ICGx8DC_ASAP7_75t_SL (GCLK, ENA, SE, CLK); + output GCLK; + input ENA, SE, CLK; + reg notifier; + wire delayed_ENA, delayed_SE, delayed_CLK; + + // Function + wire int_fwire_clk, int_fwire_IQ, int_fwire_test; + + not (int_fwire_clk, delayed_CLK); + or (int_fwire_test, delayed_ENA, delayed_SE); + //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); + and (GCLK, delayed_CLK, int_fwire_IQ); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, ENA__bar; + wire int_twire_0, SE__bar; + + + // Additional timing gates + not (ENA__bar, ENA); + and (int_twire_0, ENA__bar, SE); + or (adacond0, ENA, int_twire_0); + not (SE__bar, SE); + and (adacond1, ENA__bar, SE__bar); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFHx1_ASAP7_75t_SL (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFHx2_ASAP7_75t_SL (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFHx3_ASAP7_75t_SL (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFHx4_ASAP7_75t_SL (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_d, int_fwire_IQN, xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFLx1_ASAP7_75t_SL (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFLx2_ASAP7_75t_SL (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFLx3_ASAP7_75t_SL (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module SDFLx4_ASAP7_75t_SL (QN, D, SE, SI, CLK); + output QN; + input D, SE, SI, CLK; + reg notifier; + wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; + + // Function + wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_clk, int_fwire_d, int_fwire_IQN; + wire xcr_0; + + not (delayed_SI__bar, delayed_SI); + and (int_fwire_0, delayed_SE, delayed_SI__bar); + not (delayed_D__bar, delayed_D); + and (int_fwire_1, delayed_D__bar, delayed_SI__bar); + not (delayed_SE__bar, delayed_SE); + and (int_fwire_2, delayed_D__bar, delayed_SE__bar); + or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); + not (int_fwire_clk, delayed_CLK); + //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); + //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); + buf (QN, int_fwire_IQN); + + // Timing + + // Additional timing wires + wire adacond0, adacond1, adacond2; + wire adacond3, adacond4, adacond5; + wire adacond6, adacond7, D__bar; + wire int_twire_0, int_twire_1, int_twire_2; + wire int_twire_3, int_twire_4, int_twire_5; + wire SE__bar, SI__bar; + + + // Additional timing gates + not (SE__bar, SE); + and (adacond0, SE__bar, SI); + not (SI__bar, SI); + and (adacond1, SE__bar, SI__bar); + and (adacond2, D, SI__bar); + not (D__bar, D); + and (adacond3, D__bar, SI); + and (adacond4, D, SE); + and (adacond5, D__bar, SE); + and (int_twire_0, D__bar, SE, SI); + and (int_twire_1, D, SE__bar); + and (int_twire_2, D, SE, SI); + or (adacond6, int_twire_2, int_twire_1, int_twire_0); + and (int_twire_3, D__bar, SE__bar); + and (int_twire_4, D__bar, SE, SI__bar); + and (int_twire_5, D, SE, SI__bar); + or (adacond7, int_twire_5, int_twire_4, int_twire_3); + +endmodule +`endcelldefine diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_LVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_LVT_TT_201020.v new file mode 100644 index 0000000000..ce741d6cfa --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_LVT_TT_201020.v @@ -0,0 +1,1303 @@ +// BSD 3-Clause License +// +// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_SIMPLE_LVT_TT_201020 created by Liberate 18.1.0.293 on Fri Nov 27 12:35:46 MST 2020 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module AND2x2_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + and (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND2x4_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + and (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND2x6_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + and (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND3x1_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + and (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND3x2_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + and (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND3x4_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + and (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND4x1_ASAP7_75t_L (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + and (Y, A, B, C, D); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND4x2_ASAP7_75t_L (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + and (Y, A, B, C, D); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND5x1_ASAP7_75t_L (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + and (Y, A, B, C, D, E); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND5x2_ASAP7_75t_L (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + and (Y, A, B, C, D, E); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module FAx1_ASAP7_75t_L (CON, SN, A, B, CI); + output CON, SN; + input A, B, CI; + + // Function + wire A__bar, B__bar, CI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6; + + not (CI__bar, CI); + not (B__bar, B); + and (int_fwire_0, B__bar, CI__bar); + not (A__bar, A); + and (int_fwire_1, A__bar, CI__bar); + and (int_fwire_2, A__bar, B__bar); + or (CON, int_fwire_2, int_fwire_1, int_fwire_0); + and (int_fwire_3, A__bar, B__bar, CI__bar); + and (int_fwire_4, A__bar, B, CI); + and (int_fwire_5, A, B__bar, CI); + and (int_fwire_6, A, B, CI__bar); + or (SN, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HAxp5_ASAP7_75t_L (CON, SN, A, B); + output CON, SN; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (B__bar, B); + not (A__bar, A); + or (CON, A__bar, B__bar); + and (int_fwire_0, A__bar, B__bar); + and (int_fwire_1, A, B); + or (SN, int_fwire_1, int_fwire_0); + + // Timing + specify + (A => CON) = 0; + (B => CON) = 0; + if (B) + (A => SN) = 0; + if (~B) + (A => SN) = 0; + if (A) + (B => SN) = 0; + if (~A) + (B => SN) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module MAJIxp5_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + + not (C__bar, C); + not (B__bar, B); + and (int_fwire_0, B__bar, C__bar); + not (A__bar, A); + and (int_fwire_1, A__bar, C__bar); + and (int_fwire_2, A__bar, B__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module MAJx2_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, B, C); + and (int_fwire_1, A, C); + and (int_fwire_2, A, B); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module MAJx3_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, B, C); + and (int_fwire_1, A, C); + and (int_fwire_2, A, B); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2x1_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2x1p5_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2x2_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2xp33_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2xp5_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2xp67_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND3x1_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND3x2_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND3xp33_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND4xp25_ASAP7_75t_L (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar; + + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar, D__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND4xp75_ASAP7_75t_L (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar; + + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar, D__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND5xp2_ASAP7_75t_L (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar, E__bar; + + not (E__bar, E); + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar, D__bar, E__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2x1_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2x1p5_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2x2_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2xp33_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2xp67_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR3x1_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR3x2_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR3xp33_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR4xp25_ASAP7_75t_L (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar; + + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar, D__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR4xp75_ASAP7_75t_L (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar; + + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar, D__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR5xp2_ASAP7_75t_L (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar, E__bar; + + not (E__bar, E); + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar, D__bar, E__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR2x2_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + or (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR2x4_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + or (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR2x6_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + or (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR3x1_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + or (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR3x2_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + or (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR3x4_ASAP7_75t_L (Y, A, B, C); + output Y; + input A, B, C; + + // Function + or (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR4x1_ASAP7_75t_L (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + or (Y, A, B, C, D); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR4x2_ASAP7_75t_L (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + or (Y, A, B, C, D); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR5x1_ASAP7_75t_L (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + or (Y, A, B, C, D, E); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR5x2_ASAP7_75t_L (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + or (Y, A, B, C, D, E); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module TIEHIx1_ASAP7_75t_L (H); + output H; + + // Function + buf (H, 1'b1); + + // Timing + specify + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module TIELOx1_ASAP7_75t_L (L); + output L; + + // Function + buf (L, 1'b0); + + // Timing + specify + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XNOR2x1_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (B__bar, B); + not (A__bar, A); + and (int_fwire_0, A__bar, B__bar); + and (int_fwire_1, A, B); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (B) + (A => Y) = 0; + if (~B) + (A => Y) = 0; + if (A) + (B => Y) = 0; + if (~A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XNOR2x2_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (B__bar, B); + not (A__bar, A); + and (int_fwire_0, A__bar, B__bar); + and (int_fwire_1, A, B); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (B) + (A => Y) = 0; + if (~B) + (A => Y) = 0; + if (A) + (B => Y) = 0; + if (~A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XNOR2xp5_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (B__bar, B); + not (A__bar, A); + and (int_fwire_0, A__bar, B__bar); + and (int_fwire_1, A, B); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (B) + (A => Y) = 0; + if (~B) + (A => Y) = 0; + if (A) + (B => Y) = 0; + if (~A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XOR2x1_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (A__bar, A); + and (int_fwire_0, A__bar, B); + not (B__bar, B); + and (int_fwire_1, A, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (~B) + (A => Y) = 0; + if (B) + (A => Y) = 0; + if (~A) + (B => Y) = 0; + if (A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XOR2x2_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (A__bar, A); + and (int_fwire_0, A__bar, B); + not (B__bar, B); + and (int_fwire_1, A, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (~B) + (A => Y) = 0; + if (B) + (A => Y) = 0; + if (~A) + (B => Y) = 0; + if (A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XOR2xp5_ASAP7_75t_L (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (A__bar, A); + and (int_fwire_0, A__bar, B); + not (B__bar, B); + and (int_fwire_1, A, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (~B) + (A => Y) = 0; + if (B) + (A => Y) = 0; + if (~A) + (B => Y) = 0; + if (A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_SLVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_SLVT_TT_201020.v new file mode 100644 index 0000000000..abdd8249e8 --- /dev/null +++ b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_SLVT_TT_201020.v @@ -0,0 +1,1303 @@ +// BSD 3-Clause License +// +// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State +// University +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_SIMPLE_SLVT_TT_201020 created by Liberate 18.1.0.293 on Fri Nov 27 12:35:46 MST 2020 for SDF version 2.1 + +// type: +`timescale 1ns/10ps +`celldefine +module AND2x2_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + and (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND2x4_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + and (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND2x6_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + and (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND3x1_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + and (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND3x2_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + and (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND3x4_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + and (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND4x1_ASAP7_75t_SL (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + and (Y, A, B, C, D); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND4x2_ASAP7_75t_SL (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + and (Y, A, B, C, D); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND5x1_ASAP7_75t_SL (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + and (Y, A, B, C, D, E); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module AND5x2_ASAP7_75t_SL (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + and (Y, A, B, C, D, E); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module FAx1_ASAP7_75t_SL (CON, SN, A, B, CI); + output CON, SN; + input A, B, CI; + + // Function + wire A__bar, B__bar, CI__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + wire int_fwire_3, int_fwire_4, int_fwire_5; + wire int_fwire_6; + + not (CI__bar, CI); + not (B__bar, B); + and (int_fwire_0, B__bar, CI__bar); + not (A__bar, A); + and (int_fwire_1, A__bar, CI__bar); + and (int_fwire_2, A__bar, B__bar); + or (CON, int_fwire_2, int_fwire_1, int_fwire_0); + and (int_fwire_3, A__bar, B__bar, CI__bar); + and (int_fwire_4, A__bar, B, CI); + and (int_fwire_5, A, B__bar, CI); + and (int_fwire_6, A, B, CI__bar); + or (SN, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module HAxp5_ASAP7_75t_SL (CON, SN, A, B); + output CON, SN; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (B__bar, B); + not (A__bar, A); + or (CON, A__bar, B__bar); + and (int_fwire_0, A__bar, B__bar); + and (int_fwire_1, A, B); + or (SN, int_fwire_1, int_fwire_0); + + // Timing + specify + (A => CON) = 0; + (B => CON) = 0; + if (B) + (A => SN) = 0; + if (~B) + (A => SN) = 0; + if (A) + (B => SN) = 0; + if (~A) + (B => SN) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module MAJIxp5_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + wire int_fwire_0, int_fwire_1, int_fwire_2; + + not (C__bar, C); + not (B__bar, B); + and (int_fwire_0, B__bar, C__bar); + not (A__bar, A); + and (int_fwire_1, A__bar, C__bar); + and (int_fwire_2, A__bar, B__bar); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module MAJx2_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, B, C); + and (int_fwire_1, A, C); + and (int_fwire_2, A, B); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module MAJx3_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire int_fwire_0, int_fwire_1, int_fwire_2; + + and (int_fwire_0, B, C); + and (int_fwire_1, A, C); + and (int_fwire_2, A, B); + or (Y, int_fwire_2, int_fwire_1, int_fwire_0); +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2x1_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2x1p5_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2x2_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2xp33_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2xp5_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND2xp67_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND3x1_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND3x2_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND3xp33_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND4xp25_ASAP7_75t_SL (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar; + + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar, D__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND4xp75_ASAP7_75t_SL (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar; + + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar, D__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NAND5xp2_ASAP7_75t_SL (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar, E__bar; + + not (E__bar, E); + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + or (Y, A__bar, B__bar, C__bar, D__bar, E__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2x1_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2x1p5_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2x2_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2xp33_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR2xp67_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar; + + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR3x1_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR3x2_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR3xp33_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + wire A__bar, B__bar, C__bar; + + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR4xp25_ASAP7_75t_SL (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar; + + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar, D__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR4xp75_ASAP7_75t_SL (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar; + + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar, D__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module NOR5xp2_ASAP7_75t_SL (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + wire A__bar, B__bar, C__bar; + wire D__bar, E__bar; + + not (E__bar, E); + not (D__bar, D); + not (C__bar, C); + not (B__bar, B); + not (A__bar, A); + and (Y, A__bar, B__bar, C__bar, D__bar, E__bar); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR2x2_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + or (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR2x4_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + or (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR2x6_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + or (Y, A, B); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR3x1_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + or (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR3x2_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + or (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR3x4_ASAP7_75t_SL (Y, A, B, C); + output Y; + input A, B, C; + + // Function + or (Y, A, B, C); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR4x1_ASAP7_75t_SL (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + or (Y, A, B, C, D); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR4x2_ASAP7_75t_SL (Y, A, B, C, D); + output Y; + input A, B, C, D; + + // Function + or (Y, A, B, C, D); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR5x1_ASAP7_75t_SL (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + or (Y, A, B, C, D, E); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module OR5x2_ASAP7_75t_SL (Y, A, B, C, D, E); + output Y; + input A, B, C, D, E; + + // Function + or (Y, A, B, C, D, E); + + // Timing + specify + (A => Y) = 0; + (B => Y) = 0; + (C => Y) = 0; + (D => Y) = 0; + (E => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module TIEHIx1_ASAP7_75t_SL (H); + output H; + + // Function + buf (H, 1'b1); + + // Timing + specify + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module TIELOx1_ASAP7_75t_SL (L); + output L; + + // Function + buf (L, 1'b0); + + // Timing + specify + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XNOR2x1_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (B__bar, B); + not (A__bar, A); + and (int_fwire_0, A__bar, B__bar); + and (int_fwire_1, A, B); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (B) + (A => Y) = 0; + if (~B) + (A => Y) = 0; + if (A) + (B => Y) = 0; + if (~A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XNOR2x2_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (B__bar, B); + not (A__bar, A); + and (int_fwire_0, A__bar, B__bar); + and (int_fwire_1, A, B); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (B) + (A => Y) = 0; + if (~B) + (A => Y) = 0; + if (A) + (B => Y) = 0; + if (~A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XNOR2xp5_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (B__bar, B); + not (A__bar, A); + and (int_fwire_0, A__bar, B__bar); + and (int_fwire_1, A, B); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (B) + (A => Y) = 0; + if (~B) + (A => Y) = 0; + if (A) + (B => Y) = 0; + if (~A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XOR2x1_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (A__bar, A); + and (int_fwire_0, A__bar, B); + not (B__bar, B); + and (int_fwire_1, A, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (~B) + (A => Y) = 0; + if (B) + (A => Y) = 0; + if (~A) + (B => Y) = 0; + if (A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XOR2x2_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (A__bar, A); + and (int_fwire_0, A__bar, B); + not (B__bar, B); + and (int_fwire_1, A, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (~B) + (A => Y) = 0; + if (B) + (A => Y) = 0; + if (~A) + (B => Y) = 0; + if (A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine + +// type: +`timescale 1ns/10ps +`celldefine +module XOR2xp5_ASAP7_75t_SL (Y, A, B); + output Y; + input A, B; + + // Function + wire A__bar, B__bar, int_fwire_0; + wire int_fwire_1; + + not (A__bar, A); + and (int_fwire_0, A__bar, B); + not (B__bar, B); + and (int_fwire_1, A, B__bar); + or (Y, int_fwire_1, int_fwire_0); + + // Timing + specify + if (~B) + (A => Y) = 0; + if (B) + (A => Y) = 0; + if (~A) + (B => Y) = 0; + if (A) + (B => Y) = 0; + endspecify +endmodule +`endcelldefine From 2d6c0321137306fd67041c9390a8dbfcecb2203a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Thu, 12 Jun 2025 22:20:55 +0200 Subject: [PATCH 059/198] ihp-sg13g2: fix SDC_FILE lockup problem MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit `make DESIGN_CONFIG=designs/ihp-sg13g2/gcd/config.mk SDC_FILE= print-SDC_FILE` would cause make to simply lock up, now it terminates Signed-off-by: Øyvind Harboe --- flow/platforms/ihp-sg13g2/config.mk | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/flow/platforms/ihp-sg13g2/config.mk b/flow/platforms/ihp-sg13g2/config.mk index 4f2440675c..69818bd004 100644 --- a/flow/platforms/ihp-sg13g2/config.mk +++ b/flow/platforms/ihp-sg13g2/config.mk @@ -63,8 +63,12 @@ export CLKGATE_MAP_FILE = $(PLATFORM_DIR)/cells_clkgate.v # Define ABC driver and load export ABC_DRIVER_CELL = sg13g2_buf_4 export ABC_LOAD_IN_FF = 6.0 -# Set yosys-abc clock period to first "clk_period" value or "-period" value found in sdc file -export ABC_CLOCK_PERIOD_IN_PS ?= $(shell sed -nE "s/^set clk_period (.+)|.* -period (.+) .*/\1\2/p" $(SDC_FILE) | head -1 | awk '{print $$1*1000}') +ifeq ($(origin ABC_CLOCK_PERIOD_IN_PS), undefined) + ifneq ($(wildcard $(SDC_FILE)),) + # Set yosys-abc clock period to first "clk_period" value or "-period" value found in sdc file + export ABC_CLOCK_PERIOD_IN_PS ?= $(shell sed -nE "s/^set clk_period (.+)|.* -period (.+) .*/\1\2/p" $(SDC_FILE) | head -1 | awk '{print $$1*1000}') + endif +endif # ----------------------------------------------------- # Sizing From 50d679cd709fedd453387c227a3967a1d61be300 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Fri, 13 Jun 2025 13:14:58 +0200 Subject: [PATCH 060/198] Update OR branch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index 8861232570..8b99478b07 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 8861232570bb2c0c2184c9eaf07d1e7e734b796f +Subproject commit 8b99478b07bf08f0b32ebbd7c58673b1724d3c4c From ffd0da71316808ae3a95c5caaa85cca24ac3e0f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Fri, 13 Jun 2025 13:18:30 +0200 Subject: [PATCH 061/198] Disable insertion delay for gf12/bp_single cts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This works around ~1000 ps clock tree skew introduced by inserting 105 delay buffers in front of the `bp_clk` register tree. Signed-off-by: Martin Povišer --- flow/designs/gf12/bp_single/config.mk | 2 ++ 1 file changed, 2 insertions(+) diff --git a/flow/designs/gf12/bp_single/config.mk b/flow/designs/gf12/bp_single/config.mk index 53f9f1d165..ef20c6cdc1 100644 --- a/flow/designs/gf12/bp_single/config.mk +++ b/flow/designs/gf12/bp_single/config.mk @@ -66,5 +66,7 @@ else export DESIGN_TYPE = CHIP_NODEN endif +export CTS_ARGS = -no_insertion_delay + # enable slack margin for setup and hold fix after CTS export SETUP_SLACK_MARGIN ?= 100 From b19379f8427b024fb6724d403e91ff8a0b59a138 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 13 Jun 2025 15:21:30 +0200 Subject: [PATCH 062/198] make: introduce PYTHON_EXE dependency injection MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is consistent with OPENROAD_EXE, etc. and is useful to manage dependencies, e.g. when providing the python dependency from a venv instead of the system. Signed-off-by: Øyvind Harboe --- flow/Makefile | 10 +++++----- flow/scripts/variables.mk | 4 +++- flow/util/utils.mk | 20 ++++++++++---------- 3 files changed, 18 insertions(+), 16 deletions(-) diff --git a/flow/Makefile b/flow/Makefile index a1f8e09e76..49824ab844 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -204,7 +204,7 @@ versions.txt: .SECONDEXPANSION: $(DONT_USE_LIBS): $$(filter %$$(@F) %$$(@F).gz,$(LIB_FILES)) @mkdir -p $(OBJECTS_DIR)/lib - $(UTILS_DIR)/preprocessLib.py -i $^ -o $@ + $(PYTHON_EXE) $(UTILS_DIR)/preprocessLib.py -i $^ -o $@ $(OBJECTS_DIR)/lib/merged.lib: $(DONT_USE_LIBS) $(UTILS_DIR)/mergeLib.pl $(PLATFORM)_merged $(DONT_USE_LIBS) > $@ @@ -271,9 +271,9 @@ do-synth-report: .PHONY: memory memory: if [ -f $(RESULTS_DIR)/mem_hierarchical.json ]; then \ - python3 $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem_hierarchical.json; \ + $(PYTHON_EXE) $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem_hierarchical.json; \ fi - python3 $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem.json + $(PYTHON_EXE) $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem.json # ============================================================================== @@ -619,12 +619,12 @@ finish: $(LOG_DIR)/6_report.log \ .PHONY: elapsed elapsed: - -@$(UTILS_DIR)/genElapsedTime.py -d $(BLOCK_LOG_FOLDERS) $(LOG_DIR) + -@$(PYTHON_EXE) $(UTILS_DIR)/genElapsedTime.py -d $(BLOCK_LOG_FOLDERS) $(LOG_DIR) # Useful when working with macros, see elapsed time for all macros in platform .PHONY: elapsed-all elapsed-all: - @$(UTILS_DIR)/genElapsedTime.py -d $(shell find $(WORK_HOME)/logs/$(PLATFORM)/*/*/ -type d) + @$(PYTHON_EXE) $(UTILS_DIR)/genElapsedTime.py -d $(shell find $(WORK_HOME)/logs/$(PLATFORM)/*/*/ -type d) $(eval $(call do-step,6_1_fill,$(RESULTS_DIR)/5_route.odb $(RESULTS_DIR)/5_route.sdc $(FILL_CONFIG),density_fill)) diff --git a/flow/scripts/variables.mk b/flow/scripts/variables.mk index 75f5766f19..3f0ea97c3f 100644 --- a/flow/scripts/variables.mk +++ b/flow/scripts/variables.mk @@ -41,7 +41,7 @@ include $(PLATFORM_DIR)/config.mk # __SPACE__ is a workaround for whitespace hell in "foreach"; there # is no way to escape space in defaults.py and get "foreach" to work. -$(foreach line,$(shell $(SCRIPTS_DIR)/defaults.py),$(eval export $(subst __SPACE__, ,$(line)))) +$(foreach line,$(shell $(PYTHON_EXE) $(SCRIPTS_DIR)/defaults.py),$(eval export $(subst __SPACE__, ,$(line)))) export LOG_DIR = $(WORK_HOME)/logs/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT) export OBJECTS_DIR = $(WORK_HOME)/objects/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT) @@ -70,6 +70,8 @@ export NUM_CORES #------------------------------------------------------------------------------- # setup all commands used within this flow +export PYTHON_EXE ?= $(shell command -v python3) + export TIME_BIN ?= env time TIME_CMD = $(TIME_BIN) -f 'Elapsed time: %E[h:]min:sec. CPU time: user %U sys %S (%P). Peak memory: %MKB.' TIME_TEST = $(shell $(TIME_CMD) echo foo 2>/dev/null) diff --git a/flow/util/utils.mk b/flow/util/utils.mk index c7a5a79621..84f10aa11a 100644 --- a/flow/util/utils.mk +++ b/flow/util/utils.mk @@ -5,9 +5,9 @@ metadata: finish metadata-generate metadata-check .PHONY: metadata-generate metadata-generate: - @mkdir -p $(REPORTS_DIR) - @echo $(DESIGN_DIR) > $(REPORTS_DIR)/design-dir.txt - $(UTILS_DIR)/genMetrics.py -d $(DESIGN_NICKNAME) \ + mkdir -p $(REPORTS_DIR) + echo $(DESIGN_DIR) > $(REPORTS_DIR)/design-dir.txt + $(PYTHON_EXE) $(UTILS_DIR)/genMetrics.py -d $(DESIGN_NICKNAME) \ -p $(PLATFORM) \ -v $(FLOW_VARIANT) \ --logs $(LOG_DIR) \ @@ -20,7 +20,7 @@ export RULES_JSON ?= $(DESIGN_DIR)/rules-$(FLOW_VARIANT).json .PHONY: metadata-check metadata-check: - @$(UTILS_DIR)/checkMetadata.py \ + $(PYTHON_EXE) $(UTILS_DIR)/checkMetadata.py \ -m $(REPORTS_DIR)/metadata.json \ -r $(RULES_JSON) 2>&1 \ | tee $(abspath $(REPORTS_DIR)/metadata-check.log) @@ -40,8 +40,8 @@ update_metadata: .PHONY: do-update_rules do-update_rules: - @mkdir -p $(REPORTS_DIR) - $(UTILS_DIR)/genRuleFile.py \ + mkdir -p $(REPORTS_DIR) + $(PYTHON_EXE) $(UTILS_DIR)/genRuleFile.py \ --rules $(RULES_JSON) \ --new-rules $(REPORTS_DIR)/rules.json \ --reference $(REPORTS_DIR)/metadata.json \ @@ -59,7 +59,7 @@ update_rules: do-update_rules do-copy_update_rules .PHONY: do-update_rules_force do-update_rules_force: - @mkdir -p $(REPORTS_DIR) + mkdir -p $(REPORTS_DIR) $(UTILS_DIR)/genRuleFile.py \ --rules $(RULES_JSON) \ --new-rules $(REPORTS_DIR)/rules.json \ @@ -74,7 +74,7 @@ update_rules_force: do-update_rules_force .PHONY: update_metadata_autotuner update_metadata_autotuner: - @$(UTILS_DIR)/genMetrics.py -d $(DESIGN_NICKNAME) \ + $(PYTHON_EXE) $(UTILS_DIR)/genMetrics.py -d $(DESIGN_NICKNAME) \ -p $(PLATFORM) \ -v $(FLOW_VARIANT) \ --logs $(LOG_DIR) \ @@ -93,7 +93,7 @@ $(RESULTS_DIR)/6_net_rc.csv: .PHONY: correlate_rc correlate_rc: $(RESULTS_DIR)/6_net_rc.csv - $(UTILS_DIR)/correlateRC.py $(RESULTS_DIR)/6_net_rc.csv + $(PYTHON_EXE) $(UTILS_DIR)/correlateRC.py $(RESULTS_DIR)/6_net_rc.csv # TODO Make always wants to redo designs with this rule, regardless of which variations are tried. # $(MAKE) DESIGN_CONFIG=$$config write_net_rc; \ @@ -104,7 +104,7 @@ correlate_platform_rc: design=$$(basename $$(dirname $$config)); \ make DESIGN_CONFIG=./$$config results/$(PLATFORM)/$$design/base/6_net_rc.csv; \ done - $(UTILS_DIR)/correlateRC.py $$(find results/$(PLATFORM)/*/base -name 6_net_rc.csv) + $(PYTHON_EXE) $(UTILS_DIR)/correlateRC.py $$(find results/$(PLATFORM)/*/base -name 6_net_rc.csv) # Run test using gnu parallel #------------------------------------------------------------------------------- From cb73ed67fde9fec59874c6c03536439ba563e995 Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Fri, 13 Jun 2025 13:08:32 -0700 Subject: [PATCH 063/198] updated asap7 cva6 memory sizes to remove tied off connections updated metrics Signed-off-by: Jeff Ng --- flow/designs/asap7/cva6/config.mk | 15 +- flow/designs/asap7/cva6/rules-base.json | 22 +- flow/designs/src/cva6/README.md | 2 + .../src/cva6/common/local/util/sram_cache.sv | 4 +- .../hpdcache/rtl/src/common/hpdcache_sram.sv | 2 +- .../src/common/hpdcache_sram_wbyteenable.sv | 2 +- flow/platforms/asap7/lef/fakeram7_128x64.lef | 1341 +++++ flow/platforms/asap7/lef/fakeram7_64x25.lef | 590 ++ flow/platforms/asap7/lef/fakeram7_64x256.lef | 4854 +++++++++++++++++ flow/platforms/asap7/lef/fakeram7_64x28.lef | 644 +++ .../asap7/lib/NLDM/fakeram7_128x64.lib | 389 ++ .../asap7/lib/NLDM/fakeram7_64x25.lib | 389 ++ .../asap7/lib/NLDM/fakeram7_64x256.lib | 389 ++ .../asap7/lib/NLDM/fakeram7_64x28.lib | 389 ++ flow/platforms/asap7/ram/cva6.cfg | 50 + .../asap7/verilog/fakeram7_128x64.sv | 10 + .../platforms/asap7/verilog/fakeram7_64x25.sv | 10 + .../asap7/verilog/fakeram7_64x256.sv | 10 + .../platforms/asap7/verilog/fakeram7_64x28.sv | 10 + 19 files changed, 9104 insertions(+), 18 deletions(-) create mode 100644 flow/platforms/asap7/lef/fakeram7_128x64.lef create mode 100644 flow/platforms/asap7/lef/fakeram7_64x25.lef create mode 100644 flow/platforms/asap7/lef/fakeram7_64x256.lef create mode 100644 flow/platforms/asap7/lef/fakeram7_64x28.lef create mode 100644 flow/platforms/asap7/lib/NLDM/fakeram7_128x64.lib create mode 100644 flow/platforms/asap7/lib/NLDM/fakeram7_64x25.lib create mode 100644 flow/platforms/asap7/lib/NLDM/fakeram7_64x256.lib create mode 100644 flow/platforms/asap7/lib/NLDM/fakeram7_64x28.lib create mode 100644 flow/platforms/asap7/ram/cva6.cfg create mode 100644 flow/platforms/asap7/verilog/fakeram7_128x64.sv create mode 100644 flow/platforms/asap7/verilog/fakeram7_64x25.sv create mode 100644 flow/platforms/asap7/verilog/fakeram7_64x256.sv create mode 100644 flow/platforms/asap7/verilog/fakeram7_64x28.sv diff --git a/flow/designs/asap7/cva6/config.mk b/flow/designs/asap7/cva6/config.mk index 255fb80ebf..9412351da6 100644 --- a/flow/designs/asap7/cva6/config.mk +++ b/flow/designs/asap7/cva6/config.mk @@ -65,7 +65,10 @@ export VERILOG_FILES = $(sort $(wildcard $(SRC_HOME)/common/local/util/ $(SRC_HOME)/core/cvxif_example/include/cvxif_instr_pkg.sv \ $(sort $(wildcard $(SRC_HOME)/core/frontend/*.sv)) \ $(SRC_HOME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \ - $(PLATFORM_DIR)/verilog/fakeram7_256x256.sv + $(PLATFORM_DIR)/verilog/fakeram7_64x256.sv \ + $(PLATFORM_DIR)/verilog/fakeram7_128x64.sv \ + $(PLATFORM_DIR)/verilog/fakeram7_64x28.sv \ + $(PLATFORM_DIR)/verilog/fakeram7_64x25.sv export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include \ $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/common_cells/include \ @@ -73,9 +76,15 @@ export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include export VERILOG_DEFINES += -D HPDCACHE_ASSERT_OFF -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram7_256x256.lef +export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram7_64x256.lef \ + $(PLATFORM_DIR)/lef/fakeram7_128x64.lef \ + $(PLATFORM_DIR)/lef/fakeram7_64x28.lef \ + $(PLATFORM_DIR)/lef/fakeram7_64x25.lef -export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_256x256.lib +export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x256.lib \ + $(PLATFORM_DIR)/lib/NLDM/fakeram7_128x64.lib \ + $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x28.lib \ + $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x25.lib export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc diff --git a/flow/designs/asap7/cva6/rules-base.json b/flow/designs/asap7/cva6/rules-base.json index 7096cba6f1..c1014297b1 100644 --- a/flow/designs/asap7/cva6/rules-base.json +++ b/flow/designs/asap7/cva6/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 40631.65, + "value": 19930.01, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 45043, + "value": 23688, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 163049, + "value": 152015, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 14178, + "value": 13219, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 14178, + "value": 13219, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1884562, + "value": 1332082, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,23 +48,23 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -216.36, + "value": -147.23, "compare": ">=" }, "finish__design__instance__area": { - "value": 45315, + "value": 23925, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 7089, + "value": 6609, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 101, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -20.3, + "value": -16.08, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/src/cva6/README.md b/flow/designs/src/cva6/README.md index 0726796f5c..cd27453e1c 100644 --- a/flow/designs/src/cva6/README.md +++ b/flow/designs/src/cva6/README.md @@ -1 +1,3 @@ Extracted from https://github.com/openhwgroup/cva6 + +Based on commit 3a389af with some changes for the RAMs diff --git a/flow/designs/src/cva6/common/local/util/sram_cache.sv b/flow/designs/src/cva6/common/local/util/sram_cache.sv index 9b3cf8d89b..799c63afcd 100644 --- a/flow/designs/src/cva6/common/local/util/sram_cache.sv +++ b/flow/designs/src/cva6/common/local/util/sram_cache.sv @@ -52,7 +52,7 @@ module sram_cache #( rdata_o = rdata_user[DATA_AND_USER_WIDTH-1:DATA_WIDTH]; ruser_o = rdata_user[USER_WIDTH-1:0]; end - fakeram7_256x256 i_tc_sram_wrapper( + fakeram7_64x256 i_tc_sram_wrapper( .clk ( clk_i ), .ce_in ( req_i ), .we_in ( we_i ), @@ -91,7 +91,7 @@ module sram_cache #( rdata_o = rdata_user; ruser_o = '0; end - fakeram7_256x256 i_tc_sram_wrapper( + fakeram7_64x25 i_tc_sram_wrapper( .clk ( clk_i ), .ce_in ( req_i ), .we_in ( we_i ), diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv index bc6668a1e9..d078555ac4 100644 --- a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv @@ -39,7 +39,7 @@ module hpdcache_sram output logic [DATA_SIZE-1:0] rdata ); - fakeram7_256x256 ram_i ( + fakeram7_64x28 ram_i ( .clk(clk), .ce_in(cs), .we_in(we), diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv index b78cd44a81..d0cf76a389 100644 --- a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv @@ -39,7 +39,7 @@ module hpdcache_sram_wbyteenable input logic [DATA_SIZE/8-1:0] wbyteenable, output logic [DATA_SIZE-1:0] rdata ); - fakeram7_256x256 ram_i ( + fakeram7_128x64 ram_i ( .clk (clk), .ce_in(cs), .we_in(we), diff --git a/flow/platforms/asap7/lef/fakeram7_128x64.lef b/flow/platforms/asap7/lef/fakeram7_128x64.lef new file mode 100644 index 0000000000..8b0977f4b9 --- /dev/null +++ b/flow/platforms/asap7/lef/fakeram7_128x64.lef @@ -0,0 +1,1341 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO fakeram7_128x64 + PROPERTY width 64 ; + PROPERTY depth 128 ; + PROPERTY banks 2 ; + FOREIGN fakeram7_128x64 0 0 ; + SYMMETRY X Y R90 ; + SIZE 16.720 BY 21.600 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.192 0.024 0.216 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.024 0.360 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.480 0.024 0.504 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.024 0.648 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.768 0.024 0.792 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.024 0.936 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.056 0.024 1.080 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.024 1.224 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.344 0.024 1.368 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.024 1.512 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.632 0.024 1.656 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.776 0.024 1.800 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.920 0.024 1.944 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.064 0.024 2.088 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.208 0.024 2.232 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.024 2.376 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.024 2.520 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.640 0.024 2.664 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.024 2.808 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.024 2.952 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.024 3.096 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.024 3.240 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.024 3.384 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.504 0.024 3.528 ; + END + END rd_out[24] + PIN rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.648 0.024 3.672 ; + END + END rd_out[25] + PIN rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.792 0.024 3.816 ; + END + END rd_out[26] + PIN rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.936 0.024 3.960 ; + END + END rd_out[27] + PIN rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.080 0.024 4.104 ; + END + END rd_out[28] + PIN rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.224 0.024 4.248 ; + END + END rd_out[29] + PIN rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.368 0.024 4.392 ; + END + END rd_out[30] + PIN rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.512 0.024 4.536 ; + END + END rd_out[31] + PIN rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.656 0.024 4.680 ; + END + END rd_out[32] + PIN rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.024 4.824 ; + END + END rd_out[33] + PIN rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.944 0.024 4.968 ; + END + END rd_out[34] + PIN rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.088 0.024 5.112 ; + END + END rd_out[35] + PIN rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.232 0.024 5.256 ; + END + END rd_out[36] + PIN rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.376 0.024 5.400 ; + END + END rd_out[37] + PIN rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.520 0.024 5.544 ; + END + END rd_out[38] + PIN rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.664 0.024 5.688 ; + END + END rd_out[39] + PIN rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.024 5.832 ; + END + END rd_out[40] + PIN rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.952 0.024 5.976 ; + END + END rd_out[41] + PIN rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.096 0.024 6.120 ; + END + END rd_out[42] + PIN rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.240 0.024 6.264 ; + END + END rd_out[43] + PIN rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.384 0.024 6.408 ; + END + END rd_out[44] + PIN rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.528 0.024 6.552 ; + END + END rd_out[45] + PIN rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.672 0.024 6.696 ; + END + END rd_out[46] + PIN rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.816 0.024 6.840 ; + END + END rd_out[47] + PIN rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.960 0.024 6.984 ; + END + END rd_out[48] + PIN rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.104 0.024 7.128 ; + END + END rd_out[49] + PIN rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.248 0.024 7.272 ; + END + END rd_out[50] + PIN rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.392 0.024 7.416 ; + END + END rd_out[51] + PIN rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.536 0.024 7.560 ; + END + END rd_out[52] + PIN rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.680 0.024 7.704 ; + END + END rd_out[53] + PIN rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.824 0.024 7.848 ; + END + END rd_out[54] + PIN rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.968 0.024 7.992 ; + END + END rd_out[55] + PIN rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.112 0.024 8.136 ; + END + END rd_out[56] + PIN rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.256 0.024 8.280 ; + END + END rd_out[57] + PIN rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.400 0.024 8.424 ; + END + END rd_out[58] + PIN rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.544 0.024 8.568 ; + END + END rd_out[59] + PIN rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.688 0.024 8.712 ; + END + END rd_out[60] + PIN rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.832 0.024 8.856 ; + END + END rd_out[61] + PIN rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.976 0.024 9.000 ; + END + END rd_out[62] + PIN rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.120 0.024 9.144 ; + END + END rd_out[63] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.792 0.024 9.816 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.936 0.024 9.960 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.080 0.024 10.104 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.224 0.024 10.248 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.368 0.024 10.392 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.512 0.024 10.536 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.656 0.024 10.680 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.800 0.024 10.824 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.944 0.024 10.968 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.088 0.024 11.112 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.232 0.024 11.256 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.376 0.024 11.400 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.520 0.024 11.544 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.664 0.024 11.688 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.808 0.024 11.832 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.952 0.024 11.976 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.096 0.024 12.120 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.240 0.024 12.264 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.384 0.024 12.408 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.528 0.024 12.552 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.672 0.024 12.696 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.816 0.024 12.840 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.960 0.024 12.984 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.104 0.024 13.128 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.248 0.024 13.272 ; + END + END wd_in[24] + PIN wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.392 0.024 13.416 ; + END + END wd_in[25] + PIN wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.536 0.024 13.560 ; + END + END wd_in[26] + PIN wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.680 0.024 13.704 ; + END + END wd_in[27] + PIN wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.824 0.024 13.848 ; + END + END wd_in[28] + PIN wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.968 0.024 13.992 ; + END + END wd_in[29] + PIN wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.112 0.024 14.136 ; + END + END wd_in[30] + PIN wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.256 0.024 14.280 ; + END + END wd_in[31] + PIN wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.400 0.024 14.424 ; + END + END wd_in[32] + PIN wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.544 0.024 14.568 ; + END + END wd_in[33] + PIN wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.688 0.024 14.712 ; + END + END wd_in[34] + PIN wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.832 0.024 14.856 ; + END + END wd_in[35] + PIN wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.976 0.024 15.000 ; + END + END wd_in[36] + PIN wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.120 0.024 15.144 ; + END + END wd_in[37] + PIN wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.264 0.024 15.288 ; + END + END wd_in[38] + PIN wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.408 0.024 15.432 ; + END + END wd_in[39] + PIN wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.552 0.024 15.576 ; + END + END wd_in[40] + PIN wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.696 0.024 15.720 ; + END + END wd_in[41] + PIN wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.840 0.024 15.864 ; + END + END wd_in[42] + PIN wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.984 0.024 16.008 ; + END + END wd_in[43] + PIN wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.128 0.024 16.152 ; + END + END wd_in[44] + PIN wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.272 0.024 16.296 ; + END + END wd_in[45] + PIN wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.416 0.024 16.440 ; + END + END wd_in[46] + PIN wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.560 0.024 16.584 ; + END + END wd_in[47] + PIN wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.704 0.024 16.728 ; + END + END wd_in[48] + PIN wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.848 0.024 16.872 ; + END + END wd_in[49] + PIN wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.992 0.024 17.016 ; + END + END wd_in[50] + PIN wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.136 0.024 17.160 ; + END + END wd_in[51] + PIN wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.280 0.024 17.304 ; + END + END wd_in[52] + PIN wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.424 0.024 17.448 ; + END + END wd_in[53] + PIN wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.568 0.024 17.592 ; + END + END wd_in[54] + PIN wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.712 0.024 17.736 ; + END + END wd_in[55] + PIN wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.856 0.024 17.880 ; + END + END wd_in[56] + PIN wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.000 0.024 18.024 ; + END + END wd_in[57] + PIN wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.144 0.024 18.168 ; + END + END wd_in[58] + PIN wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.288 0.024 18.312 ; + END + END wd_in[59] + PIN wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.432 0.024 18.456 ; + END + END wd_in[60] + PIN wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.576 0.024 18.600 ; + END + END wd_in[61] + PIN wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.720 0.024 18.744 ; + END + END wd_in[62] + PIN wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.864 0.024 18.888 ; + END + END wd_in[63] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.536 0.024 19.560 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.680 0.024 19.704 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.824 0.024 19.848 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.968 0.024 19.992 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.112 0.024 20.136 ; + END + END addr_in[4] + PIN addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.256 0.024 20.280 ; + END + END addr_in[5] + PIN addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.400 0.024 20.424 ; + END + END addr_in[6] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.072 0.024 21.096 ; + END + END we_in + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.216 0.024 21.240 ; + END + END ce_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.360 0.024 21.384 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 16.672 0.096 ; + RECT 0.048 0.768 16.672 0.864 ; + RECT 0.048 1.536 16.672 1.632 ; + RECT 0.048 2.304 16.672 2.400 ; + RECT 0.048 3.072 16.672 3.168 ; + RECT 0.048 3.840 16.672 3.936 ; + RECT 0.048 4.608 16.672 4.704 ; + RECT 0.048 5.376 16.672 5.472 ; + RECT 0.048 6.144 16.672 6.240 ; + RECT 0.048 6.912 16.672 7.008 ; + RECT 0.048 7.680 16.672 7.776 ; + RECT 0.048 8.448 16.672 8.544 ; + RECT 0.048 9.216 16.672 9.312 ; + RECT 0.048 9.984 16.672 10.080 ; + RECT 0.048 10.752 16.672 10.848 ; + RECT 0.048 11.520 16.672 11.616 ; + RECT 0.048 12.288 16.672 12.384 ; + RECT 0.048 13.056 16.672 13.152 ; + RECT 0.048 13.824 16.672 13.920 ; + RECT 0.048 14.592 16.672 14.688 ; + RECT 0.048 15.360 16.672 15.456 ; + RECT 0.048 16.128 16.672 16.224 ; + RECT 0.048 16.896 16.672 16.992 ; + RECT 0.048 17.664 16.672 17.760 ; + RECT 0.048 18.432 16.672 18.528 ; + RECT 0.048 19.200 16.672 19.296 ; + RECT 0.048 19.968 16.672 20.064 ; + RECT 0.048 20.736 16.672 20.832 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 16.672 0.480 ; + RECT 0.048 1.152 16.672 1.248 ; + RECT 0.048 1.920 16.672 2.016 ; + RECT 0.048 2.688 16.672 2.784 ; + RECT 0.048 3.456 16.672 3.552 ; + RECT 0.048 4.224 16.672 4.320 ; + RECT 0.048 4.992 16.672 5.088 ; + RECT 0.048 5.760 16.672 5.856 ; + RECT 0.048 6.528 16.672 6.624 ; + RECT 0.048 7.296 16.672 7.392 ; + RECT 0.048 8.064 16.672 8.160 ; + RECT 0.048 8.832 16.672 8.928 ; + RECT 0.048 9.600 16.672 9.696 ; + RECT 0.048 10.368 16.672 10.464 ; + RECT 0.048 11.136 16.672 11.232 ; + RECT 0.048 11.904 16.672 12.000 ; + RECT 0.048 12.672 16.672 12.768 ; + RECT 0.048 13.440 16.672 13.536 ; + RECT 0.048 14.208 16.672 14.304 ; + RECT 0.048 14.976 16.672 15.072 ; + RECT 0.048 15.744 16.672 15.840 ; + RECT 0.048 16.512 16.672 16.608 ; + RECT 0.048 17.280 16.672 17.376 ; + RECT 0.048 18.048 16.672 18.144 ; + RECT 0.048 18.816 16.672 18.912 ; + RECT 0.048 19.584 16.672 19.680 ; + RECT 0.048 20.352 16.672 20.448 ; + RECT 0.048 21.120 16.672 21.216 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 16.720 21.600 ; + LAYER M2 ; + RECT 0 0 16.720 21.600 ; + LAYER M3 ; + RECT 0 0 16.720 21.600 ; + LAYER M4 ; + RECT 0 0 16.720 21.600 ; + END +END fakeram7_128x64 + +END LIBRARY diff --git a/flow/platforms/asap7/lef/fakeram7_64x25.lef b/flow/platforms/asap7/lef/fakeram7_64x25.lef new file mode 100644 index 0000000000..70cb255428 --- /dev/null +++ b/flow/platforms/asap7/lef/fakeram7_64x25.lef @@ -0,0 +1,590 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO fakeram7_64x25 + PROPERTY width 25 ; + PROPERTY depth 64 ; + PROPERTY banks 4 ; + FOREIGN fakeram7_64x25 0 0 ; + SYMMETRY X Y R90 ; + SIZE 13.110 BY 6.000 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.144 0.024 0.168 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.240 0.024 0.264 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.024 0.360 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.432 0.024 0.456 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.528 0.024 0.552 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.024 0.648 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.720 0.024 0.744 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.816 0.024 0.840 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.024 0.936 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.008 0.024 1.032 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.104 0.024 1.128 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.024 1.224 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.296 0.024 1.320 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.392 0.024 1.416 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.024 1.512 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.584 0.024 1.608 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.680 0.024 1.704 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.776 0.024 1.800 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.872 0.024 1.896 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.968 0.024 1.992 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.064 0.024 2.088 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.160 0.024 2.184 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.256 0.024 2.280 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.024 2.376 ; + END + END rd_out[24] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.024 2.520 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.592 0.024 2.616 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.688 0.024 2.712 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.024 2.808 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.880 0.024 2.904 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.976 0.024 3.000 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.024 3.096 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.168 0.024 3.192 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.264 0.024 3.288 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.024 3.384 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.456 0.024 3.480 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.552 0.024 3.576 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.648 0.024 3.672 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.744 0.024 3.768 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.840 0.024 3.864 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.936 0.024 3.960 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.032 0.024 4.056 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.128 0.024 4.152 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.224 0.024 4.248 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.320 0.024 4.344 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.416 0.024 4.440 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.512 0.024 4.536 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.608 0.024 4.632 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.704 0.024 4.728 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.024 4.824 ; + END + END wd_in[24] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.944 0.024 4.968 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.040 0.024 5.064 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.136 0.024 5.160 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.232 0.024 5.256 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.328 0.024 5.352 ; + END + END addr_in[4] + PIN addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.424 0.024 5.448 ; + END + END addr_in[5] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.568 0.024 5.592 ; + END + END we_in + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.664 0.024 5.688 ; + END + END ce_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.760 0.024 5.784 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 13.062 0.096 ; + RECT 0.048 0.768 13.062 0.864 ; + RECT 0.048 1.536 13.062 1.632 ; + RECT 0.048 2.304 13.062 2.400 ; + RECT 0.048 3.072 13.062 3.168 ; + RECT 0.048 3.840 13.062 3.936 ; + RECT 0.048 4.608 13.062 4.704 ; + RECT 0.048 5.376 13.062 5.472 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 13.062 0.480 ; + RECT 0.048 1.152 13.062 1.248 ; + RECT 0.048 1.920 13.062 2.016 ; + RECT 0.048 2.688 13.062 2.784 ; + RECT 0.048 3.456 13.062 3.552 ; + RECT 0.048 4.224 13.062 4.320 ; + RECT 0.048 4.992 13.062 5.088 ; + RECT 0.048 5.760 13.062 5.856 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 13.110 6.000 ; + LAYER M2 ; + RECT 0 0 13.110 6.000 ; + LAYER M3 ; + RECT 0 0 13.110 6.000 ; + LAYER M4 ; + RECT 0 0 13.110 6.000 ; + END +END fakeram7_64x25 + +END LIBRARY diff --git a/flow/platforms/asap7/lef/fakeram7_64x256.lef b/flow/platforms/asap7/lef/fakeram7_64x256.lef new file mode 100644 index 0000000000..d1b8f95fee --- /dev/null +++ b/flow/platforms/asap7/lef/fakeram7_64x256.lef @@ -0,0 +1,4854 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO fakeram7_64x256 + PROPERTY width 256 ; + PROPERTY depth 64 ; + PROPERTY banks 1 ; + FOREIGN fakeram7_64x256 0 0 ; + SYMMETRY X Y R90 ; + SIZE 33.250 BY 46.800 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.036 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.096 0.036 0.120 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.144 0.036 0.168 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.192 0.036 0.216 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.240 0.036 0.264 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.288 0.036 0.312 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.036 0.360 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.384 0.036 0.408 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.432 0.036 0.456 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.480 0.036 0.504 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.528 0.036 0.552 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.576 0.036 0.600 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.036 0.648 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.672 0.036 0.696 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.720 0.036 0.744 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.768 0.036 0.792 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.816 0.036 0.840 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.864 0.036 0.888 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.036 0.936 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.960 0.036 0.984 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.008 0.036 1.032 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.056 0.036 1.080 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.104 0.036 1.128 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.152 0.036 1.176 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.036 1.224 ; + END + END rd_out[24] + PIN rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.248 0.036 1.272 ; + END + END rd_out[25] + PIN rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.296 0.036 1.320 ; + END + END rd_out[26] + PIN rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.344 0.036 1.368 ; + END + END rd_out[27] + PIN rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.392 0.036 1.416 ; + END + END rd_out[28] + PIN rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.440 0.036 1.464 ; + END + END rd_out[29] + PIN rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.036 1.512 ; + END + END rd_out[30] + PIN rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.536 0.036 1.560 ; + END + END rd_out[31] + PIN rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.584 0.036 1.608 ; + END + END rd_out[32] + PIN rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.632 0.036 1.656 ; + END + END rd_out[33] + PIN rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.680 0.036 1.704 ; + END + END rd_out[34] + PIN rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.728 0.036 1.752 ; + END + END rd_out[35] + PIN rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.776 0.036 1.800 ; + END + END rd_out[36] + PIN rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.824 0.036 1.848 ; + END + END rd_out[37] + PIN rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.872 0.036 1.896 ; + END + END rd_out[38] + PIN rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.920 0.036 1.944 ; + END + END rd_out[39] + PIN rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.968 0.036 1.992 ; + END + END rd_out[40] + PIN rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.016 0.036 2.040 ; + END + END rd_out[41] + PIN rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.064 0.036 2.088 ; + END + END rd_out[42] + PIN rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.112 0.036 2.136 ; + END + END rd_out[43] + PIN rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.160 0.036 2.184 ; + END + END rd_out[44] + PIN rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.208 0.036 2.232 ; + END + END rd_out[45] + PIN rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.256 0.036 2.280 ; + END + END rd_out[46] + PIN rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.304 0.036 2.328 ; + END + END rd_out[47] + PIN rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.036 2.376 ; + END + END rd_out[48] + PIN rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.400 0.036 2.424 ; + END + END rd_out[49] + PIN rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.448 0.036 2.472 ; + END + END rd_out[50] + PIN rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.036 2.520 ; + END + END rd_out[51] + PIN rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.544 0.036 2.568 ; + END + END rd_out[52] + PIN rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.592 0.036 2.616 ; + END + END rd_out[53] + PIN rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.640 0.036 2.664 ; + END + END rd_out[54] + PIN rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.688 0.036 2.712 ; + END + END rd_out[55] + PIN rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.736 0.036 2.760 ; + END + END rd_out[56] + PIN rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.036 2.808 ; + END + END rd_out[57] + PIN rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.832 0.036 2.856 ; + END + END rd_out[58] + PIN rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.880 0.036 2.904 ; + END + END rd_out[59] + PIN rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.036 2.952 ; + END + END rd_out[60] + PIN rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.976 0.036 3.000 ; + END + END rd_out[61] + PIN rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.024 0.036 3.048 ; + END + END rd_out[62] + PIN rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.036 3.096 ; + END + END rd_out[63] + PIN rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.120 0.036 3.144 ; + END + END rd_out[64] + PIN rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.168 0.036 3.192 ; + END + END rd_out[65] + PIN rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.036 3.240 ; + END + END rd_out[66] + PIN rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.264 0.036 3.288 ; + END + END rd_out[67] + PIN rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.312 0.036 3.336 ; + END + END rd_out[68] + PIN rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.036 3.384 ; + END + END rd_out[69] + PIN rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.408 0.036 3.432 ; + END + END rd_out[70] + PIN rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.456 0.036 3.480 ; + END + END rd_out[71] + PIN rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.504 0.036 3.528 ; + END + END rd_out[72] + PIN rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.552 0.036 3.576 ; + END + END rd_out[73] + PIN rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.600 0.036 3.624 ; + END + END rd_out[74] + PIN rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.648 0.036 3.672 ; + END + END rd_out[75] + PIN rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.696 0.036 3.720 ; + END + END rd_out[76] + PIN rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.744 0.036 3.768 ; + END + END rd_out[77] + PIN rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.792 0.036 3.816 ; + END + END rd_out[78] + PIN rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.840 0.036 3.864 ; + END + END rd_out[79] + PIN rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.888 0.036 3.912 ; + END + END rd_out[80] + PIN rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.936 0.036 3.960 ; + END + END rd_out[81] + PIN rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.984 0.036 4.008 ; + END + END rd_out[82] + PIN rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.032 0.036 4.056 ; + END + END rd_out[83] + PIN rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.080 0.036 4.104 ; + END + END rd_out[84] + PIN rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.128 0.036 4.152 ; + END + END rd_out[85] + PIN rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.176 0.036 4.200 ; + END + END rd_out[86] + PIN rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.224 0.036 4.248 ; + END + END rd_out[87] + PIN rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.272 0.036 4.296 ; + END + END rd_out[88] + PIN rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.320 0.036 4.344 ; + END + END rd_out[89] + PIN rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.368 0.036 4.392 ; + END + END rd_out[90] + PIN rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.416 0.036 4.440 ; + END + END rd_out[91] + PIN rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.464 0.036 4.488 ; + END + END rd_out[92] + PIN rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.512 0.036 4.536 ; + END + END rd_out[93] + PIN rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.560 0.036 4.584 ; + END + END rd_out[94] + PIN rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.608 0.036 4.632 ; + END + END rd_out[95] + PIN rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.656 0.036 4.680 ; + END + END rd_out[96] + PIN rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.704 0.036 4.728 ; + END + END rd_out[97] + PIN rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.752 0.036 4.776 ; + END + END rd_out[98] + PIN rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.036 4.824 ; + END + END rd_out[99] + PIN rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.848 0.036 4.872 ; + END + END rd_out[100] + PIN rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.896 0.036 4.920 ; + END + END rd_out[101] + PIN rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.944 0.036 4.968 ; + END + END rd_out[102] + PIN rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.992 0.036 5.016 ; + END + END rd_out[103] + PIN rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.040 0.036 5.064 ; + END + END rd_out[104] + PIN rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.088 0.036 5.112 ; + END + END rd_out[105] + PIN rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.136 0.036 5.160 ; + END + END rd_out[106] + PIN rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.184 0.036 5.208 ; + END + END rd_out[107] + PIN rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.232 0.036 5.256 ; + END + END rd_out[108] + PIN rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.280 0.036 5.304 ; + END + END rd_out[109] + PIN rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.328 0.036 5.352 ; + END + END rd_out[110] + PIN rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.376 0.036 5.400 ; + END + END rd_out[111] + PIN rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.424 0.036 5.448 ; + END + END rd_out[112] + PIN rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.472 0.036 5.496 ; + END + END rd_out[113] + PIN rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.520 0.036 5.544 ; + END + END rd_out[114] + PIN rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.568 0.036 5.592 ; + END + END rd_out[115] + PIN rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.616 0.036 5.640 ; + END + END rd_out[116] + PIN rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.664 0.036 5.688 ; + END + END rd_out[117] + PIN rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.712 0.036 5.736 ; + END + END rd_out[118] + PIN rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.760 0.036 5.784 ; + END + END rd_out[119] + PIN rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.036 5.832 ; + END + END rd_out[120] + PIN rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.856 0.036 5.880 ; + END + END rd_out[121] + PIN rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.904 0.036 5.928 ; + END + END rd_out[122] + PIN rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.952 0.036 5.976 ; + END + END rd_out[123] + PIN rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.000 0.036 6.024 ; + END + END rd_out[124] + PIN rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.048 0.036 6.072 ; + END + END rd_out[125] + PIN rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.096 0.036 6.120 ; + END + END rd_out[126] + PIN rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.144 0.036 6.168 ; + END + END rd_out[127] + PIN rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.192 0.036 6.216 ; + END + END rd_out[128] + PIN rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.240 0.036 6.264 ; + END + END rd_out[129] + PIN rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.288 0.036 6.312 ; + END + END rd_out[130] + PIN rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.336 0.036 6.360 ; + END + END rd_out[131] + PIN rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.384 0.036 6.408 ; + END + END rd_out[132] + PIN rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.432 0.036 6.456 ; + END + END rd_out[133] + PIN rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.480 0.036 6.504 ; + END + END rd_out[134] + PIN rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.528 0.036 6.552 ; + END + END rd_out[135] + PIN rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.576 0.036 6.600 ; + END + END rd_out[136] + PIN rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.624 0.036 6.648 ; + END + END rd_out[137] + PIN rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.672 0.036 6.696 ; + END + END rd_out[138] + PIN rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.720 0.036 6.744 ; + END + END rd_out[139] + PIN rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.768 0.036 6.792 ; + END + END rd_out[140] + PIN rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.816 0.036 6.840 ; + END + END rd_out[141] + PIN rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.864 0.036 6.888 ; + END + END rd_out[142] + PIN rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.912 0.036 6.936 ; + END + END rd_out[143] + PIN rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.960 0.036 6.984 ; + END + END rd_out[144] + PIN rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.008 0.036 7.032 ; + END + END rd_out[145] + PIN rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.056 0.036 7.080 ; + END + END rd_out[146] + PIN rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.104 0.036 7.128 ; + END + END rd_out[147] + PIN rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.152 0.036 7.176 ; + END + END rd_out[148] + PIN rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.200 0.036 7.224 ; + END + END rd_out[149] + PIN rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.248 0.036 7.272 ; + END + END rd_out[150] + PIN rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.296 0.036 7.320 ; + END + END rd_out[151] + PIN rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.344 0.036 7.368 ; + END + END rd_out[152] + PIN rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.392 0.036 7.416 ; + END + END rd_out[153] + PIN rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.440 0.036 7.464 ; + END + END rd_out[154] + PIN rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.488 0.036 7.512 ; + END + END rd_out[155] + PIN rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.536 0.036 7.560 ; + END + END rd_out[156] + PIN rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.584 0.036 7.608 ; + END + END rd_out[157] + PIN rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.632 0.036 7.656 ; + END + END rd_out[158] + PIN rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.680 0.036 7.704 ; + END + END rd_out[159] + PIN rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.728 0.036 7.752 ; + END + END rd_out[160] + PIN rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.776 0.036 7.800 ; + END + END rd_out[161] + PIN rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.824 0.036 7.848 ; + END + END rd_out[162] + PIN rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.872 0.036 7.896 ; + END + END rd_out[163] + PIN rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.920 0.036 7.944 ; + END + END rd_out[164] + PIN rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.968 0.036 7.992 ; + END + END rd_out[165] + PIN rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.016 0.036 8.040 ; + END + END rd_out[166] + PIN rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.064 0.036 8.088 ; + END + END rd_out[167] + PIN rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.112 0.036 8.136 ; + END + END rd_out[168] + PIN rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.160 0.036 8.184 ; + END + END rd_out[169] + PIN rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.208 0.036 8.232 ; + END + END rd_out[170] + PIN rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.256 0.036 8.280 ; + END + END rd_out[171] + PIN rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.304 0.036 8.328 ; + END + END rd_out[172] + PIN rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.352 0.036 8.376 ; + END + END rd_out[173] + PIN rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.400 0.036 8.424 ; + END + END rd_out[174] + PIN rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.448 0.036 8.472 ; + END + END rd_out[175] + PIN rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.496 0.036 8.520 ; + END + END rd_out[176] + PIN rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.544 0.036 8.568 ; + END + END rd_out[177] + PIN rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.592 0.036 8.616 ; + END + END rd_out[178] + PIN rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.640 0.036 8.664 ; + END + END rd_out[179] + PIN rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.688 0.036 8.712 ; + END + END rd_out[180] + PIN rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.736 0.036 8.760 ; + END + END rd_out[181] + PIN rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.784 0.036 8.808 ; + END + END rd_out[182] + PIN rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.832 0.036 8.856 ; + END + END rd_out[183] + PIN rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.880 0.036 8.904 ; + END + END rd_out[184] + PIN rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.928 0.036 8.952 ; + END + END rd_out[185] + PIN rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.976 0.036 9.000 ; + END + END rd_out[186] + PIN rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.024 0.036 9.048 ; + END + END rd_out[187] + PIN rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.072 0.036 9.096 ; + END + END rd_out[188] + PIN rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.120 0.036 9.144 ; + END + END rd_out[189] + PIN rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.168 0.036 9.192 ; + END + END rd_out[190] + PIN rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.216 0.036 9.240 ; + END + END rd_out[191] + PIN rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.264 0.036 9.288 ; + END + END rd_out[192] + PIN rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.312 0.036 9.336 ; + END + END rd_out[193] + PIN rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.360 0.036 9.384 ; + END + END rd_out[194] + PIN rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.408 0.036 9.432 ; + END + END rd_out[195] + PIN rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.456 0.036 9.480 ; + END + END rd_out[196] + PIN rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.504 0.036 9.528 ; + END + END rd_out[197] + PIN rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.552 0.036 9.576 ; + END + END rd_out[198] + PIN rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.600 0.036 9.624 ; + END + END rd_out[199] + PIN rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.648 0.036 9.672 ; + END + END rd_out[200] + PIN rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.696 0.036 9.720 ; + END + END rd_out[201] + PIN rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.744 0.036 9.768 ; + END + END rd_out[202] + PIN rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.792 0.036 9.816 ; + END + END rd_out[203] + PIN rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.840 0.036 9.864 ; + END + END rd_out[204] + PIN rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.888 0.036 9.912 ; + END + END rd_out[205] + PIN rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.936 0.036 9.960 ; + END + END rd_out[206] + PIN rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.984 0.036 10.008 ; + END + END rd_out[207] + PIN rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.032 0.036 10.056 ; + END + END rd_out[208] + PIN rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.080 0.036 10.104 ; + END + END rd_out[209] + PIN rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.128 0.036 10.152 ; + END + END rd_out[210] + PIN rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.176 0.036 10.200 ; + END + END rd_out[211] + PIN rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.224 0.036 10.248 ; + END + END rd_out[212] + PIN rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.272 0.036 10.296 ; + END + END rd_out[213] + PIN rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.320 0.036 10.344 ; + END + END rd_out[214] + PIN rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.368 0.036 10.392 ; + END + END rd_out[215] + PIN rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.416 0.036 10.440 ; + END + END rd_out[216] + PIN rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.464 0.036 10.488 ; + END + END rd_out[217] + PIN rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.512 0.036 10.536 ; + END + END rd_out[218] + PIN rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.560 0.036 10.584 ; + END + END rd_out[219] + PIN rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.608 0.036 10.632 ; + END + END rd_out[220] + PIN rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.656 0.036 10.680 ; + END + END rd_out[221] + PIN rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.704 0.036 10.728 ; + END + END rd_out[222] + PIN rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.752 0.036 10.776 ; + END + END rd_out[223] + PIN rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.800 0.036 10.824 ; + END + END rd_out[224] + PIN rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.848 0.036 10.872 ; + END + END rd_out[225] + PIN rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.896 0.036 10.920 ; + END + END rd_out[226] + PIN rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.944 0.036 10.968 ; + END + END rd_out[227] + PIN rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.992 0.036 11.016 ; + END + END rd_out[228] + PIN rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.040 0.036 11.064 ; + END + END rd_out[229] + PIN rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.088 0.036 11.112 ; + END + END rd_out[230] + PIN rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.136 0.036 11.160 ; + END + END rd_out[231] + PIN rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.184 0.036 11.208 ; + END + END rd_out[232] + PIN rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.232 0.036 11.256 ; + END + END rd_out[233] + PIN rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.280 0.036 11.304 ; + END + END rd_out[234] + PIN rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.328 0.036 11.352 ; + END + END rd_out[235] + PIN rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.376 0.036 11.400 ; + END + END rd_out[236] + PIN rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.424 0.036 11.448 ; + END + END rd_out[237] + PIN rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.472 0.036 11.496 ; + END + END rd_out[238] + PIN rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.520 0.036 11.544 ; + END + END rd_out[239] + PIN rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.568 0.036 11.592 ; + END + END rd_out[240] + PIN rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.616 0.036 11.640 ; + END + END rd_out[241] + PIN rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.664 0.036 11.688 ; + END + END rd_out[242] + PIN rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.712 0.036 11.736 ; + END + END rd_out[243] + PIN rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.760 0.036 11.784 ; + END + END rd_out[244] + PIN rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.808 0.036 11.832 ; + END + END rd_out[245] + PIN rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.856 0.036 11.880 ; + END + END rd_out[246] + PIN rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.904 0.036 11.928 ; + END + END rd_out[247] + PIN rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.952 0.036 11.976 ; + END + END rd_out[248] + PIN rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.000 0.036 12.024 ; + END + END rd_out[249] + PIN rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.048 0.036 12.072 ; + END + END rd_out[250] + PIN rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.096 0.036 12.120 ; + END + END rd_out[251] + PIN rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.144 0.036 12.168 ; + END + END rd_out[252] + PIN rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.192 0.036 12.216 ; + END + END rd_out[253] + PIN rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.240 0.036 12.264 ; + END + END rd_out[254] + PIN rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.288 0.036 12.312 ; + END + END rd_out[255] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.536 0.036 19.560 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.584 0.036 19.608 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.632 0.036 19.656 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.680 0.036 19.704 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.728 0.036 19.752 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.776 0.036 19.800 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.824 0.036 19.848 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.872 0.036 19.896 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.920 0.036 19.944 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.968 0.036 19.992 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.016 0.036 20.040 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.064 0.036 20.088 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.112 0.036 20.136 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.160 0.036 20.184 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.208 0.036 20.232 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.256 0.036 20.280 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.304 0.036 20.328 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.352 0.036 20.376 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.400 0.036 20.424 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.448 0.036 20.472 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.496 0.036 20.520 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.544 0.036 20.568 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.592 0.036 20.616 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.640 0.036 20.664 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.688 0.036 20.712 ; + END + END wd_in[24] + PIN wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.736 0.036 20.760 ; + END + END wd_in[25] + PIN wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.784 0.036 20.808 ; + END + END wd_in[26] + PIN wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.832 0.036 20.856 ; + END + END wd_in[27] + PIN wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.880 0.036 20.904 ; + END + END wd_in[28] + PIN wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.928 0.036 20.952 ; + END + END wd_in[29] + PIN wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.976 0.036 21.000 ; + END + END wd_in[30] + PIN wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.024 0.036 21.048 ; + END + END wd_in[31] + PIN wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.072 0.036 21.096 ; + END + END wd_in[32] + PIN wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.120 0.036 21.144 ; + END + END wd_in[33] + PIN wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.168 0.036 21.192 ; + END + END wd_in[34] + PIN wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.216 0.036 21.240 ; + END + END wd_in[35] + PIN wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.264 0.036 21.288 ; + END + END wd_in[36] + PIN wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.312 0.036 21.336 ; + END + END wd_in[37] + PIN wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.360 0.036 21.384 ; + END + END wd_in[38] + PIN wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.408 0.036 21.432 ; + END + END wd_in[39] + PIN wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.456 0.036 21.480 ; + END + END wd_in[40] + PIN wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.504 0.036 21.528 ; + END + END wd_in[41] + PIN wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.552 0.036 21.576 ; + END + END wd_in[42] + PIN wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.600 0.036 21.624 ; + END + END wd_in[43] + PIN wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.648 0.036 21.672 ; + END + END wd_in[44] + PIN wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.696 0.036 21.720 ; + END + END wd_in[45] + PIN wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.744 0.036 21.768 ; + END + END wd_in[46] + PIN wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.792 0.036 21.816 ; + END + END wd_in[47] + PIN wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.840 0.036 21.864 ; + END + END wd_in[48] + PIN wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.888 0.036 21.912 ; + END + END wd_in[49] + PIN wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.936 0.036 21.960 ; + END + END wd_in[50] + PIN wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.984 0.036 22.008 ; + END + END wd_in[51] + PIN wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.032 0.036 22.056 ; + END + END wd_in[52] + PIN wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.080 0.036 22.104 ; + END + END wd_in[53] + PIN wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.128 0.036 22.152 ; + END + END wd_in[54] + PIN wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.176 0.036 22.200 ; + END + END wd_in[55] + PIN wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.224 0.036 22.248 ; + END + END wd_in[56] + PIN wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.272 0.036 22.296 ; + END + END wd_in[57] + PIN wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.320 0.036 22.344 ; + END + END wd_in[58] + PIN wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.368 0.036 22.392 ; + END + END wd_in[59] + PIN wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.416 0.036 22.440 ; + END + END wd_in[60] + PIN wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.464 0.036 22.488 ; + END + END wd_in[61] + PIN wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.512 0.036 22.536 ; + END + END wd_in[62] + PIN wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.560 0.036 22.584 ; + END + END wd_in[63] + PIN wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.608 0.036 22.632 ; + END + END wd_in[64] + PIN wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.656 0.036 22.680 ; + END + END wd_in[65] + PIN wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.704 0.036 22.728 ; + END + END wd_in[66] + PIN wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.752 0.036 22.776 ; + END + END wd_in[67] + PIN wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.800 0.036 22.824 ; + END + END wd_in[68] + PIN wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.848 0.036 22.872 ; + END + END wd_in[69] + PIN wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.896 0.036 22.920 ; + END + END wd_in[70] + PIN wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.944 0.036 22.968 ; + END + END wd_in[71] + PIN wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.992 0.036 23.016 ; + END + END wd_in[72] + PIN wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.040 0.036 23.064 ; + END + END wd_in[73] + PIN wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.088 0.036 23.112 ; + END + END wd_in[74] + PIN wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.136 0.036 23.160 ; + END + END wd_in[75] + PIN wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.184 0.036 23.208 ; + END + END wd_in[76] + PIN wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.232 0.036 23.256 ; + END + END wd_in[77] + PIN wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.280 0.036 23.304 ; + END + END wd_in[78] + PIN wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.328 0.036 23.352 ; + END + END wd_in[79] + PIN wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.376 0.036 23.400 ; + END + END wd_in[80] + PIN wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.424 0.036 23.448 ; + END + END wd_in[81] + PIN wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.472 0.036 23.496 ; + END + END wd_in[82] + PIN wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.520 0.036 23.544 ; + END + END wd_in[83] + PIN wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.568 0.036 23.592 ; + END + END wd_in[84] + PIN wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.616 0.036 23.640 ; + END + END wd_in[85] + PIN wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.664 0.036 23.688 ; + END + END wd_in[86] + PIN wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.712 0.036 23.736 ; + END + END wd_in[87] + PIN wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.760 0.036 23.784 ; + END + END wd_in[88] + PIN wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.808 0.036 23.832 ; + END + END wd_in[89] + PIN wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.856 0.036 23.880 ; + END + END wd_in[90] + PIN wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.904 0.036 23.928 ; + END + END wd_in[91] + PIN wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.952 0.036 23.976 ; + END + END wd_in[92] + PIN wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.000 0.036 24.024 ; + END + END wd_in[93] + PIN wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.048 0.036 24.072 ; + END + END wd_in[94] + PIN wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.096 0.036 24.120 ; + END + END wd_in[95] + PIN wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.144 0.036 24.168 ; + END + END wd_in[96] + PIN wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.192 0.036 24.216 ; + END + END wd_in[97] + PIN wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.240 0.036 24.264 ; + END + END wd_in[98] + PIN wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.288 0.036 24.312 ; + END + END wd_in[99] + PIN wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.336 0.036 24.360 ; + END + END wd_in[100] + PIN wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.384 0.036 24.408 ; + END + END wd_in[101] + PIN wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.432 0.036 24.456 ; + END + END wd_in[102] + PIN wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.480 0.036 24.504 ; + END + END wd_in[103] + PIN wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.528 0.036 24.552 ; + END + END wd_in[104] + PIN wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.576 0.036 24.600 ; + END + END wd_in[105] + PIN wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.624 0.036 24.648 ; + END + END wd_in[106] + PIN wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.672 0.036 24.696 ; + END + END wd_in[107] + PIN wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.720 0.036 24.744 ; + END + END wd_in[108] + PIN wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.768 0.036 24.792 ; + END + END wd_in[109] + PIN wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.816 0.036 24.840 ; + END + END wd_in[110] + PIN wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.864 0.036 24.888 ; + END + END wd_in[111] + PIN wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.912 0.036 24.936 ; + END + END wd_in[112] + PIN wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.960 0.036 24.984 ; + END + END wd_in[113] + PIN wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.008 0.036 25.032 ; + END + END wd_in[114] + PIN wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.056 0.036 25.080 ; + END + END wd_in[115] + PIN wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.104 0.036 25.128 ; + END + END wd_in[116] + PIN wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.152 0.036 25.176 ; + END + END wd_in[117] + PIN wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.200 0.036 25.224 ; + END + END wd_in[118] + PIN wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.248 0.036 25.272 ; + END + END wd_in[119] + PIN wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.296 0.036 25.320 ; + END + END wd_in[120] + PIN wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.344 0.036 25.368 ; + END + END wd_in[121] + PIN wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.392 0.036 25.416 ; + END + END wd_in[122] + PIN wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.440 0.036 25.464 ; + END + END wd_in[123] + PIN wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.488 0.036 25.512 ; + END + END wd_in[124] + PIN wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.536 0.036 25.560 ; + END + END wd_in[125] + PIN wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.584 0.036 25.608 ; + END + END wd_in[126] + PIN wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.632 0.036 25.656 ; + END + END wd_in[127] + PIN wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.680 0.036 25.704 ; + END + END wd_in[128] + PIN wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.728 0.036 25.752 ; + END + END wd_in[129] + PIN wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.776 0.036 25.800 ; + END + END wd_in[130] + PIN wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.824 0.036 25.848 ; + END + END wd_in[131] + PIN wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.872 0.036 25.896 ; + END + END wd_in[132] + PIN wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.920 0.036 25.944 ; + END + END wd_in[133] + PIN wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.968 0.036 25.992 ; + END + END wd_in[134] + PIN wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.016 0.036 26.040 ; + END + END wd_in[135] + PIN wd_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.064 0.036 26.088 ; + END + END wd_in[136] + PIN wd_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.112 0.036 26.136 ; + END + END wd_in[137] + PIN wd_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.160 0.036 26.184 ; + END + END wd_in[138] + PIN wd_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.208 0.036 26.232 ; + END + END wd_in[139] + PIN wd_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.256 0.036 26.280 ; + END + END wd_in[140] + PIN wd_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.304 0.036 26.328 ; + END + END wd_in[141] + PIN wd_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.352 0.036 26.376 ; + END + END wd_in[142] + PIN wd_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.400 0.036 26.424 ; + END + END wd_in[143] + PIN wd_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.448 0.036 26.472 ; + END + END wd_in[144] + PIN wd_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.496 0.036 26.520 ; + END + END wd_in[145] + PIN wd_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.544 0.036 26.568 ; + END + END wd_in[146] + PIN wd_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.592 0.036 26.616 ; + END + END wd_in[147] + PIN wd_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.640 0.036 26.664 ; + END + END wd_in[148] + PIN wd_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.688 0.036 26.712 ; + END + END wd_in[149] + PIN wd_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.736 0.036 26.760 ; + END + END wd_in[150] + PIN wd_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.784 0.036 26.808 ; + END + END wd_in[151] + PIN wd_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.832 0.036 26.856 ; + END + END wd_in[152] + PIN wd_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.880 0.036 26.904 ; + END + END wd_in[153] + PIN wd_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.928 0.036 26.952 ; + END + END wd_in[154] + PIN wd_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.976 0.036 27.000 ; + END + END wd_in[155] + PIN wd_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.024 0.036 27.048 ; + END + END wd_in[156] + PIN wd_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.072 0.036 27.096 ; + END + END wd_in[157] + PIN wd_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.120 0.036 27.144 ; + END + END wd_in[158] + PIN wd_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.168 0.036 27.192 ; + END + END wd_in[159] + PIN wd_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.216 0.036 27.240 ; + END + END wd_in[160] + PIN wd_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.264 0.036 27.288 ; + END + END wd_in[161] + PIN wd_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.312 0.036 27.336 ; + END + END wd_in[162] + PIN wd_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.360 0.036 27.384 ; + END + END wd_in[163] + PIN wd_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.408 0.036 27.432 ; + END + END wd_in[164] + PIN wd_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.456 0.036 27.480 ; + END + END wd_in[165] + PIN wd_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.504 0.036 27.528 ; + END + END wd_in[166] + PIN wd_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.552 0.036 27.576 ; + END + END wd_in[167] + PIN wd_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.600 0.036 27.624 ; + END + END wd_in[168] + PIN wd_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.648 0.036 27.672 ; + END + END wd_in[169] + PIN wd_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.696 0.036 27.720 ; + END + END wd_in[170] + PIN wd_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.744 0.036 27.768 ; + END + END wd_in[171] + PIN wd_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.792 0.036 27.816 ; + END + END wd_in[172] + PIN wd_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.840 0.036 27.864 ; + END + END wd_in[173] + PIN wd_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.888 0.036 27.912 ; + END + END wd_in[174] + PIN wd_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.936 0.036 27.960 ; + END + END wd_in[175] + PIN wd_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.984 0.036 28.008 ; + END + END wd_in[176] + PIN wd_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.032 0.036 28.056 ; + END + END wd_in[177] + PIN wd_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.080 0.036 28.104 ; + END + END wd_in[178] + PIN wd_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.128 0.036 28.152 ; + END + END wd_in[179] + PIN wd_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.176 0.036 28.200 ; + END + END wd_in[180] + PIN wd_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.224 0.036 28.248 ; + END + END wd_in[181] + PIN wd_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.272 0.036 28.296 ; + END + END wd_in[182] + PIN wd_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.320 0.036 28.344 ; + END + END wd_in[183] + PIN wd_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.368 0.036 28.392 ; + END + END wd_in[184] + PIN wd_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.416 0.036 28.440 ; + END + END wd_in[185] + PIN wd_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.464 0.036 28.488 ; + END + END wd_in[186] + PIN wd_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.512 0.036 28.536 ; + END + END wd_in[187] + PIN wd_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.560 0.036 28.584 ; + END + END wd_in[188] + PIN wd_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.608 0.036 28.632 ; + END + END wd_in[189] + PIN wd_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.656 0.036 28.680 ; + END + END wd_in[190] + PIN wd_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.704 0.036 28.728 ; + END + END wd_in[191] + PIN wd_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.752 0.036 28.776 ; + END + END wd_in[192] + PIN wd_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.800 0.036 28.824 ; + END + END wd_in[193] + PIN wd_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.848 0.036 28.872 ; + END + END wd_in[194] + PIN wd_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.896 0.036 28.920 ; + END + END wd_in[195] + PIN wd_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.944 0.036 28.968 ; + END + END wd_in[196] + PIN wd_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.992 0.036 29.016 ; + END + END wd_in[197] + PIN wd_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.040 0.036 29.064 ; + END + END wd_in[198] + PIN wd_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.088 0.036 29.112 ; + END + END wd_in[199] + PIN wd_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.136 0.036 29.160 ; + END + END wd_in[200] + PIN wd_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.184 0.036 29.208 ; + END + END wd_in[201] + PIN wd_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.232 0.036 29.256 ; + END + END wd_in[202] + PIN wd_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.280 0.036 29.304 ; + END + END wd_in[203] + PIN wd_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.328 0.036 29.352 ; + END + END wd_in[204] + PIN wd_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.376 0.036 29.400 ; + END + END wd_in[205] + PIN wd_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.424 0.036 29.448 ; + END + END wd_in[206] + PIN wd_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.472 0.036 29.496 ; + END + END wd_in[207] + PIN wd_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.520 0.036 29.544 ; + END + END wd_in[208] + PIN wd_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.568 0.036 29.592 ; + END + END wd_in[209] + PIN wd_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.616 0.036 29.640 ; + END + END wd_in[210] + PIN wd_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.664 0.036 29.688 ; + END + END wd_in[211] + PIN wd_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.712 0.036 29.736 ; + END + END wd_in[212] + PIN wd_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.760 0.036 29.784 ; + END + END wd_in[213] + PIN wd_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.808 0.036 29.832 ; + END + END wd_in[214] + PIN wd_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.856 0.036 29.880 ; + END + END wd_in[215] + PIN wd_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.904 0.036 29.928 ; + END + END wd_in[216] + PIN wd_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.952 0.036 29.976 ; + END + END wd_in[217] + PIN wd_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.000 0.036 30.024 ; + END + END wd_in[218] + PIN wd_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.048 0.036 30.072 ; + END + END wd_in[219] + PIN wd_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.096 0.036 30.120 ; + END + END wd_in[220] + PIN wd_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.144 0.036 30.168 ; + END + END wd_in[221] + PIN wd_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.192 0.036 30.216 ; + END + END wd_in[222] + PIN wd_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.240 0.036 30.264 ; + END + END wd_in[223] + PIN wd_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.288 0.036 30.312 ; + END + END wd_in[224] + PIN wd_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.336 0.036 30.360 ; + END + END wd_in[225] + PIN wd_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.384 0.036 30.408 ; + END + END wd_in[226] + PIN wd_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.432 0.036 30.456 ; + END + END wd_in[227] + PIN wd_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.480 0.036 30.504 ; + END + END wd_in[228] + PIN wd_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.528 0.036 30.552 ; + END + END wd_in[229] + PIN wd_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.576 0.036 30.600 ; + END + END wd_in[230] + PIN wd_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.624 0.036 30.648 ; + END + END wd_in[231] + PIN wd_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.672 0.036 30.696 ; + END + END wd_in[232] + PIN wd_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.720 0.036 30.744 ; + END + END wd_in[233] + PIN wd_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.768 0.036 30.792 ; + END + END wd_in[234] + PIN wd_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.816 0.036 30.840 ; + END + END wd_in[235] + PIN wd_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.864 0.036 30.888 ; + END + END wd_in[236] + PIN wd_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.912 0.036 30.936 ; + END + END wd_in[237] + PIN wd_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.960 0.036 30.984 ; + END + END wd_in[238] + PIN wd_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.008 0.036 31.032 ; + END + END wd_in[239] + PIN wd_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.056 0.036 31.080 ; + END + END wd_in[240] + PIN wd_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.104 0.036 31.128 ; + END + END wd_in[241] + PIN wd_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.152 0.036 31.176 ; + END + END wd_in[242] + PIN wd_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.200 0.036 31.224 ; + END + END wd_in[243] + PIN wd_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.248 0.036 31.272 ; + END + END wd_in[244] + PIN wd_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.296 0.036 31.320 ; + END + END wd_in[245] + PIN wd_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.344 0.036 31.368 ; + END + END wd_in[246] + PIN wd_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.392 0.036 31.416 ; + END + END wd_in[247] + PIN wd_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.440 0.036 31.464 ; + END + END wd_in[248] + PIN wd_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.488 0.036 31.512 ; + END + END wd_in[249] + PIN wd_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.536 0.036 31.560 ; + END + END wd_in[250] + PIN wd_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.584 0.036 31.608 ; + END + END wd_in[251] + PIN wd_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.632 0.036 31.656 ; + END + END wd_in[252] + PIN wd_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.680 0.036 31.704 ; + END + END wd_in[253] + PIN wd_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.728 0.036 31.752 ; + END + END wd_in[254] + PIN wd_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.776 0.036 31.800 ; + END + END wd_in[255] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.024 0.036 39.048 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.072 0.036 39.096 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.120 0.036 39.144 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.168 0.036 39.192 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.216 0.036 39.240 ; + END + END addr_in[4] + PIN addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.264 0.036 39.288 ; + END + END addr_in[5] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.512 0.036 46.536 ; + END + END we_in + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.560 0.036 46.584 ; + END + END ce_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.608 0.036 46.632 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.096 0.000 33.154 0.096 ; + RECT 0.096 0.768 33.154 0.864 ; + RECT 0.096 1.536 33.154 1.632 ; + RECT 0.096 2.304 33.154 2.400 ; + RECT 0.096 3.072 33.154 3.168 ; + RECT 0.096 3.840 33.154 3.936 ; + RECT 0.096 4.608 33.154 4.704 ; + RECT 0.096 5.376 33.154 5.472 ; + RECT 0.096 6.144 33.154 6.240 ; + RECT 0.096 6.912 33.154 7.008 ; + RECT 0.096 7.680 33.154 7.776 ; + RECT 0.096 8.448 33.154 8.544 ; + RECT 0.096 9.216 33.154 9.312 ; + RECT 0.096 9.984 33.154 10.080 ; + RECT 0.096 10.752 33.154 10.848 ; + RECT 0.096 11.520 33.154 11.616 ; + RECT 0.096 12.288 33.154 12.384 ; + RECT 0.096 13.056 33.154 13.152 ; + RECT 0.096 13.824 33.154 13.920 ; + RECT 0.096 14.592 33.154 14.688 ; + RECT 0.096 15.360 33.154 15.456 ; + RECT 0.096 16.128 33.154 16.224 ; + RECT 0.096 16.896 33.154 16.992 ; + RECT 0.096 17.664 33.154 17.760 ; + RECT 0.096 18.432 33.154 18.528 ; + RECT 0.096 19.200 33.154 19.296 ; + RECT 0.096 19.968 33.154 20.064 ; + RECT 0.096 20.736 33.154 20.832 ; + RECT 0.096 21.504 33.154 21.600 ; + RECT 0.096 22.272 33.154 22.368 ; + RECT 0.096 23.040 33.154 23.136 ; + RECT 0.096 23.808 33.154 23.904 ; + RECT 0.096 24.576 33.154 24.672 ; + RECT 0.096 25.344 33.154 25.440 ; + RECT 0.096 26.112 33.154 26.208 ; + RECT 0.096 26.880 33.154 26.976 ; + RECT 0.096 27.648 33.154 27.744 ; + RECT 0.096 28.416 33.154 28.512 ; + RECT 0.096 29.184 33.154 29.280 ; + RECT 0.096 29.952 33.154 30.048 ; + RECT 0.096 30.720 33.154 30.816 ; + RECT 0.096 31.488 33.154 31.584 ; + RECT 0.096 32.256 33.154 32.352 ; + RECT 0.096 33.024 33.154 33.120 ; + RECT 0.096 33.792 33.154 33.888 ; + RECT 0.096 34.560 33.154 34.656 ; + RECT 0.096 35.328 33.154 35.424 ; + RECT 0.096 36.096 33.154 36.192 ; + RECT 0.096 36.864 33.154 36.960 ; + RECT 0.096 37.632 33.154 37.728 ; + RECT 0.096 38.400 33.154 38.496 ; + RECT 0.096 39.168 33.154 39.264 ; + RECT 0.096 39.936 33.154 40.032 ; + RECT 0.096 40.704 33.154 40.800 ; + RECT 0.096 41.472 33.154 41.568 ; + RECT 0.096 42.240 33.154 42.336 ; + RECT 0.096 43.008 33.154 43.104 ; + RECT 0.096 43.776 33.154 43.872 ; + RECT 0.096 44.544 33.154 44.640 ; + RECT 0.096 45.312 33.154 45.408 ; + RECT 0.096 46.080 33.154 46.176 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.096 0.384 33.154 0.480 ; + RECT 0.096 1.152 33.154 1.248 ; + RECT 0.096 1.920 33.154 2.016 ; + RECT 0.096 2.688 33.154 2.784 ; + RECT 0.096 3.456 33.154 3.552 ; + RECT 0.096 4.224 33.154 4.320 ; + RECT 0.096 4.992 33.154 5.088 ; + RECT 0.096 5.760 33.154 5.856 ; + RECT 0.096 6.528 33.154 6.624 ; + RECT 0.096 7.296 33.154 7.392 ; + RECT 0.096 8.064 33.154 8.160 ; + RECT 0.096 8.832 33.154 8.928 ; + RECT 0.096 9.600 33.154 9.696 ; + RECT 0.096 10.368 33.154 10.464 ; + RECT 0.096 11.136 33.154 11.232 ; + RECT 0.096 11.904 33.154 12.000 ; + RECT 0.096 12.672 33.154 12.768 ; + RECT 0.096 13.440 33.154 13.536 ; + RECT 0.096 14.208 33.154 14.304 ; + RECT 0.096 14.976 33.154 15.072 ; + RECT 0.096 15.744 33.154 15.840 ; + RECT 0.096 16.512 33.154 16.608 ; + RECT 0.096 17.280 33.154 17.376 ; + RECT 0.096 18.048 33.154 18.144 ; + RECT 0.096 18.816 33.154 18.912 ; + RECT 0.096 19.584 33.154 19.680 ; + RECT 0.096 20.352 33.154 20.448 ; + RECT 0.096 21.120 33.154 21.216 ; + RECT 0.096 21.888 33.154 21.984 ; + RECT 0.096 22.656 33.154 22.752 ; + RECT 0.096 23.424 33.154 23.520 ; + RECT 0.096 24.192 33.154 24.288 ; + RECT 0.096 24.960 33.154 25.056 ; + RECT 0.096 25.728 33.154 25.824 ; + RECT 0.096 26.496 33.154 26.592 ; + RECT 0.096 27.264 33.154 27.360 ; + RECT 0.096 28.032 33.154 28.128 ; + RECT 0.096 28.800 33.154 28.896 ; + RECT 0.096 29.568 33.154 29.664 ; + RECT 0.096 30.336 33.154 30.432 ; + RECT 0.096 31.104 33.154 31.200 ; + RECT 0.096 31.872 33.154 31.968 ; + RECT 0.096 32.640 33.154 32.736 ; + RECT 0.096 33.408 33.154 33.504 ; + RECT 0.096 34.176 33.154 34.272 ; + RECT 0.096 34.944 33.154 35.040 ; + RECT 0.096 35.712 33.154 35.808 ; + RECT 0.096 36.480 33.154 36.576 ; + RECT 0.096 37.248 33.154 37.344 ; + RECT 0.096 38.016 33.154 38.112 ; + RECT 0.096 38.784 33.154 38.880 ; + RECT 0.096 39.552 33.154 39.648 ; + RECT 0.096 40.320 33.154 40.416 ; + RECT 0.096 41.088 33.154 41.184 ; + RECT 0.096 41.856 33.154 41.952 ; + RECT 0.096 42.624 33.154 42.720 ; + RECT 0.096 43.392 33.154 43.488 ; + RECT 0.096 44.160 33.154 44.256 ; + RECT 0.096 44.928 33.154 45.024 ; + RECT 0.096 45.696 33.154 45.792 ; + RECT 0.096 46.464 33.154 46.560 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 33.250 46.800 ; + LAYER M2 ; + RECT 0 0 33.250 46.800 ; + LAYER M3 ; + RECT 0 0 33.250 46.800 ; + LAYER M4 ; + RECT 0 0 33.250 46.800 ; + END +END fakeram7_64x256 + +END LIBRARY diff --git a/flow/platforms/asap7/lef/fakeram7_64x28.lef b/flow/platforms/asap7/lef/fakeram7_64x28.lef new file mode 100644 index 0000000000..725ac02163 --- /dev/null +++ b/flow/platforms/asap7/lef/fakeram7_64x28.lef @@ -0,0 +1,644 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO fakeram7_64x28 + PROPERTY width 28 ; + PROPERTY depth 64 ; + PROPERTY banks 4 ; + FOREIGN fakeram7_64x28 0 0 ; + SYMMETRY X Y R90 ; + SIZE 14.630 BY 6.000 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.036 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.096 0.036 0.120 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.144 0.036 0.168 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.192 0.036 0.216 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.240 0.036 0.264 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.288 0.036 0.312 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.036 0.360 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.384 0.036 0.408 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.432 0.036 0.456 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.480 0.036 0.504 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.528 0.036 0.552 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.576 0.036 0.600 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.036 0.648 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.672 0.036 0.696 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.720 0.036 0.744 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.768 0.036 0.792 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.816 0.036 0.840 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.864 0.036 0.888 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.036 0.936 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.960 0.036 0.984 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.008 0.036 1.032 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.056 0.036 1.080 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.104 0.036 1.128 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.152 0.036 1.176 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.036 1.224 ; + END + END rd_out[24] + PIN rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.248 0.036 1.272 ; + END + END rd_out[25] + PIN rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.296 0.036 1.320 ; + END + END rd_out[26] + PIN rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.344 0.036 1.368 ; + END + END rd_out[27] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.304 0.036 2.328 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.036 2.376 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.400 0.036 2.424 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.448 0.036 2.472 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.036 2.520 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.544 0.036 2.568 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.592 0.036 2.616 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.640 0.036 2.664 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.688 0.036 2.712 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.736 0.036 2.760 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.036 2.808 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.832 0.036 2.856 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.880 0.036 2.904 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.036 2.952 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.976 0.036 3.000 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.024 0.036 3.048 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.036 3.096 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.120 0.036 3.144 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.168 0.036 3.192 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.036 3.240 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.264 0.036 3.288 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.312 0.036 3.336 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.036 3.384 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.408 0.036 3.432 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.456 0.036 3.480 ; + END + END wd_in[24] + PIN wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.504 0.036 3.528 ; + END + END wd_in[25] + PIN wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.552 0.036 3.576 ; + END + END wd_in[26] + PIN wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.600 0.036 3.624 ; + END + END wd_in[27] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.560 0.036 4.584 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.608 0.036 4.632 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.656 0.036 4.680 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.704 0.036 4.728 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.752 0.036 4.776 ; + END + END addr_in[4] + PIN addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.036 4.824 ; + END + END addr_in[5] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.760 0.036 5.784 ; + END + END we_in + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.036 5.832 ; + END + END ce_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.856 0.036 5.880 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.096 0.000 14.534 0.096 ; + RECT 0.096 0.768 14.534 0.864 ; + RECT 0.096 1.536 14.534 1.632 ; + RECT 0.096 2.304 14.534 2.400 ; + RECT 0.096 3.072 14.534 3.168 ; + RECT 0.096 3.840 14.534 3.936 ; + RECT 0.096 4.608 14.534 4.704 ; + RECT 0.096 5.376 14.534 5.472 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.096 0.384 14.534 0.480 ; + RECT 0.096 1.152 14.534 1.248 ; + RECT 0.096 1.920 14.534 2.016 ; + RECT 0.096 2.688 14.534 2.784 ; + RECT 0.096 3.456 14.534 3.552 ; + RECT 0.096 4.224 14.534 4.320 ; + RECT 0.096 4.992 14.534 5.088 ; + RECT 0.096 5.760 14.534 5.856 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 14.630 6.000 ; + LAYER M2 ; + RECT 0 0 14.630 6.000 ; + LAYER M3 ; + RECT 0 0 14.630 6.000 ; + LAYER M4 ; + RECT 0 0 14.630 6.000 ; + END +END fakeram7_64x28 + +END LIBRARY diff --git a/flow/platforms/asap7/lib/NLDM/fakeram7_128x64.lib b/flow/platforms/asap7/lib/NLDM/fakeram7_128x64.lib new file mode 100644 index 0000000000..8bcf2d6ae7 --- /dev/null +++ b/flow/platforms/asap7/lib/NLDM/fakeram7_128x64.lib @@ -0,0 +1,389 @@ +library(fakeram7_128x64) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2025-06-10 17:10:26Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram7_128x64_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram7_128x64_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram7_128x64_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram7_128x64_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram7_128x64_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram7_128x64_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } + type (fakeram7_128x64_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram7_128x64) { + area : 343.985; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 64; + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram7_128x64_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram7_128x64_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rd_out) { + bus_type : fakeram7_128x64_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram7_128x64_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram7_128x64_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram7_128x64_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram7_128x64_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(ce_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_in) { + bus_type : fakeram7_128x64_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(wd_in) { + bus_type : fakeram7_128x64_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/flow/platforms/asap7/lib/NLDM/fakeram7_64x25.lib b/flow/platforms/asap7/lib/NLDM/fakeram7_64x25.lib new file mode 100644 index 0000000000..1afa95f09b --- /dev/null +++ b/flow/platforms/asap7/lib/NLDM/fakeram7_64x25.lib @@ -0,0 +1,389 @@ +library(fakeram7_64x25) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2025-06-10 17:10:26Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram7_64x25_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram7_64x25_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram7_64x25_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram7_64x25_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram7_64x25_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram7_64x25_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 25; + bit_from : 24; + bit_to : 0 ; + downto : true ; + } + type (fakeram7_64x25_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram7_64x25) { + area : 67.185; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 25; + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram7_64x25_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram7_64x25_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rd_out) { + bus_type : fakeram7_64x25_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram7_64x25_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram7_64x25_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram7_64x25_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram7_64x25_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(ce_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_in) { + bus_type : fakeram7_64x25_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(wd_in) { + bus_type : fakeram7_64x25_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/flow/platforms/asap7/lib/NLDM/fakeram7_64x256.lib b/flow/platforms/asap7/lib/NLDM/fakeram7_64x256.lib new file mode 100644 index 0000000000..8282373b44 --- /dev/null +++ b/flow/platforms/asap7/lib/NLDM/fakeram7_64x256.lib @@ -0,0 +1,389 @@ +library(fakeram7_64x256) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2025-06-12 00:08:06Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram7_64x256_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram7_64x256_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram7_64x256_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram7_64x256_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram7_64x256_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram7_64x256_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 256; + bit_from : 255; + bit_to : 0 ; + downto : true ; + } + type (fakeram7_64x256_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram7_64x256) { + area : 1517.411; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 256; + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram7_64x256_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram7_64x256_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rd_out) { + bus_type : fakeram7_64x256_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram7_64x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram7_64x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram7_64x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram7_64x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(ce_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_in) { + bus_type : fakeram7_64x256_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(wd_in) { + bus_type : fakeram7_64x256_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/flow/platforms/asap7/lib/NLDM/fakeram7_64x28.lib b/flow/platforms/asap7/lib/NLDM/fakeram7_64x28.lib new file mode 100644 index 0000000000..1681b2bf1f --- /dev/null +++ b/flow/platforms/asap7/lib/NLDM/fakeram7_64x28.lib @@ -0,0 +1,389 @@ +library(fakeram7_64x28) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2025-06-10 17:10:26Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram7_64x28_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram7_64x28_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram7_64x28_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram7_64x28_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram7_64x28_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram7_64x28_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 28; + bit_from : 27; + bit_to : 0 ; + downto : true ; + } + type (fakeram7_64x28_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram7_64x28) { + area : 75.247; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 28; + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram7_64x28_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram7_64x28_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rd_out) { + bus_type : fakeram7_64x28_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram7_64x28_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram7_64x28_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram7_64x28_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram7_64x28_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(ce_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_in) { + bus_type : fakeram7_64x28_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(wd_in) { + bus_type : fakeram7_64x28_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/flow/platforms/asap7/ram/cva6.cfg b/flow/platforms/asap7/ram/cva6.cfg new file mode 100644 index 0000000000..a7d378fa0e --- /dev/null +++ b/flow/platforms/asap7/ram/cva6.cfg @@ -0,0 +1,50 @@ +#SAMPLE INPUT FILE; VALUES NOT REALISTIC +{ + # The process node. + "tech_nm": 7, + + # The operating voltage. + "voltage": 0.7, + + # String to add in front of every metal layer number for the layer name. + "metal_prefix": "M", + + # Horizontal Metal layer for macro pins + "metal_layer": "M4", + + # The pin width for signal pins. + "pin_width_nm": 24, + + # The minimum pin pitch for signal pins + "pin_pitch_nm": 48, + + # Metal track pitch + "metal_track_pitch_nm": 48, + + # Manufacturing Grid + "manufacturing_grid_nm": 1, + + # Contacted Poly Pitch + "contacted_poly_pitch_nm": 54, + + #column mux factor + "column_mux_factor": 1, + + # Fin pitch + "fin_pitch_nm" : 27, + + # Optional snap the width and height of the sram to a multiple value. + "snap_width_nm": 190, + "snap_height_nm": 1200, + + # List of SRAM configurations (name width depth and banks) + "srams": [ + {"name": "fakeram7_64x28", "width": 28, "depth": 64, "banks": 4}, + {"name": "fakeram7_128x64", "width": 64, "depth": 128, "banks": 2}, + {"name": "fakeram7_64x25", "width": 25, "depth": 64, "banks": 4}, + {"name": "fakeram7_64x256", "width": 256, "depth": 64, "banks": 1, + "additional_height": 25} + ] + + # TENTATIVE PARAMETERS +} diff --git a/flow/platforms/asap7/verilog/fakeram7_128x64.sv b/flow/platforms/asap7/verilog/fakeram7_128x64.sv new file mode 100644 index 0000000000..d7353e1c65 --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram7_128x64.sv @@ -0,0 +1,10 @@ +(* blackbox *) +module fakeram7_128x64 ( + output reg [63:0] rd_out, + input [6:0] addr_in, + input we_in, + input [63:0] wd_in, + input clk, + input ce_in +); +endmodule diff --git a/flow/platforms/asap7/verilog/fakeram7_64x25.sv b/flow/platforms/asap7/verilog/fakeram7_64x25.sv new file mode 100644 index 0000000000..4d2c60724d --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram7_64x25.sv @@ -0,0 +1,10 @@ +(* blackbox *) +module fakeram7_64x25 ( + output reg [24:0] rd_out, + input [5:0] addr_in, + input we_in, + input [24:0] wd_in, + input clk, + input ce_in +); +endmodule diff --git a/flow/platforms/asap7/verilog/fakeram7_64x256.sv b/flow/platforms/asap7/verilog/fakeram7_64x256.sv new file mode 100644 index 0000000000..b87ffae7d7 --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram7_64x256.sv @@ -0,0 +1,10 @@ +(* blackbox *) +module fakeram7_64x256 ( + output reg [255:0] rd_out, + input [5:0] addr_in, + input we_in, + input [255:0] wd_in, + input clk, + input ce_in +); +endmodule diff --git a/flow/platforms/asap7/verilog/fakeram7_64x28.sv b/flow/platforms/asap7/verilog/fakeram7_64x28.sv new file mode 100644 index 0000000000..7ed704addd --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram7_64x28.sv @@ -0,0 +1,10 @@ +(* blackbox *) +module fakeram7_64x28 ( + output reg [27:0] rd_out, + input [5:0] addr_in, + input we_in, + input [27:0] wd_in, + input clk, + input ce_in +); +endmodule From 7318b161159137ba6cefaef4c9da1288370ad42e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 14 Jun 2025 00:19:26 +0200 Subject: [PATCH 064/198] Update OR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index 8b99478b07..39f7798d12 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 8b99478b07bf08f0b32ebbd7c58673b1724d3c4c +Subproject commit 39f7798d126357485481f3e75ad7e63c31070e05 From 5ef34aa5700514aaf0858d957d3b5372a413b4c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 14 Jun 2025 00:20:03 +0200 Subject: [PATCH 065/198] Tune gf12/bp_single cts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- flow/designs/gf12/bp_single/config.mk | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/flow/designs/gf12/bp_single/config.mk b/flow/designs/gf12/bp_single/config.mk index ef20c6cdc1..83e6a775b3 100644 --- a/flow/designs/gf12/bp_single/config.mk +++ b/flow/designs/gf12/bp_single/config.mk @@ -66,7 +66,8 @@ else export DESIGN_TYPE = CHIP_NODEN endif -export CTS_ARGS = -no_insertion_delay +# Override cts arguments to set `-no_insertion_delay` +export CTS_ARGS = -no_insertion_delay -sink_clustering_enable -balance_levels -repair_clock_nets # enable slack margin for setup and hold fix after CTS export SETUP_SLACK_MARGIN ?= 100 From 6963c57e62bd759e36127b718cecd22204ca42c1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 14 Jun 2025 00:28:18 +0200 Subject: [PATCH 066/198] Insert per-design workarounds for flow issues MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- flow/designs/nangate45/aes/config.mk | 2 ++ flow/designs/sky130hd/jpeg/config.mk | 3 +++ 2 files changed, 5 insertions(+) diff --git a/flow/designs/nangate45/aes/config.mk b/flow/designs/nangate45/aes/config.mk index f653445292..7008a46a9f 100644 --- a/flow/designs/nangate45/aes/config.mk +++ b/flow/designs/nangate45/aes/config.mk @@ -11,3 +11,5 @@ export PLACE_DENSITY_LB_ADDON = 0.20 export TNS_END_PERCENT = 100 export REMOVE_CELLS_FOR_EQY = TAPCELL* +# workaround for high congestion in post-grt repair +export SKIP_INCREMENTAL_REPAIR = 1 diff --git a/flow/designs/sky130hd/jpeg/config.mk b/flow/designs/sky130hd/jpeg/config.mk index dced6f2bca..995fbeda5f 100644 --- a/flow/designs/sky130hd/jpeg/config.mk +++ b/flow/designs/sky130hd/jpeg/config.mk @@ -13,3 +13,6 @@ export TNS_END_PERCENT = 100 export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl export REMOVE_ABC_BUFFERS = 1 + +# workaround for density growing to 0.91 from adjustments on TD/RD iterations +export GPL_ROUTABILITY_DRIVEN = 0 From f5a36bba10b3b9e3c4d2676bde49733369c5cde7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 14 Jun 2025 10:10:19 +0200 Subject: [PATCH 067/198] Update failing metrics MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit designs/sky130hd/aes/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | finish__timing__setup__ws | -0.25 | -0.61 | Failing | designs/sky130hd/chameleon/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | globalroute__antenna_diodes_count | 72 | 196 | Failing | designs/sky130hd/microwatt/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | globalroute__antenna_diodes_count | 5426 | 2476 | Tighten | | detailedroute__route__wirelength | 11745555 | 10026505 | Tighten | | detailedroute__antenna__violating__nets | 0 | 1 | Failing | | finish__timing__setup__ws | -1.96 | -3.13 | Failing | | finish__timing__drv__hold_violation_count | 104 | 262 | Failing | designs/sky130hd/riscv32i/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | placeopt__design__instance__area | 82077 | 81702 | Tighten | | globalroute__antenna_diodes_count | 21 | 10 | Tighten | | detailedroute__route__wirelength | 303859 | 301382 | Tighten | | detailedroute__antenna_diodes_count | 10 | 18 | Failing | | finish__design__instance__area | 95514 | 94909 | Tighten | designs/sky130hs/jpeg/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | globalroute__antenna_diodes_count | 112 | 60 | Tighten | | detailedroute__route__wirelength | 1630300 | 1619030 | Tighten | | detailedroute__antenna_diodes_count | 66 | 164 | Failing | Signed-off-by: Martin Povišer --- flow/designs/sky130hd/aes/rules-base.json | 2 +- flow/designs/sky130hd/chameleon/rules-base.json | 2 +- flow/designs/sky130hd/microwatt/rules-base.json | 12 ++++++------ flow/designs/sky130hd/riscv32i/rules-base.json | 10 +++++----- flow/designs/sky130hs/jpeg/rules-base.json | 6 +++--- 5 files changed, 16 insertions(+), 16 deletions(-) diff --git a/flow/designs/sky130hd/aes/rules-base.json b/flow/designs/sky130hd/aes/rules-base.json index 5780ad53ca..8427199c0d 100644 --- a/flow/designs/sky130hd/aes/rules-base.json +++ b/flow/designs/sky130hd/aes/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.25, + "value": -0.61, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/sky130hd/chameleon/rules-base.json b/flow/designs/sky130hd/chameleon/rules-base.json index 912aabd711..de98b6d05b 100644 --- a/flow/designs/sky130hd/chameleon/rules-base.json +++ b/flow/designs/sky130hd/chameleon/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 72, + "value": 196, "compare": "<=" }, "detailedroute__route__wirelength": { diff --git a/flow/designs/sky130hd/microwatt/rules-base.json b/flow/designs/sky130hd/microwatt/rules-base.json index 39d00082c8..b9c83b9ba2 100644 --- a/flow/designs/sky130hd/microwatt/rules-base.json +++ b/flow/designs/sky130hd/microwatt/rules-base.json @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 5426, + "value": 2476, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 11745555, + "value": 10026505, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -40,7 +40,7 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 0, + "value": 1, "compare": "<=" }, "detailedroute__antenna_diodes_count": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.96, + "value": -3.13, "compare": ">=" }, "finish__design__instance__area": { @@ -60,11 +60,11 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 104, + "value": 262, "compare": "<=" }, "finish__timing__wns_percent_delay": { "value": -17.68, "compare": ">=" } -} +} \ No newline at end of file diff --git a/flow/designs/sky130hd/riscv32i/rules-base.json b/flow/designs/sky130hd/riscv32i/rules-base.json index 38a3907180..c1df764f6c 100644 --- a/flow/designs/sky130hd/riscv32i/rules-base.json +++ b/flow/designs/sky130hd/riscv32i/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 82077, + "value": 81702, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 21, + "value": 10, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 303859, + "value": 301382, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 10, + "value": 18, "compare": "<=" }, "finish__timing__setup__ws": { @@ -52,7 +52,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 95514, + "value": 94909, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { diff --git a/flow/designs/sky130hs/jpeg/rules-base.json b/flow/designs/sky130hs/jpeg/rules-base.json index 06033c035a..181da8a088 100644 --- a/flow/designs/sky130hs/jpeg/rules-base.json +++ b/flow/designs/sky130hs/jpeg/rules-base.json @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 112, + "value": 60, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1630300, + "value": 1619030, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 66, + "value": 164, "compare": "<=" }, "finish__timing__setup__ws": { From 420a15b0dd72a7514bb42699237eb1d0ab85057e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 14 Jun 2025 14:50:41 +0200 Subject: [PATCH 068/198] Update one more design MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit designs/ihp-sg13g2/spi/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | finish__timing__drv__setup_violation_count | 8 | 10 | Failing | | finish__timing__wns_percent_delay | -15.74 | -15.68 | Tighten | Signed-off-by: Martin Povišer --- flow/designs/ihp-sg13g2/spi/rules-base.json | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/flow/designs/ihp-sg13g2/spi/rules-base.json b/flow/designs/ihp-sg13g2/spi/rules-base.json index d2611dfd68..48f784b4d5 100644 --- a/flow/designs/ihp-sg13g2/spi/rules-base.json +++ b/flow/designs/ihp-sg13g2/spi/rules-base.json @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 8, + "value": 10, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -15.74, + "value": -15.68, "compare": ">=" } } \ No newline at end of file From d528d9e2c8a75bab200f124fb51ee2bfce46bbcf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Sat, 14 Jun 2025 11:12:59 +0200 Subject: [PATCH 069/198] dependencies: remove sole Perl dependency in ORFS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Python is endemic, Perl was used in one place Signed-off-by: Øyvind Harboe --- flow/Makefile | 4 ++- flow/util/merge_lib.py | 56 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+), 1 deletion(-) create mode 100755 flow/util/merge_lib.py diff --git a/flow/Makefile b/flow/Makefile index 49824ab844..7095f6092f 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -207,7 +207,9 @@ $(DONT_USE_LIBS): $$(filter %$$(@F) %$$(@F).gz,$(LIB_FILES)) $(PYTHON_EXE) $(UTILS_DIR)/preprocessLib.py -i $^ -o $@ $(OBJECTS_DIR)/lib/merged.lib: $(DONT_USE_LIBS) - $(UTILS_DIR)/mergeLib.pl $(PLATFORM)_merged $(DONT_USE_LIBS) > $@ + $(UTILS_DIR)/mergeLib.pl $(PLATFORM)_merged $(DONT_USE_LIBS) > $@.old + $(PYTHON_EXE) $(UTILS_DIR)/merge_lib.py $(PLATFORM)_merged $(DONT_USE_LIBS) > $@ + diff -u $@.old $@ || (echo "Merged library differs from original!"; exit 1) # Pre-process KLayout tech # ============================================================================== diff --git a/flow/util/merge_lib.py b/flow/util/merge_lib.py new file mode 100755 index 0000000000..961b5e2330 --- /dev/null +++ b/flow/util/merge_lib.py @@ -0,0 +1,56 @@ +#!/usr/bin/env python3 + +import re +import sys + + +def process_header(filename, sclname): + with open(filename, "r") as fh: + for line in fh: + if re.search(r"library\s*\(", line): + print(f"library ({sclname}) {{") + continue + if re.match(r"^[\t ]*cell\s*\(", line): + break + print(line, end="") + + +def process_cells(filename): + with open(filename, "r") as fh: + flag = 0 # brace depth + for line in fh: + # Match 'cell ( ... )' with optional whitespace + if re.match(r"^[\t ]*cell\s*\(", line): + if flag != 0: + raise RuntimeError( + "Error! new cell before finishing the previous one!" + ) + print() # print blank line like Perl + print(line, end="") + flag = 1 # entering a cell block + elif flag > 0: + # Increase/decrease brace depth + flag += line.count("{") + flag -= line.count("}") + print(line, end="") + + # Optionally: reset flag to 0 here if it's finished + # But not necessary unless you're adding post-processing + + +def main(): + if len(sys.argv) < 3: + print("use: mergeLib.py new_library_name lib1 lib2 lib3 ....") + sys.exit(1) + + sclname = sys.argv[1] + files = sys.argv[2:] + + process_header(files[0], sclname) + for file in files: + process_cells(file) + print("\n}") + + +if __name__ == "__main__": + main() From c44fb335173c541ac99527d76be2148ac7c4a60d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Sat, 14 Jun 2025 17:34:36 +0200 Subject: [PATCH 070/198] dependencies: remove mergeLib.pl after proving .py identical MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/Makefile | 2 -- flow/util/mergeLib.pl | 61 ------------------------------------------- 2 files changed, 63 deletions(-) delete mode 100755 flow/util/mergeLib.pl diff --git a/flow/Makefile b/flow/Makefile index 7095f6092f..dfadc5ebfd 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -207,9 +207,7 @@ $(DONT_USE_LIBS): $$(filter %$$(@F) %$$(@F).gz,$(LIB_FILES)) $(PYTHON_EXE) $(UTILS_DIR)/preprocessLib.py -i $^ -o $@ $(OBJECTS_DIR)/lib/merged.lib: $(DONT_USE_LIBS) - $(UTILS_DIR)/mergeLib.pl $(PLATFORM)_merged $(DONT_USE_LIBS) > $@.old $(PYTHON_EXE) $(UTILS_DIR)/merge_lib.py $(PLATFORM)_merged $(DONT_USE_LIBS) > $@ - diff -u $@.old $@ || (echo "Merged library differs from original!"; exit 1) # Pre-process KLayout tech # ============================================================================== diff --git a/flow/util/mergeLib.pl b/flow/util/mergeLib.pl deleted file mode 100755 index 146a75febf..0000000000 --- a/flow/util/mergeLib.pl +++ /dev/null @@ -1,61 +0,0 @@ -#!/usr/bin/env perl - -# This script is sourced from Brown (with slight modifications). It merges -# several timing libraries into one. -# ------------------------------------------------------------------------------ - -use strict; -use warnings; - -my $sclname = $ARGV[0]; -shift @ARGV; -my $cnt = @ARGV; - -if($cnt>0){ - process_header($ARGV[0]); - my $file; - foreach my $file (@ARGV) { - process_cells($file) - } - print "\n}\n"; -} else { - print "use: mergeLib.pl new_library_name lib1 lib2 lib3 ...."; -} - - -sub process_header { - my $filename = shift; - open(my $fh, '<', $filename) or die "Could not open file $filename $!"; - while (<$fh>) { - if(/library\s*\(/) { - print "library ($sclname) {\n"; - next; - } - last if(/^[\t\s]*cell\s*\(/); - print $_; - } - close($fh) -} - -sub process_cells { - my $filename = shift; - - open(my $fh, '<', $filename) or die "Could not open file $filename $!"; - - my $flag = 0; - # cut the cells - while (<$fh>) { - #chomp $_; - if(/^[\t\s]*cell\s*\(/) {#&& $flag==0){ - die "Error! new cell before finishing the previous one!\n" if($flag!=0); - print "\n$_"; - $flag=1; - } elsif($flag > 0){ - $flag++ if(/\{/); - $flag-- if(/\}/); - #print "...}\n" if($flag==0); - print "$_"; - } - } - close($fh) -} From 8cee861011b88364eb530b224b4ee181743f94f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 14 Jun 2025 18:15:26 +0200 Subject: [PATCH 071/198] Point OR submodule to master MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- .gitmodules | 2 +- tools/OpenROAD | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 4afc70f8bb..ec90369ba8 100644 --- a/.gitmodules +++ b/.gitmodules @@ -3,7 +3,7 @@ url = ../../The-OpenROAD-Project/yosys.git [submodule "tools/OpenROAD"] path = tools/OpenROAD - url = ../../The-OpenROAD-Project-staging/OpenROAD.git + url = ../OpenROAD.git [submodule "tools/yosys-slang"] path = tools/yosys-slang url = https://github.com/povik/yosys-slang.git diff --git a/tools/OpenROAD b/tools/OpenROAD index 39f7798d12..a9002cfe20 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 39f7798d126357485481f3e75ad7e63c31070e05 +Subproject commit a9002cfe2000a9c297bb4b6ff8b3d2e8bf6cc65e From decb154e4d40ed7f64a6f08540dccb0a6cbeda01 Mon Sep 17 00:00:00 2001 From: LucasYuki Date: Mon, 16 Jun 2025 12:21:38 -0300 Subject: [PATCH 072/198] update klayout checksum for ubuntu 20.04 Signed-off-by: LucasYuki --- etc/DependencyInstaller.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/etc/DependencyInstaller.sh b/etc/DependencyInstaller.sh index 769758230b..abd9993c8b 100755 --- a/etc/DependencyInstaller.sh +++ b/etc/DependencyInstaller.sh @@ -170,7 +170,7 @@ _installUbuntuPackages() { fi else if [[ $1 == 20.04 ]]; then - klayoutChecksum=15a26f74cf396d8a10b7985ed70ab135 + klayoutChecksum=f78d41edf5bcfa5f1990bde1a9307e9e else klayoutChecksum=54748a49e1ab53e14cf5bf95feb2f25a fi From 8227b4909e2f45869e9f9515d003f0d18ae83cbd Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Mon, 16 Jun 2025 11:42:19 -0700 Subject: [PATCH 073/198] asap7 cva6 - switch to use SLVT library for CTS Signed-off-by: Jeff Ng --- flow/designs/asap7/cva6/config.mk | 8 ++++++-- flow/designs/asap7/cva6/rules-base.json | 20 ++++++++++---------- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/flow/designs/asap7/cva6/config.mk b/flow/designs/asap7/cva6/config.mk index 9412351da6..806cbaae13 100644 --- a/flow/designs/asap7/cva6/config.mk +++ b/flow/designs/asap7/cva6/config.mk @@ -88,10 +88,10 @@ export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x256.lib \ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc -export CORE_UTILIZATION = 40 +export CORE_UTILIZATION = 50 export CORE_MARGIN = 2 export MACRO_HALO = 5 -export PLACE_DENSITY = 0.50 +export PLACE_DENSITY = 0.64 # a smoketest for this option, there are a # few last gasp iterations @@ -101,3 +101,7 @@ export SKIP_LAST_GASP ?= 1 export SYNTH_MINIMUM_KEEP_SIZE ?= 40000 export SYNTH_HDL_FRONTEND = slang + +export ASAP7_USE_VT = RVT LVT SLVT + +export CTS_LIB_NAME = asap7sc7p5t_INVBUF_SLVT_FF_nldm_211120 diff --git a/flow/designs/asap7/cva6/rules-base.json b/flow/designs/asap7/cva6/rules-base.json index c1014297b1..5a5f6c5deb 100644 --- a/flow/designs/asap7/cva6/rules-base.json +++ b/flow/designs/asap7/cva6/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 19930.01, + "value": 19725.15, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 23688, + "value": 20743, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 152015, + "value": 137118, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 13219, + "value": 11923, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 13219, + "value": 11923, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1332082, + "value": 1124948, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -147.23, + "value": -68.36, "compare": ">=" }, "finish__design__instance__area": { - "value": 23925, + "value": 20933, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 6609, + "value": 5962, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -16.08, + "value": -10.27, "compare": ">=" } } \ No newline at end of file From 161dd12bb0a89cb807852d48bd9f2dba71594b59 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Mon, 16 Jun 2025 18:17:21 -0300 Subject: [PATCH 074/198] update FlowVariables.md Signed-off-by: Eder Monteiro --- docs/user/FlowVariables.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index aae3928c65..109d1c4b1f 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -108,8 +108,8 @@ configuration file. | GUI_TIMING| Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc.| 1| | | HOLD_SLACK_MARGIN| Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix or underfix (negative value, terminate retiming before 0 or positive slack). floorplan.tcl uses min of HOLD_SLACK_MARGIN and 0 (default hold slack margin). This avoids overrepair in floorplan for hold by default, but allows skipping hold repair using a negative HOLD_SLACK_MARGIN. Exiting timing repair early is useful in exploration where the .sdc has a fixed clock period at the design's target clock period and where HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair (extremely long running times) when exploring different parameter settings. When an ideal clock is used, that is before CTS, a clock insertion delay of 0 is used in timing paths. This creates a mismatch between macros that have a .lib file from after CTS, when the clock is propagated. To mitigate this, OpenSTA will use subtract the clock insertion delay of macros when calculating timing with ideal clock. Provided that min_clock_tree_path and max_clock_tree_path are in the .lib file, which is the case for macros built with OpenROAD. This is less accurate than if OpenROAD had created a placeholder clock tree for timing estimation purposes prior to CTS. There will inevitably be inaccuracies in the timing calculation prior to CTS. Use a slack margin that is low enough, even negative, to avoid overrepair. Inaccuracies in the timing prior to CTS can also lead to underrepair, but there no obvious and simple way to avoid underrapir in these cases. Overrepair can lead to excessive runtimes in repair or too much buffering being added, which can present itself as congestion of hold cells or buffer cells. Another use of SETUP/HOLD_SLACK_MARGIN is design parameter exploration when trying to find the minimum clock period for a design. The SDC_FILE for a design can be quite complicated and instead of modifying the clock period in the SDC_FILE, which can be non-trivial, the clock period can be fixed at the target frequency and the SETUP/HOLD_SLACK_MARGIN can be swept to find a plausible current minimum clock period.| 0| | | IO_CONSTRAINTS| File path to the IO constraints .tcl file.| | | -| IO_PLACER_H| The metal layer on which to place the I/O pins horizontally (top and bottom of the die).| | | -| IO_PLACER_V| The metal layer on which to place the I/O pins vertically (sides of the die).| | | +| IO_PLACER_H| A list of metal layers on which the I/O pins are placed horizontally (top and bottom of the die).| | | +| IO_PLACER_V| A list of metal layers on which the I/O pins are placed vertically (sides of the die).| | | | IR_DROP_LAYER| Default metal layer to report IR drop.| | | | KLAYOUT_TECH_FILE| A mapping from LEF/DEF to GDS using the KLayout tool.| | | | LATCH_MAP_FILE| List of latches treated as a black box by Yosys.| | | From 58a7031c742b694347e5594c4dea77d9bad3ea8b Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Tue, 17 Jun 2025 00:01:15 +0000 Subject: [PATCH 075/198] Remove RESYNTH_TIMING_RECOVER & RESYNTH_AREA_RECOVER These were experimental and never worked that well. Signed-off-by: Matt Liberty --- flow/scripts/floorplan.tcl | 73 ------------------------------------- flow/scripts/variables.yaml | 12 ------ 2 files changed, 85 deletions(-) diff --git a/flow/scripts/floorplan.tcl b/flow/scripts/floorplan.tcl index 259e97d57f..69133bc58a 100644 --- a/flow/scripts/floorplan.tcl +++ b/flow/scripts/floorplan.tcl @@ -110,84 +110,11 @@ if { [env_var_equals REMOVE_ABC_BUFFERS 1] } { repair_timing_helper 0 } -##### Restructure for timing ######### -if { [env_var_equals RESYNTH_TIMING_RECOVER 1] } { - repair_design_helper - repair_timing_helper - # pre restructure area/timing report (ideal clocks) - puts "Post synth-opt area" - report_design_area - report_worst_slack -min -digits 3 - puts "Post synth-opt wns" - report_worst_slack -max -digits 3 - puts "Post synth-opt tns" - report_tns -digits 3 - - write_verilog $::env(RESULTS_DIR)/2_pre_abc_timing.v - - restructure -target timing -liberty_file $::env(DONT_USE_SC_LIB) \ - -work_dir $::env(RESULTS_DIR) - - write_verilog $::env(RESULTS_DIR)/2_post_abc_timing.v - - # post restructure area/timing report (ideal clocks) - remove_buffers - repair_design_helper - repair_timing_helper - - puts "Post restructure-opt wns" - report_worst_slack -max -digits 3 - puts "Post restructure-opt tns" - report_tns -digits 3 - - # remove buffers inserted by optimization - remove_buffers -} - - puts "Default units for flow" report_units report_units_metric report_metrics 2 "floorplan final" false false -if { [env_var_equals RESYNTH_AREA_RECOVER 1] } { - - utl::push_metrics_stage "floorplan__{}__pre_restruct" - set num_instances [llength [get_cells -hier *]] - puts "number instances before restructure is $num_instances" - puts "Design Area before restructure" - report_design_area - report_design_area_metrics - utl::pop_metrics_stage - - write_verilog $::env(RESULTS_DIR)/2_pre_abc.v - - set tielo_cell_name [lindex $env(TIELO_CELL_AND_PORT) 0] - set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]] - set tielo_port $tielo_lib_name/$tielo_cell_name/[lindex $env(TIELO_CELL_AND_PORT) 1] - - set tiehi_cell_name [lindex $env(TIEHI_CELL_AND_PORT) 0] - set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]] - set tiehi_port $tiehi_lib_name/$tiehi_cell_name/[lindex $env(TIEHI_CELL_AND_PORT) 1] - - restructure -liberty_file $::env(DONT_USE_SC_LIB) -target "area" \ - -tiehi_port $tiehi_port \ - -tielo_port $tielo_port \ - -work_dir $::env(RESULTS_DIR) - - # remove buffers inserted by abc - remove_buffers - - write_verilog $::env(RESULTS_DIR)/2_post_abc.v - utl::push_metrics_stage "floorplan__{}__post_restruct" - set num_instances [llength [get_cells -hier *]] - puts "number instances after restructure is $num_instances" - puts "Design Area after restructure" - report_design_area - report_design_area_metrics - utl::pop_metrics_stage -} - if { [env_var_exists_and_non_empty POST_FLOORPLAN_TCL] } { log_cmd source $::env(POST_FLOORPLAN_TCL) } diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 433085f635..0abaced1e2 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -708,18 +708,6 @@ DIE_AREA: stages: - floorplan tunable: 1 -RESYNTH_AREA_RECOVER: - description: | - Enable re-synthesis for area reclaim. - stages: - - floorplan - default: 0 -RESYNTH_TIMING_RECOVER: - description: | - Enable re-synthesis for timing optimization. - stages: - - floorplan - default: 0 MACRO_ROWS_HALO_X: description: > Horizontal distance between the edge of the macro and the beginning of the From 932c578db1ad0646355f7fcac8c7291f2b511404 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 17 Jun 2025 06:33:42 +0200 Subject: [PATCH 076/198] docs: update MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- docs/user/FlowVariables.md | 4 ---- 1 file changed, 4 deletions(-) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 109d1c4b1f..c2b96a003d 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -143,8 +143,6 @@ configuration file. | REMOVE_CELLS_FOR_EQY| String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.| | | | REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| | | | REPORT_CLOCK_SKEW| Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable.| 1| | -| RESYNTH_AREA_RECOVER| Enable re-synthesis for area reclaim.| 0| | -| RESYNTH_TIMING_RECOVER| Enable re-synthesis for timing optimization.| 0| | | ROUTING_LAYER_ADJUSTMENT| Adjusts routing layer capacities to manage congestion and improve detailed routing. High values ease detailed routing but risk excessive detours and long global routing times, while low values reduce global routing failure but can complicate detailed routing. The global routing running time normally reduces dramatically (entirely design specific, but going from hours to minutes has been observed) when the value is low (such as 0.10). Sometimes, global routing will succeed with lower values and fail with higher values. Exploring results with different values can help shed light on the problem. Start with a too low value, such as 0.10, and bisect to value that works by doing multiple global routing runs. As a last resort, `make global_route_issue` and using the tools/OpenROAD/etc/deltaDebug.py can be useful to debug global routing errors. If there is something specific that is impossible to route, such as a clock line over a macro, global routing will terminate with DRC errors routes that could have been routed were it not for the specific impossible routes. deltaDebug.py should weed out the possible routes and leave a minimal failing case that pinpoints the problem.| 0.5| | | RTLMP_AREA_WT| Weight for the area of the current floorplan.| 0.1| | | RTLMP_ARGS| Overrides all other RTL macro placer arguments.| | | @@ -258,8 +256,6 @@ configuration file. - [PLACE_DENSITY_LB_ADDON](#PLACE_DENSITY_LB_ADDON) - [PLACE_SITE](#PLACE_SITE) - [REMOVE_ABC_BUFFERS](#REMOVE_ABC_BUFFERS) -- [RESYNTH_AREA_RECOVER](#RESYNTH_AREA_RECOVER) -- [RESYNTH_TIMING_RECOVER](#RESYNTH_TIMING_RECOVER) - [RTLMP_AREA_WT](#RTLMP_AREA_WT) - [RTLMP_ARGS](#RTLMP_ARGS) - [RTLMP_BOUNDARY_WT](#RTLMP_BOUNDARY_WT) From 6c0fe8f4f180148ba40c688771b8ff1ba41d5a3e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 17 Jun 2025 06:31:15 +0200 Subject: [PATCH 077/198] docs: flow variables background MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- docs/user/FlowVariables.md | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index c2b96a003d..7cbef32fac 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -1,10 +1,33 @@ -# Environment Variables for the OpenROAD Flow Scripts +# Variables for the OpenROAD Flow Scripts - -Environment variables are used in the OpenROAD flow to define various +Variables are used in the OpenROAD flow to define various platform, design and tool specific variables to allow finer control and -user overrides at various flow stages. These are defined in the -`config.mk` file located in the platform and design specific directories. +user overrides at various flow stages. + +These are normally defined in the `config.mk` file located in the platform and design-specific directories, but can also be defined on the command line or via environment variables. For example: + +- Command line: `make PLACE_DENSITY=0.5` +- Environment variable: `export PLACE_DENSITY=0.5` + +This works provided that `config.mk` has defined it as a default value using the `export PLACE_DENSITY?=0.4` syntax. + +The actual value used is determined by the priority rules set by `make`: + +1. **Makefile Definitions**: Variables defined in the `Makefile` or included files are used when they are defined using the no-override `=` operator, `export PLACE_DENSITY=0.4` syntax. The priority within the included files is the `DESIGN_CONFIG` file, then `Makefile` definitions and finally platform(PDK) defined variables. +2. **Command Line**: Variables defined on the command line take the highest priority in overriding defaults. +3. **Environment Variables**: Variables exported in the shell environment are used if not overridden by the command line. +4. **Default Values**: Variables defined with the `?=` operator in the `Makefile` are used only if the variable is not already defined elsewhere. + +## Types of variables + +Variables values are set in ORFS scripts or `config.mk` files and are kept in source control together with configuration files and RTL. + +| Category | Definition | User Involvement | Examples | Automation Potential | Notes | +|--------------------|----------------------------------------------------------------------------|----------------------------------------|-----------------------------------------|-----------------------------|-----------------------------------------------------------------------| +| **Trivial** | Automatically determined by tool with near-optimal results. | None (unless debugging) | Buffer sizing, default layers | **High** – can be hidden | Best if invisible; surfaced only in debug or verbose mode. | +| **Easy** | Requires input, but easy to tune using reports or visuals. | Moderate – copy/edit from reports | `PLACE_DENSITY` | **Medium–High** | Smooth response curves, intuitive tuning. | +| **Nasty** | Affects randomness or non-determinism; results vary by run. | High – requires multiple runs/sweeps | `CTS_DISTANCE_BUF` | **Low–Medium** | Needs scripted sweeps and statistical evaluation. | +| **Pinata Nightmare**| No clear mental model between value and effect, no accurate way to communicate intent; tuning is long turnaround time guesswork. | Very High – frustrating trial-and-error, few users, if any, can even attempt to succeed | RTLMP_FENCE_LX | **Very Low** | Should be deprecated, automated, or hidden from normal usage. | ## Platform @@ -20,7 +43,7 @@ variable. For OpenROAD Flow Scripts we have the following public platforms: - `nangate45` - `asap7` -## Platform Specific Environment Variables +## Platform Specific Variables The table below lists the complete set of variables used in each of the From a93e88738ba4f2f9a3219ae23056cd1efb6e3c65 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 17 Jun 2025 07:01:43 +0200 Subject: [PATCH 078/198] docs: PLACE_DENSITY color MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- docs/user/FlowVariables.md | 2 +- flow/scripts/variables.yaml | 11 +++++++++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index c2b96a003d..b7319f006e 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -128,7 +128,7 @@ configuration file. | MIN_BUF_CELL_AND_PORTS| Used to insert a buffer cell to pass through wires. Used in synthesis.| | | | MIN_ROUTING_LAYER| The lowest metal layer name to be used in routing.| | | | PDN_TCL| File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.| | | -| PLACE_DENSITY| The desired placement density of cells. It reflects how spread the cells would be on the core area. 1.0 = closely dense. 0.0 = widely spread.| | | +| PLACE_DENSITY| The desired average placement density of cells: 1.0 = dense, 0.0 = widely spread. The intended effort is also communicated by this parameter. Use a low value for faster builds and higher value for better quality of results. If a too low value is used, the placer will not be able to place all cells and a recommended minimum placement density can be found in the logs. A too high value can lead to excessive runtimes, even timeouts and subtle failures in the flow after placement, such as in CTS or global routing when timing repair fails. The default is platform specific.| | | | PLACE_DENSITY_LB_ADDON| Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists.| | | | PLACE_PINS_ARGS| Arguments to place_pins| | | | PLACE_SITE| Placement site for core cells defined in the technology LEF file.| | | diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 90b5b9ac79..9a9b8892e6 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -380,8 +380,15 @@ PLACE_PINS_ARGS: default: "" PLACE_DENSITY: description: > - The desired placement density of cells. It reflects how spread the cells - would be on the core area. 1.0 = closely dense. 0.0 = widely spread. + The desired average placement density of cells: 1.0 = dense, 0.0 = widely spread. + + The intended effort is also communicated by this parameter. Use a low value for faster builds and higher value for better quality of results. + + If a too low value is used, the placer will not be able to place all cells and a recommended minimum placement density can be found in the logs. + + A too high value can lead to excessive runtimes, even timeouts and subtle failures in the flow after placement, such as in CTS or global routing when timing repair fails. + + The default is platform specific. stages: - floorplan - place From 672fa6fdbd447acf1919f4a2598fde80a592ccef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 17 Jun 2025 08:00:28 +0200 Subject: [PATCH 079/198] docs: flow variables more background MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- docs/user/FlowVariables.md | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 7cbef32fac..e1b8bd227f 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -18,10 +18,26 @@ The actual value used is determined by the priority rules set by `make`: 3. **Environment Variables**: Variables exported in the shell environment are used if not overridden by the command line. 4. **Default Values**: Variables defined with the `?=` operator in the `Makefile` are used only if the variable is not already defined elsewhere. +## Effects of variables + +The variables for ORFS are not fully independent and can interact in complex ways. Small changes to a combination of variables can have large consequences, such as on macro placement, which can lead to vastly different quality of results. + +Due to the large number of variables, some of which are continuous and require long runtimes, other discrete, it is not feasible to perform an exhaustive end-to-end search for the best combination of variables. + +Instead, the following approaches are used to determine reasonable values, up to a point of diminishing returns: + +- **Experience**: Leveraging domain expertise to set initial values. +- **AI**: Using machine learning techniques to explore variable combinations. +- **Parameter Sweeps**: Testing a smaller subset of variables to identify optimal ranges. + +These values are then set in configuration files and kept under source control alongside the RTL input. + ## Types of variables Variables values are set in ORFS scripts or `config.mk` files and are kept in source control together with configuration files and RTL. +It is an ongoing effort to move variables upwards in the categories below. + | Category | Definition | User Involvement | Examples | Automation Potential | Notes | |--------------------|----------------------------------------------------------------------------|----------------------------------------|-----------------------------------------|-----------------------------|-----------------------------------------------------------------------| | **Trivial** | Automatically determined by tool with near-optimal results. | None (unless debugging) | Buffer sizing, default layers | **High** – can be hidden | Best if invisible; surfaced only in debug or verbose mode. | From e96d39969b1cfd1a659c4399bd7c6926e0ed80ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 17 Jun 2025 08:18:13 +0200 Subject: [PATCH 080/198] docs: variables, review feedback MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- docs/user/FlowVariables.md | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index e1b8bd227f..8e7f687e0f 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -42,8 +42,7 @@ It is an ongoing effort to move variables upwards in the categories below. |--------------------|----------------------------------------------------------------------------|----------------------------------------|-----------------------------------------|-----------------------------|-----------------------------------------------------------------------| | **Trivial** | Automatically determined by tool with near-optimal results. | None (unless debugging) | Buffer sizing, default layers | **High** – can be hidden | Best if invisible; surfaced only in debug or verbose mode. | | **Easy** | Requires input, but easy to tune using reports or visuals. | Moderate – copy/edit from reports | `PLACE_DENSITY` | **Medium–High** | Smooth response curves, intuitive tuning. | -| **Nasty** | Affects randomness or non-determinism; results vary by run. | High – requires multiple runs/sweeps | `CTS_DISTANCE_BUF` | **Low–Medium** | Needs scripted sweeps and statistical evaluation. | -| **Pinata Nightmare**| No clear mental model between value and effect, no accurate way to communicate intent; tuning is long turnaround time guesswork. | Very High – frustrating trial-and-error, few users, if any, can even attempt to succeed | RTLMP_FENCE_LX | **Very Low** | Should be deprecated, automated, or hidden from normal usage. | +| **Nasty** | No clear mental model of small changes in values with large effects. | High – requires multiple runs/sweeps | `CTS_DISTANCE_BUF`, small changes can have large effects on skew and quality of results. Small changes to independent inputs, such as RTL, can invalidate earlier "good values". | **Low–Medium** | Needs scripted sweeps and statistical evaluation. | ## Platform From 4a341f2bff200b52b31e488ef267c15d1db91df8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 17 Jun 2025 09:31:08 +0200 Subject: [PATCH 081/198] bazel-orfs: bump MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit igned-off-by: Øyvind Harboe Signed-off-by: Øyvind Harboe --- MODULE.bazel | 10 +-- MODULE.bazel.lock | 150 ++++++++++++++++++++------------ flow/util/BUILD.bazel | 3 +- flow/util/requirements_lock.txt | 2 +- 4 files changed, 100 insertions(+), 65 deletions(-) diff --git a/MODULE.bazel b/MODULE.bazel index 86dc8624e4..574d678f5d 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -11,7 +11,7 @@ bazel_dep(name = "bazel-orfs") # To bump version, run: bazelisk run @bazel-orfs//:bump git_override( module_name = "bazel-orfs", - commit = "9a3778bdbe63106a894a03e865335a31ebc860d1", + commit = "f8a4b694b37c8f5322323eba9a9ae37f9541ee17", remote = "https://github.com/The-OpenROAD-Project/bazel-orfs.git", ) @@ -20,13 +20,13 @@ bazel_dep(name = "rules_python", version = "1.2.0") python = use_extension("@rules_python//python/extensions:python.bzl", "python") python.toolchain( ignore_root_user_error = True, - python_version = "3.12", + python_version = "3.13", ) pip = use_extension("@rules_python//python/extensions:pip.bzl", "pip") pip.parse( hub_name = "orfs-pip", - python_version = "3.12", + python_version = "3.13", requirements_lock = "//flow:util/requirements_lock.txt", ) use_repo(pip, "orfs-pip") @@ -35,12 +35,12 @@ orfs = use_extension("@bazel-orfs//:extension.bzl", "orfs_repositories") # To bump version, run: bazelisk run @bazel-orfs//:bump orfs.default( - image = "docker.io/openroad/orfs:v3.0-3190-g5ac9869c", + image = "docker.io/openroad/orfs:v3.0-3273-gedf3d6bf", # Use local files instead of docker image makefile = "//flow:makefile", makefile_yosys = "//flow:makefile_yosys", pdk = "//flow:asap7", - sha256 = "2ca999699bc91144074b7f23f42da9330d7279437c386a1413fba4a6a7520916", + sha256 = "f5692c6325ebcf27cc348e033355ec95c82c35ace1af7e72a0d352624ada143e", ) use_repo(orfs, "com_github_nixos_patchelf_download") use_repo(orfs, "docker_orfs") diff --git a/MODULE.bazel.lock b/MODULE.bazel.lock index 92f3178152..45ece7112e 100644 --- a/MODULE.bazel.lock +++ b/MODULE.bazel.lock @@ -638,7 +638,7 @@ "@@bazel-orfs~//:extension.bzl%orfs_repositories": { "general": { "bzlTransitiveDigest": "opZMguyG+UPmDQ6vhzXe/u0WnKyao2m9IAQt+JWkhcA=", - "usagesDigest": "2NcMguz4FONad7PT2HxaMW3QgfrJL+IvDGhrVn5dQhU=", + "usagesDigest": "ZjAOFUXNXojx6a5mgorvg9pXsDXOsJv7KzaZaxOrWXU=", "recordedFileInputs": {}, "recordedDirentsInputs": {}, "envVariables": {}, @@ -658,8 +658,8 @@ "bzlFile": "@@bazel-orfs~//:docker.bzl", "ruleClassName": "docker_pkg", "attributes": { - "image": "docker.io/openroad/orfs:v3.0-3190-g5ac9869c", - "sha256": "2ca999699bc91144074b7f23f42da9330d7279437c386a1413fba4a6a7520916", + "image": "docker.io/openroad/orfs:v3.0-3273-gedf3d6bf", + "sha256": "f5692c6325ebcf27cc348e033355ec95c82c35ace1af7e72a0d352624ada143e", "build_file": "@@bazel-orfs~//:docker.BUILD.bazel", "timeout": 3600, "patch_cmds": [ @@ -941,12 +941,12 @@ }, "@@rules_python~//python/extensions:pip.bzl%pip": { "general": { - "bzlTransitiveDigest": "UVXSWhRHdKjw09doJ4m4mjTHC+BIiApwOePiq04rmBA=", - "usagesDigest": "pH3zwwfC5Cl9+K3uTBlFrrKV8Gno7nf5+n1aL4X3uGU=", + "bzlTransitiveDigest": "wDKx+PsqgAb8Kll8JbxI6+g8BUNJT48gxqvlHp+uPaM=", + "usagesDigest": "Pmo+R+aERo0wl9TIu+O0dXTNmE8JG2ElzftJqGKKsXk=", "recordedFileInputs": { "@@rules_python~//tools/publish/requirements_linux.txt": "d576e0d8542df61396a9b38deeaa183c24135ed5e8e73bb9622f298f2671811e", - "@@bazel-orfs~//requirements_lock_3_13.txt": "fcabafb7192fe8f92d82e7ec8ddd8e3fd6787f8acea3ec694f105ed63821416a", - "@@//flow/util/requirements_lock.txt": "016f788600d492820c9a6ff951c31a26735bcdb24a5a1bc83f68a726c6e4c884", + "@@bazel-orfs~//requirements_lock_3_13.txt": "6d409e2c9f81ceee67c23e6f26b6742b4ee6c32826c7d0591c5c57df72a6a16b", + "@@//flow/util/requirements_lock.txt": "21d4a2f4b126820247f3f9b3554210fc78861c0a367c2b52d87771900b40520c", "@@rules_fuzzing~//fuzzing/requirements.txt": "ab04664be026b632a0d2a2446c4f65982b7654f5b6851d2f9d399a19b7242a5b", "@@rules_python~//tools/publish/requirements_windows.txt": "d18538a3982beab378fd5687f4db33162ee1ece69801f9a451661b1b64286b76", "@@protobuf~//python/requirements.txt": "983be60d3cec4b319dcab6d48aeb3f5b2f7c3350f26b3a9e97486c37967c73c5", @@ -1028,6 +1028,16 @@ "requirement": "packaging==24.2 --hash=sha256:09abb1bccd265c01f4a3aa3f7a7db064b36514d2cba19a2f694fe6150451a759 --hash=sha256:c228a6dc5e932d346bc5739379109d49e8853dd8223571c7c5b55260edc0b97f" } }, + "bazel-orfs-pip_313_pandas": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + 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--hash=sha256:a8b2bc7bffae282281c8140a97d3aa9c14da0b136dfe83f850eea9a5f7470427" } }, + "bazel-orfs-pip_313_pytz": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@bazel-orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "bazel-orfs-pip_313", + "requirement": "pytz==2025.2 --hash=sha256:360b9e3dbb49a209c21ad61809c7fb453643e048b38924c765813546746e81c3 --hash=sha256:5ddf76296dd8c44c26eb8f4b6f35488f3ccbf6fbbd7adee0b7262d43f0ec2f00" + } + }, "bazel-orfs-pip_313_pyyaml": { "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", "ruleClassName": "whl_library", @@ -1078,123 +1098,133 @@ "requirement": "six==1.17.0 --hash=sha256:4721f391ed90541fddacab5acf947aa0d3dc7d27b2e1e8eda2be8970586c3274 --hash=sha256:ff70335d468e7eb6ec65b95b99d3a2836546063f63acc5171de367e834932a81" } }, - "orfs-pip_312_contourpy": { + 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"@@rules_python~~python~python_3_13_host//:python", + "repo": "orfs-pip_313", "requirement": "pyyaml==6.0.2 --hash=sha256:01179a4a8559ab5de078078f37e5c1a30d76bb88519906844fd7bdea1b7729ff --hash=sha256:0833f8694549e586547b576dcfaba4a6b55b9e96098b36cdc7ebefe667dfed48 --hash=sha256:0a9a2848a5b7feac301353437eb7d5957887edbf81d56e903999a75a3d743086 --hash=sha256:0b69e4ce7a131fe56b7e4d770c67429700908fc0752af059838b1cfb41960e4e --hash=sha256:0ffe8360bab4910ef1b9e87fb812d8bc0a308b0d0eef8c8f44e0254ab3b07133 --hash=sha256:11d8f3dd2b9c1207dcaf2ee0bbbfd5991f571186ec9cc78427ba5bd32afae4b5 --hash=sha256:17e311b6c678207928d649faa7cb0d7b4c26a0ba73d41e99c4fff6b6c3276484 --hash=sha256:1e2120ef853f59c7419231f3bf4e7021f1b936f6ebd222406c3b60212205d2ee --hash=sha256:1f71ea527786de97d1a0cc0eacd1defc0985dcf6b3f17bb77dcfc8c34bec4dc5 --hash=sha256:23502f431948090f597378482b4812b0caae32c22213aecf3b55325e049a6c68 --hash=sha256:24471b829b3bf607e04e88d79542a9d48bb037c2267d7927a874e6c205ca7e9a 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--hash=sha256:e10ce637b18caea04431ce14fabcf5c64a1c61ec9c56b071a4b7ca131ca52d44 --hash=sha256:ec031d5d2feb36d1d1a24380e4db6d43695f3748343d99434e6f5f9156aaa2ed --hash=sha256:ef6107725bd54b262d6dedcc2af448a266975032bc85ef0172c5f059da6325b4 --hash=sha256:efdca5630322a10774e8e98e1af481aad470dd62c3170801852d752aa7a783ba --hash=sha256:f753120cb8181e736c57ef7636e83f31b9c0d1722c516f7e86cf15b7aa57ff12 --hash=sha256:ff3824dc5261f50c9b0dfb3be22b4567a6f938ccce4587b38952d85fd9e9afe4" } }, - "orfs-pip_312_six": { + "orfs-pip_313_six": { "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", "ruleClassName": "whl_library", "attributes": { "dep_template": "@orfs-pip//{name}:{target}", - "python_interpreter_target": "@@rules_python~~python~python_3_12_host//:python", - "repo": "orfs-pip_312", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "orfs-pip_313", "requirement": "six==1.17.0 --hash=sha256:4721f391ed90541fddacab5acf947aa0d3dc7d27b2e1e8eda2be8970586c3274 --hash=sha256:ff70335d468e7eb6ec65b95b99d3a2836546063f63acc5171de367e834932a81" } }, @@ -3813,11 +3843,14 @@ "matplotlib": "{\"bazel-orfs-pip_313_matplotlib\":[{\"version\":\"3.13\"}]}", "numpy": "{\"bazel-orfs-pip_313_numpy\":[{\"version\":\"3.13\"}]}", "packaging": "{\"bazel-orfs-pip_313_packaging\":[{\"version\":\"3.13\"}]}", + "pandas": "{\"bazel-orfs-pip_313_pandas\":[{\"version\":\"3.13\"}]}", "pillow": "{\"bazel-orfs-pip_313_pillow\":[{\"version\":\"3.13\"}]}", "pyparsing": "{\"bazel-orfs-pip_313_pyparsing\":[{\"version\":\"3.13\"}]}", "python_dateutil": "{\"bazel-orfs-pip_313_python_dateutil\":[{\"version\":\"3.13\"}]}", + "pytz": "{\"bazel-orfs-pip_313_pytz\":[{\"version\":\"3.13\"}]}", "pyyaml": "{\"bazel-orfs-pip_313_pyyaml\":[{\"version\":\"3.13\"}]}", - "six": "{\"bazel-orfs-pip_313_six\":[{\"version\":\"3.13\"}]}" + "six": "{\"bazel-orfs-pip_313_six\":[{\"version\":\"3.13\"}]}", + "tzdata": "{\"bazel-orfs-pip_313_tzdata\":[{\"version\":\"3.13\"}]}" }, "packages": [ "contourpy", @@ -3827,11 +3860,14 @@ "matplotlib", "numpy", "packaging", + "pandas", "pillow", "pyparsing", "python_dateutil", + "pytz", "pyyaml", - "six" + "six", + "tzdata" ], "groups": {} } @@ -3843,18 +3879,18 @@ "repo_name": "orfs-pip", "extra_hub_aliases": {}, "whl_map": { - "contourpy": "{\"orfs-pip_312_contourpy\":[{\"version\":\"3.12\"}]}", - "cycler": "{\"orfs-pip_312_cycler\":[{\"version\":\"3.12\"}]}", - "fonttools": "{\"orfs-pip_312_fonttools\":[{\"version\":\"3.12\"}]}", - "kiwisolver": "{\"orfs-pip_312_kiwisolver\":[{\"version\":\"3.12\"}]}", - "matplotlib": "{\"orfs-pip_312_matplotlib\":[{\"version\":\"3.12\"}]}", - "numpy": "{\"orfs-pip_312_numpy\":[{\"version\":\"3.12\"}]}", - "packaging": "{\"orfs-pip_312_packaging\":[{\"version\":\"3.12\"}]}", - "pillow": "{\"orfs-pip_312_pillow\":[{\"version\":\"3.12\"}]}", - "pyparsing": "{\"orfs-pip_312_pyparsing\":[{\"version\":\"3.12\"}]}", - "python_dateutil": "{\"orfs-pip_312_python_dateutil\":[{\"version\":\"3.12\"}]}", - "pyyaml": "{\"orfs-pip_312_pyyaml\":[{\"version\":\"3.12\"}]}", - "six": "{\"orfs-pip_312_six\":[{\"version\":\"3.12\"}]}" + "contourpy": "{\"orfs-pip_313_contourpy\":[{\"version\":\"3.13\"}]}", + "cycler": "{\"orfs-pip_313_cycler\":[{\"version\":\"3.13\"}]}", + "fonttools": "{\"orfs-pip_313_fonttools\":[{\"version\":\"3.13\"}]}", + "kiwisolver": "{\"orfs-pip_313_kiwisolver\":[{\"version\":\"3.13\"}]}", + "matplotlib": "{\"orfs-pip_313_matplotlib\":[{\"version\":\"3.13\"}]}", + "numpy": "{\"orfs-pip_313_numpy\":[{\"version\":\"3.13\"}]}", + "packaging": "{\"orfs-pip_313_packaging\":[{\"version\":\"3.13\"}]}", + "pillow": "{\"orfs-pip_313_pillow\":[{\"version\":\"3.13\"}]}", + "pyparsing": "{\"orfs-pip_313_pyparsing\":[{\"version\":\"3.13\"}]}", + "python_dateutil": "{\"orfs-pip_313_python_dateutil\":[{\"version\":\"3.13\"}]}", + "pyyaml": "{\"orfs-pip_313_pyyaml\":[{\"version\":\"3.13\"}]}", + "six": "{\"orfs-pip_313_six\":[{\"version\":\"3.13\"}]}" }, "packages": [ "contourpy", diff --git a/flow/util/BUILD.bazel b/flow/util/BUILD.bazel index 92641ed57b..b8892cbab6 100644 --- a/flow/util/BUILD.bazel +++ b/flow/util/BUILD.bazel @@ -25,7 +25,6 @@ MAKEFILE_SHARED = [ filegroup( name = "makefile", srcs = glob(MAKEFILE_SHARED + [ - "*.pl", "*.py", "*.sh", ]), @@ -36,7 +35,7 @@ filegroup( filegroup( name = "makefile_yosys", srcs = glob(MAKEFILE_SHARED) + [ - "mergeLib.pl", + "merge_lib.py", "preprocessLib.py", ], visibility = ["//visibility:public"], diff --git a/flow/util/requirements_lock.txt b/flow/util/requirements_lock.txt index 17d4824261..e6aa58ad02 100644 --- a/flow/util/requirements_lock.txt +++ b/flow/util/requirements_lock.txt @@ -1,5 +1,5 @@ # -# This file is autogenerated by pip-compile with Python 3.12 +# This file is autogenerated by pip-compile with Python 3.13 # by the following command: # # bazel run //flow/util:requirements.update From e5b28bca70afd6af617242b9251ddf5a4b531298 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 17 Jun 2025 10:18:04 +0200 Subject: [PATCH 082/198] bazel: sky130hd/ibex update to match config.mk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/designs/sky130hd/ibex/BUILD.bazel | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/flow/designs/sky130hd/ibex/BUILD.bazel b/flow/designs/sky130hd/ibex/BUILD.bazel index 7203d88313..08f7adc3e6 100644 --- a/flow/designs/sky130hd/ibex/BUILD.bazel +++ b/flow/designs/sky130hd/ibex/BUILD.bazel @@ -5,11 +5,13 @@ orfs_flow( arguments = { "ADDER_MAP_FILE": "", "CORE_UTILIZATION": "45", - "PLACE_DENSITY_LB_ADDON": "0.2", + "PLACE_DENSITY_LB_ADDON": "0.25", "TNS_END_PERCENT": "100", "REMOVE_ABC_BUFFERS": "1", "SYNTH_HDL_FRONTEND": "slang", "VERILOG_INCLUDE_DIRS": "flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl", + "CTS_CLUSTER_SIZE": "20", + "CTS_CLUSTER_DIAMETER": "50", }, pdk = "@docker_orfs//:sky130hd", sources = { From 55a74b083c959bcb2f6078545648ebbb5296cede Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 17 Jun 2025 19:00:05 +0200 Subject: [PATCH 083/198] Update docs/user/FlowVariables.md MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Matt Liberty Signed-off-by: Øyvind Harboe --- docs/user/FlowVariables.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 8e7f687e0f..954572bee3 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -42,7 +42,7 @@ It is an ongoing effort to move variables upwards in the categories below. |--------------------|----------------------------------------------------------------------------|----------------------------------------|-----------------------------------------|-----------------------------|-----------------------------------------------------------------------| | **Trivial** | Automatically determined by tool with near-optimal results. | None (unless debugging) | Buffer sizing, default layers | **High** – can be hidden | Best if invisible; surfaced only in debug or verbose mode. | | **Easy** | Requires input, but easy to tune using reports or visuals. | Moderate – copy/edit from reports | `PLACE_DENSITY` | **Medium–High** | Smooth response curves, intuitive tuning. | -| **Nasty** | No clear mental model of small changes in values with large effects. | High – requires multiple runs/sweeps | `CTS_DISTANCE_BUF`, small changes can have large effects on skew and quality of results. Small changes to independent inputs, such as RTL, can invalidate earlier "good values". | **Low–Medium** | Needs scripted sweeps and statistical evaluation. | +| **Complex** | Small changes in values may result in large effects. | High – requires multiple runs/sweeps | `CTS_DISTANCE_BUF`, small changes can have large effects on skew and quality of results. Small changes to independent inputs, such as RTL, can invalidate earlier "good values". | **Low–Medium** | Needs scripted sweeps and statistical evaluation. | ## Platform From 0d2ae5728648e7e5a6427fba7af4777549fb89bf Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Wed, 18 Jun 2025 07:00:52 +0000 Subject: [PATCH 084/198] In floorplan.tcl skip clone & split moves and last-gasp Not necessary so early in the flow. The whole thing is to be replaced by gain-based buffering. Signed-off-by: Matt Liberty --- flow/scripts/floorplan.tcl | 3 +++ tools/OpenROAD | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/flow/scripts/floorplan.tcl b/flow/scripts/floorplan.tcl index 69133bc58a..9fb66c1b92 100644 --- a/flow/scripts/floorplan.tcl +++ b/flow/scripts/floorplan.tcl @@ -107,6 +107,9 @@ if { [env_var_equals REMOVE_ABC_BUFFERS 1] } { # remove buffers inserted by yosys/abc remove_buffers } else { + # Skip clone & split + set ::env(SETUP_MOVE_SEQUENCE) "unbuffer,sizeup,swap,buffer" + set ::env(SKIP_LAST_GASP) 1 repair_timing_helper 0 } diff --git a/tools/OpenROAD b/tools/OpenROAD index a9002cfe20..a245958df4 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit a9002cfe2000a9c297bb4b6ff8b3d2e8bf6cc65e +Subproject commit a245958df4cb45b158a2080f31ab8afeda4ce773 From 8e4e32dbe2efe7205348b2d97ffa22e240dcbbea Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" Date: Wed, 18 Jun 2025 18:59:49 +0000 Subject: [PATCH 085/198] flow: update rules Signed-off-by: github-actions[bot] --- flow/designs/asap7/aes-block/rules-base.json | 2 +- flow/designs/ihp-sg13g2/ibex/rules-base.json | 2 +- flow/designs/nangate45/swerv/rules-base.json | 2 +- flow/designs/nangate45/swerv_wrapper/rules-base.json | 2 +- flow/designs/nangate45/tinyRocket/rules-base.json | 2 +- flow/designs/sky130hd/gcd/rules-base.json | 2 +- flow/designs/sky130hd/ibex/rules-base.json | 2 +- flow/designs/sky130hd/microwatt/rules-base.json | 2 +- flow/designs/sky130hs/ibex/rules-base.json | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json index ff5a90ae0a..754e477bcd 100644 --- a/flow/designs/asap7/aes-block/rules-base.json +++ b/flow/designs/asap7/aes-block/rules-base.json @@ -67,4 +67,4 @@ "value": -18.47, "compare": ">=" } -} +} \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/ibex/rules-base.json b/flow/designs/ihp-sg13g2/ibex/rules-base.json index d4eca3580b..36f121e565 100644 --- a/flow/designs/ihp-sg13g2/ibex/rules-base.json +++ b/flow/designs/ihp-sg13g2/ibex/rules-base.json @@ -67,4 +67,4 @@ "value": -10.0, "compare": ">=" } -} +} \ No newline at end of file diff --git a/flow/designs/nangate45/swerv/rules-base.json b/flow/designs/nangate45/swerv/rules-base.json index 122ebc301b..26b84e8c90 100644 --- a/flow/designs/nangate45/swerv/rules-base.json +++ b/flow/designs/nangate45/swerv/rules-base.json @@ -67,4 +67,4 @@ "value": -21.98, "compare": ">=" } -} +} \ No newline at end of file diff --git a/flow/designs/nangate45/swerv_wrapper/rules-base.json b/flow/designs/nangate45/swerv_wrapper/rules-base.json index 981adac811..4d68fe18d5 100644 --- a/flow/designs/nangate45/swerv_wrapper/rules-base.json +++ b/flow/designs/nangate45/swerv_wrapper/rules-base.json @@ -67,4 +67,4 @@ "value": -19.88, "compare": ">=" } -} +} \ No newline at end of file diff --git a/flow/designs/nangate45/tinyRocket/rules-base.json b/flow/designs/nangate45/tinyRocket/rules-base.json index 37bf6e8722..c4e298e189 100644 --- a/flow/designs/nangate45/tinyRocket/rules-base.json +++ b/flow/designs/nangate45/tinyRocket/rules-base.json @@ -67,4 +67,4 @@ "value": -15.79, "compare": ">=" } -} +} \ No newline at end of file diff --git a/flow/designs/sky130hd/gcd/rules-base.json b/flow/designs/sky130hd/gcd/rules-base.json index 2660611f36..eda2d1a286 100644 --- a/flow/designs/sky130hd/gcd/rules-base.json +++ b/flow/designs/sky130hd/gcd/rules-base.json @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 72, + "value": 81, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/sky130hd/ibex/rules-base.json b/flow/designs/sky130hd/ibex/rules-base.json index 73030ba111..9176116e5a 100644 --- a/flow/designs/sky130hd/ibex/rules-base.json +++ b/flow/designs/sky130hd/ibex/rules-base.json @@ -67,4 +67,4 @@ "value": -16.91, "compare": ">=" } -} +} \ No newline at end of file diff --git a/flow/designs/sky130hd/microwatt/rules-base.json b/flow/designs/sky130hd/microwatt/rules-base.json index b9c83b9ba2..3d00501a44 100644 --- a/flow/designs/sky130hd/microwatt/rules-base.json +++ b/flow/designs/sky130hd/microwatt/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 2476, + "value": 4257, "compare": "<=" }, "detailedroute__route__wirelength": { diff --git a/flow/designs/sky130hs/ibex/rules-base.json b/flow/designs/sky130hs/ibex/rules-base.json index dfb2fce2ba..ab9f01be3f 100644 --- a/flow/designs/sky130hs/ibex/rules-base.json +++ b/flow/designs/sky130hs/ibex/rules-base.json @@ -67,4 +67,4 @@ "value": -10.0, "compare": ">=" } -} +} \ No newline at end of file From 09312c724d277d5015e6c21b838034cf70d91b7b Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Wed, 18 Jun 2025 20:37:55 +0000 Subject: [PATCH 086/198] Move repair_tie_fanout to floorplan.tcl Covers the rare case of a tie cell connected to multiple buffers each driving an output. You want to split up the tie cell before removing the buffers. Signed-off-by: Matt Liberty --- docs/user/FlowVariables.md | 4 ++-- flow/scripts/floorplan.tcl | 4 ++++ flow/scripts/resize.tcl | 20 -------------------- flow/scripts/util.tcl | 22 ++++++++++++++++++++++ flow/scripts/variables.yaml | 4 ++-- 5 files changed, 30 insertions(+), 24 deletions(-) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 031458210f..836c5b70dd 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -320,6 +320,8 @@ configuration file. - [SKIP_PIN_SWAP](#SKIP_PIN_SWAP) - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [TAPCELL_TCL](#TAPCELL_TCL) +- [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT) +- [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT) - [TNS_END_PERCENT](#TNS_END_PERCENT) ## place variables @@ -340,8 +342,6 @@ configuration file. - [PLACE_PINS_ARGS](#PLACE_PINS_ARGS) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) -- [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT) -- [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT) ## cts variables diff --git a/flow/scripts/floorplan.tcl b/flow/scripts/floorplan.tcl index 69133bc58a..81cd01fb18 100644 --- a/flow/scripts/floorplan.tcl +++ b/flow/scripts/floorplan.tcl @@ -103,6 +103,10 @@ if {[env_var_exists_and_non_empty FOOTPRINT_TCL]} { log_cmd source $::env(FOOTPRINT_TCL) } +# This needs to come before any call to remove_buffers. You could have one +# tie driving multiple buffers that drive multiple outputs. +repair_tie_fanout_helper + if { [env_var_equals REMOVE_ABC_BUFFERS 1] } { # remove buffers inserted by yosys/abc remove_buffers diff --git a/flow/scripts/resize.tcl b/flow/scripts/resize.tcl index 1982f9b9aa..268332b668 100644 --- a/flow/scripts/resize.tcl +++ b/flow/scripts/resize.tcl @@ -12,26 +12,6 @@ set_dont_use $::env(DONT_USE_CELLS) repair_design_helper -if { [env_var_exists_and_non_empty TIE_SEPARATION] } { - set tie_separation $env(TIE_SEPARATION) -} else { - set tie_separation 0 -} - -# Repair tie lo fanout -puts "Repair tie lo fanout..." -set tielo_cell_name [lindex $env(TIELO_CELL_AND_PORT) 0] -set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]] -set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $env(TIELO_CELL_AND_PORT) 1] -repair_tie_fanout -separation $tie_separation $tielo_pin - -# Repair tie hi fanout -puts "Repair tie hi fanout..." -set tiehi_cell_name [lindex $env(TIEHI_CELL_AND_PORT) 0] -set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]] -set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $env(TIEHI_CELL_AND_PORT) 1] -repair_tie_fanout -separation $tie_separation $tiehi_pin - # hold violations are not repaired until after CTS # post report diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl index 972892c1a3..ceb77f96a9 100644 --- a/flow/scripts/util.tcl +++ b/flow/scripts/util.tcl @@ -13,6 +13,28 @@ proc log_cmd {cmd args} { return $result } +proc repair_tie_fanout_helper {} { + if { [env_var_exists_and_non_empty TIE_SEPARATION] } { + set tie_separation $env(TIE_SEPARATION) + } else { + set tie_separation 0 + } + + # Repair tie lo fanout + puts "Repair tie lo fanout..." + set tielo_cell_name [lindex $::env(TIELO_CELL_AND_PORT) 0] + set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]] + set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $::env(TIELO_CELL_AND_PORT) 1] + repair_tie_fanout -separation $tie_separation $tielo_pin + + # Repair tie hi fanout + puts "Repair tie hi fanout..." + set tiehi_cell_name [lindex $::env(TIEHI_CELL_AND_PORT) 0] + set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]] + set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $::env(TIEHI_CELL_AND_PORT) 1] + repair_tie_fanout -separation $tie_separation $tiehi_pin +} + proc fast_route {} { if {[env_var_exists_and_non_empty FASTROUTE_TCL]} { log_cmd source $::env(FASTROUTE_TCL) diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 9a9b8892e6..15f693cf3e 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -214,13 +214,13 @@ TIEHI_CELL_AND_PORT: Netlist. stages: - synth - - place + - floorplan TIELO_CELL_AND_PORT: description: | Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist. stages: - synth - - place + - floorplan MIN_BUF_CELL_AND_PORTS: description: | Used to insert a buffer cell to pass through wires. Used in synthesis. From 9f37a9cab3d00e5c7e7048f8f99004642822e832 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Wed, 18 Jun 2025 18:59:20 -0300 Subject: [PATCH 087/198] use latest master Signed-off-by: Eder Monteiro --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index a245958df4..e743761ef8 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit a245958df4cb45b158a2080f31ab8afeda4ce773 +Subproject commit e743761ef889c67a4cc3475b23be78358c9f5ace From 4f9e43a2006106abc69136a11683a36d7affbfdf Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Wed, 18 Jun 2025 19:00:58 -0300 Subject: [PATCH 088/198] update asap7/aes-block metrics Signed-off-by: Eder Monteiro --- flow/designs/asap7/aes-block/rules-base.json | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json index 754e477bcd..69341b0032 100644 --- a/flow/designs/asap7/aes-block/rules-base.json +++ b/flow/designs/asap7/aes-block/rules-base.json @@ -24,7 +24,7 @@ "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1244, + "value": 1078, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 77091, + "value": 75984, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -83.73, + "value": -152.45, "compare": ">=" }, "finish__design__instance__area": { From e4949539e39e83ab6b150d5f40bfa6ba66f8c544 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Thu, 19 Jun 2025 22:21:10 +0200 Subject: [PATCH 089/198] versions.txt: non-zero exit code when commands don't exist MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit use-case: in bazel-orfs when generating issues for floorplan, yosys isn't a dependency and hence isn't in e.g. the `bazelisk build MockArray_floorplan --sandbox_debug` environment. Signed-off-by: Øyvind Harboe --- flow/Makefile | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/flow/Makefile b/flow/Makefile index dfadc5ebfd..1cc7913eb0 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -184,17 +184,9 @@ $(foreach block,$(BLOCKS),$(eval $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKN .PHONY: versions.txt versions.txt: mkdir -p $(OBJECTS_DIR) - @if [ -z "$(YOSYS_EXE)" ]; then \ - echo >> $(OBJECTS_DIR)/$@ "yosys not installed"; \ - else \ - $(YOSYS_EXE) -V > $(OBJECTS_DIR)/$@; \ - fi - @echo openroad `$(OPENROAD_EXE) -version` >> $(OBJECTS_DIR)/$@ - @if [ -z "$(KLAYOUT_CMD)" ]; then \ - echo >> $(OBJECTS_DIR)/$@ "klayout not installed"; \ - else \ - $(KLAYOUT_CMD) -zz -v >> $(OBJECTS_DIR)/$@; \ - fi + @echo yosys $(shell $(YOSYS_EXE) -V) > $(OBJECTS_DIR)/$@ + @echo openroad $(shell $(OPENROAD_EXE) -version) >> $(OBJECTS_DIR)/$@ + @echo klayout $(shell $(KLAYOUT_CMD) -zz -v) >> $(OBJECTS_DIR)/$@ # Pre-process libraries # ============================================================================== From 9d0c72493846155034528f94710057685bc2aec1 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Thu, 19 Jun 2025 14:38:23 -0700 Subject: [PATCH 090/198] Update gf12/bp_single for drv__hold_violation_count change designs/gf12/bp_single/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | placeopt__design__instance__area | 509289 | 491681 | Tighten | | placeopt__design__instance__count__stdcell | 546190 | 535708 | Tighten | | cts__design__instance__count__setup_buffer | 47495 | 46583 | Tighten | | cts__design__instance__count__hold_buffer | 47495 | 46583 | Tighten | | detailedroute__route__wirelength | 7863419 | 6200511 | Tighten | | detailedroute__route__drc_errors | 1 | 0 | Tighten | | finish__timing__setup__ws | -183.6 | -144.83 | Tighten | | finish__design__instance__area | 519153 | 500408 | Tighten | | finish__timing__drv__setup_violation_count | 23747 | 23292 | Tighten | | finish__timing__drv__hold_violation_count | 230 | 479 | Failing | Signed-off-by: Matt Liberty --- flow/designs/gf12/bp_single/rules-base.json | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/flow/designs/gf12/bp_single/rules-base.json b/flow/designs/gf12/bp_single/rules-base.json index 9f270fcfe6..be33224b80 100644 --- a/flow/designs/gf12/bp_single/rules-base.json +++ b/flow/designs/gf12/bp_single/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 509289, + "value": 491681, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 546190, + "value": 535708, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 47495, + "value": 46583, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 47495, + "value": 46583, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,11 +32,11 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 7863419, + "value": 6200511, "compare": "<=" }, "detailedroute__route__drc_errors": { - "value": 1, + "value": 0, "compare": "<=" }, "detailedroute__antenna__violating__nets": { @@ -48,19 +48,19 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -183.6, + "value": -144.83, "compare": ">=" }, "finish__design__instance__area": { - "value": 519153, + "value": 500408, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 23747, + "value": 23292, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 230, + "value": 479, "compare": "<=" }, "finish__timing__wns_percent_delay": { From f20471c79a18bd6c22beaca0f3f834fa892697bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 20 Jun 2025 07:02:16 +0200 Subject: [PATCH 091/198] make: versions.txt - add missing quotes and log error MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/flow/Makefile b/flow/Makefile index 1cc7913eb0..2b0bc6eb94 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -184,9 +184,9 @@ $(foreach block,$(BLOCKS),$(eval $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKN .PHONY: versions.txt versions.txt: mkdir -p $(OBJECTS_DIR) - @echo yosys $(shell $(YOSYS_EXE) -V) > $(OBJECTS_DIR)/$@ - @echo openroad $(shell $(OPENROAD_EXE) -version) >> $(OBJECTS_DIR)/$@ - @echo klayout $(shell $(KLAYOUT_CMD) -zz -v) >> $(OBJECTS_DIR)/$@ + @echo "yosys $(shell $(YOSYS_EXE) -V 2>&1)" > $(OBJECTS_DIR)/$@ + @echo "openroad $(shell $(OPENROAD_EXE) -version 2>&1)" >> $(OBJECTS_DIR)/$@ + @echo "klayout $(shell $(KLAYOUT_CMD) -zz -v 2>&1)" >> $(OBJECTS_DIR)/$@ # Pre-process libraries # ============================================================================== From eb2162f5a630138cdfb87be08602f4d127f83151 Mon Sep 17 00:00:00 2001 From: Mateusz Gancarz Date: Tue, 17 Jun 2025 09:38:08 +0200 Subject: [PATCH 092/198] synth: allow user to specify custom hier separator for flatten stage Signed-off-by: Mateusz Gancarz --- docs/user/FlowVariables.md | 2 ++ flow/scripts/synth.tcl | 4 ++++ flow/scripts/variables.yaml | 4 ++++ 3 files changed, 10 insertions(+) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 109d1c4b1f..434de4ec9c 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -187,6 +187,7 @@ configuration file. | SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | | | SYNTH_HDL_FRONTEND| Select an alternative language frontend to ingest the design. Available option is "slang". If the variable is empty, design is read with the Yosys read_verilog command.| | | | SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| | +| SYNTH_HIER_SEPARATOR| Separator used for the synthesis flatten stage.| .| | | SYNTH_KEEP_MODULES| Mark modules to keep from getting removed in flattening.| | | | SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096| | | SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| 0| | @@ -430,6 +431,7 @@ configuration file. - [SET_RC_TCL](#SET_RC_TCL) - [SLEW_MARGIN](#SLEW_MARGIN) - [SYNTH_ARGS](#SYNTH_ARGS) +- [SYNTH_HIER_SEPARATOR](#SYNTH_HIER_SEPARATOR) - [TAP_CELL_NAME](#TAP_CELL_NAME) - [TECH_LEF](#TECH_LEF) - [USE_FILL](#USE_FILL) diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl index 1d89beb0ad..0d6b2a44c5 100644 --- a/flow/scripts/synth.tcl +++ b/flow/scripts/synth.tcl @@ -17,6 +17,10 @@ if {[env_var_exists_and_non_empty SYNTH_KEEP_MODULES]} { } } +if {[env_var_exists_and_non_empty SYNTH_HIER_SEPARATOR]} { + scratchpad -set flatten.separator $::env(SYNTH_HIER_SEPARATOR) +} + set synth_full_args $::env(SYNTH_ARGS) if {[env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS]} { set synth_full_args [concat $synth_full_args $::env(SYNTH_OPERATIONS_ARGS)] diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 90b5b9ac79..7cd4d93c93 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -677,6 +677,10 @@ SYNTH_ARGS: description: | Optional synthesis variables for yosys. default: -flatten +SYNTH_HIER_SEPARATOR: + description: | + Separator used for the synthesis flatten stage. + default: . VERILOG_TOP_PARAMS: description: | Apply toplevel params (if exist). From b0bcd56c1bfc3f708b906734f408edfd95d91827 Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Fri, 20 Jun 2025 16:33:46 +0000 Subject: [PATCH 093/198] reduced clock period and die size for asap7 cva6 Signed-off-by: Jeff Ng --- flow/designs/asap7/cva6/config.mk | 6 +++--- flow/designs/asap7/cva6/constraint.sdc | 2 +- flow/designs/asap7/cva6/rules-base.json | 18 +++++++++--------- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/flow/designs/asap7/cva6/config.mk b/flow/designs/asap7/cva6/config.mk index 806cbaae13..45b0278e17 100644 --- a/flow/designs/asap7/cva6/config.mk +++ b/flow/designs/asap7/cva6/config.mk @@ -88,10 +88,10 @@ export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x256.lib \ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc -export CORE_UTILIZATION = 50 +export CORE_UTILIZATION = 70 export CORE_MARGIN = 2 -export MACRO_HALO = 5 -export PLACE_DENSITY = 0.64 +export MACRO_PLACE_HALO = 3 3 +export PLACE_DENSITY = 0.73 # a smoketest for this option, there are a # few last gasp iterations diff --git a/flow/designs/asap7/cva6/constraint.sdc b/flow/designs/asap7/cva6/constraint.sdc index 3c9064541c..d0f4fbb0d9 100644 --- a/flow/designs/asap7/cva6/constraint.sdc +++ b/flow/designs/asap7/cva6/constraint.sdc @@ -3,7 +3,7 @@ set clk_name main_clk set clk_port clk_i set clk_ports_list [list $clk_port] -set clk_period 1300 +set clk_period 1200 set input_delay 0.46 set output_delay 0.11 create_clock [get_ports $clk_port] -name $clk_name -period $clk_period diff --git a/flow/designs/asap7/cva6/rules-base.json b/flow/designs/asap7/cva6/rules-base.json index 5a5f6c5deb..203bb993c4 100644 --- a/flow/designs/asap7/cva6/rules-base.json +++ b/flow/designs/asap7/cva6/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 20743, + "value": 20690, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 137118, + "value": 136421, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 11923, + "value": 11863, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 11923, + "value": 11863, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1124948, + "value": 1074578, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -68.36, + "value": -139.89, "compare": ">=" }, "finish__design__instance__area": { - "value": 20933, + "value": 20850, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 5962, + "value": 5931, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -10.27, + "value": -10.0, "compare": ">=" } } \ No newline at end of file From 0c3d6e74eb665536e7e8eb4937687afb60f04538 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 20 Jun 2025 20:24:47 +0200 Subject: [PATCH 094/198] versions.txt: nicer output MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit if YOSYS_EXE is empty, log it with iffy code. This avoids -V being passed to bash and strange error messages appearing. If YOSYS_EXE is non-empty, log error silently into versions.txt as versions.txt goes into the make issue report and the actual output from this command will not be part of the make issue Signed-off-by: Øyvind Harboe --- flow/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/flow/Makefile b/flow/Makefile index 2b0bc6eb94..b831987275 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -184,9 +184,9 @@ $(foreach block,$(BLOCKS),$(eval $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKN .PHONY: versions.txt versions.txt: mkdir -p $(OBJECTS_DIR) - @echo "yosys $(shell $(YOSYS_EXE) -V 2>&1)" > $(OBJECTS_DIR)/$@ - @echo "openroad $(shell $(OPENROAD_EXE) -version 2>&1)" >> $(OBJECTS_DIR)/$@ - @echo "klayout $(shell $(KLAYOUT_CMD) -zz -v 2>&1)" >> $(OBJECTS_DIR)/$@ + @echo "yosys $(if $(YOSYS_EXE),$(shell $(YOSYS_EXE) -V 2>&1),not available)" > $(OBJECTS_DIR)/$@ + @echo "openroad $(if $(OPENROAD_EXE),$(shell $(OPENROAD_EXE) -version 2>&1),not available)" >> $(OBJECTS_DIR)/$@ + @echo "klayout $(if $(KLAYOUT_CMD),$(shell $(KLAYOUT_CMD) -zz -v 2>&1),not available)" >> $(OBJECTS_DIR)/$@ # Pre-process libraries # ============================================================================== From af85e680c9db91cc236a8a8c8d7a2d4654b32a49 Mon Sep 17 00:00:00 2001 From: Mateusz Gancarz Date: Mon, 23 Jun 2025 09:33:55 +0200 Subject: [PATCH 095/198] synth: pass flatten flag to synth pass explicitly Signed-off-by: Mateusz Gancarz --- docs/user/FlowVariables.md | 2 +- flow/scripts/synth.tcl | 5 ++--- flow/scripts/variables.yaml | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 92d562a6f6..7776a48be3 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -218,7 +218,7 @@ configuration file. | SKIP_PIN_SWAP| Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).| | | | SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| | | | SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| | | -| SYNTH_ARGS| Optional synthesis variables for yosys.| -flatten| | +| SYNTH_ARGS| Optional synthesis variables for yosys.| | | | SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| | | | SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | | | SYNTH_HDL_FRONTEND| Select an alternative language frontend to ingest the design. Available option is "slang". If the variable is empty, design is read with the Yosys read_verilog command.| | | diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl index 0d6b2a44c5..087856ceaf 100644 --- a/flow/scripts/synth.tcl +++ b/flow/scripts/synth.tcl @@ -30,8 +30,7 @@ if {[env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS]} { if {![env_var_equals SYNTH_HIERARCHICAL 1]} { # Perform standard coarse-level synthesis script, flatten right away - # (-flatten part of $synth_args per default) - synth -run :fine {*}$synth_full_args + synth -flatten -run :fine {*}$synth_full_args } else { # Perform standard coarse-level synthesis script, # defer flattening until we have decided what hierarchy to keep @@ -48,7 +47,7 @@ if {![env_var_equals SYNTH_HIERARCHICAL 1]} { } # Re-run coarse-level script, this time do pass -flatten - synth -run coarse:fine {*}$synth_full_args + synth -flatten -run coarse:fine {*}$synth_full_args } json -o $::env(RESULTS_DIR)/mem.json diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 9bcd9325da..3aedb6f220 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -683,7 +683,7 @@ SYNTH_KEEP_MODULES: SYNTH_ARGS: description: | Optional synthesis variables for yosys. - default: -flatten + default: "" SYNTH_HIER_SEPARATOR: description: | Separator used for the synthesis flatten stage. From c0c9825ad2396a01bcdb337b8b603014a488b1aa Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Mon, 23 Jun 2025 18:42:11 +0000 Subject: [PATCH 096/198] added support for AutoTuner to stop after a specified stage missed error handling Signed-off-by: Jeff Ng --- flow/Makefile | 3 ++- tools/AutoTuner/src/autotuner/distributed.py | 23 ++++++++++++----- tools/AutoTuner/src/autotuner/utils.py | 27 +++++++++++++------- 3 files changed, 36 insertions(+), 17 deletions(-) diff --git a/flow/Makefile b/flow/Makefile index b831987275..c96bf8f3c6 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -541,7 +541,8 @@ clean_cts: route: $(RESULTS_DIR)/5_route.odb \ $(RESULTS_DIR)/5_route.sdc -.PHONY: grt +.PHONY: grt globalroute +globalroute: grt grt: $(RESULTS_DIR)/5_1_grt.odb # ============================================================================== diff --git a/tools/AutoTuner/src/autotuner/distributed.py b/tools/AutoTuner/src/autotuner/distributed.py index 5d3e3e75d1..2d87b710ac 100644 --- a/tools/AutoTuner/src/autotuner/distributed.py +++ b/tools/AutoTuner/src/autotuner/distributed.py @@ -154,8 +154,8 @@ def step(self): install_path=INSTALL_PATH, ) self.step_ += 1 - (score, effective_clk_period, num_drc) = self.evaluate( - read_metrics(metrics_file) + (score, effective_clk_period, num_drc, die_area) = self.evaluate( + read_metrics(metrics_file, args.stop_stage) ) # Feed the score back to Tune. # return must match 'metric' used in tune.run() @@ -163,6 +163,7 @@ def step(self): METRIC: score, "effective_clk_period": effective_clk_period, "num_drc": num_drc, + "die_area": die_area, } def evaluate(self, metrics): @@ -174,13 +175,13 @@ def evaluate(self, metrics): error = "ERR" in metrics.values() not_found = "N/A" in metrics.values() if error or not_found: - return (ERROR_METRIC, "-", "-") + return (ERROR_METRIC, "-", "-", "-") effective_clk_period = metrics["clk_period"] - metrics["worst_slack"] num_drc = metrics["num_drc"] gamma = effective_clk_period / 10 score = effective_clk_period score = score * (100 / self.step_) + gamma * num_drc - return (score, effective_clk_period, num_drc) + return (score, effective_clk_period, num_drc, metrics["die_area"]) def _is_valid_config(self, config): """ @@ -247,13 +248,13 @@ def evaluate(self, metrics): error = "ERR" in metrics.values() or "ERR" in reference.values() not_found = "N/A" in metrics.values() or "N/A" in reference.values() if error or not_found: - return (ERROR_METRIC, "-", "-") + return (ERROR_METRIC, "-", "-", "-") ppa = self.get_ppa(metrics) gamma = ppa / 10 score = ppa * (self.step_ / 100) ** (-1) + (gamma * metrics["num_drc"]) effective_clk_period = metrics["clk_period"] - metrics["worst_slack"] num_drc = metrics["num_drc"] - return (score, effective_clk_period, num_drc) + return (score, effective_clk_period, num_drc, metrics["die_area"]) def parse_arguments(): @@ -307,6 +308,14 @@ def parse_arguments(): default=None, help="Time limit (in hours) for each trial run. Default is no limit.", ) + parser.add_argument( + "--stop_stage", + type=str, + metavar="", + choices=["floorplan", "place", "cts", "globalroute", "route", "finish"], + default="finish", + help="Name of the stage to stop after. Default is finish.", + ) tune_parser.add_argument( "--resume", action="store_true", @@ -598,7 +607,7 @@ def main(): TrainClass = set_training_class(args.eval) # PPAImprov requires a reference file to compute training scores. if args.eval == "ppa-improv": - reference = read_metrics(args.reference) + reference = read_metrics(args.reference, args.stop_stage) tune_args = dict( name=args.experiment, diff --git a/tools/AutoTuner/src/autotuner/utils.py b/tools/AutoTuner/src/autotuner/utils.py index b503f1fec9..61aebb3390 100644 --- a/tools/AutoTuner/src/autotuner/utils.py +++ b/tools/AutoTuner/src/autotuner/utils.py @@ -330,6 +330,8 @@ def openroad( make_command += f" FLOW_VARIANT={flow_variant} {parameters}" make_command += " EQUIVALENCE_CHECK=0" make_command += f" NUM_CORES={args.openroad_threads} SHELL=bash" + if args.stop_stage != "finish": + make_command += f" {args.stop_stage}" run_command( args, make_command, @@ -358,22 +360,29 @@ def openroad( return metrics_file -def read_metrics(file_name): +def read_metrics(file_name, stop_stage): """ Collects metrics to evaluate the user-defined objective function. + + stop_stage indicates the last stage executed, so get most of the metrics + from that stage. The default stop stage is "finish". But if the run stops + before "finish", then no need to extract the metrics from the route stage, + so set them to 0 """ with open(file_name) as file: data = json.load(file) clk_period = 9999999 worst_slack = "ERR" - wirelength = "ERR" - num_drc = "ERR" total_power = "ERR" core_util = "ERR" final_util = "ERR" design_area = "ERR" die_area = "ERR" core_area = "ERR" + if stop_stage != "finish": + num_drc = wirelength = 0 + else: + num_drc = wirelength = "ERR" for stage_name, value in data.items(): if stage_name == "constraints" and len(value["clocks__details"]) > 0: clk_period = float(value["clocks__details"][0].split()[1]) @@ -383,17 +392,17 @@ def read_metrics(file_name): num_drc = value["route__drc_errors"] if stage_name == "detailedroute" and "route__wirelength" in value: wirelength = value["route__wirelength"] - if stage_name == "finish" and "timing__setup__ws" in value: + if stage_name == stop_stage and "timing__setup__ws" in value: worst_slack = value["timing__setup__ws"] - if stage_name == "finish" and "power__total" in value: + if stage_name == stop_stage and "power__total" in value: total_power = value["power__total"] - if stage_name == "finish" and "design__instance__utilization" in value: + if stage_name == stop_stage and "design__instance__utilization" in value: final_util = value["design__instance__utilization"] - if stage_name == "finish" and "design__instance__area" in value: + if stage_name == stop_stage and "design__instance__area" in value: design_area = value["design__instance__area"] - if stage_name == "finish" and "design__core__area" in value: + if stage_name == stop_stage and "design__core__area" in value: core_area = value["design__core__area"] - if stage_name == "finish" and "design__die__area" in value: + if stage_name == stop_stage and "design__die__area" in value: die_area = value["design__die__area"] ret = { "clk_period": clk_period, From 6ce64c5e77909a77159641d1f202f4c21ae572aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 24 Jun 2025 18:15:16 +0200 Subject: [PATCH 097/198] variables: cleanup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/scripts/variables.yaml | 5 ----- 1 file changed, 5 deletions(-) diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 3aedb6f220..ef57182459 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -377,7 +377,6 @@ PLACE_PINS_ARGS: Arguments to place_pins stages: - place - default: "" PLACE_DENSITY: description: > The desired average placement density of cells: 1.0 = dense, 0.0 = widely spread. @@ -407,7 +406,6 @@ GLOBAL_PLACEMENT_ARGS: description: > Use additional tuning parameters during global placement other than default args defined in global_place.tcl. - default: "" ENABLE_DPO: description: | Enable detail placement with improve_placement feature. @@ -603,7 +601,6 @@ VERILOG_DEFINES: description: > Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF` - default: "" stages: - synth SDC_FILE: @@ -683,7 +680,6 @@ SYNTH_KEEP_MODULES: SYNTH_ARGS: description: | Optional synthesis variables for yosys. - default: "" SYNTH_HIER_SEPARATOR: description: | Separator used for the synthesis flatten stage. @@ -693,7 +689,6 @@ VERILOG_TOP_PARAMS: Apply toplevel params (if exist). stages: - synth - default: "" CORE_ASPECT_RATIO: description: > The core aspect ratio (height / width). This value is ignored if From 11ef0f6b32edc509ff87b4effe89d762816a5421 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 24 Jun 2025 18:15:16 +0200 Subject: [PATCH 098/198] variables: cleanup, fix errors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/scripts/synth.tcl | 2 +- flow/scripts/synth_canonicalize.tcl | 2 +- flow/scripts/synth_preamble.tcl | 10 ++++++---- flow/scripts/util.tcl | 8 ++++++++ 4 files changed, 16 insertions(+), 6 deletions(-) diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl index 087856ceaf..7b67ead8ea 100644 --- a/flow/scripts/synth.tcl +++ b/flow/scripts/synth.tcl @@ -21,7 +21,7 @@ if {[env_var_exists_and_non_empty SYNTH_HIER_SEPARATOR]} { scratchpad -set flatten.separator $::env(SYNTH_HIER_SEPARATOR) } -set synth_full_args $::env(SYNTH_ARGS) +set synth_full_args [env_var_or_empty SYNTH_ARGS] if {[env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS]} { set synth_full_args [concat $synth_full_args $::env(SYNTH_OPERATIONS_ARGS)] } else { diff --git a/flow/scripts/synth_canonicalize.tcl b/flow/scripts/synth_canonicalize.tcl index c66d4b58ed..f53ca13219 100644 --- a/flow/scripts/synth_canonicalize.tcl +++ b/flow/scripts/synth_canonicalize.tcl @@ -1,7 +1,7 @@ source $::env(SCRIPTS_DIR)/synth_preamble.tcl read_design_sources -dict for {key value} $::env(VERILOG_TOP_PARAMS) { +dict for {key value} [env_var_or_empty VERILOG_TOP_PARAMS] { # Apply toplevel parameters chparam -set $key $value $::env(DESIGN_NAME) } diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl index 240b292ed6..170793fcf4 100644 --- a/flow/scripts/synth_preamble.tcl +++ b/flow/scripts/synth_preamble.tcl @@ -48,20 +48,22 @@ proc read_design_sources {} { plugin -i slang yosys read_slang -D SYNTHESIS --keep-hierarchy --compat=vcs \ --ignore-assertions --top $::env(DESIGN_NAME) \ - {*}$vIdirsArgs {*}$::env(VERILOG_FILES) {*}$::env(VERILOG_DEFINES) + {*}$vIdirsArgs {*}$::env(VERILOG_FILES) {*}[env_var_or_empty VERILOG_DEFINES] # Workaround for yosys-slang#119 setattr -unset init } elseif {[env_var_equals SYNTH_HDL_FRONTEND verific]} { if {[env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS]} { - verific -vlog-incdir {*}$::env(VERILOG_INCLUDE_DIRS) + verific -vlog-incdir {*}$::env(VERILOG_INCLUDE_DIRS) } if {[env_var_exists_and_non_empty VERILOG_DEFINES]} { - verific -vlog-define {*}$::env(VERILOG_DEFINES) + verific -vlog-define {*}$::env(VERILOG_DEFINES) } verific -sv2012 {*}$::env(VERILOG_FILES) } elseif {![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND]} { verilog_defaults -push - verilog_defaults -add {*}$::env(VERILOG_DEFINES) + if {[env_var_exists_and_non_empty VERILOG_DEFINES]} { + verilog_defaults -add {*}$::env(VERILOG_DEFINES) + } foreach file $::env(VERILOG_FILES) { read_verilog -defer -sv {*}$vIdirsArgs $file } diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl index 972892c1a3..b142d51c8b 100644 --- a/flow/scripts/util.tcl +++ b/flow/scripts/util.tcl @@ -124,6 +124,14 @@ proc append_env_var {list_name var_name prefix has_arg} { } } +# Non-empty defaults should go into variables.yaml, generally +proc env_var_or_empty {env_var} { + if {[env_var_exists_and_non_empty $env_var]} { + return $::env($env_var) + } + return "" +} + proc find_macros {} { set macros "" From 0b7828e1bdb267cc039bb4cf4f9c3622e7c48560 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 24 Jun 2025 18:15:16 +0200 Subject: [PATCH 099/198] variables: cleanup, fix errors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/scripts/global_place.tcl | 2 +- flow/scripts/global_place_skip_io.tcl | 2 +- flow/scripts/io_placement.tcl | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/flow/scripts/global_place.tcl b/flow/scripts/global_place.tcl index ea7448311f..aa2b8ffc05 100644 --- a/flow/scripts/global_place.tcl +++ b/flow/scripts/global_place.tcl @@ -39,7 +39,7 @@ proc do_placement {global_placement_args} { -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)] \ $global_placement_args] - lappend all_args {*}$::env(GLOBAL_PLACEMENT_ARGS) + lappend all_args {*}[env_var_or_empty GLOBAL_PLACEMENT_ARGS] log_cmd global_placement {*}$all_args } diff --git a/flow/scripts/global_place_skip_io.tcl b/flow/scripts/global_place_skip_io.tcl index fa9a53d537..599d7d90b4 100644 --- a/flow/scripts/global_place_skip_io.tcl +++ b/flow/scripts/global_place_skip_io.tcl @@ -8,7 +8,7 @@ if { [env_var_exists_and_non_empty FLOORPLAN_DEF] } { log_cmd global_placement -skip_io -density [place_density_with_lb_addon] \ -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ - {*}$::env(GLOBAL_PLACEMENT_ARGS) + {*}[env_var_or_empty GLOBAL_PLACEMENT_ARGS] } write_db $::env(RESULTS_DIR)/3_1_place_gp_skip_io.odb diff --git a/flow/scripts/io_placement.tcl b/flow/scripts/io_placement.tcl index dc29acc671..9de14f7154 100644 --- a/flow/scripts/io_placement.tcl +++ b/flow/scripts/io_placement.tcl @@ -8,7 +8,7 @@ if {![env_var_exists_and_non_empty FLOORPLAN_DEF] && \ log_cmd place_pins \ -hor_layers $::env(IO_PLACER_H) \ -ver_layers $::env(IO_PLACER_V) \ - {*}$::env(PLACE_PINS_ARGS) + {*}[env_var_or_empty PLACE_PINS_ARGS] write_db $::env(RESULTS_DIR)/3_2_place_iop.odb write_pin_placement $::env(RESULTS_DIR)/3_2_place_iop.tcl } else { From db3db460bbc9a6687e17cab747271d7b148509c5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Thu, 26 Jun 2025 03:54:37 +0200 Subject: [PATCH 100/198] README: add bazel-orfs as an installation option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- README.md | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/README.md b/README.md index 56d3a2a1f7..515be0b597 100644 --- a/README.md +++ b/README.md @@ -46,6 +46,14 @@ timeline ## Tool Installation +There are different ways to install and develop OpenROAD and ORFS, which is the best fit depends use-case, experience and personal taste. + +### Use Bazel, avoid installing anything at all and adapt the flow to your needs in your own repository + +[bazel-orfs](https://github.com/The-OpenROAD-Project/bazel-orfs) provides a seamless, reproducible way to manage dependencies and adapt the flow without requiring manual installations(no Docker images, sudo bash scripts, etc.) + +By leveraging [Bazel](https://bazel.build/)'s robust build system, all dependencies are automatically resolved, versioned, and built in a consistent environment. This eliminates setup complexity, ensures fast incremental builds, and allows for easy customization of the flow, making it an efficient choice for both [beginners](https://github.com/Pinata-Consulting/RegFileStudy) and [advanced](https://github.com/The-OpenROAD-Project/megaboom) users. + ### Docker Based Installation To ease dependency installation issues, ORFS uses docker images. From 4abb2be8f5daf25c62710997722d5a0183099f60 Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Thu, 26 Jun 2025 06:21:53 -0700 Subject: [PATCH 101/198] initial AutoTuner config for asap7 cva6 Signed-off-by: Jeff Ng --- flow/designs/asap7/cva6/autotuner.json | 43 ++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 flow/designs/asap7/cva6/autotuner.json diff --git a/flow/designs/asap7/cva6/autotuner.json b/flow/designs/asap7/cva6/autotuner.json new file mode 100644 index 0000000000..a7315e9578 --- /dev/null +++ b/flow/designs/asap7/cva6/autotuner.json @@ -0,0 +1,43 @@ +{ + "_SDC_FILE_PATH": "constraint.sdc", + "_SDC_CLK_PERIOD": { + "type": "float", + "minmax": [ + 1000, + 1300 + ], + "step": 0 + }, + "CORE_UTILIZATION": { + "type": "int", + "minmax": [ + 65, + 75 + ], + "step": 1 + }, + "CORE_MARGIN": { + "type": "float", + "minmax": [ + 1.5, + 2 + ], + "step": 1 + }, + "CTS_CLUSTER_SIZE": { + "type": "int", + "minmax": [ + 40, + 60 + ], + "step": 1 + }, + "CTS_CLUSTER_DIAMETER": { + "type": "int", + "minmax": [ + 15, + 25 + ], + "step": 1 + } +} From 0b4e67a80a8ac3ea5eb41580bd4bc619496de66b Mon Sep 17 00:00:00 2001 From: arthurjolo Date: Thu, 26 Jun 2025 16:28:53 -0300 Subject: [PATCH 102/198] remove bp_single '-no_insertion_delay' Signed-off-by: arthurjolo --- flow/designs/gf12/bp_single/config.mk | 3 --- 1 file changed, 3 deletions(-) diff --git a/flow/designs/gf12/bp_single/config.mk b/flow/designs/gf12/bp_single/config.mk index 83e6a775b3..53f9f1d165 100644 --- a/flow/designs/gf12/bp_single/config.mk +++ b/flow/designs/gf12/bp_single/config.mk @@ -66,8 +66,5 @@ else export DESIGN_TYPE = CHIP_NODEN endif -# Override cts arguments to set `-no_insertion_delay` -export CTS_ARGS = -no_insertion_delay -sink_clustering_enable -balance_levels -repair_clock_nets - # enable slack margin for setup and hold fix after CTS export SETUP_SLACK_MARGIN ?= 100 From 5dda947cdea1102808c8c376fe3bb19dc67513b7 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Fri, 27 Jun 2025 05:04:47 +0000 Subject: [PATCH 103/198] Only do setup repair in floorplan.tcl Too early for hold and it creates new buffers with meaningless locations. Signed-off-by: Matt Liberty --- flow/scripts/floorplan.tcl | 2 +- flow/scripts/util.tcl | 6 +++--- tools/OpenROAD | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/flow/scripts/floorplan.tcl b/flow/scripts/floorplan.tcl index 9fb66c1b92..40137811ed 100644 --- a/flow/scripts/floorplan.tcl +++ b/flow/scripts/floorplan.tcl @@ -110,7 +110,7 @@ if { [env_var_equals REMOVE_ABC_BUFFERS 1] } { # Skip clone & split set ::env(SETUP_MOVE_SEQUENCE) "unbuffer,sizeup,swap,buffer" set ::env(SKIP_LAST_GASP) 1 - repair_timing_helper 0 + repair_timing_helper -setup } puts "Default units for flow" diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl index b142d51c8b..1c5b29e988 100644 --- a/flow/scripts/util.tcl +++ b/flow/scripts/util.tcl @@ -22,10 +22,10 @@ proc fast_route {} { } } -proc repair_timing_helper { {hold_margin 1} } { - set additional_args "-verbose" +proc repair_timing_helper { args } { + set additional_args "$args -verbose" append_env_var additional_args SETUP_SLACK_MARGIN -setup_margin 1 - if {$hold_margin || $::env(HOLD_SLACK_MARGIN) < 0} { + if {$::env(HOLD_SLACK_MARGIN) < 0} { append_env_var additional_args HOLD_SLACK_MARGIN -hold_margin 1 } append_env_var additional_args SETUP_MOVE_SEQUENCE -sequence 1 diff --git a/tools/OpenROAD b/tools/OpenROAD index e743761ef8..c79c8317e0 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit e743761ef889c67a4cc3475b23be78358c9f5ace +Subproject commit c79c8317e05ecbf45eba5096a74cb421ab97b7ae From b8f25756c4676424fb490bda47965a6cc7fa684a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 27 Jun 2025 07:18:26 +0200 Subject: [PATCH 104/198] docs: more readable deprecated annotation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove extra column used by deprecated variables only(1 currently...) Signed-off-by: Øyvind Harboe --- docs/user/FlowVariables.md | 306 ++++++++++++------------ flow/scripts/generate-variables-docs.py | 6 +- 2 files changed, 156 insertions(+), 156 deletions(-) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 7776a48be3..b70a868afa 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -88,159 +88,159 @@ configuration file. ## Variables in alphabetic order -| Variable | Description | Default | Deprecated | -| --- | --- | --- | --- | -| ABC_AREA| Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED.| 0| | -| ABC_CLOCK_PERIOD_IN_PS| Clock period to be used by STA during synthesis. Default value read from `constraint.sdc`.| | | -| ABC_DRIVER_CELL| Default driver cell used during ABC synthesis.| | | -| ABC_LOAD_IN_FF| During synthesis set_load value used.| | | -| ABSTRACT_SOURCE| Which .odb file to use to create abstract| | | -| ADDER_MAP_FILE| List of adders treated as a black box by Yosys.| | | -| ADDITIONAL_FILES| Additional files to be added to `make issue` archive.| | | -| ADDITIONAL_GDS| Hardened macro GDS files listed here.| | | -| ADDITIONAL_LEFS| Hardened macro LEF view files listed here. The LEF information of the macros is immutable and used throughout all stages. Stored in the .odb file.| | | -| ADDITIONAL_LIBS| Hardened macro library files listed here. The library information is immutable and used throughout all stages. Not stored in the .odb file.| | | -| BLOCKS| Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile.| | | -| CAP_MARGIN| Specifies a capacitance margin when fixing max capacitance violations. This option allows you to overfix.| | | -| CDL_FILES| Insert additional Circuit Description Language (`.cdl`) netlist files.| | | -| CELL_PAD_IN_SITES_DETAIL_PLACEMENT| Cell padding on both sides in site widths to ease routability in detail placement.| 0| | -| CELL_PAD_IN_SITES_GLOBAL_PLACEMENT| Cell padding on both sides in site widths to ease routability during global placement.| 0| | -| CLKGATE_MAP_FILE| List of cells for gating clock treated as a black box by Yosys.| | | -| CORE_AREA| The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | | -| CORE_ASPECT_RATIO| The core aspect ratio (height / width). This value is ignored if `CORE_UTILIZATION` is undefined.| | | -| CORE_MARGIN| The margin between the core area and die area, specified in microns. Allowed values are either one value for all margins or a set of four values, one for each margin. The order of the four values are: `{bottom top left right}`. This variable is ignored if `CORE_UTILIZATION` is undefined.| | | -| CORE_UTILIZATION| The core utilization percentage (0-100).| | | -| CORNER| PVT corner library selection. Only available for ASAP7 and GF180 PDKs.| | | -| CTS_ARGS| Override `clock_tree_synthesis` arguments.| | | -| CTS_BUF_DISTANCE| Distance (in microns) between buffers.| | | -| CTS_BUF_LIST| List of cells used to construct the clock tree. Overrides buffer inference.| | | -| CTS_CLUSTER_DIAMETER| Maximum diameter (in microns) of sink cluster.| 20| | -| CTS_CLUSTER_SIZE| Maximum number of sinks per cluster.| 50| | -| CTS_LIB_NAME| Name of the Liberty library to use in selecting the clock buffers.| | | -| CTS_SNAPSHOT| Creates ODB/SDC files prior to clock net and setup/hold repair.| | | -| DESIGN_NAME| The name of the top-level module of the design.| | | -| DESIGN_NICKNAME| DESIGN_NICKNAME just changes the directory name that ORFS outputs to be DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a different design.| | | -| DETAILED_METRICS| If set, then calls report_metrics prior to repair operations in the CTS and global route stages| 0| | -| DETAILED_ROUTE_ARGS| Add additional arguments for debugging purposes during detail route.| | | -| DETAILED_ROUTE_END_ITERATION| Maximum number of iterations.| 64| | -| DFF_LIB_FILES| Technology mapping liberty files for flip-flops.| | | -| DIE_AREA| The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | | -| DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| | | -| DONT_USE_LIBS| Set liberty files as `dont_use`.| | | -| DPO_MAX_DISPLACEMENT| Specifies how far an instance can be moved when optimizing.| 5 1| | -| ENABLE_DPO| Enable detail placement with improve_placement feature.| 1| | -| EQUIVALENCE_CHECK| Enable running equivalence checks to verify logical correctness of repair_timing.| 0| | -| FASTROUTE_TCL| Specifies a Tcl script with commands to run before FastRoute.| | | -| FILL_CELLS| Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped.| | | -| FILL_CONFIG| JSON rule file for metal fill during chip finishing.| | | -| FLOORPLAN_DEF| Use the DEF file to initialize floorplan.| | | -| FLOW_VARIANT| Flow variant to use, used in the flow variant directory name.| base| | -| GDS_ALLOW_EMPTY| Regular expression of module names of macros that have no .gds file| | | -| GDS_FILES| Path to platform GDS files.| | | -| GENERATE_ARTIFACTS_ON_FAILURE| For instance Bazel needs artifacts (.odb and .rpt files) on a failure to allow the user to save hours on re-running the failed step locally, but when working with a Makefile flow, it is more natural to fail the step and leave the user to manually inspect the logs and artifacts directly via the file system. Set to 1 to change the behavior to generate artifacts upon failure to e.g. do a global route. The exit code will still be non-zero on all other failures that aren't covered by the "useful to inspect the artifacts on failure" use-case. Example: just like detailed routing, a global route that fails with congestion, is not a build failure(as in exit code non-zero), it is a successful(as in zero exit code) global route that produce reports detailing the problem. Detailed route will not proceed, if there is global routing congestion This allows build systems, such as bazel, to create artifacts for global and detailed route, even if the operation had problems, without having know about the semantics between global and detailed route. Considering that global and detailed route can run for a long time and use a lot of memory, this allows inspecting results on a laptop for a build that ran on a server.| 0| | -| GLOBAL_PLACEMENT_ARGS| Use additional tuning parameters during global placement other than default args defined in global_place.tcl.| | | -| GLOBAL_ROUTE_ARGS| Replaces default arguments for global route.| -congestion_iterations 30 -congestion_report_iter_step 5 -verbose| | -| GND_NETS_VOLTAGES| Used for IR Drop calculation.| | | -| GPL_ROUTABILITY_DRIVEN| Specifies whether the placer should use routability driven placement.| 1| | -| GPL_TIMING_DRIVEN| Specifies whether the placer should use timing driven placement.| 1| | -| GUI_TIMING| Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc.| 1| | -| HOLD_SLACK_MARGIN| Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix or underfix (negative value, terminate retiming before 0 or positive slack). floorplan.tcl uses min of HOLD_SLACK_MARGIN and 0 (default hold slack margin). This avoids overrepair in floorplan for hold by default, but allows skipping hold repair using a negative HOLD_SLACK_MARGIN. Exiting timing repair early is useful in exploration where the .sdc has a fixed clock period at the design's target clock period and where HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair (extremely long running times) when exploring different parameter settings. When an ideal clock is used, that is before CTS, a clock insertion delay of 0 is used in timing paths. This creates a mismatch between macros that have a .lib file from after CTS, when the clock is propagated. To mitigate this, OpenSTA will use subtract the clock insertion delay of macros when calculating timing with ideal clock. Provided that min_clock_tree_path and max_clock_tree_path are in the .lib file, which is the case for macros built with OpenROAD. This is less accurate than if OpenROAD had created a placeholder clock tree for timing estimation purposes prior to CTS. There will inevitably be inaccuracies in the timing calculation prior to CTS. Use a slack margin that is low enough, even negative, to avoid overrepair. Inaccuracies in the timing prior to CTS can also lead to underrepair, but there no obvious and simple way to avoid underrapir in these cases. Overrepair can lead to excessive runtimes in repair or too much buffering being added, which can present itself as congestion of hold cells or buffer cells. Another use of SETUP/HOLD_SLACK_MARGIN is design parameter exploration when trying to find the minimum clock period for a design. The SDC_FILE for a design can be quite complicated and instead of modifying the clock period in the SDC_FILE, which can be non-trivial, the clock period can be fixed at the target frequency and the SETUP/HOLD_SLACK_MARGIN can be swept to find a plausible current minimum clock period.| 0| | -| IO_CONSTRAINTS| File path to the IO constraints .tcl file.| | | -| IO_PLACER_H| A list of metal layers on which the I/O pins are placed horizontally (top and bottom of the die).| | | -| IO_PLACER_V| A list of metal layers on which the I/O pins are placed vertically (sides of the die).| | | -| IR_DROP_LAYER| Default metal layer to report IR drop.| | | -| KLAYOUT_TECH_FILE| A mapping from LEF/DEF to GDS using the KLayout tool.| | | -| LATCH_MAP_FILE| List of latches treated as a black box by Yosys.| | | -| LIB_FILES| A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.| | | -| MACRO_BLOCKAGE_HALO| Distance beyond the edges of a macro that will also be covered by the blockage generated for that macro. Note that the default macro blockage halo comes from the largest of the specified MACRO_PLACE_HALO x or y values. This variable overrides that calculation.| | | -| MACRO_EXTENSION| Sets the number of GCells added to the blockages boundaries from macros.| | | -| MACRO_PLACEMENT| Specifies the path of a file on how to place certain macros manually using read_macro_placement.| | | -| MACRO_PLACEMENT_TCL| Specifies the path of a TCL file on how to place certain macros manually.| | | -| MACRO_PLACE_HALO| Horizontal/vertical halo around macros (microns). Used by automatic macro placement.| | | -| MACRO_ROWS_HALO_X| Horizontal distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.| | | -| MACRO_ROWS_HALO_Y| Vertical distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.| | | -| MACRO_WRAPPERS| The wrapper file that replaces existing macros with their wrapped version.| | | -| MAKE_TRACKS| Tcl file that defines add routing tracks to a floorplan.| | | -| MATCH_CELL_FOOTPRINT| Enforce sizing operations to only swap cells that have the same layout boundary.| 0| | -| MAX_ROUTING_LAYER| The highest metal layer name to be used in routing.| | | -| MIN_BUF_CELL_AND_PORTS| Used to insert a buffer cell to pass through wires. Used in synthesis.| | | -| MIN_ROUTING_LAYER| The lowest metal layer name to be used in routing.| | | -| PDN_TCL| File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.| | | -| PLACE_DENSITY| The desired average placement density of cells: 1.0 = dense, 0.0 = widely spread. The intended effort is also communicated by this parameter. Use a low value for faster builds and higher value for better quality of results. If a too low value is used, the placer will not be able to place all cells and a recommended minimum placement density can be found in the logs. A too high value can lead to excessive runtimes, even timeouts and subtle failures in the flow after placement, such as in CTS or global routing when timing repair fails. The default is platform specific.| | | -| PLACE_DENSITY_LB_ADDON| Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists.| | | -| PLACE_PINS_ARGS| Arguments to place_pins| | | -| PLACE_SITE| Placement site for core cells defined in the technology LEF file.| | | -| PLATFORM| Specifies process design kit or technology node to be used.| | | -| PLATFORM_TCL| Specifies a Tcl script with commands to run before loading design.| | | -| POST_CTS_TCL| Specifies a Tcl script with commands to run after CTS is completed.| | | -| PROCESS| Technology node or process in use.| | | -| PWR_NETS_VOLTAGES| Used for IR Drop calculation.| | | -| RCX_RULES| RC Extraction rules file path.| | | -| RECOVER_POWER| Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].| 0| | -| REMOVE_ABC_BUFFERS| Remove abc buffers from the netlist. If timing repair in floorplanning is taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.| | yes| -| REMOVE_CELLS_FOR_EQY| String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.| | | -| REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| | | -| REPORT_CLOCK_SKEW| Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable.| 1| | -| ROUTING_LAYER_ADJUSTMENT| Adjusts routing layer capacities to manage congestion and improve detailed routing. High values ease detailed routing but risk excessive detours and long global routing times, while low values reduce global routing failure but can complicate detailed routing. The global routing running time normally reduces dramatically (entirely design specific, but going from hours to minutes has been observed) when the value is low (such as 0.10). Sometimes, global routing will succeed with lower values and fail with higher values. Exploring results with different values can help shed light on the problem. Start with a too low value, such as 0.10, and bisect to value that works by doing multiple global routing runs. As a last resort, `make global_route_issue` and using the tools/OpenROAD/etc/deltaDebug.py can be useful to debug global routing errors. If there is something specific that is impossible to route, such as a clock line over a macro, global routing will terminate with DRC errors routes that could have been routed were it not for the specific impossible routes. deltaDebug.py should weed out the possible routes and leave a minimal failing case that pinpoints the problem.| 0.5| | -| RTLMP_AREA_WT| Weight for the area of the current floorplan.| 0.1| | -| RTLMP_ARGS| Overrides all other RTL macro placer arguments.| | | -| RTLMP_BOUNDARY_WT| Weight for the boundary or how far the hard macro clusters are from boundaries.| 50.0| | -| RTLMP_DEAD_SPACE| Specifies the target dead space percentage, which influences the utilization of a cluster.| 0.05| | -| RTLMP_FENCE_LX| Defines the lower left X coordinate for the global fence bounding box in microns.| 0.0| | -| RTLMP_FENCE_LY| Defines the lower left Y coordinate for the global fence bounding box in microns.| 0.0| | -| RTLMP_FENCE_UX| Defines the upper right X coordinate for the global fence bounding box in microns.| 100000000.0| | -| RTLMP_FENCE_UY| Defines the upper right Y coordinate for the global fence bounding box in microns.| 100000000.0| | -| RTLMP_MAX_INST| Maximum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | | -| RTLMP_MAX_LEVEL| Maximum depth of the physical hierarchy tree.| 2| | -| RTLMP_MAX_MACRO| Maximum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | | -| RTLMP_MIN_AR| Specifies the minimum aspect ratio (height/width).| 0.33| | -| RTLMP_MIN_INST| Minimum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | | -| RTLMP_MIN_MACRO| Minimum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | | -| RTLMP_NOTCH_WT| Weight for the notch, or the existence of dead space that cannot be used for placement and routing.| 10.0| | -| RTLMP_OUTLINE_WT| Weight for violating the fixed outline constraint, meaning that all clusters should be placed within the shape of their parent cluster.| 100.0| | -| RTLMP_RPT_DIR| Path to the directory where reports are saved.| | | -| RTLMP_SIGNATURE_NET_THRESHOLD| Minimum number of connections between two clusters to be identified as connected.| 50| | -| RTLMP_WIRELENGTH_WT| Weight for half-perimiter wirelength.| 100.0| | -| RULES_JSON| json files with the metrics baseline regression rules. In the ORFS Makefile, this defaults to $DESIGN_DIR/rules-base.json, but ORFS does not mandate the users source directory layout and this can be placed elsewhere when the user sets up an ORFS config.mk or from bazel-orfs.| | | -| RUN_LOG_NAME_STEM| Stem of the log file name, the log file will be named `$(LOG_DIR)/$(RUN_LOG_NAME_STEM).log`.| run| | -| RUN_SCRIPT| Path to script to run from `make run`, python or tcl script detected by .py or .tcl extension.| | | -| SC_LEF| Path to technology standard cell LEF file.| | | -| SDC_FILE| The path to design constraint (SDC) file.| | | -| SDC_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | | -| SEAL_GDS| Seal macro to place around the design.| | | -| SETUP_REPAIR_SEQUENCE| Specifies the sequence of moves to do in repair_timing -setup. This should be a string of move keywords separated by commas such as the default when not used: "unbuffer,sizedown,sizeup,swap,buffer,clone,split".| | | -| SETUP_SLACK_MARGIN| Specifies a time margin for the slack when fixing setup violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). See HOLD_SLACK_MARGIN for more details.| 0| | -| SET_RC_TCL| Metal & Via RC definition file path.| | | -| SKIP_CTS_REPAIR_TIMING| Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running.| | | -| SKIP_GATE_CLONING| Do not use gate cloning transform to fix timing violations (default: use gate cloning).| | | -| SKIP_INCREMENTAL_REPAIR| Skip incremental repair in global route.| 0| | -| SKIP_LAST_GASP| Do not use last gasp optimization to fix timing violations (default: use gate last gasp).| | | -| SKIP_PIN_SWAP| Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).| | | -| SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| | | -| SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| | | -| SYNTH_ARGS| Optional synthesis variables for yosys.| | | -| SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| | | -| SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | | -| SYNTH_HDL_FRONTEND| Select an alternative language frontend to ingest the design. Available option is "slang". If the variable is empty, design is read with the Yosys read_verilog command.| | | -| SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| | -| SYNTH_HIER_SEPARATOR| Separator used for the synthesis flatten stage.| .| | -| SYNTH_KEEP_MODULES| Mark modules to keep from getting removed in flattening.| | | -| SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096| | -| SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| 0| | -| SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| | | -| SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| | | -| TAPCELL_TCL| Path to Endcap and Welltie cells file.| | | -| TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| | | -| TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| | | -| TIEHI_CELL_AND_PORT| Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist.| | | -| TIELO_CELL_AND_PORT| Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.| | | -| TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100| | -| USE_FILL| Whether to perform metal density filling.| 0| | -| VERILOG_DEFINES| Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`| | | -| VERILOG_FILES| The path to the design Verilog/SystemVerilog files providing a description of modules.| | | -| VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| | | -| VERILOG_TOP_PARAMS| Apply toplevel params (if exist).| | | -| YOSYS_FLAGS| Flags to pass to yosys.| -v 3| | +| Variable | Description | Default | +| --- | --- | --- | +| ABC_AREA| Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED.| 0| +| ABC_CLOCK_PERIOD_IN_PS| Clock period to be used by STA during synthesis. Default value read from `constraint.sdc`.| | +| ABC_DRIVER_CELL| Default driver cell used during ABC synthesis.| | +| ABC_LOAD_IN_FF| During synthesis set_load value used.| | +| ABSTRACT_SOURCE| Which .odb file to use to create abstract| | +| ADDER_MAP_FILE| List of adders treated as a black box by Yosys.| | +| ADDITIONAL_FILES| Additional files to be added to `make issue` archive.| | +| ADDITIONAL_GDS| Hardened macro GDS files listed here.| | +| ADDITIONAL_LEFS| Hardened macro LEF view files listed here. The LEF information of the macros is immutable and used throughout all stages. Stored in the .odb file.| | +| ADDITIONAL_LIBS| Hardened macro library files listed here. The library information is immutable and used throughout all stages. Not stored in the .odb file.| | +| BLOCKS| Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile.| | +| CAP_MARGIN| Specifies a capacitance margin when fixing max capacitance violations. This option allows you to overfix.| | +| CDL_FILES| Insert additional Circuit Description Language (`.cdl`) netlist files.| | +| CELL_PAD_IN_SITES_DETAIL_PLACEMENT| Cell padding on both sides in site widths to ease routability in detail placement.| 0| +| CELL_PAD_IN_SITES_GLOBAL_PLACEMENT| Cell padding on both sides in site widths to ease routability during global placement.| 0| +| CLKGATE_MAP_FILE| List of cells for gating clock treated as a black box by Yosys.| | +| CORE_AREA| The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | +| CORE_ASPECT_RATIO| The core aspect ratio (height / width). This value is ignored if `CORE_UTILIZATION` is undefined.| | +| CORE_MARGIN| The margin between the core area and die area, specified in microns. Allowed values are either one value for all margins or a set of four values, one for each margin. The order of the four values are: `{bottom top left right}`. This variable is ignored if `CORE_UTILIZATION` is undefined.| | +| CORE_UTILIZATION| The core utilization percentage (0-100).| | +| CORNER| PVT corner library selection. Only available for ASAP7 and GF180 PDKs.| | +| CTS_ARGS| Override `clock_tree_synthesis` arguments.| | +| CTS_BUF_DISTANCE| Distance (in microns) between buffers.| | +| CTS_BUF_LIST| List of cells used to construct the clock tree. Overrides buffer inference.| | +| CTS_CLUSTER_DIAMETER| Maximum diameter (in microns) of sink cluster.| 20| +| CTS_CLUSTER_SIZE| Maximum number of sinks per cluster.| 50| +| CTS_LIB_NAME| Name of the Liberty library to use in selecting the clock buffers.| | +| CTS_SNAPSHOT| Creates ODB/SDC files prior to clock net and setup/hold repair.| | +| DESIGN_NAME| The name of the top-level module of the design.| | +| DESIGN_NICKNAME| DESIGN_NICKNAME just changes the directory name that ORFS outputs to be DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a different design.| | +| DETAILED_METRICS| If set, then calls report_metrics prior to repair operations in the CTS and global route stages| 0| +| DETAILED_ROUTE_ARGS| Add additional arguments for debugging purposes during detail route.| | +| DETAILED_ROUTE_END_ITERATION| Maximum number of iterations.| 64| +| DFF_LIB_FILES| Technology mapping liberty files for flip-flops.| | +| DIE_AREA| The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | +| DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| | +| DONT_USE_LIBS| Set liberty files as `dont_use`.| | +| DPO_MAX_DISPLACEMENT| Specifies how far an instance can be moved when optimizing.| 5 1| +| ENABLE_DPO| Enable detail placement with improve_placement feature.| 1| +| EQUIVALENCE_CHECK| Enable running equivalence checks to verify logical correctness of repair_timing.| 0| +| FASTROUTE_TCL| Specifies a Tcl script with commands to run before FastRoute.| | +| FILL_CELLS| Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped.| | +| FILL_CONFIG| JSON rule file for metal fill during chip finishing.| | +| FLOORPLAN_DEF| Use the DEF file to initialize floorplan.| | +| FLOW_VARIANT| Flow variant to use, used in the flow variant directory name.| base| +| GDS_ALLOW_EMPTY| Regular expression of module names of macros that have no .gds file| | +| GDS_FILES| Path to platform GDS files.| | +| GENERATE_ARTIFACTS_ON_FAILURE| For instance Bazel needs artifacts (.odb and .rpt files) on a failure to allow the user to save hours on re-running the failed step locally, but when working with a Makefile flow, it is more natural to fail the step and leave the user to manually inspect the logs and artifacts directly via the file system. Set to 1 to change the behavior to generate artifacts upon failure to e.g. do a global route. The exit code will still be non-zero on all other failures that aren't covered by the "useful to inspect the artifacts on failure" use-case. Example: just like detailed routing, a global route that fails with congestion, is not a build failure(as in exit code non-zero), it is a successful(as in zero exit code) global route that produce reports detailing the problem. Detailed route will not proceed, if there is global routing congestion This allows build systems, such as bazel, to create artifacts for global and detailed route, even if the operation had problems, without having know about the semantics between global and detailed route. Considering that global and detailed route can run for a long time and use a lot of memory, this allows inspecting results on a laptop for a build that ran on a server.| 0| +| GLOBAL_PLACEMENT_ARGS| Use additional tuning parameters during global placement other than default args defined in global_place.tcl.| | +| GLOBAL_ROUTE_ARGS| Replaces default arguments for global route.| -congestion_iterations 30 -congestion_report_iter_step 5 -verbose| +| GND_NETS_VOLTAGES| Used for IR Drop calculation.| | +| GPL_ROUTABILITY_DRIVEN| Specifies whether the placer should use routability driven placement.| 1| +| GPL_TIMING_DRIVEN| Specifies whether the placer should use timing driven placement.| 1| +| GUI_TIMING| Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc.| 1| +| HOLD_SLACK_MARGIN| Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix or underfix (negative value, terminate retiming before 0 or positive slack). floorplan.tcl uses min of HOLD_SLACK_MARGIN and 0 (default hold slack margin). This avoids overrepair in floorplan for hold by default, but allows skipping hold repair using a negative HOLD_SLACK_MARGIN. Exiting timing repair early is useful in exploration where the .sdc has a fixed clock period at the design's target clock period and where HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair (extremely long running times) when exploring different parameter settings. When an ideal clock is used, that is before CTS, a clock insertion delay of 0 is used in timing paths. This creates a mismatch between macros that have a .lib file from after CTS, when the clock is propagated. To mitigate this, OpenSTA will use subtract the clock insertion delay of macros when calculating timing with ideal clock. Provided that min_clock_tree_path and max_clock_tree_path are in the .lib file, which is the case for macros built with OpenROAD. This is less accurate than if OpenROAD had created a placeholder clock tree for timing estimation purposes prior to CTS. There will inevitably be inaccuracies in the timing calculation prior to CTS. Use a slack margin that is low enough, even negative, to avoid overrepair. Inaccuracies in the timing prior to CTS can also lead to underrepair, but there no obvious and simple way to avoid underrapir in these cases. Overrepair can lead to excessive runtimes in repair or too much buffering being added, which can present itself as congestion of hold cells or buffer cells. Another use of SETUP/HOLD_SLACK_MARGIN is design parameter exploration when trying to find the minimum clock period for a design. The SDC_FILE for a design can be quite complicated and instead of modifying the clock period in the SDC_FILE, which can be non-trivial, the clock period can be fixed at the target frequency and the SETUP/HOLD_SLACK_MARGIN can be swept to find a plausible current minimum clock period.| 0| +| IO_CONSTRAINTS| File path to the IO constraints .tcl file.| | +| IO_PLACER_H| A list of metal layers on which the I/O pins are placed horizontally (top and bottom of the die).| | +| IO_PLACER_V| A list of metal layers on which the I/O pins are placed vertically (sides of the die).| | +| IR_DROP_LAYER| Default metal layer to report IR drop.| | +| KLAYOUT_TECH_FILE| A mapping from LEF/DEF to GDS using the KLayout tool.| | +| LATCH_MAP_FILE| List of latches treated as a black box by Yosys.| | +| LIB_FILES| A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.| | +| MACRO_BLOCKAGE_HALO| Distance beyond the edges of a macro that will also be covered by the blockage generated for that macro. Note that the default macro blockage halo comes from the largest of the specified MACRO_PLACE_HALO x or y values. This variable overrides that calculation.| | +| MACRO_EXTENSION| Sets the number of GCells added to the blockages boundaries from macros.| | +| MACRO_PLACEMENT| Specifies the path of a file on how to place certain macros manually using read_macro_placement.| | +| MACRO_PLACEMENT_TCL| Specifies the path of a TCL file on how to place certain macros manually.| | +| MACRO_PLACE_HALO| Horizontal/vertical halo around macros (microns). Used by automatic macro placement.| | +| MACRO_ROWS_HALO_X| Horizontal distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.| | +| MACRO_ROWS_HALO_Y| Vertical distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.| | +| MACRO_WRAPPERS| The wrapper file that replaces existing macros with their wrapped version.| | +| MAKE_TRACKS| Tcl file that defines add routing tracks to a floorplan.| | +| MATCH_CELL_FOOTPRINT| Enforce sizing operations to only swap cells that have the same layout boundary.| 0| +| MAX_ROUTING_LAYER| The highest metal layer name to be used in routing.| | +| MIN_BUF_CELL_AND_PORTS| Used to insert a buffer cell to pass through wires. Used in synthesis.| | +| MIN_ROUTING_LAYER| The lowest metal layer name to be used in routing.| | +| PDN_TCL| File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.| | +| PLACE_DENSITY| The desired average placement density of cells: 1.0 = dense, 0.0 = widely spread. The intended effort is also communicated by this parameter. Use a low value for faster builds and higher value for better quality of results. If a too low value is used, the placer will not be able to place all cells and a recommended minimum placement density can be found in the logs. A too high value can lead to excessive runtimes, even timeouts and subtle failures in the flow after placement, such as in CTS or global routing when timing repair fails. The default is platform specific.| | +| PLACE_DENSITY_LB_ADDON| Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists.| | +| PLACE_PINS_ARGS| Arguments to place_pins| | +| PLACE_SITE| Placement site for core cells defined in the technology LEF file.| | +| PLATFORM| Specifies process design kit or technology node to be used.| | +| PLATFORM_TCL| Specifies a Tcl script with commands to run before loading design.| | +| POST_CTS_TCL| Specifies a Tcl script with commands to run after CTS is completed.| | +| PROCESS| Technology node or process in use.| | +| PWR_NETS_VOLTAGES| Used for IR Drop calculation.| | +| RCX_RULES| RC Extraction rules file path.| | +| RECOVER_POWER| Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].| 0| +| REMOVE_ABC_BUFFERS (deprecated)| Remove abc buffers from the netlist. If timing repair in floorplanning is taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.| | +| REMOVE_CELLS_FOR_EQY| String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.| | +| REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| | +| REPORT_CLOCK_SKEW| Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable.| 1| +| ROUTING_LAYER_ADJUSTMENT| Adjusts routing layer capacities to manage congestion and improve detailed routing. High values ease detailed routing but risk excessive detours and long global routing times, while low values reduce global routing failure but can complicate detailed routing. The global routing running time normally reduces dramatically (entirely design specific, but going from hours to minutes has been observed) when the value is low (such as 0.10). Sometimes, global routing will succeed with lower values and fail with higher values. Exploring results with different values can help shed light on the problem. Start with a too low value, such as 0.10, and bisect to value that works by doing multiple global routing runs. As a last resort, `make global_route_issue` and using the tools/OpenROAD/etc/deltaDebug.py can be useful to debug global routing errors. If there is something specific that is impossible to route, such as a clock line over a macro, global routing will terminate with DRC errors routes that could have been routed were it not for the specific impossible routes. deltaDebug.py should weed out the possible routes and leave a minimal failing case that pinpoints the problem.| 0.5| +| RTLMP_AREA_WT| Weight for the area of the current floorplan.| 0.1| +| RTLMP_ARGS| Overrides all other RTL macro placer arguments.| | +| RTLMP_BOUNDARY_WT| Weight for the boundary or how far the hard macro clusters are from boundaries.| 50.0| +| RTLMP_DEAD_SPACE| Specifies the target dead space percentage, which influences the utilization of a cluster.| 0.05| +| RTLMP_FENCE_LX| Defines the lower left X coordinate for the global fence bounding box in microns.| 0.0| +| RTLMP_FENCE_LY| Defines the lower left Y coordinate for the global fence bounding box in microns.| 0.0| +| RTLMP_FENCE_UX| Defines the upper right X coordinate for the global fence bounding box in microns.| 100000000.0| +| RTLMP_FENCE_UY| Defines the upper right Y coordinate for the global fence bounding box in microns.| 100000000.0| +| RTLMP_MAX_INST| Maximum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | +| RTLMP_MAX_LEVEL| Maximum depth of the physical hierarchy tree.| 2| +| RTLMP_MAX_MACRO| Maximum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | +| RTLMP_MIN_AR| Specifies the minimum aspect ratio (height/width).| 0.33| +| RTLMP_MIN_INST| Minimum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | +| RTLMP_MIN_MACRO| Minimum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | +| RTLMP_NOTCH_WT| Weight for the notch, or the existence of dead space that cannot be used for placement and routing.| 10.0| +| RTLMP_OUTLINE_WT| Weight for violating the fixed outline constraint, meaning that all clusters should be placed within the shape of their parent cluster.| 100.0| +| RTLMP_RPT_DIR| Path to the directory where reports are saved.| | +| RTLMP_SIGNATURE_NET_THRESHOLD| Minimum number of connections between two clusters to be identified as connected.| 50| +| RTLMP_WIRELENGTH_WT| Weight for half-perimiter wirelength.| 100.0| +| RULES_JSON| json files with the metrics baseline regression rules. In the ORFS Makefile, this defaults to $DESIGN_DIR/rules-base.json, but ORFS does not mandate the users source directory layout and this can be placed elsewhere when the user sets up an ORFS config.mk or from bazel-orfs.| | +| RUN_LOG_NAME_STEM| Stem of the log file name, the log file will be named `$(LOG_DIR)/$(RUN_LOG_NAME_STEM).log`.| run| +| RUN_SCRIPT| Path to script to run from `make run`, python or tcl script detected by .py or .tcl extension.| | +| SC_LEF| Path to technology standard cell LEF file.| | +| SDC_FILE| The path to design constraint (SDC) file.| | +| SDC_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | +| SEAL_GDS| Seal macro to place around the design.| | +| SETUP_REPAIR_SEQUENCE| Specifies the sequence of moves to do in repair_timing -setup. This should be a string of move keywords separated by commas such as the default when not used: "unbuffer,sizedown,sizeup,swap,buffer,clone,split".| | +| SETUP_SLACK_MARGIN| Specifies a time margin for the slack when fixing setup violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). See HOLD_SLACK_MARGIN for more details.| 0| +| SET_RC_TCL| Metal & Via RC definition file path.| | +| SKIP_CTS_REPAIR_TIMING| Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running.| | +| SKIP_GATE_CLONING| Do not use gate cloning transform to fix timing violations (default: use gate cloning).| | +| SKIP_INCREMENTAL_REPAIR| Skip incremental repair in global route.| 0| +| SKIP_LAST_GASP| Do not use last gasp optimization to fix timing violations (default: use gate last gasp).| | +| SKIP_PIN_SWAP| Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).| | +| SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| | +| SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| | +| SYNTH_ARGS| Optional synthesis variables for yosys.| | +| SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| | +| SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | +| SYNTH_HDL_FRONTEND| Select an alternative language frontend to ingest the design. Available option is "slang". If the variable is empty, design is read with the Yosys read_verilog command.| | +| SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| +| SYNTH_HIER_SEPARATOR| Separator used for the synthesis flatten stage.| .| +| SYNTH_KEEP_MODULES| Mark modules to keep from getting removed in flattening.| | +| SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096| +| SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| 0| +| SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| | +| SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| | +| TAPCELL_TCL| Path to Endcap and Welltie cells file.| | +| TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| | +| TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| | +| TIEHI_CELL_AND_PORT| Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist.| | +| TIELO_CELL_AND_PORT| Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.| | +| TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100| +| USE_FILL| Whether to perform metal density filling.| 0| +| VERILOG_DEFINES| Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`| | +| VERILOG_FILES| The path to the design Verilog/SystemVerilog files providing a description of modules.| | +| VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| | +| VERILOG_TOP_PARAMS| Apply toplevel params (if exist).| | +| YOSYS_FLAGS| Flags to pass to yosys.| -v 3| ## synth variables - [ABC_AREA](#ABC_AREA) diff --git a/flow/scripts/generate-variables-docs.py b/flow/scripts/generate-variables-docs.py index 241edeb245..75a38d6f4f 100755 --- a/flow/scripts/generate-variables-docs.py +++ b/flow/scripts/generate-variables-docs.py @@ -26,8 +26,8 @@ markdown_table += "## Variables in alphabetic order\n\n" table_header = """ -| Variable | Description | Default | Deprecated | -| --- | --- | --- | --- | +| Variable | Description | Default | +| --- | --- | --- | """ table_rows = "" for key in sorted(data): @@ -35,9 +35,9 @@ description = value.get("description", "").replace("\n", " ").strip() table_rows += ( f'| {key}' + + f'{" (deprecated)" if value.get("deprecated", 0) == 1 else ""}' + f"| {description}" + f'| {value.get("default", "")}' - + f'| {"yes" if value.get("deprecated", 0) == 1 else ""}' + "|\n" ) From 038c91c7a0b0bb805d914876f34f041b25511e7f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 27 Jun 2025 07:31:36 +0200 Subject: [PATCH 105/198] variables: move default value into variables.yaml MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit simplifies .tcl and improves documentation Signed-off-by: Øyvind Harboe --- docs/user/FlowVariables.md | 4 ++-- flow/scripts/floorplan.tcl | 12 ++---------- flow/scripts/variables.yaml | 2 ++ 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 7776a48be3..ff4751bea1 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -107,8 +107,8 @@ configuration file. | CELL_PAD_IN_SITES_GLOBAL_PLACEMENT| Cell padding on both sides in site widths to ease routability during global placement.| 0| | | CLKGATE_MAP_FILE| List of cells for gating clock treated as a black box by Yosys.| | | | CORE_AREA| The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | | -| CORE_ASPECT_RATIO| The core aspect ratio (height / width). This value is ignored if `CORE_UTILIZATION` is undefined.| | | -| CORE_MARGIN| The margin between the core area and die area, specified in microns. Allowed values are either one value for all margins or a set of four values, one for each margin. The order of the four values are: `{bottom top left right}`. This variable is ignored if `CORE_UTILIZATION` is undefined.| | | +| CORE_ASPECT_RATIO| The core aspect ratio (height / width). This value is ignored if `CORE_UTILIZATION` is undefined.| 1.0| | +| CORE_MARGIN| The margin between the core area and die area, specified in microns. Allowed values are either one value for all margins or a set of four values, one for each margin. The order of the four values are: `{bottom top left right}`. This variable is ignored if `CORE_UTILIZATION` is undefined.| 1.0| | | CORE_UTILIZATION| The core utilization percentage (0-100).| | | | CORNER| PVT corner library selection. Only available for ASAP7 and GF180 PDKs.| | | | CTS_ARGS| Override `clock_tree_synthesis` arguments.| | | diff --git a/flow/scripts/floorplan.tcl b/flow/scripts/floorplan.tcl index 9fb66c1b92..11c874a35f 100644 --- a/flow/scripts/floorplan.tcl +++ b/flow/scripts/floorplan.tcl @@ -73,17 +73,9 @@ if {$use_floorplan_def} { -site $::env(PLACE_SITE) \ {*}$additional_args } elseif {$use_core_utilization} { - set aspect_ratio 1.0 - if {[env_var_exists_and_non_empty "CORE_ASPECT_RATIO"]} { - set aspect_ratio $::env(CORE_ASPECT_RATIO) - } - set core_margin 1.0 - if {[env_var_exists_and_non_empty "CORE_MARGIN"]} { - set core_margin $::env(CORE_MARGIN) - } initialize_floorplan -utilization $::env(CORE_UTILIZATION) \ - -aspect_ratio $aspect_ratio \ - -core_space $core_margin \ + -aspect_ratio $::env(CORE_ASPECT_RATIO) \ + -core_space $::env(CORE_MARGIN) \ -site $::env(PLACE_SITE) \ {*}$additional_args } else { diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index ef57182459..3dbe7b40d7 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -695,6 +695,7 @@ CORE_ASPECT_RATIO: `CORE_UTILIZATION` is undefined. stages: - floorplan + default: 1.0 tunable: 1 CORE_MARGIN: description: > @@ -705,6 +706,7 @@ CORE_MARGIN: is undefined. stages: - floorplan + default: 1.0 tunable: 1 DIE_AREA: description: > From 99f0c8db708876d3eca1baaa62096feac4e55003 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 27 Jun 2025 07:07:16 +0200 Subject: [PATCH 106/198] variables: add type info for tunable variables MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DRY, AutoTuner type use-cases can use this information, also it is documentation. Signed-off-by: Øyvind Harboe --- flow/scripts/variables.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index ef57182459..8c99653989 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -95,6 +95,7 @@ CORE_UTILIZATION: stages: - floorplan tunable: 1 + type: float CORE_AREA: description: > The core area specified as a list of lower-left and upper-right corners in @@ -361,6 +362,7 @@ CELL_PAD_IN_SITES_GLOBAL_PLACEMENT: - place - floorplan default: 0 + type: float tunable: 1 CELL_PAD_IN_SITES_DETAIL_PLACEMENT: description: > @@ -371,6 +373,7 @@ CELL_PAD_IN_SITES_DETAIL_PLACEMENT: - cts - grt default: 0 + type: float tunable: 1 PLACE_PINS_ARGS: description: | @@ -399,6 +402,7 @@ PLACE_DENSITY_LB_ADDON: - floorplan - place tunable: 1 + type: float REPAIR_PDN_VIA_LAYER: description: | Remove power grid vias which generate DRC violations after detailed routing. @@ -696,6 +700,7 @@ CORE_ASPECT_RATIO: stages: - floorplan tunable: 1 + type: float CORE_MARGIN: description: > The margin between the core area and die area, specified in microns. @@ -706,6 +711,7 @@ CORE_MARGIN: stages: - floorplan tunable: 1 + type: float DIE_AREA: description: > The die area specified as a list of lower-left and upper-right corners in @@ -750,6 +756,7 @@ CTS_CLUSTER_DIAMETER: stages: - cts tunable: 1 + type: float CTS_CLUSTER_SIZE: description: > Maximum number of sinks per cluster. @@ -757,6 +764,7 @@ CTS_CLUSTER_SIZE: stages: - cts tunable: 1 + type: int CTS_LIB_NAME: description: | Name of the Liberty library to use in selecting the clock buffers. From b6aa5cc4e4b81592c0da162b55c2525585450bac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 27 Jun 2025 07:07:16 +0200 Subject: [PATCH 107/198] variables: add type info for tunable variables, review feedback MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DRY, AutoTuner type use-cases can use this information, also it is documentation. Signed-off-by: Øyvind Harboe --- flow/scripts/variables.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 8c99653989..7ae592a79a 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -362,7 +362,7 @@ CELL_PAD_IN_SITES_GLOBAL_PLACEMENT: - place - floorplan default: 0 - type: float + type: int tunable: 1 CELL_PAD_IN_SITES_DETAIL_PLACEMENT: description: > @@ -373,7 +373,7 @@ CELL_PAD_IN_SITES_DETAIL_PLACEMENT: - cts - grt default: 0 - type: float + type: int tunable: 1 PLACE_PINS_ARGS: description: | From e67985edee0955d92c26f3fd4fa8fc49f8528f08 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 27 Jun 2025 18:14:22 +0200 Subject: [PATCH 108/198] docs: update variables MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- docs/user/FlowVariables.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index b70a868afa..023a105555 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -107,8 +107,8 @@ configuration file. | CELL_PAD_IN_SITES_GLOBAL_PLACEMENT| Cell padding on both sides in site widths to ease routability during global placement.| 0| | CLKGATE_MAP_FILE| List of cells for gating clock treated as a black box by Yosys.| | | CORE_AREA| The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | -| CORE_ASPECT_RATIO| The core aspect ratio (height / width). This value is ignored if `CORE_UTILIZATION` is undefined.| | -| CORE_MARGIN| The margin between the core area and die area, specified in microns. Allowed values are either one value for all margins or a set of four values, one for each margin. The order of the four values are: `{bottom top left right}`. This variable is ignored if `CORE_UTILIZATION` is undefined.| | +| CORE_ASPECT_RATIO| The core aspect ratio (height / width). This value is ignored if `CORE_UTILIZATION` is undefined.| 1.0| +| CORE_MARGIN| The margin between the core area and die area, specified in microns. Allowed values are either one value for all margins or a set of four values, one for each margin. The order of the four values are: `{bottom top left right}`. This variable is ignored if `CORE_UTILIZATION` is undefined.| 1.0| | CORE_UTILIZATION| The core utilization percentage (0-100).| | | CORNER| PVT corner library selection. Only available for ASAP7 and GF180 PDKs.| | | CTS_ARGS| Override `clock_tree_synthesis` arguments.| | From 216a93212fe1b03d223b391cdb183227d0a094f0 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Thu, 5 Jun 2025 07:30:18 +0200 Subject: [PATCH 109/198] flow: platforms: ihp-sg13g2: Update sg13g2.map Update sg13g2.map file with latest one from IHP's Open PDK. Signed-off-by: Daniel Schultz --- flow/platforms/ihp-sg13g2/sg13g2.map | 81 +++++++++++----------------- 1 file changed, 30 insertions(+), 51 deletions(-) diff --git a/flow/platforms/ihp-sg13g2/sg13g2.map b/flow/platforms/ihp-sg13g2/sg13g2.map index 2614374122..fbb201c83d 100644 --- a/flow/platforms/ihp-sg13g2/sg13g2.map +++ b/flow/platforms/ihp-sg13g2/sg13g2.map @@ -29,13 +29,10 @@ #EDI Layer Name EDI Layer Type GDS Layer Number GDS Layer Type #============== ============== ================ ============== -Metal1 NET 8 0 -Metal1 SPNET 8 0 -Metal1 PIN 8 2 -Metal1 LEFPIN 8 2 -Metal1 FILL 8 22 -Metal1 LEFOBS 8 4 -Metal1 VIA 8 0 +Metal1 NET,SPNET,PIN,LEFPIN,VIA 8 0 +Metal1 PIN,LEFPIN 8 2 +Metal1 FILL 8 22 +Metal1 LEFOBS 8 4 #NAME Metal1/NET 20 0 #NAME Metal1/SPNET 20 0 @@ -46,13 +43,10 @@ Via1 PIN 19 0 Via1 LEFPIN 19 0 Via1 VIA 19 0 -Metal2 NET 10 0 -Metal2 SPNET 10 0 -Metal2 PIN 10 2 -Metal2 LEFPIN 10 2 -Metal2 FILL 10 22 -Metal2 VIA 10 0 -Metal2 LEFOBS 10 4 +Metal2 NET,SPNET,PIN,LEFPIN,VIA 10 0 +Metal2 PIN,LEFPIN 10 2 +Metal2 FILL 10 22 +Metal2 LEFOBS 10 4 #NAME Metal2/NET 21 0 #NAME Metal2/SPNET 21 0 @@ -64,13 +58,10 @@ Via2 LEFPIN 29 0 Via2 VIA 29 0 -Metal3 NET 30 0 -Metal3 SPNET 30 0 -Metal3 PIN 30 2 -Metal3 LEFPIN 30 2 -Metal3 FILL 30 22 -Metal3 VIA 30 0 -Metal3 LEFOBS 30 4 +Metal3 NET,SPNET,PIN,LEFPIN,VIA 30 0 +Metal3 PIN,LEFPIN 30 2 +Metal3 FILL 30 22 +Metal3 LEFOBS 30 4 #NAME Metal3/NET 22 0 #NAME Metal3/SPNET 22 0 @@ -82,13 +73,10 @@ Via3 LEFPIN 49 0 Via3 VIA 49 0 -Metal4 NET 50 0 -Metal4 SPNET 50 0 -Metal4 PIN 50 2 -Metal4 LEFPIN 50 2 -Metal4 FILL 50 22 -Metal4 VIA 50 0 -Metal4 LEFOBS 50 4 +Metal4 NET,SPNET,PIN,LEFPIN,VIA 50 0 +Metal4 PIN,LEFPIN 50 2 +Metal4 FILL 50 22 +Metal4 LEFOBS 50 4 #NAME Metal4/NET 23 0 #NAME Metal4/SPNET 23 0 @@ -100,13 +88,10 @@ Via4 LEFPIN 66 0 Via4 VIA 66 0 -Metal5 NET 67 0 -Metal5 SPNET 67 0 -Metal5 PIN 67 2 -Metal5 LEFPIN 67 2 -Metal5 FILL 67 22 -Metal5 VIA 67 0 -Metal5 LEFOBS 67 4 +Metal5 NET,SPNET,PIN,LEFPIN,VIA 67 0 +Metal5 PIN,LEFPIN 67 2 +Metal5 FILL 67 22 +Metal5 LEFOBS 67 4 #NAME Metal5/NET 70 0 #NAME Metal5/SPNET 70 0 @@ -117,13 +102,10 @@ TopVia1 PIN 125 0 TopVia1 LEFPIN 125 0 TopVia1 VIA 125 0 -TopMetal1 NET 126 0 -TopMetal1 SPNET 126 0 -TopMetal1 PIN 126 2 -TopMetal1 LEFPIN 126 2 -TopMetal1 FILL 126 22 -TopMetal1 VIA 126 0 -TopMetal1 LEFOBS 126 4 +TopMetal1 NET,SPNET,PIN,LEFPIN,VIA 126 0 +TopMetal1 PIN,LEFPIN 126 2 +TopMetal1 FILL 126 22 +TopMetal1 LEFOBS 126 4 #NAME TopMetal1/NET 130 0 #NAME TopMetal1/SPNET 130 0 @@ -134,13 +116,10 @@ TopVia2 PIN 133 0 TopVia2 LEFPIN 133 0 TopVia2 VIA 133 0 -TopMetal2 NET 134 0 -TopMetal2 SPNET 134 0 -TopMetal2 PIN 134 2 -TopMetal2 LEFPIN 134 2 -TopMetal2 FILL 134 22 -TopMetal2 VIA 134 0 -TopMetal2 LEFOBS 135 4 +TopMetal2 NET,SPNET,PIN,LEFPIN,VIA 134 0 +TopMetal2 PIN,LEFPIN 134 2 +TopMetal2 FILL 134 22 +TopMetal2 LEFOBS 134 4 #NAME TopMetal2/NET 137 0 #NAME TopMetal2/SPNET 137 0 @@ -149,6 +128,6 @@ NAME TopMetal2/PIN 134 25 NAME COMP 63 0 -COMP ALL 235 0 +COMP ALL 189 0 -DIEAREA ALL 235 4 +DIEAREA ALL 189 4 From b8a73f82c1a584788433698f24f0455af926a1c9 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Tue, 27 May 2025 21:58:57 +0200 Subject: [PATCH 110/198] flow: platforms: ihp-sg13g2: Update lib file handling Call the variable ADDITIONAL_TYP_LIBS instead of ADDITIONAL_LIBS and assign correct values to it. Also provide TYP_LIB_FILES next to LIB_FILES with the same content. Signed-off-by: Daniel Schultz --- flow/platforms/ihp-sg13g2/config.mk | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/flow/platforms/ihp-sg13g2/config.mk b/flow/platforms/ihp-sg13g2/config.mk index a45ed4a9c1..caea89b76c 100644 --- a/flow/platforms/ihp-sg13g2/config.mk +++ b/flow/platforms/ihp-sg13g2/config.mk @@ -11,11 +11,11 @@ ifneq ($(FOOTPRINT_TCL),) ifeq ($(LOAD_ADDITIONAL_FILES),1) export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/sg13g2_io.lef \ $(PLATFORM_DIR)/lef/bondpad_70x70.lef - export ADDITIONAL_SLOW_LIBS = $(ADDITIONAL_LIBS) $(PLATFORM_DIR)/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib - export ADDITIONAL_FAST_LIBS = $(ADDITIONAL_LIBS) $(PLATFORM_DIR)/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib - export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib + export ADDITIONAL_SLOW_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib + export ADDITIONAL_FAST_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib + export ADDITIONAL_TYP_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib export ADDITIONAL_GDS += $(PLATFORM_DIR)/gds/sg13g2_io.gds \ - $(PLATFORM_DIR)/gds/bondpad_70x70.gds + $(PLATFORM_DIR)/gds/bondpad_70x70.gds endif endif export TECH_LEF ?= $(PLATFORM_DIR)/lef/sg13g2_tech.lef @@ -25,8 +25,9 @@ export SLOW_LIB_FILES ?= $(PLATFORM_DIR)/lib/sg13g2_stdcell_slow_1p08V_125C.lib $(ADDITIONAL_SLOW_LIBS) export FAST_LIB_FILES ?= $(PLATFORM_DIR)/lib/sg13g2_stdcell_fast_1p32V_m40C.lib \ $(ADDITIONAL_FAST_LIBS) -export LIB_FILES ?= $(PLATFORM_DIR)/lib/sg13g2_stdcell_typ_1p20V_25C.lib \ - $(ADDITIONAL_LIBS) +export TYP_LIB_FILES ?= $(PLATFORM_DIR)/lib/sg13g2_stdcell_typ_1p20V_25C.lib \ + $(ADDITIONAL_TYP_LIBS) +export LIB_FILES ?= $(TYP_LIB_FILES) export GDS_FILES ?= $(PLATFORM_DIR)/gds/sg13g2_stdcell.gds \ $(ADDITIONAL_GDS) From eedf3880d922e8c89e209c58164a334e31f8cb19 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Fri, 27 Jun 2025 15:13:50 +0200 Subject: [PATCH 111/198] flow: designs: ihp-sg13g2: Update I2C GPIO Expander Move the I2cDeviceCtrl into a macro to have one chip design with an embedded macro generated by OR. Signed-off-by: Daniel Schultz --- .../i2c-gpio-expander/I2cDeviceCtrl/config.mk | 20 + .../I2cDeviceCtrl/constraint.sdc | 22 + .../i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl | 34 ++ .../ihp-sg13g2/i2c-gpio-expander/config.mk | 4 +- .../i2c-gpio-expander/metadata-base-ok.json | 399 ++++++++++++++++++ .../ihp-sg13g2/i2c-gpio-expander/pad.tcl | 1 + .../ihp-sg13g2/i2c-gpio-expander/pdn.tcl | 54 +-- .../i2c-gpio-expander/rules-base.json | 16 +- 8 files changed, 502 insertions(+), 48 deletions(-) create mode 100644 flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/config.mk create mode 100644 flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/constraint.sdc create mode 100644 flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl create mode 100644 flow/designs/ihp-sg13g2/i2c-gpio-expander/metadata-base-ok.json diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/config.mk b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/config.mk new file mode 100644 index 0000000000..68feb648f2 --- /dev/null +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/config.mk @@ -0,0 +1,20 @@ +export DESIGN_NAME = I2cDeviceCtrl +export TOP_DESIGN_NICKNAME = i2c-gpio-expander +export DESIGN_NICKNAME = ${TOP_DESIGN_NICKNAME}_${DESIGN_NAME} +export PLATFORM = ihp-sg13g2 + +export VERILOG_FILES = $(DESIGN_HOME)/$(PLATFORM)/${TOP_DESIGN_NICKNAME}/I2cGpioExpander.v \ + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(TOP_DESIGN_NICKNAME)/${DESIGN_NAME}/constraint.sdc + +export DIE_AREA = 0.0 0.0 147.84 147.42 +export CORE_AREA = 18.72 18.9 128.64 128.52 + +export MAX_ROUTING_LAYER = TopMetal2 + +export TNS_END_PERCENT = 100 +export PLACE_DENSITY = 0.75 + +export CORNERS = slow typ fast + +export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(TOP_DESIGN_NICKNAME)/${DESIGN_NAME}/pdn.tcl diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/constraint.sdc b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/constraint.sdc new file mode 100644 index 0000000000..95787b8df0 --- /dev/null +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/constraint.sdc @@ -0,0 +1,22 @@ +current_design I2cDeviceCtrl/I2cDeviceCtrl +set_units -time ns -resistance kOhm -capacitance pF -voltage V -current uA +set_max_fanout 8 [current_design] +set_max_capacitance 0.5 [current_design] +set_max_transition 3 [current_design] +set_max_area 0 + +create_clock [get_ports clock] -name clock -period 20.0 -waveform {0 10.0} +set_ideal_network [get_ports clock] +set_clock_uncertainty 0.15 [get_clocks clock] +set_clock_transition 0.25 [get_clocks clock] +set input_delay_value_clock 4.0 +set output_delay_value_clock 4.0 +set clk_indx_clock [lsearch [all_inputs] [get_port clock]] +set all_inputs_wo_clk_rst_clock [lreplace [all_inputs] $clk_indx_clock $clk_indx_clock ""] +set_input_delay $input_delay_value_clock -clock [get_clocks clock] $all_inputs_wo_clk_rst_clock +set_output_delay $output_delay_value_clock -clock [get_clocks clock] [all_outputs] + +set_load -pin_load 5 [all_inputs] +set_load -pin_load 5 [all_outputs] +set_timing_derate -early 0.95 +set_timing_derate -late 1.05 diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl new file mode 100644 index 0000000000..fd105772b5 --- /dev/null +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl @@ -0,0 +1,34 @@ +# standard cells +add_global_connection -net {VDD} -pin_pattern {^VDD$} -power +add_global_connection -net {VDD} -pin_pattern {^VDDPE$} +add_global_connection -net {VDD} -pin_pattern {^VDDCE$} +add_global_connection -net {VSS} -pin_pattern {^VSS$} -ground +add_global_connection -net {VSS} -pin_pattern {^VSSE$} + +# macros +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VDD!} -power +add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VSS!} -ground +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power +add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground + +# padframe core power pins +add_global_connection -net {VDD} -pin_pattern {^vdd$} -power +add_global_connection -net {VSS} -pin_pattern {^vss$} -ground + +# padframe io power pins +add_global_connection -net {IOVDD} -pin_pattern {^iovdd$} -power +add_global_connection -net {IOVSS} -pin_pattern {^iovss$} -ground + +global_connect + +# core voltage domain +set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} + +# stdcell grid +define_pdn_grid -name {grid} -voltage_domains {CORE} +add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins -extend_to_core_ring +add_pdn_ring -grid {grid} -layers {Metal3 Metal4} -widths {3.0} -spacings {2.0} -core_offsets {4.5} -connect_to_pads +add_pdn_stripe -grid {grid} -layer {Metal3} -width {1.840} -pitch {75.6} -offset {37.8} -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {Metal4} -width {1.840} -pitch {75.6} -offset {37.8} -extend_to_core_ring +add_pdn_connect -grid {grid} -layers {Metal1 Metal3} +add_pdn_connect -grid {grid} -layers {Metal3 Metal4} diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk b/flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk index c6c45aba0f..f46620b481 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk @@ -9,7 +9,7 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export SEAL_GDS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sealring.gds.gz export DIE_AREA = 0.0 0.0 1050.0 1050.0 -export CORE_AREA = 425.28 427.16 631.2 630.24 +export CORE_AREA = 351.36 351.54 699.84 699.3 export MAX_ROUTING_LAYER = TopMetal2 @@ -20,3 +20,5 @@ export CORNERS = slow fast export FOOTPRINT_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/pad.tcl export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/pdn.tcl + +export BLOCKS = I2cDeviceCtrl diff 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"run__flow__platform__time_units": "1ns", + "run__flow__platform__voltage_units": "1v", + "run__flow__platform_commit": "2b92477257a655e1c3d56c83372e3ea6262fc7e1", + "run__flow__scripts_commit": "2b92477257a655e1c3d56c83372e3ea6262fc7e1", + "run__flow__uuid": "a55e4f22-7f3b-48eb-84a6-b10f6fde9a2a", + "run__flow__variant": "base", + "synth__cpu__total": 0.88, + "synth__design__instance__area__stdcell": 253699.051, + "synth__design__instance__count__stdcell": 702.0, + "synth__mem__peak": 26056.0, + "synth__runtime__total": "0:00.90", + "total_time": "0:00:18.900000" +} \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl index 5ed1a981fa..0ec62dec93 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl @@ -2,6 +2,7 @@ set IO_LENGTH 180 set IO_WIDTH 80 set BONDPAD_SIZE 70 set SEALRING_OFFSET 70 +set IO_OFFSET [expr {$BONDPAD_SIZE + $SEALRING_OFFSET}] proc calc_horizontal_pad_location {index total} { global IO_LENGTH diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl index 0534bb5bde..8e205d1c13 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl @@ -1,12 +1,16 @@ - -# stdcell power pins +# standard cells add_global_connection -net {VDD} -pin_pattern {^VDD$} -power add_global_connection -net {VDD} -pin_pattern {^VDDPE$} add_global_connection -net {VDD} -pin_pattern {^VDDCE$} - add_global_connection -net {VSS} -pin_pattern {^VSS$} -ground add_global_connection -net {VSS} -pin_pattern {^VSSE$} +# macros +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VDD!} -power +add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VSS!} -ground +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power +add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground + # padframe core power pins add_global_connection -net {VDD} -pin_pattern {^vdd$} -power add_global_connection -net {VSS} -pin_pattern {^vss$} -ground @@ -22,43 +26,15 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} # stdcell grid define_pdn_grid -name {grid} -voltage_domains {CORE} -add_pdn_ring \ - -grid {grid} \ - -layers {Metal5 TopMetal1} \ - -widths {30.0} \ - -spacings {5.0} \ - -core_offsets {4.5} \ - -connect_to_pads -add_pdn_stripe \ - -grid {grid} \ - -layer {Metal1} \ - -width {0.44} \ - -pitch {7.56} \ - -offset {0} \ - -followpins \ - -extend_to_core_ring -add_pdn_stripe \ - -grid {grid} \ - -layer {Metal5} \ - -width {2.200} \ - -pitch {75.6} \ - -offset {13.600} \ - -extend_to_core_ring -add_pdn_stripe \ - -grid {grid} \ - -layer {TopMetal1} \ - -width {2.200} \ - -pitch {75.6} \ - -offset {13.600} \ - -extend_to_core_ring -add_pdn_stripe \ - -grid {grid} \ - -layer {TopMetal2} \ - -width {2.200} \ - -pitch {75.6} \ - -offset {13.600} \ - -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins -extend_to_core_ring +add_pdn_ring -grid {grid} -layers {Metal5 TopMetal1} -widths {8.0} -spacings {5.0} -core_offsets {4.5} -connect_to_pads +add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {37.8} -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {2.200} -pitch {75.6} -offset {37.8} -extend_to_core_ring add_pdn_connect -grid {grid} -layers {Metal1 Metal5} add_pdn_connect -grid {grid} -layers {Metal5 TopMetal1} add_pdn_connect -grid {grid} -layers {Metal5 TopMetal2} add_pdn_connect -grid {grid} -layers {TopMetal1 TopMetal2} + +define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -cells {I2cDeviceCtrl} -grid_over_boundary +add_pdn_connect -grid {CORE_macro_grid_1} -layers {Metal3 TopMetal1} +add_pdn_connect -grid {CORE_macro_grid_1} -layers {Metal4 TopMetal1} diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json index 3116dcc040..0d62bb9a3a 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 23061, + "value": 39158, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 1539, + "value": 983, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 134, + "value": 86, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 134, + "value": 86, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 0, + "value": 156, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 47873, + "value": 42588, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -52,11 +52,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 44275, + "value": 136013, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 67, + "value": 43, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { From db31749199f71f6f443eba2701fdccc7a38390ec Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Sat, 28 Jun 2025 00:28:51 +0000 Subject: [PATCH 112/198] Allow one lonely via violation in gf12/coyote (needs rule support) | Metric | Old | New | Type | | ------ | --- | --- | ---- | | detailedroute__route__wirelength | 5770855 | 5678019 | Tighten | | detailedroute__route__drc_errors | 0 | 1 | Failing | | finish__timing__drv__hold_violation_count | 100 | 266 | Failing | Signed-off-by: Matt Liberty --- flow/designs/gf12/coyote/rules-base.json | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/flow/designs/gf12/coyote/rules-base.json b/flow/designs/gf12/coyote/rules-base.json index 6c4fc6394a..8359e8a556 100644 --- a/flow/designs/gf12/coyote/rules-base.json +++ b/flow/designs/gf12/coyote/rules-base.json @@ -32,11 +32,11 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 5770855, + "value": 5678019, "compare": "<=" }, "detailedroute__route__drc_errors": { - "value": 0, + "value": 1, "compare": "<=" }, "detailedroute__antenna__violating__nets": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 100, + "value": 266, "compare": "<=" }, "finish__timing__wns_percent_delay": { From 067518792476209933d6eaab1be5e3b0d65c1590 Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Sat, 28 Jun 2025 14:42:23 +0000 Subject: [PATCH 113/198] bump tensorboard version - tensorboard < 2.16.2 used some old protobuf functions that were dropped in current protobuf, so a bump in version is needed. Signed-off-by: Jack Luar --- tools/AutoTuner/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/AutoTuner/requirements.txt b/tools/AutoTuner/requirements.txt index 42a0c73e91..d4a4dbe5ff 100644 --- a/tools/AutoTuner/requirements.txt +++ b/tools/AutoTuner/requirements.txt @@ -5,7 +5,7 @@ optuna==3.6.0 pandas>=2.0,<=2.2.1 bayesian-optimization==1.4.0 colorama==0.4.6 -tensorboard>=2.14.0,<=2.16.2 +tensorboard>=2.17.0 protobuf>=5.26.1 SQLAlchemy==1.4.17 urllib3>=1.26.17 From a4fe8af6b75f627deb9b23d788ce0d43dd344bb6 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Sun, 29 Jun 2025 00:44:40 +0000 Subject: [PATCH 114/198] update submodules Signed-off-by: Matt Liberty --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index c79c8317e0..a2641238b7 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit c79c8317e05ecbf45eba5096a74cb421ab97b7ae +Subproject commit a2641238b709488082c332d9cc0ecd5a8af01cb1 From 69aa41bbbffa3fc36ddb77a4489fc0f70a26664d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Sun, 29 Jun 2025 10:33:50 +0200 Subject: [PATCH 115/198] dependencies: missed a spot when adding PYTHON_EXE dependency injection MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/scripts/synth.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl index 7b67ead8ea..a7fb8c5a60 100644 --- a/flow/scripts/synth.tcl +++ b/flow/scripts/synth.tcl @@ -52,7 +52,7 @@ if {![env_var_equals SYNTH_HIERARCHICAL 1]} { json -o $::env(RESULTS_DIR)/mem.json # Run report and check here so as to fail early if this synthesis run is doomed -exec -- python3 $::env(SCRIPTS_DIR)/mem_dump.py --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json +exec -- $::env(PYTHON_EXE) $::env(SCRIPTS_DIR)/mem_dump.py --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json if {![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS]} { synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_full_args From 8ce5406a8a251e6205b84952c8beb2efcf716ec3 Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Sun, 29 Jun 2025 12:04:04 +0000 Subject: [PATCH 116/198] add tclint CI scaffold Signed-off-by: Jack Luar --- .github/workflows/github-actions-lint-tcl.yml | 27 + flow/designs/asap7/aes-block/constraint.sdc | 4 +- flow/designs/asap7/aes-mbff/constraint.sdc | 6 +- flow/designs/asap7/aes/constraint.sdc | 6 +- flow/designs/asap7/aes_lvt/constraint.sdc | 6 +- flow/designs/asap7/ethmac/constraint.sdc | 12 +- flow/designs/asap7/ethmac_lvt/constraint.sdc | 12 +- flow/designs/asap7/gcd/constraint.sdc | 8 +- flow/designs/asap7/ibex/constraint.sdc | 4 +- .../asap7/ibex/constraint_pos_slack.sdc | 4 +- .../designs/asap7/jpeg/jpeg_encoder15_7nm.sdc | 4 +- flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc | 204 +- .../asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc | 4 +- flow/designs/asap7/mock-alu/constraints.sdc | 10 +- flow/designs/asap7/mock-array/Element/io.tcl | 77 +- flow/designs/asap7/mock-array/io.tcl | 43 +- .../asap7/mock-array/macro-placement.tcl | 14 +- flow/designs/asap7/mock-array/power.tcl | 34 +- flow/designs/asap7/mock-cpu/constraint.sdc | 2 +- flow/designs/asap7/mock-cpu/io.tcl | 2 +- flow/designs/asap7/riscv32i/constraint.sdc | 4 +- .../asap7/swerv_wrapper/constraint.sdc | 6 +- flow/designs/asap7/uart/constraint.sdc | 6 +- flow/designs/gf12/aes/constraint.sdc | 8 +- flow/designs/gf12/ariane/constraint.sdc | 990 +- flow/designs/gf12/ariane/constraint_hier.sdc | 990 +- flow/designs/gf12/ariane133/ariane.sdc | 2 +- flow/designs/gf12/bp_single/fastroute.tcl | 3 +- flow/designs/gf12/ca53/fastroute.tcl | 3 +- flow/designs/gf12/coyote/constraint.sdc | 8 +- flow/designs/gf12/coyote/constraint_hier.sdc | 8 +- flow/designs/gf12/coyote/io.tcl | 2 +- flow/designs/gf12/gcd/constraint.sdc | 8 +- flow/designs/gf12/ibex/constraint.sdc | 8 +- flow/designs/gf12/jpeg/constraint.sdc | 8 +- .../designs/gf12/swerv_wrapper/constraint.sdc | 12 +- flow/designs/gf12/tinyRocket/constraint.sdc | 8 +- flow/designs/gf180/aes/constraint.sdc | 7 +- flow/designs/gf180/ibex/constraint.sdc | 4 +- flow/designs/gf180/jpeg/constraint.sdc | 4 +- flow/designs/gf180/jpeg/io.tcl | 2 +- flow/designs/gf180/riscv32i/constraint.sdc | 6 +- .../uart-blocks/BLOCKS_grid_strategy.tcl | 2 +- flow/designs/gf180/uart-blocks/constraint.sdc | 4 +- flow/designs/gf180/uart-blocks/tapcell.tcl | 15 +- .../gf180/uart-blocks/uart_rx/constraint.sdc | 6 +- .../designs/gf180/uart-blocks/uart_rx/pdn.tcl | 2 +- flow/designs/ihp-sg13g2/aes/constraint.sdc | 7 +- flow/designs/ihp-sg13g2/gcd/constraint.sdc | 4 +- .../i2c-gpio-expander/constraint.sdc | 8 +- .../ihp-sg13g2/i2c-gpio-expander/pad.tcl | 52 +- flow/designs/ihp-sg13g2/ibex/constraint.sdc | 4 +- .../ihp-sg13g2/ibex/constraint_doe.sdc | 6 +- flow/designs/ihp-sg13g2/jpeg/constraint.sdc | 6 +- .../ihp-sg13g2/riscv32i/constraint.sdc | 10 +- flow/designs/ihp-sg13g2/spi/constraint.sdc | 4 +- flow/designs/nangate45/aes/constraint.sdc | 6 +- .../nangate45/ariane136/constraint.sdc | 992 +- .../nangate45/black_parrot/constraint.sdc | 4790 +++--- .../nangate45/bp_be_top/constraint.sdc | 12115 ++++++++-------- flow/designs/nangate45/bp_be_top/io.tcl | 2 +- .../nangate45/bp_fe_top/constraint.sdc | 1 - flow/designs/nangate45/bp_fe_top/io.tcl | 2 +- .../nangate45/bp_multi_top/constraint.sdc | 5811 ++++---- flow/designs/nangate45/bp_multi_top/io.tcl | 2 +- flow/designs/nangate45/bp_quad/bsg_chip.sdc | 256 +- flow/designs/nangate45/bp_quad/io.tcl | 2 +- flow/designs/nangate45/gcd/constraint.sdc | 6 +- flow/designs/nangate45/ibex/constraint.sdc | 4 +- flow/designs/nangate45/jpeg/constraint.sdc | 4 +- .../nangate45/mempool_group/mempool_group.sdc | 9 +- flow/designs/nangate45/swerv/constraint.sdc | 4 +- .../nangate45/swerv_wrapper/constraint.sdc | 4 +- flow/designs/sky130hd/aes/constraint.sdc | 6 +- flow/designs/sky130hd/aes/fastroute.tcl | 1 - .../designs/sky130hd/chameleon/constraint.sdc | 8 +- flow/designs/sky130hd/gcd/constraint.sdc | 4 +- flow/designs/sky130hd/ibex/constraint.sdc | 4 +- flow/designs/sky130hd/ibex/constraint_doe.sdc | 6 +- flow/designs/sky130hd/ibex/fastroute.tcl | 1 - flow/designs/sky130hd/jpeg/constraint.sdc | 4 +- flow/designs/sky130hd/jpeg/fastroute.tcl | 1 - .../designs/sky130hd/microwatt/constraint.sdc | 4 +- flow/designs/sky130hd/microwatt/fastroute.tcl | 1 - flow/designs/sky130hd/riscv32i/constraint.sdc | 12 +- flow/designs/sky130hs/aes/constraint.sdc | 4 +- flow/designs/sky130hs/gcd/constraint.sdc | 6 +- flow/designs/sky130hs/ibex/constraint.sdc | 4 +- flow/designs/sky130hs/jpeg/constraint.sdc | 4 +- flow/designs/sky130hs/riscv32i/constraint.sdc | 10 +- flow/designs/src/mock-array/util.tcl | 88 +- flow/platforms/asap7/constraints.sdc | 8 +- flow/platforms/asap7/openRoad/make_tracks.tcl | 30 +- .../openRoad/pdn/BLOCKS_grid_strategy.tcl | 8 +- .../openRoad/pdn/BLOCK_grid_strategy.tcl | 9 +- flow/platforms/asap7/openRoad/tapcell.tcl | 2 +- .../asap7/openlane/asap7sc7p5t/config.tcl | 8 +- flow/platforms/asap7/openlane/config.tcl | 4 +- flow/platforms/gf180/fastroute.tcl | 1 - flow/platforms/gf180/openROAD/tapcell.tcl | 10 +- flow/platforms/gf180/setRC.tcl | 36 +- flow/platforms/ihp-sg13g2/fastroute.tcl | 1 - flow/platforms/ihp-sg13g2/make_tracks.tcl | 12 +- flow/platforms/ihp-sg13g2/pdn.tcl | 6 +- flow/platforms/ihp-sg13g2/setRC.tcl | 8 +- flow/platforms/nangate45/fakeram.tcl | 5 +- flow/platforms/nangate45/make_tracks.tcl | 16 +- flow/platforms/nangate45/setRC.tcl | 2 +- flow/platforms/nangate45/tapcell.tcl | 1 - flow/platforms/sky130hd/fastroute.tcl | 1 - flow/scripts/add_routing_blk.tcl | 20 +- flow/scripts/cts.tcl | 30 +- flow/scripts/deleteNonClkNets.tcl | 14 +- flow/scripts/deletePowerNets.tcl | 4 +- flow/scripts/deleteRoutingObstructions.tcl | 2 +- flow/scripts/density_fill.tcl | 2 +- flow/scripts/detail_place.tcl | 22 +- flow/scripts/detail_route.tcl | 16 +- flow/scripts/fillcell.tcl | 2 +- flow/scripts/final_report.tcl | 26 +- flow/scripts/floorplan.tcl | 72 +- flow/scripts/generate_abstract.tcl | 12 +- flow/scripts/global_place.tcl | 12 +- flow/scripts/global_place_skip_io.tcl | 6 +- flow/scripts/global_route.tcl | 26 +- flow/scripts/io_placement.tcl | 8 +- flow/scripts/klayout.tcl | 26 +- flow/scripts/load.tcl | 140 +- flow/scripts/macro_place_util.tcl | 20 +- flow/scripts/noop.tcl | 1 + flow/scripts/open.tcl | 47 +- flow/scripts/pdn.tcl | 12 +- flow/scripts/placement_blockages.tcl | 11 +- flow/scripts/read_liberty.tcl | 2 +- flow/scripts/read_macro_placement.tcl | 8 +- flow/scripts/report_metrics.tcl | 104 +- flow/scripts/save_images.tcl | 18 +- flow/scripts/synth.tcl | 26 +- flow/scripts/synth_preamble.tcl | 58 +- flow/scripts/synth_wrap_operators.tcl | 4 +- flow/scripts/tapcell.tcl | 6 +- flow/scripts/util.tcl | 70 +- flow/scripts/view_cells.tcl | 32 +- flow/scripts/write_ref_sdc.tcl | 2 +- flow/tutorials/scripts/drt/drc_fix.tcl | 12 +- flow/tutorials/scripts/drt/drc_issue.tcl | 12 +- flow/tutorials/scripts/drt/helpers.tcl | 6 +- flow/tutorials/scripts/gui/load_lef.tcl | 8 +- flow/util/cell-veneer/lefdef.tcl | 1718 +-- flow/util/cell-veneer/pkgIndex.tcl | 3 +- flow/util/cell-veneer/wrap.tcl | 4 +- flow/util/cell-veneer/wrap_stdcells.tcl | 1142 +- flow/util/write_net_rc.tcl | 18 +- tclint.toml | 23 + 154 files changed, 15431 insertions(+), 15432 deletions(-) create mode 100644 .github/workflows/github-actions-lint-tcl.yml create mode 100644 tclint.toml diff --git a/.github/workflows/github-actions-lint-tcl.yml b/.github/workflows/github-actions-lint-tcl.yml new file mode 100644 index 0000000000..5e52158e62 --- /dev/null +++ b/.github/workflows/github-actions-lint-tcl.yml @@ -0,0 +1,27 @@ +name: Lint Tcl code + +on: + push: + branches: + - master + pull_request: + branches: + - master + +jobs: + build: + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} + steps: + - name: Checkout repository + uses: actions/checkout@v4 + + - name: Install Dependencies + run: | + python3 -m pip install -U --user tclint==0.4.2 + + - name: Lint + run: | + tclfmt --version + tclfmt --in-place . + git diff --exit-code + tclint --no-check-style . diff --git a/flow/designs/asap7/aes-block/constraint.sdc b/flow/designs/asap7/aes-block/constraint.sdc index 15c31e02f8..8256fd752b 100644 --- a/flow/designs/asap7/aes-block/constraint.sdc +++ b/flow/designs/asap7/aes-block/constraint.sdc @@ -1,4 +1,4 @@ -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 475 set clk_io_pct 0.2 @@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/aes-mbff/constraint.sdc b/flow/designs/asap7/aes-mbff/constraint.sdc index e45d9100bd..f5bce962e5 100644 --- a/flow/designs/asap7/aes-mbff/constraint.sdc +++ b/flow/designs/asap7/aes-mbff/constraint.sdc @@ -1,6 +1,6 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 400 +set clk_period 400 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/aes/constraint.sdc b/flow/designs/asap7/aes/constraint.sdc index e45d9100bd..f5bce962e5 100644 --- a/flow/designs/asap7/aes/constraint.sdc +++ b/flow/designs/asap7/aes/constraint.sdc @@ -1,6 +1,6 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 400 +set clk_period 400 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/aes_lvt/constraint.sdc b/flow/designs/asap7/aes_lvt/constraint.sdc index e45d9100bd..f5bce962e5 100644 --- a/flow/designs/asap7/aes_lvt/constraint.sdc +++ b/flow/designs/asap7/aes_lvt/constraint.sdc @@ -1,6 +1,6 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 400 +set clk_period 400 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/ethmac/constraint.sdc b/flow/designs/asap7/ethmac/constraint.sdc index 71e846bd4a..43759e0718 100644 --- a/flow/designs/asap7/ethmac/constraint.sdc +++ b/flow/designs/asap7/ethmac/constraint.sdc @@ -4,7 +4,7 @@ set clk_io_pct 0.2 set clk_port [get_ports $top_clk_name] create_clock -name $top_clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs] set tx_clk_name mtx_clk_pad_i @@ -12,7 +12,7 @@ set tx_clk_port [get_ports $tx_clk_name] set tx_clk_period 300 create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port] -set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs +set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs] set rx_clk_name mrx_clk_pad_i @@ -20,12 +20,12 @@ set rx_clk_port [get_ports $rx_clk_name] set rx_clk_period 300 create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port] -set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs +set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs] set_clock_groups -name core_clock -logically_exclusive \ - -group [get_clocks $top_clk_name] \ - -group [get_clocks $tx_clk_name] \ - -group [get_clocks $rx_clk_name] + -group [get_clocks $top_clk_name] \ + -group [get_clocks $tx_clk_name] \ + -group [get_clocks $rx_clk_name] set_max_fanout 10 [current_design] diff --git a/flow/designs/asap7/ethmac_lvt/constraint.sdc b/flow/designs/asap7/ethmac_lvt/constraint.sdc index c9a876f18f..6d59823cb6 100644 --- a/flow/designs/asap7/ethmac_lvt/constraint.sdc +++ b/flow/designs/asap7/ethmac_lvt/constraint.sdc @@ -4,7 +4,7 @@ set clk_io_pct 0.2 set clk_port [get_ports $top_clk_name] create_clock -name $top_clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs] set tx_clk_name mtx_clk_pad_i @@ -12,7 +12,7 @@ set tx_clk_port [get_ports $tx_clk_name] set tx_clk_period 300 create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port] -set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs +set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs] set rx_clk_name mrx_clk_pad_i @@ -20,10 +20,10 @@ set rx_clk_port [get_ports $rx_clk_name] set rx_clk_period 300 create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port] -set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs +set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs] set_clock_groups -name core_clock -logically_exclusive \ - -group [get_clocks $top_clk_name] \ - -group [get_clocks $tx_clk_name] \ - -group [get_clocks $rx_clk_name] + -group [get_clocks $top_clk_name] \ + -group [get_clocks $tx_clk_name] \ + -group [get_clocks $rx_clk_name] diff --git a/flow/designs/asap7/gcd/constraint.sdc b/flow/designs/asap7/gcd/constraint.sdc index b4a21ce6a4..dc5d070adf 100644 --- a/flow/designs/asap7/gcd/constraint.sdc +++ b/flow/designs/asap7/gcd/constraint.sdc @@ -1,15 +1,15 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 310 +set clk_period 310 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/ibex/constraint.sdc b/flow/designs/asap7/ibex/constraint.sdc index a58c555b69..956a60e40e 100644 --- a/flow/designs/asap7/ibex/constraint.sdc +++ b/flow/designs/asap7/ibex/constraint.sdc @@ -1,4 +1,4 @@ -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 1260 set clk_io_pct 0.2 @@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/ibex/constraint_pos_slack.sdc b/flow/designs/asap7/ibex/constraint_pos_slack.sdc index 7d9d39b7c1..0627af5b19 100644 --- a/flow/designs/asap7/ibex/constraint_pos_slack.sdc +++ b/flow/designs/asap7/ibex/constraint_pos_slack.sdc @@ -1,4 +1,4 @@ -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 1468 set clk_io_pct 0.2 @@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc index 7f2469a084..3800daaf8b 100644 --- a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc +++ b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc @@ -1,6 +1,6 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 900 set clk_io_pct 0.2 @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc b/flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc index d37e20a0ee..46a528441e 100644 --- a/flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc +++ b/flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc @@ -7,7 +7,7 @@ set_units -time 1.0ps current_design jpeg_encoder create_clock -name "tclk" -period 1000.0 -waveform {0.0 500.0} [get_ports clk] -set_propagated_clock [ all_clocks ] +set_propagated_clock [all_clocks] set_load -pin_load -max 3.0 [get_ports {qnt_cnt[5]}] set_load -pin_load -max 3.0 [get_ports {qnt_cnt[4]}] set_load -pin_load -max 3.0 [get_ports {qnt_cnt[3]}] @@ -36,113 +36,113 @@ set_load -pin_load -max 3.0 [get_ports {amp[1]}] set_load -pin_load -max 3.0 [get_ports {amp[0]}] set_load -pin_load -max 3.0 [get_ports douten] set_max_delay 500 -from [list \ - [get_clocks tclk] ] -to [list \ - [get_ports douten] \ - [get_ports {amp[0]}] \ - [get_ports {amp[1]}] \ - [get_ports {amp[2]}] \ - [get_ports {amp[3]}] \ - [get_ports {amp[4]}] \ - [get_ports {amp[5]}] \ - [get_ports {amp[6]}] \ - [get_ports {amp[7]}] \ - [get_ports {amp[8]}] \ - [get_ports {amp[9]}] \ - [get_ports {amp[10]}] \ - [get_ports {amp[11]}] \ - [get_ports {rlen[0]}] \ - [get_ports {rlen[1]}] \ - [get_ports {rlen[2]}] \ - [get_ports {rlen[3]}] \ - [get_ports {size[0]}] \ - [get_ports {size[1]}] \ - [get_ports {size[2]}] \ - [get_ports {size[3]}] \ - [get_ports {qnt_cnt[0]}] \ - [get_ports {qnt_cnt[1]}] \ - [get_ports {qnt_cnt[2]}] \ - [get_ports {qnt_cnt[3]}] \ - [get_ports {qnt_cnt[4]}] \ - [get_ports {qnt_cnt[5]}] ] + [get_clocks tclk]] -to [list \ + [get_ports douten] \ + [get_ports {amp[0]}] \ + [get_ports {amp[1]}] \ + [get_ports {amp[2]}] \ + [get_ports {amp[3]}] \ + [get_ports {amp[4]}] \ + [get_ports {amp[5]}] \ + [get_ports {amp[6]}] \ + [get_ports {amp[7]}] \ + [get_ports {amp[8]}] \ + [get_ports {amp[9]}] \ + [get_ports {amp[10]}] \ + [get_ports {amp[11]}] \ + [get_ports {rlen[0]}] \ + [get_ports {rlen[1]}] \ + [get_ports {rlen[2]}] \ + [get_ports {rlen[3]}] \ + [get_ports {size[0]}] \ + [get_ports {size[1]}] \ + [get_ports {size[2]}] \ + [get_ports {size[3]}] \ + [get_ports {qnt_cnt[0]}] \ + [get_ports {qnt_cnt[1]}] \ + [get_ports {qnt_cnt[2]}] \ + [get_ports {qnt_cnt[3]}] \ + [get_ports {qnt_cnt[4]}] \ + [get_ports {qnt_cnt[5]}]] set_min_delay 500 \ - -from [list \ - [get_ports ena] \ - [get_ports rst] ] \ - -to [list \ - [get_clocks tclk] ] + -from [list \ + [get_ports ena] \ + [get_ports rst]] \ + -to [list \ + [get_clocks tclk]] group_path -weight 1.000000 -name cg_enable_group_tclk -through [list \ - [get_pins qnr_RC_CG_HIER_INST3/enable] \ - [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ - [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ - [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ - [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ - [get_pins qnr_RC_CG_HIER_INST3/enable] \ - [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ - [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ - [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ - [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ - [get_pins qnr_RC_CG_HIER_INST3/enable] \ - [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ - [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ - [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ - [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ - [get_pins RC_CG_DECLONE_HIER_INST/enable] \ - [get_pins qnr_RC_CG_HIER_INST3/enable] \ - [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ - [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ - [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ - [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ - [get_pins RC_CG_DECLONE_HIER_INST/enable] ] + [get_pins qnr_RC_CG_HIER_INST3/enable] \ + [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ + [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ + [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ + [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ + [get_pins qnr_RC_CG_HIER_INST3/enable] \ + [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ + [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ + [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ + [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ + [get_pins qnr_RC_CG_HIER_INST3/enable] \ + [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ + [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ + [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ + [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ + [get_pins RC_CG_DECLONE_HIER_INST/enable] \ + [get_pins qnr_RC_CG_HIER_INST3/enable] \ + [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ + [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ + [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ + [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ + [get_pins RC_CG_DECLONE_HIER_INST/enable]] set_clock_gating_check -setup 0.0 -set_input_delay 100 -clock tclk [get_ports ena] -set_input_delay 100 -clock tclk [get_ports rst] +set_input_delay 100 -clock tclk [get_ports ena] +set_input_delay 100 -clock tclk [get_ports rst] -set_input_delay 100 -clock tclk [get_ports {qnt_val[0]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[1]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[2]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[3]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[4]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[5]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[6]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[7]}] -set_input_delay 100 -clock tclk [get_ports {din[0]}] -set_input_delay 100 -clock tclk [get_ports {din[1]}] -set_input_delay 100 -clock tclk [get_ports {din[2]}] -set_input_delay 100 -clock tclk [get_ports {din[3]}] -set_input_delay 100 -clock tclk [get_ports {din[4]}] -set_input_delay 100 -clock tclk [get_ports {din[5]}] -set_input_delay 100 -clock tclk [get_ports {din[6]}] -set_input_delay 100 -clock tclk [get_ports {din[7]}] -set_input_delay 100 -clock tclk [get_ports dstrb] -set_output_delay 100 -clock tclk [get_ports douten] -set_output_delay 100 -clock tclk [get_ports {amp[0]}] -set_output_delay 100 -clock tclk [get_ports {amp[1]}] -set_output_delay 100 -clock tclk [get_ports {amp[2]}] -set_output_delay 100 -clock tclk [get_ports {amp[3]}] -set_output_delay 100 -clock tclk [get_ports {amp[4]}] -set_output_delay 100 -clock tclk [get_ports {amp[5]}] -set_output_delay 100 -clock tclk [get_ports {amp[6]}] -set_output_delay 100 -clock tclk [get_ports {amp[7]}] -set_output_delay 100 -clock tclk [get_ports {amp[8]}] -set_output_delay 100 -clock tclk [get_ports {amp[9]}] -set_output_delay 100 -clock tclk [get_ports {amp[10]}] -set_output_delay 100 -clock tclk [get_ports {amp[11]}] -set_output_delay 100 -clock tclk [get_ports {rlen[0]}] -set_output_delay 100 -clock tclk [get_ports {rlen[1]}] -set_output_delay 100 -clock tclk [get_ports {rlen[2]}] -set_output_delay 100 -clock tclk [get_ports {rlen[3]}] -set_output_delay 100 -clock tclk [get_ports {size[0]}] -set_output_delay 100 -clock tclk [get_ports {size[1]}] -set_output_delay 100 -clock tclk [get_ports {size[2]}] -set_output_delay 100 -clock tclk [get_ports {size[3]}] -set_output_delay 100 -clock tclk [get_ports {qnt_cnt[0]}] -set_output_delay 100 -clock tclk [get_ports {qnt_cnt[1]}] -set_output_delay 100 -clock tclk [get_ports {qnt_cnt[2]}] -set_output_delay 100 -clock tclk [get_ports {qnt_cnt[3]}] -set_output_delay 100 -clock tclk [get_ports {qnt_cnt[4]}] -set_output_delay 100 -clock tclk [get_ports {qnt_cnt[5]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[0]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[1]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[2]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[3]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[4]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[5]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[6]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[7]}] +set_input_delay 100 -clock tclk [get_ports {din[0]}] +set_input_delay 100 -clock tclk [get_ports {din[1]}] +set_input_delay 100 -clock tclk [get_ports {din[2]}] +set_input_delay 100 -clock tclk [get_ports {din[3]}] +set_input_delay 100 -clock tclk [get_ports {din[4]}] +set_input_delay 100 -clock tclk [get_ports {din[5]}] +set_input_delay 100 -clock tclk [get_ports {din[6]}] +set_input_delay 100 -clock tclk [get_ports {din[7]}] +set_input_delay 100 -clock tclk [get_ports dstrb] +set_output_delay 100 -clock tclk [get_ports douten] +set_output_delay 100 -clock tclk [get_ports {amp[0]}] +set_output_delay 100 -clock tclk [get_ports {amp[1]}] +set_output_delay 100 -clock tclk [get_ports {amp[2]}] +set_output_delay 100 -clock tclk [get_ports {amp[3]}] +set_output_delay 100 -clock tclk [get_ports {amp[4]}] +set_output_delay 100 -clock tclk [get_ports {amp[5]}] +set_output_delay 100 -clock tclk [get_ports {amp[6]}] +set_output_delay 100 -clock tclk [get_ports {amp[7]}] +set_output_delay 100 -clock tclk [get_ports {amp[8]}] +set_output_delay 100 -clock tclk [get_ports {amp[9]}] +set_output_delay 100 -clock tclk [get_ports {amp[10]}] +set_output_delay 100 -clock tclk [get_ports {amp[11]}] +set_output_delay 100 -clock tclk [get_ports {rlen[0]}] +set_output_delay 100 -clock tclk [get_ports {rlen[1]}] +set_output_delay 100 -clock tclk [get_ports {rlen[2]}] +set_output_delay 100 -clock tclk [get_ports {rlen[3]}] +set_output_delay 100 -clock tclk [get_ports {size[0]}] +set_output_delay 100 -clock tclk [get_ports {size[1]}] +set_output_delay 100 -clock tclk [get_ports {size[2]}] +set_output_delay 100 -clock tclk [get_ports {size[3]}] +set_output_delay 100 -clock tclk [get_ports {qnt_cnt[0]}] +set_output_delay 100 -clock tclk [get_ports {qnt_cnt[1]}] +set_output_delay 100 -clock tclk [get_ports {qnt_cnt[2]}] +set_output_delay 100 -clock tclk [get_ports {qnt_cnt[3]}] +set_output_delay 100 -clock tclk [get_ports {qnt_cnt[4]}] +set_output_delay 100 -clock tclk [get_ports {qnt_cnt[5]}] set_max_fanout 40.000 [current_design] set_max_transition 80.0 [current_design] set_clock_uncertainty -setup 20.0 [get_clocks tclk] diff --git a/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc index a1f1601f12..2e77403245 100644 --- a/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc +++ b/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc @@ -1,6 +1,6 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 1100 set clk_io_pct 0.2 @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/mock-alu/constraints.sdc b/flow/designs/asap7/mock-alu/constraints.sdc index 2a2d4d2f56..66d1e5725e 100644 --- a/flow/designs/asap7/mock-alu/constraints.sdc +++ b/flow/designs/asap7/mock-alu/constraints.sdc @@ -5,15 +5,15 @@ set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * 0.7] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * 0.7] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] set output_regs [get_cells *io_out_REG*] -if {[llength $output_regs] == 0} { - puts "Error: Could not find *io_out_REG*" - exit 1 +if { [llength $output_regs] == 0 } { + puts "Error: Could not find *io_out_REG*" + exit 1 } diff --git a/flow/designs/asap7/mock-array/Element/io.tcl b/flow/designs/asap7/mock-array/Element/io.tcl index 07e4edceb6..e0e50243c7 100644 --- a/flow/designs/asap7/mock-array/Element/io.tcl +++ b/flow/designs/asap7/mock-array/Element/io.tcl @@ -1,58 +1,51 @@ # bazel has root of OpenROAD-flow-scripts as working directory foreach prefix {"" flow/} { set f ${prefix}designs/src/mock-array/util.tcl - if {[file exists $f]} { + if { [file exists $f] } { source $f } } set assignments [list \ - top bottom \ - [list [ concat \ - {*}[match_pins io_ins_down.*] \ - {*}[match_pins io_outs_up.*] \ - ] \ - [ concat \ - {*}[match_pins io_outs_down.*] \ - {*}[match_pins io_ins_up.*] \ - ]] \ - left right \ - [list [ concat \ - {*}[match_pins io_ins_right.*] \ - {*}[match_pins io_outs_left.*] \ - ] \ - [ concat \ - {*}[match_pins io_outs_right.*] \ - {*}[match_pins io_ins_left.*] \ - ]] \ - left right \ - [list [ concat \ - {*}[match_pins io_lsbIns_.*] \ - ] \ - [ concat \ - {*}[match_pins io_lsbOuts_.*] \ - ]] -] + top bottom \ + [list [concat \ + {*}[match_pins io_ins_down.*] \ + {*}[match_pins io_outs_up.*]] \ + [concat \ + {*}[match_pins io_outs_down.*] \ + {*}[match_pins io_ins_up.*]]] \ + left right \ + [list [concat \ + {*}[match_pins io_ins_right.*] \ + {*}[match_pins io_outs_left.*]] \ + [concat \ + {*}[match_pins io_outs_right.*] \ + {*}[match_pins io_ins_left.*]]] \ + left right \ + [list [concat \ + {*}[match_pins io_lsbIns_.*]] \ + [concat \ + {*}[match_pins io_lsbOuts_.*]]]] -proc zip {list1 list2} { - set result {} - set length [llength $list1] - set skip [expr [llength $list2] - [llength $list1]] - for {set i 0} {$i < $length} {incr i} { - lappend result [lindex $list2 [expr $skip + $i]] [lindex $list1 $i] - } - return $result +proc zip { list1 list2 } { + set result {} + set length [llength $list1] + set skip [expr [llength $list2] - [llength $list1]] + for { set i 0 } { $i < $length } { incr i } { + lappend result [lindex $list2 [expr $skip + $i]] [lindex $list1 $i] + } + return $result } foreach {direction direction2 names} $assignments { - set mirrored [zip {*}$names] - set_io_pin_constraint -region $direction2:* -pin_names [lindex $names 1] - # Test pins across multiple metal layers; so don't group - # pins as a group of pins must be on a single metal layer. - # - # set_io_pin_constraint -group -order -pin_names [lindex $names 1] - set_io_pin_constraint -mirrored_pins $mirrored + set mirrored [zip {*}$names] + set_io_pin_constraint -region $direction2:* -pin_names [lindex $names 1] + # Test pins across multiple metal layers; so don't group + # pins as a group of pins must be on a single metal layer. + # + # set_io_pin_constraint -group -order -pin_names [lindex $names 1] + set_io_pin_constraint -mirrored_pins $mirrored } set_io_pin_constraint -region top:* -pin_names clock diff --git a/flow/designs/asap7/mock-array/io.tcl b/flow/designs/asap7/mock-array/io.tcl index 9f1cdde4a5..1bf0ee962b 100644 --- a/flow/designs/asap7/mock-array/io.tcl +++ b/flow/designs/asap7/mock-array/io.tcl @@ -1,35 +1,30 @@ # bazel has root of OpenROAD-flow-scripts as working directory foreach prefix {"" flow/} { set f ${prefix}designs/src/mock-array/util.tcl - if {[file exists $f]} { + if { [file exists $f] } { source $f } } set assignments [list \ - top \ - [ concat \ - {*}[match_pins io_ins_down_.*] \ - {*}[match_pins io_outs_up_.*] \ - ] \ - bottom \ - [ concat \ - {*}[match_pins io_ins_up_.*] \ - {*}[match_pins io_outs_down_.*] \ - ] \ - left \ - [ concat \ - {*}[match_pins io_ins_right_.*] \ - {*}[match_pins io_outs_left_.*] \ - ] \ - right \ - [ concat \ - {*}[match_pins io_ins_left_.*] \ - {*}[match_pins io_outs_right_.*] \ - {*}[match_pins io_lsbs_.*] \ - ] \ -] + top \ + [concat \ + {*}[match_pins io_ins_down_.*] \ + {*}[match_pins io_outs_up_.*]] \ + bottom \ + [concat \ + {*}[match_pins io_ins_up_.*] \ + {*}[match_pins io_outs_down_.*]] \ + left \ + [concat \ + {*}[match_pins io_ins_right_.*] \ + {*}[match_pins io_outs_left_.*]] \ + right \ + [concat \ + {*}[match_pins io_ins_left_.*] \ + {*}[match_pins io_outs_right_.*] \ + {*}[match_pins io_lsbs_.*]]] foreach {direction names} $assignments { - set_io_pin_constraint -region $direction:* -pin_names $names + set_io_pin_constraint -region $direction:* -pin_names $names } diff --git a/flow/designs/asap7/mock-array/macro-placement.tcl b/flow/designs/asap7/mock-array/macro-placement.tcl index 18bd768798..9b1bc3fb70 100644 --- a/flow/designs/asap7/mock-array/macro-placement.tcl +++ b/flow/designs/asap7/mock-array/macro-placement.tcl @@ -15,11 +15,11 @@ set x_offset [expr [$core xMin] + ([$core dx] - (7 * $x_pitch) - [$bbox getDX])/ set y_offset [expr [$core yMin] + ([$core dy] - (7 * $y_pitch) - [$bbox getDY])/2] # Loop through the 8x8 array, add the offset, and invoke place_macro -for {set i 0} {$i < 8} {incr i} { - for {set j 0} {$j < 8} {incr j} { - set macro_name [format "ces_%d_%d" $i $j] - set x_location [expr {$j * $x_pitch + $x_offset}] - set y_location [expr {$i * $y_pitch + $y_offset}] - place_macro -macro_name $macro_name -location [list [expr [ord::dbu_to_microns 1] * $x_location] [expr [ord::dbu_to_microns 1] * $y_location]] -orientation R0 - } +for { set i 0 } { $i < 8 } { incr i } { + for { set j 0 } { $j < 8 } { incr j } { + set macro_name [format "ces_%d_%d" $i $j] + set x_location [expr { $j * $x_pitch + $x_offset }] + set y_location [expr { $i * $y_pitch + $y_offset }] + place_macro -macro_name $macro_name -location [list [expr [ord::dbu_to_microns 1] * $x_location] [expr [ord::dbu_to_microns 1] * $y_location]] -orientation R0 + } } diff --git a/flow/designs/asap7/mock-array/power.tcl b/flow/designs/asap7/mock-array/power.tcl index c53beade09..5f7f136cf9 100644 --- a/flow/designs/asap7/mock-array/power.tcl +++ b/flow/designs/asap7/mock-array/power.tcl @@ -1,7 +1,7 @@ source $::env(SCRIPTS_DIR)/util.tcl foreach libFile $::env(LIB_FILES) { - if {[lsearch -exact $::env(ADDITIONAL_LIBS) $libFile] == -1} { + if { [lsearch -exact $::env(ADDITIONAL_LIBS) $libFile] == -1 } { read_liberty $libFile } } @@ -14,8 +14,8 @@ log_cmd link_design MockArray log_cmd read_sdc $::env(RESULTS_DIR)/6_final.sdc log_cmd read_spef $::env(RESULTS_DIR)/6_final.spef puts "read_spef for ces_*_* macros" -for {set x 0} {$x < 8} {incr x} { - for {set y 0} {$y < 8} {incr y} { +for { set x 0 } { $x < 8 } { incr x } { + for { set y 0 } { $y < 8 } { incr y } { read_spef -path ces_${x}_${y} results/asap7/mock-array_Element/base/6_final.spef } } @@ -36,7 +36,7 @@ set clock_period [expr [get_property [get_clocks] period] * 1e-12] foreach pin $pins { set activity [get_property $pin activity] set activity_origin [lindex $activity 2] - if {$activity_origin != "vcd"} { + if { $activity_origin != "vcd" } { continue } puts $fp "set_power_activity \ @@ -51,32 +51,32 @@ set no_vcd_activity {} foreach pin $pins { set activity [get_property $pin activity] set activity_origin [lindex $activity 2] - if {$activity_origin == "vcd"} { + if { $activity_origin == "vcd" } { continue } - if {$activity_origin == "constant"} { + if { $activity_origin == "constant" } { continue } - if {$activity_origin == "unknown"} { + if { $activity_origin == "unknown" } { continue } - if {[get_property $pin is_hierarchical]} { + if { [get_property $pin is_hierarchical] } { continue } - if {$activity_origin == "clock"} { + if { $activity_origin == "clock" } { continue } set direction [get_property $pin direction] - if {$direction == "internal"} { + if { $direction == "internal" } { continue } lappend no_vcd_activity "[get_full_name $pin] $activity $direction" - if {[llength $no_vcd_activity] >= 10} { + if { [llength $no_vcd_activity] >= 10 } { break } } -if {[llength $no_vcd_activity] > 0} { +if { [llength $no_vcd_activity] > 0 } { puts "Error: Listing [llength $no_vcd_activity] pins without activity from $vcd_file:" foreach pin $no_vcd_activity { puts $pin @@ -85,8 +85,8 @@ if {[llength $no_vcd_activity] > 0} { } set ces {} -for {set x 0} {$x < 8} {incr x} { - for {set y 0} {$y < 8} {incr y} { +for { set x 0 } { $x < 8 } { incr x } { + for { set y 0 } { $y < 8 } { incr y } { lappend ces ces_${x}_${y} } } @@ -94,7 +94,7 @@ for {set x 0} {$x < 8} {incr x} { puts {report_power -instances [get_cells $ces]} report_power -instances [get_cells $ces] -proc total_power {} { +proc total_power { } { return [lindex [sta::design_power [sta::corners]] 3] } @@ -108,12 +108,12 @@ set total_power_user_activity [total_power] puts "Total power from VCD: $total_power_vcd" puts "Total power from user activity: $total_power_user_activity" -if {$total_power_vcd == $total_power_user_activity} { +if { $total_power_vcd == $total_power_user_activity } { puts "Error: settting user power activity had no effect, expected some loss in accuracy" exit 1 } -if {abs($total_power_vcd - $total_power_user_activity) > 1e-3} { +if { abs($total_power_vcd - $total_power_user_activity) > 1e-3 } { puts "Error: Total power mismatch between VCD and user activity: $total_power_vcd vs $total_power_user_activity" exit 1 } diff --git a/flow/designs/asap7/mock-cpu/constraint.sdc b/flow/designs/asap7/mock-cpu/constraint.sdc index 15002f21dd..8f5b42e89f 100644 --- a/flow/designs/asap7/mock-cpu/constraint.sdc +++ b/flow/designs/asap7/mock-cpu/constraint.sdc @@ -31,7 +31,7 @@ set_false_path -to [get_ports *rst_n] set non_clk_inputs {} set clock_ports [list [get_ports $clk1_name] [get_ports $clk2_name]] foreach input [all_inputs] { - if {[lsearch -exact $clock_ports $input] == -1} { + if { [lsearch -exact $clock_ports $input] == -1 } { lappend non_clk_inputs $input } } diff --git a/flow/designs/asap7/mock-cpu/io.tcl b/flow/designs/asap7/mock-cpu/io.tcl index 01693e7da3..322f85c1f4 100644 --- a/flow/designs/asap7/mock-cpu/io.tcl +++ b/flow/designs/asap7/mock-cpu/io.tcl @@ -1,7 +1,7 @@ # bazel has root of OpenROAD-flow-scripts as working directory foreach prefix {"" flow/} { set f ${prefix}designs/src/mock-array/util.tcl - if {[file exists $f]} { + if { [file exists $f] } { source $f } } diff --git a/flow/designs/asap7/riscv32i/constraint.sdc b/flow/designs/asap7/riscv32i/constraint.sdc index 74dca22a8f..3cea613851 100644 --- a/flow/designs/asap7/riscv32i/constraint.sdc +++ b/flow/designs/asap7/riscv32i/constraint.sdc @@ -1,6 +1,6 @@ current_design riscv_top -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 1260 set clk_io_pct 0.125 @@ -10,5 +10,5 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/swerv_wrapper/constraint.sdc b/flow/designs/asap7/swerv_wrapper/constraint.sdc index f679177441..955b0805d5 100644 --- a/flow/designs/asap7/swerv_wrapper/constraint.sdc +++ b/flow/designs/asap7/swerv_wrapper/constraint.sdc @@ -1,8 +1,8 @@ current_design swerv_wrapper -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 2500 +set clk_period 2500 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/uart/constraint.sdc b/flow/designs/asap7/uart/constraint.sdc index cc49402954..0d7aa226f0 100644 --- a/flow/designs/asap7/uart/constraint.sdc +++ b/flow/designs/asap7/uart/constraint.sdc @@ -1,6 +1,6 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 300 +set clk_period 300 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf12/aes/constraint.sdc b/flow/designs/gf12/aes/constraint.sdc index a930ae4ba7..ae1bc48d58 100644 --- a/flow/designs/gf12/aes/constraint.sdc +++ b/flow/designs/gf12/aes/constraint.sdc @@ -1,17 +1,17 @@ current_design aes_cipher_top -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 420 +set clk_period 420 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] set_timing_derate -early 0.9500 diff --git a/flow/designs/gf12/ariane/constraint.sdc b/flow/designs/gf12/ariane/constraint.sdc index 2430c4b71e..d5971e4984 100644 --- a/flow/designs/gf12/ariane/constraint.sdc +++ b/flow/designs/gf12/ariane/constraint.sdc @@ -1,495 +1,495 @@ -create_clock [get_ports clk_i] -name core_clock -period 3400 -waveform {0 850} -set_input_delay -clock core_clock 1000 [get_ports rst_ni] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[63]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[62]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[61]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[60]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[59]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[58]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[57]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[56]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[55]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[54]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[53]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[52]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[51]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[50]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[49]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[48]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[47]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[46]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[45]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[44]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[43]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[42]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[41]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[40]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[39]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[38]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[37]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[36]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[35]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[34]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[33]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[32]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[31]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[30]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[29]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[28]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[27]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[26]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[25]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[24]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[23]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[22]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[21]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[20]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[19]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[18]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[17]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[16]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[15]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[14]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[13]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[12]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[11]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[10]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[9]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[8]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[7]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[6]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[5]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[4]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[3]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[2]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[1]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[0]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[63]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[62]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[61]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[60]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[59]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[58]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[57]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[56]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[55]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[54]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[53]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[52]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[51]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[50]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[49]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[48]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[47]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[46]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[45]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[44]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[43]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[42]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[41]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[40]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[39]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[38]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[37]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[36]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[35]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[34]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[33]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[32]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[31]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[30]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[29]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[28]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[27]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[26]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[25]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[24]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[23]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[22]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[21]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[20]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[19]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[18]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[17]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[16]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[15]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[14]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[13]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[12]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[11]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[10]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[9]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[8]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[7]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[6]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[5]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[4]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[3]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[2]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[1]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[0]}] -set_input_delay -clock core_clock 1000 [get_ports {irq_i[1]}] -set_input_delay -clock core_clock 1000 [get_ports {irq_i[0]}] -set_input_delay -clock core_clock 1000 [get_ports ipi_i] -set_input_delay -clock core_clock 1000 [get_ports time_irq_i] -set_input_delay -clock core_clock 1000 [get_ports debug_req_i] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[81]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[80]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[79]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[78]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[77]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[76]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[75]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[74]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[73]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[72]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[71]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[70]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[69]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[68]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[67]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[66]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[65]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[64]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[63]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[62]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[61]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[60]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[59]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[58]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[57]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[56]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[55]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[54]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[53]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[52]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[51]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[50]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[49]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[48]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[47]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[46]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[45]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[44]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[43]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[42]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[41]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[40]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[39]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[38]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[37]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[36]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[35]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[34]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[33]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[32]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[31]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[30]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[29]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[28]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[27]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[26]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[25]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[24]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[23]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[22]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[21]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[20]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[19]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[18]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[17]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[16]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[15]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[14]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[13]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[12]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[11]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[10]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[9]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[8]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[7]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[6]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[5]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[4]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[3]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[2]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[1]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[0]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[277]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[276]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[275]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[274]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[273]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[272]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[271]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[270]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[269]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[268]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[267]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[266]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[265]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[264]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[263]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[262]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[261]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[260]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[259]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[258]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[257]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[256]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[255]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[254]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[253]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[252]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[251]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[250]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[249]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[248]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[247]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[246]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[245]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[244]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[243]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[242]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[241]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[240]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[239]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[238]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[237]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[236]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[235]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[234]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[233]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[232]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[231]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[230]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[229]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[228]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[227]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[226]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[225]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[224]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[223]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[222]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[221]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[220]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[219]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[218]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[217]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[216]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[215]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[214]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[213]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[212]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[211]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[210]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[209]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[208]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[207]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[206]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[205]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[204]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[203]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[202]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[201]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[200]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[199]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[198]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[197]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[196]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[195]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[194]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[193]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[192]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[191]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[190]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[189]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[188]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[187]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[186]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[185]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[184]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[183]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[182]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[181]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[180]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[179]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[178]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[177]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[176]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[175]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[174]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[173]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[172]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[171]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[170]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[169]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[168]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[167]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[166]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[165]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[164]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[163]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[162]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[161]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[160]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[159]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[158]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[157]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[156]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[155]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[154]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[153]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[152]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[151]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[150]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[149]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[148]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[147]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[146]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[145]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[144]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[143]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[142]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[141]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[140]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[139]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[138]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[137]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[136]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[135]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[134]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[133]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[132]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[131]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[130]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[129]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[128]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[127]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[126]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[125]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[124]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[123]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[122]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[121]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[120]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[119]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[118]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[117]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[116]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[115]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[114]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[113]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[112]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[111]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[110]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[109]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[108]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[107]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[106]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[105]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[104]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[103]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[102]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[101]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[100]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[99]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[98]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[97]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[96]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[95]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[94]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[93]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[92]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[91]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[90]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[89]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[88]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[87]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[86]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[85]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[84]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[83]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[82]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[81]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[80]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[79]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[78]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[77]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[76]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[75]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[74]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[73]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[72]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[71]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[70]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[69]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[68]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[67]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[66]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[65]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[64]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[63]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[62]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[61]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[60]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[59]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[58]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[57]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[56]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[55]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[54]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[53]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[52]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[51]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[50]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[49]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[48]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[47]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[46]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[45]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[44]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[43]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[42]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[41]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[40]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[39]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[38]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[37]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[36]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[35]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[34]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[33]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[32]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[31]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[30]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[29]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[28]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[27]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[26]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[25]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[24]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[23]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[22]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[21]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[20]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[19]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[18]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[17]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[16]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[15]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[14]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[13]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[12]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[11]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[10]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[9]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[8]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[7]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[6]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[5]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[4]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[3]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[2]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[1]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[0]}] +create_clock [get_ports clk_i] -name core_clock -period 3400 -waveform {0 850} +set_input_delay -clock core_clock 1000 [get_ports rst_ni] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[63]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[62]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[61]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[60]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[59]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[58]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[57]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[56]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[55]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[54]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[53]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[52]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[51]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[50]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[49]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[48]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[47]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[46]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[45]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[44]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[43]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[42]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[41]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[40]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[39]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[38]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[37]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[36]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[35]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[34]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[33]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[32]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[31]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[30]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[29]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[28]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[27]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[26]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[25]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[24]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[23]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[22]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[21]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[20]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[19]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[18]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[17]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[16]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[15]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[14]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[13]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[12]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[11]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[10]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[9]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[8]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[7]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[6]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[5]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[4]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[3]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[2]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[1]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[0]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[63]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[62]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[61]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[60]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[59]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[58]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[57]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[56]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[55]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[54]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[53]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[52]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[51]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[50]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[49]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[48]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[47]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[46]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[45]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[44]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[43]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[42]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[41]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[40]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[39]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[38]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[37]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[36]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[35]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[34]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[33]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[32]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[31]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[30]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[29]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[28]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[27]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[26]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[25]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[24]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[23]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[22]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[21]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[20]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[19]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[18]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[17]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[16]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[15]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[14]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[13]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[12]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[11]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[10]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[9]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[8]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[7]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[6]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[5]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[4]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[3]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[2]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[1]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[0]}] +set_input_delay -clock core_clock 1000 [get_ports {irq_i[1]}] +set_input_delay -clock core_clock 1000 [get_ports {irq_i[0]}] +set_input_delay -clock core_clock 1000 [get_ports ipi_i] +set_input_delay -clock core_clock 1000 [get_ports time_irq_i] +set_input_delay -clock core_clock 1000 [get_ports debug_req_i] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[81]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[80]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[79]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[78]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[77]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[76]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[75]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[74]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[73]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[72]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[71]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[70]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[69]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[68]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[67]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[66]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[65]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[64]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[63]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[62]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[61]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[60]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[59]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[58]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[57]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[56]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[55]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[54]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[53]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[52]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[51]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[50]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[49]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[48]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[47]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[46]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[45]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[44]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[43]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[42]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[41]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[40]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[39]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[38]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[37]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[36]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[35]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[34]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[33]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[32]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[31]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[30]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[29]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[28]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[27]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[26]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[25]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[24]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[23]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[22]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[21]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[20]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[19]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[18]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[17]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[16]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[15]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[14]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[13]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[12]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[11]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[10]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[9]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[8]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[7]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[6]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[5]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[4]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[3]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[2]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[1]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[0]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[277]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[276]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[275]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[274]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[273]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[272]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[271]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[270]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[269]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[268]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[267]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[266]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[265]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[264]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[263]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[262]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[261]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[260]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[259]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[258]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[257]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[256]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[255]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[254]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[253]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[252]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[251]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[250]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[249]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[248]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[247]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[246]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[245]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[244]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[243]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[242]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[241]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[240]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[239]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[238]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[237]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[236]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[235]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[234]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[233]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[232]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[231]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[230]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[229]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[228]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[227]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[226]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[225]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[224]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[223]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[222]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[221]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[220]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[219]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[218]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[217]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[216]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[215]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[214]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[213]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[212]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[211]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[210]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[209]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[208]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[207]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[206]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[205]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[204]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[203]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[202]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[201]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[200]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[199]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[198]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[197]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[196]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[195]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[194]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[193]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[192]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[191]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[190]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[189]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[188]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[187]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[186]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[185]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[184]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[183]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[182]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[181]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[180]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[179]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[178]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[177]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[176]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[175]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[174]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[173]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[172]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[171]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[170]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[169]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[168]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[167]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[166]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[165]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[164]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[163]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[162]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[161]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[160]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[159]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[158]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[157]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[156]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[155]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[154]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[153]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[152]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[151]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[150]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[149]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[148]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[147]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[146]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[145]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[144]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[143]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[142]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[141]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[140]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[139]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[138]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[137]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[136]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[135]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[134]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[133]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[132]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[131]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[130]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[129]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[128]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[127]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[126]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[125]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[124]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[123]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[122]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[121]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[120]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[119]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[118]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[117]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[116]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[115]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[114]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[113]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[112]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[111]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[110]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[109]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[108]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[107]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[106]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[105]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[104]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[103]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[102]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[101]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[100]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[99]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[98]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[97]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[96]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[95]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[94]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[93]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[92]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[91]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[90]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[89]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[88]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[87]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[86]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[85]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[84]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[83]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[82]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[81]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[80]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[79]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[78]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[77]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[76]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[75]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[74]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[73]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[72]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[71]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[70]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[69]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[68]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[67]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[66]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[65]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[64]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[63]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[62]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[61]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[60]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[59]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[58]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[57]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[56]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[55]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[54]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[53]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[52]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[51]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[50]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[49]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[48]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[47]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[46]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[45]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[44]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[43]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[42]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[41]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[40]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[39]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[38]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[37]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[36]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[35]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[34]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[33]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[32]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[31]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[30]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[29]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[28]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[27]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[26]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[25]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[24]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[23]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[22]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[21]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[20]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[19]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[18]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[17]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[16]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[15]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[14]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[13]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[12]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[11]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[10]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[9]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[8]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[7]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[6]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[5]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[4]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[3]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[2]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[1]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[0]}] diff --git a/flow/designs/gf12/ariane/constraint_hier.sdc b/flow/designs/gf12/ariane/constraint_hier.sdc index 89c4ae0115..1a22a7607f 100644 --- a/flow/designs/gf12/ariane/constraint_hier.sdc +++ b/flow/designs/gf12/ariane/constraint_hier.sdc @@ -1,495 +1,495 @@ -create_clock [get_ports clk_i] -name core_clock -period 3000 -waveform {0 1500} -set_input_delay -clock core_clock 1500 [get_ports rst_ni] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[63]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[62]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[61]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[60]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[59]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[58]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[57]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[56]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[55]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[54]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[53]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[52]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[51]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[50]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[49]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[48]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[47]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[46]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[45]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[44]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[43]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[42]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[41]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[40]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[39]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[38]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[37]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[36]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[35]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[34]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[33]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[32]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[31]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[30]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[29]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[28]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[27]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[26]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[25]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[24]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[23]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[22]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[21]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[20]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[19]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[18]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[17]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[16]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[15]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[14]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[13]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[12]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[11]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[10]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[9]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[8]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[7]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[6]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[5]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[4]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[3]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[2]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[1]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[0]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[63]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[62]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[61]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[60]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[59]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[58]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[57]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[56]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[55]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[54]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[53]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[52]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[51]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[50]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[49]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[48]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[47]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[46]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[45]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[44]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[43]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[42]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[41]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[40]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[39]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[38]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[37]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[36]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[35]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[34]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[33]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[32]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[31]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[30]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[29]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[28]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[27]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[26]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[25]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[24]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[23]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[22]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[21]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[20]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[19]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[18]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[17]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[16]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[15]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[14]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[13]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[12]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[11]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[10]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[9]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[8]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[7]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[6]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[5]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[4]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[3]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[2]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[1]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[0]}] -set_input_delay -clock core_clock 1500 [get_ports {irq_i[1]}] -set_input_delay -clock core_clock 1500 [get_ports {irq_i[0]}] -set_input_delay -clock core_clock 1500 [get_ports ipi_i] -set_input_delay -clock core_clock 1500 [get_ports time_irq_i] -set_input_delay -clock core_clock 1500 [get_ports debug_req_i] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[81]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[80]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[79]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[78]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[77]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[76]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[75]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[74]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[73]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[72]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[71]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[70]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[69]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[68]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[67]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[66]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[65]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[64]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[63]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[62]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[61]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[60]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[59]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[58]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[57]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[56]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[55]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[54]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[53]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[52]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[51]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[50]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[49]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[48]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[47]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[46]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[45]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[44]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[43]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[42]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[41]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[40]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[39]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[38]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[37]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[36]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[35]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[34]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[33]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[32]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[31]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[30]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[29]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[28]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[27]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[26]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[25]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[24]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[23]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[22]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[21]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[20]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[19]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[18]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[17]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[16]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[15]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[14]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[13]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[12]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[11]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[10]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[9]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[8]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[7]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[6]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[5]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[4]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[3]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[2]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[1]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[0]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[277]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[276]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[275]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[274]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[273]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[272]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[271]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[270]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[269]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[268]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[267]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[266]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[265]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[264]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[263]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[262]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[261]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[260]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[259]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[258]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[257]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[256]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[255]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[254]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[253]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[252]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[251]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[250]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[249]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[248]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[247]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[246]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[245]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[244]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[243]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[242]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[241]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[240]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[239]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[238]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[237]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[236]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[235]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[234]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[233]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[232]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[231]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[230]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[229]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[228]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[227]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[226]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[225]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[224]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[223]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[222]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[221]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[220]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[219]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[218]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[217]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[216]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[215]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[214]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[213]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[212]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[211]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[210]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[209]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[208]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[207]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[206]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[205]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[204]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[203]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[202]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[201]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[200]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[199]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[198]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[197]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[196]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[195]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[194]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[193]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[192]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[191]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[190]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[189]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[188]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[187]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[186]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[185]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[184]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[183]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[182]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[181]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[180]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[179]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[178]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[177]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[176]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[175]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[174]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[173]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[172]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[171]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[170]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[169]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[168]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[167]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[166]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[165]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[164]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[163]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[162]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[161]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[160]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[159]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[158]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[157]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[156]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[155]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[154]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[153]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[152]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[151]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[150]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[149]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[148]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[147]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[146]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[145]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[144]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[143]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[142]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[141]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[140]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[139]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[138]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[137]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[136]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[135]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[134]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[133]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[132]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[131]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[130]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[129]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[128]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[127]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[126]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[125]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[124]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[123]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[122]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[121]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[120]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[119]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[118]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[117]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[116]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[115]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[114]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[113]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[112]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[111]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[110]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[109]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[108]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[107]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[106]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[105]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[104]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[103]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[102]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[101]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[100]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[99]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[98]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[97]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[96]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[95]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[94]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[93]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[92]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[91]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[90]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[89]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[88]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[87]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[86]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[85]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[84]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[83]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[82]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[81]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[80]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[79]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[78]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[77]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[76]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[75]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[74]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[73]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[72]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[71]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[70]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[69]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[68]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[67]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[66]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[65]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[64]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[63]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[62]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[61]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[60]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[59]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[58]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[57]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[56]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[55]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[54]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[53]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[52]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[51]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[50]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[49]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[48]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[47]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[46]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[45]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[44]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[43]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[42]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[41]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[40]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[39]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[38]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[37]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[36]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[35]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[34]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[33]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[32]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[31]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[30]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[29]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[28]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[27]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[26]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[25]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[24]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[23]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[22]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[21]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[20]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[19]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[18]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[17]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[16]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[15]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[14]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[13]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[12]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[11]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[10]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[9]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[8]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[7]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[6]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[5]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[4]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[3]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[2]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[1]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[0]}] +create_clock [get_ports clk_i] -name core_clock -period 3000 -waveform {0 1500} +set_input_delay -clock core_clock 1500 [get_ports rst_ni] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[63]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[62]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[61]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[60]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[59]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[58]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[57]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[56]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[55]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[54]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[53]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[52]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[51]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[50]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[49]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[48]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[47]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[46]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[45]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[44]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[43]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[42]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[41]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[40]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[39]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[38]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[37]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[36]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[35]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[34]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[33]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[32]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[31]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[30]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[29]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[28]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[27]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[26]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[25]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[24]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[23]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[22]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[21]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[20]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[19]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[18]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[17]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[16]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[15]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[14]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[13]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[12]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[11]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[10]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[9]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[8]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[7]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[6]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[5]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[4]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[3]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[2]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[1]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[0]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[63]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[62]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[61]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[60]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[59]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[58]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[57]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[56]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[55]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[54]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[53]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[52]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[51]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[50]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[49]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[48]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[47]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[46]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[45]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[44]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[43]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[42]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[41]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[40]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[39]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[38]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[37]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[36]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[35]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[34]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[33]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[32]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[31]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[30]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[29]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[28]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[27]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[26]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[25]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[24]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[23]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[22]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[21]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[20]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[19]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[18]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[17]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[16]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[15]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[14]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[13]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[12]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[11]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[10]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[9]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[8]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[7]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[6]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[5]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[4]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[3]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[2]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[1]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[0]}] +set_input_delay -clock core_clock 1500 [get_ports {irq_i[1]}] +set_input_delay -clock core_clock 1500 [get_ports {irq_i[0]}] +set_input_delay -clock core_clock 1500 [get_ports ipi_i] +set_input_delay -clock core_clock 1500 [get_ports time_irq_i] +set_input_delay -clock core_clock 1500 [get_ports debug_req_i] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[81]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[80]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[79]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[78]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[77]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[76]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[75]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[74]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[73]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[72]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[71]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[70]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[69]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[68]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[67]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[66]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[65]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[64]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[63]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[62]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[61]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[60]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[59]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[58]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[57]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[56]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[55]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[54]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[53]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[52]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[51]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[50]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[49]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[48]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[47]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[46]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[45]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[44]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[43]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[42]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[41]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[40]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[39]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[38]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[37]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[36]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[35]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[34]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[33]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[32]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[31]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[30]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[29]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[28]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[27]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[26]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[25]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[24]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[23]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[22]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[21]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[20]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[19]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[18]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[17]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[16]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[15]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[14]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[13]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[12]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[11]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[10]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[9]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[8]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[7]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[6]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[5]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[4]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[3]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[2]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[1]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[0]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[277]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[276]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[275]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[274]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[273]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[272]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[271]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[270]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[269]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[268]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[267]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[266]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[265]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[264]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[263]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[262]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[261]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[260]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[259]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[258]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[257]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[256]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[255]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[254]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[253]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[252]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[251]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[250]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[249]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[248]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[247]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[246]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[245]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[244]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[243]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[242]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[241]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[240]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[239]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[238]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[237]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[236]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[235]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[234]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[233]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[232]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[231]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[230]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[229]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[228]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[227]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[226]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[225]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[224]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[223]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[222]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[221]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[220]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[219]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[218]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[217]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[216]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[215]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[214]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[213]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[212]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[211]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[210]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[209]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[208]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[207]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[206]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[205]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[204]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[203]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[202]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[201]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[200]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[199]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[198]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[197]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[196]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[195]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[194]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[193]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[192]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[191]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[190]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[189]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[188]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[187]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[186]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[185]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[184]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[183]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[182]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[181]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[180]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[179]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[178]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[177]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[176]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[175]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[174]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[173]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[172]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[171]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[170]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[169]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[168]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[167]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[166]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[165]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[164]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[163]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[162]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[161]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[160]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[159]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[158]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[157]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[156]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[155]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[154]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[153]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[152]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[151]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[150]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[149]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[148]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[147]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[146]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[145]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[144]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[143]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[142]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[141]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[140]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[139]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[138]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[137]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[136]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[135]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[134]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[133]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[132]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[131]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[130]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[129]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[128]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[127]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[126]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[125]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[124]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[123]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[122]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[121]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[120]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[119]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[118]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[117]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[116]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[115]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[114]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[113]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[112]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[111]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[110]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[109]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[108]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[107]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[106]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[105]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[104]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[103]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[102]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[101]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[100]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[99]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[98]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[97]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[96]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[95]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[94]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[93]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[92]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[91]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[90]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[89]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[88]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[87]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[86]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[85]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[84]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[83]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[82]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[81]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[80]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[79]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[78]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[77]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[76]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[75]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[74]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[73]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[72]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[71]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[70]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[69]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[68]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[67]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[66]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[65]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[64]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[63]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[62]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[61]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[60]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[59]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[58]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[57]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[56]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[55]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[54]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[53]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[52]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[51]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[50]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[49]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[48]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[47]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[46]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[45]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[44]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[43]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[42]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[41]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[40]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[39]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[38]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[37]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[36]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[35]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[34]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[33]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[32]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[31]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[30]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[29]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[28]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[27]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[26]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[25]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[24]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[23]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[22]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[21]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[20]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[19]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[18]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[17]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[16]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[15]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[14]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[13]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[12]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[11]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[10]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[9]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[8]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[7]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[6]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[5]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[4]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[3]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[2]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[1]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[0]}] diff --git a/flow/designs/gf12/ariane133/ariane.sdc b/flow/designs/gf12/ariane133/ariane.sdc index c756ae05a3..4ddcb37965 100644 --- a/flow/designs/gf12/ariane133/ariane.sdc +++ b/flow/designs/gf12/ariane133/ariane.sdc @@ -7,5 +7,5 @@ set_units -time 1ps current_design ariane create_clock -name "core_clock" -period 1300.0 -waveform {0.0 900.0} [get_ports clk_i] -set_clock_gating_check -setup 0.0 +set_clock_gating_check -setup 0.0 set_wire_load_mode "top" diff --git a/flow/designs/gf12/bp_single/fastroute.tcl b/flow/designs/gf12/bp_single/fastroute.tcl index 24379738d7..e05f213a65 100644 --- a/flow/designs/gf12/bp_single/fastroute.tcl +++ b/flow/designs/gf12/bp_single/fastroute.tcl @@ -3,5 +3,4 @@ set_global_routing_layer_adjustment M3 0.6 set_global_routing_layer_adjustment C4-C5 0.5 set_global_routing_layer_adjustment K1-K4 0.45 -set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) -clock K1-$::env(MAX_ROUTING_LAYER) - +set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) -clock K1-$::env(MAX_ROUTING_LAYER) diff --git a/flow/designs/gf12/ca53/fastroute.tcl b/flow/designs/gf12/ca53/fastroute.tcl index 177a36a3e5..7b9941dfdb 100644 --- a/flow/designs/gf12/ca53/fastroute.tcl +++ b/flow/designs/gf12/ca53/fastroute.tcl @@ -3,5 +3,4 @@ set_global_routing_layer_adjustment M3 0.5 set_global_routing_layer_adjustment C4-K4 0.5 #set_global_routing_layer_adjustment H1-H2 0.5 -set_routing_layers -signal M2-$::env(MAX_ROUTING_LAYER) -clock K1-$::env(MAX_ROUTING_LAYER) - +set_routing_layers -signal M2-$::env(MAX_ROUTING_LAYER) -clock K1-$::env(MAX_ROUTING_LAYER) diff --git a/flow/designs/gf12/coyote/constraint.sdc b/flow/designs/gf12/coyote/constraint.sdc index a27541fdcd..d80a6cd806 100644 --- a/flow/designs/gf12/coyote/constraint.sdc +++ b/flow/designs/gf12/coyote/constraint.sdc @@ -814,10 +814,10 @@ set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dca set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem0.macro_mem0}] set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem1.macro_mem0}] set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem1.macro_mem0}] -set_false_path\ - -to [list [get_ports {rocc_ctrl_o_exception_}]\ - [get_ports {rocc_ctrl_o_host_id_}]\ - [get_ports {rocc_ctrl_o_s_}]] +set_false_path \ + -to [list [get_ports {rocc_ctrl_o_exception_}] \ + [get_ports {rocc_ctrl_o_host_id_}] \ + [get_ports {rocc_ctrl_o_s_}]] ############################################################################### # Environment ############################################################################### diff --git a/flow/designs/gf12/coyote/constraint_hier.sdc b/flow/designs/gf12/coyote/constraint_hier.sdc index 19f548615f..d8a085a067 100644 --- a/flow/designs/gf12/coyote/constraint_hier.sdc +++ b/flow/designs/gf12/coyote/constraint_hier.sdc @@ -814,10 +814,10 @@ set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dca set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem0/macro_mem0}] set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}] set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}] -set_false_path\ - -to [list [get_ports {rocc_ctrl_o_exception_}]\ - [get_ports {rocc_ctrl_o_host_id_}]\ - [get_ports {rocc_ctrl_o_s_}]] +set_false_path \ + -to [list [get_ports {rocc_ctrl_o_exception_}] \ + [get_ports {rocc_ctrl_o_host_id_}] \ + [get_ports {rocc_ctrl_o_s_}]] ############################################################################### # Environment ############################################################################### diff --git a/flow/designs/gf12/coyote/io.tcl b/flow/designs/gf12/coyote/io.tcl index 39d22dc7cf..eddd0b8d59 100644 --- a/flow/designs/gf12/coyote/io.tcl +++ b/flow/designs/gf12/coyote/io.tcl @@ -1 +1 @@ -exclude_io_pin_region -region left:* -region right:* -region top:* -region bottom:0-20 -region bottom:450-750 \ No newline at end of file +exclude_io_pin_region -region left:* -region right:* -region top:* -region bottom:0-20 -region bottom:450-750 diff --git a/flow/designs/gf12/gcd/constraint.sdc b/flow/designs/gf12/gcd/constraint.sdc index e1df1eb91a..18fe09d581 100644 --- a/flow/designs/gf12/gcd/constraint.sdc +++ b/flow/designs/gf12/gcd/constraint.sdc @@ -1,17 +1,17 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 280 +set clk_period 280 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] # set_timing_derate -early 0.9500 diff --git a/flow/designs/gf12/ibex/constraint.sdc b/flow/designs/gf12/ibex/constraint.sdc index 1684b897b5..3d19120721 100644 --- a/flow/designs/gf12/ibex/constraint.sdc +++ b/flow/designs/gf12/ibex/constraint.sdc @@ -1,17 +1,17 @@ current_design ibex_core -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i -set clk_period 1020 +set clk_period 1020 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] set_timing_derate -early 0.9500 diff --git a/flow/designs/gf12/jpeg/constraint.sdc b/flow/designs/gf12/jpeg/constraint.sdc index 86761946c6..d196f8f423 100644 --- a/flow/designs/gf12/jpeg/constraint.sdc +++ b/flow/designs/gf12/jpeg/constraint.sdc @@ -1,17 +1,17 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 770 +set clk_period 770 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] set_timing_derate -early 0.9500 diff --git a/flow/designs/gf12/swerv_wrapper/constraint.sdc b/flow/designs/gf12/swerv_wrapper/constraint.sdc index a7296dd71c..186b5121f8 100644 --- a/flow/designs/gf12/swerv_wrapper/constraint.sdc +++ b/flow/designs/gf12/swerv_wrapper/constraint.sdc @@ -8,11 +8,11 @@ current_design swerv_wrapper ############################################################################### create_clock -name core_clock -period 1500.0 -waveform {0.0000 750.0} [get_ports {clk}] set_clock_uncertainty -setup 70.0000 core_clock -set_clock_uncertainty -hold 70.0000 core_clock +set_clock_uncertainty -hold 70.0000 core_clock #set_propagated_clock [get_clocks {core_clock}] create_clock -name jtag_clock -period 1500 -waveform {0.0000 750.0} [get_ports {jtag_tck}] set_clock_uncertainty -setup 70.0000 jtag_clock -set_clock_uncertainty -hold 70.0000 jtag_clock +set_clock_uncertainty -hold 70.0000 jtag_clock #set_propagated_clock [get_clocks {jtag_clock}] # There is sync logic between jtag and core_clock @@ -25,7 +25,7 @@ set_clock_uncertainty -hold 70.0000 jtag_clock # Design Rules ############################################################################### set clock_ports "jtag_tck clk" -set jtag_ports "jtag_id* jtag_tdi jtag_tms jtag_trst_n" +set jtag_ports "jtag_id* jtag_tdi jtag_tms jtag_trst_n" #set input_not_jtag_ports [remove_from_collection [all_inputs] "$jtag_ports $clock_ports"] set input_not_jtag_ports [list] foreach input [all_inputs] { @@ -40,9 +40,9 @@ foreach input [all_inputs] { lappend input_not_jtag_ports $input } } -set_input_delay 375 -clock jtag_clock $jtag_ports +set_input_delay 375 -clock jtag_clock $jtag_ports set_output_delay 375 -clock jtag_clock [get_ports "jtag_tdo"] -set_input_delay 750 -clock core_clock $input_not_jtag_ports +set_input_delay 750 -clock core_clock $input_not_jtag_ports set ports_list [list] foreach output [all_outputs] { set addFlag 1 @@ -63,5 +63,3 @@ set_driving_cell -lib_cell BUFH_X2N_A9PP84TR_C14 [all_inputs] foreach input [all_inputs] { set_load 0 $input } - - diff --git a/flow/designs/gf12/tinyRocket/constraint.sdc b/flow/designs/gf12/tinyRocket/constraint.sdc index e5604adf91..02e8f6f066 100644 --- a/flow/designs/gf12/tinyRocket/constraint.sdc +++ b/flow/designs/gf12/tinyRocket/constraint.sdc @@ -1,13 +1,13 @@ -set clk_name core_clock +set clk_name core_clock set clk_port_name clock -set clk_period 800 +set clk_period 800 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/aes/constraint.sdc b/flow/designs/gf180/aes/constraint.sdc index 2e7189ca5f..da8e0a8244 100644 --- a/flow/designs/gf180/aes/constraint.sdc +++ b/flow/designs/gf180/aes/constraint.sdc @@ -1,19 +1,18 @@ current_design aes_cipher_top -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 3 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] set_timing_derate -early 0.9500 set_timing_derate -late 1.0500 - diff --git a/flow/designs/gf180/ibex/constraint.sdc b/flow/designs/gf180/ibex/constraint.sdc index e6e7f6257a..d91411c4dc 100644 --- a/flow/designs/gf180/ibex/constraint.sdc +++ b/flow/designs/gf180/ibex/constraint.sdc @@ -1,6 +1,6 @@ current_design ibex_core -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 10.0 set clk_io_pct 0.2 @@ -11,6 +11,6 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] set_false_path -from [get_ports {rst_ni}] diff --git a/flow/designs/gf180/jpeg/constraint.sdc b/flow/designs/gf180/jpeg/constraint.sdc index d123c56533..5862d8ce02 100644 --- a/flow/designs/gf180/jpeg/constraint.sdc +++ b/flow/designs/gf180/jpeg/constraint.sdc @@ -1,6 +1,6 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 7.5 set clk_io_pct 0.2 @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/jpeg/io.tcl b/flow/designs/gf180/jpeg/io.tcl index e023ab42b4..0c81b1f9fa 100644 --- a/flow/designs/gf180/jpeg/io.tcl +++ b/flow/designs/gf180/jpeg/io.tcl @@ -1 +1 @@ -exclude_io_pin_region -region top:* -region bottom:* \ No newline at end of file +exclude_io_pin_region -region top:* -region bottom:* diff --git a/flow/designs/gf180/riscv32i/constraint.sdc b/flow/designs/gf180/riscv32i/constraint.sdc index 26f4484628..e38107b41f 100644 --- a/flow/designs/gf180/riscv32i/constraint.sdc +++ b/flow/designs/gf180/riscv32i/constraint.sdc @@ -1,6 +1,6 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 10.0 +set clk_period 10.0 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -8,5 +8,5 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl b/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl index c89b0808dd..15070643eb 100644 --- a/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl +++ b/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl @@ -18,7 +18,7 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} #################################### # standard cell grid #################################### -define_pdn_grid -name {block} -voltage_domains {CORE} +define_pdn_grid -name {block} -voltage_domains {CORE} add_pdn_stripe -grid {block} -layer {Metal1} -width {0.900} -pitch {5.040} -offset {0} -followpins add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} -offset {22.4} add_pdn_stripe -grid {block} -layer {Metal5} -width {4.480} -pitch {89.6} -offset {44.8} diff --git a/flow/designs/gf180/uart-blocks/constraint.sdc b/flow/designs/gf180/uart-blocks/constraint.sdc index e921f859f9..5c231242df 100644 --- a/flow/designs/gf180/uart-blocks/constraint.sdc +++ b/flow/designs/gf180/uart-blocks/constraint.sdc @@ -1,4 +1,4 @@ -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 6 set clk_io_pct 0.2 @@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/uart-blocks/tapcell.tcl b/flow/designs/gf180/uart-blocks/tapcell.tcl index b3d1bf1303..aa4a9daa9d 100644 --- a/flow/designs/gf180/uart-blocks/tapcell.tcl +++ b/flow/designs/gf180/uart-blocks/tapcell.tcl @@ -1,8 +1,7 @@ - tapcell \ - -endcap_cpp "12" \ - -distance 100 \ - -tapcell_master $::env(TIE_CELL) \ - -endcap_master $::env(ENDCAP_CELL) \ - -halo_width_x $::env(MACRO_ROWS_HALO_X) \ - -halo_width_y $::env(MACRO_ROWS_HALO_Y) - +tapcell \ + -endcap_cpp "12" \ + -distance 100 \ + -tapcell_master $::env(TIE_CELL) \ + -endcap_master $::env(ENDCAP_CELL) \ + -halo_width_x $::env(MACRO_ROWS_HALO_X) \ + -halo_width_y $::env(MACRO_ROWS_HALO_Y) diff --git a/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc b/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc index ffe2329cf5..5c231242df 100644 --- a/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc +++ b/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc @@ -1,6 +1,6 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 6 +set clk_period 6 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl b/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl index f5185790be..fce426a382 100644 --- a/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl +++ b/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl @@ -18,7 +18,7 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} #################################### # standard cell grid #################################### -define_pdn_grid -name {block} -voltage_domains {CORE} +define_pdn_grid -name {block} -voltage_domains {CORE} add_pdn_stripe -grid {block} -layer {Metal1} -width {0.900} -pitch {5.040} -offset {0} -followpins add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} -offset {22.4} add_pdn_connect -grid {block} -layers {Metal1 Metal4} diff --git a/flow/designs/ihp-sg13g2/aes/constraint.sdc b/flow/designs/ihp-sg13g2/aes/constraint.sdc index ec67329fda..f32c9be836 100644 --- a/flow/designs/ihp-sg13g2/aes/constraint.sdc +++ b/flow/designs/ihp-sg13g2/aes/constraint.sdc @@ -1,8 +1,8 @@ current_design aes_cipher_top -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 4.5 +set clk_period 4.5 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -11,6 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] - diff --git a/flow/designs/ihp-sg13g2/gcd/constraint.sdc b/flow/designs/ihp-sg13g2/gcd/constraint.sdc index 0e975c114d..20c0c7a73e 100644 --- a/flow/designs/ihp-sg13g2/gcd/constraint.sdc +++ b/flow/designs/ihp-sg13g2/gcd/constraint.sdc @@ -1,6 +1,6 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk set clk_period 2.6 set clk_io_pct 0.2 @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc b/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc index 02aff71773..7f9b71f07d 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc @@ -24,7 +24,7 @@ set clk_core_inout_16mA_ports [get_ports { io_gpio_5_PAD io_gpio_6_PAD io_gpio_7_PAD -}] +}] set_driving_cell -lib_cell sg13g2_IOPadInOut16mA -pin pad $clk_core_inout_16mA_ports set_input_delay 8 -clock clk_core $clk_core_inout_16mA_ports set_output_delay 8 -clock clk_core $clk_core_inout_16mA_ports @@ -32,7 +32,7 @@ set_output_delay 8 -clock clk_core $clk_core_inout_16mA_ports set clk_core_inout_4mA_ports [get_ports { io_i2c_scl_PAD io_i2c_sda_PAD -}] +}] set_driving_cell -lib_cell sg13g2_IOPadInOut4mA -pin pad $clk_core_inout_4mA_ports set_input_delay 8 -clock clk_core $clk_core_inout_4mA_ports set_output_delay 8 -clock clk_core $clk_core_inout_4mA_ports @@ -42,13 +42,13 @@ set clk_core_input_ports [get_ports { io_address_0_PAD io_address_1_PAD io_address_2_PAD -}] +}] set_driving_cell -lib_cell sg13g2_IOPadIn -pin pad $clk_core_input_ports set_input_delay 8 -clock clk_core $clk_core_input_ports set clk_core_output_4mA_ports [get_ports { io_i2c_interrupt_PAD -}] +}] set_driving_cell -lib_cell sg13g2_IOPadOut4mA -pin pad $clk_core_output_4mA_ports set_output_delay 8 -clock clk_core $clk_core_output_4mA_ports diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl index 0ec62dec93..2e2773ec98 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl @@ -2,46 +2,46 @@ set IO_LENGTH 180 set IO_WIDTH 80 set BONDPAD_SIZE 70 set SEALRING_OFFSET 70 -set IO_OFFSET [expr {$BONDPAD_SIZE + $SEALRING_OFFSET}] +set IO_OFFSET [expr { $BONDPAD_SIZE + $SEALRING_OFFSET }] -proc calc_horizontal_pad_location {index total} { - global IO_LENGTH - global IO_WIDTH - global BONDPAD_SIZE - global SEALRING_OFFSET +proc calc_horizontal_pad_location { index total } { + global IO_LENGTH + global IO_WIDTH + global BONDPAD_SIZE + global SEALRING_OFFSET - set DIE_WIDTH [expr {[lindex $::env(DIE_AREA) 2] - [lindex $::env(DIE_AREA) 0]}] - set PAD_OFFSET [expr {$IO_LENGTH + $BONDPAD_SIZE + $SEALRING_OFFSET}] - set PAD_AREA_WIDTH [expr {$DIE_WIDTH - ($PAD_OFFSET * 2)}] - set HORIZONTAL_PAD_DISTANCE [expr {($PAD_AREA_WIDTH / $total) - $IO_WIDTH}] + set DIE_WIDTH [expr { [lindex $::env(DIE_AREA) 2] - [lindex $::env(DIE_AREA) 0] }] + set PAD_OFFSET [expr { $IO_LENGTH + $BONDPAD_SIZE + $SEALRING_OFFSET }] + set PAD_AREA_WIDTH [expr { $DIE_WIDTH - ($PAD_OFFSET * 2) }] + set HORIZONTAL_PAD_DISTANCE [expr { ($PAD_AREA_WIDTH / $total) - $IO_WIDTH }] - return [expr {$PAD_OFFSET + (($IO_WIDTH + $HORIZONTAL_PAD_DISTANCE) * $index) + ($HORIZONTAL_PAD_DISTANCE / 2)}] + return [expr { $PAD_OFFSET + (($IO_WIDTH + $HORIZONTAL_PAD_DISTANCE) * $index) + ($HORIZONTAL_PAD_DISTANCE / 2) }] } -proc calc_vertical_pad_location {index total} { - global IO_LENGTH - global IO_WIDTH - global BONDPAD_SIZE - global SEALRING_OFFSET +proc calc_vertical_pad_location { index total } { + global IO_LENGTH + global IO_WIDTH + global BONDPAD_SIZE + global SEALRING_OFFSET - set DIE_HEIGHT [expr {[lindex $::env(DIE_AREA) 3] - [lindex $::env(DIE_AREA) 1]}] - set PAD_OFFSET [expr {$IO_LENGTH + $BONDPAD_SIZE + $SEALRING_OFFSET}] - set PAD_AREA_HEIGHT [expr {$DIE_HEIGHT - ($PAD_OFFSET * 2)}] - set VERTICAL_PAD_DISTANCE [expr {($PAD_AREA_HEIGHT / $total) - $IO_WIDTH}] + set DIE_HEIGHT [expr { [lindex $::env(DIE_AREA) 3] - [lindex $::env(DIE_AREA) 1] }] + set PAD_OFFSET [expr { $IO_LENGTH + $BONDPAD_SIZE + $SEALRING_OFFSET }] + set PAD_AREA_HEIGHT [expr { $DIE_HEIGHT - ($PAD_OFFSET * 2) }] + set VERTICAL_PAD_DISTANCE [expr { ($PAD_AREA_HEIGHT / $total) - $IO_WIDTH }] - return [expr {$PAD_OFFSET + (($IO_WIDTH + $VERTICAL_PAD_DISTANCE) * $index) + ($VERTICAL_PAD_DISTANCE / 2)}] + return [expr { $PAD_OFFSET + (($IO_WIDTH + $VERTICAL_PAD_DISTANCE) * $index) + ($VERTICAL_PAD_DISTANCE / 2) }] } make_fake_io_site -name IOLibSite -width 1 -height $IO_LENGTH make_fake_io_site -name IOLibCSite -width $IO_LENGTH -height $IO_LENGTH -set IO_OFFSET [expr {$BONDPAD_SIZE + $SEALRING_OFFSET}] +set IO_OFFSET [expr { $BONDPAD_SIZE + $SEALRING_OFFSET }] # Create IO Rows make_io_sites \ - -horizontal_site IOLibSite \ - -vertical_site IOLibSite \ - -corner_site IOLibCSite \ - -offset $IO_OFFSET + -horizontal_site IOLibSite \ + -vertical_site IOLibSite \ + -corner_site IOLibCSite \ + -offset $IO_OFFSET # Place Pads\n# IO pin io_clock place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 0 5] {sg13g2_IOPad_io_clock} -master sg13g2_IOPadIn diff --git a/flow/designs/ihp-sg13g2/ibex/constraint.sdc b/flow/designs/ihp-sg13g2/ibex/constraint.sdc index a4faf836eb..979e0b0b28 100644 --- a/flow/designs/ihp-sg13g2/ibex/constraint.sdc +++ b/flow/designs/ihp-sg13g2/ibex/constraint.sdc @@ -1,6 +1,6 @@ current_design ibex_core -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 10.0 set clk_io_pct 0.2 @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/ibex/constraint_doe.sdc b/flow/designs/ihp-sg13g2/ibex/constraint_doe.sdc index e169d10114..31ddde31d7 100644 --- a/flow/designs/ihp-sg13g2/ibex/constraint_doe.sdc +++ b/flow/designs/ihp-sg13g2/ibex/constraint_doe.sdc @@ -1,5 +1,5 @@ set uncertainty 1.0 -set io_delay 7.0 +set io_delay 7.0 set clock_port clk_i @@ -11,5 +11,5 @@ create_clock -name core_clock -period 15.0 -waveform {0.0000 7.5} [get_ports {cl set_clock_uncertainty $uncertainty [all_clocks] # -set_input_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_inputs] -set_output_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_outputs] +set_input_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_inputs] +set_output_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_outputs] diff --git a/flow/designs/ihp-sg13g2/jpeg/constraint.sdc b/flow/designs/ihp-sg13g2/jpeg/constraint.sdc index 879a3ef4b4..923cf1199f 100644 --- a/flow/designs/ihp-sg13g2/jpeg/constraint.sdc +++ b/flow/designs/ihp-sg13g2/jpeg/constraint.sdc @@ -1,8 +1,8 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 8.0 +set clk_period 8.0 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc b/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc index 72adf7e57f..5b0a6f1b4e 100644 --- a/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc +++ b/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc @@ -1,4 +1,4 @@ -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 6.0 set clk_io_pct 0.2 @@ -9,10 +9,10 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [list] foreach input [all_inputs] { - if {$clk_port != $input} { - lappend $non_clock_inputs $input - } + if { $clk_port != $input } { + lappend $non_clock_inputs $input + } } -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/spi/constraint.sdc b/flow/designs/ihp-sg13g2/spi/constraint.sdc index 5c7d8643e9..225f73938c 100644 --- a/flow/designs/ihp-sg13g2/spi/constraint.sdc +++ b/flow/designs/ihp-sg13g2/spi/constraint.sdc @@ -1,6 +1,6 @@ current_design spi -set clk_name core_clock +set clk_name core_clock set clk_port_name clk set clk_period 0.9 set clk_io_pct 0.2 @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/aes/constraint.sdc b/flow/designs/nangate45/aes/constraint.sdc index 6bf0879d5b..d7b8414c8e 100644 --- a/flow/designs/nangate45/aes/constraint.sdc +++ b/flow/designs/nangate45/aes/constraint.sdc @@ -1,8 +1,8 @@ current_design aes_cipher_top -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 0.82 +set clk_period 0.82 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/ariane136/constraint.sdc b/flow/designs/nangate45/ariane136/constraint.sdc index e0f4e320df..34dd047647 100644 --- a/flow/designs/nangate45/ariane136/constraint.sdc +++ b/flow/designs/nangate45/ariane136/constraint.sdc @@ -1,496 +1,496 @@ -create_clock [get_ports clk_i] -name core_clock -period 6 -waveform {0 3} -set_input_delay -clock core_clock 0 [get_ports clk_i] -set_input_delay -clock core_clock 0 [get_ports rst_ni] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[63]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[62]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[61]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[60]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[59]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[58]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[57]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[56]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[55]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[54]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[53]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[52]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[51]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[50]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[49]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[48]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[47]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[46]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[45]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[44]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[43]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[42]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[41]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[40]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[39]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[38]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[37]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[36]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[35]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[34]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[33]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[32]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[31]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[30]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[29]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[28]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[27]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[26]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[25]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[24]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[23]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[22]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[21]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[20]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[19]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[18]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[17]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[16]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[15]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[14]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[13]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[12]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[11]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[10]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[9]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[8]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[7]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[6]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[5]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[4]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[3]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[2]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[1]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[0]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[63]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[62]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[61]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[60]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[59]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[58]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[57]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[56]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[55]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[54]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[53]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[52]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[51]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[50]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[49]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[48]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[47]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[46]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[45]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[44]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[43]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[42]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[41]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[40]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[39]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[38]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[37]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[36]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[35]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[34]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[33]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[32]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[31]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[30]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[29]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[28]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[27]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[26]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[25]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[24]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[23]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[22]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[21]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[20]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[19]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[18]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[17]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[16]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[15]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[14]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[13]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[12]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[11]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[10]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[9]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[8]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[7]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[6]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[5]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[4]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[3]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[2]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[1]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[0]}] -set_input_delay -clock core_clock 0 [get_ports {irq_i[1]}] -set_input_delay -clock core_clock 0 [get_ports {irq_i[0]}] -set_input_delay -clock core_clock 0 [get_ports ipi_i] -set_input_delay -clock core_clock 0 [get_ports time_irq_i] -set_input_delay -clock core_clock 0 [get_ports debug_req_i] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[81]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[80]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[79]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[78]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[77]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[76]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[75]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[74]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[73]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[72]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[71]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[70]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[69]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[68]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[67]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[66]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[65]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[64]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[63]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[62]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[61]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[60]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[59]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[58]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[57]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[56]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[55]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[54]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[53]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[52]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[51]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[50]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[49]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[48]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[47]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[46]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[45]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[44]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[43]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[42]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[41]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[40]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[39]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[38]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[37]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[36]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[35]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[34]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[33]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[32]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[31]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[30]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[29]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[28]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[27]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[26]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[25]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[24]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[23]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[22]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[21]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[20]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[19]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[18]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[17]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[16]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[15]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[14]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[13]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[12]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[11]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[10]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[9]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[8]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[7]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[6]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[5]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[4]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[3]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[2]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[1]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[0]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[277]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[276]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[275]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[274]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[273]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[272]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[271]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[270]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[269]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[268]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[267]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[266]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[265]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[264]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[263]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[262]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[261]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[260]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[259]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[258]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[257]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[256]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[255]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[254]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[253]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[252]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[251]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[250]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[249]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[248]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[247]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[246]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[245]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[244]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[243]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[242]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[241]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[240]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[239]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[238]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[237]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[236]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[235]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[234]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[233]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[232]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[231]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[230]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[229]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[228]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[227]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[226]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[225]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[224]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[223]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[222]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[221]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[220]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[219]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[218]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[217]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[216]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[215]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[214]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[213]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[212]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[211]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[210]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[209]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[208]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[207]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[206]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[205]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[204]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[203]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[202]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[201]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[200]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[199]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[198]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[197]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[196]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[195]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[194]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[193]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[192]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[191]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[190]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[189]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[188]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[187]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[186]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[185]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[184]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[183]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[182]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[181]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[180]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[179]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[178]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[177]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[176]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[175]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[174]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[173]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[172]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[171]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[170]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[169]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[168]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[167]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[166]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[165]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[164]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[163]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[162]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[161]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[160]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[159]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[158]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[157]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[156]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[155]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[154]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[153]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[152]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[151]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[150]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[149]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[148]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[147]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[146]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[145]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[144]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[143]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[142]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[141]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[140]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[139]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[138]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[137]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[136]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[135]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[134]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[133]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[132]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[131]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[130]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[129]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[128]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[127]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[126]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[125]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[124]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[123]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[122]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[121]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[120]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[119]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[118]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[117]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[116]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[115]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[114]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[113]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[112]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[111]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[110]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[109]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[108]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[107]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[106]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[105]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[104]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[103]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[102]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[101]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[100]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[99]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[98]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[97]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[96]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[95]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[94]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[93]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[92]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[91]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[90]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[89]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[88]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[87]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[86]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[85]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[84]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[83]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[82]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[81]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[80]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[79]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[78]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[77]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[76]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[75]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[74]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[73]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[72]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[71]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[70]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[69]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[68]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[67]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[66]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[65]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[64]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[63]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[62]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[61]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[60]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[59]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[58]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[57]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[56]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[55]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[54]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[53]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[52]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[51]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[50]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[49]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[48]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[47]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[46]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[45]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[44]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[43]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[42]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[41]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[40]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[39]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[38]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[37]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[36]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[35]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[34]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[33]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[32]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[31]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[30]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[29]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[28]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[27]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[26]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[25]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[24]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[23]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[22]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[21]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[20]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[19]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[18]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[17]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[16]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[15]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[14]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[13]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[12]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[11]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[10]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[9]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[8]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[7]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[6]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[5]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[4]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[3]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[2]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[1]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[0]}] +create_clock [get_ports clk_i] -name core_clock -period 6 -waveform {0 3} +set_input_delay -clock core_clock 0 [get_ports clk_i] +set_input_delay -clock core_clock 0 [get_ports rst_ni] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[63]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[62]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[61]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[60]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[59]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[58]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[57]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[56]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[55]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[54]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[53]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[52]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[51]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[50]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[49]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[48]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[47]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[46]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[45]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[44]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[43]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[42]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[41]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[40]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[39]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[38]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[37]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[36]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[35]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[34]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[33]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[32]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[31]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[30]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[29]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[28]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[27]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[26]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[25]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[24]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[23]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[22]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[21]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[20]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[19]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[18]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[17]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[16]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[15]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[14]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[13]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[12]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[11]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[10]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[9]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[8]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[7]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[6]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[5]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[4]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[3]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[2]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[1]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[0]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[63]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[62]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[61]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[60]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[59]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[58]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[57]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[56]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[55]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[54]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[53]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[52]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[51]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[50]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[49]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[48]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[47]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[46]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[45]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[44]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[43]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[42]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[41]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[40]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[39]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[38]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[37]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[36]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[35]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[34]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[33]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[32]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[31]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[30]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[29]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[28]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[27]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[26]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[25]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[24]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[23]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[22]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[21]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[20]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[19]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[18]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[17]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[16]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[15]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[14]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[13]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[12]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[11]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[10]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[9]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[8]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[7]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[6]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[5]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[4]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[3]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[2]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[1]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[0]}] +set_input_delay -clock core_clock 0 [get_ports {irq_i[1]}] +set_input_delay -clock core_clock 0 [get_ports {irq_i[0]}] +set_input_delay -clock core_clock 0 [get_ports ipi_i] +set_input_delay -clock core_clock 0 [get_ports time_irq_i] +set_input_delay -clock core_clock 0 [get_ports debug_req_i] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[81]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[80]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[79]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[78]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[77]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[76]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[75]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[74]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[73]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[72]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[71]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[70]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[69]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[68]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[67]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[66]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[65]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[64]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[63]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[62]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[61]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[60]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[59]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[58]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[57]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[56]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[55]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[54]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[53]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[52]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[51]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[50]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[49]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[48]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[47]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[46]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[45]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[44]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[43]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[42]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[41]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[40]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[39]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[38]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[37]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[36]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[35]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[34]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[33]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[32]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[31]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[30]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[29]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[28]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[27]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[26]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[25]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[24]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[23]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[22]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[21]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[20]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[19]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[18]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[17]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[16]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[15]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[14]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[13]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[12]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[11]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[10]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[9]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[8]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[7]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[6]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[5]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[4]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[3]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[2]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[1]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[0]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[277]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[276]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[275]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[274]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[273]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[272]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[271]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[270]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[269]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[268]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[267]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[266]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[265]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[264]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[263]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[262]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[261]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[260]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[259]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[258]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[257]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[256]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[255]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[254]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[253]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[252]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[251]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[250]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[249]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[248]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[247]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[246]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[245]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[244]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[243]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[242]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[241]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[240]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[239]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[238]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[237]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[236]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[235]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[234]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[233]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[232]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[231]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[230]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[229]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[228]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[227]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[226]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[225]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[224]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[223]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[222]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[221]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[220]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[219]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[218]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[217]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[216]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[215]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[214]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[213]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[212]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[211]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[210]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[209]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[208]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[207]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[206]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[205]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[204]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[203]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[202]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[201]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[200]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[199]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[198]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[197]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[196]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[195]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[194]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[193]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[192]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[191]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[190]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[189]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[188]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[187]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[186]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[185]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[184]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[183]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[182]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[181]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[180]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[179]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[178]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[177]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[176]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[175]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[174]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[173]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[172]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[171]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[170]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[169]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[168]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[167]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[166]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[165]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[164]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[163]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[162]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[161]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[160]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[159]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[158]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[157]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[156]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[155]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[154]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[153]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[152]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[151]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[150]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[149]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[148]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[147]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[146]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[145]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[144]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[143]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[142]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[141]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[140]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[139]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[138]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[137]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[136]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[135]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[134]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[133]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[132]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[131]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[130]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[129]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[128]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[127]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[126]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[125]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[124]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[123]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[122]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[121]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[120]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[119]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[118]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[117]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[116]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[115]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[114]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[113]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[112]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[111]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[110]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[109]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[108]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[107]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[106]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[105]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[104]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[103]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[102]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[101]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[100]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[99]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[98]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[97]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[96]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[95]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[94]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[93]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[92]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[91]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[90]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[89]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[88]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[87]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[86]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[85]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[84]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[83]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[82]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[81]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[80]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[79]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[78]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[77]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[76]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[75]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[74]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[73]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[72]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[71]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[70]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[69]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[68]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[67]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[66]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[65]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[64]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[63]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[62]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[61]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[60]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[59]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[58]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[57]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[56]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[55]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[54]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[53]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[52]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[51]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[50]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[49]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[48]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[47]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[46]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[45]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[44]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[43]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[42]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[41]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[40]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[39]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[38]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[37]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[36]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[35]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[34]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[33]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[32]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[31]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[30]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[29]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[28]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[27]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[26]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[25]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[24]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[23]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[22]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[21]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[20]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[19]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[18]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[17]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[16]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[15]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[14]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[13]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[12]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[11]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[10]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[9]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[8]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[7]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[6]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[5]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[4]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[3]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[2]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[1]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[0]}] diff --git a/flow/designs/nangate45/black_parrot/constraint.sdc b/flow/designs/nangate45/black_parrot/constraint.sdc index d6a53ebbd8..a5514ffe49 100644 --- a/flow/designs/nangate45/black_parrot/constraint.sdc +++ b/flow/designs/nangate45/black_parrot/constraint.sdc @@ -1,4 +1,4 @@ -set clk_name CLK +set clk_name CLK set clk_port_name clk_i set clk_period 6.0 set clk_io_pct 0.2 @@ -9,2397 +9,2397 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set_input_delay -clock CLK -max 3.42 [get_ports reset_i] -set_input_delay -clock CLK -min $min_arrival [get_ports reset_i] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_cmd_yumi_i[0]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_yumi_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_yumi_i[0]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_yumi_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[54]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[54]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[53]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[53]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[52]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[52]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[51]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[51]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[50]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[50]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[49]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[49]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[48]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[48]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[47]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[47]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[46]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[46]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[45]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[45]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[44]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[44]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[43]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[43]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[42]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[42]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[41]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[41]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[40]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[40]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[39]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[39]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[38]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[38]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[37]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[37]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[36]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[36]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[35]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[35]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[34]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[34]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[33]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[33]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[32]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[32]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[31]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[31]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[30]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[30]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[29]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[29]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[28]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[28]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[27]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[27]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[26]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[26]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[25]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[25]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[24]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[24]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[23]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[23]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[22]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[22]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[21]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[21]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[20]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[20]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[19]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[19]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[18]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[18]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[17]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[17]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[16]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[16]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[15]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[15]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[14]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[14]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[13]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[13]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[12]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[12]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[11]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[11]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[10]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[10]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[9]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[9]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[8]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[8]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[7]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[7]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[6]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[6]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[5]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[5]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[4]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[4]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[3]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[3]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[2]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[2]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[1]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[1]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[0]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_v_i[0]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_v_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[538]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[538]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[537]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[537]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[536]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[536]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[535]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[535]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[534]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[534]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[533]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[533]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[532]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[532]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[531]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[531]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[530]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[530]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[529]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[529]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[528]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[528]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[527]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[527]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[526]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[526]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[525]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[525]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[524]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[524]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[523]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[523]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[522]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[522]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[521]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[521]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[520]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[520]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[519]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[519]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[518]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[518]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[517]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[517]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[516]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[516]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[515]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[515]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[514]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[514]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[513]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[513]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[512]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[512]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[511]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[511]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[510]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[510]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[509]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[509]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[508]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[508]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[507]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[507]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[506]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[506]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[505]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[505]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[504]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[504]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[503]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[503]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[502]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[502]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[501]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[501]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[500]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[500]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[499]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[499]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[498]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[498]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[497]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[497]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[496]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[496]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[495]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[495]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[494]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[494]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[493]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[493]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[492]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[492]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[491]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[491]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[490]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[490]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[489]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[489]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[488]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[488]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[487]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[487]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[486]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[486]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[485]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[485]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[484]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[484]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[483]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[483]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[482]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[482]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[481]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[481]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[480]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[480]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[479]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[479]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[478]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[478]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[477]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[477]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[476]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[476]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[475]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[475]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[474]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[474]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[473]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[473]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[472]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[472]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[471]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[471]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[470]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[470]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[469]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[469]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[468]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[468]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[467]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[467]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[466]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[466]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[465]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[465]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[464]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[464]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[463]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[463]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[462]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[462]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[461]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[461]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[460]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[460]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[459]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[459]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[458]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[458]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[457]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[457]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[456]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[456]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[455]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[455]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[454]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[454]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[453]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[453]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[452]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[452]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[451]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[451]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[450]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[450]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[449]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[449]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[448]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[448]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[447]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[447]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[446]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[446]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[445]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[445]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[444]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[444]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[443]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[443]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[442]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[442]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[441]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[441]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[440]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[440]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[439]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[439]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[438]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[438]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[437]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[437]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[436]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[436]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[435]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[435]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[434]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[434]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[433]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[433]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[432]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[432]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[431]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[431]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[430]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[430]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[429]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[429]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[428]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[428]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[427]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[427]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[426]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[426]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[425]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[425]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[424]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[424]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[423]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[423]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[422]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[422]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[421]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[421]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[420]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[420]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[419]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[419]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[418]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[418]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[417]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[417]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[416]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[416]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[415]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[415]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[414]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[414]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[413]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[413]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[412]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[412]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[411]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[411]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[410]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[410]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[409]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[409]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[408]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[408]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[407]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[407]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[406]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[406]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[405]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[405]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[404]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[404]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[403]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[403]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[402]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[402]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[401]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[401]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[400]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[400]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[399]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[399]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[398]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[398]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[397]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[397]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[396]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[396]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[395]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[395]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[394]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[394]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[393]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[393]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[392]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[392]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[391]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[391]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[390]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[390]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[389]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[389]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[388]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[388]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[387]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[387]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[386]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[386]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[385]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[385]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[384]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[384]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[383]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[383]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[382]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[382]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[381]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[381]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[380]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[380]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[379]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[379]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[378]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[378]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[377]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[377]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[376]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[376]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[375]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[375]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[374]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[374]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[373]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[373]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[372]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[372]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[371]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[371]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[370]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[370]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[369]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[369]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[368]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[368]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[367]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[367]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[366]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[366]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[365]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[365]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[364]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[364]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[363]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[363]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[362]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[362]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[361]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[361]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[360]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[360]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[359]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[359]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[358]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[358]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[357]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[357]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[356]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[356]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[355]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[355]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[354]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[354]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[353]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[353]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[352]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[352]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[351]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[351]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[350]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[350]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[349]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[349]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[348]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[348]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[347]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[347]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[346]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[346]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[345]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[345]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[344]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[344]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[343]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[343]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[342]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[342]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[341]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[341]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[340]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[340]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[339]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[339]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[338]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[338]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[337]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[337]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[336]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[336]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[335]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[335]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[334]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[334]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[333]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[333]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[332]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[332]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[331]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[331]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[330]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[330]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[329]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[329]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[328]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[328]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[327]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[327]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[326]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[326]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[325]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[325]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[324]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[324]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[323]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[323]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[322]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[322]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[321]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[321]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[320]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[320]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[319]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[319]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[318]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[318]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[317]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[317]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[316]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[316]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[315]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[315]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[314]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[314]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[313]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[313]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[312]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[312]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[311]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[311]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[310]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[310]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[309]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[309]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[308]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[308]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[307]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[307]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[306]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[306]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[305]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[305]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[304]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[304]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[303]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[303]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[302]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[302]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[301]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[301]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[300]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[300]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[299]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[299]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[298]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[298]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[297]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[297]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[296]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[296]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[295]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[295]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[294]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[294]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[293]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[293]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[292]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[292]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[291]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[291]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[290]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[290]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[289]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[289]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[288]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[288]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[287]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[287]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[286]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[286]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[285]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[285]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[284]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[284]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[283]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[283]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[282]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[282]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[281]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[281]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[280]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[280]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[279]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[279]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[278]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[278]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[277]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[277]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[276]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[276]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[275]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[275]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[274]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[274]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[273]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[273]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[272]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[272]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[271]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[271]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[270]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[270]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[269]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[269]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[268]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[268]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[267]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[267]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[266]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[266]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[265]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[265]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[264]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[264]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[263]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[263]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[262]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[262]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[261]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[261]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[260]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[260]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[259]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[259]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[258]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[258]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[257]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[257]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[256]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[256]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[255]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[255]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[254]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[254]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[253]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[253]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[252]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[252]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[251]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[251]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[250]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[250]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[249]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[249]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[248]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[248]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[247]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[247]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[246]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[246]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[245]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[245]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[244]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[244]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[243]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[243]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[242]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[242]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[241]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[241]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[240]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[240]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[239]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[239]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[238]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[238]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[237]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[237]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[236]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[236]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[235]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[235]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[234]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[234]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[233]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[233]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[232]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[232]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[231]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[231]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[230]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[230]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[229]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[229]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[228]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[228]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[227]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[227]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[226]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[226]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[225]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[225]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[224]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[224]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[223]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[223]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[222]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[222]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[221]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[221]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[220]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[220]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[219]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[219]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[218]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[218]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[217]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[217]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[216]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[216]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[215]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[215]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[214]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[214]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[213]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[213]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[212]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[212]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[211]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[211]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[210]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[210]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[209]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[209]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[208]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[208]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[207]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[207]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[206]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[206]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[205]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[205]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[204]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[204]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[203]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[203]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[202]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[202]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[201]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[201]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[200]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[200]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[199]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[199]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[198]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[198]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[197]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[197]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[196]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[196]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[195]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[195]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[194]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[194]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[193]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[193]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[192]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[192]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[191]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[191]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[190]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[190]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[189]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[189]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[188]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[188]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[187]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[187]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[186]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[186]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[185]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[185]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[184]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[184]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[183]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[183]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[182]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[182]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[181]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[181]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[180]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[180]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[179]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[179]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[178]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[178]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[177]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[177]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[176]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[176]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[175]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[175]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[174]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[174]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[173]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[173]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[172]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[172]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[171]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[171]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[170]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[170]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[169]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[169]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[168]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[168]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[167]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[167]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[166]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[166]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[165]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[165]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[164]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[164]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[163]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[163]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[162]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[162]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[161]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[161]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[160]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[160]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[159]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[159]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[158]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[158]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[157]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[157]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[156]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[156]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[155]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[155]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[154]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[154]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[153]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[153]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[152]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[152]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[151]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[151]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[150]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[150]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[149]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[149]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[148]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[148]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[147]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[147]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[146]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[146]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[145]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[145]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[144]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[144]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[143]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[143]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[142]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[142]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[141]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[141]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[140]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[140]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[139]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[139]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[138]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[138]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[137]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[137]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[136]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[136]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[135]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[135]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[134]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[134]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[133]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[133]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[132]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[132]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[131]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[131]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[130]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[130]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[129]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[129]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[128]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[128]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[127]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[127]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[126]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[126]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[125]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[125]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[124]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[124]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[123]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[123]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[122]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[122]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[121]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[121]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[120]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[120]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[119]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[119]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[118]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[118]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[117]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[117]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[116]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[116]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[115]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[115]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[114]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[114]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[113]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[113]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[112]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[112]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[111]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[111]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[110]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[110]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[109]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[109]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[108]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[108]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[107]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[107]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[106]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[106]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[105]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[105]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[104]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[104]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[103]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[103]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[102]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[102]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[101]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[101]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[100]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[100]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[99]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[99]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[98]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[98]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[97]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[97]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[96]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[96]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[95]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[95]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[94]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[94]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[93]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[93]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[92]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[92]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[91]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[91]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[90]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[90]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[89]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[89]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[88]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[88]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[87]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[87]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[86]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[86]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[85]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[85]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[84]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[84]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[83]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[83]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[82]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[82]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[81]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[81]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[80]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[80]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[79]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[79]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[78]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[78]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[77]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[77]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[76]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[76]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[75]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[75]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[74]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[74]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[73]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[73]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[72]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[72]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[71]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[71]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[70]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[70]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[69]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[69]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[68]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[68]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[67]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[67]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[66]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[66]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[65]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[65]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[64]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[64]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[63]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[63]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[62]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[62]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[61]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[61]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[60]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[60]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[59]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[59]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[58]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[58]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[57]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[57]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[56]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[56]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[55]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[55]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[54]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[54]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[53]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[53]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[52]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[52]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[51]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[51]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[50]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[50]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[49]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[49]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[48]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[48]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[47]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[47]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[46]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[46]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[45]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[45]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[44]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[44]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[43]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[43]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[42]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[42]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[41]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[41]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[40]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[40]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[39]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[39]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[38]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[38]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[37]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[37]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[36]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[36]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[35]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[35]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[34]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[34]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[33]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[33]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[32]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[32]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[31]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[31]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[30]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[30]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[29]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[29]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[28]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[28]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[27]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[27]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[26]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[26]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[25]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[25]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[24]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[24]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[23]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[23]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[22]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[22]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[21]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[21]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[20]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[20]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[19]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[19]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[18]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[18]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[17]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[17]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[16]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[16]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[15]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[15]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[14]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[14]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[13]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[13]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[12]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[12]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[11]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[11]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[10]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[10]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[9]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[9]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[8]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[8]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[7]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[7]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[6]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[6]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[5]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[5]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[4]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[4]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[3]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[3]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[2]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[2]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[1]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[1]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[0]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_v_i[0]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_v_i[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[26]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[26]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[25]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[25]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[24]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[24]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[23]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[23]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[22]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[22]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[21]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[21]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[20]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[20]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[19]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[19]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[18]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[18]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[17]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[17]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[16]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[16]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[15]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[15]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[14]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[14]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[13]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[13]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[12]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[12]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[11]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[11]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[10]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[10]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[9]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[9]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[8]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[8]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[7]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[7]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[6]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[6]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[5]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[5]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[4]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[4]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[3]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[3]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[2]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[2]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[1]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[1]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[0]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_v_o[0]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_v_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[566]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[566]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[565]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[565]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[564]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[564]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[563]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[563]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[562]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[562]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[561]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[561]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[560]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[560]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[559]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[559]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[558]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[558]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[557]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[557]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[556]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[556]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[555]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[555]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[554]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[554]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[553]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[553]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[552]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[552]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[551]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[551]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[550]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[550]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[549]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[549]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[548]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[548]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[547]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[547]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[546]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[546]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[545]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[545]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[544]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[544]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[543]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[543]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[542]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[542]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[541]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[541]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[540]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[540]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[539]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[539]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[538]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[538]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[537]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[537]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[536]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[536]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[535]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[535]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[534]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[534]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[533]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[533]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[532]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[532]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[531]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[531]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[530]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[530]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[529]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[529]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[528]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[528]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[527]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[527]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[526]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[526]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[525]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[525]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[524]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[524]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[523]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[523]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[522]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[522]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[521]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[521]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[520]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[520]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[519]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[519]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[518]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[518]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[517]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[517]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[516]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[516]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[515]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[515]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[514]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[514]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[513]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[513]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[512]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[512]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[511]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[511]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[510]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[510]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[509]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[509]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[508]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[508]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[507]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[507]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[506]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[506]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[505]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[505]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[504]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[504]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[503]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[503]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[502]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[502]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[501]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[501]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[500]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[500]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[499]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[499]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[498]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[498]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[497]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[497]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[496]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[496]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[495]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[495]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[494]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[494]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[493]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[493]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[492]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[492]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[491]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[491]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[490]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[490]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[489]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[489]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[488]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[488]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[487]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[487]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[486]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[486]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[485]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[485]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[484]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[484]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[483]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[483]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[482]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[482]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[481]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[481]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[480]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[480]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[479]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[479]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[478]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[478]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[477]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[477]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[476]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[476]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[475]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[475]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[474]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[474]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[473]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[473]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[472]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[472]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[471]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[471]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[470]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[470]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[469]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[469]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[468]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[468]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[467]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[467]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[466]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[466]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[465]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[465]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[464]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[464]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[463]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[463]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[462]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[462]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[461]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[461]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[460]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[460]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[459]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[459]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[458]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[458]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[457]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[457]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[456]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[456]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[455]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[455]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[454]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[454]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[453]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[453]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[452]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[452]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[451]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[451]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[450]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[450]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[449]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[449]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[448]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[448]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[447]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[447]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[446]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[446]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[445]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[445]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[444]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[444]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[443]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[443]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[442]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[442]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[441]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[441]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[440]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[440]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[439]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[439]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[438]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[438]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[437]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[437]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[436]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[436]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[435]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[435]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[434]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[434]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[433]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[433]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[432]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[432]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[431]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[431]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[430]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[430]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[429]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[429]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[428]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[428]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[427]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[427]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[426]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[426]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[425]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[425]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[424]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[424]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[423]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[423]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[422]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[422]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[421]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[421]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[420]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[420]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[419]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[419]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[418]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[418]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[417]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[417]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[416]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[416]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[415]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[415]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[414]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[414]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[413]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[413]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[412]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[412]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[411]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[411]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[410]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[410]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[409]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[409]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[408]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[408]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[407]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[407]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[406]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[406]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[405]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[405]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[404]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[404]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[403]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[403]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[402]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[402]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[401]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[401]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[400]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[400]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[399]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[399]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[398]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[398]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[397]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[397]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[396]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[396]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[395]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[395]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[394]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[394]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[393]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[393]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[392]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[392]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[391]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[391]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[390]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[390]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[389]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[389]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[388]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[388]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[387]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[387]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[386]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[386]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[385]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[385]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[384]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[384]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[383]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[383]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[382]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[382]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[381]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[381]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[380]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[380]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[379]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[379]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[378]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[378]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[377]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[377]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[376]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[376]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[375]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[375]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[374]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[374]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[373]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[373]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[372]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[372]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[371]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[371]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[370]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[370]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[369]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[369]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[368]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[368]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[367]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[367]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[366]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[366]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[365]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[365]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[364]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[364]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[363]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[363]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[362]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[362]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[361]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[361]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[360]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[360]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[359]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[359]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[358]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[358]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[357]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[357]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[356]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[356]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[355]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[355]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[354]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[354]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[353]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[353]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[352]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[352]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[351]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[351]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[350]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[350]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[349]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[349]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[348]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[348]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[347]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[347]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[346]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[346]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[345]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[345]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[344]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[344]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[343]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[343]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[342]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[342]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[341]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[341]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[340]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[340]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[339]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[339]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[338]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[338]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[337]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[337]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[336]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[336]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[335]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[335]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[334]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[334]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[333]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[333]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[332]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[332]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[331]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[331]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[330]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[330]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[329]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[329]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[328]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[328]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[327]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[327]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[326]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[326]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[325]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[325]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[324]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[324]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[323]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[323]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[322]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[322]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[321]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[321]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[320]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[320]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[319]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[319]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[318]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[318]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[317]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[317]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[316]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[316]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[315]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[315]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[314]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[314]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[313]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[313]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[312]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[312]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[311]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[311]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[310]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[310]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[309]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[309]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[308]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[308]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[307]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[307]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[306]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[306]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[305]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[305]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[304]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[304]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[303]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[303]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[302]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[302]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[301]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[301]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[300]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[300]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[299]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[299]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[298]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[298]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[297]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[297]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[296]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[296]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[295]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[295]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[294]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[294]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[293]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[293]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[292]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[292]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[291]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[291]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[290]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[290]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[289]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[289]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[288]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[288]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[287]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[287]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[286]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[286]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[285]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[285]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[284]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[284]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[283]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[283]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[282]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[282]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[281]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[281]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[280]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[280]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[279]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[279]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[278]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[278]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[277]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[277]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[276]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[276]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[275]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[275]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[274]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[274]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[273]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[273]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[272]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[272]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[271]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[271]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[270]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[270]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[269]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[269]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[268]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[268]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[267]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[267]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[266]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[266]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[265]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[265]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[264]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[264]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[263]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[263]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[262]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[262]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[261]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[261]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[260]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[260]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[259]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[259]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[258]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[258]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[257]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[257]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[256]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[256]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[255]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[255]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[254]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[254]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[253]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[253]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[252]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[252]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[251]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[251]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[250]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[250]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[249]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[249]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[248]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[248]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[247]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[247]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[246]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[246]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[245]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[245]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[244]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[244]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[243]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[243]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[242]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[242]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[241]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[241]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[240]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[240]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[239]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[239]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[238]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[238]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[237]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[237]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[236]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[236]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[235]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[235]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[234]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[234]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[233]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[233]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[232]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[232]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[231]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[231]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[230]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[230]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[229]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[229]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[228]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[228]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[227]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[227]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[226]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[226]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[225]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[225]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[224]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[224]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[223]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[223]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[222]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[222]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[221]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[221]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[220]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[220]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[219]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[219]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[218]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[218]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[217]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[217]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[216]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[216]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[215]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[215]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[214]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[214]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[213]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[213]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[212]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[212]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[211]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[211]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[210]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[210]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[209]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[209]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[208]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[208]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[207]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[207]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[206]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[206]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[205]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[205]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[204]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[204]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[203]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[203]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[202]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[202]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[201]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[201]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[200]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[200]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[199]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[199]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[198]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[198]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[197]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[197]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[196]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[196]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[195]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[195]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[194]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[194]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[193]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[193]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[192]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[192]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[191]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[191]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[190]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[190]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[189]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[189]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[188]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[188]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[187]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[187]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[186]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[186]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[185]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[185]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[184]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[184]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[183]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[183]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[182]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[182]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[181]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[181]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[180]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[180]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[179]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[179]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[178]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[178]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[177]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[177]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[176]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[176]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[175]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[175]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[174]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[174]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[173]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[173]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[172]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[172]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[171]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[171]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[170]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[170]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[169]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[169]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[168]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[168]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[167]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[167]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[166]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[166]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[165]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[165]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[164]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[164]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[163]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[163]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[162]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[162]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[161]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[161]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[160]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[160]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[159]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[159]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[158]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[158]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[157]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[157]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[156]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[156]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[155]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[155]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[154]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[154]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[153]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[153]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[152]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[152]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[151]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[151]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[150]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[150]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[149]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[149]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[148]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[148]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[147]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[147]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[146]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[146]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[145]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[145]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[144]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[144]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[143]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[143]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[142]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[142]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[141]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[141]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[140]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[140]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[139]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[139]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[138]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[138]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[137]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[137]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[136]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[136]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[135]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[135]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[134]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[134]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[133]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[133]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[132]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[132]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[131]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[131]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[130]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[130]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[129]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[129]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[128]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[128]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[127]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[127]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[126]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[126]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[125]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[125]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[124]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[124]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[123]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[123]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[122]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[122]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[121]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[121]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[120]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[120]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[119]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[119]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[118]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[118]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[117]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[117]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[116]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[116]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[115]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[115]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[114]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[114]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[113]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[113]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[112]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[112]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[111]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[111]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[110]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[110]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[109]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[109]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[108]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[108]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[107]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[107]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[106]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[106]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[105]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[105]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[104]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[104]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[103]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[103]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[102]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[102]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[101]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[101]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[100]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[100]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[99]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[99]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[98]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[98]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[97]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[97]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[96]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[96]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[95]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[95]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[94]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[94]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[93]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[93]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[92]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[92]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[91]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[91]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[90]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[90]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[89]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[89]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[88]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[88]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[87]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[87]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[86]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[86]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[85]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[85]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[84]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[84]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[83]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[83]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[82]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[82]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[81]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[81]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[80]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[80]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[79]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[79]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[78]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[78]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[77]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[77]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[76]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[76]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[75]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[75]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[74]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[74]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[73]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[73]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[72]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[72]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[71]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[71]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[70]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[70]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[69]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[69]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[68]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[68]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[67]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[67]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[66]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[66]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[65]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[65]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[64]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[64]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[63]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[63]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[62]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[62]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[61]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[61]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[60]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[60]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[59]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[59]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[58]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[58]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[57]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[57]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[56]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[56]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[55]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[55]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[54]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[54]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[53]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[53]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[52]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[52]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[51]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[51]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[50]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[50]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[49]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[49]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[48]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[48]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[47]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[47]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[46]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[46]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[45]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[45]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[44]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[44]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[43]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[43]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[42]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[42]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[41]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[41]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[40]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[40]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[39]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[39]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[38]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[38]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[37]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[37]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[36]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[36]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[35]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[35]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[34]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[34]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[33]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[33]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[32]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[32]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[31]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[31]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[30]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[30]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[29]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[29]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[28]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[28]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[27]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[27]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[26]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[26]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[25]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[25]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[24]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[24]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[23]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[23]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[22]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[22]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[21]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[21]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[20]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[20]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[19]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[19]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[18]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[18]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[17]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[17]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[16]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[16]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[15]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[15]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[14]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[14]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[13]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[13]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[12]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[12]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[11]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[11]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[10]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[10]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[9]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[9]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[8]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[8]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[7]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[7]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[6]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[6]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[5]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[5]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[4]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[4]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[3]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[3]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[2]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[2]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[1]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[1]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[0]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_v_o[0]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_v_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_resp_ready_o[0]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_resp_ready_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_ready_o[0]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_ready_o[0]}] +set_input_delay -clock CLK -max 3.42 [get_ports reset_i] +set_input_delay -clock CLK -min $min_arrival [get_ports reset_i] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_cmd_yumi_i[0]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_yumi_i[0]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_yumi_i[0]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_yumi_i[0]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[54]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[54]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[53]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[53]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[52]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[52]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[51]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[51]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[50]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[50]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[49]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[49]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[48]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[48]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[47]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[47]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[46]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[46]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[45]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[45]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[44]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[44]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[43]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[43]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[42]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[42]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[41]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[41]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[40]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[40]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[39]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[39]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[38]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[38]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[37]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[37]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[36]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[36]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[35]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[35]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[34]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[34]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[33]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[33]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[32]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[32]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[31]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[31]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[30]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[30]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[29]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[29]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[28]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[28]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[27]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[27]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[26]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[26]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[25]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[25]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[24]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[24]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[23]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[23]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[22]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[22]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[21]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[21]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[20]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[20]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[19]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[19]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[18]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[18]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[17]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[17]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[16]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[16]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[15]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[15]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[14]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[14]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[13]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[13]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[12]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[12]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[11]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[11]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[10]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[10]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[9]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[9]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[8]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[8]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[7]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[7]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[6]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[6]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[5]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[5]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[4]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[4]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[3]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[3]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[2]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[2]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[1]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[1]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[0]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[0]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_v_i[0]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_v_i[0]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[538]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[538]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[537]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[537]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[536]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[536]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[535]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[535]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[534]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[534]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[533]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[533]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[532]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[532]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[531]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[531]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[530]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[530]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[529]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[529]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[528]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[528]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[527]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[527]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[526]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[526]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[525]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[525]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[524]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[524]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[523]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[523]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[522]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[522]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[521]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[521]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[520]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[520]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[519]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[519]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[518]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[518]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[517]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[517]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[516]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[516]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[515]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[515]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[514]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[514]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[513]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[513]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[512]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[512]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[511]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[511]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[510]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[510]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[509]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[509]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[508]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[508]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[507]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[507]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[506]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[506]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[505]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[505]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[504]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[504]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[503]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[503]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[502]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[502]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[501]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[501]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[500]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[500]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[499]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[499]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[498]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[498]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[497]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[497]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[496]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[496]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[495]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[495]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[494]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[494]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[493]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[493]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[492]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[492]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[491]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[491]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[490]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[490]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[489]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[489]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[488]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[488]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[487]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[487]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[486]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[486]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[485]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[485]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[484]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[484]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[483]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[483]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[482]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[482]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[481]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[481]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[480]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[480]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[479]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[479]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[478]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[478]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[477]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[477]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[476]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[476]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[475]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[475]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[474]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[474]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[473]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[473]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[472]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[472]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[471]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[471]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[470]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[470]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[469]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[469]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[468]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[468]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[467]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[467]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[466]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[466]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[465]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[465]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[464]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[464]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[463]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[463]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[462]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[462]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[461]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[461]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[460]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[460]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[459]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[459]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[458]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[458]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[457]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[457]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[456]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[456]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[455]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[455]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[454]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[454]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[453]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[453]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[452]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[452]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[451]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[451]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[450]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[450]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[449]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[449]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[448]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[448]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[447]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[447]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[446]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[446]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[445]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[445]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[444]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[444]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[443]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[443]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[442]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[442]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[441]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[441]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[440]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[440]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[439]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[439]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[438]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[438]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[437]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[437]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[436]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[436]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[435]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[435]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[434]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[434]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[433]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[433]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[432]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[432]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[431]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[431]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[430]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[430]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[429]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[429]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[428]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[428]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[427]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[427]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[426]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[426]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[425]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[425]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[424]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[424]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[423]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[423]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[422]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[422]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[421]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[421]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[420]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[420]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[419]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[419]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[418]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[418]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[417]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[417]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[416]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[416]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[415]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[415]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[414]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[414]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[413]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[413]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[412]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[412]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[411]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[411]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[410]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[410]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[409]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[409]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[408]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[408]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[407]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[407]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[406]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[406]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[405]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[405]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[404]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[404]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[403]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[403]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[402]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[402]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[401]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[401]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[400]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[400]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[399]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[399]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[398]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[398]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[397]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[397]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[396]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[396]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[395]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[395]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[394]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[394]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[393]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[393]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[392]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[392]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[391]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[391]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[390]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[390]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[389]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[389]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[388]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[388]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[387]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[387]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[386]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[386]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[385]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[385]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[384]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[384]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[383]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[383]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[382]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[382]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[381]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[381]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[380]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[380]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[379]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[379]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[378]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[378]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[377]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[377]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[376]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[376]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[375]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[375]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[374]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[374]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[373]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[373]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[372]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[372]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[371]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[371]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[370]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[370]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[369]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[369]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[368]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[368]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[367]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[367]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[366]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[366]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[365]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[365]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[364]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[364]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[363]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[363]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[362]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[362]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[361]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[361]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[360]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[360]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[359]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[359]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[358]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[358]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[357]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[357]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[356]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[356]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[355]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[355]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[354]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[354]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[353]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[353]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[352]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[352]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[351]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[351]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[350]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[350]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[349]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[349]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[348]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[348]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[347]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[347]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[346]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[346]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[345]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[345]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[344]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[344]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[343]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[343]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[342]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[342]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[341]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[341]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[340]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[340]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[339]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[339]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[338]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[338]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[337]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[337]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[336]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[336]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[335]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[335]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[334]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[334]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[333]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[333]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[332]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[332]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[331]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[331]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[330]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[330]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[329]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[329]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[328]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[328]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[327]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[327]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[326]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[326]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[325]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[325]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[324]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[324]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[323]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[323]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[322]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[322]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[321]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[321]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[320]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[320]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[319]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[319]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[318]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[318]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[317]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[317]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[316]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[316]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[315]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[315]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[314]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[314]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[313]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[313]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[312]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[312]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[311]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[311]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[310]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[310]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[309]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[309]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[308]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[308]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[307]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[307]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[306]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[306]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[305]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[305]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[304]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[304]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[303]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[303]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[302]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[302]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[301]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[301]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[300]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[300]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[299]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[299]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[298]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[298]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[297]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[297]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[296]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[296]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[295]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[295]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[294]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[294]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[293]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[293]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[292]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[292]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[291]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[291]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[290]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[290]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[289]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[289]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[288]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[288]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[287]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[287]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[286]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[286]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[285]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[285]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[284]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[284]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[283]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[283]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[282]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[282]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[281]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[281]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[280]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[280]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[279]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[279]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[278]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[278]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[277]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[277]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[276]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[276]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[275]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[275]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[274]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[274]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[273]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[273]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[272]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[272]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[271]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[271]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[270]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[270]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[269]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[269]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[268]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[268]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[267]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[267]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[266]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[266]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[265]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[265]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[264]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[264]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[263]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[263]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[262]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[262]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[261]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[261]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[260]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[260]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[259]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[259]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[258]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[258]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[257]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[257]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[256]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[256]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[255]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[255]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[254]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[254]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[253]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[253]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[252]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[252]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[251]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[251]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[250]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[250]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[249]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[249]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[248]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[248]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[247]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[247]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[246]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[246]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[245]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[245]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[244]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[244]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[243]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[243]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[242]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[242]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[241]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[241]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[240]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[240]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[239]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[239]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[238]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[238]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[237]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[237]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[236]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[236]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[235]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[235]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[234]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[234]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[233]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[233]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[232]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[232]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[231]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[231]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[230]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[230]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[229]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[229]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[228]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[228]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[227]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[227]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[226]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[226]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[225]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[225]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[224]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[224]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[223]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[223]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[222]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[222]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[221]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[221]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[220]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[220]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[219]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[219]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[218]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[218]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[217]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[217]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[216]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[216]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[215]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[215]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[214]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[214]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[213]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[213]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[212]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[212]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[211]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[211]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[210]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[210]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[209]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[209]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[208]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[208]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[207]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[207]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[206]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[206]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[205]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[205]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[204]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[204]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[203]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[203]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[202]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[202]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[201]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[201]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[200]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[200]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[199]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[199]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[198]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[198]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[197]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[197]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[196]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[196]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[195]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[195]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[194]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[194]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[193]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[193]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[192]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[192]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[191]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[191]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[190]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[190]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[189]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[189]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[188]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[188]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[187]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[187]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[186]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[186]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[185]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[185]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[184]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[184]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[183]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[183]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[182]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[182]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[181]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[181]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[180]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[180]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[179]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[179]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[178]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[178]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[177]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[177]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[176]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[176]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[175]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[175]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[174]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[174]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[173]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[173]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[172]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[172]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[171]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[171]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[170]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[170]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[169]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[169]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[168]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[168]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[167]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[167]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[166]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[166]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[165]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[165]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[164]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[164]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[163]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[163]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[162]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[162]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[161]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[161]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[160]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[160]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[159]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[159]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[158]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[158]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[157]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[157]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[156]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[156]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[155]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[155]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[154]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[154]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[153]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[153]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[152]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[152]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[151]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[151]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[150]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[150]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[149]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[149]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[148]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[148]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[147]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[147]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[146]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[146]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[145]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[145]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[144]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[144]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[143]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[143]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[142]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[142]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[141]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[141]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[140]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[140]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[139]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[139]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[138]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[138]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[137]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[137]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[136]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[136]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[135]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[135]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[134]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[134]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[133]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[133]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[132]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[132]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[131]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[131]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[130]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[130]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[129]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[129]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[128]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[128]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[127]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[127]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[126]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[126]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[125]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[125]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[124]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[124]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[123]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[123]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[122]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[122]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[121]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[121]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[120]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[120]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[119]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[119]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[118]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[118]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[117]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[117]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[116]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[116]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[115]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[115]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[114]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[114]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[113]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[113]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[112]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[112]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[111]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[111]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[110]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[110]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[109]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[109]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[108]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[108]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[107]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[107]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[106]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[106]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[105]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[105]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[104]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[104]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[103]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[103]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[102]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[102]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[101]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[101]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[100]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[100]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[99]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[99]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[98]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[98]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[97]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[97]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[96]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[96]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[95]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[95]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[94]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[94]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[93]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[93]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[92]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[92]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[91]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[91]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[90]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[90]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[89]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[89]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[88]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[88]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[87]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[87]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[86]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[86]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[85]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[85]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[84]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[84]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[83]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[83]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[82]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[82]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[81]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[81]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[80]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[80]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[79]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[79]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[78]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[78]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[77]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[77]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[76]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[76]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[75]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[75]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[74]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[74]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[73]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[73]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[72]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[72]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[71]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[71]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[70]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[70]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[69]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[69]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[68]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[68]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[67]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[67]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[66]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[66]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[65]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[65]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[64]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[64]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[63]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[63]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[62]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[62]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[61]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[61]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[60]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[60]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[59]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[59]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[58]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[58]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[57]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[57]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[56]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[56]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[55]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[55]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[54]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[54]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[53]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[53]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[52]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[52]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[51]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[51]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[50]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[50]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[49]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[49]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[48]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[48]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[47]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[47]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[46]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[46]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[45]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[45]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[44]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[44]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[43]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[43]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[42]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[42]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[41]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[41]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[40]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[40]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[39]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[39]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[38]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[38]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[37]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[37]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[36]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[36]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[35]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[35]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[34]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[34]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[33]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[33]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[32]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[32]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[31]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[31]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[30]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[30]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[29]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[29]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[28]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[28]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[27]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[27]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[26]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[26]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[25]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[25]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[24]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[24]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[23]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[23]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[22]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[22]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[21]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[21]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[20]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[20]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[19]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[19]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[18]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[18]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[17]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[17]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[16]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[16]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[15]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[15]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[14]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[14]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[13]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[13]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[12]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[12]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[11]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[11]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[10]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[10]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[9]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[9]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[8]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[8]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[7]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[7]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[6]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[6]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[5]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[5]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[4]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[4]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[3]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[3]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[2]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[2]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[1]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[1]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[0]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[0]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_v_i[0]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_v_i[0]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[26]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[26]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[25]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[25]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[24]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[24]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[23]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[23]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[22]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[22]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[21]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[21]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[20]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[20]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[19]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[19]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[18]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[18]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[17]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[17]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[16]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[16]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[15]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[15]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[14]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[14]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[13]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[13]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[12]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[12]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[11]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[11]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[10]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[10]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[9]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[9]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[8]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[8]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[7]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[7]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[6]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[6]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[5]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[5]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[4]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[4]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[3]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[3]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[2]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[2]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[1]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[1]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[0]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[0]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_v_o[0]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_v_o[0]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[566]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[566]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[565]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[565]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[564]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[564]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[563]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[563]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[562]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[562]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[561]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[561]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[560]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[560]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[559]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[559]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[558]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[558]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[557]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[557]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[556]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[556]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[555]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[555]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[554]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[554]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[553]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[553]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[552]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[552]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[551]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[551]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[550]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[550]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[549]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[549]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[548]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[548]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[547]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[547]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[546]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[546]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[545]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[545]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[544]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[544]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[543]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[543]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[542]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[542]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[541]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[541]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[540]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[540]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[539]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[539]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[538]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[538]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[537]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[537]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[536]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[536]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[535]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[535]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[534]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[534]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[533]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[533]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[532]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[532]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[531]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[531]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[530]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[530]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[529]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[529]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[528]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[528]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[527]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[527]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[526]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[526]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[525]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[525]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[524]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[524]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[523]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[523]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[522]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[522]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[521]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[521]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[520]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[520]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[519]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[519]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[518]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[518]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[517]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[517]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[516]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[516]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[515]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[515]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[514]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[514]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[513]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[513]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[512]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[512]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[511]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[511]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[510]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[510]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[509]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[509]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[508]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[508]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[507]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[507]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[506]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[506]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[505]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[505]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[504]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[504]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[503]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[503]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[502]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[502]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[501]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[501]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[500]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[500]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[499]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[499]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[498]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[498]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[497]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[497]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[496]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[496]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[495]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[495]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[494]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[494]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[493]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[493]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[492]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[492]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[491]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[491]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[490]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[490]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[489]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[489]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[488]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[488]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[487]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[487]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[486]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[486]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[485]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[485]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[484]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[484]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[483]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[483]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[482]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[482]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[481]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[481]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[480]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[480]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[479]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[479]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[478]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[478]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[477]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[477]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[476]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[476]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[475]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[475]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[474]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[474]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[473]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[473]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[472]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[472]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[471]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[471]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[470]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[470]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[469]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[469]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[468]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[468]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[467]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[467]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[466]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[466]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[465]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[465]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[464]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[464]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[463]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[463]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[462]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[462]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[461]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[461]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[460]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[460]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[459]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[459]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[458]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[458]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[457]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[457]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[456]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[456]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[455]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[455]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[454]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[454]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[453]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[453]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[452]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[452]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[451]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[451]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[450]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[450]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[449]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[449]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[448]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[448]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[447]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[447]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[446]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[446]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[445]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[445]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[444]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[444]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[443]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[443]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[442]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[442]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[441]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[441]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[440]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[440]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[439]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[439]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[438]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[438]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[437]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[437]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[436]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[436]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[435]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[435]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[434]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[434]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[433]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[433]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[432]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[432]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[431]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[431]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[430]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[430]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[429]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[429]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[428]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[428]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[427]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[427]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[426]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[426]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[425]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[425]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[424]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[424]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[423]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[423]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[422]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[422]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[421]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[421]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[420]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[420]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[419]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[419]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[418]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[418]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[417]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[417]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[416]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[416]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[415]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[415]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[414]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[414]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[413]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[413]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[412]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[412]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[411]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[411]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[410]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[410]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[409]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[409]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[408]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[408]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[407]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[407]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[406]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[406]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[405]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[405]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[404]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[404]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[403]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[403]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[402]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[402]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[401]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[401]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[400]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[400]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[399]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[399]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[398]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[398]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[397]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[397]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[396]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[396]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[395]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[395]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[394]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[394]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[393]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[393]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[392]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[392]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[391]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[391]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[390]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[390]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[389]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[389]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[388]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[388]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[387]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[387]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[386]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[386]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[385]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[385]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[384]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[384]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[383]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[383]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[382]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[382]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[381]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[381]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[380]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[380]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[379]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[379]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[378]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[378]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[377]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[377]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[376]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[376]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[375]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[375]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[374]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[374]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[373]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[373]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[372]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[372]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[371]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[371]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[370]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[370]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[369]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[369]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[368]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[368]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[367]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[367]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[366]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[366]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[365]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[365]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[364]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[364]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[363]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[363]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[362]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[362]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[361]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[361]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[360]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[360]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[359]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[359]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[358]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[358]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[357]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[357]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[356]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[356]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[355]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[355]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[354]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[354]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[353]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[353]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[352]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[352]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[351]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[351]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[350]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[350]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[349]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[349]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[348]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[348]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[347]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[347]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[346]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[346]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[345]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[345]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[344]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[344]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[343]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[343]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[342]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[342]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[341]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[341]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[340]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[340]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[339]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[339]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[338]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[338]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[337]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[337]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[336]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[336]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[335]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[335]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[334]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[334]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[333]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[333]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[332]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[332]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[331]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[331]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[330]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[330]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[329]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[329]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[328]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[328]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[327]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[327]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[326]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[326]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[325]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[325]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[324]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[324]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[323]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[323]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[322]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[322]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[321]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[321]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[320]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[320]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[319]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[319]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[318]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[318]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[317]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[317]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[316]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[316]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[315]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[315]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[314]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[314]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[313]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[313]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[312]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[312]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[311]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[311]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[310]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[310]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[309]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[309]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[308]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[308]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[307]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[307]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[306]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[306]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[305]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[305]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[304]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[304]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[303]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[303]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[302]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[302]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[301]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[301]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[300]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[300]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[299]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[299]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[298]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[298]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[297]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[297]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[296]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[296]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[295]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[295]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[294]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[294]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[293]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[293]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[292]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[292]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[291]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[291]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[290]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[290]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[289]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[289]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[288]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[288]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[287]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[287]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[286]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[286]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[285]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[285]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[284]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[284]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[283]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[283]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[282]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[282]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[281]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[281]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[280]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[280]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[279]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[279]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[278]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[278]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[277]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[277]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[276]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[276]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[275]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[275]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[274]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[274]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[273]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[273]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[272]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[272]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[271]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[271]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[270]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[270]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[269]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[269]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[268]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[268]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[267]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[267]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[266]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[266]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[265]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[265]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[264]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[264]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[263]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[263]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[262]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[262]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[261]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[261]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[260]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[260]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[259]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[259]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[258]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[258]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[257]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[257]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[256]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[256]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[255]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[255]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[254]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[254]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[253]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[253]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[252]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[252]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[251]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[251]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[250]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[250]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[249]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[249]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[248]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[248]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[247]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[247]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[246]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[246]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[245]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[245]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[244]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[244]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[243]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[243]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[242]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[242]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[241]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[241]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[240]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[240]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[239]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[239]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[238]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[238]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[237]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[237]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[236]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[236]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[235]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[235]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[234]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[234]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[233]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[233]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[232]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[232]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[231]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[231]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[230]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[230]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[229]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[229]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[228]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[228]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[227]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[227]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[226]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[226]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[225]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[225]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[224]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[224]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[223]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[223]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[222]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[222]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[221]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[221]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[220]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[220]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[219]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[219]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[218]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[218]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[217]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[217]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[216]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[216]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[215]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[215]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[214]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[214]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[213]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[213]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[212]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[212]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[211]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[211]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[210]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[210]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[209]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[209]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[208]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[208]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[207]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[207]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[206]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[206]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[205]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[205]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[204]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[204]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[203]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[203]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[202]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[202]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[201]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[201]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[200]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[200]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[199]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[199]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[198]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[198]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[197]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[197]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[196]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[196]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[195]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[195]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[194]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[194]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[193]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[193]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[192]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[192]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[191]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[191]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[190]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[190]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[189]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[189]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[188]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[188]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[187]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[187]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[186]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[186]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[185]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[185]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[184]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[184]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[183]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[183]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[182]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[182]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[181]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[181]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[180]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[180]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[179]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[179]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[178]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[178]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[177]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[177]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[176]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[176]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[175]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[175]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[174]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[174]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[173]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[173]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[172]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[172]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[171]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[171]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[170]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[170]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[169]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[169]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[168]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[168]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[167]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[167]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[166]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[166]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[165]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[165]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[164]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[164]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[163]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[163]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[162]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[162]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[161]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[161]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[160]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[160]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[159]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[159]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[158]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[158]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[157]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[157]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[156]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[156]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[155]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[155]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[154]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[154]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[153]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[153]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[152]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[152]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[151]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[151]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[150]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[150]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[149]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[149]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[148]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[148]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[147]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[147]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[146]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[146]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[145]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[145]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[144]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[144]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[143]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[143]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[142]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[142]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[141]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[141]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[140]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[140]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[139]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[139]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[138]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[138]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[137]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[137]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[136]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[136]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[135]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[135]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[134]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[134]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[133]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[133]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[132]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[132]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[131]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[131]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[130]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[130]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[129]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[129]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[128]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[128]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[127]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[127]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[126]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[126]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[125]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[125]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[124]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[124]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[123]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[123]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[122]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[122]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[121]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[121]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[120]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[120]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[119]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[119]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[118]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[118]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[117]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[117]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[116]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[116]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[115]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[115]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[114]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[114]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[113]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[113]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[112]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[112]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[111]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[111]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[110]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[110]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[109]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[109]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[108]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[108]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[107]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[107]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[106]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[106]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[105]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[105]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[104]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[104]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[103]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[103]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[102]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[102]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[101]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[101]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[100]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[100]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[99]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[99]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[98]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[98]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[97]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[97]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[96]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[96]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[95]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[95]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[94]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[94]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[93]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[93]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[92]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[92]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[91]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[91]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[90]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[90]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[89]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[89]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[88]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[88]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[87]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[87]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[86]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[86]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[85]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[85]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[84]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[84]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[83]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[83]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[82]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[82]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[81]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[81]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[80]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[80]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[79]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[79]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[78]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[78]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[77]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[77]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[76]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[76]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[75]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[75]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[74]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[74]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[73]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[73]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[72]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[72]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[71]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[71]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[70]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[70]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[69]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[69]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[68]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[68]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[67]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[67]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[66]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[66]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[65]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[65]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[64]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[64]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[63]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[63]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[62]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[62]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[61]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[61]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[60]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[60]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[59]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[59]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[58]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[58]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[57]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[57]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[56]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[56]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[55]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[55]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[54]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[54]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[53]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[53]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[52]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[52]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[51]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[51]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[50]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[50]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[49]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[49]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[48]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[48]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[47]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[47]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[46]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[46]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[45]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[45]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[44]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[44]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[43]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[43]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[42]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[42]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[41]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[41]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[40]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[40]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[39]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[39]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[38]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[38]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[37]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[37]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[36]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[36]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[35]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[35]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[34]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[34]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[33]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[33]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[32]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[32]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[31]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[31]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[30]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[30]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[29]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[29]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[28]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[28]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[27]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[27]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[26]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[26]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[25]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[25]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[24]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[24]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[23]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[23]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[22]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[22]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[21]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[21]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[20]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[20]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[19]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[19]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[18]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[18]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[17]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[17]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[16]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[16]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[15]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[15]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[14]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[14]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[13]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[13]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[12]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[12]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[11]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[11]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[10]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[10]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[9]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[9]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[8]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[8]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[7]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[7]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[6]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[6]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[5]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[5]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[4]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[4]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[3]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[3]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[2]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[2]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[1]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[1]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[0]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[0]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_v_o[0]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_v_o[0]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_resp_ready_o[0]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_resp_ready_o[0]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_ready_o[0]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_ready_o[0]}] diff --git a/flow/designs/nangate45/bp_be_top/constraint.sdc b/flow/designs/nangate45/bp_be_top/constraint.sdc index 632222055a..3df6fe408f 100644 --- a/flow/designs/nangate45/bp_be_top/constraint.sdc +++ b/flow/designs/nangate45/bp_be_top/constraint.sdc @@ -1,6058 +1,6057 @@ - -create_clock [get_ports clk_i] -name CLK -period 2.6 -waveform {0 1.3} -set_input_delay -clock CLK -max 0.6 [get_ports reset_i] -set_input_delay -clock CLK -min 0.6 [get_ports reset_i] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[133]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[133]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[132]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[132]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[131]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[131]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[130]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[130]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[129]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[129]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[128]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[128]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[127]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[127]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[126]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[126]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[125]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[125]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[124]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[124]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[123]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[123]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[122]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[122]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[121]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[121]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[120]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[120]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[119]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[119]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[118]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[118]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[117]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[117]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[116]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[116]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[115]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[115]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[114]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[114]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[113]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[113]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[112]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[112]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[111]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[111]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[110]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[110]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[109]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[109]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[108]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[108]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[107]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[107]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[106]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[106]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[105]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[105]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[104]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[104]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[103]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[103]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[102]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[102]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[101]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[101]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[100]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[100]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[99]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[99]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[98]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[98]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[97]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[97]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[96]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[96]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[95]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[95]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[94]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[94]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[93]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[93]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[92]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[92]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[91]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[91]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[90]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[90]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[89]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[89]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[88]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[88]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[87]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[87]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[86]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[86]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[85]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[85]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[84]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[84]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[83]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[83]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[82]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[82]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[81]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[81]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[80]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[80]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[79]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[79]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[78]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[78]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[77]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[77]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[76]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[76]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[75]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[75]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[74]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[74]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[73]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[73]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[72]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[72]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[71]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[71]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[70]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[70]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[69]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[69]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[68]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[68]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[67]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[67]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[66]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[66]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[65]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[65]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[64]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[64]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[63]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[63]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[62]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[62]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[61]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[61]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[60]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[60]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[59]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[59]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[58]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[58]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[57]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[57]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[56]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[56]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[55]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[55]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[54]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[54]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[53]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[53]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[52]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[52]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[51]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[51]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[50]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[50]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[49]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[49]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[48]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[48]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[47]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[47]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[46]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[46]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[45]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[45]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[44]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[44]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[43]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[43]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[42]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[42]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[41]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[41]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[40]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[40]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[39]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[39]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[38]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[38]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[37]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[37]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[36]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[36]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[35]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[34]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[33]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[32]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[31]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[30]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[29]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[28]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[27]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[26]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[25]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[24]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[23]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[22]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[21]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[20]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[19]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[18]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[17]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[16]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[15]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[14]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[13]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[12]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[11]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[10]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[9]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[8]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[7]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[6]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[5]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[4]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[3]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[0]}] -set_input_delay -clock CLK -max 0.6 [get_ports fe_queue_v_i] -set_input_delay -clock CLK -min 0.6 [get_ports fe_queue_v_i] -set_input_delay -clock CLK -max 0.6 [get_ports fe_cmd_ready_i] -set_input_delay -clock CLK -min 0.6 [get_ports fe_cmd_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports lce_req_ready_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_req_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports lce_resp_ready_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_resp_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports lce_data_resp_ready_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_data_resp_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[35]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[34]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[33]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[32]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[31]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[30]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[29]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[28]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[27]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[26]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[25]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[24]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[23]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[22]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[21]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[20]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[19]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[18]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[17]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[16]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[15]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[14]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[13]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[12]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[11]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[10]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[9]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[8]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[7]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[6]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[5]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[4]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[3]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[0]}] -set_input_delay -clock CLK -max 0.6 [get_ports lce_cmd_v_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_cmd_v_i] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[539]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[539]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[538]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[538]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[537]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[537]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[536]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[536]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[535]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[535]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[534]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[534]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[533]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[533]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[532]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[532]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[531]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[531]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[530]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[530]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[529]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[529]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[528]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[528]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[527]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[527]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[526]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[526]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[525]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[525]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[524]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[524]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[523]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[523]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[522]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[522]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[521]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[521]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[520]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[520]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[519]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[519]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[518]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[518]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[517]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[517]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[516]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[516]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[515]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[515]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[514]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[514]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[513]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[513]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[512]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[512]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[511]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[511]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[510]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[510]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[509]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[509]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[508]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[508]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[507]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[507]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[506]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[506]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[505]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[505]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[504]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[504]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[503]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[503]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[502]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[502]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[501]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[501]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[500]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[500]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[499]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[499]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[498]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[498]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[497]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[497]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[496]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[496]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[495]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[495]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[494]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[494]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[493]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[493]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[492]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[492]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[491]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[491]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[490]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[490]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[489]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[489]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[488]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[488]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[487]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[487]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[486]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[486]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[485]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[485]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[484]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[484]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[483]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[483]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[482]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[482]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[481]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[481]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[480]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[480]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[479]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[479]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[478]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[478]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[477]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[477]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[476]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[476]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[475]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[475]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[474]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[474]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[473]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[473]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[472]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[472]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[471]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[471]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[470]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[470]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[469]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[469]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[468]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[468]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[467]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[467]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[466]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[466]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[465]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[465]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[464]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[464]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[463]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[463]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[462]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[462]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[461]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[461]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[460]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[460]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[459]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[459]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[458]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[458]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[457]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[457]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[456]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[456]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[455]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[455]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[454]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[454]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[453]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[453]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[452]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[452]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[451]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[451]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[450]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[450]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[449]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[449]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[448]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[448]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[447]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[447]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[446]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[446]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[445]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[445]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[444]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[444]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[443]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[443]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[442]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[442]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[441]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[441]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[440]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[440]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[439]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[439]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[438]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[438]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[437]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[437]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[436]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[436]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[435]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[435]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[434]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[434]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[433]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[433]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[432]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[432]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[431]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[431]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[430]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[430]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[429]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[429]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[428]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[428]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[427]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[427]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[426]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[426]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[425]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[425]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[424]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[424]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[423]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[423]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[422]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[422]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[421]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[421]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[420]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[420]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[419]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[419]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[418]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[418]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[417]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[417]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[416]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[416]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[415]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[415]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[414]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[414]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[413]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[413]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[412]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[412]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[411]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[411]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[410]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[410]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[409]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[409]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[408]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[408]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[407]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[407]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[406]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[406]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[405]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[405]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[404]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[404]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[403]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[403]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[402]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[402]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[401]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[401]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[400]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[400]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[399]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[399]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[398]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[398]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[397]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[397]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[396]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[396]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[395]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[395]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[394]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[394]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[393]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[393]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[392]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[392]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[391]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[391]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[390]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[390]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[389]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[389]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[388]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[388]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[387]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[387]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[386]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[386]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[385]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[385]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[384]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[384]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[383]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[383]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[382]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[382]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[381]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[381]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[380]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[380]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[379]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[379]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[378]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[378]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[377]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[377]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[376]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[376]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[375]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[375]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[374]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[374]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[373]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[373]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[372]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[372]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[371]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[371]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[370]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[370]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[369]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[369]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[368]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[368]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[367]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[367]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[366]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[366]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[365]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[365]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[364]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[364]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[363]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[363]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[362]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[362]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[361]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[361]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[360]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[360]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[359]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[359]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[358]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[358]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[357]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[357]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[356]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[356]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[355]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[355]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[354]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[354]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[353]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[353]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[352]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[352]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[351]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[351]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[350]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[350]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[349]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[349]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[348]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[348]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[347]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[347]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[346]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[346]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[345]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[345]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[344]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[344]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[343]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[343]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[342]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[342]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[341]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[341]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[340]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[340]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[339]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[339]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[338]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[338]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[337]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[337]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[336]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[336]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[335]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[335]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[334]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[334]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[333]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[333]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[332]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[332]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[331]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[331]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[330]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[330]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[329]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[329]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[328]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[328]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[327]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[327]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[326]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[326]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[325]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[325]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[324]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[324]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[323]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[323]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[322]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[322]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[321]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[321]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[320]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[320]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[319]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[319]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[318]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[318]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[317]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[317]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[316]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[316]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[315]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[315]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[314]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[314]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[313]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[313]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[312]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[312]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[311]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[311]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[310]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[310]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[309]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[309]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[308]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[308]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[307]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[307]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[306]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[306]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[305]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[305]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[304]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[304]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[303]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[303]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[302]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[302]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[301]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[301]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[300]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[300]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[299]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[299]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[298]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[298]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[297]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[297]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[296]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[296]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[295]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[295]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[294]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[294]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[293]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[293]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[292]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[292]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[291]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[291]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[290]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[290]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[289]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[289]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[288]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[288]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[287]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[287]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[286]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[286]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[285]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[285]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[284]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[284]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[283]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[283]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[282]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[282]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[281]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[281]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[280]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[280]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[279]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[279]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[278]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[278]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[277]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[277]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[276]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[276]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[275]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[275]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[274]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[274]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[273]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[273]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[272]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[272]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[271]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[271]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[270]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[270]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[269]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[269]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[268]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[268]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[267]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[267]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[266]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[266]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[265]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[265]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[264]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[264]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[263]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[263]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[262]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[262]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[261]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[261]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[260]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[260]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[259]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[259]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[258]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[258]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[257]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[257]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[256]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[256]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[255]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[255]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[254]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[254]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[253]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[253]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[252]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[252]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[251]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[251]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[250]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[250]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[249]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[249]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[248]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[248]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[247]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[247]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[246]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[246]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[245]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[245]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[244]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[244]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[243]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[243]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[242]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[242]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[241]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[241]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[240]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[240]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[239]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[239]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[238]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[238]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[237]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[237]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[236]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[236]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[235]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[235]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[234]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[234]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[233]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[233]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[232]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[232]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[231]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[231]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[230]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[230]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[229]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[229]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[228]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[228]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[227]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[227]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[226]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[226]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[225]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[225]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[224]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[224]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[223]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[223]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[222]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[222]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[221]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[221]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[220]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[220]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[219]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[219]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[218]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[218]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[217]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[217]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[216]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[216]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[215]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[215]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[214]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[214]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[213]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[213]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[212]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[212]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[211]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[211]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[210]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[210]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[209]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[209]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[208]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[208]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[207]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[207]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[206]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[206]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[205]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[205]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[204]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[204]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[203]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[203]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[202]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[202]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[201]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[201]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[200]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[200]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[199]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[199]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[198]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[198]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[197]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[197]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[196]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[196]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[195]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[195]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[194]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[194]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[193]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[193]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[192]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[192]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[191]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[191]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[190]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[190]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[189]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[189]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[188]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[188]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[187]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[187]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[186]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[186]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[185]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[185]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[184]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[184]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[183]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[183]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[182]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[182]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[181]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[181]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[180]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[180]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[179]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[179]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[178]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[178]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[177]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[177]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[176]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[176]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[175]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[175]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[174]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[174]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[173]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[173]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[172]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[172]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[171]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[171]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[170]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[170]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[169]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[169]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[168]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[168]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[167]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[167]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[166]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[166]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[165]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[165]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[164]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[164]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[163]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[163]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[162]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[162]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[161]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[161]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[160]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[160]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[159]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[159]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[158]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[158]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[157]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[157]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[156]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[156]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[155]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[155]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[154]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[154]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[153]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[153]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[152]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[152]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[151]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[151]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[150]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[150]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[149]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[149]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[148]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[148]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[147]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[147]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[146]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[146]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[145]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[145]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[144]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[144]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[143]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[143]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[142]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[142]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[141]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[141]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[140]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[140]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[139]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[139]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[138]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[138]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[137]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[137]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[136]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[136]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[135]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[135]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[134]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[134]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[133]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[133]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[132]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[132]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[131]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[131]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[130]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[130]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[129]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[129]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[128]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[128]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[127]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[127]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[126]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[126]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[125]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[125]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[124]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[124]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[123]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[123]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[122]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[122]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[121]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[121]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[120]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[120]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[119]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[119]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[118]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[118]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[117]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[117]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[116]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[116]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[115]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[115]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[114]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[114]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[113]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[113]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[112]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[112]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[111]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[111]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[110]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[110]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[109]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[109]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[108]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[108]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[107]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[107]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[106]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[106]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[105]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[105]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[104]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[104]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[103]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[103]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[102]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[102]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[101]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[101]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[100]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[100]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[99]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[99]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[98]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[98]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[97]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[97]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[96]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[96]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[95]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[95]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[94]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[94]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[93]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[93]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[92]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[92]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[91]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[91]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[90]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[90]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[89]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[89]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[88]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[88]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[87]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[87]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[86]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[86]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[85]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[85]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[84]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[84]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[83]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[83]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[82]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[82]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[81]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[81]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[80]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[80]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[79]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[79]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[78]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[78]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[77]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[77]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[76]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[76]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[75]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[75]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[74]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[74]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[73]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[73]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[72]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[72]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[71]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[71]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[70]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[70]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[69]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[69]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[68]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[68]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[67]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[67]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[66]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[66]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[65]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[65]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[64]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[64]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[63]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[63]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[62]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[62]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[61]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[61]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[60]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[60]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[59]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[59]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[58]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[58]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[57]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[57]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[56]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[56]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[55]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[55]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[54]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[54]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[53]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[53]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[52]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[52]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[51]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[51]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[50]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[50]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[49]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[49]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[48]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[48]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[47]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[47]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[46]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[46]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[45]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[45]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[44]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[44]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[43]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[43]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[42]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[42]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[41]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[41]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[40]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[40]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[39]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[39]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[38]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[38]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[37]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[37]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[36]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[36]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[35]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[34]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[33]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[32]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[31]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[30]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[29]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[28]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[27]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[26]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[25]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[24]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[23]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[22]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[21]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[20]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[19]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[18]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[17]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[16]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[15]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[14]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[13]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[12]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[11]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[10]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[9]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[8]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[7]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[6]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[5]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[4]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[3]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[0]}] -set_input_delay -clock CLK -max 0.6 [get_ports lce_data_cmd_v_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_data_cmd_v_i] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[538]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[538]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[537]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[537]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[536]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[536]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[535]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[535]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[534]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[534]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[533]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[533]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[532]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[532]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[531]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[531]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[530]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[530]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[529]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[529]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[528]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[528]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[527]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[527]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[526]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[526]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[525]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[525]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[524]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[524]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[523]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[523]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[522]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[522]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[521]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[521]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[520]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[520]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[519]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[519]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[518]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[518]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[517]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[517]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[516]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[516]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[515]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[515]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[514]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[514]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[513]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[513]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[512]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[512]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[511]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[511]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[510]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[510]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[509]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[509]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[508]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[508]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[507]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[507]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[506]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[506]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[505]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[505]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[504]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[504]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[503]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[503]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[502]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[502]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[501]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[501]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[500]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[500]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[499]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[499]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[498]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[498]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[497]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[497]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[496]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[496]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[495]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[495]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[494]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[494]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[493]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[493]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[492]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[492]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[491]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[491]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[490]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[490]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[489]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[489]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[488]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[488]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[487]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[487]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[486]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[486]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[485]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[485]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[484]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[484]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[483]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[483]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[482]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[482]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[481]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[481]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[480]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[480]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[479]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[479]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[478]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[478]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[477]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[477]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[476]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[476]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[475]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[475]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[474]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[474]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[473]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[473]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[472]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[472]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[471]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[471]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[470]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[470]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[469]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[469]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[468]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[468]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[467]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[467]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[466]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[466]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[465]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[465]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[464]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[464]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[463]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[463]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[462]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[462]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[461]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[461]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[460]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[460]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[459]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[459]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[458]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[458]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[457]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[457]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[456]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[456]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[455]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[455]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[454]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[454]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[453]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[453]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[452]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[452]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[451]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[451]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[450]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[450]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[449]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[449]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[448]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[448]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[447]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[447]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[446]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[446]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[445]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[445]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[444]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[444]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[443]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[443]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[442]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[442]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[441]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[441]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[440]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[440]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[439]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[439]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[438]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[438]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[437]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[437]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[436]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[436]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[435]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[435]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[434]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[434]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[433]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[433]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[432]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[432]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[431]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[431]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[430]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[430]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[429]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[429]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[428]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[428]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[427]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[427]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[426]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[426]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[425]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[425]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[424]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[424]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[423]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[423]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[422]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[422]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[421]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[421]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[420]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[420]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[419]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[419]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[418]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[418]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[417]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[417]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[416]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[416]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[415]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[415]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[414]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[414]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[413]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[413]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[412]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[412]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[411]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[411]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[410]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[410]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[409]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[409]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[408]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[408]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[407]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[407]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[406]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[406]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[405]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[405]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[404]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[404]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[403]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[403]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[402]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[402]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[401]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[401]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[400]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[400]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[399]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[399]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[398]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[398]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[397]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[397]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[396]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[396]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[395]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[395]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[394]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[394]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[393]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[393]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[392]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[392]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[391]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[391]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[390]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[390]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[389]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[389]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[388]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[388]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[387]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[387]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[386]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[386]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[385]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[385]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[384]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[384]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[383]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[383]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[382]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[382]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[381]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[381]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[380]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[380]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[379]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[379]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[378]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[378]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[377]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[377]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[376]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[376]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[375]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[375]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[374]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[374]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[373]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[373]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[372]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[372]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[371]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[371]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[370]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[370]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[369]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[369]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[368]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[368]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[367]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[367]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[366]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[366]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[365]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[365]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[364]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[364]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[363]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[363]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[362]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[362]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[361]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[361]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[360]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[360]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[359]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[359]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[358]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[358]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[357]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[357]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[356]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[356]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[355]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[355]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[354]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[354]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[353]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[353]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[352]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[352]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[351]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[351]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[350]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[350]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[349]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[349]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[348]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[348]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[347]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[347]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[346]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[346]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[345]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[345]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[344]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[344]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[343]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[343]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[342]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[342]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[341]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[341]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[340]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[340]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[339]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[339]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[338]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[338]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[337]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[337]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[336]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[336]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[335]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[335]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[334]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[334]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[333]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[333]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[332]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[332]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[331]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[331]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[330]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[330]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[329]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[329]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[328]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[328]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[327]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[327]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[326]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[326]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[325]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[325]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[324]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[324]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[323]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[323]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[322]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[322]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[321]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[321]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[320]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[320]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[319]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[319]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[318]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[318]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[317]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[317]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[316]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[316]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[315]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[315]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[314]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[314]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[313]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[313]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[312]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[312]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[311]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[311]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[310]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[310]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[309]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[309]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[308]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[308]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[307]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[307]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[306]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[306]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[305]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[305]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[304]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[304]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[303]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[303]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[302]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[302]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[301]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[301]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[300]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[300]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[299]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[299]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[298]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[298]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[297]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[297]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[296]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[296]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[295]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[295]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[294]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[294]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[293]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[293]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[292]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[292]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[291]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[291]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[290]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[290]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[289]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[289]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[288]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[288]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[287]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[287]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[286]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[286]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[285]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[285]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[284]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[284]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[283]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[283]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[282]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[282]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[281]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[281]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[280]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[280]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[279]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[279]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[278]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[278]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[277]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[277]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[276]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[276]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[275]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[275]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[274]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[274]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[273]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[273]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[272]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[272]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[271]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[271]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[270]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[270]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[269]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[269]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[268]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[268]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[267]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[267]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[266]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[266]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[265]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[265]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[264]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[264]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[263]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[263]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[262]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[262]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[261]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[261]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[260]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[260]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[259]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[259]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[258]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[258]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[257]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[257]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[256]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[256]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[255]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[255]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[254]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[254]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[253]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[253]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[252]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[252]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[251]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[251]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[250]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[250]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[249]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[249]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[248]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[248]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[247]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[247]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[246]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[246]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[245]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[245]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[244]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[244]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[243]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[243]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[242]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[242]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[241]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[241]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[240]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[240]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[239]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[239]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[238]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[238]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[237]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[237]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[236]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[236]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[235]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[235]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[234]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[234]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[233]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[233]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[232]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[232]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[231]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[231]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[230]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[230]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[229]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[229]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[228]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[228]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[227]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[227]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[226]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[226]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[225]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[225]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[224]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[224]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[223]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[223]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[222]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[222]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[221]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[221]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[220]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[220]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[219]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[219]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[218]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[218]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[217]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[217]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[216]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[216]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[215]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[215]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[214]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[214]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[213]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[213]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[212]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[212]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[211]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[211]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[210]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[210]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[209]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[209]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[208]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[208]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[207]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[207]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[206]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[206]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[205]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[205]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[204]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[204]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[203]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[203]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[202]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[202]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[201]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[201]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[200]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[200]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[199]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[199]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[198]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[198]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[197]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[197]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[196]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[196]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[195]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[195]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[194]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[194]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[193]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[193]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[192]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[192]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[191]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[191]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[190]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[190]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[189]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[189]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[188]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[188]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[187]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[187]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[186]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[186]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[185]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[185]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[184]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[184]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[183]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[183]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[182]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[182]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[181]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[181]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[180]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[180]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[179]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[179]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[178]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[178]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[177]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[177]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[176]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[176]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[175]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[175]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[174]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[174]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[173]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[173]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[172]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[172]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[171]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[171]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[170]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[170]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[169]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[169]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[168]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[168]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[167]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[167]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[166]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[166]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[165]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[165]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[164]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[164]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[163]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[163]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[162]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[162]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[161]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[161]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[160]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[160]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[159]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[159]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[158]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[158]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[157]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[157]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[156]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[156]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[155]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[155]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[154]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[154]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[153]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[153]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[152]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[152]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[151]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[151]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[150]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[150]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[149]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[149]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[148]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[148]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[147]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[147]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[146]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[146]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[145]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[145]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[144]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[144]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[143]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[143]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[142]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[142]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[141]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[141]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[140]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[140]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[139]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[139]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[138]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[138]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[137]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[137]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[136]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[136]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[135]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[135]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[134]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[134]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[133]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[133]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[132]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[132]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[131]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[131]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[130]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[130]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[129]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[129]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[128]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[128]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[127]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[127]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[126]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[126]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[125]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[125]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[124]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[124]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[123]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[123]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[122]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[122]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[121]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[121]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[120]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[120]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[119]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[119]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[118]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[118]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[117]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[117]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[116]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[116]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[115]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[115]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[114]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[114]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[113]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[113]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[112]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[112]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[111]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[111]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[110]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[110]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[109]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[109]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[108]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[108]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[107]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[107]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[106]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[106]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[105]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[105]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[104]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[104]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[103]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[103]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[102]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[102]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[101]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[101]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[100]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[100]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[99]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[99]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[98]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[98]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[97]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[97]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[96]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[96]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[95]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[95]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[94]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[94]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[93]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[93]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[92]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[92]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[91]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[91]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[90]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[90]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[89]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[89]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[88]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[88]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[87]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[87]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[86]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[86]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[85]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[85]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[84]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[84]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[83]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[83]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[82]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[82]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[81]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[81]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[80]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[80]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[79]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[79]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[78]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[78]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[77]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[77]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[76]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[76]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[75]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[75]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[74]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[74]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[73]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[73]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[72]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[72]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[71]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[71]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[70]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[70]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[69]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[69]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[68]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[68]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[67]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[67]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[66]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[66]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[65]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[65]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[64]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[64]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[63]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[63]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[62]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[62]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[61]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[61]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[60]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[60]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[59]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[59]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[58]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[58]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[57]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[57]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[56]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[56]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[55]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[55]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[54]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[54]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[53]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[53]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[52]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[52]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[51]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[51]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[50]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[50]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[49]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[49]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[48]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[48]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[47]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[47]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[46]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[46]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[45]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[45]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[44]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[44]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[43]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[43]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[42]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[42]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[41]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[41]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[40]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[40]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[39]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[39]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[38]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[38]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[37]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[37]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[36]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[36]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[35]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[34]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[33]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[32]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[31]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[30]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[29]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[28]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[27]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[26]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[25]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[24]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[23]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[22]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[21]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[20]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[19]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[18]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[17]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[16]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[15]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[14]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[13]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[12]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[11]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[10]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[9]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[8]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[7]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[6]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[5]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[4]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[3]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[0]}] -set_input_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_v_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_v_i] -set_input_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_ready_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_ready_o] -set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_ready_o] -set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_clr_o] -set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_clr_o] -set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_dequeue_o] -set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_dequeue_o] -set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_rollback_o] -set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_rollback_o] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[108]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[107]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[106]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[105]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[104]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[103]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[102]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[101]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[100]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[99]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[98]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[97]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[96]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[95]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[94]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[93]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[92]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[91]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[90]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[89]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[88]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[87]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[86]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[85]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[84]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[83]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[82]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[81]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[80]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[79]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[78]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[77]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[76]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[75]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[74]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[73]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[72]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[71]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[70]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[69]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[68]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[67]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[66]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[65]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[64]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports fe_cmd_v_o] -set_output_delay -clock CLK -min 0.6 [get_ports fe_cmd_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports lce_req_v_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_req_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports lce_resp_v_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_resp_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[536]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[536]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[535]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[535]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[534]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[534]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[533]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[533]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[532]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[532]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[531]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[531]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[530]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[530]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[529]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[529]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[528]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[528]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[527]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[527]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[526]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[526]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[525]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[525]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[524]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[524]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[523]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[523]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[522]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[522]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[521]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[521]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[520]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[520]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[519]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[519]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[518]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[518]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[517]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[517]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[516]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[516]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[515]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[515]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[514]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[514]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[513]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[513]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[512]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[512]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[511]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[511]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[510]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[510]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[509]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[509]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[508]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[508]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[507]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[507]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[506]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[506]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[505]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[505]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[504]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[504]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[503]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[503]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[502]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[502]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[501]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[501]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[500]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[500]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[499]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[499]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[498]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[498]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[497]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[497]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[496]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[496]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[495]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[495]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[494]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[494]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[493]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[493]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[492]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[492]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[491]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[491]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[490]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[490]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[489]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[489]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[488]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[488]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[487]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[487]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[486]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[486]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[485]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[485]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[484]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[484]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[483]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[483]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[482]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[482]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[481]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[481]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[480]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[480]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[479]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[479]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[478]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[478]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[477]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[477]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[476]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[476]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[475]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[475]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[474]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[474]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[473]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[473]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[472]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[472]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[471]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[471]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[470]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[470]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[469]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[469]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[468]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[468]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[467]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[467]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[466]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[466]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[465]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[465]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[464]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[464]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[463]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[463]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[462]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[462]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[461]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[461]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[460]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[460]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[459]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[459]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[458]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[458]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[457]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[457]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[456]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[456]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[455]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[455]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[454]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[454]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[453]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[453]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[452]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[452]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[451]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[451]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[450]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[450]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[449]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[449]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[448]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[448]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[447]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[447]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[446]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[446]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[445]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[445]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[444]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[444]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[443]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[443]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[442]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[442]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[441]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[441]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[440]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[440]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[439]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[439]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[438]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[438]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[437]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[437]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[436]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[436]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[435]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[435]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[434]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[434]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[433]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[433]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[432]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[432]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[431]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[431]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[430]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[430]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[429]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[429]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[428]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[428]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[427]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[427]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[426]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[426]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[425]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[425]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[424]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[424]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[423]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[423]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[422]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[422]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[421]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[421]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[420]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[420]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[419]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[419]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[418]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[418]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[417]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[417]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[416]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[416]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[415]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[415]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[414]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[414]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[413]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[413]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[412]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[412]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[411]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[411]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[410]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[410]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[409]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[409]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[408]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[408]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[407]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[407]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[406]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[406]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[405]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[405]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[404]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[404]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[403]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[403]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[402]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[402]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[401]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[401]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[400]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[400]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[399]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[399]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[398]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[398]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[397]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[397]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[396]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[396]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[395]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[395]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[394]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[394]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[393]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[393]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[392]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[392]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[391]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[391]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[390]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[390]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[389]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[389]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[388]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[388]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[387]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[387]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[386]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[386]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[385]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[385]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[384]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[384]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[383]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[383]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[382]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[382]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[381]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[381]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[380]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[380]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[379]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[379]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[378]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[378]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[377]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[377]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[376]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[376]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[375]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[375]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[374]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[374]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[373]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[373]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[372]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[372]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[371]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[371]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[370]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[370]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[369]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[369]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[368]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[368]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[367]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[367]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[366]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[366]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[365]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[365]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[364]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[364]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[363]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[363]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[362]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[362]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[361]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[361]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[360]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[360]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[359]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[359]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[358]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[358]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[357]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[357]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[356]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[356]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[355]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[355]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[354]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[354]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[353]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[353]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[352]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[352]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[351]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[351]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[350]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[350]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[349]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[349]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[348]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[348]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[347]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[347]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[346]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[346]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[345]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[345]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[344]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[344]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[343]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[343]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[342]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[342]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[341]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[341]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[340]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[340]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[339]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[339]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[338]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[338]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[337]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[337]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[336]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[336]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[335]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[335]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[334]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[334]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[333]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[333]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[332]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[332]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[331]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[331]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[330]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[330]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[329]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[329]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[328]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[328]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[327]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[327]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[326]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[326]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[325]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[325]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[324]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[324]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[323]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[323]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[322]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[322]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[321]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[321]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[320]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[320]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[319]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[319]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[318]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[318]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[317]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[317]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[316]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[316]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[315]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[315]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[314]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[314]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[313]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[313]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[312]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[312]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[311]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[311]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[310]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[310]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[309]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[309]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[308]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[308]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[307]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[307]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[306]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[306]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[305]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[305]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[304]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[304]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[303]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[303]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[302]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[302]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[301]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[301]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[300]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[300]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[299]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[299]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[298]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[298]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[297]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[297]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[296]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[296]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[295]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[295]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[294]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[294]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[293]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[293]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[292]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[292]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[291]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[291]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[290]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[290]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[289]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[289]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[288]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[288]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[287]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[287]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[286]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[286]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[285]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[285]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[284]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[284]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[283]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[283]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[282]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[282]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[281]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[281]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[280]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[280]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[279]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[279]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[278]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[278]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[277]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[277]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[276]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[276]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[275]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[275]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[274]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[274]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[273]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[273]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[272]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[272]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[271]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[271]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[270]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[270]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[269]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[269]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[268]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[268]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[267]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[267]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[266]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[266]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[265]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[265]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[264]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[264]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[263]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[263]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[262]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[262]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[261]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[261]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[260]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[260]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[259]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[259]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[258]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[258]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[257]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[257]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[256]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[256]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[255]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[255]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[254]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[254]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[253]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[253]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[252]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[252]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[251]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[251]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[250]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[250]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[249]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[249]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[248]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[248]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[247]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[247]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[246]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[246]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[245]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[245]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[244]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[244]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[243]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[243]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[242]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[242]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[241]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[241]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[240]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[240]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[239]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[239]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[238]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[238]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[237]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[237]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[236]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[236]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[235]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[235]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[234]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[234]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[233]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[233]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[232]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[232]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[231]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[231]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[230]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[230]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[229]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[229]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[228]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[228]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[227]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[227]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[226]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[226]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[225]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[225]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[224]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[224]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[223]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[223]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[222]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[222]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[221]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[221]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[220]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[220]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[219]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[219]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[218]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[218]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[217]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[217]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[216]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[216]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[215]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[215]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[214]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[214]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[213]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[213]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[212]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[212]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[211]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[211]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[210]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[210]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[209]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[209]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[208]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[208]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[207]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[207]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[206]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[206]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[205]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[205]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[204]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[204]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[203]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[203]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[202]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[202]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[201]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[201]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[200]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[200]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[199]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[199]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[198]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[198]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[197]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[197]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[196]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[196]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[195]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[195]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[194]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[194]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[193]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[193]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[192]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[192]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[191]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[191]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[190]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[190]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[189]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[189]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[188]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[188]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[187]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[187]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[186]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[186]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[185]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[185]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[184]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[184]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[183]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[183]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[182]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[182]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[181]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[181]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[180]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[180]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[179]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[179]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[178]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[178]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[177]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[177]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[176]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[176]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[175]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[175]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[174]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[174]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[173]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[173]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[172]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[172]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[171]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[171]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[170]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[170]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[169]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[169]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[168]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[168]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[167]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[167]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[166]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[166]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[165]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[165]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[164]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[164]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[163]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[163]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[162]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[162]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[161]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[161]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[160]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[160]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[159]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[159]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[158]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[158]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[157]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[157]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[156]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[156]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[155]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[155]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[154]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[154]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[153]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[153]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[152]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[152]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[151]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[151]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[150]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[150]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[149]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[149]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[148]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[148]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[147]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[147]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[146]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[146]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[145]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[145]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[144]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[144]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[143]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[143]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[142]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[142]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[141]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[141]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[140]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[140]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[139]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[139]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[138]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[138]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[137]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[137]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[136]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[136]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[135]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[135]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[134]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[134]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[133]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[133]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[132]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[132]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[131]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[131]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[130]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[130]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[129]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[129]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[128]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[128]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[127]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[127]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[126]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[126]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[125]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[125]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[124]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[124]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[123]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[123]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[122]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[122]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[121]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[121]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[120]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[120]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[119]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[119]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[118]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[118]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[117]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[117]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[116]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[116]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[115]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[115]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[114]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[114]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[113]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[113]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[112]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[112]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[111]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[111]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[110]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[110]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[109]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[109]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[108]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[107]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[106]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[105]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[104]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[103]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[102]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[101]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[100]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[99]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[98]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[97]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[96]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[95]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[94]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[93]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[92]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[91]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[90]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[89]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[88]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[87]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[86]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[85]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[84]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[83]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[82]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[81]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[80]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[79]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[78]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[77]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[76]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[75]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[74]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[73]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[72]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[71]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[70]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[69]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[68]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[67]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[66]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[65]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[64]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports lce_data_resp_v_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_data_resp_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports lce_cmd_ready_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_cmd_ready_o] -set_output_delay -clock CLK -max 0.6 [get_ports lce_data_cmd_ready_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_data_cmd_ready_o] -set_output_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_ready_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_ready_o] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[538]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[538]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[537]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[537]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[536]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[536]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[535]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[535]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[534]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[534]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[533]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[533]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[532]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[532]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[531]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[531]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[530]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[530]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[529]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[529]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[528]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[528]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[527]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[527]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[526]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[526]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[525]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[525]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[524]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[524]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[523]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[523]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[522]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[522]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[521]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[521]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[520]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[520]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[519]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[519]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[518]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[518]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[517]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[517]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[516]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[516]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[515]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[515]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[514]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[514]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[513]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[513]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[512]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[512]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[511]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[511]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[510]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[510]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[509]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[509]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[508]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[508]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[507]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[507]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[506]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[506]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[505]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[505]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[504]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[504]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[503]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[503]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[502]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[502]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[501]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[501]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[500]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[500]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[499]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[499]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[498]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[498]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[497]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[497]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[496]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[496]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[495]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[495]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[494]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[494]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[493]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[493]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[492]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[492]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[491]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[491]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[490]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[490]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[489]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[489]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[488]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[488]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[487]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[487]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[486]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[486]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[485]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[485]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[484]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[484]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[483]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[483]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[482]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[482]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[481]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[481]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[480]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[480]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[479]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[479]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[478]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[478]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[477]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[477]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[476]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[476]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[475]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[475]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[474]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[474]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[473]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[473]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[472]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[472]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[471]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[471]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[470]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[470]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[469]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[469]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[468]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[468]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[467]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[467]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[466]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[466]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[465]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[465]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[464]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[464]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[463]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[463]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[462]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[462]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[461]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[461]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[460]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[460]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[459]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[459]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[458]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[458]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[457]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[457]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[456]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[456]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[455]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[455]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[454]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[454]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[453]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[453]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[452]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[452]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[451]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[451]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[450]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[450]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[449]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[449]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[448]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[448]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[447]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[447]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[446]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[446]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[445]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[445]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[444]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[444]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[443]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[443]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[442]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[442]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[441]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[441]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[440]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[440]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[439]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[439]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[438]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[438]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[437]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[437]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[436]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[436]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[435]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[435]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[434]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[434]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[433]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[433]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[432]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[432]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[431]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[431]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[430]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[430]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[429]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[429]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[428]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[428]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[427]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[427]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[426]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[426]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[425]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[425]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[424]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[424]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[423]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[423]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[422]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[422]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[421]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[421]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[420]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[420]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[419]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[419]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[418]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[418]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[417]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[417]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[416]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[416]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[415]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[415]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[414]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[414]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[413]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[413]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[412]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[412]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[411]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[411]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[410]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[410]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[409]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[409]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[408]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[408]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[407]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[407]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[406]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[406]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[405]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[405]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[404]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[404]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[403]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[403]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[402]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[402]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[401]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[401]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[400]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[400]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[399]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[399]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[398]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[398]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[397]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[397]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[396]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[396]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[395]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[395]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[394]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[394]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[393]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[393]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[392]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[392]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[391]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[391]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[390]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[390]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[389]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[389]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[388]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[388]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[387]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[387]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[386]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[386]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[385]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[385]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[384]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[384]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[383]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[383]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[382]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[382]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[381]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[381]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[380]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[380]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[379]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[379]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[378]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[378]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[377]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[377]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[376]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[376]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[375]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[375]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[374]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[374]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[373]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[373]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[372]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[372]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[371]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[371]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[370]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[370]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[369]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[369]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[368]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[368]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[367]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[367]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[366]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[366]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[365]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[365]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[364]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[364]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[363]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[363]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[362]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[362]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[361]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[361]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[360]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[360]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[359]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[359]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[358]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[358]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[357]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[357]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[356]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[356]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[355]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[355]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[354]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[354]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[353]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[353]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[352]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[352]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[351]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[351]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[350]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[350]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[349]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[349]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[348]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[348]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[347]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[347]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[346]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[346]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[345]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[345]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[344]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[344]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[343]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[343]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[342]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[342]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[341]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[341]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[340]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[340]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[339]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[339]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[338]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[338]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[337]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[337]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[336]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[336]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[335]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[335]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[334]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[334]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[333]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[333]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[332]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[332]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[331]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[331]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[330]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[330]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[329]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[329]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[328]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[328]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[327]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[327]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[326]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[326]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[325]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[325]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[324]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[324]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[323]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[323]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[322]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[322]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[321]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[321]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[320]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[320]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[319]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[319]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[318]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[318]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[317]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[317]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[316]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[316]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[315]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[315]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[314]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[314]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[313]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[313]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[312]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[312]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[311]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[311]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[310]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[310]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[309]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[309]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[308]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[308]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[307]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[307]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[306]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[306]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[305]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[305]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[304]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[304]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[303]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[303]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[302]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[302]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[301]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[301]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[300]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[300]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[299]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[299]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[298]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[298]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[297]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[297]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[296]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[296]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[295]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[295]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[294]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[294]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[293]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[293]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[292]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[292]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[291]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[291]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[290]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[290]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[289]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[289]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[288]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[288]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[287]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[287]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[286]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[286]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[285]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[285]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[284]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[284]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[283]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[283]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[282]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[282]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[281]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[281]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[280]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[280]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[279]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[279]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[278]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[278]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[277]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[277]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[276]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[276]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[275]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[275]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[274]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[274]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[273]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[273]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[272]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[272]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[271]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[271]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[270]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[270]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[269]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[269]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[268]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[268]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[267]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[267]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[266]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[266]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[265]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[265]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[264]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[264]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[263]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[263]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[262]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[262]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[261]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[261]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[260]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[260]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[259]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[259]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[258]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[258]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[257]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[257]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[256]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[256]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[255]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[255]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[254]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[254]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[253]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[253]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[252]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[252]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[251]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[251]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[250]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[250]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[249]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[249]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[248]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[248]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[247]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[247]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[246]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[246]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[245]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[245]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[244]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[244]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[243]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[243]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[242]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[242]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[241]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[241]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[240]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[240]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[239]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[239]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[238]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[238]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[237]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[237]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[236]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[236]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[235]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[235]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[234]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[234]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[233]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[233]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[232]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[232]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[231]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[231]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[230]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[230]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[229]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[229]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[228]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[228]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[227]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[227]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[226]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[226]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[225]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[225]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[224]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[224]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[223]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[223]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[222]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[222]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[221]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[221]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[220]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[220]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[219]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[219]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[218]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[218]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[217]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[217]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[216]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[216]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[215]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[215]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[214]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[214]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[213]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[213]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[212]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[212]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[211]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[211]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[210]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[210]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[209]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[209]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[208]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[208]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[207]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[207]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[206]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[206]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[205]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[205]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[204]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[204]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[203]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[203]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[202]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[202]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[201]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[201]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[200]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[200]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[199]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[199]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[198]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[198]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[197]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[197]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[196]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[196]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[195]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[195]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[194]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[194]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[193]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[193]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[192]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[192]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[191]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[191]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[190]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[190]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[189]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[189]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[188]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[188]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[187]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[187]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[186]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[186]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[185]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[185]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[184]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[184]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[183]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[183]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[182]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[182]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[181]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[181]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[180]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[180]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[179]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[179]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[178]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[178]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[177]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[177]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[176]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[176]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[175]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[175]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[174]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[174]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[173]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[173]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[172]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[172]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[171]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[171]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[170]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[170]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[169]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[169]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[168]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[168]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[167]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[167]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[166]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[166]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[165]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[165]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[164]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[164]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[163]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[163]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[162]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[162]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[161]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[161]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[160]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[160]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[159]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[159]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[158]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[158]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[157]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[157]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[156]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[156]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[155]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[155]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[154]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[154]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[153]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[153]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[152]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[152]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[151]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[151]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[150]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[150]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[149]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[149]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[148]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[148]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[147]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[147]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[146]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[146]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[145]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[145]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[144]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[144]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[143]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[143]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[142]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[142]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[141]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[141]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[140]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[140]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[139]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[139]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[138]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[138]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[137]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[137]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[136]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[136]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[135]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[135]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[134]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[134]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[133]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[133]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[132]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[132]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[131]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[131]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[130]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[130]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[129]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[129]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[128]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[128]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[127]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[127]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[126]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[126]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[125]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[125]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[124]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[124]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[123]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[123]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[122]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[122]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[121]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[121]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[120]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[120]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[119]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[119]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[118]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[118]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[117]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[117]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[116]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[116]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[115]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[115]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[114]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[114]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[113]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[113]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[112]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[112]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[111]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[111]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[110]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[110]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[109]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[109]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[108]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[107]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[106]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[105]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[104]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[103]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[102]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[101]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[100]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[99]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[98]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[97]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[96]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[95]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[94]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[93]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[92]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[91]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[90]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[89]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[88]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[87]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[86]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[85]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[84]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[83]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[82]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[81]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[80]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[79]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[78]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[77]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[76]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[75]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[74]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[73]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[72]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[71]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[70]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[69]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[68]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[67]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[66]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[65]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[64]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_v_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[377]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[377]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[376]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[376]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[375]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[375]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[374]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[374]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[373]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[373]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[372]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[372]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[371]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[371]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[370]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[370]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[369]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[369]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[368]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[368]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[367]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[367]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[366]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[366]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[365]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[365]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[364]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[364]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[363]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[363]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[362]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[362]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[361]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[361]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[360]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[360]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[359]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[359]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[358]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[358]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[357]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[357]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[356]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[356]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[355]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[355]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[354]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[354]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[353]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[353]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[352]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[352]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[351]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[351]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[350]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[350]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[349]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[349]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[348]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[348]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[347]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[347]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[346]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[346]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[345]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[345]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[344]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[344]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[343]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[343]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[342]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[342]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[341]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[341]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[340]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[340]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[339]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[339]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[338]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[338]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[337]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[337]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[336]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[336]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[335]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[335]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[334]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[334]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[333]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[333]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[332]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[332]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[331]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[331]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[330]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[330]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[329]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[329]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[328]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[328]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[327]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[327]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[326]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[326]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[325]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[325]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[324]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[324]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[323]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[323]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[322]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[322]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[321]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[321]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[320]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[320]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[319]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[319]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[318]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[318]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[317]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[317]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[316]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[316]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[315]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[315]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[314]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[314]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[313]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[313]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[312]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[312]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[311]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[311]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[310]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[310]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[309]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[309]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[308]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[308]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[307]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[307]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[306]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[306]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[305]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[305]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[304]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[304]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[303]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[303]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[302]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[302]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[301]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[301]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[300]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[300]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[299]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[299]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[298]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[298]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[297]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[297]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[296]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[296]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[295]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[295]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[294]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[294]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[293]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[293]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[292]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[292]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[291]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[291]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[290]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[290]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[289]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[289]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[288]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[288]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[287]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[287]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[286]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[286]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[285]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[285]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[284]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[284]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[283]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[283]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[282]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[282]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[281]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[281]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[280]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[280]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[279]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[279]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[278]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[278]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[277]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[277]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[276]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[276]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[275]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[275]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[274]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[274]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[273]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[273]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[272]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[272]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[271]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[271]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[270]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[270]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[269]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[269]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[268]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[268]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[267]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[267]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[266]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[266]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[265]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[265]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[264]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[264]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[263]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[263]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[262]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[262]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[261]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[261]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[260]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[260]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[259]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[259]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[258]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[258]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[257]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[257]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[256]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[256]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[255]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[255]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[254]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[254]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[253]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[253]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[252]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[252]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[251]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[251]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[250]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[250]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[249]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[249]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[248]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[248]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[247]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[247]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[246]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[246]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[245]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[245]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[244]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[244]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[243]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[243]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[242]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[242]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[241]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[241]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[240]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[240]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[239]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[239]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[238]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[238]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[237]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[237]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[236]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[236]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[235]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[235]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[234]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[234]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[233]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[233]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[232]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[232]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[231]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[231]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[230]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[230]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[229]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[229]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[228]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[228]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[227]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[227]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[226]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[226]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[225]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[225]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[224]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[224]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[223]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[223]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[222]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[222]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[221]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[221]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[220]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[220]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[219]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[219]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[218]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[218]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[217]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[217]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[216]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[216]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[215]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[215]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[214]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[214]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[213]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[213]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[212]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[212]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[211]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[211]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[210]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[210]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[209]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[209]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[208]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[208]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[207]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[207]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[206]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[206]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[205]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[205]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[204]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[204]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[203]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[203]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[202]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[202]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[201]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[201]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[200]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[200]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[199]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[199]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[198]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[198]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[197]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[197]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[196]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[196]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[195]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[195]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[194]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[194]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[193]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[193]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[192]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[192]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[191]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[191]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[190]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[190]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[189]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[189]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[188]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[188]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[187]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[187]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[186]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[186]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[185]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[185]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[184]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[184]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[183]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[183]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[182]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[182]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[181]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[181]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[180]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[180]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[179]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[179]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[178]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[178]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[177]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[177]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[176]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[176]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[175]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[175]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[174]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[174]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[173]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[173]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[172]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[172]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[171]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[171]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[170]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[170]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[169]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[169]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[168]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[168]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[167]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[167]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[166]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[166]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[165]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[165]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[164]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[164]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[163]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[163]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[162]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[162]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[161]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[161]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[160]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[160]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[159]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[159]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[158]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[158]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[157]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[157]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[156]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[156]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[155]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[155]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[154]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[154]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[153]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[153]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[152]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[152]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[151]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[151]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[150]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[150]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[149]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[149]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[148]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[148]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[147]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[147]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[146]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[146]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[145]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[145]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[144]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[144]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[143]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[143]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[142]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[142]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[141]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[141]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[140]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[140]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[139]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[139]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[138]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[138]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[137]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[137]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[136]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[136]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[135]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[135]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[134]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[134]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[133]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[133]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[132]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[132]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[131]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[131]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[130]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[130]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[129]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[129]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[128]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[128]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[127]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[127]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[126]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[126]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[125]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[125]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[124]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[124]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[123]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[123]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[122]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[122]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[121]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[121]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[120]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[120]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[119]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[119]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[118]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[118]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[117]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[117]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[116]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[116]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[115]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[115]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[114]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[114]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[113]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[113]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[112]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[112]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[111]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[111]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[110]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[110]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[109]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[109]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[108]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[107]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[106]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[105]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[104]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[103]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[102]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[101]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[100]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[99]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[98]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[97]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[96]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[95]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[94]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[93]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[92]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[91]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[90]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[89]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[88]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[87]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[86]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[85]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[84]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[83]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[82]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[81]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[80]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[79]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[78]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[77]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[76]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[75]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[74]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[73]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[72]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[71]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[70]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[69]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[68]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[67]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[66]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[65]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[64]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[127]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[127]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[126]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[126]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[125]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[125]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[124]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[124]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[123]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[123]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[122]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[122]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[121]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[121]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[120]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[120]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[119]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[119]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[118]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[118]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[117]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[117]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[116]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[116]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[115]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[115]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[114]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[114]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[113]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[113]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[112]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[112]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[111]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[111]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[110]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[110]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[109]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[109]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[108]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[107]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[106]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[105]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[104]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[103]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[102]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[101]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[100]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[99]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[98]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[97]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[96]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[95]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[94]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[93]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[92]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[91]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[90]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[89]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[88]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[87]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[86]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[85]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[84]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[83]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[82]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[81]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[80]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[79]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[78]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[77]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[76]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[75]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[74]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[73]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[72]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[71]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[70]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[69]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[68]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[67]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[66]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[65]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[64]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[0]}] +create_clock [get_ports clk_i] -name CLK -period 2.6 -waveform {0 1.3} +set_input_delay -clock CLK -max 0.6 [get_ports reset_i] +set_input_delay -clock CLK -min 0.6 [get_ports reset_i] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[133]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[133]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[132]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[132]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[131]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[131]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[130]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[130]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[129]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[129]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[128]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[128]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[127]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[127]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[126]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[126]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[125]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[125]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[124]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[124]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[123]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[123]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[122]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[122]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[121]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[121]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[120]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[120]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[119]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[119]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[118]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[118]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[117]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[117]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[116]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[116]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[115]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[115]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[114]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[114]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[113]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[113]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[112]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[112]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[111]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[111]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[110]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[110]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[109]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[109]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[108]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[108]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[107]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[107]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[106]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[106]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[105]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[105]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[104]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[104]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[103]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[103]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[102]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[102]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[101]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[101]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[100]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[100]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[99]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[99]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[98]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[98]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[97]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[97]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[96]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[96]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[95]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[95]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[94]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[94]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[93]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[93]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[92]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[92]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[91]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[91]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[90]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[90]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[89]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[89]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[88]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[88]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[87]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[87]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[86]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[86]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[85]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[85]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[84]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[84]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[83]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[83]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[82]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[82]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[81]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[81]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[80]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[80]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[79]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[79]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[78]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[78]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[77]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[77]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[76]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[76]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[75]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[75]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[74]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[74]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[73]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[73]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[72]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[72]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[71]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[71]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[70]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[70]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[69]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[69]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[68]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[68]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[67]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[67]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[66]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[66]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[65]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[65]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[64]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[64]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[63]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[63]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[62]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[62]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[61]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[61]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[60]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[60]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[59]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[59]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[58]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[58]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[57]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[57]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[56]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[56]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[55]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[55]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[54]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[54]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[53]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[53]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[52]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[52]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[51]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[51]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[50]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[50]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[49]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[49]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[48]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[48]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[47]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[47]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[46]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[46]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[45]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[45]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[44]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[44]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[43]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[43]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[42]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[42]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[41]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[41]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[40]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[40]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[39]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[39]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[38]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[38]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[37]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[37]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[36]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[36]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[35]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[34]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[33]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[32]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[31]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[30]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[29]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[28]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[27]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[26]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[25]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[24]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[23]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[22]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[21]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[20]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[19]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[18]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[17]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[16]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[15]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[14]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[13]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[12]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[11]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[10]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[9]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[8]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[7]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[6]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[5]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[4]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[3]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[2]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[1]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[0]}] +set_input_delay -clock CLK -max 0.6 [get_ports fe_queue_v_i] +set_input_delay -clock CLK -min 0.6 [get_ports fe_queue_v_i] +set_input_delay -clock CLK -max 0.6 [get_ports fe_cmd_ready_i] +set_input_delay -clock CLK -min 0.6 [get_ports fe_cmd_ready_i] +set_input_delay -clock CLK -max 0.6 [get_ports lce_req_ready_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_req_ready_i] +set_input_delay -clock CLK -max 0.6 [get_ports lce_resp_ready_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_resp_ready_i] +set_input_delay -clock CLK -max 0.6 [get_ports lce_data_resp_ready_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_data_resp_ready_i] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[35]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[34]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[33]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[32]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[31]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[30]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[29]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[28]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[27]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[26]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[25]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[24]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[23]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[22]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[21]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[20]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[19]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[18]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[17]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[16]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[15]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[14]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[13]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[12]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[11]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[10]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[9]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[8]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[7]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[6]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[5]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[4]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[3]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[2]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[1]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[0]}] +set_input_delay -clock CLK -max 0.6 [get_ports lce_cmd_v_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_cmd_v_i] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[539]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[539]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[538]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[538]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[537]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[537]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[536]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[536]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[535]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[535]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[534]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[534]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[533]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[533]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[532]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[532]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[531]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[531]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[530]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[530]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[529]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[529]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[528]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[528]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[527]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[527]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[526]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[526]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[525]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[525]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[524]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[524]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[523]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[523]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[522]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[522]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[521]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[521]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[520]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[520]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[519]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[519]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[518]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[518]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[517]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[517]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[516]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[516]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[515]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[515]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[514]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[514]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[513]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[513]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[512]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[512]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[511]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[511]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[510]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[510]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[509]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[509]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[508]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[508]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[507]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[507]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[506]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[506]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[505]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[505]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[504]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[504]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[503]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[503]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[502]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[502]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[501]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[501]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[500]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[500]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[499]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[499]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[498]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[498]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[497]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[497]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[496]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[496]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[495]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[495]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[494]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[494]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[493]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[493]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[492]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[492]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[491]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[491]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[490]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[490]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[489]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[489]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[488]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[488]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[487]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[487]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[486]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[486]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[485]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[485]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[484]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[484]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[483]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[483]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[482]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[482]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[481]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[481]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[480]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[480]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[479]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[479]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[478]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[478]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[477]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[477]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[476]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[476]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[475]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[475]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[474]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[474]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[473]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[473]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[472]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[472]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[471]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[471]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[470]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[470]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[469]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[469]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[468]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[468]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[467]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[467]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[466]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[466]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[465]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[465]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[464]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[464]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[463]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[463]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[462]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[462]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[461]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[461]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[460]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[460]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[459]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[459]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[458]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[458]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[457]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[457]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[456]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[456]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[455]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[455]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[454]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[454]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[453]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[453]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[452]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[452]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[451]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[451]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[450]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[450]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[449]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[449]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[448]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[448]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[447]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[447]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[446]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[446]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[445]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[445]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[444]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[444]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[443]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[443]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[442]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[442]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[441]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[441]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[440]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[440]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[439]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[439]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[438]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[438]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[437]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[437]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[436]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[436]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[435]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[435]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[434]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[434]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[433]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[433]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[432]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[432]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[431]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[431]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[430]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[430]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[429]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[429]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[428]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[428]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[427]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[427]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[426]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[426]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[425]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[425]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[424]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[424]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[423]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[423]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[422]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[422]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[421]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[421]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[420]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[420]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[419]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[419]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[418]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[418]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[417]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[417]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[416]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[416]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[415]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[415]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[414]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[414]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[413]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[413]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[412]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[412]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[411]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[411]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[410]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[410]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[409]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[409]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[408]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[408]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[407]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[407]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[406]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[406]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[405]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[405]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[404]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[404]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[403]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[403]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[402]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[402]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[401]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[401]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[400]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[400]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[399]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[399]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[398]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[398]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[397]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[397]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[396]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[396]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[395]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[395]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[394]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[394]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[393]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[393]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[392]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[392]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[391]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[391]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[390]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[390]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[389]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[389]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[388]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[388]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[387]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[387]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[386]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[386]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[385]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[385]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[384]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[384]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[383]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[383]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[382]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[382]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[381]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[381]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[380]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[380]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[379]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[379]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[378]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[378]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[377]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[377]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[376]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[376]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[375]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[375]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[374]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[374]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[373]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[373]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[372]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[372]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[371]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[371]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[370]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[370]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[369]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[369]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[368]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[368]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[367]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[367]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[366]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[366]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[365]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[365]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[364]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[364]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[363]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[363]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[362]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[362]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[361]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[361]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[360]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[360]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[359]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[359]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[358]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[358]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[357]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[357]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[356]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[356]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[355]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[355]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[354]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[354]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[353]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[353]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[352]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[352]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[351]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[351]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[350]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[350]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[349]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[349]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[348]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[348]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[347]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[347]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[346]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[346]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[345]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[345]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[344]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[344]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[343]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[343]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[342]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[342]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[341]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[341]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[340]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[340]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[339]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[339]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[338]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[338]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[337]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[337]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[336]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[336]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[335]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[335]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[334]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[334]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[333]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[333]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[332]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[332]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[331]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[331]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[330]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[330]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[329]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[329]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[328]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[328]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[327]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[327]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[326]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[326]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[325]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[325]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[324]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[324]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[323]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[323]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[322]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[322]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[321]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[321]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[320]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[320]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[319]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[319]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[318]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[318]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[317]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[317]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[316]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[316]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[315]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[315]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[314]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[314]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[313]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[313]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[312]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[312]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[311]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[311]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[310]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[310]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[309]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[309]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[308]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[308]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[307]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[307]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[306]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[306]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[305]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[305]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[304]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[304]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[303]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[303]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[302]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[302]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[301]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[301]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[300]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[300]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[299]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[299]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[298]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[298]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[297]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[297]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[296]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[296]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[295]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[295]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[294]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[294]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[293]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[293]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[292]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[292]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[291]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[291]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[290]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[290]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[289]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[289]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[288]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[288]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[287]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[287]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[286]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[286]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[285]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[285]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[284]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[284]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[283]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[283]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[282]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[282]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[281]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[281]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[280]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[280]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[279]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[279]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[278]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[278]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[277]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[277]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[276]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[276]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[275]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[275]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[274]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[274]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[273]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[273]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[272]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[272]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[271]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[271]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[270]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[270]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[269]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[269]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[268]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[268]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[267]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[267]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[266]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[266]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[265]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[265]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[264]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[264]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[263]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[263]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[262]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[262]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[261]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[261]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[260]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[260]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[259]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[259]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[258]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[258]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[257]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[257]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[256]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[256]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[255]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[255]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[254]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[254]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[253]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[253]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[252]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[252]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[251]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[251]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[250]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[250]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[249]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[249]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[248]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[248]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[247]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[247]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[246]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[246]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[245]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[245]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[244]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[244]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[243]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[243]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[242]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[242]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[241]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[241]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[240]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[240]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[239]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[239]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[238]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[238]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[237]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[237]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[236]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[236]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[235]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[235]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[234]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[234]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[233]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[233]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[232]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[232]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[231]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[231]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[230]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[230]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[229]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[229]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[228]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[228]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[227]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[227]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[226]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[226]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[225]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[225]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[224]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[224]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[223]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[223]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[222]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[222]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[221]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[221]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[220]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[220]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[219]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[219]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[218]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[218]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[217]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[217]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[216]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[216]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[215]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[215]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[214]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[214]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[213]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[213]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[212]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[212]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[211]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[211]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[210]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[210]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[209]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[209]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[208]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[208]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[207]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[207]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[206]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[206]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[205]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[205]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[204]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[204]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[203]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[203]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[202]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[202]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[201]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[201]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[200]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[200]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[199]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[199]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[198]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[198]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[197]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[197]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[196]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[196]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[195]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[195]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[194]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[194]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[193]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[193]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[192]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[192]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[191]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[191]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[190]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[190]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[189]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[189]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[188]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[188]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[187]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[187]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[186]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[186]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[185]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[185]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[184]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[184]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[183]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[183]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[182]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[182]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[181]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[181]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[180]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[180]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[179]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[179]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[178]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[178]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[177]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[177]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[176]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[176]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[175]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[175]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[174]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[174]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[173]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[173]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[172]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[172]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[171]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[171]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[170]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[170]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[169]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[169]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[168]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[168]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[167]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[167]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[166]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[166]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[165]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[165]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[164]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[164]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[163]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[163]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[162]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[162]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[161]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[161]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[160]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[160]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[159]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[159]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[158]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[158]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[157]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[157]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[156]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[156]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[155]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[155]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[154]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[154]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[153]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[153]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[152]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[152]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[151]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[151]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[150]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[150]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[149]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[149]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[148]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[148]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[147]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[147]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[146]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[146]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[145]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[145]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[144]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[144]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[143]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[143]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[142]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[142]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[141]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[141]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[140]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[140]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[139]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[139]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[138]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[138]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[137]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[137]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[136]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[136]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[135]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[135]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[134]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[134]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[133]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[133]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[132]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[132]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[131]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[131]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[130]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[130]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[129]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[129]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[128]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[128]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[127]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[127]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[126]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[126]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[125]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[125]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[124]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[124]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[123]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[123]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[122]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[122]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[121]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[121]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[120]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[120]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[119]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[119]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[118]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[118]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[117]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[117]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[116]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[116]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[115]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[115]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[114]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[114]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[113]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[113]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[112]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[112]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[111]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[111]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[110]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[110]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[109]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[109]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[108]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[108]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[107]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[107]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[106]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[106]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[105]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[105]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[104]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[104]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[103]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[103]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[102]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[102]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[101]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[101]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[100]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[100]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[99]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[99]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[98]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[98]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[97]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[97]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[96]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[96]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[95]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[95]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[94]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[94]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[93]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[93]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[92]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[92]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[91]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[91]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[90]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[90]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[89]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[89]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[88]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[88]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[87]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[87]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[86]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[86]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[85]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[85]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[84]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[84]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[83]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[83]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[82]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[82]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[81]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[81]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[80]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[80]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[79]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[79]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[78]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[78]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[77]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[77]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[76]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[76]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[75]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[75]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[74]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[74]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[73]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[73]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[72]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[72]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[71]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[71]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[70]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[70]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[69]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[69]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[68]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[68]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[67]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[67]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[66]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[66]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[65]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[65]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[64]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[64]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[63]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[63]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[62]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[62]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[61]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[61]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[60]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[60]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[59]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[59]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[58]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[58]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[57]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[57]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[56]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[56]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[55]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[55]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[54]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[54]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[53]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[53]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[52]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[52]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[51]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[51]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[50]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[50]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[49]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[49]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[48]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[48]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[47]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[47]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[46]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[46]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[45]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[45]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[44]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[44]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[43]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[43]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[42]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[42]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[41]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[41]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[40]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[40]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[39]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[39]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[38]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[38]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[37]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[37]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[36]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[36]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[35]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[34]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[33]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[32]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[31]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[30]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[29]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[28]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[27]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[26]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[25]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[24]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[23]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[22]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[21]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[20]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[19]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[18]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[17]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[16]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[15]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[14]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[13]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[12]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[11]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[10]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[9]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[8]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[7]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[6]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[5]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[4]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[3]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[2]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[1]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[0]}] +set_input_delay -clock CLK -max 0.6 [get_ports lce_data_cmd_v_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_data_cmd_v_i] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[538]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[538]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[537]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[537]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[536]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[536]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[535]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[535]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[534]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[534]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[533]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[533]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[532]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[532]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[531]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[531]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[530]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[530]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[529]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[529]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[528]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[528]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[527]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[527]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[526]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[526]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[525]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[525]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[524]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[524]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[523]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[523]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[522]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[522]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[521]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[521]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[520]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[520]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[519]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[519]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[518]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[518]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[517]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[517]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[516]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[516]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[515]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[515]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[514]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[514]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[513]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[513]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[512]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[512]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[511]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[511]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[510]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[510]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[509]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[509]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[508]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[508]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[507]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[507]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[506]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[506]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[505]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[505]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[504]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[504]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[503]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[503]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[502]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[502]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[501]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[501]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[500]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[500]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[499]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[499]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[498]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[498]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[497]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[497]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[496]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[496]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[495]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[495]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[494]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[494]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[493]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[493]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[492]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[492]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[491]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[491]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[490]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[490]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[489]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[489]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[488]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[488]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[487]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[487]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[486]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[486]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[485]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[485]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[484]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[484]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[483]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[483]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[482]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[482]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[481]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[481]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[480]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[480]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[479]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[479]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[478]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[478]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[477]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[477]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[476]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[476]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[475]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[475]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[474]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[474]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[473]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[473]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[472]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[472]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[471]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[471]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[470]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[470]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[469]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[469]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[468]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[468]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[467]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[467]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[466]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[466]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[465]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[465]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[464]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[464]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[463]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[463]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[462]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[462]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[461]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[461]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[460]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[460]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[459]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[459]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[458]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[458]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[457]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[457]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[456]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[456]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[455]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[455]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[454]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[454]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[453]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[453]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[452]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[452]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[451]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[451]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[450]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[450]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[449]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[449]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[448]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[448]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[447]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[447]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[446]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[446]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[445]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[445]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[444]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[444]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[443]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[443]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[442]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[442]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[441]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[441]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[440]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[440]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[439]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[439]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[438]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[438]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[437]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[437]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[436]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[436]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[435]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[435]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[434]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[434]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[433]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[433]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[432]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[432]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[431]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[431]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[430]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[430]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[429]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[429]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[428]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[428]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[427]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[427]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[426]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[426]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[425]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[425]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[424]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[424]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[423]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[423]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[422]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[422]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[421]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[421]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[420]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[420]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[419]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[419]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[418]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[418]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[417]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[417]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[416]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[416]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[415]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[415]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[414]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[414]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[413]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[413]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[412]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[412]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[411]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[411]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[410]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[410]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[409]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[409]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[408]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[408]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[407]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[407]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[406]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[406]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[405]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[405]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[404]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[404]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[403]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[403]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[402]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[402]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[401]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[401]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[400]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[400]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[399]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[399]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[398]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[398]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[397]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[397]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[396]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[396]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[395]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[395]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[394]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[394]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[393]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[393]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[392]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[392]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[391]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[391]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[390]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[390]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[389]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[389]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[388]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[388]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[387]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[387]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[386]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[386]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[385]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[385]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[384]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[384]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[383]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[383]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[382]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[382]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[381]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[381]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[380]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[380]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[379]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[379]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[378]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[378]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[377]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[377]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[376]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[376]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[375]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[375]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[374]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[374]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[373]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[373]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[372]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[372]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[371]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[371]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[370]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[370]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[369]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[369]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[368]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[368]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[367]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[367]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[366]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[366]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[365]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[365]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[364]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[364]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[363]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[363]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[362]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[362]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[361]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[361]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[360]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[360]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[359]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[359]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[358]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[358]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[357]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[357]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[356]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[356]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[355]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[355]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[354]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[354]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[353]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[353]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[352]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[352]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[351]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[351]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[350]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[350]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[349]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[349]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[348]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[348]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[347]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[347]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[346]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[346]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[345]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[345]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[344]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[344]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[343]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[343]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[342]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[342]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[341]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[341]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[340]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[340]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[339]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[339]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[338]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[338]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[337]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[337]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[336]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[336]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[335]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[335]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[334]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[334]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[333]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[333]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[332]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[332]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[331]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[331]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[330]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[330]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[329]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[329]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[328]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[328]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[327]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[327]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[326]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[326]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[325]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[325]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[324]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[324]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[323]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[323]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[322]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[322]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[321]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[321]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[320]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[320]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[319]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[319]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[318]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[318]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[317]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[317]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[316]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[316]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[315]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[315]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[314]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[314]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[313]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[313]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[312]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[312]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[311]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[311]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[310]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[310]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[309]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[309]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[308]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[308]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[307]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[307]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[306]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[306]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[305]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[305]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[304]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[304]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[303]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[303]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[302]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[302]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[301]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[301]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[300]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[300]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[299]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[299]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[298]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[298]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[297]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[297]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[296]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[296]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[295]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[295]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[294]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[294]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[293]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[293]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[292]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[292]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[291]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[291]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[290]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[290]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[289]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[289]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[288]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[288]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[287]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[287]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[286]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[286]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[285]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[285]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[284]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[284]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[283]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[283]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[282]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[282]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[281]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[281]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[280]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[280]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[279]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[279]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[278]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[278]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[277]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[277]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[276]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[276]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[275]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[275]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[274]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[274]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[273]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[273]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[272]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[272]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[271]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[271]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[270]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[270]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[269]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[269]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[268]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[268]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[267]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[267]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[266]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[266]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[265]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[265]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[264]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[264]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[263]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[263]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[262]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[262]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[261]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[261]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[260]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[260]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[259]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[259]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[258]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[258]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[257]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[257]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[256]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[256]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[255]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[255]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[254]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[254]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[253]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[253]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[252]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[252]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[251]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[251]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[250]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[250]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[249]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[249]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[248]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[248]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[247]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[247]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[246]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[246]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[245]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[245]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[244]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[244]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[243]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[243]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[242]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[242]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[241]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[241]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[240]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[240]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[239]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[239]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[238]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[238]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[237]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[237]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[236]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[236]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[235]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[235]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[234]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[234]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[233]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[233]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[232]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[232]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[231]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[231]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[230]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[230]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[229]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[229]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[228]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[228]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[227]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[227]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[226]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[226]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[225]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[225]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[224]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[224]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[223]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[223]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[222]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[222]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[221]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[221]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[220]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[220]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[219]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[219]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[218]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[218]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[217]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[217]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[216]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[216]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[215]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[215]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[214]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[214]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[213]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[213]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[212]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[212]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[211]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[211]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[210]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[210]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[209]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[209]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[208]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[208]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[207]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[207]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[206]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[206]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[205]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[205]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[204]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[204]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[203]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[203]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[202]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[202]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[201]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[201]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[200]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[200]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[199]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[199]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[198]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[198]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[197]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[197]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[196]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[196]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[195]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[195]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[194]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[194]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[193]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[193]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[192]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[192]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[191]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[191]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[190]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[190]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[189]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[189]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[188]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[188]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[187]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[187]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[186]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[186]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[185]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[185]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[184]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[184]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[183]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[183]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[182]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[182]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[181]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[181]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[180]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[180]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[179]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[179]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[178]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[178]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[177]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[177]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[176]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[176]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[175]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[175]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[174]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[174]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[173]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[173]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[172]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[172]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[171]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[171]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[170]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[170]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[169]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[169]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[168]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[168]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[167]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[167]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[166]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[166]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[165]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[165]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[164]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[164]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[163]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[163]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[162]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[162]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[161]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[161]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[160]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[160]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[159]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[159]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[158]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[158]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[157]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[157]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[156]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[156]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[155]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[155]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[154]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[154]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[153]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[153]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[152]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[152]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[151]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[151]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[150]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[150]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[149]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[149]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[148]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[148]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[147]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[147]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[146]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[146]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[145]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[145]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[144]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[144]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[143]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[143]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[142]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[142]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[141]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[141]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[140]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[140]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[139]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[139]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[138]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[138]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[137]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[137]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[136]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[136]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[135]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[135]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[134]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[134]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[133]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[133]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[132]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[132]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[131]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[131]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[130]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[130]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[129]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[129]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[128]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[128]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[127]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[127]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[126]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[126]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[125]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[125]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[124]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[124]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[123]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[123]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[122]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[122]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[121]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[121]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[120]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[120]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[119]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[119]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[118]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[118]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[117]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[117]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[116]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[116]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[115]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[115]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[114]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[114]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[113]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[113]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[112]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[112]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[111]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[111]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[110]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[110]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[109]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[109]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[108]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[108]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[107]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[107]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[106]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[106]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[105]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[105]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[104]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[104]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[103]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[103]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[102]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[102]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[101]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[101]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[100]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[100]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[99]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[99]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[98]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[98]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[97]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[97]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[96]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[96]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[95]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[95]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[94]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[94]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[93]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[93]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[92]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[92]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[91]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[91]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[90]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[90]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[89]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[89]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[88]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[88]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[87]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[87]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[86]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[86]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[85]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[85]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[84]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[84]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[83]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[83]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[82]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[82]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[81]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[81]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[80]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[80]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[79]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[79]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[78]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[78]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[77]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[77]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[76]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[76]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[75]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[75]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[74]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[74]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[73]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[73]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[72]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[72]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[71]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[71]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[70]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[70]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[69]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[69]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[68]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[68]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[67]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[67]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[66]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[66]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[65]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[65]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[64]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[64]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[63]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[63]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[62]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[62]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[61]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[61]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[60]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[60]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[59]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[59]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[58]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[58]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[57]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[57]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[56]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[56]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[55]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[55]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[54]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[54]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[53]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[53]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[52]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[52]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[51]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[51]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[50]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[50]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[49]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[49]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[48]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[48]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[47]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[47]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[46]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[46]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[45]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[45]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[44]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[44]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[43]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[43]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[42]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[42]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[41]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[41]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[40]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[40]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[39]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[39]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[38]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[38]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[37]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[37]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[36]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[36]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[35]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[34]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[33]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[32]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[31]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[30]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[29]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[28]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[27]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[26]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[25]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[24]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[23]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[22]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[21]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[20]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[19]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[18]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[17]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[16]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[15]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[14]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[13]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[12]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[11]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[10]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[9]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[8]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[7]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[6]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[5]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[4]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[3]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[2]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[1]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[0]}] +set_input_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_v_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_v_i] +set_input_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_ready_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_ready_i] +set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[2]}] +set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[1]}] +set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_ready_o] +set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_ready_o] +set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_clr_o] +set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_clr_o] +set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_dequeue_o] +set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_dequeue_o] +set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_rollback_o] +set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_rollback_o] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[108]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[108]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[107]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[107]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[106]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[106]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[105]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[105]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[104]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[104]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[103]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[103]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[102]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[102]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[101]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[101]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[100]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[100]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[99]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[99]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[98]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[98]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[97]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[97]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[96]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[96]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[95]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[95]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[94]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[94]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[93]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[93]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[92]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[92]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[91]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[91]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[90]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[90]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[89]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[89]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[88]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[88]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[87]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[87]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[86]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[86]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[85]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[85]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[84]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[84]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[83]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[83]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[82]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[82]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[81]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[81]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[80]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[80]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[79]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[79]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[78]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[78]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[77]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[77]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[76]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[76]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[75]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[75]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[74]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[74]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[73]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[73]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[72]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[72]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[71]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[71]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[70]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[70]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[69]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[69]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[68]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[68]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[67]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[67]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[66]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[66]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[65]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[65]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[64]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[64]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[63]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[62]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[61]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[60]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[59]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[58]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[57]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[56]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[55]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[54]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[53]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[52]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[51]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[50]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[49]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[48]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[47]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[46]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[45]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[44]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[43]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[42]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[41]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[40]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[39]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[38]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[37]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[36]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[35]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[34]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[33]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[32]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[31]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[30]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[29]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[28]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[27]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[26]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports fe_cmd_v_o] +set_output_delay -clock CLK -min 0.6 [get_ports fe_cmd_v_o] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[29]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[28]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[27]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[26]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports lce_req_v_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_req_v_o] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports lce_resp_v_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_resp_v_o] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[536]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[536]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[535]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[535]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[534]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[534]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[533]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[533]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[532]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[532]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[531]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[531]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[530]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[530]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[529]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[529]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[528]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[528]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[527]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[527]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[526]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[526]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[525]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[525]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[524]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[524]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[523]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[523]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[522]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[522]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[521]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[521]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[520]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[520]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[519]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[519]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[518]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[518]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[517]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[517]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[516]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[516]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[515]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[515]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[514]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[514]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[513]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[513]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[512]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[512]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[511]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[511]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[510]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[510]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[509]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[509]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[508]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[508]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[507]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[507]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[506]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[506]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[505]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[505]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[504]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[504]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[503]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[503]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[502]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[502]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[501]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[501]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[500]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[500]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[499]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[499]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[498]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[498]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[497]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[497]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[496]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[496]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[495]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[495]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[494]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[494]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[493]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[493]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[492]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[492]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[491]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[491]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[490]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[490]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[489]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[489]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[488]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[488]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[487]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[487]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[486]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[486]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[485]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[485]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[484]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[484]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[483]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[483]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[482]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[482]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[481]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[481]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[480]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[480]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[479]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[479]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[478]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[478]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[477]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[477]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[476]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[476]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[475]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[475]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[474]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[474]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[473]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[473]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[472]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[472]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[471]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[471]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[470]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[470]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[469]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[469]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[468]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[468]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[467]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[467]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[466]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[466]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[465]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[465]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[464]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[464]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[463]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[463]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[462]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[462]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[461]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[461]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[460]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[460]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[459]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[459]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[458]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[458]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[457]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[457]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[456]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[456]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[455]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[455]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[454]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[454]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[453]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[453]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[452]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[452]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[451]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[451]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[450]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[450]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[449]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[449]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[448]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[448]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[447]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[447]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[446]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[446]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[445]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[445]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[444]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[444]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[443]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[443]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[442]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[442]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[441]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[441]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[440]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[440]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[439]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[439]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[438]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[438]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[437]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[437]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[436]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[436]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[435]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[435]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[434]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[434]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[433]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[433]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[432]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[432]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[431]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[431]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[430]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[430]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[429]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[429]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[428]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[428]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[427]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[427]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[426]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[426]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[425]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[425]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[424]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[424]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[423]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[423]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[422]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[422]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[421]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[421]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[420]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[420]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[419]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[419]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[418]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[418]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[417]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[417]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[416]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[416]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[415]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[415]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[414]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[414]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[413]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[413]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[412]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[412]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[411]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[411]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[410]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[410]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[409]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[409]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[408]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[408]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[407]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[407]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[406]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[406]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[405]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[405]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[404]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[404]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[403]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[403]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[402]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[402]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[401]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[401]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[400]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[400]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[399]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[399]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[398]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[398]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[397]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[397]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[396]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[396]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[395]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[395]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[394]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[394]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[393]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[393]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[392]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[392]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[391]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[391]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[390]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[390]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[389]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[389]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[388]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[388]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[387]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[387]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[386]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[386]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[385]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[385]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[384]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[384]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[383]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[383]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[382]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[382]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[381]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[381]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[380]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[380]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[379]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[379]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[378]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[378]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[377]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[377]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[376]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[376]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[375]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[375]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[374]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[374]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[373]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[373]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[372]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[372]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[371]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[371]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[370]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[370]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[369]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[369]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[368]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[368]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[367]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[367]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[366]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[366]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[365]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[365]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[364]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[364]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[363]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[363]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[362]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[362]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[361]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[361]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[360]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[360]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[359]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[359]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[358]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[358]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[357]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[357]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[356]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[356]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[355]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[355]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[354]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[354]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[353]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[353]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[352]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[352]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[351]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[351]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[350]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[350]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[349]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[349]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[348]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[348]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[347]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[347]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[346]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[346]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[345]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[345]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[344]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[344]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[343]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[343]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[342]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[342]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[341]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[341]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[340]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[340]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[339]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[339]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[338]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[338]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[337]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[337]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[336]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[336]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[335]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[335]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[334]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[334]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[333]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[333]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[332]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[332]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[331]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[331]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[330]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[330]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[329]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[329]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[328]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[328]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[327]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[327]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[326]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[326]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[325]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[325]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[324]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[324]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[323]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[323]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[322]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[322]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[321]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[321]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[320]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[320]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[319]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[319]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[318]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[318]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[317]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[317]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[316]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[316]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[315]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[315]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[314]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[314]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[313]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[313]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[312]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[312]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[311]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[311]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[310]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[310]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[309]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[309]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[308]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[308]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[307]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[307]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[306]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[306]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[305]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[305]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[304]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[304]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[303]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[303]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[302]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[302]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[301]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[301]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[300]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[300]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[299]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[299]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[298]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[298]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[297]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[297]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[296]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[296]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[295]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[295]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[294]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[294]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[293]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[293]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[292]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[292]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[291]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[291]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[290]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[290]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[289]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[289]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[288]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[288]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[287]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[287]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[286]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[286]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[285]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[285]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[284]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[284]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[283]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[283]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[282]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[282]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[281]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[281]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[280]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[280]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[279]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[279]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[278]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[278]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[277]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[277]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[276]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[276]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[275]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[275]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[274]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[274]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[273]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[273]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[272]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[272]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[271]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[271]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[270]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[270]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[269]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[269]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[268]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[268]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[267]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[267]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[266]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[266]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[265]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[265]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[264]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[264]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[263]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[263]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[262]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[262]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[261]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[261]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[260]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[260]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[259]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[259]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[258]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[258]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[257]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[257]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[256]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[256]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[255]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[255]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[254]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[254]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[253]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[253]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[252]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[252]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[251]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[251]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[250]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[250]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[249]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[249]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[248]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[248]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[247]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[247]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[246]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[246]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[245]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[245]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[244]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[244]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[243]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[243]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[242]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[242]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[241]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[241]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[240]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[240]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[239]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[239]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[238]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[238]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[237]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[237]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[236]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[236]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[235]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[235]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[234]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[234]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[233]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[233]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[232]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[232]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[231]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[231]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[230]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[230]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[229]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[229]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[228]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[228]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[227]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[227]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[226]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[226]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[225]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[225]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[224]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[224]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[223]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[223]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[222]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[222]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[221]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[221]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[220]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[220]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[219]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[219]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[218]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[218]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[217]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[217]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[216]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[216]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[215]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[215]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[214]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[214]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[213]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[213]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[212]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[212]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[211]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[211]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[210]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[210]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[209]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[209]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[208]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[208]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[207]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[207]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[206]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[206]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[205]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[205]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[204]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[204]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[203]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[203]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[202]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[202]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[201]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[201]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[200]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[200]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[199]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[199]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[198]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[198]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[197]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[197]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[196]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[196]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[195]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[195]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[194]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[194]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[193]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[193]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[192]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[192]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[191]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[191]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[190]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[190]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[189]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[189]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[188]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[188]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[187]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[187]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[186]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[186]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[185]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[185]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[184]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[184]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[183]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[183]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[182]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[182]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[181]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[181]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[180]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[180]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[179]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[179]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[178]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[178]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[177]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[177]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[176]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[176]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[175]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[175]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[174]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[174]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[173]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[173]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[172]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[172]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[171]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[171]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[170]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[170]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[169]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[169]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[168]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[168]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[167]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[167]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[166]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[166]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[165]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[165]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[164]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[164]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[163]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[163]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[162]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[162]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[161]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[161]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[160]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[160]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[159]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[159]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[158]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[158]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[157]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[157]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[156]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[156]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[155]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[155]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[154]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[154]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[153]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[153]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[152]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[152]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[151]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[151]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[150]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[150]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[149]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[149]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[148]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[148]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[147]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[147]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[146]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[146]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[145]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[145]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[144]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[144]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[143]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[143]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[142]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[142]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[141]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[141]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[140]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[140]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[139]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[139]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[138]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[138]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[137]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[137]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[136]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[136]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[135]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[135]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[134]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[134]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[133]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[133]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[132]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[132]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[131]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[131]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[130]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[130]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[129]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[129]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[128]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[128]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[127]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[127]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[126]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[126]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[125]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[125]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[124]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[124]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[123]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[123]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[122]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[122]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[121]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[121]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[120]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[120]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[119]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[119]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[118]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[118]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[117]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[117]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[116]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[116]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[115]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[115]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[114]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[114]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[113]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[113]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[112]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[112]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[111]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[111]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[110]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[110]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[109]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[109]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[108]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[108]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[107]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[107]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[106]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[106]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[105]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[105]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[104]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[104]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[103]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[103]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[102]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[102]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[101]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[101]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[100]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[100]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[99]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[99]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[98]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[98]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[97]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[97]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[96]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[96]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[95]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[95]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[94]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[94]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[93]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[93]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[92]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[92]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[91]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[91]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[90]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[90]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[89]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[89]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[88]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[88]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[87]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[87]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[86]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[86]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[85]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[85]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[84]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[84]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[83]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[83]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[82]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[82]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[81]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[81]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[80]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[80]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[79]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[79]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[78]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[78]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[77]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[77]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[76]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[76]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[75]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[75]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[74]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[74]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[73]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[73]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[72]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[72]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[71]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[71]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[70]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[70]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[69]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[69]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[68]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[68]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[67]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[67]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[66]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[66]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[65]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[65]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[64]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[64]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[63]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[62]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[61]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[60]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[59]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[58]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[57]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[56]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[55]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[54]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[53]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[52]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[51]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[50]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[49]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[48]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[47]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[46]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[45]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[44]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[43]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[42]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[41]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[40]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[39]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[38]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[37]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[36]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[35]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[34]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[33]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[32]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[31]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[30]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[29]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[28]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[27]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[26]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports lce_data_resp_v_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_data_resp_v_o] +set_output_delay -clock CLK -max 0.6 [get_ports lce_cmd_ready_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_cmd_ready_o] +set_output_delay -clock CLK -max 0.6 [get_ports lce_data_cmd_ready_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_data_cmd_ready_o] +set_output_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_ready_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_ready_o] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[538]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[538]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[537]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[537]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[536]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[536]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[535]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[535]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[534]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[534]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[533]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[533]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[532]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[532]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[531]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[531]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[530]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[530]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[529]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[529]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[528]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[528]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[527]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[527]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[526]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[526]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[525]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[525]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[524]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[524]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[523]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[523]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[522]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[522]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[521]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[521]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[520]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[520]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[519]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[519]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[518]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[518]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[517]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[517]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[516]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[516]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[515]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[515]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[514]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[514]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[513]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[513]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[512]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[512]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[511]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[511]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[510]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[510]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[509]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[509]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[508]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[508]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[507]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[507]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[506]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[506]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[505]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[505]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[504]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[504]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[503]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[503]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[502]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[502]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[501]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[501]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[500]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[500]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[499]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[499]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[498]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[498]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[497]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[497]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[496]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[496]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[495]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[495]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[494]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[494]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[493]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[493]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[492]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[492]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[491]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[491]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[490]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[490]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[489]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[489]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[488]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[488]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[487]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[487]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[486]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[486]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[485]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[485]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[484]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[484]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[483]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[483]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[482]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[482]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[481]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[481]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[480]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[480]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[479]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[479]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[478]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[478]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[477]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[477]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[476]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[476]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[475]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[475]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[474]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[474]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[473]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[473]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[472]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[472]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[471]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[471]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[470]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[470]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[469]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[469]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[468]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[468]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[467]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[467]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[466]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[466]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[465]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[465]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[464]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[464]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[463]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[463]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[462]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[462]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[461]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[461]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[460]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[460]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[459]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[459]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[458]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[458]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[457]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[457]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[456]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[456]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[455]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[455]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[454]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[454]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[453]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[453]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[452]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[452]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[451]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[451]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[450]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[450]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[449]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[449]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[448]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[448]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[447]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[447]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[446]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[446]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[445]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[445]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[444]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[444]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[443]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[443]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[442]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[442]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[441]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[441]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[440]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[440]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[439]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[439]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[438]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[438]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[437]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[437]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[436]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[436]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[435]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[435]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[434]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[434]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[433]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[433]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[432]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[432]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[431]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[431]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[430]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[430]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[429]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[429]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[428]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[428]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[427]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[427]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[426]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[426]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[425]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[425]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[424]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[424]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[423]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[423]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[422]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[422]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[421]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[421]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[420]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[420]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[419]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[419]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[418]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[418]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[417]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[417]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[416]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[416]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[415]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[415]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[414]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[414]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[413]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[413]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[412]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[412]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[411]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[411]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[410]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[410]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[409]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[409]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[408]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[408]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[407]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[407]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[406]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[406]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[405]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[405]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[404]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[404]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[403]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[403]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[402]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[402]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[401]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[401]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[400]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[400]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[399]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[399]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[398]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[398]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[397]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[397]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[396]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[396]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[395]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[395]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[394]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[394]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[393]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[393]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[392]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[392]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[391]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[391]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[390]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[390]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[389]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[389]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[388]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[388]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[387]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[387]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[386]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[386]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[385]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[385]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[384]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[384]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[383]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[383]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[382]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[382]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[381]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[381]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[380]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[380]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[379]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[379]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[378]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[378]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[377]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[377]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[376]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[376]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[375]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[375]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[374]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[374]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[373]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[373]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[372]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[372]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[371]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[371]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[370]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[370]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[369]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[369]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[368]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[368]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[367]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[367]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[366]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[366]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[365]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[365]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[364]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[364]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[363]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[363]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[362]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[362]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[361]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[361]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[360]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[360]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[359]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[359]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[358]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[358]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[357]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[357]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[356]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[356]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[355]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[355]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[354]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[354]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[353]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[353]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[352]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[352]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[351]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[351]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[350]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[350]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[349]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[349]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[348]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[348]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[347]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[347]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[346]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[346]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[345]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[345]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[344]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[344]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[343]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[343]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[342]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[342]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[341]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[341]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[340]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[340]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[339]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[339]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[338]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[338]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[337]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[337]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[336]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[336]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[335]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[335]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[334]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[334]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[333]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[333]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[332]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[332]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[331]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[331]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[330]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[330]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[329]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[329]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[328]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[328]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[327]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[327]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[326]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[326]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[325]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[325]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[324]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[324]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[323]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[323]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[322]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[322]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[321]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[321]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[320]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[320]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[319]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[319]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[318]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[318]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[317]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[317]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[316]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[316]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[315]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[315]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[314]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[314]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[313]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[313]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[312]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[312]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[311]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[311]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[310]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[310]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[309]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[309]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[308]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[308]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[307]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[307]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[306]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[306]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[305]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[305]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[304]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[304]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[303]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[303]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[302]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[302]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[301]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[301]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[300]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[300]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[299]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[299]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[298]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[298]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[297]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[297]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[296]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[296]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[295]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[295]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[294]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[294]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[293]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[293]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[292]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[292]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[291]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[291]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[290]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[290]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[289]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[289]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[288]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[288]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[287]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[287]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[286]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[286]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[285]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[285]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[284]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[284]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[283]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[283]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[282]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[282]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[281]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[281]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[280]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[280]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[279]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[279]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[278]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[278]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[277]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[277]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[276]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[276]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[275]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[275]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[274]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[274]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[273]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[273]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[272]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[272]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[271]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[271]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[270]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[270]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[269]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[269]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[268]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[268]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[267]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[267]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[266]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[266]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[265]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[265]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[264]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[264]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[263]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[263]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[262]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[262]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[261]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[261]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[260]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[260]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[259]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[259]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[258]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[258]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[257]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[257]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[256]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[256]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[255]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[255]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[254]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[254]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[253]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[253]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[252]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[252]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[251]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[251]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[250]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[250]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[249]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[249]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[248]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[248]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[247]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[247]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[246]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[246]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[245]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[245]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[244]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[244]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[243]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[243]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[242]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[242]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[241]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[241]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[240]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[240]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[239]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[239]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[238]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[238]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[237]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[237]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[236]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[236]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[235]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[235]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[234]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[234]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[233]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[233]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[232]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[232]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[231]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[231]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[230]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[230]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[229]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[229]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[228]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[228]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[227]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[227]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[226]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[226]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[225]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[225]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[224]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[224]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[223]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[223]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[222]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[222]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[221]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[221]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[220]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[220]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[219]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[219]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[218]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[218]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[217]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[217]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[216]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[216]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[215]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[215]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[214]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[214]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[213]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[213]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[212]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[212]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[211]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[211]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[210]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[210]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[209]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[209]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[208]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[208]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[207]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[207]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[206]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[206]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[205]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[205]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[204]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[204]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[203]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[203]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[202]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[202]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[201]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[201]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[200]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[200]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[199]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[199]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[198]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[198]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[197]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[197]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[196]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[196]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[195]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[195]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[194]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[194]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[193]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[193]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[192]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[192]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[191]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[191]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[190]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[190]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[189]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[189]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[188]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[188]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[187]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[187]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[186]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[186]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[185]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[185]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[184]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[184]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[183]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[183]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[182]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[182]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[181]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[181]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[180]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[180]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[179]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[179]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[178]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[178]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[177]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[177]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[176]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[176]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[175]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[175]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[174]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[174]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[173]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[173]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[172]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[172]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[171]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[171]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[170]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[170]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[169]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[169]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[168]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[168]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[167]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[167]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[166]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[166]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[165]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[165]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[164]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[164]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[163]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[163]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[162]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[162]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[161]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[161]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[160]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[160]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[159]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[159]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[158]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[158]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[157]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[157]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[156]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[156]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[155]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[155]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[154]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[154]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[153]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[153]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[152]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[152]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[151]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[151]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[150]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[150]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[149]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[149]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[148]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[148]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[147]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[147]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[146]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[146]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[145]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[145]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[144]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[144]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[143]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[143]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[142]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[142]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[141]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[141]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[140]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[140]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[139]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[139]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[138]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[138]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[137]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[137]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[136]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[136]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[135]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[135]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[134]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[134]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[133]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[133]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[132]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[132]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[131]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[131]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[130]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[130]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[129]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[129]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[128]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[128]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[127]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[127]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[126]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[126]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[125]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[125]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[124]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[124]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[123]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[123]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[122]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[122]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[121]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[121]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[120]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[120]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[119]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[119]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[118]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[118]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[117]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[117]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[116]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[116]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[115]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[115]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[114]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[114]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[113]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[113]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[112]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[112]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[111]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[111]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[110]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[110]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[109]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[109]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[108]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[108]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[107]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[107]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[106]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[106]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[105]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[105]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[104]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[104]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[103]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[103]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[102]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[102]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[101]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[101]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[100]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[100]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[99]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[99]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[98]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[98]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[97]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[97]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[96]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[96]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[95]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[95]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[94]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[94]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[93]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[93]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[92]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[92]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[91]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[91]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[90]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[90]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[89]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[89]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[88]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[88]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[87]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[87]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[86]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[86]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[85]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[85]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[84]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[84]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[83]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[83]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[82]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[82]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[81]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[81]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[80]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[80]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[79]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[79]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[78]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[78]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[77]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[77]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[76]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[76]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[75]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[75]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[74]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[74]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[73]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[73]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[72]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[72]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[71]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[71]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[70]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[70]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[69]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[69]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[68]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[68]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[67]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[67]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[66]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[66]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[65]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[65]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[64]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[64]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[63]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[62]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[61]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[60]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[59]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[58]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[57]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[56]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[55]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[54]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[53]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[52]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[51]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[50]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[49]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[48]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[47]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[46]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[45]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[44]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[43]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[42]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[41]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[40]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[39]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[38]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[37]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[36]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[35]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[34]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[33]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[32]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[31]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[30]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[29]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[28]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[27]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[26]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_v_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_v_o] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[377]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[377]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[376]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[376]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[375]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[375]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[374]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[374]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[373]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[373]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[372]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[372]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[371]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[371]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[370]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[370]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[369]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[369]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[368]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[368]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[367]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[367]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[366]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[366]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[365]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[365]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[364]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[364]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[363]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[363]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[362]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[362]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[361]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[361]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[360]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[360]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[359]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[359]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[358]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[358]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[357]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[357]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[356]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[356]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[355]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[355]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[354]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[354]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[353]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[353]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[352]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[352]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[351]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[351]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[350]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[350]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[349]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[349]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[348]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[348]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[347]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[347]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[346]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[346]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[345]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[345]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[344]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[344]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[343]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[343]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[342]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[342]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[341]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[341]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[340]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[340]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[339]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[339]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[338]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[338]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[337]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[337]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[336]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[336]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[335]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[335]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[334]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[334]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[333]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[333]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[332]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[332]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[331]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[331]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[330]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[330]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[329]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[329]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[328]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[328]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[327]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[327]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[326]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[326]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[325]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[325]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[324]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[324]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[323]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[323]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[322]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[322]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[321]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[321]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[320]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[320]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[319]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[319]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[318]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[318]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[317]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[317]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[316]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[316]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[315]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[315]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[314]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[314]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[313]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[313]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[312]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[312]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[311]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[311]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[310]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[310]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[309]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[309]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[308]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[308]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[307]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[307]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[306]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[306]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[305]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[305]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[304]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[304]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[303]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[303]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[302]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[302]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[301]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[301]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[300]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[300]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[299]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[299]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[298]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[298]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[297]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[297]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[296]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[296]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[295]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[295]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[294]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[294]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[293]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[293]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[292]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[292]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[291]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[291]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[290]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[290]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[289]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[289]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[288]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[288]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[287]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[287]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[286]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[286]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[285]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[285]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[284]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[284]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[283]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[283]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[282]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[282]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[281]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[281]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[280]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[280]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[279]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[279]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[278]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[278]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[277]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[277]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[276]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[276]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[275]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[275]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[274]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[274]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[273]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[273]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[272]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[272]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[271]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[271]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[270]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[270]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[269]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[269]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[268]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[268]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[267]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[267]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[266]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[266]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[265]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[265]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[264]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[264]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[263]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[263]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[262]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[262]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[261]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[261]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[260]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[260]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[259]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[259]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[258]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[258]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[257]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[257]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[256]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[256]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[255]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[255]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[254]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[254]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[253]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[253]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[252]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[252]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[251]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[251]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[250]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[250]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[249]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[249]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[248]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[248]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[247]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[247]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[246]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[246]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[245]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[245]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[244]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[244]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[243]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[243]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[242]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[242]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[241]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[241]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[240]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[240]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[239]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[239]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[238]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[238]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[237]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[237]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[236]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[236]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[235]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[235]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[234]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[234]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[233]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[233]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[232]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[232]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[231]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[231]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[230]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[230]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[229]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[229]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[228]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[228]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[227]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[227]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[226]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[226]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[225]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[225]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[224]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[224]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[223]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[223]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[222]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[222]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[221]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[221]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[220]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[220]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[219]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[219]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[218]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[218]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[217]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[217]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[216]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[216]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[215]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[215]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[214]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[214]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[213]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[213]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[212]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[212]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[211]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[211]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[210]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[210]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[209]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[209]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[208]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[208]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[207]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[207]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[206]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[206]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[205]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[205]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[204]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[204]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[203]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[203]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[202]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[202]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[201]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[201]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[200]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[200]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[199]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[199]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[198]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[198]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[197]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[197]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[196]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[196]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[195]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[195]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[194]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[194]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[193]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[193]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[192]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[192]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[191]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[191]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[190]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[190]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[189]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[189]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[188]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[188]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[187]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[187]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[186]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[186]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[185]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[185]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[184]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[184]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[183]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[183]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[182]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[182]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[181]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[181]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[180]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[180]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[179]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[179]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[178]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[178]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[177]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[177]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[176]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[176]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[175]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[175]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[174]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[174]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[173]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[173]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[172]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[172]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[171]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[171]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[170]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[170]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[169]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[169]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[168]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[168]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[167]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[167]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[166]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[166]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[165]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[165]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[164]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[164]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[163]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[163]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[162]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[162]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[161]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[161]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[160]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[160]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[159]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[159]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[158]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[158]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[157]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[157]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[156]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[156]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[155]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[155]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[154]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[154]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[153]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[153]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[152]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[152]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[151]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[151]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[150]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[150]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[149]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[149]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[148]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[148]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[147]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[147]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[146]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[146]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[145]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[145]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[144]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[144]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[143]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[143]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[142]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[142]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[141]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[141]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[140]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[140]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[139]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[139]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[138]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[138]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[137]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[137]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[136]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[136]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[135]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[135]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[134]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[134]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[133]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[133]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[132]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[132]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[131]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[131]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[130]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[130]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[129]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[129]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[128]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[128]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[127]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[127]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[126]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[126]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[125]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[125]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[124]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[124]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[123]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[123]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[122]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[122]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[121]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[121]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[120]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[120]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[119]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[119]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[118]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[118]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[117]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[117]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[116]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[116]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[115]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[115]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[114]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[114]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[113]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[113]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[112]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[112]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[111]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[111]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[110]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[110]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[109]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[109]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[108]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[108]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[107]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[107]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[106]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[106]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[105]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[105]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[104]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[104]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[103]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[103]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[102]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[102]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[101]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[101]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[100]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[100]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[99]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[99]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[98]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[98]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[97]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[97]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[96]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[96]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[95]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[95]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[94]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[94]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[93]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[93]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[92]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[92]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[91]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[91]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[90]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[90]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[89]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[89]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[88]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[88]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[87]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[87]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[86]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[86]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[85]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[85]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[84]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[84]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[83]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[83]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[82]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[82]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[81]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[81]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[80]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[80]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[79]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[79]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[78]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[78]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[77]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[77]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[76]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[76]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[75]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[75]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[74]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[74]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[73]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[73]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[72]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[72]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[71]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[71]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[70]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[70]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[69]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[69]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[68]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[68]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[67]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[67]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[66]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[66]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[65]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[65]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[64]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[64]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[63]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[62]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[61]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[60]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[59]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[58]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[57]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[56]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[55]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[54]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[53]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[52]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[51]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[50]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[49]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[48]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[47]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[46]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[45]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[44]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[43]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[42]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[41]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[40]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[39]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[38]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[37]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[36]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[35]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[34]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[33]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[32]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[31]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[30]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[29]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[28]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[27]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[26]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[127]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[127]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[126]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[126]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[125]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[125]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[124]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[124]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[123]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[123]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[122]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[122]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[121]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[121]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[120]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[120]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[119]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[119]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[118]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[118]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[117]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[117]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[116]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[116]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[115]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[115]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[114]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[114]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[113]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[113]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[112]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[112]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[111]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[111]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[110]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[110]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[109]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[109]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[108]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[108]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[107]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[107]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[106]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[106]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[105]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[105]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[104]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[104]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[103]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[103]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[102]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[102]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[101]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[101]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[100]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[100]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[99]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[99]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[98]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[98]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[97]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[97]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[96]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[96]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[95]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[95]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[94]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[94]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[93]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[93]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[92]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[92]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[91]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[91]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[90]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[90]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[89]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[89]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[88]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[88]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[87]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[87]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[86]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[86]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[85]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[85]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[84]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[84]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[83]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[83]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[82]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[82]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[81]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[81]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[80]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[80]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[79]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[79]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[78]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[78]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[77]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[77]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[76]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[76]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[75]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[75]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[74]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[74]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[73]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[73]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[72]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[72]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[71]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[71]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[70]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[70]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[69]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[69]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[68]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[68]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[67]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[67]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[66]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[66]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[65]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[65]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[64]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[64]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[63]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[62]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[61]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[60]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[59]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[58]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[57]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[56]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[55]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[54]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[53]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[52]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[51]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[50]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[49]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[48]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[47]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[46]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[45]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[44]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[43]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[42]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[41]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[40]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[39]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[38]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[37]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[36]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[35]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[34]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[33]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[32]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[31]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[30]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[29]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[28]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[27]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[26]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[0]}] diff --git a/flow/designs/nangate45/bp_be_top/io.tcl b/flow/designs/nangate45/bp_be_top/io.tcl index b3bbef4631..713f1d0db0 100644 --- a/flow/designs/nangate45/bp_be_top/io.tcl +++ b/flow/designs/nangate45/bp_be_top/io.tcl @@ -1 +1 @@ -exclude_io_pin_region -region left:500-800 -region right:500-800 -region top:* \ No newline at end of file +exclude_io_pin_region -region left:500-800 -region right:500-800 -region top:* diff --git a/flow/designs/nangate45/bp_fe_top/constraint.sdc b/flow/designs/nangate45/bp_fe_top/constraint.sdc index b2d5405cf1..7428491fbe 100644 --- a/flow/designs/nangate45/bp_fe_top/constraint.sdc +++ b/flow/designs/nangate45/bp_fe_top/constraint.sdc @@ -1,4 +1,3 @@ - set clk_period 1.8 create_clock [get_ports clk_i] -name CLK -period $clk_period set io_delay [expr $clk_period * .2] diff --git a/flow/designs/nangate45/bp_fe_top/io.tcl b/flow/designs/nangate45/bp_fe_top/io.tcl index 8e24fc28ea..82d99e921d 100644 --- a/flow/designs/nangate45/bp_fe_top/io.tcl +++ b/flow/designs/nangate45/bp_fe_top/io.tcl @@ -1 +1 @@ -exclude_io_pin_region -region left:400-700 -region right:400-700 -region top:* \ No newline at end of file +exclude_io_pin_region -region left:400-700 -region right:400-700 -region top:* diff --git a/flow/designs/nangate45/bp_multi_top/constraint.sdc b/flow/designs/nangate45/bp_multi_top/constraint.sdc index f9be728c02..24d87fe369 100644 --- a/flow/designs/nangate45/bp_multi_top/constraint.sdc +++ b/flow/designs/nangate45/bp_multi_top/constraint.sdc @@ -1,2906 +1,2905 @@ - -create_clock [get_ports clk_i] -name CLK -period 4.8 -waveform {0 2.4} -set_input_delay -clock CLK -max 1.8 [get_ports reset_i] -set_input_delay -clock CLK -min 0.6 [get_ports reset_i] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[95]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[95]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[94]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[94]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[93]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[93]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[92]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[92]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[91]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[91]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[90]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[90]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[89]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[89]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[88]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[88]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[87]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[87]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[86]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[86]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[85]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[85]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[84]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[84]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[83]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[83]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[82]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[82]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[81]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[81]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[80]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[80]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[79]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[79]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[78]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[78]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[77]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[77]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[76]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[76]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[75]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[75]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[74]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[74]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[73]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[73]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[72]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[72]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[71]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[71]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[70]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[70]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[69]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[69]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[68]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[68]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[67]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[67]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[66]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[66]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[65]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[65]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[64]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[64]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[63]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[63]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[62]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[62]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[61]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[61]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[60]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[60]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[59]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[59]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[58]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[58]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[57]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[57]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[56]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[56]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[55]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[55]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[54]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[54]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[53]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[53]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[52]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[52]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[51]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[51]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[50]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[50]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[49]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[49]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[48]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[48]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[47]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[47]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[46]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[46]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[45]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[45]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[44]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[44]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[43]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[43]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[42]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[42]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[41]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[41]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[40]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[40]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[39]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[39]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[38]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[38]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[37]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[37]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[36]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[36]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[35]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[34]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[33]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[32]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[31]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[30]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[29]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[28]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[27]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[26]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[25]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[24]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[23]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[22]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[21]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[20]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[19]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[18]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[17]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[16]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[15]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[14]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[13]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[12]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[11]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[10]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[9]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[8]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[7]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[6]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[5]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[4]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[3]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[2]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[1]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[57]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[57]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[56]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[56]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[55]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[55]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[54]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[54]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[53]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[53]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[52]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[52]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[51]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[51]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[50]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[50]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[49]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[49]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[48]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[48]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[47]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[47]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[46]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[46]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[45]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[45]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[44]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[44]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[43]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[43]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[42]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[42]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[41]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[41]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[40]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[40]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[39]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[39]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[38]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[38]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[37]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[37]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[36]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[36]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[35]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[34]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[33]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[32]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[31]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[30]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[29]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[28]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[27]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[26]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[25]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[24]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[23]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[22]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[21]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[20]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[19]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[18]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[17]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[16]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[15]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[14]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[13]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[12]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[11]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[10]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[9]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[8]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[7]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[6]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[5]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[4]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[3]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[2]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[1]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_v_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_v_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[541]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[541]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[540]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[540]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[539]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[539]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[538]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[538]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[537]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[537]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[536]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[536]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[535]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[535]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[534]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[534]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[533]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[533]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[532]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[532]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[531]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[531]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[530]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[530]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[529]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[529]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[528]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[528]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[527]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[527]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[526]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[526]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[525]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[525]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[524]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[524]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[523]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[523]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[522]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[522]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[521]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[521]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[520]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[520]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[519]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[519]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[518]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[518]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[517]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[517]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[516]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[516]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[515]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[515]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[514]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[514]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[513]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[513]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[512]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[512]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[511]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[511]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[510]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[510]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[509]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[509]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[508]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[508]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[507]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[507]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[506]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[506]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[505]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[505]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[504]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[504]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[503]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[503]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[502]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[502]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[501]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[501]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[500]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[500]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[499]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[499]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[498]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[498]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[497]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[497]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[496]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[496]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[495]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[495]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[494]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[494]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[493]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[493]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[492]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[492]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[491]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[491]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[490]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[490]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[489]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[489]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[488]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[488]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[487]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[487]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[486]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[486]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[485]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[485]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[484]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[484]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[483]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[483]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[482]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[482]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[481]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[481]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[480]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[480]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[479]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[479]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[478]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[478]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[477]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[477]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[476]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[476]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[475]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[475]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[474]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[474]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[473]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[473]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[472]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[472]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[471]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[471]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[470]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[470]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[469]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[469]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[468]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[468]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[467]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[467]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[466]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[466]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[465]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[465]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[464]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[464]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[463]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[463]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[462]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[462]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[461]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[461]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[460]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[460]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[459]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[459]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[458]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[458]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[457]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[457]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[456]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[456]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[455]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[455]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[454]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[454]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[453]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[453]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[452]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[452]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[451]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[451]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[450]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[450]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[449]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[449]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[448]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[448]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[447]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[447]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[446]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[446]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[445]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[445]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[444]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[444]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[443]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[443]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[442]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[442]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[441]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[441]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[440]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[440]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[439]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[439]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[438]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[438]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[437]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[437]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[436]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[436]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[435]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[435]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[434]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[434]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[433]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[433]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[432]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[432]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[431]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[431]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[430]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[430]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[429]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[429]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[428]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[428]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[427]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[427]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[426]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[426]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[425]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[425]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[424]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[424]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[423]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[423]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[422]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[422]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[421]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[421]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[420]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[420]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[419]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[419]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[418]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[418]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[417]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[417]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[416]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[416]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[415]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[415]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[414]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[414]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[413]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[413]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[412]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[412]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[411]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[411]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[410]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[410]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[409]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[409]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[408]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[408]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[407]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[407]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[406]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[406]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[405]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[405]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[404]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[404]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[403]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[403]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[402]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[402]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[401]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[401]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[400]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[400]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[399]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[399]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[398]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[398]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[397]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[397]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[396]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[396]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[395]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[395]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[394]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[394]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[393]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[393]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[392]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[392]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[391]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[391]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[390]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[390]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[389]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[389]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[388]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[388]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[387]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[387]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[386]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[386]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[385]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[385]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[384]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[384]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[383]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[383]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[382]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[382]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[381]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[381]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[380]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[380]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[379]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[379]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[378]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[378]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[377]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[377]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[376]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[376]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[375]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[375]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[374]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[374]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[373]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[373]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[372]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[372]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[371]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[371]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[370]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[370]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[369]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[369]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[368]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[368]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[367]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[367]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[366]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[366]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[365]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[365]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[364]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[364]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[363]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[363]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[362]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[362]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[361]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[361]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[360]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[360]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[359]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[359]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[358]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[358]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[357]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[357]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[356]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[356]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[355]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[355]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[354]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[354]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[353]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[353]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[352]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[352]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[351]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[351]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[350]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[350]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[349]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[349]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[348]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[348]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[347]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[347]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[346]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[346]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[345]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[345]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[344]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[344]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[343]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[343]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[342]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[342]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[341]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[341]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[340]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[340]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[339]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[339]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[338]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[338]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[337]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[337]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[336]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[336]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[335]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[335]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[334]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[334]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[333]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[333]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[332]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[332]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[331]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[331]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[330]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[330]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[329]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[329]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[328]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[328]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[327]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[327]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[326]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[326]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[325]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[325]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[324]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[324]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[323]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[323]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[322]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[322]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[321]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[321]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[320]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[320]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[319]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[319]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[318]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[318]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[317]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[317]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[316]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[316]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[315]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[315]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[314]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[314]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[313]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[313]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[312]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[312]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[311]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[311]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[310]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[310]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[309]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[309]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[308]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[308]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[307]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[307]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[306]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[306]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[305]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[305]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[304]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[304]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[303]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[303]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[302]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[302]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[301]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[301]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[300]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[300]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[299]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[299]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[298]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[298]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[297]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[297]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[296]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[296]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[295]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[295]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[294]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[294]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[293]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[293]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[292]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[292]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[291]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[291]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[290]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[290]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[289]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[289]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[288]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[288]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[287]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[287]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[286]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[286]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[285]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[285]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[284]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[284]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[283]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[283]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[282]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[282]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[281]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[281]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[280]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[280]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[279]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[279]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[278]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[278]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[277]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[277]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[276]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[276]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[275]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[275]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[274]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[274]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[273]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[273]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[272]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[272]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[271]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[271]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[270]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[270]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[269]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[269]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[268]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[268]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[267]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[267]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[266]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[266]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[265]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[265]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[264]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[264]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[263]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[263]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[262]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[262]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[261]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[261]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[260]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[260]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[259]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[259]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[258]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[258]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[257]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[257]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[256]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[256]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[255]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[255]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[254]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[254]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[253]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[253]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[252]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[252]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[251]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[251]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[250]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[250]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[249]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[249]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[248]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[248]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[247]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[247]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[246]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[246]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[245]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[245]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[244]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[244]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[243]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[243]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[242]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[242]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[241]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[241]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[240]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[240]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[239]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[239]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[238]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[238]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[237]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[237]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[236]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[236]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[235]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[235]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[234]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[234]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[233]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[233]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[232]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[232]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[231]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[231]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[230]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[230]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[229]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[229]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[228]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[228]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[227]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[227]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[226]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[226]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[225]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[225]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[224]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[224]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[223]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[223]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[222]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[222]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[221]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[221]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[220]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[220]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[219]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[219]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[218]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[218]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[217]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[217]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[216]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[216]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[215]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[215]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[214]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[214]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[213]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[213]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[212]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[212]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[211]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[211]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[210]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[210]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[209]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[209]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[208]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[208]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[207]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[207]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[206]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[206]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[205]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[205]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[204]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[204]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[203]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[203]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[202]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[202]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[201]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[201]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[200]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[200]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[199]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[199]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[198]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[198]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[197]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[197]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[196]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[196]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[195]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[195]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[194]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[194]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[193]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[193]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[192]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[192]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[191]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[191]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[190]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[190]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[189]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[189]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[188]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[188]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[187]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[187]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[186]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[186]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[185]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[185]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[184]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[184]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[183]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[183]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[182]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[182]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[181]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[181]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[180]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[180]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[179]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[179]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[178]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[178]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[177]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[177]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[176]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[176]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[175]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[175]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[174]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[174]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[173]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[173]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[172]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[172]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[171]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[171]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[170]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[170]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[169]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[169]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[168]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[168]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[167]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[167]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[166]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[166]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[165]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[165]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[164]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[164]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[163]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[163]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[162]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[162]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[161]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[161]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[160]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[160]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[159]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[159]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[158]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[158]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[157]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[157]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[156]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[156]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[155]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[155]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[154]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[154]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[153]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[153]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[152]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[152]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[151]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[151]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[150]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[150]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[149]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[149]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[148]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[148]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[147]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[147]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[146]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[146]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[145]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[145]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[144]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[144]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[143]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[143]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[142]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[142]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[141]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[141]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[140]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[140]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[139]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[139]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[138]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[138]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[137]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[137]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[136]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[136]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[135]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[135]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[134]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[134]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[133]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[133]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[132]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[132]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[131]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[131]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[130]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[130]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[129]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[129]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[128]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[128]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[127]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[127]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[126]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[126]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[125]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[125]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[124]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[124]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[123]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[123]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[122]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[122]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[121]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[121]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[120]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[120]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[119]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[119]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[118]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[118]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[117]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[117]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[116]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[116]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[115]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[115]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[114]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[114]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[113]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[113]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[112]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[112]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[111]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[111]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[110]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[110]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[109]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[109]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[108]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[108]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[107]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[107]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[106]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[106]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[105]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[105]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[104]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[104]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[103]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[103]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[102]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[102]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[101]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[101]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[100]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[100]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[99]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[99]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[98]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[98]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[97]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[97]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[96]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[96]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[95]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[95]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[94]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[94]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[93]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[93]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[92]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[92]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[91]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[91]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[90]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[90]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[89]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[89]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[88]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[88]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[87]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[87]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[86]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[86]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[85]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[85]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[84]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[84]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[83]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[83]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[82]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[82]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[81]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[81]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[80]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[80]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[79]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[79]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[78]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[78]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[77]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[77]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[76]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[76]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[75]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[75]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[74]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[74]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[73]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[73]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[72]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[72]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[71]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[71]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[70]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[70]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[69]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[69]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[68]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[68]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[67]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[67]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[66]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[66]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[65]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[65]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[64]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[64]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[63]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[63]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[62]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[62]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[61]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[61]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[60]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[60]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[59]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[59]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[58]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[58]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[57]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[57]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[56]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[56]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[55]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[55]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[54]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[54]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[53]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[53]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[52]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[52]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[51]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[51]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[50]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[50]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[49]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[49]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[48]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[48]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[47]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[47]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[46]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[46]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[45]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[45]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[44]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[44]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[43]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[43]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[42]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[42]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[41]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[41]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[40]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[40]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[39]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[39]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[38]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[38]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[37]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[37]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[36]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[36]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[35]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[34]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[33]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[32]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[31]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[30]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[29]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[28]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[27]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[26]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[25]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[24]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[23]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[22]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[21]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[20]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[19]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[18]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[17]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[16]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[15]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[14]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[13]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[12]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[11]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[10]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[9]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[8]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[7]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[6]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[5]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[4]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[3]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[2]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[1]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_v_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_v_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_cmd_yumi_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_cmd_yumi_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_yumi_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_yumi_i[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_resp_ready_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_resp_ready_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_ready_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_ready_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[29]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[28]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[27]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[26]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[25]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[24]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[23]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[22]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[21]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[20]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[19]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[18]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[17]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[16]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[15]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[14]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[13]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[12]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[11]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[10]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[9]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[8]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_v_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_v_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[569]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[569]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[568]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[568]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[567]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[567]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[566]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[566]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[565]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[565]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[564]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[564]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[563]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[563]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[562]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[562]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[561]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[561]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[560]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[560]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[559]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[559]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[558]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[558]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[557]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[557]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[556]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[556]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[555]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[555]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[554]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[554]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[553]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[553]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[552]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[552]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[551]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[551]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[550]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[550]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[549]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[549]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[548]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[548]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[547]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[547]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[546]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[546]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[545]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[545]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[544]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[544]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[543]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[543]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[542]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[542]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[541]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[541]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[540]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[540]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[539]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[539]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[538]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[538]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[537]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[537]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[536]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[536]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[535]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[535]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[534]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[534]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[533]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[533]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[532]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[532]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[531]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[531]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[530]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[530]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[529]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[529]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[528]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[528]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[527]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[527]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[526]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[526]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[525]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[525]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[524]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[524]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[523]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[523]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[522]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[522]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[521]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[521]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[520]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[520]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[519]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[519]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[518]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[518]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[517]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[517]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[516]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[516]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[515]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[515]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[514]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[514]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[513]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[513]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[512]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[512]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[511]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[511]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[510]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[510]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[509]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[509]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[508]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[508]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[507]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[507]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[506]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[506]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[505]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[505]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[504]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[504]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[503]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[503]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[502]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[502]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[501]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[501]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[500]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[500]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[499]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[499]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[498]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[498]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[497]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[497]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[496]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[496]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[495]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[495]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[494]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[494]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[493]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[493]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[492]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[492]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[491]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[491]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[490]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[490]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[489]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[489]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[488]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[488]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[487]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[487]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[486]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[486]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[485]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[485]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[484]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[484]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[483]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[483]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[482]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[482]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[481]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[481]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[480]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[480]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[479]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[479]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[478]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[478]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[477]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[477]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[476]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[476]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[475]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[475]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[474]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[474]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[473]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[473]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[472]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[472]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[471]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[471]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[470]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[470]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[469]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[469]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[468]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[468]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[467]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[467]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[466]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[466]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[465]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[465]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[464]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[464]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[463]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[463]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[462]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[462]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[461]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[461]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[460]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[460]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[459]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[459]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[458]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[458]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[457]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[457]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[456]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[456]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[455]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[455]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[454]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[454]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[453]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[453]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[452]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[452]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[451]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[451]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[450]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[450]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[449]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[449]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[448]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[448]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[447]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[447]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[446]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[446]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[445]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[445]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[444]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[444]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[443]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[443]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[442]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[442]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[441]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[441]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[440]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[440]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[439]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[439]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[438]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[438]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[437]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[437]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[436]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[436]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[435]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[435]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[434]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[434]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[433]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[433]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[432]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[432]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[431]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[431]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[430]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[430]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[429]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[429]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[428]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[428]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[427]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[427]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[426]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[426]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[425]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[425]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[424]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[424]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[423]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[423]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[422]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[422]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[421]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[421]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[420]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[420]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[419]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[419]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[418]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[418]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[417]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[417]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[416]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[416]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[415]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[415]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[414]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[414]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[413]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[413]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[412]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[412]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[411]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[411]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[410]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[410]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[409]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[409]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[408]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[408]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[407]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[407]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[406]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[406]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[405]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[405]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[404]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[404]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[403]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[403]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[402]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[402]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[401]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[401]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[400]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[400]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[399]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[399]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[398]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[398]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[397]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[397]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[396]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[396]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[395]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[395]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[394]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[394]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[393]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[393]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[392]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[392]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[391]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[391]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[390]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[390]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[389]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[389]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[388]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[388]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[387]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[387]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[386]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[386]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[385]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[385]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[384]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[384]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[383]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[383]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[382]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[382]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[381]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[381]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[380]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[380]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[379]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[379]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[378]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[378]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[377]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[377]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[376]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[376]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[375]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[375]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[374]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[374]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[373]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[373]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[372]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[372]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[371]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[371]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[370]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[370]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[369]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[369]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[368]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[368]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[367]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[367]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[366]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[366]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[365]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[365]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[364]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[364]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[363]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[363]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[362]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[362]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[361]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[361]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[360]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[360]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[359]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[359]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[358]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[358]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[357]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[357]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[356]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[356]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[355]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[355]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[354]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[354]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[353]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[353]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[352]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[352]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[351]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[351]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[350]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[350]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[349]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[349]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[348]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[348]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[347]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[347]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[346]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[346]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[345]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[345]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[344]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[344]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[343]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[343]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[342]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[342]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[341]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[341]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[340]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[340]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[339]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[339]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[338]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[338]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[337]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[337]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[336]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[336]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[335]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[335]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[334]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[334]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[333]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[333]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[332]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[332]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[331]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[331]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[330]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[330]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[329]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[329]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[328]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[328]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[327]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[327]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[326]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[326]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[325]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[325]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[324]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[324]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[323]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[323]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[322]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[322]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[321]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[321]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[320]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[320]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[319]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[319]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[318]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[318]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[317]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[317]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[316]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[316]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[315]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[315]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[314]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[314]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[313]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[313]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[312]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[312]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[311]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[311]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[310]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[310]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[309]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[309]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[308]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[308]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[307]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[307]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[306]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[306]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[305]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[305]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[304]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[304]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[303]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[303]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[302]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[302]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[301]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[301]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[300]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[300]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[299]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[299]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[298]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[298]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[297]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[297]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[296]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[296]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[295]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[295]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[294]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[294]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[293]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[293]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[292]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[292]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[291]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[291]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[290]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[290]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[289]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[289]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[288]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[288]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[287]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[287]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[286]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[286]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[285]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[285]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[284]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[284]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[283]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[283]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[282]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[282]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[281]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[281]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[280]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[280]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[279]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[279]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[278]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[278]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[277]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[277]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[276]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[276]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[275]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[275]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[274]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[274]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[273]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[273]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[272]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[272]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[271]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[271]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[270]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[270]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[269]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[269]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[268]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[268]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[267]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[267]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[266]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[266]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[265]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[265]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[264]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[264]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[263]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[263]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[262]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[262]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[261]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[261]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[260]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[260]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[259]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[259]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[258]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[258]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[257]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[257]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[256]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[256]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[255]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[255]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[254]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[254]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[253]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[253]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[252]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[252]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[251]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[251]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[250]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[250]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[249]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[249]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[248]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[248]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[247]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[247]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[246]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[246]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[245]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[245]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[244]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[244]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[243]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[243]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[242]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[242]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[241]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[241]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[240]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[240]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[239]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[239]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[238]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[238]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[237]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[237]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[236]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[236]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[235]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[235]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[234]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[234]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[233]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[233]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[232]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[232]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[231]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[231]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[230]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[230]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[229]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[229]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[228]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[228]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[227]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[227]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[226]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[226]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[225]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[225]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[224]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[224]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[223]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[223]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[222]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[222]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[221]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[221]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[220]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[220]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[219]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[219]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[218]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[218]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[217]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[217]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[216]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[216]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[215]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[215]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[214]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[214]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[213]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[213]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[212]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[212]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[211]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[211]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[210]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[210]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[209]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[209]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[208]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[208]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[207]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[207]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[206]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[206]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[205]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[205]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[204]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[204]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[203]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[203]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[202]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[202]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[201]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[201]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[200]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[200]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[199]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[199]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[198]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[198]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[197]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[197]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[196]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[196]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[195]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[195]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[194]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[194]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[193]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[193]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[192]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[192]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[191]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[191]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[190]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[190]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[189]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[189]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[188]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[188]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[187]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[187]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[186]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[186]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[185]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[185]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[184]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[184]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[183]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[183]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[182]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[182]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[181]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[181]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[180]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[180]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[179]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[179]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[178]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[178]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[177]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[177]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[176]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[176]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[175]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[175]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[174]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[174]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[173]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[173]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[172]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[172]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[171]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[171]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[170]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[170]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[169]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[169]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[168]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[168]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[167]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[167]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[166]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[166]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[165]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[165]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[164]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[164]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[163]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[163]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[162]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[162]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[161]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[161]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[160]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[160]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[159]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[159]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[158]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[158]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[157]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[157]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[156]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[156]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[155]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[155]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[154]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[154]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[153]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[153]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[152]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[152]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[151]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[151]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[150]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[150]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[149]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[149]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[148]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[148]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[147]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[147]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[146]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[146]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[145]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[145]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[144]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[144]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[143]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[143]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[142]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[142]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[141]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[141]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[140]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[140]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[139]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[139]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[138]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[138]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[137]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[137]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[136]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[136]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[135]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[135]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[134]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[134]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[133]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[133]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[132]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[132]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[131]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[131]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[130]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[130]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[129]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[129]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[128]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[128]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[127]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[127]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[126]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[126]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[125]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[125]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[124]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[124]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[123]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[123]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[122]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[122]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[121]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[121]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[120]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[120]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[119]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[119]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[118]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[118]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[117]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[117]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[116]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[116]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[115]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[115]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[114]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[114]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[113]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[113]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[112]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[112]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[111]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[111]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[110]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[110]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[109]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[109]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[108]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[108]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[107]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[107]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[106]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[106]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[105]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[105]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[104]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[104]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[103]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[103]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[102]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[102]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[101]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[101]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[100]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[100]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[99]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[99]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[98]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[98]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[97]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[97]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[96]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[96]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[95]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[95]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[94]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[94]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[93]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[93]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[92]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[92]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[91]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[91]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[90]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[90]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[89]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[89]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[88]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[88]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[87]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[87]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[86]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[86]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[85]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[85]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[84]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[84]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[83]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[83]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[82]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[82]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[81]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[81]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[80]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[80]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[79]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[79]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[78]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[78]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[77]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[77]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[76]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[76]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[75]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[75]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[74]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[74]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[73]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[73]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[72]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[72]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[71]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[71]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[70]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[70]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[69]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[69]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[68]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[68]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[67]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[67]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[66]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[66]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[65]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[65]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[64]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[64]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[63]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[62]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[61]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[60]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[59]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[58]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[57]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[56]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[55]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[54]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[53]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[52]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[51]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[50]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[49]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[48]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[47]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[46]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[45]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[44]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[43]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[42]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[41]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[40]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[39]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[38]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[37]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[36]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[35]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[34]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[33]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[32]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[31]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[30]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[29]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[28]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[27]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[26]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[25]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[24]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[23]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[22]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[21]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[20]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[19]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[18]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[17]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[16]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[15]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[14]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[13]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[12]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[11]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[10]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[9]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[8]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_v_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_v_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_w_v_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_w_v_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_w_v_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_w_v_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[63]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[62]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[61]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[60]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[59]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[58]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[57]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[56]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[55]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[54]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[53]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[52]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[51]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[50]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[49]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[48]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[47]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[46]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[45]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[44]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[43]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[42]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[41]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[40]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[39]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[38]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[37]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[36]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[35]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[34]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[33]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[32]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[31]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[30]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[29]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[28]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[27]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[26]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[25]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[24]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[23]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[22]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[21]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[20]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[19]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[18]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[17]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[16]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[15]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[14]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[13]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[12]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[11]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[10]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[9]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[8]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[63]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[62]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[61]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[60]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[59]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[58]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[57]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[56]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[55]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[54]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[53]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[52]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[51]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[50]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[49]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[48]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[47]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[46]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[45]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[44]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[43]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[42]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[41]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[40]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[39]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[38]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[37]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[36]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[35]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[34]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[33]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[32]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[31]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[30]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[29]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[28]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[27]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[26]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[25]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[24]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[23]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[22]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[21]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[20]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[19]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[18]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[17]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[16]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[15]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[14]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[13]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[12]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[11]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[10]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[9]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[8]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[0]}] +create_clock [get_ports clk_i] -name CLK -period 4.8 -waveform {0 2.4} +set_input_delay -clock CLK -max 1.8 [get_ports reset_i] +set_input_delay -clock CLK -min 0.6 [get_ports reset_i] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[95]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[95]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[94]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[94]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[93]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[93]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[92]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[92]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[91]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[91]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[90]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[90]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[89]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[89]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[88]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[88]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[87]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[87]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[86]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[86]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[85]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[85]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[84]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[84]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[83]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[83]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[82]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[82]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[81]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[81]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[80]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[80]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[79]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[79]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[78]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[78]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[77]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[77]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[76]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[76]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[75]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[75]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[74]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[74]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[73]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[73]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[72]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[72]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[71]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[71]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[70]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[70]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[69]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[69]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[68]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[68]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[67]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[67]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[66]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[66]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[65]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[65]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[64]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[64]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[63]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[63]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[62]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[62]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[61]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[61]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[60]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[60]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[59]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[59]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[58]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[58]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[57]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[57]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[56]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[56]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[55]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[55]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[54]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[54]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[53]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[53]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[52]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[52]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[51]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[51]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[50]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[50]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[49]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[49]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[48]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[48]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[47]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[47]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[46]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[46]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[45]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[45]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[44]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[44]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[43]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[43]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[42]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[42]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[41]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[41]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[40]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[40]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[39]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[39]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[38]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[38]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[37]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[37]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[36]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[36]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[35]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[34]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[33]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[32]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[31]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[30]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[29]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[28]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[27]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[26]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[25]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[24]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[23]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[22]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[21]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[20]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[19]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[18]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[17]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[16]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[15]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[14]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[13]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[12]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[11]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[10]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[9]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[8]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[7]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[6]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[5]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[4]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[3]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[2]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[1]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[0]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[57]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[57]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[56]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[56]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[55]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[55]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[54]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[54]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[53]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[53]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[52]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[52]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[51]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[51]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[50]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[50]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[49]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[49]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[48]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[48]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[47]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[47]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[46]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[46]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[45]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[45]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[44]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[44]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[43]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[43]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[42]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[42]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[41]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[41]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[40]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[40]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[39]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[39]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[38]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[38]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[37]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[37]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[36]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[36]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[35]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[34]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[33]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[32]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[31]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[30]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[29]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[28]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[27]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[26]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[25]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[24]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[23]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[22]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[21]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[20]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[19]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[18]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[17]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[16]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[15]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[14]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[13]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[12]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[11]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[10]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[9]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[8]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[7]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[6]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[5]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[4]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[3]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[2]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[1]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[0]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_v_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_v_i[0]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[541]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[541]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[540]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[540]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[539]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[539]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[538]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[538]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[537]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[537]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[536]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[536]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[535]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[535]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[534]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[534]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[533]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[533]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[532]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[532]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[531]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[531]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[530]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[530]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[529]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[529]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[528]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[528]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[527]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[527]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[526]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[526]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[525]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[525]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[524]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[524]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[523]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[523]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[522]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[522]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[521]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[521]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[520]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[520]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[519]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[519]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[518]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[518]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[517]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[517]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[516]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[516]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[515]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[515]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[514]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[514]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[513]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[513]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[512]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[512]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[511]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[511]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[510]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[510]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[509]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[509]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[508]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[508]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[507]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[507]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[506]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[506]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[505]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[505]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[504]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[504]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[503]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[503]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[502]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[502]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[501]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[501]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[500]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[500]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[499]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[499]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[498]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[498]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[497]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[497]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[496]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[496]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[495]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[495]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[494]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[494]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[493]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[493]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[492]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[492]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[491]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[491]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[490]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[490]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[489]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[489]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[488]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[488]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[487]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[487]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[486]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[486]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[485]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[485]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[484]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[484]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[483]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[483]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[482]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[482]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[481]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[481]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[480]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[480]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[479]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[479]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[478]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[478]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[477]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[477]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[476]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[476]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[475]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[475]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[474]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[474]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[473]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[473]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[472]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[472]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[471]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[471]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[470]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[470]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[469]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[469]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[468]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[468]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[467]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[467]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[466]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[466]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[465]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[465]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[464]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[464]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[463]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[463]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[462]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[462]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[461]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[461]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[460]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[460]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[459]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[459]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[458]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[458]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[457]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[457]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[456]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[456]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[455]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[455]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[454]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[454]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[453]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[453]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[452]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[452]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[451]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[451]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[450]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[450]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[449]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[449]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[448]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[448]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[447]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[447]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[446]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[446]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[445]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[445]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[444]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[444]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[443]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[443]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[442]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[442]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[441]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[441]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[440]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[440]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[439]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[439]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[438]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[438]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[437]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[437]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[436]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[436]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[435]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[435]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[434]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[434]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[433]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[433]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[432]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[432]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[431]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[431]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[430]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[430]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[429]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[429]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[428]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[428]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[427]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[427]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[426]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[426]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[425]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[425]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[424]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[424]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[423]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[423]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[422]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[422]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[421]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[421]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[420]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[420]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[419]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[419]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[418]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[418]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[417]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[417]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[416]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[416]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[415]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[415]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[414]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[414]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[413]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[413]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[412]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[412]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[411]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[411]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[410]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[410]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[409]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[409]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[408]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[408]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[407]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[407]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[406]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[406]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[405]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[405]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[404]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[404]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[403]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[403]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[402]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[402]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[401]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[401]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[400]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[400]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[399]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[399]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[398]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[398]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[397]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[397]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[396]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[396]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[395]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[395]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[394]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[394]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[393]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[393]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[392]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[392]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[391]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[391]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[390]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[390]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[389]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[389]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[388]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[388]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[387]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[387]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[386]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[386]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[385]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[385]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[384]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[384]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[383]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[383]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[382]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[382]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[381]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[381]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[380]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[380]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[379]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[379]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[378]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[378]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[377]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[377]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[376]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[376]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[375]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[375]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[374]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[374]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[373]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[373]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[372]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[372]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[371]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[371]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[370]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[370]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[369]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[369]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[368]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[368]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[367]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[367]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[366]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[366]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[365]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[365]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[364]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[364]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[363]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[363]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[362]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[362]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[361]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[361]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[360]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[360]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[359]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[359]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[358]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[358]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[357]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[357]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[356]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[356]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[355]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[355]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[354]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[354]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[353]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[353]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[352]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[352]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[351]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[351]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[350]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[350]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[349]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[349]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[348]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[348]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[347]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[347]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[346]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[346]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[345]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[345]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[344]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[344]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[343]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[343]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[342]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[342]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[341]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[341]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[340]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[340]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[339]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[339]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[338]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[338]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[337]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[337]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[336]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[336]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[335]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[335]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[334]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[334]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[333]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[333]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[332]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[332]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[331]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[331]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[330]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[330]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[329]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[329]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[328]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[328]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[327]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[327]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[326]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[326]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[325]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[325]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[324]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[324]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[323]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[323]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[322]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[322]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[321]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[321]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[320]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[320]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[319]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[319]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[318]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[318]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[317]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[317]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[316]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[316]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[315]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[315]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[314]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[314]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[313]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[313]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[312]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[312]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[311]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[311]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[310]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[310]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[309]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[309]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[308]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[308]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[307]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[307]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[306]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[306]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[305]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[305]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[304]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[304]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[303]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[303]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[302]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[302]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[301]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[301]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[300]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[300]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[299]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[299]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[298]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[298]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[297]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[297]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[296]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[296]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[295]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[295]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[294]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[294]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[293]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[293]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[292]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[292]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[291]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[291]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[290]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[290]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[289]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[289]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[288]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[288]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[287]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[287]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[286]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[286]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[285]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[285]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[284]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[284]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[283]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[283]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[282]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[282]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[281]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[281]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[280]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[280]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[279]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[279]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[278]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[278]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[277]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[277]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[276]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[276]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[275]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[275]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[274]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[274]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[273]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[273]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[272]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[272]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[271]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[271]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[270]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[270]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[269]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[269]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[268]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[268]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[267]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[267]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[266]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[266]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[265]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[265]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[264]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[264]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[263]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[263]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[262]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[262]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[261]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[261]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[260]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[260]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[259]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[259]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[258]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[258]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[257]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[257]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[256]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[256]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[255]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[255]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[254]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[254]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[253]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[253]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[252]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[252]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[251]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[251]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[250]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[250]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[249]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[249]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[248]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[248]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[247]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[247]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[246]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[246]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[245]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[245]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[244]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[244]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[243]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[243]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[242]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[242]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[241]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[241]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[240]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[240]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[239]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[239]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[238]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[238]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[237]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[237]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[236]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[236]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[235]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[235]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[234]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[234]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[233]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[233]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[232]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[232]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[231]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[231]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[230]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[230]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[229]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[229]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[228]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[228]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[227]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[227]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[226]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[226]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[225]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[225]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[224]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[224]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[223]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[223]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[222]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[222]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[221]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[221]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[220]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[220]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[219]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[219]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[218]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[218]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[217]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[217]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[216]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[216]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[215]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[215]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[214]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[214]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[213]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[213]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[212]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[212]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[211]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[211]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[210]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[210]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[209]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[209]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[208]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[208]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[207]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[207]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[206]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[206]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[205]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[205]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[204]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[204]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[203]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[203]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[202]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[202]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[201]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[201]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[200]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[200]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[199]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[199]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[198]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[198]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[197]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[197]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[196]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[196]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[195]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[195]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[194]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[194]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[193]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[193]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[192]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[192]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[191]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[191]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[190]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[190]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[189]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[189]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[188]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[188]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[187]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[187]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[186]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[186]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[185]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[185]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[184]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[184]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[183]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[183]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[182]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[182]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[181]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[181]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[180]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[180]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[179]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[179]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[178]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[178]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[177]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[177]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[176]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[176]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[175]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[175]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[174]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[174]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[173]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[173]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[172]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[172]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[171]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[171]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[170]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[170]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[169]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[169]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[168]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[168]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[167]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[167]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[166]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[166]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[165]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[165]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[164]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[164]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[163]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[163]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[162]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[162]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[161]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[161]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[160]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[160]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[159]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[159]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[158]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[158]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[157]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[157]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[156]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[156]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[155]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[155]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[154]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[154]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[153]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[153]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[152]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[152]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[151]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[151]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[150]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[150]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[149]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[149]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[148]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[148]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[147]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[147]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[146]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[146]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[145]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[145]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[144]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[144]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[143]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[143]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[142]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[142]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[141]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[141]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[140]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[140]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[139]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[139]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[138]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[138]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[137]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[137]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[136]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[136]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[135]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[135]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[134]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[134]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[133]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[133]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[132]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[132]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[131]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[131]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[130]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[130]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[129]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[129]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[128]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[128]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[127]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[127]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[126]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[126]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[125]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[125]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[124]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[124]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[123]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[123]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[122]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[122]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[121]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[121]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[120]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[120]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[119]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[119]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[118]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[118]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[117]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[117]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[116]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[116]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[115]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[115]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[114]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[114]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[113]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[113]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[112]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[112]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[111]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[111]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[110]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[110]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[109]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[109]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[108]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[108]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[107]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[107]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[106]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[106]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[105]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[105]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[104]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[104]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[103]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[103]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[102]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[102]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[101]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[101]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[100]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[100]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[99]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[99]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[98]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[98]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[97]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[97]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[96]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[96]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[95]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[95]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[94]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[94]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[93]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[93]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[92]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[92]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[91]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[91]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[90]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[90]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[89]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[89]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[88]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[88]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[87]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[87]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[86]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[86]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[85]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[85]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[84]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[84]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[83]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[83]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[82]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[82]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[81]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[81]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[80]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[80]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[79]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[79]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[78]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[78]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[77]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[77]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[76]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[76]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[75]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[75]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[74]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[74]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[73]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[73]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[72]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[72]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[71]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[71]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[70]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[70]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[69]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[69]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[68]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[68]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[67]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[67]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[66]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[66]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[65]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[65]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[64]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[64]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[63]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[63]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[62]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[62]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[61]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[61]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[60]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[60]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[59]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[59]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[58]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[58]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[57]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[57]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[56]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[56]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[55]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[55]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[54]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[54]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[53]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[53]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[52]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[52]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[51]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[51]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[50]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[50]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[49]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[49]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[48]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[48]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[47]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[47]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[46]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[46]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[45]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[45]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[44]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[44]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[43]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[43]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[42]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[42]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[41]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[41]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[40]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[40]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[39]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[39]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[38]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[38]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[37]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[37]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[36]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[36]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[35]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[34]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[33]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[32]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[31]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[30]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[29]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[28]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[27]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[26]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[25]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[24]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[23]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[22]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[21]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[20]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[19]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[18]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[17]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[16]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[15]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[14]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[13]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[12]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[11]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[10]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[9]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[8]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[7]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[6]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[5]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[4]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[3]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[2]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[1]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[0]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_v_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_v_i[0]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_cmd_yumi_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_cmd_yumi_i[0]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_yumi_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_yumi_i[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[7]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[6]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[5]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[4]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_resp_ready_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_resp_ready_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_ready_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_ready_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[29]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[28]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[27]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[26]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[25]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[24]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[23]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[22]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[21]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[20]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[19]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[18]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[17]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[16]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[15]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[14]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[13]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[12]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[11]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[10]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[9]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[8]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[7]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[6]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[5]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[4]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_v_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_v_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[569]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[569]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[568]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[568]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[567]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[567]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[566]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[566]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[565]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[565]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[564]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[564]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[563]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[563]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[562]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[562]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[561]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[561]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[560]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[560]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[559]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[559]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[558]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[558]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[557]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[557]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[556]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[556]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[555]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[555]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[554]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[554]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[553]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[553]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[552]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[552]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[551]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[551]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[550]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[550]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[549]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[549]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[548]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[548]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[547]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[547]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[546]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[546]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[545]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[545]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[544]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[544]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[543]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[543]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[542]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[542]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[541]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[541]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[540]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[540]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[539]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[539]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[538]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[538]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[537]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[537]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[536]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[536]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[535]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[535]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[534]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[534]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[533]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[533]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[532]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[532]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[531]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[531]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[530]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[530]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[529]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[529]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[528]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[528]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[527]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[527]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[526]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[526]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[525]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[525]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[524]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[524]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[523]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[523]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[522]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[522]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[521]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[521]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[520]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[520]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[519]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[519]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[518]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[518]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[517]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[517]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[516]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[516]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[515]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[515]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[514]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[514]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[513]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[513]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[512]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[512]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[511]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[511]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[510]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[510]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[509]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[509]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[508]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[508]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[507]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[507]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[506]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[506]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[505]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[505]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[504]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[504]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[503]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[503]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[502]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[502]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[501]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[501]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[500]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[500]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[499]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[499]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[498]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[498]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[497]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[497]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[496]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[496]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[495]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[495]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[494]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[494]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[493]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[493]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[492]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[492]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[491]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[491]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[490]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[490]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[489]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[489]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[488]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[488]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[487]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[487]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[486]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[486]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[485]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[485]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[484]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[484]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[483]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[483]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[482]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[482]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[481]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[481]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[480]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[480]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[479]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[479]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[478]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[478]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[477]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[477]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[476]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[476]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[475]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[475]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[474]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[474]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[473]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[473]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[472]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[472]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[471]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[471]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[470]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[470]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[469]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[469]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[468]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[468]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[467]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[467]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[466]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[466]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[465]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[465]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[464]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[464]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[463]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[463]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[462]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[462]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[461]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[461]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[460]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[460]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[459]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[459]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[458]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[458]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[457]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[457]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[456]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[456]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[455]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[455]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[454]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[454]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[453]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[453]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[452]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[452]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[451]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[451]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[450]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[450]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[449]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[449]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[448]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[448]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[447]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[447]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[446]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[446]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[445]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[445]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[444]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[444]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[443]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[443]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[442]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[442]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[441]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[441]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[440]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[440]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[439]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[439]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[438]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[438]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[437]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[437]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[436]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[436]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[435]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[435]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[434]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[434]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[433]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[433]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[432]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[432]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[431]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[431]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[430]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[430]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[429]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[429]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[428]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[428]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[427]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[427]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[426]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[426]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[425]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[425]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[424]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[424]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[423]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[423]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[422]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[422]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[421]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[421]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[420]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[420]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[419]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[419]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[418]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[418]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[417]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[417]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[416]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[416]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[415]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[415]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[414]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[414]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[413]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[413]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[412]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[412]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[411]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[411]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[410]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[410]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[409]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[409]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[408]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[408]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[407]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[407]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[406]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[406]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[405]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[405]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[404]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[404]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[403]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[403]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[402]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[402]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[401]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[401]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[400]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[400]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[399]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[399]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[398]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[398]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[397]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[397]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[396]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[396]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[395]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[395]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[394]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[394]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[393]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[393]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[392]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[392]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[391]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[391]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[390]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[390]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[389]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[389]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[388]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[388]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[387]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[387]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[386]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[386]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[385]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[385]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[384]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[384]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[383]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[383]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[382]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[382]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[381]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[381]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[380]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[380]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[379]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[379]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[378]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[378]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[377]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[377]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[376]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[376]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[375]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[375]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[374]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[374]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[373]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[373]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[372]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[372]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[371]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[371]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[370]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[370]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[369]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[369]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[368]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[368]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[367]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[367]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[366]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[366]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[365]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[365]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[364]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[364]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[363]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[363]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[362]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[362]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[361]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[361]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[360]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[360]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[359]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[359]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[358]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[358]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[357]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[357]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[356]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[356]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[355]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[355]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[354]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[354]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[353]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[353]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[352]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[352]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[351]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[351]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[350]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[350]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[349]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[349]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[348]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[348]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[347]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[347]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[346]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[346]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[345]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[345]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[344]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[344]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[343]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[343]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[342]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[342]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[341]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[341]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[340]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[340]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[339]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[339]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[338]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[338]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[337]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[337]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[336]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[336]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[335]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[335]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[334]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[334]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[333]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[333]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[332]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[332]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[331]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[331]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[330]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[330]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[329]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[329]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[328]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[328]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[327]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[327]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[326]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[326]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[325]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[325]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[324]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[324]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[323]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[323]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[322]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[322]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[321]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[321]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[320]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[320]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[319]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[319]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[318]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[318]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[317]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[317]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[316]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[316]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[315]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[315]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[314]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[314]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[313]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[313]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[312]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[312]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[311]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[311]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[310]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[310]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[309]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[309]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[308]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[308]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[307]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[307]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[306]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[306]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[305]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[305]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[304]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[304]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[303]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[303]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[302]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[302]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[301]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[301]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[300]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[300]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[299]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[299]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[298]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[298]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[297]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[297]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[296]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[296]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[295]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[295]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[294]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[294]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[293]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[293]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[292]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[292]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[291]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[291]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[290]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[290]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[289]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[289]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[288]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[288]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[287]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[287]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[286]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[286]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[285]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[285]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[284]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[284]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[283]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[283]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[282]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[282]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[281]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[281]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[280]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[280]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[279]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[279]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[278]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[278]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[277]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[277]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[276]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[276]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[275]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[275]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[274]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[274]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[273]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[273]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[272]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[272]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[271]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[271]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[270]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[270]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[269]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[269]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[268]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[268]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[267]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[267]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[266]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[266]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[265]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[265]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[264]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[264]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[263]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[263]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[262]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[262]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[261]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[261]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[260]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[260]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[259]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[259]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[258]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[258]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[257]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[257]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[256]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[256]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[255]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[255]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[254]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[254]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[253]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[253]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[252]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[252]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[251]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[251]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[250]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[250]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[249]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[249]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[248]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[248]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[247]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[247]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[246]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[246]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[245]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[245]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[244]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[244]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[243]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[243]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[242]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[242]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[241]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[241]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[240]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[240]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[239]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[239]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[238]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[238]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[237]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[237]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[236]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[236]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[235]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[235]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[234]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[234]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[233]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[233]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[232]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[232]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[231]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[231]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[230]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[230]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[229]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[229]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[228]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[228]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[227]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[227]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[226]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[226]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[225]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[225]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[224]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[224]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[223]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[223]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[222]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[222]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[221]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[221]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[220]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[220]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[219]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[219]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[218]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[218]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[217]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[217]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[216]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[216]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[215]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[215]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[214]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[214]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[213]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[213]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[212]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[212]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[211]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[211]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[210]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[210]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[209]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[209]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[208]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[208]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[207]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[207]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[206]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[206]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[205]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[205]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[204]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[204]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[203]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[203]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[202]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[202]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[201]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[201]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[200]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[200]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[199]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[199]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[198]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[198]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[197]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[197]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[196]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[196]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[195]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[195]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[194]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[194]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[193]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[193]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[192]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[192]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[191]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[191]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[190]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[190]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[189]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[189]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[188]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[188]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[187]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[187]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[186]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[186]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[185]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[185]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[184]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[184]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[183]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[183]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[182]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[182]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[181]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[181]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[180]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[180]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[179]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[179]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[178]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[178]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[177]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[177]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[176]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[176]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[175]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[175]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[174]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[174]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[173]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[173]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[172]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[172]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[171]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[171]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[170]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[170]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[169]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[169]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[168]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[168]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[167]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[167]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[166]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[166]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[165]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[165]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[164]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[164]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[163]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[163]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[162]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[162]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[161]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[161]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[160]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[160]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[159]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[159]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[158]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[158]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[157]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[157]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[156]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[156]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[155]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[155]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[154]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[154]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[153]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[153]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[152]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[152]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[151]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[151]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[150]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[150]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[149]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[149]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[148]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[148]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[147]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[147]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[146]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[146]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[145]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[145]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[144]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[144]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[143]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[143]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[142]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[142]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[141]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[141]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[140]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[140]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[139]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[139]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[138]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[138]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[137]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[137]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[136]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[136]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[135]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[135]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[134]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[134]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[133]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[133]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[132]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[132]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[131]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[131]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[130]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[130]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[129]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[129]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[128]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[128]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[127]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[127]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[126]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[126]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[125]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[125]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[124]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[124]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[123]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[123]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[122]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[122]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[121]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[121]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[120]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[120]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[119]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[119]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[118]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[118]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[117]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[117]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[116]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[116]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[115]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[115]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[114]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[114]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[113]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[113]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[112]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[112]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[111]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[111]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[110]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[110]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[109]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[109]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[108]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[108]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[107]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[107]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[106]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[106]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[105]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[105]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[104]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[104]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[103]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[103]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[102]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[102]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[101]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[101]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[100]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[100]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[99]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[99]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[98]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[98]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[97]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[97]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[96]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[96]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[95]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[95]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[94]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[94]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[93]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[93]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[92]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[92]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[91]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[91]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[90]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[90]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[89]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[89]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[88]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[88]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[87]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[87]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[86]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[86]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[85]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[85]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[84]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[84]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[83]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[83]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[82]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[82]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[81]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[81]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[80]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[80]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[79]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[79]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[78]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[78]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[77]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[77]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[76]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[76]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[75]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[75]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[74]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[74]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[73]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[73]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[72]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[72]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[71]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[71]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[70]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[70]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[69]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[69]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[68]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[68]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[67]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[67]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[66]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[66]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[65]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[65]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[64]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[64]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[63]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[62]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[61]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[60]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[59]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[58]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[57]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[56]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[55]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[54]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[53]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[52]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[51]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[50]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[49]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[48]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[47]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[46]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[45]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[44]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[43]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[42]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[41]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[40]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[39]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[38]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[37]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[36]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[35]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[34]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[33]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[32]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[31]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[30]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[29]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[28]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[27]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[26]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[25]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[24]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[23]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[22]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[21]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[20]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[19]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[18]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[17]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[16]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[15]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[14]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[13]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[12]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[11]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[10]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[9]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[8]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[7]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[6]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[5]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[4]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_v_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_v_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_w_v_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_w_v_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[4]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_w_v_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_w_v_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[63]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[62]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[61]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[60]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[59]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[58]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[57]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[56]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[55]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[54]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[53]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[52]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[51]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[50]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[49]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[48]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[47]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[46]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[45]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[44]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[43]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[42]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[41]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[40]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[39]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[38]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[37]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[36]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[35]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[34]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[33]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[32]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[31]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[30]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[29]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[28]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[27]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[26]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[25]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[24]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[23]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[22]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[21]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[20]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[19]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[18]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[17]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[16]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[15]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[14]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[13]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[12]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[11]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[10]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[9]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[8]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[7]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[6]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[5]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[4]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[63]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[62]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[61]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[60]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[59]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[58]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[57]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[56]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[55]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[54]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[53]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[52]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[51]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[50]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[49]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[48]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[47]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[46]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[45]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[44]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[43]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[42]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[41]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[40]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[39]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[38]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[37]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[36]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[35]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[34]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[33]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[32]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[31]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[30]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[29]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[28]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[27]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[26]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[25]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[24]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[23]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[22]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[21]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[20]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[19]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[18]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[17]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[16]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[15]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[14]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[13]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[12]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[11]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[10]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[9]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[8]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[7]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[6]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[5]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[4]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[0]}] diff --git a/flow/designs/nangate45/bp_multi_top/io.tcl b/flow/designs/nangate45/bp_multi_top/io.tcl index b2bdd9fce6..46c1375a1d 100644 --- a/flow/designs/nangate45/bp_multi_top/io.tcl +++ b/flow/designs/nangate45/bp_multi_top/io.tcl @@ -1 +1 @@ -exclude_io_pin_region -region left:100-1100 -region right:100-1100 -region top:* \ No newline at end of file +exclude_io_pin_region -region left:100-1100 -region right:100-1100 -region top:* diff --git a/flow/designs/nangate45/bp_quad/bsg_chip.sdc b/flow/designs/nangate45/bp_quad/bsg_chip.sdc index 69ce39fe4b..ea9a593ed0 100644 --- a/flow/designs/nangate45/bp_quad/bsg_chip.sdc +++ b/flow/designs/nangate45/bp_quad/bsg_chip.sdc @@ -17,132 +17,132 @@ set mx_delay2 [expr ${l_clk_p2}*0.28] set mn_delay1 [expr ${l_clk_p1}*0.02] -set_units -time ps -resistance kOhm -capacitance fF -power mW -voltage V \ --current uA -create_clock [get_ports p_bsg_tag_clk_i] -name tag_clk -period $l_clk_p2 -waveform $wv3 -set_clock_uncertainty -hold $clk_uncertainty [get_clocks tag_clk] -create_clock [get_ports p_clk_A_i] -name bp_clk -period $clk_period -waveform $wv1 -set_clock_uncertainty $clk_uncertainty [get_clocks bp_clk] -create_clock [get_ports p_clk_B_i] -name io_master_clk -period $clk_period -waveform $wv1 -set_clock_uncertainty $clk_uncertainty [get_clocks io_master_clk] -create_clock [get_ports p_clk_C_i] -name router_clk -period $clk_period -waveform $wv1 -set_clock_uncertainty $clk_uncertainty [get_clocks router_clk] -create_clock [get_ports p_ci_clk_i] -name sdi_a_clk -period $l_clk_p1 -waveform $wv2 -set_clock_uncertainty $clk_uncertainty [get_clocks sdi_a_clk] -create_clock [get_ports p_ci2_tkn_i] -name sdo_a_tkn_clk -period $l_clk_p1 -waveform $wv2 -set_clock_uncertainty $clk_uncertainty [get_clocks sdo_a_tkn_clk] -create_clock [get_ports p_co_clk_i] -name sdi_b_clk -period $l_clk_p1 -waveform $wv2 -set_clock_uncertainty $clk_uncertainty [get_clocks sdi_b_clk] -create_clock [get_ports p_co2_tkn_i] -name sdo_b_tkn_clk -period $l_clk_p1 -waveform $wv2 -set_clock_uncertainty $clk_uncertainty [get_clocks sdo_b_tkn_clk] +set_units -time ps -resistance kOhm -capacitance fF -power mW -voltage V \ + -current uA +create_clock [get_ports p_bsg_tag_clk_i] -name tag_clk -period $l_clk_p2 -waveform $wv3 +set_clock_uncertainty -hold $clk_uncertainty [get_clocks tag_clk] +create_clock [get_ports p_clk_A_i] -name bp_clk -period $clk_period -waveform $wv1 +set_clock_uncertainty $clk_uncertainty [get_clocks bp_clk] +create_clock [get_ports p_clk_B_i] -name io_master_clk -period $clk_period -waveform $wv1 +set_clock_uncertainty $clk_uncertainty [get_clocks io_master_clk] +create_clock [get_ports p_clk_C_i] -name router_clk -period $clk_period -waveform $wv1 +set_clock_uncertainty $clk_uncertainty [get_clocks router_clk] +create_clock [get_ports p_ci_clk_i] -name sdi_a_clk -period $l_clk_p1 -waveform $wv2 +set_clock_uncertainty $clk_uncertainty [get_clocks sdi_a_clk] +create_clock [get_ports p_ci2_tkn_i] -name sdo_a_tkn_clk -period $l_clk_p1 -waveform $wv2 +set_clock_uncertainty $clk_uncertainty [get_clocks sdo_a_tkn_clk] +create_clock [get_ports p_co_clk_i] -name sdi_b_clk -period $l_clk_p1 -waveform $wv2 +set_clock_uncertainty $clk_uncertainty [get_clocks sdi_b_clk] +create_clock [get_ports p_co2_tkn_i] -name sdo_b_tkn_clk -period $l_clk_p1 -waveform $wv2 +set_clock_uncertainty $clk_uncertainty [get_clocks sdo_b_tkn_clk] # -set_multicycle_path 0 -hold -to [list [get_ports p_ci2_clk_o] [get_ports \ -p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o] \ -[get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports \ -p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]] -set_multicycle_path 1 -setup -to [list [get_ports p_ci2_clk_o] [get_ports \ -p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o] \ -[get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports \ -p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]] -set_multicycle_path 0 -hold -to [list [get_ports p_co2_clk_o] [get_ports \ -p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o] \ -[get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports \ -p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]] -set_multicycle_path 1 -setup -to [list [get_ports p_co2_clk_o] [get_ports \ -p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o] \ -[get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports \ -p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]] -set_false_path -from [get_clocks router_clk] -to [get_clocks bp_clk] -set_false_path -from [get_clocks tag_clk] -to [get_clocks bp_clk] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_clk_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_clk_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_clk_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_clk_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_clk_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_clk_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_clk_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_clk_i] -set_input_delay -clock tag_clk $mx_delay2 [get_ports p_bsg_tag_data_i] -set_input_delay -clock tag_clk $mx_delay2 [get_ports p_bsg_tag_en_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_v_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_v_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_v_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_v_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_0_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_0_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_0_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_0_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_1_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_1_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_1_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_1_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_2_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_2_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_2_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_2_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_3_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_3_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_3_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_3_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_4_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_4_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_4_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_4_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_5_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_5_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_5_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_5_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_6_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_6_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_6_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_6_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_7_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_7_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_7_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_7_i] -set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_8_i] -set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_8_i] -set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_8_i] -set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_8_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_v_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_v_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_v_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_v_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_0_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_0_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_0_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_0_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_1_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_1_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_1_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_1_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_2_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_2_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_2_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_2_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_3_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_3_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_3_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_3_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_4_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_4_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_4_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_4_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_5_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_5_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_5_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_5_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_6_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_6_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_6_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_6_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_7_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_7_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_7_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_7_i] -set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_8_i] -set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_8_i] -set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_8_i] -set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_8_i] -set_timing_derate -early -cell_delay 0.97 [get_cells \ -{bp_processor/cc/y_0__x_0__tile_node/tile/core/fe/mem/icache/tag_mem/macro_bmem/db1_wb_0__bank/macro_mem}] +set_multicycle_path 0 -hold -to [list [get_ports p_ci2_clk_o] [get_ports \ + p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o] \ + [get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports \ + p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]] +set_multicycle_path 1 -setup -to [list [get_ports p_ci2_clk_o] [get_ports \ + p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o] \ + [get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports \ + p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]] +set_multicycle_path 0 -hold -to [list [get_ports p_co2_clk_o] [get_ports \ + p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o] \ + [get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports \ + p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]] +set_multicycle_path 1 -setup -to [list [get_ports p_co2_clk_o] [get_ports \ + p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o] \ + [get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports \ + p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]] +set_false_path -from [get_clocks router_clk] -to [get_clocks bp_clk] +set_false_path -from [get_clocks tag_clk] -to [get_clocks bp_clk] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_clk_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_clk_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_clk_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_clk_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_clk_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_clk_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_clk_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_clk_i] +set_input_delay -clock tag_clk $mx_delay2 [get_ports p_bsg_tag_data_i] +set_input_delay -clock tag_clk $mx_delay2 [get_ports p_bsg_tag_en_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_v_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_v_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_v_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_v_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_0_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_0_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_0_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_0_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_1_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_1_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_1_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_1_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_2_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_2_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_2_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_2_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_3_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_3_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_3_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_3_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_4_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_4_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_4_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_4_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_5_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_5_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_5_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_5_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_6_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_6_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_6_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_6_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_7_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_7_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_7_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_7_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_8_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_8_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_8_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_8_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_v_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_v_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_v_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_v_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_0_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_0_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_0_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_0_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_1_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_1_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_1_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_1_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_2_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_2_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_2_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_2_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_3_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_3_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_3_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_3_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_4_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_4_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_4_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_4_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_5_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_5_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_5_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_5_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_6_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_6_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_6_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_6_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_7_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_7_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_7_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_7_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_8_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_8_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_8_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_8_i] +set_timing_derate -early -cell_delay 0.97 [get_cells \ + {bp_processor/cc/y_0__x_0__tile_node/tile/core/fe/mem/icache/tag_mem/macro_bmem/db1_wb_0__bank/macro_mem}] diff --git a/flow/designs/nangate45/bp_quad/io.tcl b/flow/designs/nangate45/bp_quad/io.tcl index c368ed9bf9..c9e50c4b0a 100644 --- a/flow/designs/nangate45/bp_quad/io.tcl +++ b/flow/designs/nangate45/bp_quad/io.tcl @@ -1 +1 @@ -exclude_io_pin_region -region left:* -region right:* -region top:* -region bottom:0-1000 -region bottom:2400-3600 \ No newline at end of file +exclude_io_pin_region -region left:* -region right:* -region top:* -region bottom:0-1000 -region bottom:2400-3600 diff --git a/flow/designs/nangate45/gcd/constraint.sdc b/flow/designs/nangate45/gcd/constraint.sdc index 57be8eb9c6..852fef6395 100644 --- a/flow/designs/nangate45/gcd/constraint.sdc +++ b/flow/designs/nangate45/gcd/constraint.sdc @@ -1,8 +1,8 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 0.46 +set clk_period 0.46 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/ibex/constraint.sdc b/flow/designs/nangate45/ibex/constraint.sdc index 625bba41ec..210d591716 100644 --- a/flow/designs/nangate45/ibex/constraint.sdc +++ b/flow/designs/nangate45/ibex/constraint.sdc @@ -1,6 +1,6 @@ current_design ibex_core -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 2.2 set clk_io_pct 0.2 @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/jpeg/constraint.sdc b/flow/designs/nangate45/jpeg/constraint.sdc index af18e2d682..4548cad10c 100644 --- a/flow/designs/nangate45/jpeg/constraint.sdc +++ b/flow/designs/nangate45/jpeg/constraint.sdc @@ -1,6 +1,6 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 1.2 set clk_io_pct 0.2 @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/mempool_group/mempool_group.sdc b/flow/designs/nangate45/mempool_group/mempool_group.sdc index 87e865fbac..3d6bf172ca 100755 --- a/flow/designs/nangate45/mempool_group/mempool_group.sdc +++ b/flow/designs/nangate45/mempool_group/mempool_group.sdc @@ -29,22 +29,21 @@ set_case_analysis 0 [get_ports scan_enable_i] set_max_fanout $maxFanout [current_design] - # False path some of the quasi-static signals. #set_false_path -from tile_id_i # TCDM Master -set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter { name =~ tcdm_master_.*req_.*_i}] +set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter { name =~ tcdm_master_.*req_.*_i}] set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter { name =~ tcdm_master_*req_*_o}] -set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_master_*resp_*_i}] +set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_master_*resp_*_i}] set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_master_*resp_*_o}] # TCDM Slave #set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*req_*_i}] set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*req_*_o}] -set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*resp_*_i}] +set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*resp_*_i}] set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*resp_*_o}] # Refill port @@ -52,7 +51,7 @@ set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name #set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ refill_*_o}] # Reset -set_input_delay [expr 0.30*$clock_cycle] -clock vclk_i rst_ni +set_input_delay [expr 0.30*$clock_cycle] -clock vclk_i rst_ni # Critical range # Depending on the synthesis tool used, this can be helpful. diff --git a/flow/designs/nangate45/swerv/constraint.sdc b/flow/designs/nangate45/swerv/constraint.sdc index 9fd406be5e..be7426a1a2 100644 --- a/flow/designs/nangate45/swerv/constraint.sdc +++ b/flow/designs/nangate45/swerv/constraint.sdc @@ -1,6 +1,6 @@ current_design swerv -set clk_name core_clock +set clk_name core_clock set clk_port_name clk set clk_period 2.0 set clk_io_pct 0.2 @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/swerv_wrapper/constraint.sdc b/flow/designs/nangate45/swerv_wrapper/constraint.sdc index 308fd50a14..4ccc054acb 100644 --- a/flow/designs/nangate45/swerv_wrapper/constraint.sdc +++ b/flow/designs/nangate45/swerv_wrapper/constraint.sdc @@ -1,6 +1,6 @@ current_design swerv_wrapper -set clk_name core_clock +set clk_name core_clock set clk_port_name clk set clk_period 2.0 set clk_io_pct 0.2 @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/aes/constraint.sdc b/flow/designs/sky130hd/aes/constraint.sdc index 7fa2a489d8..f32c9be836 100644 --- a/flow/designs/sky130hd/aes/constraint.sdc +++ b/flow/designs/sky130hd/aes/constraint.sdc @@ -1,8 +1,8 @@ current_design aes_cipher_top -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 4.5 +set clk_period 4.5 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/aes/fastroute.tcl b/flow/designs/sky130hd/aes/fastroute.tcl index 66eb939e6f..80e4274ee2 100644 --- a/flow/designs/sky130hd/aes/fastroute.tcl +++ b/flow/designs/sky130hd/aes/fastroute.tcl @@ -2,4 +2,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/designs/sky130hd/chameleon/constraint.sdc b/flow/designs/sky130hd/chameleon/constraint.sdc index 6dcc28d927..da65f16f66 100644 --- a/flow/designs/sky130hd/chameleon/constraint.sdc +++ b/flow/designs/sky130hd/chameleon/constraint.sdc @@ -1,6 +1,6 @@ -set clk_name core_clock -set clk_port_name HCLK -set clk_period 7.0 +set clk_name core_clock +set clk_port_name HCLK +set clk_period 7.0 set clk_io_pct 0.1 set clk_port [get_ports $clk_port_name] @@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/gcd/constraint.sdc b/flow/designs/sky130hd/gcd/constraint.sdc index 7177c71e7b..d3fcca89a9 100644 --- a/flow/designs/sky130hd/gcd/constraint.sdc +++ b/flow/designs/sky130hd/gcd/constraint.sdc @@ -1,6 +1,6 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk set clk_period 1.1 set clk_io_pct 0.2 @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/ibex/constraint.sdc b/flow/designs/sky130hd/ibex/constraint.sdc index a4faf836eb..979e0b0b28 100644 --- a/flow/designs/sky130hd/ibex/constraint.sdc +++ b/flow/designs/sky130hd/ibex/constraint.sdc @@ -1,6 +1,6 @@ current_design ibex_core -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 10.0 set clk_io_pct 0.2 @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/ibex/constraint_doe.sdc b/flow/designs/sky130hd/ibex/constraint_doe.sdc index e169d10114..31ddde31d7 100644 --- a/flow/designs/sky130hd/ibex/constraint_doe.sdc +++ b/flow/designs/sky130hd/ibex/constraint_doe.sdc @@ -1,5 +1,5 @@ set uncertainty 1.0 -set io_delay 7.0 +set io_delay 7.0 set clock_port clk_i @@ -11,5 +11,5 @@ create_clock -name core_clock -period 15.0 -waveform {0.0000 7.5} [get_ports {cl set_clock_uncertainty $uncertainty [all_clocks] # -set_input_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_inputs] -set_output_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_outputs] +set_input_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_inputs] +set_output_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_outputs] diff --git a/flow/designs/sky130hd/ibex/fastroute.tcl b/flow/designs/sky130hd/ibex/fastroute.tcl index 24af379c99..76f9321967 100644 --- a/flow/designs/sky130hd/ibex/fastroute.tcl +++ b/flow/designs/sky130hd/ibex/fastroute.tcl @@ -2,4 +2,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/designs/sky130hd/jpeg/constraint.sdc b/flow/designs/sky130hd/jpeg/constraint.sdc index 28aa0cc7ca..5ac34a1acf 100644 --- a/flow/designs/sky130hd/jpeg/constraint.sdc +++ b/flow/designs/sky130hd/jpeg/constraint.sdc @@ -1,6 +1,6 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 5.5 set clk_io_pct 0.2 @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/jpeg/fastroute.tcl b/flow/designs/sky130hd/jpeg/fastroute.tcl index 80a2ca181e..e795f5e820 100644 --- a/flow/designs/sky130hd/jpeg/fastroute.tcl +++ b/flow/designs/sky130hd/jpeg/fastroute.tcl @@ -2,4 +2,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/designs/sky130hd/microwatt/constraint.sdc b/flow/designs/sky130hd/microwatt/constraint.sdc index cc9dbbe523..30f2da4808 100644 --- a/flow/designs/sky130hd/microwatt/constraint.sdc +++ b/flow/designs/sky130hd/microwatt/constraint.sdc @@ -49,8 +49,8 @@ set jtag_clk_port [get_ports $jtag_clk_port_name] create_clock -name $jtag_clk_name -period $jtag_clk_period $jtag_clk_port set_clock_groups -name group1 -logically_exclusive \ - -group [get_clocks $jtag_clk_name]\ - -group [get_clocks $clk_name] + -group [get_clocks $jtag_clk_name] \ + -group [get_clocks $clk_name] set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] -clock $jtag_clk_name [get_ports jtag_tdi] set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] -clock $jtag_clk_name [get_ports jtag_tms] diff --git a/flow/designs/sky130hd/microwatt/fastroute.tcl b/flow/designs/sky130hd/microwatt/fastroute.tcl index b39791ca0e..e1ea87c701 100644 --- a/flow/designs/sky130hd/microwatt/fastroute.tcl +++ b/flow/designs/sky130hd/microwatt/fastroute.tcl @@ -2,4 +2,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/designs/sky130hd/riscv32i/constraint.sdc b/flow/designs/sky130hd/riscv32i/constraint.sdc index 70a1fcf751..5b0a6f1b4e 100644 --- a/flow/designs/sky130hd/riscv32i/constraint.sdc +++ b/flow/designs/sky130hd/riscv32i/constraint.sdc @@ -1,6 +1,6 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 6.0 +set clk_period 6.0 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -9,10 +9,10 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [list] foreach input [all_inputs] { - if {$clk_port != $input} { - lappend $non_clock_inputs $input - } + if { $clk_port != $input } { + lappend $non_clock_inputs $input + } } -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/aes/constraint.sdc b/flow/designs/sky130hs/aes/constraint.sdc index 09f157ee3d..f99ac98b46 100644 --- a/flow/designs/sky130hs/aes/constraint.sdc +++ b/flow/designs/sky130hs/aes/constraint.sdc @@ -1,6 +1,6 @@ current_design aes_cipher_top -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 3.1 set clk_io_pct 0.2 @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/gcd/constraint.sdc b/flow/designs/sky130hs/gcd/constraint.sdc index f347111b34..71ddb64d28 100644 --- a/flow/designs/sky130hs/gcd/constraint.sdc +++ b/flow/designs/sky130hs/gcd/constraint.sdc @@ -1,8 +1,8 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 2.2 +set clk_period 2.2 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/ibex/constraint.sdc b/flow/designs/sky130hs/ibex/constraint.sdc index 72bc0ce1a3..a844a0dba6 100644 --- a/flow/designs/sky130hs/ibex/constraint.sdc +++ b/flow/designs/sky130hs/ibex/constraint.sdc @@ -1,6 +1,6 @@ current_design ibex_core -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 9.0 set clk_io_pct 0.2 @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/jpeg/constraint.sdc b/flow/designs/sky130hs/jpeg/constraint.sdc index d9420273eb..d150e21e15 100644 --- a/flow/designs/sky130hs/jpeg/constraint.sdc +++ b/flow/designs/sky130hs/jpeg/constraint.sdc @@ -1,6 +1,6 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 6.0 set clk_io_pct 0.2 @@ -11,5 +11,5 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/riscv32i/constraint.sdc b/flow/designs/sky130hs/riscv32i/constraint.sdc index 4be7147ef9..a598e70954 100644 --- a/flow/designs/sky130hs/riscv32i/constraint.sdc +++ b/flow/designs/sky130hs/riscv32i/constraint.sdc @@ -1,4 +1,4 @@ -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 5.2 set clk_io_pct 0.2 @@ -9,10 +9,10 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [list] foreach input [all_inputs] { - if {$clk_port != $input} { - lappend $non_clock_inputs $input - } + if { $clk_port != $input } { + lappend $non_clock_inputs $input + } } -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/src/mock-array/util.tcl b/flow/designs/src/mock-array/util.tcl index 960a3dffdb..6f3e9624c8 100644 --- a/flow/designs/src/mock-array/util.tcl +++ b/flow/designs/src/mock-array/util.tcl @@ -1,56 +1,56 @@ # Helper function to split a string into a list of strings and numbers -proc split_strings_and_numbers {str} { - set result {} - foreach {all letters numbers} [regexp -all -inline {(\D*)(\d*)} $str] { - if {$letters ne ""} { - lappend result $letters - } - if {$numbers ne ""} { - lappend result [expr {$numbers + 0}] ;# Convert to integer - } +proc split_strings_and_numbers { str } { + set result {} + foreach {all letters numbers} [regexp -all -inline {(\D*)(\d*)} $str] { + if { $letters ne "" } { + lappend result $letters } - return $result + if { $numbers ne "" } { + lappend result [expr { $numbers + 0 }] ;# Convert to integer + } + } + return $result } # Custom comparison function -proc natural_compare {str1 str2} { - set list1 [split_strings_and_numbers $str1] - set list2 [split_strings_and_numbers $str2] - set len [expr {min([llength $list1], [llength $list2])}] - for {set i 0} {$i < $len} {incr i} { - set part1 [lindex $list1 $i] - set part2 [lindex $list2 $i] - if {$part1 ne $part2} { - if {[string is integer -strict $part1] && [string is integer -strict $part2]} { - return [expr {$part1 - $part2}] - } else { - return [string compare $part1 $part2] - } - } +proc natural_compare { str1 str2 } { + set list1 [split_strings_and_numbers $str1] + set list2 [split_strings_and_numbers $str2] + set len [expr { min([llength $list1], [llength $list2]) }] + for { set i 0 } { $i < $len } { incr i } { + set part1 [lindex $list1 $i] + set part2 [lindex $list2 $i] + if { $part1 ne $part2 } { + if { [string is integer -strict $part1] && [string is integer -strict $part2] } { + return [expr { $part1 - $part2 }] + } else { + return [string compare $part1 $part2] + } } - return [expr {[llength $list1] - [llength $list2]}] ;# If all parts are equal, compare by length + } + return [expr { [llength $list1] - [llength $list2] }] ;# If all parts are equal, compare by length } -proc natural_sort {list} { - return [lsort -command natural_compare $list] +proc natural_sort { list } { + return [lsort -command natural_compare $list] } -proc match_pins { regex {direction .*} {is_clock 0}} { - set pins {} - # The regex for get_ports is not the tcl regex - foreach pin [get_ports -regex .*] { - set input [get_property $pin name] - # We want the Tcl regex - if {![regexp $regex $input]} { - continue - } - if {![regexp $direction [get_property $pin direction]]} { - continue - } - if {[expr $is_clock != [sta::is_clock_src [sta::get_port_pin $pin]]]} { - continue - } - lappend pins [get_property $pin name] +proc match_pins { regex { direction .* } { is_clock 0 } } { + set pins {} + # The regex for get_ports is not the tcl regex + foreach pin [get_ports -regex .*] { + set input [get_property $pin name] + # We want the Tcl regex + if { ![regexp $regex $input] } { + continue + } + if { ![regexp $direction [get_property $pin direction]] } { + continue + } + if { [expr $is_clock != [sta::is_clock_src [sta::get_port_pin $pin]]] } { + continue } - return [natural_sort $pins] + lappend pins [get_property $pin name] + } + return [natural_sort $pins] } diff --git a/flow/platforms/asap7/constraints.sdc b/flow/platforms/asap7/constraints.sdc index e7ca24cb2b..b08b9fa596 100644 --- a/flow/platforms/asap7/constraints.sdc +++ b/flow/platforms/asap7/constraints.sdc @@ -69,7 +69,7 @@ set sdc_version 2.0 set clk_port [get_ports $clk_port_name] create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port -set non_clk_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clk_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] set all_register_outputs [get_pins -of_objects [all_registers] -filter {direction == output}] # Optimization targets: overconstrain by default and @@ -77,9 +77,9 @@ set all_register_outputs [get_pins -of_objects [all_registers] -filter {directio # # Minimum time for io-io, io-reg, reg-io paths in macro is on # the order of 80ps for a small macro on ASAP7. -set_max_delay [expr {[info exists in2reg_max] ? $in2reg_max : 80}] -from $non_clk_inputs -to [all_registers] -set_max_delay [expr {[info exists reg2out_max] ? $reg2out_max : 80}] -from $all_register_outputs -to [all_outputs] -set_max_delay [expr {[info exists in2out_max] ? $in2out_max : 80}] -from $non_clk_inputs -to [all_outputs] +set_max_delay [expr { [info exists in2reg_max] ? $in2reg_max : 80 }] -from $non_clk_inputs -to [all_registers] +set_max_delay [expr { [info exists reg2out_max] ? $reg2out_max : 80 }] -from $all_register_outputs -to [all_outputs] +set_max_delay [expr { [info exists in2out_max] ? $in2out_max : 80 }] -from $non_clk_inputs -to [all_outputs] # This allows us to view the different groups # in the histogram in the GUI and also includes these diff --git a/flow/platforms/asap7/openRoad/make_tracks.tcl b/flow/platforms/asap7/openRoad/make_tracks.tcl index f404ab2209..ffd85fc94b 100644 --- a/flow/platforms/asap7/openRoad/make_tracks.tcl +++ b/flow/platforms/asap7/openRoad/make_tracks.tcl @@ -1,18 +1,18 @@ make_tracks Pad -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080 -make_tracks M9 -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080 -make_tracks M8 -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080 -make_tracks M7 -x_offset 0.016 -x_pitch 0.064 -y_offset 0.016 -y_pitch 0.064 -make_tracks M6 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.016 -y_pitch 0.064 -make_tracks M5 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.012 -y_pitch 0.048 -make_tracks M4 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.012 -y_pitch 0.048 -make_tracks M3 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036 +make_tracks M9 -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080 +make_tracks M8 -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080 +make_tracks M7 -x_offset 0.016 -x_pitch 0.064 -y_offset 0.016 -y_pitch 0.064 +make_tracks M6 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.016 -y_pitch 0.064 +make_tracks M5 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.012 -y_pitch 0.048 +make_tracks M4 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.012 -y_pitch 0.048 +make_tracks M3 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.045 -y_pitch 0.270 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.081 -y_pitch 0.270 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.117 -y_pitch 0.270 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.153 -y_pitch 0.270 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.189 -y_pitch 0.270 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.225 -y_pitch 0.270 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.270 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.045 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.081 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.117 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.153 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.189 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.225 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.270 -y_pitch 0.270 -make_tracks M1 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036 +make_tracks M1 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036 diff --git a/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl b/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl index bd7977d717..02d76cdcec 100644 --- a/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl +++ b/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl @@ -18,9 +18,9 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} define_pdn_grid -name {top} -voltage_domains {CORE} add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins -add_pdn_ring -grid {top} -layers {M5 M6} -widths {0.504 0.544} -spacings {0.096} -core_offset {0.504} +add_pdn_ring -grid {top} -layers {M5 M6} -widths {0.504 0.544} -spacings {0.096} -core_offset {0.504} -add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.16} -offset {1.50} -extend_to_core_ring +add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.16} -offset {1.50} -extend_to_core_ring add_pdn_stripe -grid {top} -layer {M6} -width {0.288} -spacing {0.096} -pitch {4.32} -offset {1.504} -extend_to_core_ring add_pdn_connect -grid {top} -layers {M1 M2} @@ -41,7 +41,7 @@ foreach macro [find_macros] { set macro_names [dict keys $macro_names] define_pdn_grid -macro -cells $macro_names \ - -halo "$::env(MACRO_ROWS_HALO_X) $::env(MACRO_ROWS_HALO_Y) $::env(MACRO_ROWS_HALO_X) $::env(MACRO_ROWS_HALO_Y)" \ - -voltage_domains {CORE} -name ElementGrid + -halo "$::env(MACRO_ROWS_HALO_X) $::env(MACRO_ROWS_HALO_Y) $::env(MACRO_ROWS_HALO_X) $::env(MACRO_ROWS_HALO_Y)" \ + -voltage_domains {CORE} -name ElementGrid add_pdn_connect -grid {ElementGrid} -layers {M5 M6} diff --git a/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl b/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl index 26234aae64..b8d6c4d392 100644 --- a/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl +++ b/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl @@ -20,14 +20,13 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} #################################### define_pdn_grid -name {top} -voltage_domains {CORE} -add_pdn_ring -grid {top} -layers {M5 M4} -widths {0.12 0.12} -spacings {0.072} -core_offset {0.084} +add_pdn_ring -grid {top} -layers {M5 M4} -widths {0.12 0.12} -spacings {0.072} -core_offset {0.084} -add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins -add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins +add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins +add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins -add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.976} -offset {1.5} -extend_to_core_ring +add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.976} -offset {1.5} -extend_to_core_ring add_pdn_connect -grid {top} -layers {M1 M2} add_pdn_connect -grid {top} -layers {M2 M5} add_pdn_connect -grid {top} -layers {M4 M5} - diff --git a/flow/platforms/asap7/openRoad/tapcell.tcl b/flow/platforms/asap7/openRoad/tapcell.tcl index 9526ba83d0..809d6952aa 100644 --- a/flow/platforms/asap7/openRoad/tapcell.tcl +++ b/flow/platforms/asap7/openRoad/tapcell.tcl @@ -9,6 +9,6 @@ puts " TAP Cell Distance : 25" tapcell \ -distance 25 \ -tapcell_master "$::env(TAP_CELL_NAME)" \ - -endcap_master "$::env(TAP_CELL_NAME)" \ + -endcap_master "$::env(TAP_CELL_NAME)" \ -halo_width_x $::env(MACRO_ROWS_HALO_X) \ -halo_width_y $::env(MACRO_ROWS_HALO_Y) diff --git a/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl b/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl index 28c2da3eed..9e23b6d0bd 100644 --- a/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl +++ b/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl @@ -11,9 +11,9 @@ set ::env(LIB_SLOWEST) "" set lib_path "$libs_ref/lib" foreach lib {"AO" "INVBUF" "OA" "SEQ" "SIMPLE"} { - append ::env(LIB_FASTEST) "$lib_path/asap7sc7p5t_${lib}_RVT_FF_nldm_201020.lib " - append ::env(LIB_TYPICAL) "$lib_path/asap7sc7p5t_${lib}_RVT_TT_nldm_201020.lib " - append ::env(LIB_SLOWEST) "$lib_path/asap7sc7p5t_${lib}_RVT_SS_nldm_201020.lib " + append ::env(LIB_FASTEST) "$lib_path/asap7sc7p5t_${lib}_RVT_FF_nldm_201020.lib " + append ::env(LIB_TYPICAL) "$lib_path/asap7sc7p5t_${lib}_RVT_TT_nldm_201020.lib " + append ::env(LIB_SLOWEST) "$lib_path/asap7sc7p5t_${lib}_RVT_SS_nldm_201020.lib " } set ::env(LIB_SYNTH) $::env(LIB_TYPICAL) @@ -36,7 +36,7 @@ set ::env(FP_ENDCAP_CELL) "TAPCELL_ASAP7_75t_R" # defaults (can be overridden by designs): set ::env(SYNTH_DRIVING_CELL) "BUFx2_ASAP7_75t_R" set ::env(SYNTH_DRIVING_CELL_PIN) "Y" -set ::env(SYNTH_CAP_LOAD) "4.61057" ; # femtofarad INVx8_ASAP7_75t_R pin A cap +set ::env(SYNTH_CAP_LOAD) "4.61057" ;# femtofarad INVx8_ASAP7_75t_R pin A cap set ::env(SYNTH_MIN_BUF_PORT) "BUFx2_ASAP7_75t_R A Y" set ::env(SYNTH_TIEHI_PORT) "TIEHIx1_ASAP7_75t_R H" set ::env(SYNTH_TIELO_PORT) "TIELOx1_ASAP7_75t_R L" diff --git a/flow/platforms/asap7/openlane/config.tcl b/flow/platforms/asap7/openlane/config.tcl index d7a4ee0bd1..ac404b4e2f 100755 --- a/flow/platforms/asap7/openlane/config.tcl +++ b/flow/platforms/asap7/openlane/config.tcl @@ -15,7 +15,7 @@ set ::env(STD_CELL_GROUND_PINS) "VSS" set ::env(TECH_LEF) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/techlef/asap7_tech_1x_201209.lef" set ::env(CELLS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*.lef"] set ::env(GDS_FILES) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/gds/*.gds"] -set ::env(STD_CELL_LIBRARY_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/cdl/$::env(STD_CELL_LIBRARY).cdl" +set ::env(STD_CELL_LIBRARY_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/cdl/$::env(STD_CELL_LIBRARY).cdl" set ::env(GPIO_PADS_LEF) "" @@ -25,7 +25,7 @@ set ::env(GPIO_PADS_VERILOG) "" set ::env(TECH_LEF_OPT) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/techlef/$::env(STD_CELL_LIBRARY_OPT).tlef" set ::env(CELLS_LEF_OPT) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/lef/*.lef"] set ::env(GDS_FILES_OPT) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/gds/*.gds"] -set ::env(STD_CELL_LIBRARY_OPT_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/cdl/$::env(STD_CELL_LIBRARY_OPT).cdl" +set ::env(STD_CELL_LIBRARY_OPT_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/cdl/$::env(STD_CELL_LIBRARY_OPT).cdl" # Optimization library slowest corner diff --git a/flow/platforms/gf180/fastroute.tcl b/flow/platforms/gf180/fastroute.tcl index d91e3b4dcc..42e6b5996b 100644 --- a/flow/platforms/gf180/fastroute.tcl +++ b/flow/platforms/gf180/fastroute.tcl @@ -1,3 +1,2 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.25 set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/platforms/gf180/openROAD/tapcell.tcl b/flow/platforms/gf180/openROAD/tapcell.tcl index fecbde985a..24ebce5587 100644 --- a/flow/platforms/gf180/openROAD/tapcell.tcl +++ b/flow/platforms/gf180/openROAD/tapcell.tcl @@ -1,5 +1,5 @@ - tapcell \ - -endcap_cpp "12" \ - -distance 100 \ - -tapcell_master $::env(TIE_CELL) \ - -endcap_master $::env(ENDCAP_CELL) +tapcell \ + -endcap_cpp "12" \ + -distance 100 \ + -tapcell_master $::env(TIE_CELL) \ + -endcap_master $::env(ENDCAP_CELL) diff --git a/flow/platforms/gf180/setRC.tcl b/flow/platforms/gf180/setRC.tcl index 7c6828b1de..33ae86856a 100644 --- a/flow/platforms/gf180/setRC.tcl +++ b/flow/platforms/gf180/setRC.tcl @@ -17,14 +17,12 @@ set_layer_rc -layer Metal5 -resistance 7.92778E-05 -capacitance 1.55595E-04 regexp {(\d+)} $::env(METAL_OPTION) metal if { $metal == "6" } { - set_wire_rc -signal -layer Metal2 - set_wire_rc -clock -layer Metal5 - -} elseif { $metal == "5" } { + set_wire_rc -clock -layer Metal5 +} elseif { $metal == "5" } { # TC matches LEF. These are the temperature adjusted values. # The other stacks are likely similar but I haven't checked yet. - if {$::env(CORNER) == "WC"} { + if { $::env(CORNER) == "WC" } { set_layer_rc -via Via1 -resistance 16.845 set_layer_rc -via Via2 -resistance 16.845 set_layer_rc -via Via3 -resistance 16.845 @@ -32,11 +30,11 @@ if { $metal == "6" } { set tech [ord::get_db_tech] foreach via [$tech getVias] { - if {[$via getResistance] == 4.5} { + if { [$via getResistance] == 4.5 } { $via setResistance 16.845 } } - } elseif {$::env(CORNER) == "BC"} { + } elseif { $::env(CORNER) == "BC" } { set_layer_rc -via Via1 -resistance 4.23 set_layer_rc -via Via2 -resistance 4.23 set_layer_rc -via Via3 -resistance 4.23 @@ -44,27 +42,21 @@ if { $metal == "6" } { set tech [ord::get_db_tech] foreach via [$tech getVias] { - if {[$via getResistance] == 4.5} { + if { [$via getResistance] == 4.5 } { $via setResistance 4.23 } } } - - set_wire_rc -signal -layer Metal2 - set_wire_rc -clock -layer Metal4 - -} elseif { $metal == "4" } { set_wire_rc -signal -layer Metal2 - set_wire_rc -clock -layer Metal3 - -} elseif { $metal == "3" } { - + set_wire_rc -clock -layer Metal4 +} elseif { $metal == "4" } { set_wire_rc -signal -layer Metal2 - set_wire_rc -clock -layer Metal2 - -} elseif { $metal == "2" } { - + set_wire_rc -clock -layer Metal3 +} elseif { $metal == "3" } { + set_wire_rc -signal -layer Metal2 + set_wire_rc -clock -layer Metal2 +} elseif { $metal == "2" } { set_wire_rc -signal -layer Metal2 - set_wire_rc -clock -layer Metal2 + set_wire_rc -clock -layer Metal2 } diff --git a/flow/platforms/ihp-sg13g2/fastroute.tcl b/flow/platforms/ihp-sg13g2/fastroute.tcl index 079fa662e8..e386fefda4 100644 --- a/flow/platforms/ihp-sg13g2/fastroute.tcl +++ b/flow/platforms/ihp-sg13g2/fastroute.tcl @@ -1,4 +1,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.05 set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/platforms/ihp-sg13g2/make_tracks.tcl b/flow/platforms/ihp-sg13g2/make_tracks.tcl index 4b6c63fd52..b3380eb7ef 100644 --- a/flow/platforms/ihp-sg13g2/make_tracks.tcl +++ b/flow/platforms/ihp-sg13g2/make_tracks.tcl @@ -1,7 +1,7 @@ -make_tracks Metal1 -x_offset 0.0 -x_pitch 0.48 -y_offset 0.0 -y_pitch 0.48 -make_tracks Metal2 -x_offset 0.0 -x_pitch 0.42 -y_offset 0.0 -y_pitch 0.42 -make_tracks Metal3 -x_offset 0.0 -x_pitch 0.48 -y_offset 0.0 -y_pitch 0.48 -make_tracks Metal4 -x_offset 0.0 -x_pitch 0.42 -y_offset 0.0 -y_pitch 0.42 -make_tracks Metal5 -x_offset 0.0 -x_pitch 3.48 -y_offset 0.0 -y_pitch 0.48 +make_tracks Metal1 -x_offset 0.0 -x_pitch 0.48 -y_offset 0.0 -y_pitch 0.48 +make_tracks Metal2 -x_offset 0.0 -x_pitch 0.42 -y_offset 0.0 -y_pitch 0.42 +make_tracks Metal3 -x_offset 0.0 -x_pitch 0.48 -y_offset 0.0 -y_pitch 0.48 +make_tracks Metal4 -x_offset 0.0 -x_pitch 0.42 -y_offset 0.0 -y_pitch 0.42 +make_tracks Metal5 -x_offset 0.0 -x_pitch 3.48 -y_offset 0.0 -y_pitch 0.48 make_tracks TopMetal1 -x_offset 1.46 -x_pitch 2.28 -y_offset 1.46 -y_pitch 2.28 -make_tracks TopMetal2 -x_offset 2.0 -x_pitch 4.0 -y_offset 2.0 -y_pitch 4.0 +make_tracks TopMetal2 -x_offset 2.0 -x_pitch 4.0 -y_offset 2.0 -y_pitch 4.0 diff --git a/flow/platforms/ihp-sg13g2/pdn.tcl b/flow/platforms/ihp-sg13g2/pdn.tcl index 99d911feae..27c506046a 100644 --- a/flow/platforms/ihp-sg13g2/pdn.tcl +++ b/flow/platforms/ihp-sg13g2/pdn.tcl @@ -20,9 +20,9 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} #################################### define_pdn_grid -name {grid} -voltage_domains {CORE} add_pdn_ring -grid {grid} -layers {Metal5 TopMetal1} -widths {5.0} -spacings {2.0} -core_offsets {4.5} -connect_to_pads -add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins -extend_to_core_ring -add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {13.600} -extend_to_core_ring -add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {1.800} -pitch {75.6} -offset {13.570} -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {13.600} -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {1.800} -pitch {75.6} -offset {13.570} -extend_to_core_ring add_pdn_connect -grid {grid} -layers {Metal1 Metal5} add_pdn_connect -grid {grid} -layers {Metal5 TopMetal1} # I/O pads diff --git a/flow/platforms/ihp-sg13g2/setRC.tcl b/flow/platforms/ihp-sg13g2/setRC.tcl index 65ea6cc833..35bfff7693 100644 --- a/flow/platforms/ihp-sg13g2/setRC.tcl +++ b/flow/platforms/ihp-sg13g2/setRC.tcl @@ -8,9 +8,9 @@ set_layer_rc -layer Metal5 -resistance 6.84051E-04 -capacitance 8.57431E-05 set_wire_rc -signal -resistance 2.07259E-03 -capacitance 1.73072E-04 set_wire_rc -clock -resistance 2.48603E-03 -capacitance 1.44812E-04 -set_layer_rc -via Via1 -resistance 2.0E-3 -set_layer_rc -via Via2 -resistance 2.0E-3 -set_layer_rc -via Via3 -resistance 2.0E-3 -set_layer_rc -via Via4 -resistance 2.0E-3 +set_layer_rc -via Via1 -resistance 2.0E-3 +set_layer_rc -via Via2 -resistance 2.0E-3 +set_layer_rc -via Via3 -resistance 2.0E-3 +set_layer_rc -via Via4 -resistance 2.0E-3 set_layer_rc -via TopVia1 -resistance 0.4E-3 set_layer_rc -via TopVia2 -resistance 0.22E-3 diff --git a/flow/platforms/nangate45/fakeram.tcl b/flow/platforms/nangate45/fakeram.tcl index 4c8f9997e6..d4706cbe1a 100644 --- a/flow/platforms/nangate45/fakeram.tcl +++ b/flow/platforms/nangate45/fakeram.tcl @@ -1,4 +1,3 @@ - set design_rams { swerv {2048x39 256x34 64x21} bp_be_top {64x96 512x64 64x15} @@ -11,7 +10,7 @@ set design_rams { set results_dir "~/import/fakeram/results" set flow_dir "~/import/flow/flow/platforms/nangate45" -proc make_fakeram_links {} { +proc make_fakeram_links { } { global design_rams flow_dir foreach {design sizes} $design_rams { @@ -27,7 +26,7 @@ proc make_fakeram_links {} { } } -proc copy_fakeram_results {} { +proc copy_fakeram_results { } { global design_rams results_dir flow_dir foreach {design sizes} $design_rams { diff --git a/flow/platforms/nangate45/make_tracks.tcl b/flow/platforms/nangate45/make_tracks.tcl index 923d6a1fda..0411a74b72 100644 --- a/flow/platforms/nangate45/make_tracks.tcl +++ b/flow/platforms/nangate45/make_tracks.tcl @@ -1,10 +1,10 @@ make_tracks metal1 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14 -make_tracks metal2 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14 -make_tracks metal3 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14 -make_tracks metal4 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28 -make_tracks metal5 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28 -make_tracks metal6 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28 -make_tracks metal7 -x_offset 0.095 -x_pitch 0.8 -y_offset 0.07 -y_pitch 0.8 -make_tracks metal8 -x_offset 0.095 -x_pitch 0.8 -y_offset 0.07 -y_pitch 0.8 -make_tracks metal9 -x_offset 0.095 -x_pitch 1.6 -y_offset 0.07 -y_pitch 1.6 +make_tracks metal2 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14 +make_tracks metal3 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14 +make_tracks metal4 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28 +make_tracks metal5 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28 +make_tracks metal6 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28 +make_tracks metal7 -x_offset 0.095 -x_pitch 0.8 -y_offset 0.07 -y_pitch 0.8 +make_tracks metal8 -x_offset 0.095 -x_pitch 0.8 -y_offset 0.07 -y_pitch 0.8 +make_tracks metal9 -x_offset 0.095 -x_pitch 1.6 -y_offset 0.07 -y_pitch 1.6 make_tracks metal10 -x_offset 0.095 -x_pitch 1.6 -y_offset 0.07 -y_pitch 1.6 diff --git a/flow/platforms/nangate45/setRC.tcl b/flow/platforms/nangate45/setRC.tcl index d52baaa67d..f39d456de7 100644 --- a/flow/platforms/nangate45/setRC.tcl +++ b/flow/platforms/nangate45/setRC.tcl @@ -12,4 +12,4 @@ set_layer_rc -layer metal8 -resistance 1.8750e-04 -capacitance 9.69714E-02 #set_layer_rc -layer metal10 -resistance 3.7500e-05 -capacitance 2.8042e-02 set_wire_rc -signal -layer metal3 -set_wire_rc -clock -layer metal5 +set_wire_rc -clock -layer metal5 diff --git a/flow/platforms/nangate45/tapcell.tcl b/flow/platforms/nangate45/tapcell.tcl index 9057b795cd..edd4e1d15b 100644 --- a/flow/platforms/nangate45/tapcell.tcl +++ b/flow/platforms/nangate45/tapcell.tcl @@ -2,4 +2,3 @@ tapcell \ -distance 120 \ -tapcell_master "$::env(TAP_CELL_NAME)" \ -endcap_master "$::env(TAP_CELL_NAME)" - diff --git a/flow/platforms/sky130hd/fastroute.tcl b/flow/platforms/sky130hd/fastroute.tcl index 24af379c99..76f9321967 100644 --- a/flow/platforms/sky130hd/fastroute.tcl +++ b/flow/platforms/sky130hd/fastroute.tcl @@ -2,4 +2,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/scripts/add_routing_blk.tcl b/flow/scripts/add_routing_blk.tcl index 7fc079f446..f4aadedbe7 100644 --- a/flow/scripts/add_routing_blk.tcl +++ b/flow/scripts/add_routing_blk.tcl @@ -22,19 +22,19 @@ foreach inst $allInsts { set loc_llx [lindex [$inst getLocation] 0] set loc_lly [lindex [$inst getLocation] 1] - if {[string match "*gf12*" $name]||[string match "IN12LP*" $name]} { + if { [string match "*gf12*" $name] || [string match "IN12LP*" $name] } { set w [$master getWidth] set h [$master getHeight] - set llx_Mx [expr $loc_llx - (128*$numTrack)] - set lly_Mx [expr $loc_lly - (128*$numTrack)] - set urx_Mx [expr $loc_llx + $w + (128*$numTrack)] - set ury_Mx [expr $loc_lly + $h + (128*$numTrack)] + set llx_Mx [expr $loc_llx - (128*$numTrack)] + set lly_Mx [expr $loc_lly - (128*$numTrack)] + set urx_Mx [expr $loc_llx + $w + (128*$numTrack)] + set ury_Mx [expr $loc_lly + $h + (128*$numTrack)] - set llx_Cx $loc_llx - set lly_Cx [expr $loc_lly - (160*$numTrack)] - set urx_Cx [expr $loc_llx + $w] - set ury_Cx [expr $loc_lly + $h + (160*$numTrack)] + set llx_Cx $loc_llx + set lly_Cx [expr $loc_lly - (160*$numTrack)] + set urx_Cx [expr $loc_llx + $w] + set ury_Cx [expr $loc_lly + $h + (160*$numTrack)] set obs_M2 [odb::dbObstruction_create $block $layer_M2 $llx_Mx $lly_Mx $urx_Mx $ury_Mx] set obs_M3 [odb::dbObstruction_create $block $layer_M3 $llx_Mx $lly_Mx $urx_Mx $ury_Mx] @@ -44,6 +44,6 @@ foreach inst $allInsts { } } -if {$cnt != 0} { +if { $cnt != 0 } { puts "Created $cnt routing blockages over macros" } diff --git a/flow/scripts/cts.tcl b/flow/scripts/cts.tcl index 5350eaa3eb..5865a19485 100644 --- a/flow/scripts/cts.tcl +++ b/flow/scripts/cts.tcl @@ -7,7 +7,7 @@ load_design 3_place.odb 3_place.sdc # so cts does not try to buffer the inverted clocks. repair_clock_inverters -proc save_progress {stage} { +proc save_progress { stage } { puts "Run 'make gui_$stage.odb' to load progress snapshot" write_db $::env(RESULTS_DIR)/$stage.odb write_sdc -no_timestamp $::env(RESULTS_DIR)/$stage.sdc @@ -15,9 +15,9 @@ proc save_progress {stage} { # Run CTS set cts_args [list \ - -sink_clustering_enable \ - -balance_levels \ - -repair_clock_nets] + -sink_clustering_enable \ + -balance_levels \ + -repair_clock_nets] append_env_var cts_args CTS_BUF_DISTANCE -distance_between_buffers 1 append_env_var cts_args CTS_CLUSTER_SIZE -sink_clustering_size 1 @@ -26,7 +26,7 @@ append_env_var cts_args CTS_BUF_LIST -buf_list 1 append_env_var cts_args CTS_LIB_NAME -library 1 -if {[env_var_exists_and_non_empty CTS_ARGS]} { +if { [env_var_exists_and_non_empty CTS_ARGS] } { set cts_args $::env(CTS_ARGS) } @@ -42,29 +42,29 @@ if { $::env(DETAILED_METRICS) } { utl::pop_metrics_stage set_placement_padding -global \ - -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ - -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) + -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ + -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) detailed_placement estimate_parasitics -placement -if {[env_var_equals CTS_SNAPSHOTS 1]} { +if { [env_var_equals CTS_SNAPSHOTS 1] } { save_progress 4_1_pre_repair_hold_setup } -if {![env_var_equals SKIP_CTS_REPAIR_TIMING 1]} { - if {$::env(EQUIVALENCE_CHECK)} { - write_eqy_verilog 4_before_rsz.v +if { ![env_var_equals SKIP_CTS_REPAIR_TIMING 1] } { + if { $::env(EQUIVALENCE_CHECK) } { + write_eqy_verilog 4_before_rsz.v } repair_timing_helper - if {$::env(EQUIVALENCE_CHECK)} { - run_equivalence_test + if { $::env(EQUIVALENCE_CHECK) } { + run_equivalence_test } - set result [catch {detailed_placement} msg] - if {$result != 0} { + set result [catch { detailed_placement } msg] + if { $result != 0 } { save_progress 4_1_error puts "Detailed placement failed in CTS: $msg" exit $result diff --git a/flow/scripts/deleteNonClkNets.tcl b/flow/scripts/deleteNonClkNets.tcl index 0a6e80bb3c..bad10a4772 100644 --- a/flow/scripts/deleteNonClkNets.tcl +++ b/flow/scripts/deleteNonClkNets.tcl @@ -1,6 +1,6 @@ read_lef $::env(TECH_LEF) read_lef $::env(SC_LEF) -if {[info exist ::env(ADDITIONAL_LEFS)]} { +if { [info exist ::env(ADDITIONAL_LEFS)] } { foreach lef $::env(ADDITIONAL_LEFS) { read_lef $lef } @@ -13,24 +13,26 @@ source $::env(SCRIPTS_DIR)/read_liberty.tcl read_def $::env(RESULTS_DIR)/6_final.def set block [[[ord::get_db] getChip] getBlock] -set nets [$block getNets] +set nets [$block getNets] set insts [$block getInsts] # Delete all non-clock nets foreach net $nets { set sigType [$net getSigType] set wire [$net getWire] - if {"$sigType" eq "SIGNAL" && "$wire" ne "NULL"} { + if { "$sigType" eq "SIGNAL" && "$wire" ne "NULL" } { odb::dbWire_destroy $wire - } elseif {"$sigType" eq "POWER" || - "$sigType" eq "GROUND"} { + } elseif { + "$sigType" eq "POWER" || + "$sigType" eq "GROUND" + } { $net destroySWires } } # Delete fill cells to clean up screenshot foreach inst $insts { - if {"[[$inst getMaster] getType]" eq "CORE_SPACER"} { + if { "[[$inst getMaster] getType]" eq "CORE_SPACER" } { odb::dbInst_destroy $inst } } diff --git a/flow/scripts/deletePowerNets.tcl b/flow/scripts/deletePowerNets.tcl index 74120d50b3..e1e6def4e1 100644 --- a/flow/scripts/deletePowerNets.tcl +++ b/flow/scripts/deletePowerNets.tcl @@ -1,6 +1,6 @@ read_lef $::env(TECH_LEF) read_lef $::env(SC_LEF) -if {[info exist ::env(ADDITIONAL_LEFS)]} { +if { [info exist ::env(ADDITIONAL_LEFS)] } { foreach lef $::env(ADDITIONAL_LEFS) { read_lef $lef } @@ -12,7 +12,7 @@ source $::env(SCRIPTS_DIR)/read_liberty.tcl # Read def and sdc read_def $::env(RESULTS_DIR)/6_final.def -proc deleteNetByName {name} { +proc deleteNetByName { name } { set db [ord::get_db] set chip [$db getChip] set block [$chip getBlock] diff --git a/flow/scripts/deleteRoutingObstructions.tcl b/flow/scripts/deleteRoutingObstructions.tcl index 5f78de4e06..2743009338 100644 --- a/flow/scripts/deleteRoutingObstructions.tcl +++ b/flow/scripts/deleteRoutingObstructions.tcl @@ -1,4 +1,4 @@ -proc deleteRoutingObstructions {} { +proc deleteRoutingObstructions { } { set db [ord::get_db] set chip [$db getChip] set block [$chip getBlock] diff --git a/flow/scripts/density_fill.tcl b/flow/scripts/density_fill.tcl index 3709a447d3..0c4e10585e 100644 --- a/flow/scripts/density_fill.tcl +++ b/flow/scripts/density_fill.tcl @@ -2,7 +2,7 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables final load_design 5_route.odb 5_route.sdc -if {[env_var_equals USE_FILL 1]} { +if { [env_var_equals USE_FILL 1] } { set_propagated_clock [all_clocks] density_fill -rules $::env(FILL_CONFIG) # The .v file is just for debugging purposes, not a result of diff --git a/flow/scripts/detail_place.tcl b/flow/scripts/detail_place.tcl index a92a5ae800..c093b162fe 100644 --- a/flow/scripts/detail_place.tcl +++ b/flow/scripts/detail_place.tcl @@ -5,19 +5,19 @@ load_design 3_4_place_resized.odb 2_floorplan.sdc source $::env(PLATFORM_DIR)/setRC.tcl -proc do_dpl {} { +proc do_dpl { } { # Only for use with hybrid rows - if {[env_var_equals BALANCE_ROWS 1]} { + if { [env_var_equals BALANCE_ROWS 1] } { balance_row_usage } - + set_placement_padding -global \ - -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ - -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) + -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ + -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) detailed_placement - - if {[env_var_equals ENABLE_DPO 1]} { - if {[env_var_exists_and_non_empty DPO_MAX_DISPLACEMENT]} { + + if { [env_var_equals ENABLE_DPO 1] } { + if { [env_var_exists_and_non_empty DPO_MAX_DISPLACEMENT] } { improve_placement -max_displacement $::env(DPO_MAX_DISPLACEMENT) } else { improve_placement @@ -26,12 +26,12 @@ proc do_dpl {} { optimize_mirroring utl::info FLW 12 "Placement violations [check_placement -verbose]." - + estimate_parasitics -placement } -set result [catch {do_dpl} errMsg] -if {$result != 0} { +set result [catch { do_dpl } errMsg] +if { $result != 0 } { write_db $::env(RESULTS_DIR)/3_5_place_dp-failed.odb error $errMsg } diff --git a/flow/scripts/detail_route.tcl b/flow/scripts/detail_route.tcl index df1bdc1999..0ec28b2135 100644 --- a/flow/scripts/detail_route.tcl +++ b/flow/scripts/detail_route.tcl @@ -1,7 +1,7 @@ utl::set_metrics_stage "detailedroute__{}" source $::env(SCRIPTS_DIR)/load.tcl load_design 5_1_grt.odb 5_1_grt.sdc -if {![grt::have_routes]} { +if { ![grt::have_routes] } { error "Global routing failed, run `make gui_grt` and load $::global_route_congestion_report \ in DRC viewer to view congestion" } @@ -36,8 +36,10 @@ append additional_args " -verbose 1" # having to go spelunking in Tcl or modify configuration scripts, while # not having to wait too long or generating large useless reports. -set arguments [expr {[env_var_exists_and_non_empty DETAILED_ROUTE_ARGS] ? $::env(DETAILED_ROUTE_ARGS) : \ - [concat $additional_args {-drc_report_iter_step 5}]}] +set arguments [expr { + [env_var_exists_and_non_empty DETAILED_ROUTE_ARGS] ? $::env(DETAILED_ROUTE_ARGS) : + [concat $additional_args {-drc_report_iter_step 5}] +}] set all_args [concat [list \ -output_drc $::env(REPORTS_DIR)/5_route_drc.rpt \ @@ -46,12 +48,12 @@ set all_args [concat [list \ log_cmd detailed_route {*}$all_args -if {![env_var_equals SKIP_ANTENNA_REPAIR_POST_DRT 1]} { +if { ![env_var_equals SKIP_ANTENNA_REPAIR_POST_DRT 1] } { set repair_antennas_iters 1 - if {[repair_antennas]} { + if { [repair_antennas] } { detailed_route {*}$all_args } - while {[check_antennas] && $repair_antennas_iters < 5} { + while { [check_antennas] && $repair_antennas_iters < 5 } { repair_antennas detailed_route {*}$all_args incr repair_antennas_iters @@ -66,7 +68,7 @@ if { [env_var_exists_and_non_empty POST_DETAIL_ROUTE_TCL] } { check_antennas -report_file $env(REPORTS_DIR)/drt_antennas.log -if {![design_is_routed]} { +if { ![design_is_routed] } { error "Design has unrouted nets." } diff --git a/flow/scripts/fillcell.tcl b/flow/scripts/fillcell.tcl index 293f69ac83..ea23e5b24f 100644 --- a/flow/scripts/fillcell.tcl +++ b/flow/scripts/fillcell.tcl @@ -1,6 +1,6 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables route -if {[env_var_exists_and_non_empty FILL_CELLS]} { +if { [env_var_exists_and_non_empty FILL_CELLS] } { load_design 5_2_route.odb 5_1_grt.sdc set_propagated_clock [all_clocks] diff --git a/flow/scripts/final_report.tcl b/flow/scripts/final_report.tcl index d5c8d98e6a..a843d6dad6 100644 --- a/flow/scripts/final_report.tcl +++ b/flow/scripts/final_report.tcl @@ -18,11 +18,10 @@ write_def $::env(RESULTS_DIR)/6_final.def write_verilog $::env(RESULTS_DIR)/6_final.v # Run extraction and STA -if {[env_var_exists_and_non_empty RCX_RULES]} { - +if { [env_var_exists_and_non_empty RCX_RULES] } { # Set RC corner for RCX # Set in config.mk - if {[env_var_exists_and_non_empty RCX_RC_CORNER]} { + if { [env_var_exists_and_non_empty RCX_RC_CORNER] } { set rc_corner $::env(RCX_RC_CORNER) } @@ -38,25 +37,24 @@ if {[env_var_exists_and_non_empty RCX_RULES]} { read_spef $::env(RESULTS_DIR)/6_final.spef # Static IR drop analysis - if {[env_var_exists_and_non_empty PWR_NETS_VOLTAGES]} { + if { [env_var_exists_and_non_empty PWR_NETS_VOLTAGES] } { dict for {pwrNetName pwrNetVoltage} $::env(PWR_NETS_VOLTAGES) { - set_pdnsim_net_voltage -net ${pwrNetName} -voltage ${pwrNetVoltage} - analyze_power_grid -net ${pwrNetName} \ - -error_file $::env(REPORTS_DIR)/${pwrNetName}.rpt + set_pdnsim_net_voltage -net ${pwrNetName} -voltage ${pwrNetVoltage} + analyze_power_grid -net ${pwrNetName} \ + -error_file $::env(REPORTS_DIR)/${pwrNetName}.rpt } } else { puts "IR drop analysis for power nets is skipped because PWR_NETS_VOLTAGES is undefined" } - if {[env_var_exists_and_non_empty GND_NETS_VOLTAGES]} { + if { [env_var_exists_and_non_empty GND_NETS_VOLTAGES] } { dict for {gndNetName gndNetVoltage} $::env(GND_NETS_VOLTAGES) { - set_pdnsim_net_voltage -net ${gndNetName} -voltage ${gndNetVoltage} - analyze_power_grid -net ${gndNetName} \ - -error_file $::env(REPORTS_DIR)/${gndNetName}.rpt + set_pdnsim_net_voltage -net ${gndNetName} -voltage ${gndNetVoltage} + analyze_power_grid -net ${gndNetName} \ + -error_file $::env(REPORTS_DIR)/${gndNetName}.rpt } } else { puts "IR drop analysis for ground nets is skipped because GND_NETS_VOLTAGES is undefined" } - } else { puts "OpenRCX is not enabled for this platform." } @@ -66,6 +64,6 @@ report_cell_usage report_metrics 6 "finish" # Save a final image if openroad is compiled with the gui -if {[ord::openroad_gui_compiled]} { - gui::show "source $::env(SCRIPTS_DIR)/save_images.tcl" false +if { [ord::openroad_gui_compiled] } { + gui::show "source $::env(SCRIPTS_DIR)/save_images.tcl" false } diff --git a/flow/scripts/floorplan.tcl b/flow/scripts/floorplan.tcl index 3e0c655ef0..7e58e3fd9f 100644 --- a/flow/scripts/floorplan.tcl +++ b/flow/scripts/floorplan.tcl @@ -3,14 +3,14 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables floorplan load_design 1_synth.v 1_synth.sdc -proc report_unused_masters {} { +proc report_unused_masters { } { set db [ord::get_db] set libs [$db getLibs] set masters "" foreach lib $libs { foreach master [$lib getMasters] { # filter out non-block masters, or you can remove this conditional to detect any unused master - if {[$master getType] == "BLOCK"} { + if { [$master getType] == "BLOCK" } { lappend masters $master } } @@ -45,53 +45,53 @@ append_env_var additional_args ADDITIONAL_SITES -additional_sites 1 set use_floorplan_def [env_var_exists_and_non_empty FLOORPLAN_DEF] set use_footprint [env_var_exists_and_non_empty FOOTPRINT] -set use_die_and_core_area [expr {[env_var_exists_and_non_empty DIE_AREA] && [env_var_exists_and_non_empty CORE_AREA]}] +set use_die_and_core_area [expr { [env_var_exists_and_non_empty DIE_AREA] && [env_var_exists_and_non_empty CORE_AREA] }] set use_core_utilization [env_var_exists_and_non_empty CORE_UTILIZATION] -set methods_defined [expr {$use_floorplan_def + $use_footprint + $use_die_and_core_area + $use_core_utilization}] -if {$methods_defined > 1} { - puts "Error: Floorplan initialization methods are mutually exclusive, pick one." - exit 1 +set methods_defined [expr { $use_floorplan_def + $use_footprint + $use_die_and_core_area + $use_core_utilization }] +if { $methods_defined > 1 } { + puts "Error: Floorplan initialization methods are mutually exclusive, pick one." + exit 1 } -if {$use_floorplan_def} { - # Initialize floorplan by reading in floorplan DEF - log_cmd read_def -floorplan_initialize $env(FLOORPLAN_DEF) -} elseif {$use_footprint} { - # Initialize floorplan using ICeWall FOOTPRINT - ICeWall load_footprint $env(FOOTPRINT) - - initialize_floorplan \ - -die_area [ICeWall get_die_area] \ - -core_area [ICeWall get_core_area] \ - -site $::env(PLACE_SITE) - - ICeWall init_footprint $env(SIG_MAP_FILE) -} elseif {$use_die_and_core_area} { - initialize_floorplan -die_area $::env(DIE_AREA) \ - -core_area $::env(CORE_AREA) \ - -site $::env(PLACE_SITE) \ - {*}$additional_args -} elseif {$use_core_utilization} { - initialize_floorplan -utilization $::env(CORE_UTILIZATION) \ - -aspect_ratio $::env(CORE_ASPECT_RATIO) \ - -core_space $::env(CORE_MARGIN) \ - -site $::env(PLACE_SITE) \ - {*}$additional_args +if { $use_floorplan_def } { + # Initialize floorplan by reading in floorplan DEF + log_cmd read_def -floorplan_initialize $env(FLOORPLAN_DEF) +} elseif { $use_footprint } { + # Initialize floorplan using ICeWall FOOTPRINT + ICeWall load_footprint $env(FOOTPRINT) + + initialize_floorplan \ + -die_area [ICeWall get_die_area] \ + -core_area [ICeWall get_core_area] \ + -site $::env(PLACE_SITE) + + ICeWall init_footprint $env(SIG_MAP_FILE) +} elseif { $use_die_and_core_area } { + initialize_floorplan -die_area $::env(DIE_AREA) \ + -core_area $::env(CORE_AREA) \ + -site $::env(PLACE_SITE) \ + {*}$additional_args +} elseif { $use_core_utilization } { + initialize_floorplan -utilization $::env(CORE_UTILIZATION) \ + -aspect_ratio $::env(CORE_ASPECT_RATIO) \ + -core_space $::env(CORE_MARGIN) \ + -site $::env(PLACE_SITE) \ + {*}$additional_args } else { - puts "Error: No floorplan initialization method specified" - exit 1 + puts "Error: No floorplan initialization method specified" + exit 1 } if { [env_var_exists_and_non_empty MAKE_TRACKS] } { log_cmd source $::env(MAKE_TRACKS) -} elseif {[file exists $::env(PLATFORM_DIR)/make_tracks.tcl]} { +} elseif { [file exists $::env(PLATFORM_DIR)/make_tracks.tcl] } { log_cmd source $::env(PLATFORM_DIR)/make_tracks.tcl } else { make_tracks } -if {[env_var_exists_and_non_empty FOOTPRINT_TCL]} { +if { [env_var_exists_and_non_empty FOOTPRINT_TCL] } { log_cmd source $::env(FOOTPRINT_TCL) } @@ -115,7 +115,7 @@ if { [env_var_exists_and_non_empty POST_FLOORPLAN_TCL] } { } -if {[env_var_exists_and_non_empty IO_CONSTRAINTS]} { +if { [env_var_exists_and_non_empty IO_CONSTRAINTS] } { log_cmd source $::env(IO_CONSTRAINTS) } diff --git a/flow/scripts/generate_abstract.tcl b/flow/scripts/generate_abstract.tcl index 8ba73b46f5..6fc76b693a 100644 --- a/flow/scripts/generate_abstract.tcl +++ b/flow/scripts/generate_abstract.tcl @@ -1,7 +1,7 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables generate_abstract -set stem [expr {[env_var_exists_and_non_empty ABSTRACT_SOURCE] ? $::env(ABSTRACT_SOURCE) : "6_final"}] +set stem [expr { [env_var_exists_and_non_empty ABSTRACT_SOURCE] ? $::env(ABSTRACT_SOURCE) : "6_final" }] set result [find_sdc_file $stem.odb] set design_stage [lindex $result 0] @@ -9,19 +9,19 @@ set sdc_file [lindex $result 1] log_cmd load_design $stem.odb [file tail $sdc_file] -if {$design_stage >= 6 && [file exists $::env(RESULTS_DIR)/$stem.spef]} { +if { $design_stage >= 6 && [file exists $::env(RESULTS_DIR)/$stem.spef] } { log_cmd read_spef $::env(RESULTS_DIR)/$stem.spef -} elseif {$design_stage >= 3} { +} elseif { $design_stage >= 3 } { log_cmd estimate_parasitics -placement } -if {$design_stage >= 4} { +if { $design_stage >= 4 } { set_propagated_clock [all_clocks] } # write_timing_model includes the source latency in the model set_clock_latency -source 0 [all_clocks] puts "Generating abstract views" -if {[env_var_exists_and_non_empty CORNERS]} { +if { [env_var_exists_and_non_empty CORNERS] } { # corners foreach corner $::env(CORNERS) { log_cmd write_timing_model -corner $corner $::env(RESULTS_DIR)/$::env(DESIGN_NAME)_$corner.lib @@ -32,7 +32,7 @@ if {[env_var_exists_and_non_empty CORNERS]} { } log_cmd write_abstract_lef -bloat_occupied_layers $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lef -if {[env_var_exists_and_non_empty CDL_FILES]} { +if { [env_var_exists_and_non_empty CDL_FILES] } { cdl read_masters $::env(CDL_FILES) cdl out $::env(RESULTS_DIR)/$stem.cdl } diff --git a/flow/scripts/global_place.tcl b/flow/scripts/global_place.tcl index aa2b8ffc05..ac9d5c6722 100644 --- a/flow/scripts/global_place.tcl +++ b/flow/scripts/global_place.tcl @@ -26,14 +26,14 @@ set global_placement_args {} append_env_var global_placement_args GPL_ROUTABILITY_DRIVEN -routability_driven 0 # Parameters for timing driven mode in global placement -if {$::env(GPL_TIMING_DRIVEN)} { +if { $::env(GPL_TIMING_DRIVEN) } { lappend global_placement_args {-timing_driven} - if {[info exists ::env(GPL_KEEP_OVERFLOW)]} { + if { [info exists ::env(GPL_KEEP_OVERFLOW)] } { lappend global_placement_args -keep_resize_below_overflow $::env(GPL_KEEP_OVERFLOW) } } -proc do_placement {global_placement_args} { +proc do_placement { global_placement_args } { set all_args [concat [list -density [place_density_with_lb_addon] \ -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)] \ @@ -44,15 +44,15 @@ proc do_placement {global_placement_args} { log_cmd global_placement {*}$all_args } -set result [catch {do_placement $global_placement_args} errMsg] -if {$result != 0} { +set result [catch { do_placement $global_placement_args } errMsg] +if { $result != 0 } { write_db $::env(RESULTS_DIR)/3_3_place_gp-failed.odb error $errMsg } estimate_parasitics -placement -if {[env_var_equals CLUSTER_FLOPS 1]} { +if { [env_var_equals CLUSTER_FLOPS 1] } { cluster_flops estimate_parasitics -placement } diff --git a/flow/scripts/global_place_skip_io.tcl b/flow/scripts/global_place_skip_io.tcl index 599d7d90b4..ff05f363f6 100644 --- a/flow/scripts/global_place_skip_io.tcl +++ b/flow/scripts/global_place_skip_io.tcl @@ -6,9 +6,9 @@ if { [env_var_exists_and_non_empty FLOORPLAN_DEF] } { puts "FLOORPLAN_DEF is set. Skipping global placement without IOs" } else { log_cmd global_placement -skip_io -density [place_density_with_lb_addon] \ - -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ - -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ - {*}[env_var_or_empty GLOBAL_PLACEMENT_ARGS] + -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ + -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ + {*}[env_var_or_empty GLOBAL_PLACEMENT_ARGS] } write_db $::env(RESULTS_DIR)/3_1_place_gp_skip_io.odb diff --git a/flow/scripts/global_route.tcl b/flow/scripts/global_route.tcl index ecbf18109f..360a0067cc 100644 --- a/flow/scripts/global_route.tcl +++ b/flow/scripts/global_route.tcl @@ -5,12 +5,12 @@ load_design 4_cts.odb 4_cts.sdc # This proc is here to allow us to use 'return' to return early from this # file which is sourced -proc global_route_helper {} { - if {[env_var_exists_and_non_empty PRE_GLOBAL_ROUTE]} { +proc global_route_helper { } { + if { [env_var_exists_and_non_empty PRE_GLOBAL_ROUTE] } { source $::env(PRE_GLOBAL_ROUTE) } - proc do_global_route {} { + proc do_global_route { } { set all_args [concat [list \ -congestion_report_file $::global_route_congestion_report] \ $::env(GLOBAL_ROUTE_ARGS)] @@ -19,14 +19,16 @@ proc global_route_helper {} { } pin_access -bottom_routing_layer $::env(MIN_ROUTING_LAYER) \ - -top_routing_layer $::env(MAX_ROUTING_LAYER) + -top_routing_layer $::env(MAX_ROUTING_LAYER) - set result [catch {do_global_route} errMsg] + set result [catch { do_global_route } errMsg] - if {$result != 0} { - if {[expr !$::env(GENERATE_ARTIFACTS_ON_FAILURE) || \ + if { $result != 0 } { + if { + [expr !$::env(GENERATE_ARTIFACTS_ON_FAILURE) || \ ![file exists $::global_route_congestion_report] || \ - [file size $::global_route_congestion_report] == 0]} { + [file size $::global_route_congestion_report] == 0] + } { write_db $::env(RESULTS_DIR)/5_1_grt-failed.odb error $errMsg } @@ -36,13 +38,13 @@ proc global_route_helper {} { } set_placement_padding -global \ - -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ - -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) + -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ + -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) set_propagated_clock [all_clocks] estimate_parasitics -global_routing - if {[env_var_exists_and_non_empty DONT_USE_CELLS]} { + if { [env_var_exists_and_non_empty DONT_USE_CELLS] } { set_dont_use $::env(DONT_USE_CELLS) } @@ -88,7 +90,7 @@ proc global_route_helper {} { # Route the modified nets by rsz journal restore log_cmd global_route -end_incremental -congestion_report_file $::env(REPORTS_DIR)/congestion_post_recover_power.rpt - if {![env_var_equals SKIP_ANTENNA_REPAIR 1]} { + if { ![env_var_equals SKIP_ANTENNA_REPAIR 1] } { puts "Repair antennas..." repair_antennas -iterations 5 check_placement -verbose diff --git a/flow/scripts/io_placement.tcl b/flow/scripts/io_placement.tcl index 9de14f7154..e4f61e0983 100644 --- a/flow/scripts/io_placement.tcl +++ b/flow/scripts/io_placement.tcl @@ -1,9 +1,11 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables place -if {![env_var_exists_and_non_empty FLOORPLAN_DEF] && \ - ![env_var_exists_and_non_empty FOOTPRINT] && \ - ![env_var_exists_and_non_empty FOOTPRINT_TCL]} { +if { + ![env_var_exists_and_non_empty FLOORPLAN_DEF] && + ![env_var_exists_and_non_empty FOOTPRINT] && + ![env_var_exists_and_non_empty FOOTPRINT_TCL] +} { load_design 3_1_place_gp_skip_io.odb 2_floorplan.sdc log_cmd place_pins \ -hor_layers $::env(IO_PLACER_H) \ diff --git a/flow/scripts/klayout.tcl b/flow/scripts/klayout.tcl index 56cc08ad6b..811902d6c7 100644 --- a/flow/scripts/klayout.tcl +++ b/flow/scripts/klayout.tcl @@ -1,20 +1,20 @@ -if {[env_var_exists_and_non_empty FILL_CONFIG]} { - set fill_config $::env(FILL_CONFIG) +if { [env_var_exists_and_non_empty FILL_CONFIG] } { + set fill_config $::env(FILL_CONFIG) } else { - set fill_config "" + set fill_config "" } -if {[env_var_exists_and_non_empty SEAL_GDS]} { - set seal_gds $::env(SEAL_GDS) +if { [env_var_exists_and_non_empty SEAL_GDS] } { + set seal_gds $::env(SEAL_GDS) } else { - set seal_gds "" + set seal_gds "" } exec klayout -zz -rd design_name=$::env(DESIGN_NAME) \ - -rd in_def=$::env(RESULTS_DIR)/6_final.def \ - -rd in_files="$::env(GDSOAS_FILES) $::env(WRAPPED_GDSOAS)" \ - -rd config_file=$fill_config \ - -rd seal_file=$seal_gds \ - -rd out_file=$::env(RESULTS_DIR)/6_final.$::env(STREAM_SYSTEM_EXT) \ - -rd tech_file=$::env(OBJECTS_DIR)/klayout.lyt \ - -rm $::env(UTILS_DIR)/def2stream.py + -rd in_def=$::env(RESULTS_DIR)/6_final.def \ + -rd in_files="$::env(GDSOAS_FILES) $::env(WRAPPED_GDSOAS)" \ + -rd config_file=$fill_config \ + -rd seal_file=$seal_gds \ + -rd out_file=$::env(RESULTS_DIR)/6_final.$::env(STREAM_SYSTEM_EXT) \ + -rd tech_file=$::env(OBJECTS_DIR)/klayout.lyt \ + -rm $::env(UTILS_DIR)/def2stream.py diff --git a/flow/scripts/load.tcl b/flow/scripts/load.tcl index a8f6f1e642..2134f61dda 100644 --- a/flow/scripts/load.tcl +++ b/flow/scripts/load.tcl @@ -2,29 +2,29 @@ source $::env(SCRIPTS_DIR)/util.tcl source $::env(SCRIPTS_DIR)/report_metrics.tcl -proc load_design {design_file sdc_file} { +proc load_design { design_file sdc_file } { # Source platform-related Tcl command (initially for suppressing Liberty # warnings - if {[env_var_exists_and_non_empty PLATFORM_TCL]} { + if { [env_var_exists_and_non_empty PLATFORM_TCL] } { log_cmd source $::env(PLATFORM_TCL) } - + # Read liberty files source $::env(SCRIPTS_DIR)/read_liberty.tcl # Read design files set ext [file extension $design_file] - if {$ext == ".v"} { + if { $ext == ".v" } { read_lef $::env(TECH_LEF) read_lef $::env(SC_LEF) - if {[env_var_exists_and_non_empty ADDITIONAL_LEFS]} { + if { [env_var_exists_and_non_empty ADDITIONAL_LEFS] } { foreach lef $::env(ADDITIONAL_LEFS) { read_lef $lef } } read_verilog $::env(RESULTS_DIR)/$design_file link_design $::env(DESIGN_NAME) - } elseif {$ext == ".odb"} { + } elseif { $ext == ".odb" } { read_db $::env(RESULTS_DIR)/$design_file } else { error "Unrecognized input file $design_file" @@ -49,89 +49,89 @@ proc load_design {design_file sdc_file} { # Routines to run equivalence tests when they are enabled. proc get_verilog_cells_for_design { } { - set dir "$::env(PLATFORM_DIR)/work_around_yosys/" - set cell_files [glob $dir/*.v ] + set dir "$::env(PLATFORM_DIR)/work_around_yosys/" + set cell_files [glob $dir/*.v] } -proc write_eqy_verilog {filename} { +proc write_eqy_verilog { filename } { # Filter out cells with no verilog/not needed for equivalence such # as fillers and tap cells - if {[env_var_exists_and_non_empty REMOVE_CELLS_FOR_EQY]} { + if { [env_var_exists_and_non_empty REMOVE_CELLS_FOR_EQY] } { write_verilog -remove_cells $::env(REMOVE_CELLS_FOR_EQY) $::env(RESULTS_DIR)/$filename } else { - write_verilog $::env(RESULTS_DIR)/$filename + write_verilog $::env(RESULTS_DIR)/$filename } } -proc write_eqy_script_for_sky130hd {} { - error "this routine is not yet implemented" - #[gold] - #read_verilog -sv ./before.v ./formal_pdk.v +proc write_eqy_script_for_sky130hd { } { + error "this routine is not yet implemented" + #[gold] + #read_verilog -sv ./before.v ./formal_pdk.v - #[gate] - #read_verilog -sv ./after.v ./formal_pdk.v + #[gate] + #read_verilog -sv ./after.v ./formal_pdk.v - #[script] - #prep -top aes_cipher_top -flatten + #[script] + #prep -top aes_cipher_top -flatten - ## Using `rename -hide` is a better performing choice than nomatch if the signal names have no meaning at all - #rename -hide */_*_.* + ## Using `rename -hide` is a better performing choice than nomatch if the signal names have no meaning at all + #rename -hide */_*_.* - ## This removes unused signals before partitioning so no partitions are created for them - #opt_clean -purge - #memory_map + ## This removes unused signals before partitioning so no partitions are created for them + #opt_clean -purge + #memory_map - #[collect *] - ## This groups signals like `some_signal[0]`, `some_signal[1]`, ... that only differ in the index - #group *[] \1[] + #[collect *] + ## This groups signals like `some_signal[0]`, `some_signal[1]`, ... that only differ in the index + #group *[] \1[] - #[strategy basic] - #use sat - #depth 2 + #[strategy basic] + #use sat + #depth 2 } proc write_eqy_script { } { - set top_cell [current_design] - set cell_files [get_verilog_cells_for_design] - set outfile [open "$::env(OBJECTS_DIR)/4_eqy_test.eqy" w] - # Gold netlist - puts $outfile "\[gold]\nread_verilog -sv $::env(RESULTS_DIR)/4_before_rsz.v $cell_files\n" - puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n" - # Modified netlist - puts $outfile "\[gate]\nread_verilog -sv $::env(RESULTS_DIR)/4_after_rsz.v $cell_files\n" - puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n" - - # Recommendation from eqy team on how to speed up a design - puts $outfile "\[match *]\ngate-nomatch _*_.*" - - # See issue OpenROAD#6545 "Equivalence check failure due to non-unique resizer nets" - puts $outfile "gate-nomatch net*" - - # Necessary to avoid false positive after Yosys 0.49 - puts $outfile "gate-nomatch clone*\n\n" - - # Equivalence check recipe 1 - puts $outfile "\[strategy basic]\nuse sat\ndepth 10\n\n" - # Equivalence check recipe 2 - puts $outfile "\[strategy sby]\nuse sby\ndepth 10\nengine smtbmc bitwuzla\n\n" - - close $outfile + set top_cell [current_design] + set cell_files [get_verilog_cells_for_design] + set outfile [open "$::env(OBJECTS_DIR)/4_eqy_test.eqy" w] + # Gold netlist + puts $outfile "\[gold]\nread_verilog -sv $::env(RESULTS_DIR)/4_before_rsz.v $cell_files\n" + puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n" + # Modified netlist + puts $outfile "\[gate]\nread_verilog -sv $::env(RESULTS_DIR)/4_after_rsz.v $cell_files\n" + puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n" + + # Recommendation from eqy team on how to speed up a design + puts $outfile "\[match *]\ngate-nomatch _*_.*" + + # See issue OpenROAD#6545 "Equivalence check failure due to non-unique resizer nets" + puts $outfile "gate-nomatch net*" + + # Necessary to avoid false positive after Yosys 0.49 + puts $outfile "gate-nomatch clone*\n\n" + + # Equivalence check recipe 1 + puts $outfile "\[strategy basic]\nuse sat\ndepth 10\n\n" + # Equivalence check recipe 2 + puts $outfile "\[strategy sby]\nuse sby\ndepth 10\nengine smtbmc bitwuzla\n\n" + + close $outfile } -proc run_equivalence_test {} { - write_eqy_verilog 4_after_rsz.v - write_eqy_script - - eval exec eqy -d $::env(LOG_DIR)/4_eqy_output \ - --force \ - --jobs $::env(NUM_CORES) \ - $::env(OBJECTS_DIR)/4_eqy_test.eqy \ - > $::env(LOG_DIR)/4_equivalence_check.log - set count [exec grep -c "Successfully proved designs equivalent" $::env(LOG_DIR)/4_equivalence_check.log] - if { $count == 0 } { - error "Repair timing output failed equivalence test" - } else { - puts "Repair timing output passed equivalence test" - } +proc run_equivalence_test { } { + write_eqy_verilog 4_after_rsz.v + write_eqy_script + + eval exec eqy -d $::env(LOG_DIR)/4_eqy_output \ + --force \ + --jobs $::env(NUM_CORES) \ + $::env(OBJECTS_DIR)/4_eqy_test.eqy \ + > $::env(LOG_DIR)/4_equivalence_check.log + set count [exec grep -c "Successfully proved designs equivalent" $::env(LOG_DIR)/4_equivalence_check.log] + if { $count == 0 } { + error "Repair timing output failed equivalence test" + } else { + puts "Repair timing output passed equivalence test" + } } diff --git a/flow/scripts/macro_place_util.tcl b/flow/scripts/macro_place_util.tcl index de8c5ff99b..8aa9963ad0 100644 --- a/flow/scripts/macro_place_util.tcl +++ b/flow/scripts/macro_place_util.tcl @@ -1,16 +1,16 @@ -if {[find_macros] != ""} { - if {![env_var_exists_and_non_empty RTLMP_RPT_DIR]} { +if { [find_macros] != "" } { + if { ![env_var_exists_and_non_empty RTLMP_RPT_DIR] } { set ::env(RTLMP_RPT_DIR) "$::env(OBJECTS_DIR)/rtlmp" } - if {![env_var_exists_and_non_empty RTLMP_RPT_FILE]} { + if { ![env_var_exists_and_non_empty RTLMP_RPT_FILE] } { set ::env(RTLMP_RPT_FILE) "partition.txt" } - if {![env_var_exists_and_non_empty RTLMP_BLOCKAGE_FILE]} { + if { ![env_var_exists_and_non_empty RTLMP_BLOCKAGE_FILE] } { set ::env(RTLMP_BLOCKAGE_FILE) "$::env(OBJECTS_DIR)/rtlmp/partition.txt.blockage" } # If wrappers defined replace macros with their wrapped version - if {[env_var_exists_and_non_empty MACRO_WRAPPERS]} { + if { [env_var_exists_and_non_empty MACRO_WRAPPERS] } { source $::env(MACRO_WRAPPERS) set wrapped_macros [dict keys [dict get $wrapper around]] @@ -18,7 +18,7 @@ if {[find_macros] != ""} { set block [ord::get_db_block] foreach inst [$block getInsts] { - if {[lsearch -exact $wrapped_macros [[$inst getMaster] getName]] > -1} { + if { [lsearch -exact $wrapped_macros [[$inst getMaster] getName]] > -1 } { set new_master [dict get $wrapper around [[$inst getMaster] getName]] puts "Replacing [[$inst getMaster] getName] with $new_master for [$inst getName]" $inst swapMaster [$db findMaster $new_master] @@ -30,13 +30,13 @@ if {[find_macros] != ""} { set halo_max [expr max($halo_x, $halo_y)] set blockage_width $halo_max - if {[env_var_exists_and_non_empty MACRO_BLOCKAGE_HALO]} { + if { [env_var_exists_and_non_empty MACRO_BLOCKAGE_HALO] } { set blockage_width $::env(MACRO_BLOCKAGE_HALO) } - if {[env_var_exists_and_non_empty MACRO_PLACEMENT_TCL]} { + if { [env_var_exists_and_non_empty MACRO_PLACEMENT_TCL] } { log_cmd source $::env(MACRO_PLACEMENT_TCL) - } elseif {[env_var_exists_and_non_empty MACRO_PLACEMENT]} { + } elseif { [env_var_exists_and_non_empty MACRO_PLACEMENT] } { source $::env(SCRIPTS_DIR)/read_macro_placement.tcl log_cmd read_macro_placement $::env(MACRO_PLACEMENT) } else { @@ -74,7 +74,7 @@ if {[find_macros] != ""} { } source $::env(SCRIPTS_DIR)/placement_blockages.tcl - block_channels $blockage_width + block_channels $blockage_width } else { puts "No macros found: Skipping macro_placement" } diff --git a/flow/scripts/noop.tcl b/flow/scripts/noop.tcl index e69de29bb2..8b13789179 100644 --- a/flow/scripts/noop.tcl +++ b/flow/scripts/noop.tcl @@ -0,0 +1 @@ + diff --git a/flow/scripts/open.tcl b/flow/scripts/open.tcl index 79b8322dfe..36659892e0 100644 --- a/flow/scripts/open.tcl +++ b/flow/scripts/open.tcl @@ -3,51 +3,51 @@ source $::env(SCRIPTS_DIR)/util.tcl source $::env(SCRIPTS_DIR)/read_liberty.tcl # Read def -if {[env_var_exists_and_non_empty DEF_FILE]} { - # Read lef - log_cmd read_lef $::env(TECH_LEF) - log_cmd read_lef $::env(SC_LEF) - if {[env_var_exists_and_non_empty ADDITIONAL_LEFS]} { - foreach lef $::env(ADDITIONAL_LEFS) { - log_cmd read_lef $lef - } +if { [env_var_exists_and_non_empty DEF_FILE] } { + # Read lef + log_cmd read_lef $::env(TECH_LEF) + log_cmd read_lef $::env(SC_LEF) + if { [env_var_exists_and_non_empty ADDITIONAL_LEFS] } { + foreach lef $::env(ADDITIONAL_LEFS) { + log_cmd read_lef $lef } - set input_file $::env(DEF_FILE) - log_cmd read_def $input_file + } + set input_file $::env(DEF_FILE) + log_cmd read_def $input_file } else { - set input_file $::env(ODB_FILE) - log_cmd read_db $input_file + set input_file $::env(ODB_FILE) + log_cmd read_db $input_file } -proc read_timing {input_file} { +proc read_timing { input_file } { set result [find_sdc_file $input_file] set design_stage [lindex $result 0] set sdc_file [lindex $result 1] - if {$sdc_file == ""} { + if { $sdc_file == "" } { set sdc_file $::env(SDC_FILE) } log_cmd read_sdc $sdc_file if [file exists $::env(PLATFORM_DIR)/derate.tcl] { source $::env(PLATFORM_DIR)/derate.tcl } - + source $::env(PLATFORM_DIR)/setRC.tcl - if {$design_stage >= 4} { + if { $design_stage >= 4 } { # CTS has run, so propagate clocks set_propagated_clock [all_clocks] } - - if {$design_stage >= 6 && [file exist $::env(RESULTS_DIR)/6_final.spef]} { + + if { $design_stage >= 6 && [file exist $::env(RESULTS_DIR)/6_final.spef] } { log_cmd read_spef $::env(RESULTS_DIR)/6_final.spef - } elseif {$design_stage >= 5} { + } elseif { $design_stage >= 5 } { if { [log_cmd grt::have_routes] } { log_cmd estimate_parasitics -global_routing } else { puts "No global routing results available, skipping estimate_parasitics" puts "Load $::global_route_congestion_report for details" } - } elseif {$design_stage >= 3} { + } elseif { $design_stage >= 3 } { log_cmd estimate_parasitics -placement } @@ -55,17 +55,16 @@ proc read_timing {input_file} { set _tmp [log_cmd find_timing_paths] } -if {[ord::openroad_gui_compiled]} { +if { [ord::openroad_gui_compiled] } { set db_basename [file rootname [file tail $input_file]] gui::set_title "OpenROAD - $::env(PLATFORM)/$::env(DESIGN_NICKNAME)/$::env(FLOW_VARIANT) - ${db_basename}" } -if {[env_var_equals GUI_TIMING 1]} { +if { [env_var_equals GUI_TIMING 1] } { puts "GUI_TIMING=1 reading timing, takes a little while for large designs..." read_timing $input_file - if {[gui::enabled]} { + if { [gui::enabled] } { log_cmd gui::select_chart "Endpoint Slack" log_cmd gui::update_timing_report } } - diff --git a/flow/scripts/pdn.tcl b/flow/scripts/pdn.tcl index ea3941177b..628c4727c5 100644 --- a/flow/scripts/pdn.tcl +++ b/flow/scripts/pdn.tcl @@ -12,12 +12,12 @@ if { [env_var_exists_and_non_empty POST_PDN_TCL] } { # Check all supply nets set block [ord::get_db_block] foreach net [$block getNets] { - set type [$net getSigType] - if {$type == "POWER" || $type == "GROUND"} { -# Temporarily disable due to CI issues -# puts "Check supply: [$net getName]" -# check_power_grid -net [$net getName] - } + set type [$net getSigType] + if { $type == "POWER" || $type == "GROUND" } { + # Temporarily disable due to CI issues + # puts "Check supply: [$net getName]" + # check_power_grid -net [$net getName] + } } write_db $::env(RESULTS_DIR)/2_4_floorplan_pdn.odb diff --git a/flow/scripts/placement_blockages.tcl b/flow/scripts/placement_blockages.tcl index 876a01f903..82c306474b 100644 --- a/flow/scripts/placement_blockages.tcl +++ b/flow/scripts/placement_blockages.tcl @@ -1,4 +1,4 @@ -proc block_channels {channel_width_in_microns} { +proc block_channels { channel_width_in_microns } { set tech [ord::get_db_tech] set units [$tech getDbUnitsPerMicron] set block [ord::get_db_block] @@ -8,7 +8,7 @@ proc block_channels {channel_width_in_microns} { # set shapes {} foreach inst [$block getInsts] { - if {[[$inst getMaster] getType] == "BLOCK"} { + if { [[$inst getMaster] getType] == "BLOCK" } { set box [$inst getBBox] lappend shapes [odb::newSetFromRect [$box xMin] [$box yMin] [$box xMax] [$box yMax]] } @@ -37,9 +37,8 @@ proc block_channels {channel_width_in_microns} { # set rects [odb::getRectangles $shapeSet] foreach rect $rects { - set b [odb::dbBlockage_create $block \ - [$rect xMin] [$rect yMin] [$rect xMax] [$rect yMax]] - $b setSoft + set b [odb::dbBlockage_create $block \ + [$rect xMin] [$rect yMin] [$rect xMax] [$rect yMax]] + $b setSoft } } - diff --git a/flow/scripts/read_liberty.tcl b/flow/scripts/read_liberty.tcl index d556c7ff27..89ff2df733 100644 --- a/flow/scripts/read_liberty.tcl +++ b/flow/scripts/read_liberty.tcl @@ -1,5 +1,5 @@ #Read Liberty -if {[env_var_exists_and_non_empty CORNERS]} { +if { [env_var_exists_and_non_empty CORNERS] } { # corners define_corners {*}$::env(CORNERS) foreach corner $::env(CORNERS) { diff --git a/flow/scripts/read_macro_placement.tcl b/flow/scripts/read_macro_placement.tcl index 68c08231a4..bc643c7734 100644 --- a/flow/scripts/read_macro_placement.tcl +++ b/flow/scripts/read_macro_placement.tcl @@ -1,19 +1,19 @@ -proc read_macro_placement {macro_placement_file} { +proc read_macro_placement { macro_placement_file } { set block [ord::get_db_block] set units [$block getDefUnits] set ch [open $macro_placement_file] - while {![eof $ch]} { + while { ![eof $ch] } { set line [gets $ch] - if {[llength $line] == 0} {continue} + if { [llength $line] == 0 } { continue } set inst_name [lindex $line 0] set orientation [lindex $line 1] set x [expr round([lindex $line 2] * $units)] set y [expr round([lindex $line 3] * $units)] - if {[set inst [$block findInst $inst_name]] == "NULL"} { + if { [set inst [$block findInst $inst_name]] == "NULL" } { error "Cannot find instance $inst_name" } diff --git a/flow/scripts/report_metrics.tcl b/flow/scripts/report_metrics.tcl index 340de7e629..a1c31864f6 100644 --- a/flow/scripts/report_metrics.tcl +++ b/flow/scripts/report_metrics.tcl @@ -1,13 +1,13 @@ proc report_puts { out } { - upvar 1 when when - upvar 1 filename filename - set fileId [open $filename a] - puts $fileId $out - close $fileId + upvar 1 when when + upvar 1 filename filename + set fileId [open $filename a] + puts $fileId $out + close $fileId } -proc report_metrics { stage when {include_erc true} {include_clock_skew true} } { - if {[env_var_equals SKIP_REPORT_METRICS 1]} { +proc report_metrics { stage when { include_erc true } { include_clock_skew true } } { + if { [env_var_equals SKIP_REPORT_METRICS 1] } { return } puts "Report metrics stage $stage, $when..." @@ -33,7 +33,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_worst_slack_metric >> $filename report_worst_slack_metric -hold >> $filename - if {$include_clock_skew && $::env(REPORT_CLOCK_SKEW)} { + if { $include_clock_skew && $::env(REPORT_CLOCK_SKEW) } { report_puts "\n==========================================================================" report_puts "$when report_clock_skew" report_puts "--------------------------------------------------------------------------" @@ -57,7 +57,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "--------------------------------------------------------------------------" report_checks -unconstrained -fields {slew cap input net fanout} -format full_clock_expanded >> $filename - if {$include_erc} { + if { $include_erc } { report_puts "\n==========================================================================" report_puts "$when report_check_types -max_slew -max_cap -max_fanout -violators" report_puts "--------------------------------------------------------------------------" @@ -75,7 +75,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "--------------------------------------------------------------------------" report_puts "[sta::max_slew_check_limit]" - if {[sta::max_slew_check_limit] < 1e30} { + if { [sta::max_slew_check_limit] < 1e30 } { report_puts "\n==========================================================================" report_puts "$when max_slew_check_slack_limit" report_puts "--------------------------------------------------------------------------" @@ -92,7 +92,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "--------------------------------------------------------------------------" report_puts "[sta::max_fanout_check_limit]" - if {[sta::max_fanout_check_limit] < 1e30} { + if { [sta::max_fanout_check_limit] < 1e30 } { report_puts "\n==========================================================================" report_puts "$when max_fanout_check_slack_limit" report_puts "--------------------------------------------------------------------------" @@ -109,7 +109,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "--------------------------------------------------------------------------" report_puts "[sta::max_capacitance_check_limit]" - if {[sta::max_capacitance_check_limit] < 1e30} { + if { [sta::max_capacitance_check_limit] < 1e30 } { report_puts "\n==========================================================================" report_puts "$when max_capacitance_check_slack_limit" report_puts "--------------------------------------------------------------------------" @@ -142,7 +142,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "hold violation count [sta::endpoint_violation_count min]" set critical_path [lindex [find_timing_paths -sort_by_slack] 0] - if {$critical_path != ""} { + if { $critical_path != "" } { set path_delay [sta::format_time [[$critical_path path] arrival] 4] set path_slack [sta::format_time [[$critical_path path] slack] 4] } else { @@ -150,52 +150,52 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } set path_slack 0 } - if { [llength [all_registers]] != 0} { - report_puts "\n==========================================================================" - report_puts "$when report_checks -path_delay max reg to reg" - report_puts "--------------------------------------------------------------------------" - report_checks -path_delay max -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename - report_puts "\n==========================================================================" - report_puts "$when report_checks -path_delay min reg to reg" - report_puts "--------------------------------------------------------------------------" - report_checks -path_delay min -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename + if { [llength [all_registers]] != 0 } { + report_puts "\n==========================================================================" + report_puts "$when report_checks -path_delay max reg to reg" + report_puts "--------------------------------------------------------------------------" + report_checks -path_delay max -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename + report_puts "\n==========================================================================" + report_puts "$when report_checks -path_delay min reg to reg" + report_puts "--------------------------------------------------------------------------" + report_checks -path_delay min -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename - set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay max -from [all_inputs] -to [all_registers]] 0] - if {$inp_to_reg_critical_path != ""} { - set target_clock_latency_max [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4] - } else { - set target_clock_latency_max 0 - } + set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay max -from [all_inputs] -to [all_registers]] 0] + if { $inp_to_reg_critical_path != "" } { + set target_clock_latency_max [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4] + } else { + set target_clock_latency_max 0 + } - set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay min -from [all_inputs] -to [all_registers]] 0] - if {$inp_to_reg_critical_path != ""} { - set target_clock_latency_min [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4] - set source_clock_latency [sta::format_time [$inp_to_reg_critical_path source_clk_latency] 4] - } else { - set target_clock_latency_min 0 - set source_clock_latency 0 - } - - report_puts "\n==========================================================================" - report_puts "$when critical path target clock latency max path" - report_puts "--------------------------------------------------------------------------" - report_puts "$target_clock_latency_max" + set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay min -from [all_inputs] -to [all_registers]] 0] + if { $inp_to_reg_critical_path != "" } { + set target_clock_latency_min [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4] + set source_clock_latency [sta::format_time [$inp_to_reg_critical_path source_clk_latency] 4] + } else { + set target_clock_latency_min 0 + set source_clock_latency 0 + } - report_puts "\n==========================================================================" - report_puts "$when critical path target clock latency min path" - report_puts "--------------------------------------------------------------------------" - report_puts "$target_clock_latency_min" + report_puts "\n==========================================================================" + report_puts "$when critical path target clock latency max path" + report_puts "--------------------------------------------------------------------------" + report_puts "$target_clock_latency_max" - report_puts "\n==========================================================================" - report_puts "$when critical path source clock latency min path" - report_puts "--------------------------------------------------------------------------" - report_puts "$source_clock_latency" + report_puts "\n==========================================================================" + report_puts "$when critical path target clock latency min path" + report_puts "--------------------------------------------------------------------------" + report_puts "$target_clock_latency_min" + + report_puts "\n==========================================================================" + report_puts "$when critical path source clock latency min path" + report_puts "--------------------------------------------------------------------------" + report_puts "$source_clock_latency" } else { - puts "No registers in design" + puts "No registers in design" } # end if all_registers - + report_puts "\n==========================================================================" report_puts "$when critical path delay" report_puts "--------------------------------------------------------------------------" @@ -215,7 +215,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "\n==========================================================================" report_puts "$when report_power" report_puts "--------------------------------------------------------------------------" - if {[env_var_exists_and_non_empty CORNERS]} { + if { [env_var_exists_and_non_empty CORNERS] } { foreach corner $::env(CORNERS) { report_puts "Corner: $corner" report_power -corner $corner >> $filename diff --git a/flow/scripts/save_images.tcl b/flow/scripts/save_images.tcl index 67017a90f9..5dec935009 100644 --- a/flow/scripts/save_images.tcl +++ b/flow/scripts/save_images.tcl @@ -7,7 +7,7 @@ set height [ord::dbu_to_microns $height] set resolution [expr $height / 1000] set markerdb [[ord::get_db_block] findMarkerCategory DRC] -if {$markerdb != "NULL" && [$markerdb getMarkerCount] > 0} { +if { $markerdb != "NULL" && [$markerdb getMarkerCount] > 0 } { gui::select_marker_category $markerdb } @@ -41,7 +41,7 @@ gui::set_display_controls "Instances/Physical/*" visible false gui::set_display_controls "Misc/Instances/*" visible false save_image -resolution $resolution $::env(REPORTS_DIR)/final_placement.webp -if {[env_var_exists_and_non_empty PWR_NETS_VOLTAGES]} { +if { [env_var_exists_and_non_empty PWR_NETS_VOLTAGES] } { gui::set_display_controls "Heat Maps/IR Drop" visible true gui::set_heatmap IRDrop Layer $::env(IR_DROP_LAYER) gui::set_heatmap IRDrop ShowLegend 1 @@ -66,8 +66,8 @@ foreach clock [get_clocks *] { if { [llength [get_property $clock sources]] > 0 } { set clock_name [get_name $clock] save_clocktree_image -clock $clock_name \ - -width 1024 -height 1024 \ - $::env(REPORTS_DIR)/cts_$clock_name.webp + -width 1024 -height 1024 \ + $::env(REPORTS_DIR)/cts_$clock_name.webp gui::select_clockviewer_clock $clock_name save_image -resolution $resolution $::env(REPORTS_DIR)/cts_${clock_name}_layout.webp } @@ -81,17 +81,17 @@ gui::set_display_controls "Nets/Ground" visible false gui::set_display_controls "Shape Types/Routing/*" visible false gui::set_display_controls "Instances/*" visible true gui::set_display_controls "Instances/Physical/*" visible false -select -name "hold*" -type Inst -highlight 0 ;# green -select -name "input*" -type Inst -highlight 1 ;# yellow +select -name "hold*" -type Inst -highlight 0 ;# green +select -name "input*" -type Inst -highlight 1 ;# yellow select -name "output*" -type Inst -highlight 1 -select -name "repeater*" -type Inst -highlight 3 ;# magenta +select -name "repeater*" -type Inst -highlight 3 ;# magenta select -name "fanout*" -type Inst -highlight 3 select -name "load_slew*" -type Inst -highlight 3 select -name "max_cap*" -type Inst -highlight 3 select -name "max_length*" -type Inst -highlight 3 select -name "wire*" -type Inst -highlight 3 -select -name "rebuffer*" -type Inst -highlight 4 ;# red -select -name "split*" -type Inst -highlight 5 ;# dark green +select -name "rebuffer*" -type Inst -highlight 4 ;# red +select -name "split*" -type Inst -highlight 5 ;# dark green save_image -resolution $resolution $::env(REPORTS_DIR)/final_resizer.webp diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl index 7b67ead8ea..5f8909ebc4 100644 --- a/flow/scripts/synth.tcl +++ b/flow/scripts/synth.tcl @@ -9,7 +9,7 @@ if { [env_var_equals SYNTH_GUT 1] } { delete $::env(DESIGN_NAME)/c:* } -if {[env_var_exists_and_non_empty SYNTH_KEEP_MODULES]} { +if { [env_var_exists_and_non_empty SYNTH_KEEP_MODULES] } { foreach module $::env(SYNTH_KEEP_MODULES) { select -module $module setattr -mod -set keep_hierarchy 1 @@ -17,18 +17,18 @@ if {[env_var_exists_and_non_empty SYNTH_KEEP_MODULES]} { } } -if {[env_var_exists_and_non_empty SYNTH_HIER_SEPARATOR]} { +if { [env_var_exists_and_non_empty SYNTH_HIER_SEPARATOR] } { scratchpad -set flatten.separator $::env(SYNTH_HIER_SEPARATOR) } set synth_full_args [env_var_or_empty SYNTH_ARGS] -if {[env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS]} { +if { [env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS] } { set synth_full_args [concat $synth_full_args $::env(SYNTH_OPERATIONS_ARGS)] } else { set synth_full_args [concat $synth_full_args "-extra-map $::env(FLOW_HOME)/platforms/common/lcu_kogge_stone.v"] } -if {![env_var_equals SYNTH_HIERARCHICAL 1]} { +if { ![env_var_equals SYNTH_HIERARCHICAL 1] } { # Perform standard coarse-level synthesis script, flatten right away synth -flatten -run :fine {*}$synth_full_args } else { @@ -36,7 +36,7 @@ if {![env_var_equals SYNTH_HIERARCHICAL 1]} { # defer flattening until we have decided what hierarchy to keep synth -run :fine - if {[env_var_exists_and_non_empty SYNTH_MINIMUM_KEEP_SIZE]} { + if { [env_var_exists_and_non_empty SYNTH_MINIMUM_KEEP_SIZE] } { set ungroup_threshold $::env(SYNTH_MINIMUM_KEEP_SIZE) puts "Keep modules above estimated size of $ungroup_threshold gate equivalents" @@ -54,7 +54,7 @@ json -o $::env(RESULTS_DIR)/mem.json # Run report and check here so as to fail early if this synthesis run is doomed exec -- python3 $::env(SCRIPTS_DIR)/mem_dump.py --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json -if {![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS]} { +if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } { synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_full_args } else { source $::env(SCRIPTS_DIR)/synth_wrap_operators.tcl @@ -73,7 +73,7 @@ renames -wire opt -purge # Technology mapping of adders -if {[env_var_exists_and_non_empty ADDER_MAP_FILE]} { +if { [env_var_exists_and_non_empty ADDER_MAP_FILE] } { # extract the full adders extract_fa # map full adders @@ -84,7 +84,7 @@ if {[env_var_exists_and_non_empty ADDER_MAP_FILE]} { } # Technology mapping of latches -if {[env_var_exists_and_non_empty LATCH_MAP_FILE]} { +if { [env_var_exists_and_non_empty LATCH_MAP_FILE] } { techmap -map $::env(LATCH_MAP_FILE) } @@ -95,14 +95,14 @@ foreach cell $::env(DONT_USE_CELLS) { # Technology mapping of flip-flops # dfflibmap only supports one liberty file -if {[env_var_exists_and_non_empty DFF_LIB_FILE]} { +if { [env_var_exists_and_non_empty DFF_LIB_FILE] } { dfflibmap -liberty $::env(DFF_LIB_FILE) {*}$dfflibmap_args } else { dfflibmap -liberty $::env(DONT_USE_SC_LIB) {*}$dfflibmap_args } opt -if {![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS]} { +if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } { log_cmd abc {*}$abc_args } else { scratchpad -set abc9.script scripts/abc_speed_gia_only.script @@ -123,8 +123,8 @@ opt_clean -purge # Technology mapping of constant hi- and/or lo-drivers hilomap -singleton \ - -hicell {*}$::env(TIEHI_CELL_AND_PORT) \ - -locell {*}$::env(TIELO_CELL_AND_PORT) + -hicell {*}$::env(TIEHI_CELL_AND_PORT) \ + -locell {*}$::env(TIELO_CELL_AND_PORT) # Insert buffer cells for pass through wires insbuf -buf {*}$::env(MIN_BUF_CELL_AND_PORTS) @@ -135,7 +135,7 @@ tee -o $::env(REPORTS_DIR)/synth_check.txt check tee -o $::env(REPORTS_DIR)/synth_stat.txt stat {*}$stat_libs # check the design is composed exclusively of target cells, and check for other problems -if {![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS]} { +if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } { check -assert -mapped } else { # Wrapped operator synthesis leaves around $buf cells which `check -mapped` diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl index 170793fcf4..a148fd9460 100644 --- a/flow/scripts/synth_preamble.tcl +++ b/flow/scripts/synth_preamble.tcl @@ -6,8 +6,8 @@ erase_non_stage_variables synth # If using a cached, gate level netlist, then copy over to the results dir with # preserve timestamps flag set. If you don't, subsequent runs will cause the # floorplan step to be re-executed. -if {[env_var_exists_and_non_empty SYNTH_NETLIST_FILES]} { - if {[llength $::env(SYNTH_NETLIST_FILES)] == 1} { +if { [env_var_exists_and_non_empty SYNTH_NETLIST_FILES] } { + if { [llength $::env(SYNTH_NETLIST_FILES)] == 1 } { log_cmd exec cp -p $::env(SYNTH_NETLIST_FILES) $::env(RESULTS_DIR)/1_1_yosys.v } else { # The date should be the most recent date of the files, but to @@ -15,35 +15,35 @@ if {[env_var_exists_and_non_empty SYNTH_NETLIST_FILES]} { log_cmd exec cat {*}$::env(SYNTH_NETLIST_FILES) > $::env(RESULTS_DIR)/1_1_yosys.v } log_cmd exec cp -p $::env(SDC_FILE) $::env(RESULTS_DIR)/1_synth.sdc - if {[env_var_exists_and_non_empty CACHED_REPORTS]} { + if { [env_var_exists_and_non_empty CACHED_REPORTS] } { log_cmd exec cp -p {*}$::env(CACHED_REPORTS) $::env(REPORTS_DIR)/. } exit } -proc read_checkpoint {file} { +proc read_checkpoint { file } { # We are reading a Yosys checkpoint - if {[file extension $file] == ".json"} { + if { [file extension $file] == ".json" } { read_json $file } else { read_rtlil $file - } + } } -proc read_design_sources {} { +proc read_design_sources { } { # We are reading Verilog sources source $::env(SCRIPTS_DIR)/synth_stdcells.tcl # Setup verilog include directories set vIdirsArgs "" - if {[env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS]} { + if { [env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS] } { foreach dir $::env(VERILOG_INCLUDE_DIRS) { lappend vIdirsArgs "-I$dir" } set vIdirsArgs [join $vIdirsArgs] } - if {[env_var_equals SYNTH_HDL_FRONTEND slang]} { + if { [env_var_equals SYNTH_HDL_FRONTEND slang] } { # slang requires all files at once plugin -i slang yosys read_slang -D SYNTHESIS --keep-hierarchy --compat=vcs \ @@ -51,17 +51,17 @@ proc read_design_sources {} { {*}$vIdirsArgs {*}$::env(VERILOG_FILES) {*}[env_var_or_empty VERILOG_DEFINES] # Workaround for yosys-slang#119 setattr -unset init - } elseif {[env_var_equals SYNTH_HDL_FRONTEND verific]} { - if {[env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS]} { - verific -vlog-incdir {*}$::env(VERILOG_INCLUDE_DIRS) + } elseif { [env_var_equals SYNTH_HDL_FRONTEND verific] } { + if { [env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS] } { + verific -vlog-incdir {*}$::env(VERILOG_INCLUDE_DIRS) } - if {[env_var_exists_and_non_empty VERILOG_DEFINES]} { - verific -vlog-define {*}$::env(VERILOG_DEFINES) + if { [env_var_exists_and_non_empty VERILOG_DEFINES] } { + verific -vlog-define {*}$::env(VERILOG_DEFINES) } verific -sv2012 {*}$::env(VERILOG_FILES) - } elseif {![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND]} { + } elseif { ![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND] } { verilog_defaults -push - if {[env_var_exists_and_non_empty VERILOG_DEFINES]} { + if { [env_var_exists_and_non_empty VERILOG_DEFINES] } { verilog_defaults -add {*}$::env(VERILOG_DEFINES) } foreach file $::env(VERILOG_FILES) { @@ -69,15 +69,15 @@ proc read_design_sources {} { } verilog_defaults -pop } else { - error "Unrecognized HDL frontend: $::env(SYNTH_HDL_FRONTEND)" + error "Unrecognized HDL frontend: $::env(SYNTH_HDL_FRONTEND)" } # Read platform specific mapfile for OPENROAD_CLKGATE cells - if {[env_var_exists_and_non_empty CLKGATE_MAP_FILE]} { + if { [env_var_exists_and_non_empty CLKGATE_MAP_FILE] } { read_verilog -defer $::env(CLKGATE_MAP_FILE) } - if {[env_var_exists_and_non_empty SYNTH_BLACKBOXES]} { + if { [env_var_exists_and_non_empty SYNTH_BLACKBOXES] } { hierarchy -check -top $::env(DESIGN_NAME) foreach m $::env(SYNTH_BLACKBOXES) { blackbox $m @@ -85,7 +85,7 @@ proc read_design_sources {} { } } -if {$::env(ABC_AREA)} { +if { $::env(ABC_AREA) } { puts "Using ABC area script." set abc_script $::env(SCRIPTS_DIR)/abc_area.script } else { @@ -96,22 +96,22 @@ if {$::env(ABC_AREA)} { # Technology mapping for cells # ABC supports multiple liberty files, but the hook from Yosys to ABC doesn't set abc_args [list -script $abc_script \ - -liberty $::env(DONT_USE_SC_LIB) \ - -constr $::env(OBJECTS_DIR)/abc.constr] + -liberty $::env(DONT_USE_SC_LIB) \ + -constr $::env(OBJECTS_DIR)/abc.constr] # Exclude dont_use cells. This includes macros that are specified via # LIB_FILES and ADDITIONAL_LIBS that are included in LIB_FILES. -if {[env_var_exists_and_non_empty DONT_USE_CELLS]} { +if { [env_var_exists_and_non_empty DONT_USE_CELLS] } { foreach cell $::env(DONT_USE_CELLS) { lappend abc_args -dont_use $cell } } -if {[env_var_exists_and_non_empty SDC_FILE_CLOCK_PERIOD]} { +if { [env_var_exists_and_non_empty SDC_FILE_CLOCK_PERIOD] } { puts "Extracting clock period from SDC file: $::env(SDC_FILE_CLOCK_PERIOD)" set fp [open $::env(SDC_FILE_CLOCK_PERIOD) r] set clock_period [string trim [read $fp]] - if {$clock_period != ""} { + if { $clock_period != "" } { puts "Setting clock period to $clock_period" lappend abc_args -D $clock_period } @@ -129,24 +129,24 @@ puts $constr "set_driving_cell $::env(ABC_DRIVER_CELL)" puts $constr "set_load $::env(ABC_LOAD_IN_FF)" close $constr -proc convert_liberty_areas {} { +proc convert_liberty_areas { } { cellmatch -derive_luts =A:liberty_cell # find a reference nand2 gate set found_cell "" set found_cell_area "" # iterate over all cells with a nand2 signature foreach cell [tee -q -s result.string select -list-mod =*/a:lut=4'b0111 %m] { - if {! [rtlil::has_attr -mod $cell area]} { + if { ![rtlil::has_attr -mod $cell area] } { puts "Cell $cell missing area information" continue } set area [rtlil::get_attr -string -mod $cell area] - if {$found_cell == "" || [expr $area < $found_cell_area]} { + if { $found_cell == "" || [expr $area < $found_cell_area] } { set found_cell $cell set found_cell_area $area } } - if {$found_cell == ""} { + if { $found_cell == "" } { error "reference nand2 cell not found" } diff --git a/flow/scripts/synth_wrap_operators.tcl b/flow/scripts/synth_wrap_operators.tcl index c9b9ded629..a003aa2e32 100644 --- a/flow/scripts/synth_wrap_operators.tcl +++ b/flow/scripts/synth_wrap_operators.tcl @@ -15,7 +15,7 @@ set deferred_cells { } } -techmap {*}[join [lmap cell $deferred_cells {string cat "-dont_map [lindex $cell 0]"}] " "] +techmap {*}[join [lmap cell $deferred_cells { string cat "-dont_map [lindex $cell 0]" }] " "] foreach info $deferred_cells { set type [lindex $info 0] @@ -53,7 +53,7 @@ foreach info $deferred_cells { # iterate over all architectures, both the default and non-default foreach arch [lrange $info 2 end] { set suffix [lindex $arch 0] - set extra_map_args [lrange $arch 1 end] + set extra_map_args [lrange $arch 1 end] # map all operator copies which were selected to have this architecture techmap -map +/techmap.v {*}$extra_map_args A:source_cell=$type A:architecture=$suffix %i diff --git a/flow/scripts/tapcell.tcl b/flow/scripts/tapcell.tcl index 16c007c079..eb00d11e23 100644 --- a/flow/scripts/tapcell.tcl +++ b/flow/scripts/tapcell.tcl @@ -3,10 +3,10 @@ erase_non_stage_variables floorplan load_design 2_2_floorplan_macro.odb 2_1_floorplan.sdc -if {[env_var_exists_and_non_empty TAPCELL_TCL]} { - source $::env(TAPCELL_TCL) +if { [env_var_exists_and_non_empty TAPCELL_TCL] } { + source $::env(TAPCELL_TCL) } else { - cut_rows + cut_rows } write_db $::env(RESULTS_DIR)/2_3_floorplan_tapcell.odb diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl index 1c5b29e988..4e6bca9d99 100644 --- a/flow/scripts/util.tcl +++ b/flow/scripts/util.tcl @@ -1,11 +1,11 @@ -proc log_cmd {cmd args} { +proc log_cmd { cmd args } { # log the command, escape arguments with spaces - set log_cmd "$cmd[join [lmap arg $args {format " %s" [expr {[string match {* *} $arg] ? "\"$arg\"" : "$arg"}]}] ""]" + set log_cmd "$cmd[join [lmap arg $args { format " %s" [expr { [string mtch {* *} $arg] ? "\"$arg\"" : "$arg" }] }] ""]" puts $log_cmd set start [clock seconds] set result [uplevel 1 [list $cmd {*}$args]] - set time [expr {[clock seconds] - $start}] - if {$time >= 5} { + set time [expr { [clock seconds] - $start }] + if { $time >= 5 } { # Ideally we'd use a single line, but the command can output text # and we don't want to mix it with the log, so output the time it took afterwards. puts "Took $time seconds: $log_cmd" @@ -13,8 +13,8 @@ proc log_cmd {cmd args} { return $result } -proc fast_route {} { - if {[env_var_exists_and_non_empty FASTROUTE_TCL]} { +proc fast_route { } { + if { [env_var_exists_and_non_empty FASTROUTE_TCL] } { log_cmd source $::env(FASTROUTE_TCL) } else { log_cmd set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) $::env(ROUTING_LAYER_ADJUSTMENT) @@ -25,7 +25,7 @@ proc fast_route {} { proc repair_timing_helper { args } { set additional_args "$args -verbose" append_env_var additional_args SETUP_SLACK_MARGIN -setup_margin 1 - if {$::env(HOLD_SLACK_MARGIN) < 0} { + if { $::env(HOLD_SLACK_MARGIN) < 0 } { append_env_var additional_args HOLD_SLACK_MARGIN -hold_margin 1 } append_env_var additional_args SETUP_MOVE_SEQUENCE -sequence 1 @@ -38,7 +38,7 @@ proc repair_timing_helper { args } { log_cmd repair_timing {*}$additional_args } -proc repair_design_helper {} { +proc repair_design_helper { } { puts "Perform buffer insertion and gate resizing..." set additional_args "-verbose" @@ -48,7 +48,7 @@ proc repair_design_helper {} { log_cmd repair_design {*}$additional_args } -proc recover_power_helper {} { +proc recover_power_helper { } { if { $::env(RECOVER_POWER) == 0 } { return } @@ -66,20 +66,20 @@ proc recover_power_helper {} { report_power } -proc extract_stage {input_file} { - if {![regexp {/([0-9])_(([0-9])_)?} $input_file match num1 _ num2]} { +proc extract_stage { input_file } { + if { ![regexp {/([0-9])_(([0-9])_)?} $input_file match num1 _ num2] } { puts "Error: Could not determine design stage from $input_file" exit 1 } lappend number_groups $num1 - if {$num2!=""} { - lappend number_groups $num2 + if { $num2 != "" } { + lappend number_groups $num2 } else { lappend number_groups "0" } } -proc find_sdc_file {input_file} { +proc find_sdc_file { input_file } { # canonicalize input file, sometimes it is called with an input # file relative to $::env(RESULTS_DIR), other times with # an absolute path @@ -95,9 +95,9 @@ proc find_sdc_file {input_file} { set exact_sdc [string map {.odb .sdc} $input_file] set sdc_files [glob -nocomplain -directory $::env(RESULTS_DIR) -types f "\[1-9+\]_\[1-9_A-Za-z\]*\.sdc"] set sdc_files [lsort -decreasing -dictionary $sdc_files] - set sdc_files [lmap file $sdc_files {file normalize $file}] + set sdc_files [lmap file $sdc_files { file normalize $file }] foreach name $sdc_files { - if {[lindex [lsort -decreasing -dictionary [list $name $exact_sdc] ] 0] == $exact_sdc} { + if { [lindex [lsort -decreasing -dictionary [list $name $exact_sdc]] 0] == $exact_sdc } { set sdc_file $name break } @@ -105,34 +105,36 @@ proc find_sdc_file {input_file} { return [list $design_stage $sdc_file] } -proc env_var_equals {env_var value} { - return [expr {[info exists ::env($env_var)] && $::env($env_var) == $value}] +proc env_var_equals { env_var value } { + return [expr { [info exists ::env($env_var)] && $::env($env_var) == $value }] } -proc env_var_exists_and_non_empty {env_var} { - return [expr {[info exists ::env($env_var)] && ![string equal $::env($env_var) ""]}] +proc env_var_exists_and_non_empty { env_var } { + return [expr { [info exists ::env($env_var)] && ![string equal $::env($env_var) ""] }] } -proc append_env_var {list_name var_name prefix has_arg} { +proc append_env_var { list_name var_name prefix has_arg } { upvar $list_name list - if {(!$has_arg && [env_var_equals $var_name 1]) || - ($has_arg && [env_var_exists_and_non_empty $var_name])} { + if { + (!$has_arg && [env_var_equals $var_name 1]) || + ($has_arg && [env_var_exists_and_non_empty $var_name]) + } { lappend list $prefix - if {$has_arg} { + if { $has_arg } { lappend list $::env($var_name) } } } # Non-empty defaults should go into variables.yaml, generally -proc env_var_or_empty {env_var} { - if {[env_var_exists_and_non_empty $env_var]} { +proc env_var_or_empty { env_var } { + if { [env_var_exists_and_non_empty $env_var] } { return $::env($env_var) } return "" } -proc find_macros {} { +proc find_macros { } { set macros "" set db [ord::get_db] @@ -148,7 +150,7 @@ proc find_macros {} { return $macros } -proc erase_non_stage_variables {stage_name} { +proc erase_non_stage_variables { stage_name } { # "$::env(SCRIPTS_DIR)/stage_variables.py stage_name" returns list of # variables to erase. # @@ -157,7 +159,7 @@ proc erase_non_stage_variables {stage_name} { # https://github.com/The-OpenROAD-Project/OpenROAD/issues/5875 set variables [exec $::env(SCRIPTS_DIR)/non_stage_variables.py $stage_name] foreach var $variables { - if {[info exists ::env($var)]} { + if { [info exists ::env($var)] } { unset ::env($var) } } @@ -165,14 +167,14 @@ proc erase_non_stage_variables {stage_name} { set global_route_congestion_report $::env(REPORTS_DIR)/congestion.rpt -proc place_density_with_lb_addon {} { - if {[env_var_exists_and_non_empty PLACE_DENSITY_LB_ADDON]} { +proc place_density_with_lb_addon { } { + if { [env_var_exists_and_non_empty PLACE_DENSITY_LB_ADDON] } { # check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON set place_density_lb [gpl::get_global_placement_uniform_density \ - -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ - -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)] + -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ + -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)] set place_density [expr $place_density_lb + ((1.0 - $place_density_lb) * $::env(PLACE_DENSITY_LB_ADDON)) + 0.01] - if {$place_density > 1.0} { + if { $place_density > 1.0 } { utl::error FLW 24 "Place density exceeds 1.0 (current PLACE_DENSITY_LB_ADDON = $::env(PLACE_DENSITY_LB_ADDON)). Please check if the value of PLACE_DENSITY_LB_ADDON is between 0 and 0.99." } puts "Placement density is $place_density, computed from PLACE_DENSITY_LB_ADDON $::env(PLACE_DENSITY_LB_ADDON) and lower bound $place_density_lb" diff --git a/flow/scripts/view_cells.tcl b/flow/scripts/view_cells.tcl index d6bf433d9a..c7a4ca087c 100644 --- a/flow/scripts/view_cells.tcl +++ b/flow/scripts/view_cells.tcl @@ -2,7 +2,7 @@ read_lef $::env(TECH_LEF) read_lef $::env(SC_LEF) -if {[info exist ::env(ADDITIONAL_LEFS)]} { +if { [info exist ::env(ADDITIONAL_LEFS)] } { foreach lef $::env(ADDITIONAL_LEFS) { read_lef $lef } @@ -16,9 +16,9 @@ set block [odb::dbBlock_create $chip all_cells] # Get all the masters set masters {} foreach lib [$db getLibs] { - foreach master [$lib getMasters] { - lappend masters $master - } + foreach master [$lib getMasters] { + lappend masters $master + } } # Find the number of masters & the max width and height of any master @@ -26,9 +26,9 @@ set max_width 0 set max_height 0 set num_masters 0 foreach master $masters { - set max_width [expr max($max_width, [$master getWidth])] - set max_height [expr max($max_height, [$master getHeight])] - incr num_masters + set max_width [expr max($max_width, [$master getWidth])] + set max_height [expr max($max_height, [$master getHeight])] + incr num_masters } # The steps for laying out the cells @@ -42,15 +42,15 @@ set x_width [expr ceil(sqrt($num_masters * $y_step / $x_step))] set x 0 set y 0 foreach master $masters { - set inst [odb::dbInst_create $block $master [$master getName]] - $inst setPlacementStatus PLACED - $inst setLocation [expr $x * $x_step] [expr $y * $y_step] - - incr x - if {$x == $x_width} { - set x 0 - incr y - } + set inst [odb::dbInst_create $block $master [$master getName]] + $inst setPlacementStatus PLACED + $inst setLocation [expr $x * $x_step] [expr $y * $y_step] + + incr x + if { $x == $x_width } { + set x 0 + incr y + } } gui::design_created gui::fit diff --git a/flow/scripts/write_ref_sdc.tcl b/flow/scripts/write_ref_sdc.tcl index 5de57dc045..60c6bb7658 100644 --- a/flow/scripts/write_ref_sdc.tcl +++ b/flow/scripts/write_ref_sdc.tcl @@ -19,7 +19,7 @@ if { [llength $clks] == 0 } { set ref_period [expr ($period - $slack) * (1.0 - $margin/100.0)] utl::info "FLW" 8 "Clock $clk_name period [format %.3f $ref_period]" utl::info "FLW" 9 "Clock $clk_name slack [format %.3f $slack]" - + set sources [$clk sources] # Redefine clock with updated period. create_clock -name $clk_name -period $ref_period $sources diff --git a/flow/tutorials/scripts/drt/drc_fix.tcl b/flow/tutorials/scripts/drt/drc_fix.tcl index e62042582a..b54c0fe41d 100644 --- a/flow/tutorials/scripts/drt/drc_fix.tcl +++ b/flow/tutorials/scripts/drt/drc_fix.tcl @@ -9,8 +9,8 @@ read_sdc ./gcd/gcd.sdc set_global_routing_layer_adjustment met1-met5 0.5 set_routing_layers -signal met1-met5 global_route -guide_file [make_result_file route.guide] \ - -congestion_iterations 100 \ - -verbose + -congestion_iterations 100 \ + -verbose source ../../../platforms/sky130hd/setRC.tcl set_propagated_clock [all_clocks] @@ -22,10 +22,10 @@ set_thread_count 2 set drc_rpt [make_result_file 5_route_drc.rpt] set maze_log [make_result_file maze.log] detailed_route -output_drc $drc_rpt \ - -output_maze $maze_log \ - -bottom_routing_layer met1 \ - -top_routing_layer met5 \ - -verbose 1 + -output_maze $maze_log \ + -bottom_routing_layer met1 \ + -top_routing_layer met5 \ + -verbose 1 set route_def [make_result_file 5_route.def] write_def $route_def puts "Number of DRC Violations = [detailed_route_num_drvs]" diff --git a/flow/tutorials/scripts/drt/drc_issue.tcl b/flow/tutorials/scripts/drt/drc_issue.tcl index 0ea32dce63..8ddc41817e 100644 --- a/flow/tutorials/scripts/drt/drc_issue.tcl +++ b/flow/tutorials/scripts/drt/drc_issue.tcl @@ -9,8 +9,8 @@ read_sdc ./gcd/gcd.sdc set_global_routing_layer_adjustment met1-met5 0.5 set_routing_layers -signal met1-met5 global_route -guide_file [make_result_file route.guide] \ - -congestion_iterations 100 \ - -verbose + -congestion_iterations 100 \ + -verbose source ../../../platforms/sky130hd/setRC.tcl set_propagated_clock [all_clocks] @@ -22,10 +22,10 @@ set_thread_count 2 set drc_rpt [make_result_file 5_route_drc.rpt] set maze_log [make_result_file maze.log] detailed_route -output_drc $drc_rpt \ - -output_maze $maze_log \ - -bottom_routing_layer met1 \ - -top_routing_layer met5 \ - -verbose 1 + -output_maze $maze_log \ + -bottom_routing_layer met1 \ + -top_routing_layer met5 \ + -verbose 1 set route_def [make_result_file 5_route.def] write_def $route_def puts "Number of DRC Violations = [detailed_route_num_drvs]" diff --git a/flow/tutorials/scripts/drt/helpers.tcl b/flow/tutorials/scripts/drt/helpers.tcl index be1af8e7c2..bfb1fe8386 100644 --- a/flow/tutorials/scripts/drt/helpers.tcl +++ b/flow/tutorials/scripts/drt/helpers.tcl @@ -14,7 +14,7 @@ proc make_result_file { filename } { # puts [exec cat $file] without forking. proc report_file { file } { set stream [open $file r] - + while { [gets $stream line] >= 0 } { puts $line } @@ -24,9 +24,9 @@ proc report_file { file } { proc diff_files { file1 file2 } { set stream1 [open $file1 r] set stream2 [open $file2 r] - + set line 1 - set diff_line 0; + set diff_line 0 while { [gets $stream1 line1] >= 0 && [gets $stream2 line2] >= 0 } { if { $line1 != $line2 } { set diff_line $line diff --git a/flow/tutorials/scripts/gui/load_lef.tcl b/flow/tutorials/scripts/gui/load_lef.tcl index 259bdb4c03..34d5760cb8 100644 --- a/flow/tutorials/scripts/gui/load_lef.tcl +++ b/flow/tutorials/scripts/gui/load_lef.tcl @@ -1,6 +1,6 @@ -proc load_lef_sky130 {} { - set FLOW_PATH [exec pwd] - read_lef $FLOW_PATH/../../../platforms/sky130hd/lef/sky130_fd_sc_hd.tlef - read_lef $FLOW_PATH/../../../platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef +proc load_lef_sky130 { } { + set FLOW_PATH [exec pwd] + read_lef $FLOW_PATH/../../../platforms/sky130hd/lef/sky130_fd_sc_hd.tlef + read_lef $FLOW_PATH/../../../platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef } create_toolbar_button -name "Load_LEF" -text "Load_LEF" -script {load_lef_sky130} -echo diff --git a/flow/util/cell-veneer/lefdef.tcl b/flow/util/cell-veneer/lefdef.tcl index 2507dd5fb9..76e02aa17e 100644 --- a/flow/util/cell-veneer/lefdef.tcl +++ b/flow/util/cell-veneer/lefdef.tcl @@ -1,18 +1,16 @@ -proc absolute_rectangle {rect offset} { - return [list \ - [expr [lindex $rect 0] + [lindex $offset 0]] \ - [expr [lindex $rect 1] + [lindex $offset 1]] \ - [expr [lindex $rect 2] + [lindex $offset 0]] \ - [expr [lindex $rect 3] + [lindex $offset 1]] \ - ] -} -proc relative_rectangle {rect offset} { - return [list \ - [expr [lindex $rect 0] - [lindex $offset 0]] \ - [expr [lindex $rect 1] - [lindex $offset 1]] \ - [expr [lindex $rect 2] - [lindex $offset 0]] \ - [expr [lindex $rect 3] - [lindex $offset 1]] \ - ] +proc absolute_rectangle { rect offset } { + return [list \ + [expr [lindex $rect 0] + [lindex $offset 0]] \ + [expr [lindex $rect 1] + [lindex $offset 1]] \ + [expr [lindex $rect 2] + [lindex $offset 0]] \ + [expr [lindex $rect 3] + [lindex $offset 1]]] +} +proc relative_rectangle { rect offset } { + return [list \ + [expr [lindex $rect 0] - [lindex $offset 0]] \ + [expr [lindex $rect 1] - [lindex $offset 1]] \ + [expr [lindex $rect 2] - [lindex $offset 0]] \ + [expr [lindex $rect 3] - [lindex $offset 1]]] } if [package vcompare 8.6 $tcl_version] { @@ -25,919 +23,921 @@ if [package vcompare 8.6 $tcl_version] { } namespace eval lef { - variable lefOut stdout - variable def_units 2000 - - proc open {file_name} { - variable lefOut - set lefOut [::open $file_name w] - } - - proc close {} { - variable lefOut - if {$lefOut != "stdout"} { - ::close $lefOut - } - set lefOut stdout - } - - proc out {args} { - variable lefOut - - if {[llength $args] == 2} { - puts [lindex $args 0] $lefOut [lindex $args 1] - } else { - puts $lefOut [lindex $args 0] - } - } +variable lefOut stdout +variable def_units 2000 - variable cells - - proc get_cells {} { - variable cells - return $cells - } - - proc get_cell {cell_name} { - variable cells - return [dict get $cells $cell_name] - } - - proc get_width {cell} { - return [expr [lindex [dict get $cell die_area] 2] - [lindex [dict get $cell die_area] 0]] - } - - proc get_height {cell} { - return [expr [lindex [dict get $cell die_area] 3] - [lindex [dict get $cell die_area] 1]] - } - - proc read_macros {file_name} { - variable cells - variable def_units - - set ch [::open $file_name] - - set cells {} +proc open { file_name } { + variable lefOut + set lefOut [::open $file_name w] +} - while {![eof $ch]} { - set line [gets $ch] +proc close { } { + variable lefOut + if { $lefOut != "stdout" } { + ::close $lefOut + } + set lefOut stdout +} - if {[regexp {MACRO\s*([^\s]*)} $line - cell_name]} { - dict set cells $cell_name units $def_units - dict set cells $cell_name name $cell_name - while {![eof $ch]} { - set line [gets $ch] - if {[regexp {^\s*$} $line]} { - continue - } elseif {[regexp {CLASS\s+([^\s]*)} $line - cell_class]} { - dict set cells $cell_name cell_class $cell_class - } elseif {[regexp {ORIGIN\s+([^\s]*)\s+([^\s]*)} $line - origin_x origin_y]} { - dict set cells $cell_name origin [lmap x [list $origin_x $origin_y] {expr round($x * $def_units)}] - } elseif {[regexp {FOREIGN\s+([^\s]*)\s+([^\s]*)\s+([^\s]*)} $line - foreign x y]} { - dict set cells $cell_name foreign [list ref $foreign origin [lmap x [list $x $y] {expr round($x * $def_units)}]] - } elseif {[regexp {SIZE\s+([^\s]*)\s+BY\s+([^\s]*)} $line - width height]} { - dict set cells $cell_name die_area [list 0 0 [expr round($width * $def_units)] [expr round($height * $def_units)]] - } elseif {[regexp {SYMMETRY\s+(.*)\s;} $line - symmetry]} { - dict set cells $cell_name symmetry $symmetry - } elseif {[regexp {SITE\s+([^\s]*)} $line - site]} { - dict set cells $cell_name site $site - } elseif {[regexp {PIN\s*([^\s]*)} $line - pin_name]} { - set pin_pattern [regsub -all {([\[\]])} $pin_name {\\\1}] - if {[info vars antennamodel] != ""} { - unset antennamodel - } - while {![eof $ch]} { - set line [gets $ch] - if {[regexp {^\s*$} $line]} { - continue - } elseif {[regexp {DIRECTION\s+([^\s]*)} $line - direction]} { - dict set cells $cell_name pins $pin_name direction $direction - } elseif {[regexp {USE\s+([^\s]*)} $line - use]} { - dict set cells $cell_name pins $pin_name use $use - } elseif {[regexp {ANTENNAMODEL\s+([^\s]*)} $line - antennamodel]} { - continue - } elseif {[regexp {ANTENNAGATEAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - gate_area layer]} { - if {[info vars antennamodel] == ""} { - set antennamodel "default" - } - if {[dict exists $cells $cell_name pins $pin_name antenna_model $antennamodel]} { - set model [dict get $cells $cell_name pins $pin_name antenna_model $antennamodel] - } else { - set model {} - } - lappend model [list gate_area $gate_area layer $layer] - dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model - } elseif {[regexp {ANTENNAGATEAREA\s+([^\s]*)} $line - gate_area]} { - if {[info vars antennamodel] == ""} { - set antennamodel "default" - } - if {[dict exists $cells $cell_name pins $pin_name antenna_model $antennamodel]} { - set model [dict get $cells $cell_name pins $pin_name antenna_model $antennamodel] - } else { - set model {} - } - lappend model [list gate_area $gate_area] - dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model - } elseif {[regexp {ANTENNADIFFAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - antennadiffarea layer]} { - dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea - dict set cells $cell_name pins $pin_name antennadiffarea layer $antennadiffarea - } elseif {[regexp {ANTENNADIFFAREA\s+([^\s]*)\s} $line - antennadiffarea]} { - dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea - } elseif {[regexp {SHAPE\s+([^\s]*)\s+([^\s]*)} $line - shape]} { - dict set cells $cell_name pins $pin_name shape $shape - } elseif {[regexp {PORT} $line]} { - set port {} - dict set port orientation N - while {![eof $ch]} { - set line [gets $ch] - if {[regexp {^\s*$} $line]} { - continue - } elseif {[regexp {LAYER\s+([^\s]*)} $line - layer]} { - continue - } elseif {[regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2]} { - if {[dict exists $port layers $layer shapes]} { - set layer_shapes [dict get $port layers $layer shapes] - } else { - set layer_shapes {} - } - if {[dict exists $port fixed]} { - set offset [dict get $port fixed] - } else { - set offset [lmap x [list $x1 $y1] {expr round($x * $def_units)}] - dict set port fixed $offset - } - set new_shape [list \ - rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] {expr round($x * $def_units)}] $offset] \ - mask $mask \ - ] - lappend layer_shapes $new_shape - dict set port layers $layer shapes $layer_shapes - } elseif {[regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2]} { - if {[dict exists $port layers $layer shapes]} { - set layer_shapes [dict get $port layers $layer shapes] - } else { - set layer_shapes {} - } - if {[dict exists $port fixed]} { - set offset [dict get $port fixed] - } else { - set offset [lmap x [list $x1 $y1] {expr round($x * $def_units)}] - dict set port fixed $offset - } - set new_shape [list \ - rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] {expr round($x * $def_units)}] $offset] \ - ] - lappend layer_shapes $new_shape - dict set port layers $layer shapes $layer_shapes - } elseif {[regexp {END} $line]} { - if {[dict exists $cells $cell_name pins $pin_name ports]} { - set ports [dict get $cells $cell_name pins $pin_name ports] - } else { - set ports {} - } - lappend ports $port - dict set cells $cell_name pins $pin_name ports $ports - break - } else { - error "Parsing failure PORT:\n$line" - } - } - } elseif {[regexp "END\\s$pin_pattern" $line]} { - break - } else { - error "Parsing failure PIN:\n$line" - } - } - } elseif {[regexp {OBS} $line]} { - while {![eof $ch]} { - set line [gets $ch] - if {[regexp {^\s*$} $line]} { - continue - } elseif {[regexp {LAYER\s+([^\s]*)(\s+DESIGNRULEWIDTH\s+([0-9.]+))?} $line - layer - drw]} { - if {$drw != ""} { - dict set cells $cell_name layers $layer drw $drw - } - continue - } elseif {[regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2]} { - if {[dict exists $cells $cell_name obstructions $layer]} { - set obstructions [dict get $cells $cell_name obstructions $layer] - } else { - set obstructions {} - } - lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] {expr round($x * $def_units)}] mask $mask] - dict set cells $cell_name obstructions $layer $obstructions - } elseif {[regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2]} { - if {[dict exists $cells $cell_name obstructions $layer]} { - set obstructions [dict get $cells $cell_name obstructions $layer] - } else { - set obstructions {} - } - lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] {expr round($x * $def_units)}]] - dict set cells $cell_name obstructions $layer $obstructions - } elseif {[regexp {END} $line]} { - break - } else { - error "Parsing failure OBS:\n$line" - } - } - } elseif {[regexp "END\\s*$cell_name" $line]} { - break - } else { - error "Parsing failure MACRO\n$line" - } - } - } - } +proc out { args } { + variable lefOut - ::close $ch - } + if { [llength $args] == 2 } { + puts [lindex $args 0] $lefOut [lindex $args 1] + } else { + puts $lefOut [lindex $args 0] + } +} - proc get_blockage_layers {design} { - if {[dict exists $design blockage_layers]} { - return [dict get $design blockage_layers] - } +variable cells - set blocked_layers {} +proc get_cells { } { + variable cells + return $cells +} - dict for {layer_name obstructions} [dict get $design obstructions] { - lappend blocked_layers $layer_name - } - return $blocked_layers - } +proc get_cell { cell_name } { + variable cells + return [dict get $cells $cell_name] +} - proc write_header {} { - } - proc write_footer {} { - } - # Read a LEF from a file into a dictionary with the name of the cell as the key and the following entries - # - cell_class - # - origin - # - foreign - # - ref - # - origin - # - die_area - # - symmetry - # - site - # - pins: dict with the name of the pin as the key - # - antenna_model - # - gate_area - # - layer - # - antennadiffarea - # - layer - # - area - # - direction - # - use - # - shape - # - ports: a list of lists of shapes that make up a physical connection - # - layer - # - rect - # - mask? - # - obstructions - # - layer: a dictionaries with layer_name as the key - # - rect - # - mask? - # - proc write {design} { - set def_units [dict get $design units] - - out "MACRO [dict get $design name]" - out " CLASS [dict get $design cell_class] ;" - if {[dict exists $design origin]} { - out " ORIGIN [dict get $design origin] ;" - } else { - out " ORIGIN 0.0 0.0 ;" - } - out " FOREIGN [dict get $design foreign ref] [dict get $design foreign origin] ;" - out " SIZE [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units] BY [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units] ;" - out " SYMMETRY [dict get $design symmetry] ;" - if {[dict exists $design site]} { - out " SITE [dict get $design site] ;" - } +proc get_width { cell } { + return [expr [lindex [dict get $cell die_area] 2] - [lindex [dict get $cell die_area] 0]] +} - if {[dict exists $design pins]} { - dict for {pin_name pin} [dict get $design pins] { - out " PIN $pin_name" - out " DIRECTION [dict get $pin direction] ;" - if {[dict exists $pin use]} { - out " USE [dict get $pin use] ;" - } - foreach port [dict get $pin ports] { - out " PORT " - foreach layer_name [dict keys [dict get $port layers]] { - set shapes [dict get $port layers $layer_name shapes] - - out " LAYER $layer_name ;" - foreach shape $shapes { - if {[dict exists $port fixed]} { - set offset [dict get $port fixed] - } elseif {[dict exists $port placed]} { - set offset [dict get $port placed] - } else { - set offset [list 0 0] - } - set rect [absolute_rectangle [dict get $shape rect] $offset] - - if {[dict exists $shape mask]} { - out " RECT MASK [dict get $shape mask] [lmap x $rect {expr 1.0 * $x / $def_units}] ;" - } else { - out " RECT [lmap x $rect {expr 1.0 * $x / $def_units}] ;" - } - } - } - out " END " - } - out " END $pin_name" - } - } +proc get_height { cell } { + return [expr [lindex [dict get $cell die_area] 3] - [lindex [dict get $cell die_area] 1]] +} - if {[dict exists $design obstructions]} { - out " OBS" - if {[dict get $design use_sheet_obstructions]} { - dict for {layer_name obstructions} [dict get $design obstructions] { - lappend blocked_layers $layer_name +proc read_macros { file_name } { + variable cells + variable def_units + + set ch [::open $file_name] + + set cells {} + + while { ![eof $ch] } { + set line [gets $ch] + + if { [regexp {MACRO\s*([^\s]*)} $line - cell_name] } { + dict set cells $cell_name units $def_units + dict set cells $cell_name name $cell_name + while { ![eof $ch] } { + set line [gets $ch] + if { [regexp {^\s*$} $line] } { + continue + } elseif { [regexp {CLASS\s+([^\s]*)} $line - cell_class] } { + dict set cells $cell_name cell_class $cell_class + } elseif { [regexp {ORIGIN\s+([^\s]*)\s+([^\s]*)} $line - origin_x origin_y] } { + dict set cells $cell_name origin [lmap x [list $origin_x $origin_y] { expr round($x * $def_units) }] + } elseif { [regexp {FOREIGN\s+([^\s]*)\s+([^\s]*)\s+([^\s]*)} $line - foreign x y] } { + dict set cells $cell_name foreign [list ref $foreign origin [lmap x [list $x $y] { expr round($x * $def_units) }]] + } elseif { [regexp {SIZE\s+([^\s]*)\s+BY\s+([^\s]*)} $line - width height] } { + dict set cells $cell_name die_area [list 0 0 [expr round($width * $def_units)] [expr round($height * $def_units)]] + } elseif { [regexp {SYMMETRY\s+(.*)\s;} $line - symmetry] } { + dict set cells $cell_name symmetry $symmetry + } elseif { [regexp {SITE\s+([^\s]*)} $line - site] } { + dict set cells $cell_name site $site + } elseif { [regexp {PIN\s*([^\s]*)} $line - pin_name] } { + set pin_pattern [regsub -all {([\[\]])} $pin_name {\\\1}] + if { [info vars antennamodel] != "" } { + unset antennamodel + } + while { ![eof $ch] } { + set line [gets $ch] + if { [regexp {^\s*$} $line] } { + continue + } elseif { [regexp {DIRECTION\s+([^\s]*)} $line - direction] } { + dict set cells $cell_name pins $pin_name direction $direction + } elseif { [regexp {USE\s+([^\s]*)} $line - use] } { + dict set cells $cell_name pins $pin_name use $use + } elseif { [regexp {ANTENNAMODEL\s+([^\s]*)} $line - antennamodel] } { + continue + } elseif { [regexp {ANTENNAGATEAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - gate_area layer] } { + if { [info vars antennamodel] == "" } { + set antennamodel "default" + } + if { [dict exists $cells $cell_name pins $pin_name antenna_model $antennamodel] } { + set model [dict get $cells $cell_name pins $pin_name antenna_model $antennamodel] + } else { + set model {} + } + lappend model [list gate_area $gate_area layer $layer] + dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model + } elseif { [regexp {ANTENNAGATEAREA\s+([^\s]*)} $line - gate_area] } { + if { [info vars antennamodel] == "" } { + set antennamodel "default" } - set sheet "0 0 [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units] [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units]" - foreach layer_name [get_blockage_layers $design] { - if {[dict exists $design layers $layer_name drw]} { - set drw "DESIGNRULEWIDTH [dict get $design layers $layer_name drw] " + if { [dict exists $cells $cell_name pins $pin_name antenna_model $antennamodel] } { + set model [dict get $cells $cell_name pins $pin_name antenna_model $antennamodel] + } else { + set model {} + } + lappend model [list gate_area $gate_area] + dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model + } elseif { [regexp {ANTENNADIFFAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - antennadiffarea layer] } { + dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea + dict set cells $cell_name pins $pin_name antennadiffarea layer $antennadiffarea + } elseif { [regexp {ANTENNADIFFAREA\s+([^\s]*)\s} $line - antennadiffarea] } { + dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea + } elseif { [regexp {SHAPE\s+([^\s]*)\s+([^\s]*)} $line - shape] } { + dict set cells $cell_name pins $pin_name shape $shape + } elseif { [regexp {PORT} $line] } { + set port {} + dict set port orientation N + while { ![eof $ch] } { + set line [gets $ch] + if { [regexp {^\s*$} $line] } { + continue + } elseif { [regexp {LAYER\s+([^\s]*)} $line - layer] } { + continue + } elseif { [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] } { + if { [dict exists $port layers $layer shapes] } { + set layer_shapes [dict get $port layers $layer shapes] + } else { + set layer_shapes {} + } + if { [dict exists $port fixed] } { + set offset [dict get $port fixed] + } else { + set offset [lmap x [list $x1 $y1] { expr round($x * $def_units) }] + dict set port fixed $offset + } + set new_shape [list \ + rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] $offset] \ + mask $mask] + lappend layer_shapes $new_shape + dict set port layers $layer shapes $layer_shapes + } elseif { [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] } { + if { [dict exists $port layers $layer shapes] } { + set layer_shapes [dict get $port layers $layer shapes] + } else { + set layer_shapes {} + } + if { [dict exists $port fixed] } { + set offset [dict get $port fixed] + } else { + set offset [lmap x [list $x1 $y1] { expr round($x * $def_units) }] + dict set port fixed $offset + } + set new_shape [list \ + rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] $offset]] + lappend layer_shapes $new_shape + dict set port layers $layer shapes $layer_shapes + } elseif { [regexp {END} $line] } { + if { [dict exists $cells $cell_name pins $pin_name ports] } { + set ports [dict get $cells $cell_name pins $pin_name ports] + } else { + set ports {} + } + lappend ports $port + dict set cells $cell_name pins $pin_name ports $ports + break } else { - set drw "" + error "Parsing failure PORT:\n$line" } - out " LAYER $layer_name $drw;" - out " RECT $sheet ;" } + } elseif { [regexp "END\\s$pin_pattern" $line] } { + break } else { - dict for {layer_name obstructions} [dict get $design obstructions] { - out " LAYER $layer_name ;" - foreach obs $obstructions { - if {[dict exists $obs mask]} { - out " RECT MASK [dict get $obs mask] [lmap x [dict get $obs rect] {expr 1.0 * $x / $def_units}] ;" - } else { - out " RECT [lmap x [dict get $obs rect] {expr 1.0 * $x / $def_units}] ;" - } - } + error "Parsing failure PIN:\n$line" + } + } + } elseif { [regexp {OBS} $line] } { + while { ![eof $ch] } { + set line [gets $ch] + if { [regexp {^\s*$} $line] } { + continue + } elseif { [regexp {LAYER\s+([^\s]*)(\s+DESIGNRULEWIDTH\s+([0-9.]+))?} $line - layer - drw] } { + if { $drw != "" } { + dict set cells $cell_name layers $layer drw $drw + } + continue + } elseif { [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] } { + if { [dict exists $cells $cell_name obstructions $layer] } { + set obstructions [dict get $cells $cell_name obstructions $layer] + } else { + set obstructions {} + } + lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] mask $mask] + dict set cells $cell_name obstructions $layer $obstructions + } elseif { [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] } { + if { [dict exists $cells $cell_name obstructions $layer] } { + set obstructions [dict get $cells $cell_name obstructions $layer] + } else { + set obstructions {} } + lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }]] + dict set cells $cell_name obstructions $layer $obstructions + } elseif { [regexp {END} $line] } { + break + } else { + error "Parsing failure OBS:\n$line" } - out " END" + } + } elseif { [regexp "END\\s*$cell_name" $line] } { + break + } else { + error "Parsing failure MACRO\n$line" } - out "END [dict get $design name]" - out "" + } } - - proc write_cells {file_name cells} { - lef open $file_name - - out "###############################################################" - out "# Created by cell-veneer" - out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]" - out "###############################################################" - out "" - out "VERSION 5.8 ;" - out "BUSBITCHARS \"\[\]\" ;" - out "DIVIDERCHAR \"/\" ;" - out "" - out "SITE sc10p5mcpp84_14lpp" - out " CLASS CORE ;" - out " SIZE 0.084 BY 0.672 ;" - out " SYMMETRY Y ;" - out "END sc10p5mcpp84_14lpp" - out "" - out "SITE sc10p5mcpp84_14lpp_pg" - out " CLASS CORE ;" - out " SIZE 0.084 BY 1.344 ;" - out " SYMMETRY Y ;" - out "END sc10p5mcpp84_14lpp_pg" - out "" + } - dict for {cell_name cell} $cells { - lef write $cell - } + ::close $ch +} - out "END LIBRARY" - out "" - lef close - } +proc get_blockage_layers { design } { + if { [dict exists $design blockage_layers] } { + return [dict get $design blockage_layers] + } - proc write_macros {file_name cells} { - lef open $file_name + set blocked_layers {} - out "###############################################################" - out "# Created by cell-veneer" - out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]" - out "###############################################################" - out "" - out "VERSION 5.8 ;" - out "BUSBITCHARS \"\[\]\" ;" - out "DIVIDERCHAR \"/\" ;" - out "" + dict for {layer_name obstructions} [dict get $design obstructions] { + lappend blocked_layers $layer_name + } + return $blocked_layers +} - dict for {cell_name cell} $cells { - lef write $cell - } +proc write_header { } { - out "END LIBRARY" - out "" - lef close - } +} +proc write_footer { } { - namespace export read_macros get_width get_height - namespace export get_cell get_cells write write_cells write_macros - namespace export open close out - namespace ensemble create } +# Read a LEF from a file into a dictionary with the name of the cell as the key and the following entries +# - cell_class +# - origin +# - foreign +# - ref +# - origin +# - die_area +# - symmetry +# - site +# - pins: dict with the name of the pin as the key +# - antenna_model +# - gate_area +# - layer +# - antennadiffarea +# - layer +# - area +# - direction +# - use +# - shape +# - ports: a list of lists of shapes that make up a physical connection +# - layer +# - rect +# - mask? +# - obstructions +# - layer: a dictionaries with layer_name as the key +# - rect +# - mask? +# +proc write { design } { + set def_units [dict get $design units] + + out "MACRO [dict get $design name]" + out " CLASS [dict get $design cell_class] ;" + if { [dict exists $design origin] } { + out " ORIGIN [dict get $design origin] ;" + } else { + out " ORIGIN 0.0 0.0 ;" + } + out " FOREIGN [dict get $design foreign ref] [dict get $design foreign origin] ;" + out " SIZE [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units] BY [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units] ;" + out " SYMMETRY [dict get $design symmetry] ;" + if { [dict exists $design site] } { + out " SITE [dict get $design site] ;" + } + + if { [dict exists $design pins] } { + dict for {pin_name pin} [dict get $design pins] { + out " PIN $pin_name" + out " DIRECTION [dict get $pin direction] ;" + if { [dict exists $pin use] } { + out " USE [dict get $pin use] ;" + } + foreach port [dict get $pin ports] { + out " PORT " + foreach layer_name [dict keys [dict get $port layers]] { + set shapes [dict get $port layers $layer_name shapes] + + out " LAYER $layer_name ;" + foreach shape $shapes { + if { [dict exists $port fixed] } { + set offset [dict get $port fixed] + } elseif { [dict exists $port placed] } { + set offset [dict get $port placed] + } else { + set offset [list 0 0] + } + set rect [absolute_rectangle [dict get $shape rect] $offset] -namespace eval def { - variable def_units - variable defOut stdout - variable designs {} - - proc open {file_name} { - variable defOut - set defOut [::open $file_name w] - } - - proc close {} { - variable defOut - if {$defOut != "stdout"} { - ::close $defOut + if { [dict exists $shape mask] } { + out " RECT MASK [dict get $shape mask] [lmap x $rect { expr 1.0 * $x / $def_units }] ;" + } else { + out " RECT [lmap x $rect { expr 1.0 * $x / $def_units }] ;" + } + } } - set defOut stdout + out " END " + } + out " END $pin_name" } - - proc out {args} { - variable defOut - - if {[llength $args] == 2} { - puts [lindex $args 0] $defOut [lindex $args 1] + } + + if { [dict exists $design obstructions] } { + out " OBS" + if { [dict get $design use_sheet_obstructions] } { + dict for {layer_name obstructions} [dict get $design obstructions] { + lappend blocked_layers $layer_name + } + set sheet "0 0 [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units] [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units]" + foreach layer_name [get_blockage_layers $design] { + if { [dict exists $design layers $layer_name drw] } { + set drw "DESIGNRULEWIDTH [dict get $design layers $layer_name drw] " } else { - puts $defOut [lindex $args 0] + set drw "" } + out " LAYER $layer_name $drw;" + out " RECT $sheet ;" + } + } else { + dict for {layer_name obstructions} [dict get $design obstructions] { + out " LAYER $layer_name ;" + foreach obs $obstructions { + if { [dict exists $obs mask] } { + out " RECT MASK [dict get $obs mask] [lmap x [dict get $obs rect] { expr 1.0 * $x / $def_units }] ;" + } else { + out " RECT [lmap x [dict get $obs rect] { expr 1.0 * $x / $def_units }] ;" + } + } + } } + out " END" + } + out "END [dict get $design name]" + out "" +} - # Write out DEF from a design structure which is a dictionary with the following keys - # - name - # - tool - # - units - # - die_area - # - core_area - # - rows: dict with the index of the row as the key - # - site - # - start - # - height - # - orientation - # - num_sites - # - site_width - # - pins: dict with the name of the pin as the key - # - net_name - # - direction - # - use - # - special - # - ports : a list of dictionaries, one per port - # - orientation - # - (placed|fixed) - # - layers - # - spacing - # - designrulewidth - # - shapes : list of rectangles (or polygons) - # - (rect|polygon) - # - physical_viarules: dict with the name of the viarule as the key - # - rule - # - cutsize - # - layers - # - cutspacing - # - enclosure - # - rowcol - # - components: dict with the instance name of the component as the key - # - inst_name - # - cell_name - # - (fixed|placed)? - # - orientation - # - nets: dict with the name of the net as the key - # - use: SIGNAL | POWER | GROUND - # - connections: list of instance pin pairs - # - routes: list of dictionaries - # - layer - # - points: list of points, where a point can be an XY location or the name of a VIA - # - special_nets: dict with the name of the net as the key - # - use: SIGNAL | POWER | GROUND - # - connections: list of instance pin pairs - # - routes: list of dictioaries - # - layer - # - width - # - shape - # - points: list of points, where a point can be an XY location or the name of a VIA - # - - proc shift_point {point x y} { - return [list [expr [lindex $point 0] + $x] [expr [lindex $point 1] + $y]] - } - - proc shift_rect {rect x y} { - return [list [expr [lindex $rect 0] + $x] [expr [lindex $rect 1] + $y] [expr [lindex $rect 2] + $x] [expr [lindex $rect 3] + $y]] - } +proc write_cells { file_name cells } { + lef open $file_name + + out "###############################################################" + out "# Created by cell-veneer" + out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]" + out "###############################################################" + out "" + out "VERSION 5.8 ;" + out "BUSBITCHARS \"\[\]\" ;" + out "DIVIDERCHAR \"/\" ;" + out "" + out "SITE sc10p5mcpp84_14lpp" + out " CLASS CORE ;" + out " SIZE 0.084 BY 0.672 ;" + out " SYMMETRY Y ;" + out "END sc10p5mcpp84_14lpp" + out "" + out "SITE sc10p5mcpp84_14lpp_pg" + out " CLASS CORE ;" + out " SIZE 0.084 BY 1.344 ;" + out " SYMMETRY Y ;" + out "END sc10p5mcpp84_14lpp_pg" + out "" + + dict for {cell_name cell} $cells { + lef write $cell + } + + out "END LIBRARY" + out "" + lef close +} - proc shift_origin {design x y} { - if {[dict exists $design die_area]} { - dict set design die_area [shift_rect [dict get $design die_area] $x $y] - } - if {[dict exists $design core_area]} { - dict set design core_area [shift_rect [dict get $design core_area] $x $y] - } - if {[dict exists $design rows]} { - } - if {[dict exists $design pins]} { - dict for {pin_name pin} [dict get $design pins] { - set ports {} - foreach port [dict get $pin ports] { - if {[dict exists $port fixed]} { - dict set port fixed [shift_point [dict get $port fixed] $x $y] - } elseif {[dict exists $port placed]} { - dict set port placed [shift_point [dict get $port placed] $x $y] - } - lappend ports $port - } - dict set design pins $pin_name ports $ports - } - } - if {[dict exists $design components]} { - dict for {inst_name inst} [dict get $design components] { - if {[dict exists $inst fixed]} { - dict set design components $inst_name fixed [shift_point [dict get $inst fixed] $x $y] - } elseif {[dict exists $inst placed]} { - dict set design components $inst_name placed [shift_point [dict get $inst placed] $x $y] - } - } - } - if {[dict exists $design nets]} { - dict for {net_name net} [dict get $design nets] { - if {[dict exists $net routes]} { - set routes {} - foreach route [dict get $net routes] { - set points {} - foreach point $points { - if {[llength $point] == 2} { - lappend points [shift_point $point $x $y] - } else { - lappend points $point - } - } - lappend routes $route - } - dict set design nets $net_name routes $routes - } - } - } - if {[dict exists $design special_nets]} { - dict for {net_name net} [dict get $design special_nets] { - set routes {} - if {[dict exists $net routes]} { - foreach route [dict get $net routes] { - set points {} - foreach point $points { - if {[llength $point] == 2} { - lappend points [shift_point $point $x $y] - } else { - lappend points $point - } - } - lappend routes $route - } - dict set design special_nets $net_name routes $routes - } - } - } - if {[dict exists $design obstructions]} { - dict for {layer_name obstructions} [dict get $design obstructions] { - set new_obs {} - foreach obs $obstructions { - dict set obs rect [def::shift_rect [dict get $obs rect] $x $y] - lappend new_obs $obs - } - dict set design obstructions $layer_name $new_obs - } - } +proc write_macros { file_name cells } { + lef open $file_name + + out "###############################################################" + out "# Created by cell-veneer" + out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]" + out "###############################################################" + out "" + out "VERSION 5.8 ;" + out "BUSBITCHARS \"\[\]\" ;" + out "DIVIDERCHAR \"/\" ;" + out "" + + dict for {cell_name cell} $cells { + lef write $cell + } + + out "END LIBRARY" + out "" + lef close +} - return $design - } +namespace export read_macros get_width get_height +namespace export get_cell get_cells write write_cells write_macros +namespace export open close out +namespace ensemble create +} - variable layer_info {} - proc set_layer_info {layer_name key value} { - variable layer_info +namespace eval def { +variable def_units +variable defOut stdout +variable designs {} - dict set layer_info layers $layer_name $key $value - } +proc open { file_name } { + variable defOut + set defOut [::open $file_name w] +} - proc get_layer_width {layer_name} { - variable layer_info - return [dict get $layer_info layers $layer_name width] - } +proc close { } { + variable defOut + if { $defOut != "stdout" } { + ::close $defOut + } + set defOut stdout +} - proc get_layer_non_preferred_width {layer_name} { - variable layer_info - if {[dict exists $layer_info layers $layer_name non_preferred_width]} { - return [dict get $layer_info layers $layer_name non_preferred_width] - } - return [dict get $layer_info layers $layer_name width] - } +proc out { args } { + variable defOut - proc get_layer_direction {layer_name} { - variable layer_info - return [dict get $layer_info layers $layer_name direction] - } + if { [llength $args] == 2 } { + puts [lindex $args 0] $defOut [lindex $args 1] + } else { + puts $defOut [lindex $args 0] + } +} - proc get_line_direction {points} { - if {[lindex $points 0 0] == [lindex $points 1 0]} { - set direction "VERTICAL" - } elseif {[lindex $points 0 1] == [lindex $points 1 1]} { - set direction "HORIZONTAL" - } else { - error "Non orthogonal line $points" +# Write out DEF from a design structure which is a dictionary with the following keys +# - name +# - tool +# - units +# - die_area +# - core_area +# - rows: dict with the index of the row as the key +# - site +# - start +# - height +# - orientation +# - num_sites +# - site_width +# - pins: dict with the name of the pin as the key +# - net_name +# - direction +# - use +# - special +# - ports : a list of dictionaries, one per port +# - orientation +# - (placed|fixed) +# - layers +# - spacing +# - designrulewidth +# - shapes : list of rectangles (or polygons) +# - (rect|polygon) +# - physical_viarules: dict with the name of the viarule as the key +# - rule +# - cutsize +# - layers +# - cutspacing +# - enclosure +# - rowcol +# - components: dict with the instance name of the component as the key +# - inst_name +# - cell_name +# - (fixed|placed)? +# - orientation +# - nets: dict with the name of the net as the key +# - use: SIGNAL | POWER | GROUND +# - connections: list of instance pin pairs +# - routes: list of dictionaries +# - layer +# - points: list of points, where a point can be an XY location or the name of a VIA +# - special_nets: dict with the name of the net as the key +# - use: SIGNAL | POWER | GROUND +# - connections: list of instance pin pairs +# - routes: list of dictioaries +# - layer +# - width +# - shape +# - points: list of points, where a point can be an XY location or the name of a VIA +# + +proc shift_point { point x y } { + return [list [expr [lindex $point 0] + $x] [expr [lindex $point 1] + $y]] +} + +proc shift_rect { rect x y } { + return [list [expr [lindex $rect 0] + $x] [expr [lindex $rect 1] + $y] [expr [lindex $rect 2] + $x] [expr [lindex $rect 3] + $y]] +} + +proc shift_origin { design x y } { + if { [dict exists $design die_area] } { + dict set design die_area [shift_rect [dict get $design die_area] $x $y] + } + if { [dict exists $design core_area] } { + dict set design core_area [shift_rect [dict get $design core_area] $x $y] + } + if { [dict exists $design rows] } { + + } + if { [dict exists $design pins] } { + dict for {pin_name pin} [dict get $design pins] { + set ports {} + foreach port [dict get $pin ports] { + if { [dict exists $port fixed] } { + dict set port fixed [shift_point [dict get $port fixed] $x $y] + } elseif { [dict exists $port placed] } { + dict set port placed [shift_point [dict get $port placed] $x $y] + } + lappend ports $port + } + dict set design pins $pin_name ports $ports + } + } + if { [dict exists $design components] } { + dict for {inst_name inst} [dict get $design components] { + if { [dict exists $inst fixed] } { + dict set design components $inst_name fixed [shift_point [dict get $inst fixed] $x $y] + } elseif { [dict exists $inst placed] } { + dict set design components $inst_name placed [shift_point [dict get $inst placed] $x $y] + } + } + } + if { [dict exists $design nets] } { + dict for {net_name net} [dict get $design nets] { + if { [dict exists $net routes] } { + set routes {} + foreach route [dict get $net routes] { + set points {} + foreach point $points { + if { [llength $point] == 2 } { + lappend points [shift_point $point $x $y] + } else { + lappend points $point + } + } + lappend routes $route } - return $direction + dict set design nets $net_name routes $routes + } } - proc get_line_width {layer_name points} { - set direction [get_line_direction $points] - - if {[get_layer_direction $layer_name] == $direction} { - return [get_layer_width $layer_name] - } else { - return [get_layer_non_preferred_width $layer_name] + } + if { [dict exists $design special_nets] } { + dict for {net_name net} [dict get $design special_nets] { + set routes {} + if { [dict exists $net routes] } { + foreach route [dict get $net routes] { + set points {} + foreach point $points { + if { [llength $point] == 2 } { + lappend points [shift_point $point $x $y] + } else { + lappend points $point + } + } + lappend routes $route } + dict set design special_nets $net_name routes $routes + } + } + } + if { [dict exists $design obstructions] } { + dict for {layer_name obstructions} [dict get $design obstructions] { + set new_obs {} + foreach obs $obstructions { + dict set obs rect [def::shift_rect [dict get $obs rect] $x $y] + lappend new_obs $obs + } + dict set design obstructions $layer_name $new_obs } + } - proc get_extended_line {layer_name points} { - if {[llength [lindex $points 1]] == 1} { - return "( [lindex $points 0] ) [lindex $points 1]" - } + return $design +} - set direction [get_line_direction $points] +variable layer_info {} +proc set_layer_info { layer_name key value } { + variable layer_info - if {$direction == [get_layer_direction $layer_name]} { - set extension [expr [get_layer_non_preferred_width $layer_name] / 2] - } else { - set extension [expr [get_layer_width $layer_name] / 2] - } + dict set layer_info layers $layer_name $key $value +} - if {$direction == "VERTICAL"} { - set x_min [lindex $points 0 0] - set x_max [lindex $points 0 0] - set y_min [expr min([lindex $points 0 1], [lindex $points 1 1]) - $extension] - set y_max [expr max([lindex $points 0 1], [lindex $points 1 1]) + $extension] - } else { - set x_min [expr min([lindex $points 0 0], [lindex $points 1 0])] - set x_max [expr max([lindex $points 0 0], [lindex $points 1 0])] - set y_min [lindex $points 0 1] - set y_max [lindex $points 0 1] - } +proc get_layer_width { layer_name } { + variable layer_info + return [dict get $layer_info layers $layer_name width] +} - return "( $x_min $y_min ) ( $x_max $y_max )" - } +proc get_layer_non_preferred_width { layer_name } { + variable layer_info + if { [dict exists $layer_info layers $layer_name non_preferred_width] } { + return [dict get $layer_info layers $layer_name non_preferred_width] + } + return [dict get $layer_info layers $layer_name width] +} - proc write {design} { - out "###############################################################" - if {[dict exists $design tool]} { - out "# Created by [dict get $design tool]" - } - out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]" - out "###############################################################" - - out "VERSION 5.8 ;" - out "DIVIDERCHAR \"/\" ;" - out "BUSBITCHARS \"\[\]\" ;" - out "DESIGN [dict get $design name] ;" - out "UNITS DISTANCE MICRONS [dict get $design units] ;" - out "" +proc get_layer_direction { layer_name } { + variable layer_info + return [dict get $layer_info layers $layer_name direction] +} - if {[dict exists $design properties]} { - out "PROPERTYDEFINITIONS " - if {[dict exists $design properties core_area]} { - out "DESIGN FE_CORE_BOX_LL_X REAL [lindex [dict get $design properties core_area] 0] ;" - out "DESIGN FE_CORE_BOX_UR_X REAL [lindex [dict get $design properties core_area] 1] ;" - out "DESIGN FE_CORE_BOX_LL_Y REAL [lindex [dict get $design properties core_area] 2] ;" - out "DESIGN FE_CORE_BOX_UR_Y REAL [lindex [dict get $design properties core_area] 3] ;" - } - out "END PROPERTYDEFINITIONS" - } +proc get_line_direction { points } { + if { [lindex $points 0 0] == [lindex $points 1 0] } { + set direction "VERTICAL" + } elseif { [lindex $points 0 1] == [lindex $points 1 1] } { + set direction "HORIZONTAL" + } else { + error "Non orthogonal line $points" + } + return $direction +} +proc get_line_width { layer_name points } { + set direction [get_line_direction $points] + + if { [get_layer_direction $layer_name] == $direction } { + return [get_layer_width $layer_name] + } else { + return [get_layer_non_preferred_width $layer_name] + } +} - out "" - out "DIEAREA ( [lrange [dict get $design die_area] 0 1] ) ( [lrange [dict get $design die_area] 2 3] ) ;" +proc get_extended_line { layer_name points } { + if { [llength [lindex $points 1]] == 1 } { + return "( [lindex $points 0] ) [lindex $points 1]" + } + + set direction [get_line_direction $points] + + if { $direction == [get_layer_direction $layer_name] } { + set extension [expr [get_layer_non_preferred_width $layer_name] / 2] + } else { + set extension [expr [get_layer_width $layer_name] / 2] + } + + if { $direction == "VERTICAL" } { + set x_min [lindex $points 0 0] + set x_max [lindex $points 0 0] + set y_min [expr min([lindex $points 0 1], [lindex $points 1 1]) - $extension] + set y_max [expr max([lindex $points 0 1], [lindex $points 1 1]) + $extension] + } else { + set x_min [expr min([lindex $points 0 0], [lindex $points 1 0])] + set x_max [expr max([lindex $points 0 0], [lindex $points 1 0])] + set y_min [lindex $points 0 1] + set y_max [lindex $points 0 1] + } + + return "( $x_min $y_min ) ( $x_max $y_max )" +} - if {[dict exists $design tracks]} { - } - - if {[dict exists $design rows]} { - foreach idx [lsort -integer [dict keys $design rows]] { - out -nonewline "ROW ROW_$idx [dict keys $design rows $idx site] [dict keys $design rows $idx start] [dict keys $design rows $idx height] [dict keys $design rows $idx orientation]" - out " DO [dict keys $design rows $idx num_sites] BY 1 STEP [dict keys $design rows $idx site_width] 0 ;" +proc write { design } { + out "###############################################################" + if { [dict exists $design tool] } { + out "# Created by [dict get $design tool]" + } + out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]" + out "###############################################################" + + out "VERSION 5.8 ;" + out "DIVIDERCHAR \"/\" ;" + out "BUSBITCHARS \"\[\]\" ;" + out "DESIGN [dict get $design name] ;" + out "UNITS DISTANCE MICRONS [dict get $design units] ;" + out "" + + if { [dict exists $design properties] } { + out "PROPERTYDEFINITIONS " + if { [dict exists $design properties core_area] } { + out "DESIGN FE_CORE_BOX_LL_X REAL [lindex [dict get $design properties core_area] 0] ;" + out "DESIGN FE_CORE_BOX_UR_X REAL [lindex [dict get $design properties core_area] 1] ;" + out "DESIGN FE_CORE_BOX_LL_Y REAL [lindex [dict get $design properties core_area] 2] ;" + out "DESIGN FE_CORE_BOX_UR_Y REAL [lindex [dict get $design properties core_area] 3] ;" + } + out "END PROPERTYDEFINITIONS" + } + + out "" + out "DIEAREA ( [lrange [dict get $design die_area] 0 1] ) ( [lrange [dict get $design die_area] 2 3] ) ;" + + if { [dict exists $design tracks] } { + + } + + if { [dict exists $design rows] } { + foreach idx [lsort -integer [dict keys $design rows]] { + out -nonewline "ROW ROW_$idx [dict keys $design rows $idx site] [dict keys $design rows $idx start] [dict keys $design rows $idx height] [dict keys $design rows $idx orientation]" + out " DO [dict keys $design rows $idx num_sites] BY 1 STEP [dict keys $design rows $idx site_width] 0 ;" + } + } + + if { [dict exists $design pins] } { + out "" + out "PINS [dict size [dict get $design pins]] ;" + dict for {pin_name pin} [dict get $design pins] { + out -nonewline "- $pin_name + NET [dict get $pin net_name] + DIRECTION [dict get $pin direction] " + if { [dict exists $pin use] } { + out -nonewline "+ USE [dict get $pin use] " + } + if { [dict exists $pin special] } { + out -nonewline "+ SPECIAL " + } + out "" + if { [dict exists $pin ports] } { + foreach port [dict get $pin ports] { + if { [llength [dict get $design pins $pin_name ports]] > 1 } { + out " + PORT " + } + dict for {layer_name layer_info} [dict get $port layers] { + foreach shape [dict get $port layers $layer_name shapes] { + out -nonewline " + LAYER $layer_name " + if { [dict exists $port layers $layer_name spacing] } { + out "SPACING [dict get $port layers $layer_name spacing] " + } elseif { [dict exists $port layers $layer_name designrulewidth] } { + out "DESIGNRULEWIDTH [dict get $port layers $layer_name designrulewidth] " + } + out "( [lrange [dict get $shape rect] 0 1] ) ( [lrange [dict get $shape rect] 2 3] ) " } - } - - if {[dict exists $design pins]} { - out "" - out "PINS [dict size [dict get $design pins]] ;" - dict for {pin_name pin} [dict get $design pins] { - out -nonewline "- $pin_name + NET [dict get $pin net_name] + DIRECTION [dict get $pin direction] " - if {[dict exists $pin use]} { - out -nonewline "+ USE [dict get $pin use] " - } - if {[dict exists $pin special]} { - out -nonewline "+ SPECIAL " - } - out "" - if {[dict exists $pin ports]} { - foreach port [dict get $pin ports] { - if {[llength [dict get $design pins $pin_name ports]] > 1} { - out " + PORT " - } - dict for {layer_name layer_info} [dict get $port layers] { - foreach shape [dict get $port layers $layer_name shapes] { - out -nonewline " + LAYER $layer_name " - if {[dict exists $port layers $layer_name spacing]} { - out "SPACING [dict get $port layers $layer_name spacing] " - } elseif {[dict exists $port layers $layer_name designrulewidth]} { - out "DESIGNRULEWIDTH [dict get $port layers $layer_name designrulewidth] " - } - out "( [lrange [dict get $shape rect] 0 1] ) ( [lrange [dict get $shape rect] 2 3] ) " - } - } - if {[dict exists $port fixed]} { - out " + FIXED ( [dict get $port fixed] ) [dict get $port orientation] " - } elseif {[dict exists $shape placed]} { - out " + PLACED ( [dict get $port placed] ) [dict get $port orientation] " - } - } - out " ;" - } + } + if { [dict exists $port fixed] } { + out " + FIXED ( [dict get $port fixed] ) [dict get $port orientation] " + } elseif { [dict exists $shape placed] } { + out " + PLACED ( [dict get $port placed] ) [dict get $port orientation] " + } + } + out " ;" + } + } + out "END PINS" + } + + ##### Generating via rules + + if { [dict exists $design physical_viarules] } { + out "" + out "VIAS [dict size [dict get $design physical_viarules]] ;" + dict for {name rule} [dict get $design physical_viarules] { + out "- $name" + out " + VIARULE [dict get $rule rule]" + out " + CUTSIZE [dict get $rule cutsize]" + out " + LAYERS [dict get $rule layers]" + out " + CUTSPACING [dict get $rule cutspacing]" + out " + ENCLOSURE [dict get $rule enclosure]" + out " + ROWCOL [dict get $rule rowcol]" + out " ;" + } + out "END VIAS" + } + + if { [dict exists $design components] } { + out "" + out "COMPONENTS [dict size [dict get $design components]] ;" + dict for {inst_name inst} [dict get $design components] { + out -nonewline "- $inst_name [dict get $inst cell_name] " + if { [dict exists $inst fixed] } { + out -nonewline "+ FIXED ( [dict get $inst fixed] ) " + } elseif { [dict exists $inst placed] } { + out -nonewline "+ PLACED ( [dict get $inst placed] ) " + } + if { [dict exists $inst orientation] } { + out -nonewline "[dict get $inst orientation] " + } + out ";" + } + out "END COMPONENTS" + } + + if { [dict exists $design nets] } { + out "" + out "SPECIALNETS [dict size [dict get $design nets]] ;" + dict for {net_name net} [dict get $design nets] { + out -nonewline "- $net_name " + foreach connection [dict get $net connections] { + out " ( $connection )" + } + if { [dict exists $net routes] } { + set type "ROUTED" + foreach route [dict get $net routes] { + set first_point [lindex [dict get $route points] 0] + + foreach point [lrange [dict get $route points] 1 end] { + set points [get_extended_line [dict get $route layer] [list $first_point $point]] + if { [dict exists $route shape] } { + set shape " + SHAPE [dict get $route shape] " + } else { + set shape "" } - out "END PINS" - } - - ##### Generating via rules - - if {[dict exists $design physical_viarules]} { - out "" - out "VIAS [dict size [dict get $design physical_viarules]] ;" - dict for {name rule} [dict get $design physical_viarules] { - out "- $name" - out " + VIARULE [dict get $rule rule]" - out " + CUTSIZE [dict get $rule cutsize]" - out " + LAYERS [dict get $rule layers]" - out " + CUTSPACING [dict get $rule cutspacing]" - out " + ENCLOSURE [dict get $rule enclosure]" - out " + ROWCOL [dict get $rule rowcol]" - out " ;" + if { [dict exists $route mask] } { + set mask "MASK [dict get $route mask] " + } else { + set mask "" } - out "END VIAS" - } - - if {[dict exists $design components]} { - out "" - out "COMPONENTS [dict size [dict get $design components]] ;" - dict for {inst_name inst} [dict get $design components] { - out -nonewline "- $inst_name [dict get $inst cell_name] " - if {[dict exists $inst fixed]} { - out -nonewline "+ FIXED ( [dict get $inst fixed] ) " - } elseif {[dict exists $inst placed]} { - out -nonewline "+ PLACED ( [dict get $inst placed] ) " - } - if {[dict exists $inst orientation]} { - out -nonewline "[dict get $inst orientation] " - } - out ";" + if { [llength $point] == 2 } { + out -nonewline " + $type [dict get $route layer] [get_line_width [dict get $route layer] [list $first_point $point]] " + out -nonewline $shape + out -nonewline $points + out -nonewline $mask + } else { + out -nonewline " + $type [dict get $route layer] 0 " + out -nonewline $shape + out -nonewline $points + out -nonewline $mask } - out "END COMPONENTS" - } - - if {[dict exists $design nets]} { out "" - out "SPECIALNETS [dict size [dict get $design nets]] ;" - dict for {net_name net} [dict get $design nets] { - out -nonewline "- $net_name " - foreach connection [dict get $net connections] { - out " ( $connection )" - } - if {[dict exists $net routes]} { - set type "ROUTED" - foreach route [dict get $net routes] { - set first_point [lindex [dict get $route points] 0] - - foreach point [lrange [dict get $route points] 1 end] { - set points [get_extended_line [dict get $route layer] [list $first_point $point]] - if {[dict exists $route shape]} { - set shape " + SHAPE [dict get $route shape] " - } else { - set shape "" - } - if {[dict exists $route mask]} { - set mask "MASK [dict get $route mask] " - } else { - set mask "" - } - if {[llength $point] == 2} { - out -nonewline " + $type [dict get $route layer] [get_line_width [dict get $route layer] [list $first_point $point]] " - out -nonewline $shape - out -nonewline $points - out -nonewline $mask - } else { - out -nonewline " + $type [dict get $route layer] 0 " - out -nonewline $shape - out -nonewline $points - out -nonewline $mask - } - out "" - set first_point $point - set type "ROUTED" - } - } - } - out " + USE [dict get $net use]\n ;" - } - out "END SPECIALNETS" + set first_point $point + set type "ROUTED" + } } - - if {[dict exists $design special_nets]} { - out "" - out "SPECIALNETS [dict size [dict get $design special_nets]] ;" - dict for {net_name net} [dict get $design special_nets] { - out -nonewline "- $net_name " - foreach connection [dict get $net connections] { - out " ( $connection )" - } - if {[dict exists $net routes]} { - set route [lindex [dict get $net routes] 0] - out -nonewline " + ROUTED [dict get $route layer] [expr round([dict get $route width])] + SHAPE [dict get $route shape] " - foreach point [dict get $route points] { - out -nonewline " $point" - } - out "" - - foreach route [lrange [dict get $net routes] 1 end] { - out " NEW [dict get $route layer] [expr round([dict get $route width])] + SHAPE [dict get $route shape] " - foreach point [dict get $route points] { - out -nonewline " $point" - } - out "" - } - } - out " + USE [dict get $net use]\n ;" - } - out "\nEND SPECIALNETS" + } + out " + USE [dict get $net use]\n ;" + } + out "END SPECIALNETS" + } + + if { [dict exists $design special_nets] } { + out "" + out "SPECIALNETS [dict size [dict get $design special_nets]] ;" + dict for {net_name net} [dict get $design special_nets] { + out -nonewline "- $net_name " + foreach connection [dict get $net connections] { + out " ( $connection )" + } + if { [dict exists $net routes] } { + set route [lindex [dict get $net routes] 0] + out -nonewline " + ROUTED [dict get $route layer] [expr round([dict get $route width])] + SHAPE [dict get $route shape] " + foreach point [dict get $route points] { + out -nonewline " $point" } - out "" - out "END DESIGN" + + foreach route [lrange [dict get $net routes] 1 end] { + out " NEW [dict get $route layer] [expr round([dict get $route width])] + SHAPE [dict get $route shape] " + foreach point [dict get $route points] { + out -nonewline " $point" + } + out "" + } + } + out " + USE [dict get $net use]\n ;" } + out "\nEND SPECIALNETS" + } - proc new_design {design_name units {die_area {0 0 0 0}}} { - variable designs - variable current_design - set current_design $design_name + out "" + out "END DESIGN" +} - dict set designs $current_design [list name $design_name units $units die_area $die_area] - } +proc new_design { design_name units { die_area {0 0 0 0} } } { + variable designs + variable current_design + set current_design $design_name - proc add_component {inst_name cell_name x y orientation status} { - variable designs - variable current_design + dict set designs $current_design [list name $design_name units $units die_area $die_area] +} - dict set designs $current_design components $inst_name inst_name $inst_name - dict set designs $current_design components $inst_name cell_name $cell_name - dict set designs $current_design components $inst_name $status [list $x $y] - dict set designs $current_design components $inst_name orientation $orientation - } - - proc get_current_design {} { - variable designs - variable current_design +proc add_component { inst_name cell_name x y orientation status } { + variable designs + variable current_design - return [dict get $designs $current_design] - } - - proc write_cells {cells} { - dict for {cell_name cell} $cells { - def open ${cell_name}.def - def write $cell - def close - } - } - - proc set_def_units {units} { - variable def_units - - set def_units $units - } - - proc get_def_units {} { - variable def_units - - return $def_units - } - - namespace export new_design add_component get_current_design - namespace export set_def_units get_def_units shift_origin shift_rect - namespace export open close out write write_cells - namespace export set_layer_info - namespace ensemble create + dict set designs $current_design components $inst_name inst_name $inst_name + dict set designs $current_design components $inst_name cell_name $cell_name + dict set designs $current_design components $inst_name $status [list $x $y] + dict set designs $current_design components $inst_name orientation $orientation +} + +proc get_current_design { } { + variable designs + variable current_design + + return [dict get $designs $current_design] +} + +proc write_cells { cells } { + dict for {cell_name cell} $cells { + def open ${cell_name}.def + def write $cell + def close + } +} + +proc set_def_units { units } { + variable def_units + + set def_units $units +} + +proc get_def_units { } { + variable def_units + + return $def_units +} + +namespace export new_design add_component get_current_design +namespace export set_def_units get_def_units shift_origin shift_rect +namespace export open close out write write_cells +namespace export set_layer_info +namespace ensemble create } package provide lefdef 1.0.0 diff --git a/flow/util/cell-veneer/pkgIndex.tcl b/flow/util/cell-veneer/pkgIndex.tcl index 806a34f75f..b739cc635c 100644 --- a/flow/util/cell-veneer/pkgIndex.tcl +++ b/flow/util/cell-veneer/pkgIndex.tcl @@ -1,3 +1,2 @@ -package ifneeded lefdef 1.0.0 [list source [file join $dir lefdef.tcl]] +package ifneeded lefdef 1.0.0 [list source [file join $dir lefdef.tcl]] package ifneeded wrapper 1.0.0 [list source [file join $dir wrap_stdcells.tcl]] - diff --git a/flow/util/cell-veneer/wrap.tcl b/flow/util/cell-veneer/wrap.tcl index 3ca893b8fd..8fa52113ab 100755 --- a/flow/util/cell-veneer/wrap.tcl +++ b/flow/util/cell-veneer/wrap.tcl @@ -5,7 +5,7 @@ exec tclsh "$0" ${1+"$@"} package require wrapper package require lefdef -if {[set idx [lsearch -exact $argv {-cfg}]] > -1} { +if { [set idx [lsearch -exact $argv {-cfg}]] > -1 } { set cfg_file [lindex $argv [expr $idx + 1]] set argv [lreplace $argv $idx [expr $idx + 1]] @@ -15,7 +15,7 @@ if {[set idx [lsearch -exact $argv {-cfg}]] > -1} { wrapper critical 2 "no configuration data loaded" } -if {[lindex $argv 0] == "-macro"} { +if { [lindex $argv 0] == "-macro" } { set lef_files [lrange $argv 1 end] set cells {} foreach file_name $lef_files { diff --git a/flow/util/cell-veneer/wrap_stdcells.tcl b/flow/util/cell-veneer/wrap_stdcells.tcl index f6abb4a674..96b2612cfa 100644 --- a/flow/util/cell-veneer/wrap_stdcells.tcl +++ b/flow/util/cell-veneer/wrap_stdcells.tcl @@ -1,701 +1,683 @@ namespace eval wrapper { - variable wrapper_cfg - - proc set_message {level message} { - return "\[$level\] $message" - } +variable wrapper_cfg - proc debug {message} { - set state [info frame -1] - set str "" - if {[dict exists $state file]} { - set str "$str[dict get $state file]:" - } - if {[dict exists $state proc]} { - set str "$str[dict get $state proc]:" - } - if {[dict exists $state line]} { - set str "$str[dict get $state line]" - } - puts [set_message DEBUG "$str: $message"] - } +proc set_message { level message } { + return "\[$level\] $message" +} - proc information {id message} { - puts [set_message INFO [format "\[WRAP-%04d\] %s" $id $message]] +proc debug { message } { + set state [info frame -1] + set str "" + if { [dict exists $state file] } { + set str "$str[dict get $state file]:" } - - proc warning {id message} { - puts [set_message WARN [format "\[WRAP-%04d\] %s" $id $message]] + if { [dict exists $state proc] } { + set str "$str[dict get $state proc]:" } - - proc err {id message} { - puts [set_message ERROR [format "\[WRAP-%04d\] %s" $id $message]] + if { [dict exists $state line] } { + set str "$str[dict get $state line]" } + puts [set_message DEBUG "$str: $message"] +} - proc critical {id message} { - error [set_message CRIT [format "\[WRAP-%04d\] %s" $id $message]] - } +proc information { id message } { + puts [set_message INFO [format "\[WRAP-%04d\] %s" $id $message]] +} + +proc warning { id message } { + puts [set_message WARN [format "\[WRAP-%04d\] %s" $id $message]] +} + +proc err { id message } { + puts [set_message ERROR [format "\[WRAP-%04d\] %s" $id $message]] +} + +proc critical { id message } { + error [set_message CRIT [format "\[WRAP-%04d\] %s" $id $message]] +} + +proc find_cells_with_m2_pins { } { + set cells [lef get_cells] + set data {} + + dict for {cell_name cell} $cells { + dict for {pin_name pin} [dict get $cell pins] { + foreach port [dict get $pin ports] { + set offset [wrapper::get_port_offset $port] + set layer_name "M2" + if { [dict exists $port layers $layer_name] } { + foreach shape [dict get $port layers $layer_name shapes] { + set rect [absolute_rectangle [dict get $shape rect] $offset] + set x1 [lindex $rect 0] + set y1 [lindex $rect 1] + set x2 [lindex $rect 2] + set y2 [lindex $rect 3] - proc find_cells_with_m2_pins {} { - set cells [lef get_cells] - set data {} - - dict for {cell_name cell} $cells { - dict for {pin_name pin} [dict get $cell pins] { - foreach port [dict get $pin ports] { - set offset [wrapper::get_port_offset $port] - set layer_name "M2" - if {[dict exists $port layers $layer_name]} { - foreach shape [dict get $port layers $layer_name shapes] { - - set rect [absolute_rectangle [dict get $shape rect] $offset] - set x1 [lindex $rect 0] - set y1 [lindex $rect 1] - set x2 [lindex $rect 2] - set y2 [lindex $rect 3] - - if {[dict exists $data $cell_name pins $pin_name]} { - set pins [dict get $data $cell_name pins $pin_name] - } else { - set pins {} - } - if {round($y2 - $y1) > 64} { - error "cell $cell_name, pin: $pin_name, [expr $y2 - $y1] -> vertical M2 pin: $y2, $y1" - } - lappend pins [list track [expr round(($y2 + $y1) / 2 / 128)] from $x1 to $x2] - dict set data $cell_name pins $pin_name $pins + if { [dict exists $data $cell_name pins $pin_name] } { + set pins [dict get $data $cell_name pins $pin_name] + } else { + set pins {} + } + if { round($y2 - $y1) > 64 } { + error "cell $cell_name, pin: $pin_name, [expr $y2 - $y1] -> vertical M2 pin: $y2, $y1" } + lappend pins [list track [expr round(($y2 + $y1) / 2 / 128)] from $x1 to $x2] + dict set data $cell_name pins $pin_name $pins } } } + } - if {[dict exists $data $cell_name]} { - dict for {layer_name obstructions} [dict get $cell obstructions] { - if {$layer_name == "M2"} { - foreach obs $obstructions { - set rect [dict get $obs rect] - set x1 [lindex $rect 0] - set y1 [lindex $rect 1] - set x2 [lindex $rect 2] - set y2 [lindex $rect 3] - - if {round(($y2 - $y1)) > 64} { - error "cell $cell_name, blockage, [expr $y2 - $y1] -> vertical blockage: $y2, $y1" - } - if {[dict exists $data $cell_name blockages]} { - set blockages [dict get $data $cell_name blockages] - } else { - set blockages {} - } - - lappend blockages [list track [expr round(($y2 + $y1) / 2 / 128)] from $x1 to $x2] - dict set data $cell_name blockages $blockages + if { [dict exists $data $cell_name] } { + dict for {layer_name obstructions} [dict get $cell obstructions] { + if { $layer_name == "M2" } { + foreach obs $obstructions { + set rect [dict get $obs rect] + set x1 [lindex $rect 0] + set y1 [lindex $rect 1] + set x2 [lindex $rect 2] + set y2 [lindex $rect 3] + + if { round(($y2 - $y1)) > 64 } { + error "cell $cell_name, blockage, [expr $y2 - $y1] -> vertical blockage: $y2, $y1" + } + if { [dict exists $data $cell_name blockages] } { + set blockages [dict get $data $cell_name blockages] + } else { + set blockages {} } + + lappend blockages [list track [expr round(($y2 + $y1) / 2 / 128)] from $x1 to $x2] + dict set data $cell_name blockages $blockages } } } } - - return $data } - proc clear_left {physical_pin blockages} { - set track [dict get $physical_pin track] + return $data +} - foreach blockage $blockages { - if {[dict get $blockage track] == $track && [dict get $blockage to] < [dict get $physical_pin from]} { - return 0 - } +proc clear_left { physical_pin blockages } { + set track [dict get $physical_pin track] + + foreach blockage $blockages { + if { [dict get $blockage track] == $track && [dict get $blockage to] < [dict get $physical_pin from] } { + return 0 } - return 1 } + return 1 +} - proc clear_right {physical_pin blockages} { - set track [dict get $physical_pin track] +proc clear_right { physical_pin blockages } { + set track [dict get $physical_pin track] - foreach blockage $blockages { - if {[dict get $blockage track] == $track && [dict get $blockage from] > [dict get $physical_pin to]} { - return 0 - } + foreach blockage $blockages { + if { [dict get $blockage track] == $track && [dict get $blockage from] > [dict get $physical_pin to] } { + return 0 } - return 1 } + return 1 +} - proc create_def_wrapper {cell_name new_cell_name} { - variable tech - set orig_cell [lef get_cell $cell_name] - - set design $orig_cell - - dict set design name $new_cell_name - dict set design tool "cell-veneer" - dict set design units 2000 - dict set design use_sheet_obstructions 0 - if {[dict exists $tech use_sheet_obstructions]} { - dict set design use_sheet_obstructions [dict get $tech use_sheet_obstructions] - } - if {[dict exists $tech blockage_layers]} { - dict set design blockage_layers [dict get $tech blockage_layers] - } - dict set design die_area [dict get $orig_cell die_area] - - dict set design components u0 cell_name $cell_name - dict set design components u0 placed "0 0" - dict set design components u0 orientation "N" - - dict for {pin_name pin} [dict get $orig_cell pins] { - - dict set design pins $pin_name net_name $pin_name - if {[dict exists $pin use]} { - if {[dict get $pin use] == "POWER" || [dict get $pin use] == "GROUND"} { - dict set design special_nets $pin_name connections [list "PIN $pin_name" "* $pin_name"] - dict set design special_nets $pin_name use [dict get $pin use] - } else { - dict set design nets $pin_name connections [list "PIN $pin_name" "u0 $pin_name"] - dict set design nets $pin_name use [dict get $pin use] - } +proc create_def_wrapper { cell_name new_cell_name } { + variable tech + set orig_cell [lef get_cell $cell_name] + + set design $orig_cell + + dict set design name $new_cell_name + dict set design tool "cell-veneer" + dict set design units 2000 + dict set design use_sheet_obstructions 0 + if { [dict exists $tech use_sheet_obstructions] } { + dict set design use_sheet_obstructions [dict get $tech use_sheet_obstructions] + } + if { [dict exists $tech blockage_layers] } { + dict set design blockage_layers [dict get $tech blockage_layers] + } + dict set design die_area [dict get $orig_cell die_area] + + dict set design components u0 cell_name $cell_name + dict set design components u0 placed "0 0" + dict set design components u0 orientation "N" + + dict for {pin_name pin} [dict get $orig_cell pins] { + dict set design pins $pin_name net_name $pin_name + if { [dict exists $pin use] } { + if { [dict get $pin use] == "POWER" || [dict get $pin use] == "GROUND" } { + dict set design special_nets $pin_name connections [list "PIN $pin_name" "* $pin_name"] + dict set design special_nets $pin_name use [dict get $pin use] } else { dict set design nets $pin_name connections [list "PIN $pin_name" "u0 $pin_name"] + dict set design nets $pin_name use [dict get $pin use] } + } else { + dict set design nets $pin_name connections [list "PIN $pin_name" "u0 $pin_name"] } - - return $design } - - proc get_port_offset {port} { - if {[dict exists $port fixed]} { - return [dict get $port fixed] - } elseif {[dict exists $port placed]} { - return [dict get $port fixed] - } - return [list 0 0] + return $design +} + +proc get_port_offset { port } { + if { [dict exists $port fixed] } { + return [dict get $port fixed] + } elseif { [dict exists $port placed] } { + return [dict get $port fixed] } - proc move_m2_pins_to_edge {cell_name cell_data} { - variable wrapper_cfg - - set wrapper_cell [lef get_cell [dict get $wrapper_cfg padding_cell]] - set padding_cell_width [lindex [dict get $wrapper_cell die_area] 2] - set def_units [dict get $wrapper_cfg def_units] - set layer_name [dict get $wrapper_cfg remove_pins layer] - set layer_width [expr round([dict get $wrapper_cfg layer $layer_name width] * $def_units)] - set new_pin_layer_name [dict get $wrapper_cfg new_pins layer] - set new_pin_layer_width [expr round([dict get $wrapper_cfg layer $new_pin_layer_name width] * $def_units)] - set cell_width [lindex [dict get [lef get_cell $cell_name] die_area] 2] - set design [wrapper::create_def_wrapper $cell_name ${cell_name}_mod] - set lower_y [expr 2 * 128] - set upper_y [expr 8 * 128] - set via_overlap [expr round([dict get $wrapper_cfg via_overlap] * $def_units)] - - set right_padding 0 - set left_padding 0 - - # Determine which sides to route the M2 pins to and create a wire - dict for {pin_name pin} [dict get $cell_data pins] { - set wires {} - foreach physical_pin $pin { - if {[dict get $physical_pin to] >= [expr $cell_width / 2.0]} { - if {[dict exists $cell_data blockages]} { - if {[wrapper::clear_right $physical_pin [dict get $cell_data blockages]]} { - set direction right - } elseif {[wrapper::clear_left $physical_pin [dict get $cell_data blockages]]} { - set direction left - } else { - set direction blocked - } - } else { + return [list 0 0] +} + +proc move_m2_pins_to_edge { cell_name cell_data } { + variable wrapper_cfg + + set wrapper_cell [lef get_cell [dict get $wrapper_cfg padding_cell]] + set padding_cell_width [lindex [dict get $wrapper_cell die_area] 2] + set def_units [dict get $wrapper_cfg def_units] + set layer_name [dict get $wrapper_cfg remove_pins layer] + set layer_width [expr round([dict get $wrapper_cfg layer $layer_name width] * $def_units)] + set new_pin_layer_name [dict get $wrapper_cfg new_pins layer] + set new_pin_layer_width [expr round([dict get $wrapper_cfg layer $new_pin_layer_name width] * $def_units)] + set cell_width [lindex [dict get [lef get_cell $cell_name] die_area] 2] + set design [wrapper::create_def_wrapper $cell_name ${cell_name}_mod] + set lower_y [expr 2 * 128] + set upper_y [expr 8 * 128] + set via_overlap [expr round([dict get $wrapper_cfg via_overlap] * $def_units)] + + set right_padding 0 + set left_padding 0 + + # Determine which sides to route the M2 pins to and create a wire + dict for {pin_name pin} [dict get $cell_data pins] { + set wires {} + foreach physical_pin $pin { + if { [dict get $physical_pin to] >= [expr $cell_width / 2.0] } { + if { [dict exists $cell_data blockages] } { + if { [wrapper::clear_right $physical_pin [dict get $cell_data blockages]] } { set direction right + } elseif { [wrapper::clear_left $physical_pin [dict get $cell_data blockages]] } { + set direction left + } else { + set direction blocked } } else { - if {[dict exists $cell_data blockages]} { - if {[wrapper::clear_left $physical_pin [dict get $cell_data blockages]]} { - set direction left - } elseif {[wrapper::clear_right $physical_pin [dict get $cell_data blockages]]} { - set direction right - } else { - set direction blocked - } - } else { + set direction right + } + } else { + if { [dict exists $cell_data blockages] } { + if { [wrapper::clear_left $physical_pin [dict get $cell_data blockages]] } { set direction left + } elseif { [wrapper::clear_right $physical_pin [dict get $cell_data blockages]] } { + set direction right + } else { + set direction blocked } - } - - if {$direction == "blocked"} { - break - } - - set y [expr [dict get $physical_pin track] * 128] - if {$direction == "right"} { - set x1 [dict get $physical_pin to] - set x2 [expr $cell_width + ($padding_cell_width * ($right_padding + 1))] - set x3 [expr $cell_width + ($padding_cell_width * ($right_padding + 1)) + $via_overlap] - incr right_padding - } elseif {$direction == "left"} { - set x1 [dict get $physical_pin from] - set x2 [expr 0 - ($padding_cell_width * ($left_padding + 1))] - set x3 [expr 0 - ($padding_cell_width * ($left_padding + 1)) - $via_overlap] - incr left_padding - } - - # Route M2 out to the side of the block - lappend wires [list \ - layer $layer_name \ - points [list [list $x1 $y] [list $x3 $y] [dict get $wrapper_cfg via]] - ] - set new_wire [list \ - layer "M1" \ - points [list [list $x2 $lower_y] [list $x2 $upper_y]] \ - ] - if {[dict exists $wrapper_cfg new_pins mask]} { - dict set new_wire mask [dict get $wrapper_cfg new_pins mask] - } - lappend wires $new_wire - # Add the new M2 wire as an obstruction when writing the LEF of the cell - if {[dict exists $design obstructions $layer_name]} { - set obstructions [dict get $design obstructions $layer_name] } else { - set obstructions {} + set direction left } - lappend obstructions [list \ - rect [list \ - [expr min($x1, $x3)] [expr $y - round($layer_width / 2)] \ - [expr max($x1, $x3)] [expr $y + round($layer_width / 2)] \ - ] - ] - dict set design obstructions $layer_name $obstructions + } + if { $direction == "blocked" } { break } - if {$direction == "blocked"} { - break + set y [expr [dict get $physical_pin track] * 128] + if { $direction == "right" } { + set x1 [dict get $physical_pin to] + set x2 [expr $cell_width + ($padding_cell_width * ($right_padding + 1))] + set x3 [expr $cell_width + ($padding_cell_width * ($right_padding + 1)) + $via_overlap] + incr right_padding + } elseif { $direction == "left" } { + set x1 [dict get $physical_pin from] + set x2 [expr 0 - ($padding_cell_width * ($left_padding + 1))] + set x3 [expr 0 - ($padding_cell_width * ($left_padding + 1)) - $via_overlap] + incr left_padding } - set ports {} - foreach port [dict get $design pins $pin_name ports] { - if {[dict exists $port layers "M2"]} { - set offset [get_port_offset $port] - # Copy all M2 pins on instance to M2 obstructions - foreach shape [dict get $port layers "M2" shapes] { - set pin_rect [absolute_rectangle [dict get $shape rect] $offset] - - set m2_obstructions [dict get $design obstructions M2] - lappend m2_obstructions [list \ - rect $pin_rect \ - ] - dict set design obstructions M2 $m2_obstructions - } - # Replace the M2 port with an M1 port which is now at the side of the cells - set new_pin_rect [list [expr round($x2 - ($new_pin_layer_width / 2))] $lower_y [expr round($x2 + ($new_pin_layer_width / 2))] $upper_y] - if {[dict exists $port layers "M1" shapes]} { - set shapes [dict get $port layers "M1" shapes] - } else { - set shapes {} - } - set new_shape [list \ - rect [relative_rectangle $new_pin_rect $offset] \ - ] - if {[dict exists $wrapper_cfg new_pins mask]} { - dict set new_shape mask [dict get $wrapper_cfg new_pins mask] - } - lappend shapes $new_shape - dict set port layers M1 shapes $shapes - } - dict set port layers [dict remove [dict get $port layers] "M2"] - lappend ports $port + # Route M2 out to the side of the block + lappend wires [list \ + layer $layer_name \ + points [list [list $x1 $y] [list $x3 $y] [dict get $wrapper_cfg via]]] + set new_wire [list \ + layer "M1" \ + points [list [list $x2 $lower_y] [list $x2 $upper_y]]] + if { [dict exists $wrapper_cfg new_pins mask] } { + dict set new_wire mask [dict get $wrapper_cfg new_pins mask] + } + lappend wires $new_wire + # Add the new M2 wire as an obstruction when writing the LEF of the cell + if { [dict exists $design obstructions $layer_name] } { + set obstructions [dict get $design obstructions $layer_name] + } else { + set obstructions {} } - dict set design pins $pin_name ports $ports - dict set design nets $pin_name routes $wires + lappend obstructions [list \ + rect [list \ + [expr min($x1, $x3)] [expr $y - round($layer_width / 2)] \ + [expr max($x1, $x3)] [expr $y + round($layer_width / 2)]]] + dict set design obstructions $layer_name $obstructions + + break } - # Adjust the placement of the component if we have padding on the left - if {$left_padding > 0} { - dict set design components u0 placed [list [expr $padding_cell_width * ($left_padding + 1)] 0] + if { $direction == "blocked" } { + break } - # Add in the cell padding - set pad_idx 0 - if {$left_padding > 0} { - for {set i 0} {$i <= $left_padding} {incr i} { - set x [expr $padding_cell_width * ($i + 1) * -1] - set y 0 - dict set design components p$pad_idx inst_name p$pad_idx - dict set design components p$pad_idx cell_name [dict get $wrapper_cfg padding_cell] - dict set design components p$pad_idx placed [list $x $y] - dict set design components p$pad_idx orientation N - - # Add all obstructions of padding cell to obstructions of wrapper - dict for {layer_name obstructions} [dict get $wrapper_cell obstructions] { - if {[dict exists $design obstructions $layer_name]} { - set current_obstructions [dict get $design obstructions $layer_name] - } else { - set current_obstructions {} - } - foreach obs $obstructions { - dict set obs rect [def shift_rect [dict get $obs rect] $x $y] - lappend current_obstructions $obs - } - dict set design obstructions $layer_name $current_obstructions + set ports {} + foreach port [dict get $design pins $pin_name ports] { + if { [dict exists $port layers "M2"] } { + set offset [get_port_offset $port] + # Copy all M2 pins on instance to M2 obstructions + foreach shape [dict get $port layers "M2" shapes] { + set pin_rect [absolute_rectangle [dict get $shape rect] $offset] + + set m2_obstructions [dict get $design obstructions M2] + lappend m2_obstructions [list \ + rect $pin_rect] + dict set design obstructions M2 $m2_obstructions } - incr pad_idx + # Replace the M2 port with an M1 port which is now at the side of the cells + set new_pin_rect [list [expr round($x2 - ($new_pin_layer_width / 2))] $lower_y [expr round($x2 + ($new_pin_layer_width / 2))] $upper_y] + if { [dict exists $port layers "M1" shapes] } { + set shapes [dict get $port layers "M1" shapes] + } else { + set shapes {} + } + set new_shape [list \ + rect [relative_rectangle $new_pin_rect $offset]] + if { [dict exists $wrapper_cfg new_pins mask] } { + dict set new_shape mask [dict get $wrapper_cfg new_pins mask] + } + lappend shapes $new_shape + dict set port layers M1 shapes $shapes } - } else { - set left_padding -1 + dict set port layers [dict remove [dict get $port layers] "M2"] + lappend ports $port } - if {$right_padding > 0} { - for {set i 0} {$i <= $right_padding} {incr i} { - set x [expr $padding_cell_width * $i + $cell_width] - set y 0 - dict set design components p$pad_idx inst_name p$pad_idx - dict set design components p$pad_idx cell_name [dict get $wrapper_cfg padding_cell] - dict set design components p$pad_idx placed [list $x $y] - dict set design components p$pad_idx orientation N - - # Add all obstructions of padding cell to obstructions of wrapper - dict for {layer_name obstructions} [dict get $wrapper_cell obstructions] { - if {[dict exists $design obstructions $layer_name]} { - set current_obstructions [dict get $design obstructions $layer_name] - } else { - set current_obstructions {} - } - foreach obs $obstructions { - dict set obs rect [def shift_rect [dict get $obs rect] $x $y] - lappend current_obstructions $obs - } - dict set design obstructions $layer_name $current_obstructions + dict set design pins $pin_name ports $ports + dict set design nets $pin_name routes $wires + } + + # Adjust the placement of the component if we have padding on the left + if { $left_padding > 0 } { + dict set design components u0 placed [list [expr $padding_cell_width * ($left_padding + 1)] 0] + } + + # Add in the cell padding + set pad_idx 0 + if { $left_padding > 0 } { + for { set i 0 } { $i <= $left_padding } { incr i } { + set x [expr $padding_cell_width * ($i + 1) * -1] + set y 0 + dict set design components p$pad_idx inst_name p$pad_idx + dict set design components p$pad_idx cell_name [dict get $wrapper_cfg padding_cell] + dict set design components p$pad_idx placed [list $x $y] + dict set design components p$pad_idx orientation N + + # Add all obstructions of padding cell to obstructions of wrapper + dict for {layer_name obstructions} [dict get $wrapper_cell obstructions] { + if { [dict exists $design obstructions $layer_name] } { + set current_obstructions [dict get $design obstructions $layer_name] + } else { + set current_obstructions {} + } + foreach obs $obstructions { + dict set obs rect [def shift_rect [dict get $obs rect] $x $y] + lappend current_obstructions $obs } - incr pad_idx + dict set design obstructions $layer_name $current_obstructions } + incr pad_idx } + } else { + set left_padding -1 + } + if { $right_padding > 0 } { + for { set i 0 } { $i <= $right_padding } { incr i } { + set x [expr $padding_cell_width * $i + $cell_width] + set y 0 + dict set design components p$pad_idx inst_name p$pad_idx + dict set design components p$pad_idx cell_name [dict get $wrapper_cfg padding_cell] + dict set design components p$pad_idx placed [list $x $y] + dict set design components p$pad_idx orientation N + + # Add all obstructions of padding cell to obstructions of wrapper + dict for {layer_name obstructions} [dict get $wrapper_cell obstructions] { + if { [dict exists $design obstructions $layer_name] } { + set current_obstructions [dict get $design obstructions $layer_name] + } else { + set current_obstructions {} + } + foreach obs $obstructions { + dict set obs rect [def shift_rect [dict get $obs rect] $x $y] + lappend current_obstructions $obs + } + dict set design obstructions $layer_name $current_obstructions + } + incr pad_idx + } + } - # Adjust origin so that 0,0 is the lowr left corner of the cell - set adjustment [expr $padding_cell_width * ($left_padding + 1)] - set design [def shift_origin $design $adjustment 0] - - dict set design die_area [list \ - 0 \ - 0 \ - [expr [lindex [dict get $design die_area] 2] + (($pad_idx - ($left_padding + 1)) * $padding_cell_width)] \ - [lindex [dict get $design die_area] 3] \ - ] - - # Extend VDD, VSS, VPW, VNW pins to be the width of the wrapper - # VDD overlaps by 0.009 on each side - # VSS overlaps by 0.009 on each side - # VNW overlaps the edges of the cell by 0.1 on both sides - set extend_ports { + # Adjust origin so that 0,0 is the lowr left corner of the cell + set adjustment [expr $padding_cell_width * ($left_padding + 1)] + set design [def shift_origin $design $adjustment 0] + + dict set design die_area [list \ + 0 \ + 0 \ + [expr [lindex [dict get $design die_area] 2] + (($pad_idx - ($left_padding + 1)) * $padding_cell_width)] \ + [lindex [dict get $design die_area] 3]] + + # Extend VDD, VSS, VPW, VNW pins to be the width of the wrapper + # VDD overlaps by 0.009 on each side + # VSS overlaps by 0.009 on each side + # VNW overlaps the edges of the cell by 0.1 on both sides + set extend_ports { VDD {layer M1 overlap 0.009} VSS {layer M1 overlap 0.009} VNW {layer NW overlap 0.1} VPW {layer SXCUT overlap 0} } - dict for {pin_name info} $extend_ports { - set layer [dict get $info layer] - set overlap [dict get $info overlap] - - set ports {} - foreach port [dict get $design pins $pin_name ports] { - if {[dict exists $port layers $layer]} { - set shapes {} - set offset [get_port_offset $port] - - foreach shape [dict get $port layers $layer shapes] { - set rect [absolute_rectangle [dict get $shape rect] $offset] - dict set shape rect [relative_rectangle \ - [list \ - [expr [lindex [dict get $design die_area] 0] - [expr round($overlap * $def_units)]] \ - [lindex $rect 1] \ - [expr [lindex [dict get $design die_area] 2] + [expr round($overlap * $def_units)]] \ - [lindex $rect 3] \ - ] \ - $offset \ - ] - lappend shapes $shape - } - dict set port layers $layer shapes $shapes + dict for {pin_name info} $extend_ports { + set layer [dict get $info layer] + set overlap [dict get $info overlap] + + set ports {} + foreach port [dict get $design pins $pin_name ports] { + if { [dict exists $port layers $layer] } { + set shapes {} + set offset [get_port_offset $port] + + foreach shape [dict get $port layers $layer shapes] { + set rect [absolute_rectangle [dict get $shape rect] $offset] + dict set shape rect [relative_rectangle \ + [list \ + [expr [lindex [dict get $design die_area] 0] - [expr round($overlap * $def_units)]] \ + [lindex $rect 1] \ + [expr [lindex [dict get $design die_area] 2] + [expr round($overlap * $def_units)]] \ + [lindex $rect 3]] \ + $offset] + lappend shapes $shape } - lappend ports $port + dict set port layers $layer shapes $shapes } - dict set design pins $pin_name ports $ports + lappend ports $port } - - return $design + dict set design pins $pin_name ports $ports } - proc build_wrappers {data} { - variable wrapper_cfg - - set designs {} + return $design +} - dict for {cell_name cell_data} $data { - set data [move_m2_pins_to_edge $cell_name $cell_data $wrapper_cfg] - dict set designs [dict get $data name] $data - } +proc build_wrappers { data } { + variable wrapper_cfg - return $designs - } + set designs {} - proc get_pin_rect {port layer} { - if {[dict exists $port fixed]} { - set offset [dict get $port fixed] - } elseif {[dict exists $port placed]} { - set offset [dict get $port placed] - } else { - set offset [list 0 0] - } - - return [absolute_rectangle [dict get [lindex [dict get $port layers $layer shapes] 0] rect] $offset] + dict for {cell_name cell_data} $data { + set data [move_m2_pins_to_edge $cell_name $cell_data $wrapper_cfg] + dict set designs [dict get $data name] $data } - - proc wrap_macro {cell_name} { - variable tech - set wrapper [wrapper::create_def_wrapper $cell_name ${cell_name}_mod] - debug "$tech" - debug "[dict get $wrapper use_sheet_obstructions]" - - set cell [lef get_cell $cell_name] - # debug "$cell_name" - - # Order the signal pins based on the y location of the pin - set pin_info {} - set net_info {} - set grid_pins {} - dict for {pin_name pin} [dict get $cell pins] { - if {[dict get $pin use] != "SIGNAL"} {continue} - - # CHEAT: Assume that there is only one port for each pin and one rectangle per layer - set port [lindex [dict get $pin ports] 0] - if {[dict exists $port layers C4]} { - set pin_rect [get_pin_rect $port C4] - dict set net_info $pin_name pin_layer "C4" - } elseif {[dict exists $port layers M3]} { - set pin_rect [get_pin_rect $port M3] - dict set net_info $pin_name pin_layer "M3" - } + return $designs +} - set macro_pin_y [expr ([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2] - set grid_y [expr round((floor(([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2 / [dict get $tech pitch horizontal_track]) - 1))] +proc get_pin_rect { port layer } { + if { [dict exists $port fixed] } { + set offset [dict get $port fixed] + } elseif { [dict exists $port placed] } { + set offset [dict get $port placed] + } else { + set offset [list 0 0] + } - # Need to check that the grid point we're trying to use is going to be accessible. - # If it is not, then try the point 2 grid points higher - if {[dict exists $grid_pins $grid_y]} { - if {[dict exists [expr $grid_y + 2]]} { - puts "Cell $cell_name" - puts "Problem assigning pin grid - requested and upper grid points for $pin_name at $grid_y already allocated to [dict get $grid_pins $grid_y] and [dict get $grid_pins [expr $grid_y + 2]]" - exit -1 - } - set grid_y [expr $grid_y + 2] - } - dict set grid_pins $grid_y $pin_name + return [absolute_rectangle [dict get [lindex [dict get $port layers $layer shapes] 0] rect] $offset] +} - dict set net_info $pin_name grid_y $grid_y - dict set net_info $pin_name macro_pin_y $macro_pin_y +proc wrap_macro { cell_name } { + variable tech + set wrapper [wrapper::create_def_wrapper $cell_name ${cell_name}_mod] + debug "$tech" + debug "[dict get $wrapper use_sheet_obstructions]" + + set cell [lef get_cell $cell_name] + # debug "$cell_name" + + # Order the signal pins based on the y location of the pin + set pin_info {} + set net_info {} + set grid_pins {} + + dict for {pin_name pin} [dict get $cell pins] { + if { [dict get $pin use] != "SIGNAL" } { continue } + + # CHEAT: Assume that there is only one port for each pin and one rectangle per layer + set port [lindex [dict get $pin ports] 0] + if { [dict exists $port layers C4] } { + set pin_rect [get_pin_rect $port C4] + dict set net_info $pin_name pin_layer "C4" + } elseif { [dict exists $port layers M3] } { + set pin_rect [get_pin_rect $port M3] + dict set net_info $pin_name pin_layer "M3" } - set order [lsort -integer [dict keys $grid_pins]] - set prev_pos [lindex $order 0] + set macro_pin_y [expr ([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2] + set grid_y [expr round((floor(([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2 / [dict get $tech pitch horizontal_track]) - 1))] - # We will have a jog in the track, which needs to be on a vertical grid 3 units from the edge of the macro - # If there is another pin close by, the we will need to have the jog 3 grids further in - dict set net_info [dict get $grid_pins $prev_pos] h_offset 3 - foreach pin_pos [lrange $order 1 end] { - if {$pin_pos - $prev_pos > 3} { - dict set net_info [dict get $grid_pins $pin_pos] h_offset 3 - } else { - dict set net_info [dict get $grid_pins $pin_pos] h_offset [expr [dict get $net_info [dict get $grid_pins $prev_pos] h_offset] + 3] + # Need to check that the grid point we're trying to use is going to be accessible. + # If it is not, then try the point 2 grid points higher + if { [dict exists $grid_pins $grid_y] } { + if { [dict exists [expr $grid_y + 2]] } { + puts "Cell $cell_name" + puts "Problem assigning pin grid - requested and upper grid points for $pin_name at $grid_y already allocated to [dict get $grid_pins $grid_y] and [dict get $grid_pins [expr $grid_y + 2]]" + exit -1 } - set prev_pos $pin_pos + set grid_y [expr $grid_y + 2] } + dict set grid_pins $grid_y $pin_name - # Work out where to place the instance based on the size of amount of jogging space needed - set wrapper_depth 0 - dict for {net_name net} [dict get $net_info] { - if {$wrapper_depth < [dict get $net h_offset]} { - set wrapper_depth [dict get $net h_offset] - } + dict set net_info $pin_name grid_y $grid_y + dict set net_info $pin_name macro_pin_y $macro_pin_y + } + + set order [lsort -integer [dict keys $grid_pins]] + set prev_pos [lindex $order 0] + + # We will have a jog in the track, which needs to be on a vertical grid 3 units from the edge of the macro + # If there is another pin close by, the we will need to have the jog 3 grids further in + dict set net_info [dict get $grid_pins $prev_pos] h_offset 3 + foreach pin_pos [lrange $order 1 end] { + if { $pin_pos - $prev_pos > 3 } { + dict set net_info [dict get $grid_pins $pin_pos] h_offset 3 + } else { + dict set net_info [dict get $grid_pins $pin_pos] h_offset [expr [dict get $net_info [dict get $grid_pins $prev_pos] h_offset] + 3] } - set wrapper_depth [expr $wrapper_depth + 3] - set macro_x [expr $wrapper_depth * [dict get $tech pitch vertical_track]] - set width [expr round((floor([lef get_width $cell] / [dict get $tech pitch vertical_track]) + 1) * [dict get $tech pitch vertical_track] )] - set height [expr round((floor([lef get_height $cell] / [dict get $tech pitch horizontal_track]) + 1) * [dict get $tech pitch horizontal_track])] - - # Now we know where the macro is placed, we know the size of the wrapper - dict set wrapper die_area [list [expr round(-1 * $macro_x)] 0 [expr $width] $height] - # debug "Set die area [dict get $wrapper die_area]" - # Now we know the maximum extent of the space needed for the job we can add in the pins the appropriate number of grids to the left of the RAM - - # Shift the wrapper so the lower left corner is at (0, 0) - set wrapper [def shift_origin $wrapper $macro_x 0] - # debug "Shifted die area [dict get $wrapper die_area]" - - # Add obstructions - foreach obs_layer {M3 J3 C4} { - set obstructions {} - if {[dict exists $wrapper obstructions $obs_layer]} { - set obstructions [dict get $wrapper obstructions $obs_layer] - } - # debug "[lindex [dict get $wrapper obstructions $obs_layer] 0]" - lappend obstructions [list rect [list 0 0 $macro_x $height]] - # debug "[lindex $obstructions 0]" - dict set wrapper obstructions $obs_layer $obstructions - # debug "Added wrapper obstruction [list 0 0 [expr $width + $macro_x] $height]" + set prev_pos $pin_pos + } + + # Work out where to place the instance based on the size of amount of jogging space needed + set wrapper_depth 0 + dict for {net_name net} [dict get $net_info] { + if { $wrapper_depth < [dict get $net h_offset] } { + set wrapper_depth [dict get $net h_offset] } - - - # Add wrapper pins and nets - dict for {net_name net} [dict get $net_info] { - set grid_y [dict get $net grid_y] - set y_position [expr $grid_y * [dict get $tech pitch horizontal_track]] - - set new_port [lindex [dict get $wrapper pins $net_name ports] 0] - dict set new_port layers {} - dict set new_port fixed [list 0 $y_position] - dict set new_port layers "C4" shapes [list \ - [list rect [list 0 [expr 0 - [dict get $tech layer C4 width] / 2] [dict get $tech layer C4 depth] [expr 0 + [dict get $tech layer C4 width] / 2]]] \ - ] - # debug "Replacing pin $net_name with $new_port" - dict set wrapper pins $net_name ports [list $new_port] - - set segments {} - - # First segment from RAM to jog location, to the y grid of the pin - set target_grid_point [expr ($wrapper_depth - [dict get $net h_offset]) * [dict get $tech pitch vertical_track]] - set width [dict get $tech layer [dict get $net pin_layer] width] + } + set wrapper_depth [expr $wrapper_depth + 3] + set macro_x [expr $wrapper_depth * [dict get $tech pitch vertical_track]] + set width [expr round((floor([lef get_width $cell] / [dict get $tech pitch vertical_track]) + 1) * [dict get $tech pitch vertical_track] )] + set height [expr round((floor([lef get_height $cell] / [dict get $tech pitch horizontal_track]) + 1) * [dict get $tech pitch horizontal_track])] + + # Now we know where the macro is placed, we know the size of the wrapper + dict set wrapper die_area [list [expr round(-1 * $macro_x)] 0 [expr $width] $height] + # debug "Set die area [dict get $wrapper die_area]" + # Now we know the maximum extent of the space needed for the job we can add in the pins the appropriate number of grids to the left of the RAM + + # Shift the wrapper so the lower left corner is at (0, 0) + set wrapper [def shift_origin $wrapper $macro_x 0] + # debug "Shifted die area [dict get $wrapper die_area]" + + # Add obstructions + foreach obs_layer {M3 J3 C4} { + set obstructions {} + if { [dict exists $wrapper obstructions $obs_layer] } { + set obstructions [dict get $wrapper obstructions $obs_layer] + } + # debug "[lindex [dict get $wrapper obstructions $obs_layer] 0]" + lappend obstructions [list rect [list 0 0 $macro_x $height]] + # debug "[lindex $obstructions 0]" + dict set wrapper obstructions $obs_layer $obstructions + # debug "Added wrapper obstruction [list 0 0 [expr $width + $macro_x] $height]" + } + + + # Add wrapper pins and nets + dict for {net_name net} [dict get $net_info] { + set grid_y [dict get $net grid_y] + set y_position [expr $grid_y * [dict get $tech pitch horizontal_track]] + + set new_port [lindex [dict get $wrapper pins $net_name ports] 0] + dict set new_port layers {} + dict set new_port fixed [list 0 $y_position] + dict set new_port layers "C4" shapes [list \ + [list rect [list 0 [expr 0 - [dict get $tech layer C4 width] / 2] [dict get $tech layer C4 depth] [expr 0 + [dict get $tech layer C4 width] / 2]]]] + # debug "Replacing pin $net_name with $new_port" + dict set wrapper pins $net_name ports [list $new_port] + + set segments {} + + # First segment from RAM to jog location, to the y grid of the pin + set target_grid_point [expr ($wrapper_depth - [dict get $net h_offset]) * [dict get $tech pitch vertical_track]] + set width [dict get $tech layer [dict get $net pin_layer] width] + lappend segments [list \ + layer [dict get $net pin_layer] \ + points [list \ + "$macro_x [dict get $net macro_pin_y]" \ + "$target_grid_point [dict get $net macro_pin_y]" \ + "$target_grid_point $y_position"]] + if { [dict get $net pin_layer] != "C4" } { lappend segments [list \ layer [dict get $net pin_layer] \ - points [list \ - "$macro_x [dict get $net macro_pin_y]" \ - "$target_grid_point [dict get $net macro_pin_y]" \ - "$target_grid_point $y_position" \ - ] - ] - if {[dict get $net pin_layer] != "C4"} { - lappend segments [list \ - layer [dict get $net pin_layer] \ - points [list \ - "$target_grid_point $y_position" \ - [dict get $tech via] \ - ] \ - ] - } - lappend segments [list \ - layer C4 \ points [list \ "$target_grid_point $y_position" \ - "0 $y_position" \ - ] \ - ] - - dict set wrapper nets $net_name routes $segments + [dict get $tech via]]] } + lappend segments [list \ + layer C4 \ + points [list \ + "$target_grid_point $y_position" \ + "0 $y_position"]] - return $wrapper + dict set wrapper nets $net_name routes $segments } - proc test_harness {wrappers} { - variable wrapper_cfg - - set site_height [expr [dict get $wrapper_cfg site height] * [dict get $wrapper_cfg def_units]] - set site_width [expr [dict get $wrapper_cfg site width] * [dict get $wrapper_cfg def_units]] - set idx 0 - set num_cells [dict size $wrappers] - set num_grids [expr round(sqrt($num_cells)) + 1] - set max_cell_width 0 - dict for {cell_name cell} $wrappers { - set max_cell_width [expr max($max_cell_width,[lindex [dict get $cell die_area] 2])] - } - set grid_x_size [expr $max_cell_width + (2 * $site_width)] - set grid_y_size [expr 4 * $site_height] + return $wrapper +} - def new_design "test_harness" [dict get $wrapper_cfg def_units] [list 0 0 [expr round($grid_x_size * $num_grids)] [expr round($grid_y_size * $num_grids)]] +proc test_harness { wrappers } { + variable wrapper_cfg - foreach cell [dict keys $wrappers] { - set x [expr round(($idx % $num_grids) * $grid_x_size)] - set y [expr round(round($idx / $num_grids) * $grid_y_size)] + set site_height [expr [dict get $wrapper_cfg site height] * [dict get $wrapper_cfg def_units]] + set site_width [expr [dict get $wrapper_cfg site width] * [dict get $wrapper_cfg def_units]] + set idx 0 + set num_cells [dict size $wrappers] + set num_grids [expr round(sqrt($num_cells)) + 1] + set max_cell_width 0 + dict for {cell_name cell} $wrappers { + set max_cell_width [expr max($max_cell_width,[lindex [dict get $cell die_area] 2])] + } + set grid_x_size [expr $max_cell_width + (2 * $site_width)] + set grid_y_size [expr 4 * $site_height] - set orig_cell [regsub {_mod} $cell {}] - def add_component "w_$idx" $cell $x $y N placed - def add_component "o_$idx" $orig_cell $x [expr round($y + (2 * $site_height))] N placed + def new_design "test_harness" [dict get $wrapper_cfg def_units] [list 0 0 [expr round($grid_x_size * $num_grids)] [expr round($grid_y_size * $num_grids)]] - incr idx - } + foreach cell [dict keys $wrappers] { + set x [expr round(($idx % $num_grids) * $grid_x_size)] + set y [expr round(round($idx / $num_grids) * $grid_y_size)] - def open test_harness.def - def write [set design [def get_current_design]] - def close + set orig_cell [regsub {_mod} $cell {}] + def add_component "w_$idx" $cell $x $y N placed + def add_component "o_$idx" $orig_cell $x [expr round($y + (2 * $site_height))] N placed - return $design + incr idx } - proc set_stdcell_config {config} { - variable wrapper_cfg - set wrapper_cfg $config - } + def open test_harness.def + def write [set design [def get_current_design]] + def close - proc run {} { - set file_name /projects/ssg/pj10000064_diphda/users/colhol01/openroad/library/arm/cp/14lpp/sc10p5mcpp84_base_lvt_c14/r2p1/lef/sc10p5mcpp84_14lpp_base_lvt_c14.lef + return $design +} - lef read_macros $file_name - set data [wrapper find_cells_with_m2_pins] +proc set_stdcell_config { config } { + variable wrapper_cfg + set wrapper_cfg $config +} - set wrappers [wrapper build_wrappers $data] +proc run { } { + set file_name /projects/ssg/pj10000064_diphda/users/colhol01/openroad/library/arm/cp/14lpp/sc10p5mcpp84_base_lvt_c14/r2p1/lef/sc10p5mcpp84_14lpp_base_lvt_c14.lef - lef write_cells sc10p5mcpp84_14lpp_base_lvt_c14.mod.lef $wrappers - def write_cells $wrappers - } + lef read_macros $file_name + set data [wrapper find_cells_with_m2_pins] - proc convert_tech_to_def_units {tech} { - set def_units [dict get $tech units] - dict for {layer_name layer} [dict get $tech layer] { - foreach property {depth width non_preferred_width} { - if {[dict exists $layer $property]} { - dict set tech layer $layer_name $property [expr round([dict get $layer $property] * $def_units)] - } + set wrappers [wrapper build_wrappers $data] + + lef write_cells sc10p5mcpp84_14lpp_base_lvt_c14.mod.lef $wrappers + def write_cells $wrappers +} + +proc convert_tech_to_def_units { tech } { + set def_units [dict get $tech units] + dict for {layer_name layer} [dict get $tech layer] { + foreach property {depth width non_preferred_width} { + if { [dict exists $layer $property] } { + dict set tech layer $layer_name $property [expr round([dict get $layer $property] * $def_units)] } } - - foreach layer_name [dict keys [dict get $tech layer]] { - foreach property {direction width non_preferred_width} { - if {[dict exists $tech layer $layer_name $property]} { - def set_layer_info $layer_name $property [dict get $tech layer $layer_name $property] - } + } + + foreach layer_name [dict keys [dict get $tech layer]] { + foreach property {direction width non_preferred_width} { + if { [dict exists $tech layer $layer_name $property] } { + def set_layer_info $layer_name $property [dict get $tech layer $layer_name $property] } } + } - dict set tech pitch vertical_track [expr round([dict get $tech pitch vertical_track] * $def_units)] - dict set tech pitch horizontal_track [expr round([dict get $tech pitch horizontal_track] * $def_units)] + dict set tech pitch vertical_track [expr round([dict get $tech pitch vertical_track] * $def_units)] + dict set tech pitch horizontal_track [expr round([dict get $tech pitch horizontal_track] * $def_units)] - return $tech - } + return $tech +} - proc set_macro_config {lef_tech} { - variable tech - - set tech [convert_tech_to_def_units $lef_tech] - } - - proc macro {lef_file} { - lef read_macros $lef_file - set cells {} - - foreach cell_name [dict keys [lef get_cells]] { +proc set_macro_config { lef_tech } { + variable tech + + set tech [convert_tech_to_def_units $lef_tech] +} + +proc macro { lef_file } { + lef read_macros $lef_file + set cells {} + + foreach cell_name [dict keys [lef get_cells]] { # debug "$cell_name" - set designs [list ${cell_name}_mod [wrap_macro $cell_name]] - lef write_macros ${cell_name}_mod.lef $designs - def write_cells $designs - lappend cells $cell_name - } - - return $cells + set designs [list ${cell_name}_mod [wrap_macro $cell_name]] + lef write_macros ${cell_name}_mod.lef $designs + def write_cells $designs + lappend cells $cell_name } - namespace export find_cells_with_m2_pins macro set_stdcell_config set_macro_config - namespace export information warning err critical - namespace export build_wrappers - namespace export test_harness - namespace ensemble create + return $cells +} + +namespace export find_cells_with_m2_pins macro set_stdcell_config set_macro_config +namespace export information warning err critical +namespace export build_wrappers +namespace export test_harness +namespace ensemble create } package provide wrapper 1.0.0 diff --git a/flow/util/write_net_rc.tcl b/flow/util/write_net_rc.tcl index 9e5dd99b58..68aa931832 100644 --- a/flow/util/write_net_rc.tcl +++ b/flow/util/write_net_rc.tcl @@ -56,20 +56,22 @@ proc write_rc_csv { filename } { } } } - puts $stream "" + puts $stream "" set use_drt_data [env_var_exists_and_non_empty CORRELATE_DRT_WIRELENGTH] foreach net [get_nets *] { set db_net [sta::sta_to_db_net $net] set type [$db_net getSigType] - if {([string equal $type "CLOCK"] || [string equal $type "SIGNAL"]) && - (!$use_drt_data || [$db_net getWire] ne "NULL")} { + if { + ([string equal $type "CLOCK"] || [string equal $type "SIGNAL"]) && + (!$use_drt_data || [$db_net getWire] ne "NULL") + } { set net_name [get_full_name $net] lassign $rc_var1($net_name) wire_res1 wire_cap1 lassign $rc_var2($net_name) wire_res2 wire_cap2 lassign $rc_var3($net_name) wire_res3 wire_cap3 - puts -nonewline $stream "[get_full_name $net],[expr {[string equal $type "CLOCK"] ? "clock" : "signal"}]," + puts -nonewline $stream "[get_full_name $net],[expr { [string equal $type "CLOCK"] ? "clock" : "signal" }]," puts -nonewline $stream "[format %.3e $wire_res1],[format %.3e $wire_cap1],[format %.3e $wire_res2],[format %.3e $wire_cap2],[format %.3e $wire_res3],[format %.3e $wire_cap3]" set db_net [sta::sta_to_db_net $net] @@ -79,13 +81,13 @@ proc write_rc_csv { filename } { set layer_lengths [grt::route_layer_lengths $db_net] } - for {set layer 0} {$layer < [$tech getLayerCount]} {incr layer} { + for { set layer 0 } { $layer < [$tech getLayerCount] } { incr layer } { set length [lindex $layer_lengths $layer] if $is_routing($layer) { puts -nonewline $stream ",[ord::dbu_to_microns $length]" } else { puts -nonewline $stream ",$length" - } + } } puts $stream "" @@ -197,7 +199,7 @@ proc compare_wire_rc1 { net var_name ref_var_name } { } else { set cap_delta 0.0 } - + set total_cap [expr $pin_cap + $wire_cap] set total_cap_ref [expr $pin_cap + $wire_cap_ref] if { $total_cap_ref != 0.0 } { @@ -205,7 +207,7 @@ proc compare_wire_rc1 { net var_name ref_var_name } { } else { set total_delta 0.0 } - + set fanout [llength [get_pins -of $net -filter "direction == input"]] puts -nonewline "[format %-20s $net_name] [format %5d $fanout] [format %8s [sta::format_capacitance $wire_cap 3]] [format %8s [sta::format_capacitance $wire_cap_ref 3]] [format %4.0f $cap_delta]% [format %4.0f $total_delta]%" diff --git a/tclint.toml b/tclint.toml new file mode 100644 index 0000000000..314f9c3e0b --- /dev/null +++ b/tclint.toml @@ -0,0 +1,23 @@ +# hardcoded list of paths to exclude while we incrementally lint codebase +# See issue #3268 for tracking +exclude = [ + "flow/results", + "flow/logs", + "flow/designs", + "flow/platforms", + "flow/util", + "flow/scripts/*.tcl", + "tools/OpenROAD", + "tools/yosys", +] + +ignore = [ + "unbraced-expr", +] + +[style] +indent = 2 +line-length = 100 +allow-aligned-sets = true +indent-namespace-eval = false +spaces-in-braces = true \ No newline at end of file From 380ddb0d7b30bedaecda4a259c8af6ec05713896 Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Sun, 29 Jun 2025 12:46:28 +0000 Subject: [PATCH 117/198] fix typo Signed-off-by: Jack Luar --- flow/scripts/util.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl index 4e6bca9d99..2c0695ef3f 100644 --- a/flow/scripts/util.tcl +++ b/flow/scripts/util.tcl @@ -1,6 +1,6 @@ proc log_cmd { cmd args } { # log the command, escape arguments with spaces - set log_cmd "$cmd[join [lmap arg $args { format " %s" [expr { [string mtch {* *} $arg] ? "\"$arg\"" : "$arg" }] }] ""]" + set log_cmd "$cmd[join [lmap arg $args { format " %s" [expr { [string match {* *} $arg] ? "\"$arg\"" : "$arg" }] }] ""]" puts $log_cmd set start [clock seconds] set result [uplevel 1 [list $cmd {*}$args]] From 9c9ce06a67ee89e7cc86cca9b9d8c81695e010e0 Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Mon, 30 Jun 2025 18:04:05 +0000 Subject: [PATCH 118/198] flow/util: fix non-line length issues Signed-off-by: Jack Luar --- flow/util/cell-veneer/lefdef.tcl | 49 ++++++++++++++----------- flow/util/cell-veneer/pkgIndex.tcl | 1 + flow/util/cell-veneer/wrap_stdcells.tcl | 4 +- flow/util/write_net_rc.tcl | 6 +-- tclint.toml | 2 +- 5 files changed, 34 insertions(+), 28 deletions(-) diff --git a/flow/util/cell-veneer/lefdef.tcl b/flow/util/cell-veneer/lefdef.tcl index 76e02aa17e..0d6d672c50 100644 --- a/flow/util/cell-veneer/lefdef.tcl +++ b/flow/util/cell-veneer/lefdef.tcl @@ -13,6 +13,7 @@ proc relative_rectangle { rect offset } { [expr [lindex $rect 3] - [lindex $offset 1]]] } +# tclint-disable-next-line command-args if [package vcompare 8.6 $tcl_version] { proc lmap {_var list body} { upvar 1 $_var var @@ -26,11 +27,13 @@ namespace eval lef { variable lefOut stdout variable def_units 2000 +# tclint-disable-next-line redefined-builtin proc open { file_name } { variable lefOut set lefOut [::open $file_name w] } +# tclint-disable-next-line redefined-builtin proc close { } { variable lefOut if { $lefOut != "stdout" } { @@ -288,13 +291,13 @@ proc write_footer { } { # - shape # - ports: a list of lists of shapes that make up a physical connection # - layer -# - rect +# - rect # - mask? # - obstructions # - layer: a dictionaries with layer_name as the key -# - rect +# - rect # - mask? -# +# proc write { design } { set def_units [dict get $design units] @@ -449,11 +452,13 @@ variable def_units variable defOut stdout variable designs {} +# tclint-disable-next-line redefined-builtin proc open { file_name } { variable defOut set defOut [::open $file_name w] } +# tclint-disable-next-line redefined-builtin proc close { } { variable defOut if { $defOut != "stdout" } { @@ -499,12 +504,12 @@ proc out { args } { # - shapes : list of rectangles (or polygons) # - (rect|polygon) # - physical_viarules: dict with the name of the viarule as the key -# - rule -# - cutsize -# - layers -# - cutspacing -# - enclosure -# - rowcol +# - rule +# - cutsize +# - layers +# - cutspacing +# - enclosure +# - rowcol # - components: dict with the instance name of the component as the key # - inst_name # - cell_name @@ -512,19 +517,19 @@ proc out { args } { # - orientation # - nets: dict with the name of the net as the key # - use: SIGNAL | POWER | GROUND -# - connections: list of instance pin pairs -# - routes: list of dictionaries -# - layer -# - points: list of points, where a point can be an XY location or the name of a VIA +# - connections: list of instance pin pairs +# - routes: list of dictionaries +# - layer +# - points: list of points, where a point can be an XY location or the name of a VIA # - special_nets: dict with the name of the net as the key -# - use: SIGNAL | POWER | GROUND -# - connections: list of instance pin pairs -# - routes: list of dictioaries -# - layer -# - width -# - shape +# - use: SIGNAL | POWER | GROUND +# - connections: list of instance pin pairs +# - routes: list of dictioaries +# - layer +# - width +# - shape # - points: list of points, where a point can be an XY location or the name of a VIA -# +# proc shift_point { point x y } { return [list [expr [lindex $point 0] + $x] [expr [lindex $point 1] + $y]] @@ -727,8 +732,8 @@ proc write { design } { if { [dict exists $design rows] } { foreach idx [lsort -integer [dict keys $design rows]] { - out -nonewline "ROW ROW_$idx [dict keys $design rows $idx site] [dict keys $design rows $idx start] [dict keys $design rows $idx height] [dict keys $design rows $idx orientation]" - out " DO [dict keys $design rows $idx num_sites] BY 1 STEP [dict keys $design rows $idx site_width] 0 ;" + out -nonewline "ROW ROW_$idx [dict get $design rows $idx site] [dict get $design rows $idx start] [dict get $design rows $idx height] [dict get $design rows $idx orientation]" + out " DO [dict get $design rows $idx num_sites] BY 1 STEP [dict get $design rows $idx site_width] 0 ;" } } diff --git a/flow/util/cell-veneer/pkgIndex.tcl b/flow/util/cell-veneer/pkgIndex.tcl index b739cc635c..45719f8484 100644 --- a/flow/util/cell-veneer/pkgIndex.tcl +++ b/flow/util/cell-veneer/pkgIndex.tcl @@ -1,2 +1,3 @@ +# tclint-disable command-args package ifneeded lefdef 1.0.0 [list source [file join $dir lefdef.tcl]] package ifneeded wrapper 1.0.0 [list source [file join $dir wrap_stdcells.tcl]] diff --git a/flow/util/cell-veneer/wrap_stdcells.tcl b/flow/util/cell-veneer/wrap_stdcells.tcl index 96b2612cfa..820df77436 100644 --- a/flow/util/cell-veneer/wrap_stdcells.tcl +++ b/flow/util/cell-veneer/wrap_stdcells.tcl @@ -193,7 +193,7 @@ proc move_m2_pins_to_edge { cell_name cell_data } { dict for {pin_name pin} [dict get $cell_data pins] { set wires {} foreach physical_pin $pin { - if { [dict get $physical_pin to] >= [expr $cell_width / 2.0] } { + if { [dict get $physical_pin to] >= ($cell_width / 2.0) } { if { [dict exists $cell_data blockages] } { if { [wrapper::clear_right $physical_pin [dict get $cell_data blockages]] } { set direction right @@ -470,7 +470,7 @@ proc wrap_macro { cell_name } { # Need to check that the grid point we're trying to use is going to be accessible. # If it is not, then try the point 2 grid points higher if { [dict exists $grid_pins $grid_y] } { - if { [dict exists [expr $grid_y + 2]] } { + if { [dict exists $grid_pins [expr $grid_y + 2]] } { puts "Cell $cell_name" puts "Problem assigning pin grid - requested and upper grid points for $pin_name at $grid_y already allocated to [dict get $grid_pins $grid_y] and [dict get $grid_pins [expr $grid_y + 2]]" exit -1 diff --git a/flow/util/write_net_rc.tcl b/flow/util/write_net_rc.tcl index 68aa931832..3330091469 100644 --- a/flow/util/write_net_rc.tcl +++ b/flow/util/write_net_rc.tcl @@ -46,7 +46,7 @@ proc write_rc_csv { filename } { set is_routing([$layer getNumber]) $routing set is_routing([$layer getNumber]) $routing puts -nonewline $stream " [$layer getName]" - if $routing { + if { $routing } { puts -nonewline $stream "(routing)" } else { # insert via resistance information @@ -75,7 +75,7 @@ proc write_rc_csv { filename } { puts -nonewline $stream "[format %.3e $wire_res1],[format %.3e $wire_cap1],[format %.3e $wire_res2],[format %.3e $wire_cap2],[format %.3e $wire_res3],[format %.3e $wire_cap3]" set db_net [sta::sta_to_db_net $net] - if $use_drt_data { + if { $use_drt_data } { set layer_lengths [drt::route_layer_lengths [$db_net getWire]] } else { set layer_lengths [grt::route_layer_lengths $db_net] @@ -83,7 +83,7 @@ proc write_rc_csv { filename } { for { set layer 0 } { $layer < [$tech getLayerCount] } { incr layer } { set length [lindex $layer_lengths $layer] - if $is_routing($layer) { + if { $is_routing($layer) } { puts -nonewline $stream ",[ord::dbu_to_microns $length]" } else { puts -nonewline $stream ",$length" diff --git a/tclint.toml b/tclint.toml index 314f9c3e0b..8545a28fad 100644 --- a/tclint.toml +++ b/tclint.toml @@ -5,10 +5,10 @@ exclude = [ "flow/logs", "flow/designs", "flow/platforms", - "flow/util", "flow/scripts/*.tcl", "tools/OpenROAD", "tools/yosys", + "tools/yosys-slang", ] ignore = [ From 590f576a5435082f2ac136e8ecaefbee121c6a6b Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Mon, 30 Jun 2025 18:43:43 +0000 Subject: [PATCH 119/198] line-length: fix write_net_rc Signed-off-by: Jack Luar --- flow/util/write_net_rc.tcl | 46 +++++++++++++++++++++++++++++--------- 1 file changed, 36 insertions(+), 10 deletions(-) diff --git a/flow/util/write_net_rc.tcl b/flow/util/write_net_rc.tcl index 3330091469..35cb193a6a 100644 --- a/flow/util/write_net_rc.tcl +++ b/flow/util/write_net_rc.tcl @@ -71,8 +71,12 @@ proc write_rc_csv { filename } { lassign $rc_var1($net_name) wire_res1 wire_cap1 lassign $rc_var2($net_name) wire_res2 wire_cap2 lassign $rc_var3($net_name) wire_res3 wire_cap3 - puts -nonewline $stream "[get_full_name $net],[expr { [string equal $type "CLOCK"] ? "clock" : "signal" }]," - puts -nonewline $stream "[format %.3e $wire_res1],[format %.3e $wire_cap1],[format %.3e $wire_res2],[format %.3e $wire_cap2],[format %.3e $wire_res3],[format %.3e $wire_cap3]" + set net_type [expr {[string equal $type "CLOCK"] ? "clock" : "signal"}] + puts -nonewline $stream "[get_full_name $net],$net_type," + puts -nonewline $stream [concat \ + [format "%.3e" $wire_res1] "," [format "%.3e" $wire_cap1] "," \ + [format "%.3e" $wire_res2] "," [format "%.3e" $wire_cap2] "," \ + [format "%.3e" $wire_res3] "," [format "%.3e" $wire_cap3]] set db_net [sta::sta_to_db_net $net] if { $use_drt_data } { @@ -142,7 +146,8 @@ proc compare_wire_rc { count var_name ref_var_name } { # implicit arg to net_var_cap_less set var_cap_less_name $ref_var_name set nets [lsort -command net_var_cap_less [get_nets *]] - puts "net fanout [format %5s $var_name] [format %5s $ref_var_name] wire total [format %5s $var_name] [format %5s $ref_var_name]" + puts "net fanout [format %4s $var_name] [format %5s $ref_var_name] \ + wire total [format %5s $var_name] [format %5s $ref_var_name]" puts " cap cap delta delta res res delta" set res_sum 0.0 set res_count 0 @@ -163,8 +168,11 @@ proc compare_wire_rc { count var_name ref_var_name } { set res_avg [expr $res_sum / $count] set cap_avg [expr $cap_sum / $count] set total_cap_avg [expr $total_cap_sum / $count] - puts " ----- ----- -----" - puts " [format %+4.0f $cap_avg]% [format %+4.0f $total_cap_avg]% [format %+4.0f $res_avg]%" + puts " \ + ----- ----- -----" + puts " \ + [format %+4.0f $cap_avg]% [format %+4.0f $total_cap_avg]%\ + [format %+4.0f $res_avg]%" } proc compare_net_wire_rc { net_name var_name ref_var_name } { @@ -172,7 +180,8 @@ proc compare_net_wire_rc { net_name var_name ref_var_name } { upvar 1 $ref_var_name ref_var global var_cap_less_name - puts "net fanout [format %5s $var_name] [format %5s $ref_var_name] wire total" + puts "net fanout [format %5s $var_name] [format %5s $ref_var_name] \ + wire total" puts " cap cap delta delta" compare_wire_rc1 [get_net $net_name] $var_name $ref_var_name } @@ -210,9 +219,20 @@ proc compare_wire_rc1 { net var_name ref_var_name } { set fanout [llength [get_pins -of $net -filter "direction == input"]] - puts -nonewline "[format %-20s $net_name] [format %5d $fanout] [format %8s [sta::format_capacitance $wire_cap 3]] [format %8s [sta::format_capacitance $wire_cap_ref 3]] [format %4.0f $cap_delta]% [format %4.0f $total_delta]%" + puts -nonewline [concat \ + [format "%-20s" $net_name] " " \ + [format "%5d" $fanout] " " \ + [format "%8s" [sta::format_capacitance $wire_cap 3]] " " \ + [format "%8s" [sta::format_capacitance $wire_cap_ref 3]] " " \ + [format "%4.0f" $cap_delta]% " " \ + [format "%4.0f" $total_delta]% \ + ] if { $res > 0.0 } { - puts "[format %8s [sta::format_resistance $res 3]] [format %8s [sta::format_resistance $res_ref 3]] [format %4.0f $res_delta]%" + puts [concat \ + [format "%8s" [sta::format_resistance $res 3]] " " \ + [format "%8s" [sta::format_resistance $res_ref 3]] " " \ + [format "%4.0f" $res_delta]% \ + ] } else { puts "" } @@ -231,8 +251,14 @@ proc write_layer_rc_cmds { adjustment } { set cap_edge [$layer getEdgeCapacitance] set cap_area [$layer getCapacitance] # Convert pF/um to F/um. - set cap [expr ($cap_edge * 2.0 + $wire_width * $cap_area) * 1e-12 / (1.0 + $adjustment / 100.0)] - puts "set_layer_rc -layer [$layer getConstName] -resistance [format %.4e [sta::resistance_sta_ui $res]] -capacitance [format %.4e [sta::capacitance_sta_ui $cap]]" + set cap [expr \ + ($cap_edge * 2.0 + $wire_width * $cap_area) * 1e-12 / (1.0 + $adjustment / 100.0) \ + ] + puts [concat \ + "set_layer_rc -layer [$layer getConstName] " \ + "-resistance [format %.4e [sta::resistance_sta_ui $res]] " \ + "-capacitance [format %.4e [sta::capacitance_sta_ui $cap]]" \ + ] } } } From 613ca65253e03f8ba2ce2f1376b1b6f8cf420e30 Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Mon, 30 Jun 2025 18:56:54 +0000 Subject: [PATCH 120/198] line-length: fix cell-veneer/lefdef Signed-off-by: Jack Luar --- flow/util/cell-veneer/lefdef.tcl | 125 ++++++++++++++++++++++++------- 1 file changed, 97 insertions(+), 28 deletions(-) diff --git a/flow/util/cell-veneer/lefdef.tcl b/flow/util/cell-veneer/lefdef.tcl index 0d6d672c50..95ea39a364 100644 --- a/flow/util/cell-veneer/lefdef.tcl +++ b/flow/util/cell-veneer/lefdef.tcl @@ -93,11 +93,17 @@ proc read_macros { file_name } { } elseif { [regexp {CLASS\s+([^\s]*)} $line - cell_class] } { dict set cells $cell_name cell_class $cell_class } elseif { [regexp {ORIGIN\s+([^\s]*)\s+([^\s]*)} $line - origin_x origin_y] } { - dict set cells $cell_name origin [lmap x [list $origin_x $origin_y] { expr round($x * $def_units) }] + dict set cells $cell_name origin \ + [lmap x [list $origin_x $origin_y] { expr round($x * $def_units) }] } elseif { [regexp {FOREIGN\s+([^\s]*)\s+([^\s]*)\s+([^\s]*)} $line - foreign x y] } { - dict set cells $cell_name foreign [list ref $foreign origin [lmap x [list $x $y] { expr round($x * $def_units) }]] + dict set cells $cell_name foreign \ + [list ref $foreign \ + origin [lmap x [list $x $y] { expr round($x * $def_units) }]] } elseif { [regexp {SIZE\s+([^\s]*)\s+BY\s+([^\s]*)} $line - width height] } { - dict set cells $cell_name die_area [list 0 0 [expr round($width * $def_units)] [expr round($height * $def_units)]] + dict set cells $cell_name die_area \ + [list 0 0 \ + [expr round($width * $def_units)] \ + [expr round($height * $def_units)]] } elseif { [regexp {SYMMETRY\s+(.*)\s;} $line - symmetry] } { dict set cells $cell_name symmetry $symmetry } elseif { [regexp {SITE\s+([^\s]*)} $line - site] } { @@ -117,7 +123,8 @@ proc read_macros { file_name } { dict set cells $cell_name pins $pin_name use $use } elseif { [regexp {ANTENNAMODEL\s+([^\s]*)} $line - antennamodel] } { continue - } elseif { [regexp {ANTENNAGATEAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - gate_area layer] } { + } elseif { [regexp {ANTENNAGATEAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} \ + $line - gate_area layer] } { if { [info vars antennamodel] == "" } { set antennamodel "default" } @@ -139,7 +146,8 @@ proc read_macros { file_name } { } lappend model [list gate_area $gate_area] dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model - } elseif { [regexp {ANTENNADIFFAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - antennadiffarea layer] } { + } elseif { [regexp {ANTENNADIFFAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} \ + $line - antennadiffarea layer] } { dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea dict set cells $cell_name pins $pin_name antennadiffarea layer $antennadiffarea } elseif { [regexp {ANTENNADIFFAREA\s+([^\s]*)\s} $line - antennadiffarea] } { @@ -155,7 +163,8 @@ proc read_macros { file_name } { continue } elseif { [regexp {LAYER\s+([^\s]*)} $line - layer] } { continue - } elseif { [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] } { + } elseif { [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\ + \s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] } { if { [dict exists $port layers $layer shapes] } { set layer_shapes [dict get $port layers $layer shapes] } else { @@ -168,11 +177,14 @@ proc read_macros { file_name } { dict set port fixed $offset } set new_shape [list \ - rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] $offset] \ + rect [relative_rectangle \ + [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] \ + $offset] \ mask $mask] lappend layer_shapes $new_shape dict set port layers $layer shapes $layer_shapes - } elseif { [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] } { + } elseif { [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\ + \s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] } { if { [dict exists $port layers $layer shapes] } { set layer_shapes [dict get $port layers $layer shapes] } else { @@ -184,8 +196,11 @@ proc read_macros { file_name } { set offset [lmap x [list $x1 $y1] { expr round($x * $def_units) }] dict set port fixed $offset } - set new_shape [list \ - rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] $offset]] + set new_shape [list \ + rect [relative_rectangle \ + [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] \ + $offset] \ + ] lappend layer_shapes $new_shape dict set port layers $layer shapes $layer_shapes } elseif { [regexp {END} $line] } { @@ -212,26 +227,36 @@ proc read_macros { file_name } { set line [gets $ch] if { [regexp {^\s*$} $line] } { continue - } elseif { [regexp {LAYER\s+([^\s]*)(\s+DESIGNRULEWIDTH\s+([0-9.]+))?} $line - layer - drw] } { + } elseif { [regexp {LAYER\s+([^\s]*)(\s+DESIGNRULEWIDTH\s+([0-9.]+))?} \ + $line - layer - drw] } { if { $drw != "" } { dict set cells $cell_name layers $layer drw $drw } continue - } elseif { [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] } { + } elseif { [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\ + \s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] } { if { [dict exists $cells $cell_name obstructions $layer] } { set obstructions [dict get $cells $cell_name obstructions $layer] } else { set obstructions {} } - lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] mask $mask] + lappend obstructions [concat \ + [list rect [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }]] \ + [list mask $mask] \ + ] dict set cells $cell_name obstructions $layer $obstructions - } elseif { [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] } { + } elseif { [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\ + \s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] } { if { [dict exists $cells $cell_name obstructions $layer] } { set obstructions [dict get $cells $cell_name obstructions $layer] } else { set obstructions {} } - lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }]] + lappend obstructions [concat \ + [list rect \ + [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] \ + ] \ + ] dict set cells $cell_name obstructions $layer $obstructions } elseif { [regexp {END} $line] } { break @@ -270,6 +295,7 @@ proc write_header { } { proc write_footer { } { } +# tclint-disable-next-line line-length # Read a LEF from a file into a dictionary with the name of the cell as the key and the following entries # - cell_class # - origin @@ -309,7 +335,10 @@ proc write { design } { out " ORIGIN 0.0 0.0 ;" } out " FOREIGN [dict get $design foreign ref] [dict get $design foreign origin] ;" - out " SIZE [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units] BY [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units] ;" + out [concat \ + " SIZE [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units]" \ + " BY [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units] ;" \ + ] out " SYMMETRY [dict get $design symmetry] ;" if { [dict exists $design site] } { out " SITE [dict get $design site] ;" @@ -339,7 +368,11 @@ proc write { design } { set rect [absolute_rectangle [dict get $shape rect] $offset] if { [dict exists $shape mask] } { - out " RECT MASK [dict get $shape mask] [lmap x $rect { expr 1.0 * $x / $def_units }] ;" + out [concat \ + " RECT MASK [dict get $shape mask]" \ + " [lmap x $rect { expr {1.0 * $x / $def_units} }]" \ + " ;" \ + ] } else { out " RECT [lmap x $rect { expr 1.0 * $x / $def_units }] ;" } @@ -357,7 +390,11 @@ proc write { design } { dict for {layer_name obstructions} [dict get $design obstructions] { lappend blocked_layers $layer_name } - set sheet "0 0 [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units] [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units]" + set sheet [concat \ + 0 0 \ + [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units] \ + [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units] \ + ] foreach layer_name [get_blockage_layers $design] { if { [dict exists $design layers $layer_name drw] } { set drw "DESIGNRULEWIDTH [dict get $design layers $layer_name drw] " @@ -371,8 +408,12 @@ proc write { design } { dict for {layer_name obstructions} [dict get $design obstructions] { out " LAYER $layer_name ;" foreach obs $obstructions { - if { [dict exists $obs mask] } { - out " RECT MASK [dict get $obs mask] [lmap x [dict get $obs rect] { expr 1.0 * $x / $def_units }] ;" + if { [dict exists $obs mask] } { + out [concat \ + " RECT MASK [dict get $obs mask]" \ + " [lmap x [dict get $obs rect] { expr {1.0 * $x / $def_units} }]" \ + " ;" \ + ] } else { out " RECT [lmap x [dict get $obs rect] { expr 1.0 * $x / $def_units }] ;" } @@ -536,7 +577,10 @@ proc shift_point { point x y } { } proc shift_rect { rect x y } { - return [list [expr [lindex $rect 0] + $x] [expr [lindex $rect 1] + $y] [expr [lindex $rect 2] + $x] [expr [lindex $rect 3] + $y]] + return [concat \ + [list [expr [lindex $rect 0] + $x] [expr [lindex $rect 1] + $y]] \ + [list [expr [lindex $rect 2] + $x] [expr [lindex $rect 3] + $y]] \ + ] } proc shift_origin { design x y } { @@ -724,7 +768,10 @@ proc write { design } { } out "" - out "DIEAREA ( [lrange [dict get $design die_area] 0 1] ) ( [lrange [dict get $design die_area] 2 3] ) ;" + out [concat \ + "DIEAREA ( [lrange [dict get $design die_area] 0 1] )" \ + " ( [lrange [dict get $design die_area] 2 3] ) ;" \ + ] if { [dict exists $design tracks] } { @@ -732,8 +779,17 @@ proc write { design } { if { [dict exists $design rows] } { foreach idx [lsort -integer [dict keys $design rows]] { - out -nonewline "ROW ROW_$idx [dict get $design rows $idx site] [dict get $design rows $idx start] [dict get $design rows $idx height] [dict get $design rows $idx orientation]" - out " DO [dict get $design rows $idx num_sites] BY 1 STEP [dict get $design rows $idx site_width] 0 ;" + out -nonewline [concat \ + "ROW ROW_$idx" \ + [dict get $design rows $idx site] \ + [dict get $design rows $idx start] \ + [dict get $design rows $idx height] \ + [dict get $design rows $idx orientation] \ + ] + out [concat \ + " DO [dict get $design rows $idx num_sites] BY 1 STEP " \ + "[dict get $design rows $idx site_width] 0 ;" \ + ] } } @@ -741,7 +797,10 @@ proc write { design } { out "" out "PINS [dict size [dict get $design pins]] ;" dict for {pin_name pin} [dict get $design pins] { - out -nonewline "- $pin_name + NET [dict get $pin net_name] + DIRECTION [dict get $pin direction] " + out -nonewline [concat \ + "- $pin_name + NET [dict get $pin net_name]" \ + "+ DIRECTION [dict get $pin direction] " \ + ] if { [dict exists $pin use] } { out -nonewline "+ USE [dict get $pin use] " } @@ -839,7 +898,10 @@ proc write { design } { set mask "" } if { [llength $point] == 2 } { - out -nonewline " + $type [dict get $route layer] [get_line_width [dict get $route layer] [list $first_point $point]] " + out -nonewline [concat \ + " + $type [dict get $route layer] " \ + "[get_line_width [dict get $route layer] [list $first_point $point]] " \ + ] out -nonewline $shape out -nonewline $points out -nonewline $mask @@ -870,14 +932,21 @@ proc write { design } { } if { [dict exists $net routes] } { set route [lindex [dict get $net routes] 0] - out -nonewline " + ROUTED [dict get $route layer] [expr round([dict get $route width])] + SHAPE [dict get $route shape] " + out -nonewline [concat \ + " + ROUTED [dict get $route layer] " \ + "[expr round([dict get $route width])] " \ + "+ SHAPE [dict get $route shape] " \ + ] foreach point [dict get $route points] { out -nonewline " $point" } out "" foreach route [lrange [dict get $net routes] 1 end] { - out " NEW [dict get $route layer] [expr round([dict get $route width])] + SHAPE [dict get $route shape] " + out [concat \ + " NEW [dict get $route layer] [expr round([dict get $route width])]" \ + "+ SHAPE [dict get $route shape] " \ + ] foreach point [dict get $route points] { out -nonewline " $point" } From f849db42261533451a268e2bee9f313d81195b64 Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Mon, 30 Jun 2025 19:05:50 +0000 Subject: [PATCH 121/198] line-length: fix cell-veneer/wrap_stdcells Signed-off-by: Jack Luar --- flow/util/cell-veneer/wrap_stdcells.tcl | 90 ++++++++++++++++++++----- 1 file changed, 73 insertions(+), 17 deletions(-) diff --git a/flow/util/cell-veneer/wrap_stdcells.tcl b/flow/util/cell-veneer/wrap_stdcells.tcl index 820df77436..0cd86e23e3 100644 --- a/flow/util/cell-veneer/wrap_stdcells.tcl +++ b/flow/util/cell-veneer/wrap_stdcells.tcl @@ -102,7 +102,8 @@ proc clear_left { physical_pin blockages } { set track [dict get $physical_pin track] foreach blockage $blockages { - if { [dict get $blockage track] == $track && [dict get $blockage to] < [dict get $physical_pin from] } { + if { [dict get $blockage track] == $track && \ + [dict get $blockage to] < [dict get $physical_pin from] } { return 0 } } @@ -113,7 +114,8 @@ proc clear_right { physical_pin blockages } { set track [dict get $physical_pin track] foreach blockage $blockages { - if { [dict get $blockage track] == $track && [dict get $blockage from] > [dict get $physical_pin to] } { + if { [dict get $blockage track] == $track && \ + [dict get $blockage from] > [dict get $physical_pin to] } { return 0 } } @@ -179,7 +181,10 @@ proc move_m2_pins_to_edge { cell_name cell_data } { set layer_name [dict get $wrapper_cfg remove_pins layer] set layer_width [expr round([dict get $wrapper_cfg layer $layer_name width] * $def_units)] set new_pin_layer_name [dict get $wrapper_cfg new_pins layer] - set new_pin_layer_width [expr round([dict get $wrapper_cfg layer $new_pin_layer_name width] * $def_units)] + set new_pin_layer_width [expr round( \ + [dict get $wrapper_cfg layer $new_pin_layer_name width] * \ + $def_units \ + )] set cell_width [lindex [dict get [lef get_cell $cell_name] die_area] 2] set design [wrapper::create_def_wrapper $cell_name ${cell_name}_mod] set lower_y [expr 2 * 128] @@ -280,7 +285,14 @@ proc move_m2_pins_to_edge { cell_name cell_data } { dict set design obstructions M2 $m2_obstructions } # Replace the M2 port with an M1 port which is now at the side of the cells - set new_pin_rect [list [expr round($x2 - ($new_pin_layer_width / 2))] $lower_y [expr round($x2 + ($new_pin_layer_width / 2))] $upper_y] + set new_pin_rect [concat \ + [list \ + [expr round($x2 - ($new_pin_layer_width / 2))] \ + $lower_y \ + [expr round($x2 + ($new_pin_layer_width / 2))] \ + $upper_y \ + ] \ + ] if { [dict exists $port layers "M1" shapes] } { set shapes [dict get $port layers "M1" shapes] } else { @@ -368,7 +380,10 @@ proc move_m2_pins_to_edge { cell_name cell_data } { dict set design die_area [list \ 0 \ 0 \ - [expr [lindex [dict get $design die_area] 2] + (($pad_idx - ($left_padding + 1)) * $padding_cell_width)] \ + [concat \ + [expr [lindex [dict get $design die_area] 2] + \ + (($pad_idx - ($left_padding + 1)) * $padding_cell_width)] \ + ] \ [lindex [dict get $design die_area] 3]] # Extend VDD, VSS, VPW, VNW pins to be the width of the wrapper @@ -434,7 +449,13 @@ proc get_pin_rect { port layer } { set offset [list 0 0] } - return [absolute_rectangle [dict get [lindex [dict get $port layers $layer shapes] 0] rect] $offset] + return [absolute_rectangle \ + [dict get \ + [lindex \ + [dict get $port layers $layer shapes] 0 \ + ] rect \ + ] $offset \ + ] } proc wrap_macro { cell_name } { @@ -465,14 +486,19 @@ proc wrap_macro { cell_name } { } set macro_pin_y [expr ([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2] - set grid_y [expr round((floor(([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2 / [dict get $tech pitch horizontal_track]) - 1))] + set grid_y [expr round((floor( \ + ([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2 / \ + [dict get $tech pitch horizontal_track]) - 1))] # Need to check that the grid point we're trying to use is going to be accessible. # If it is not, then try the point 2 grid points higher if { [dict exists $grid_pins $grid_y] } { if { [dict exists $grid_pins [expr $grid_y + 2]] } { puts "Cell $cell_name" - puts "Problem assigning pin grid - requested and upper grid points for $pin_name at $grid_y already allocated to [dict get $grid_pins $grid_y] and [dict get $grid_pins [expr $grid_y + 2]]" + puts [concat "Problem assigning pin grid - requested and upper grid points " \ + "for $pin_name at " \ + "$grid_y already allocated to [dict get $grid_pins $grid_y] and " \ + "[dict get $grid_pins [expr $grid_y + 2]]"] exit -1 } set grid_y [expr $grid_y + 2] @@ -486,6 +512,7 @@ proc wrap_macro { cell_name } { set order [lsort -integer [dict keys $grid_pins]] set prev_pos [lindex $order 0] + # tclint-disable-next-line line-length # We will have a jog in the track, which needs to be on a vertical grid 3 units from the edge of the macro # If there is another pin close by, the we will need to have the jog 3 grids further in dict set net_info [dict get $grid_pins $prev_pos] h_offset 3 @@ -493,7 +520,11 @@ proc wrap_macro { cell_name } { if { $pin_pos - $prev_pos > 3 } { dict set net_info [dict get $grid_pins $pin_pos] h_offset 3 } else { - dict set net_info [dict get $grid_pins $pin_pos] h_offset [expr [dict get $net_info [dict get $grid_pins $prev_pos] h_offset] + 3] + dict set net_info [dict get $grid_pins $pin_pos] h_offset \ + [expr \ + [dict get $net_info [dict get $grid_pins $prev_pos] h_offset] \ + + 3 \ + ] } set prev_pos $pin_pos } @@ -507,12 +538,18 @@ proc wrap_macro { cell_name } { } set wrapper_depth [expr $wrapper_depth + 3] set macro_x [expr $wrapper_depth * [dict get $tech pitch vertical_track]] - set width [expr round((floor([lef get_width $cell] / [dict get $tech pitch vertical_track]) + 1) * [dict get $tech pitch vertical_track] )] - set height [expr round((floor([lef get_height $cell] / [dict get $tech pitch horizontal_track]) + 1) * [dict get $tech pitch horizontal_track])] + set width [expr round((floor([lef get_width $cell] / \ + [dict get $tech pitch vertical_track]) + 1) * \ + [dict get $tech pitch vertical_track])] + set height [expr round((floor([lef get_height $cell] / \ + [dict get $tech pitch horizontal_track]) + 1) * \ + [dict get $tech pitch horizontal_track])] # Now we know where the macro is placed, we know the size of the wrapper dict set wrapper die_area [list [expr round(-1 * $macro_x)] 0 [expr $width] $height] # debug "Set die area [dict get $wrapper die_area]" + + # tclint-disable-next-line line-length # Now we know the maximum extent of the space needed for the job we can add in the pins the appropriate number of grids to the left of the RAM # Shift the wrapper so the lower left corner is at (0, 0) @@ -542,14 +579,24 @@ proc wrap_macro { cell_name } { dict set new_port layers {} dict set new_port fixed [list 0 $y_position] dict set new_port layers "C4" shapes [list \ - [list rect [list 0 [expr 0 - [dict get $tech layer C4 width] / 2] [dict get $tech layer C4 depth] [expr 0 + [dict get $tech layer C4 width] / 2]]]] + [list rect [concat \ + [list 0 \ + [expr 0 - [dict get $tech layer C4 width] / 2] \ + [dict get $tech layer C4 depth] \ + [expr 0 + [dict get $tech layer C4 width] / 2] \ + ] \ + ]] \ + ] # debug "Replacing pin $net_name with $new_port" dict set wrapper pins $net_name ports [list $new_port] set segments {} # First segment from RAM to jog location, to the y grid of the pin - set target_grid_point [expr ($wrapper_depth - [dict get $net h_offset]) * [dict get $tech pitch vertical_track]] + set target_grid_point [expr \ + ($wrapper_depth - [dict get $net h_offset]) * \ + [dict get $tech pitch vertical_track] \ + ] set width [dict get $tech layer [dict get $net pin_layer] width] lappend segments [list \ layer [dict get $net pin_layer] \ @@ -591,7 +638,10 @@ proc test_harness { wrappers } { set grid_x_size [expr $max_cell_width + (2 * $site_width)] set grid_y_size [expr 4 * $site_height] - def new_design "test_harness" [dict get $wrapper_cfg def_units] [list 0 0 [expr round($grid_x_size * $num_grids)] [expr round($grid_y_size * $num_grids)]] + def new_design "test_harness" [dict get $wrapper_cfg def_units] \ + [concat [list 0 0] \ + [list [expr round($grid_x_size * $num_grids)] \ + [expr round($grid_y_size * $num_grids)]]] foreach cell [dict keys $wrappers] { set x [expr round(($idx % $num_grids) * $grid_x_size)] @@ -617,6 +667,7 @@ proc set_stdcell_config { config } { } proc run { } { + # tclint-disable-next-line line-length set file_name /projects/ssg/pj10000064_diphda/users/colhol01/openroad/library/arm/cp/14lpp/sc10p5mcpp84_base_lvt_c14/r2p1/lef/sc10p5mcpp84_14lpp_base_lvt_c14.lef lef read_macros $file_name @@ -633,7 +684,10 @@ proc convert_tech_to_def_units { tech } { dict for {layer_name layer} [dict get $tech layer] { foreach property {depth width non_preferred_width} { if { [dict exists $layer $property] } { - dict set tech layer $layer_name $property [expr round([dict get $layer $property] * $def_units)] + dict set tech layer $layer_name $property \ + [expr round( \ + [dict get $layer $property] * $def_units \ + )] } } } @@ -646,8 +700,10 @@ proc convert_tech_to_def_units { tech } { } } - dict set tech pitch vertical_track [expr round([dict get $tech pitch vertical_track] * $def_units)] - dict set tech pitch horizontal_track [expr round([dict get $tech pitch horizontal_track] * $def_units)] + dict set tech pitch vertical_track [expr round( \ + [dict get $tech pitch vertical_track] * $def_units)] + dict set tech pitch horizontal_track [expr round( \ + [dict get $tech pitch horizontal_track] * $def_units)] return $tech } From 6369d28c74ac89da7e6905a6c8132a60b4451c93 Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Mon, 30 Jun 2025 19:06:32 +0000 Subject: [PATCH 122/198] apply tclfmt Signed-off-by: Jack Luar --- flow/util/cell-veneer/lefdef.tcl | 108 ++++++++++++------------ flow/util/cell-veneer/wrap_stdcells.tcl | 47 +++++------ flow/util/write_net_rc.tcl | 14 ++- 3 files changed, 78 insertions(+), 91 deletions(-) diff --git a/flow/util/cell-veneer/lefdef.tcl b/flow/util/cell-veneer/lefdef.tcl index 95ea39a364..8beaa06df1 100644 --- a/flow/util/cell-veneer/lefdef.tcl +++ b/flow/util/cell-veneer/lefdef.tcl @@ -98,7 +98,7 @@ proc read_macros { file_name } { } elseif { [regexp {FOREIGN\s+([^\s]*)\s+([^\s]*)\s+([^\s]*)} $line - foreign x y] } { dict set cells $cell_name foreign \ [list ref $foreign \ - origin [lmap x [list $x $y] { expr round($x * $def_units) }]] + origin [lmap x [list $x $y] { expr round($x * $def_units) }]] } elseif { [regexp {SIZE\s+([^\s]*)\s+BY\s+([^\s]*)} $line - width height] } { dict set cells $cell_name die_area \ [list 0 0 \ @@ -123,8 +123,10 @@ proc read_macros { file_name } { dict set cells $cell_name pins $pin_name use $use } elseif { [regexp {ANTENNAMODEL\s+([^\s]*)} $line - antennamodel] } { continue - } elseif { [regexp {ANTENNAGATEAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} \ - $line - gate_area layer] } { + } elseif { + [regexp {ANTENNAGATEAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} \ + $line - gate_area layer] + } { if { [info vars antennamodel] == "" } { set antennamodel "default" } @@ -146,8 +148,10 @@ proc read_macros { file_name } { } lappend model [list gate_area $gate_area] dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model - } elseif { [regexp {ANTENNADIFFAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} \ - $line - antennadiffarea layer] } { + } elseif { + [regexp {ANTENNADIFFAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} \ + $line - antennadiffarea layer] + } { dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea dict set cells $cell_name pins $pin_name antennadiffarea layer $antennadiffarea } elseif { [regexp {ANTENNADIFFAREA\s+([^\s]*)\s} $line - antennadiffarea] } { @@ -163,8 +167,10 @@ proc read_macros { file_name } { continue } elseif { [regexp {LAYER\s+([^\s]*)} $line - layer] } { continue - } elseif { [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\ - \s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] } { + } elseif { + [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\ + \s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] + } { if { [dict exists $port layers $layer shapes] } { set layer_shapes [dict get $port layers $layer shapes] } else { @@ -183,8 +189,10 @@ proc read_macros { file_name } { mask $mask] lappend layer_shapes $new_shape dict set port layers $layer shapes $layer_shapes - } elseif { [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\ - \s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] } { + } elseif { + [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\ + \s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] + } { if { [dict exists $port layers $layer shapes] } { set layer_shapes [dict get $port layers $layer shapes] } else { @@ -196,11 +204,10 @@ proc read_macros { file_name } { set offset [lmap x [list $x1 $y1] { expr round($x * $def_units) }] dict set port fixed $offset } - set new_shape [list \ + set new_shape [list \ rect [relative_rectangle \ [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] \ - $offset] \ - ] + $offset]] lappend layer_shapes $new_shape dict set port layers $layer shapes $layer_shapes } elseif { [regexp {END} $line] } { @@ -227,36 +234,39 @@ proc read_macros { file_name } { set line [gets $ch] if { [regexp {^\s*$} $line] } { continue - } elseif { [regexp {LAYER\s+([^\s]*)(\s+DESIGNRULEWIDTH\s+([0-9.]+))?} \ - $line - layer - drw] } { + } elseif { + [regexp {LAYER\s+([^\s]*)(\s+DESIGNRULEWIDTH\s+([0-9.]+))?} \ + $line - layer - drw] + } { if { $drw != "" } { dict set cells $cell_name layers $layer drw $drw } continue - } elseif { [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\ - \s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] } { + } elseif { + [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\ + \s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] + } { if { [dict exists $cells $cell_name obstructions $layer] } { set obstructions [dict get $cells $cell_name obstructions $layer] } else { set obstructions {} } - lappend obstructions [concat \ + lappend obstructions [concat \ [list rect [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }]] \ - [list mask $mask] \ - ] + [list mask $mask]] dict set cells $cell_name obstructions $layer $obstructions - } elseif { [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\ - \s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] } { + } elseif { + [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\ + \s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] + } { if { [dict exists $cells $cell_name obstructions $layer] } { set obstructions [dict get $cells $cell_name obstructions $layer] } else { set obstructions {} } - lappend obstructions [concat \ + lappend obstructions [concat \ [list rect \ - [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] \ - ] \ - ] + [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }]]] dict set cells $cell_name obstructions $layer $obstructions } elseif { [regexp {END} $line] } { break @@ -337,8 +347,7 @@ proc write { design } { out " FOREIGN [dict get $design foreign ref] [dict get $design foreign origin] ;" out [concat \ " SIZE [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units]" \ - " BY [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units] ;" \ - ] + " BY [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units] ;"] out " SYMMETRY [dict get $design symmetry] ;" if { [dict exists $design site] } { out " SITE [dict get $design site] ;" @@ -369,10 +378,9 @@ proc write { design } { if { [dict exists $shape mask] } { out [concat \ - " RECT MASK [dict get $shape mask]" \ - " [lmap x $rect { expr {1.0 * $x / $def_units} }]" \ - " ;" \ - ] + " RECT MASK [dict get $shape mask]" \ + " [lmap x $rect { expr { 1.0 * $x / $def_units } }]" \ + " ;"] } else { out " RECT [lmap x $rect { expr 1.0 * $x / $def_units }] ;" } @@ -393,8 +401,7 @@ proc write { design } { set sheet [concat \ 0 0 \ [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units] \ - [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units] \ - ] + [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units]] foreach layer_name [get_blockage_layers $design] { if { [dict exists $design layers $layer_name drw] } { set drw "DESIGNRULEWIDTH [dict get $design layers $layer_name drw] " @@ -408,12 +415,11 @@ proc write { design } { dict for {layer_name obstructions} [dict get $design obstructions] { out " LAYER $layer_name ;" foreach obs $obstructions { - if { [dict exists $obs mask] } { + if { [dict exists $obs mask] } { out [concat \ " RECT MASK [dict get $obs mask]" \ - " [lmap x [dict get $obs rect] { expr {1.0 * $x / $def_units} }]" \ - " ;" \ - ] + " [lmap x [dict get $obs rect] { expr { 1.0 * $x / $def_units } }]" \ + " ;"] } else { out " RECT [lmap x [dict get $obs rect] { expr 1.0 * $x / $def_units }] ;" } @@ -579,8 +585,7 @@ proc shift_point { point x y } { proc shift_rect { rect x y } { return [concat \ [list [expr [lindex $rect 0] + $x] [expr [lindex $rect 1] + $y]] \ - [list [expr [lindex $rect 2] + $x] [expr [lindex $rect 3] + $y]] \ - ] + [list [expr [lindex $rect 2] + $x] [expr [lindex $rect 3] + $y]]] } proc shift_origin { design x y } { @@ -770,8 +775,7 @@ proc write { design } { out "" out [concat \ "DIEAREA ( [lrange [dict get $design die_area] 0 1] )" \ - " ( [lrange [dict get $design die_area] 2 3] ) ;" \ - ] + " ( [lrange [dict get $design die_area] 2 3] ) ;"] if { [dict exists $design tracks] } { @@ -784,12 +788,10 @@ proc write { design } { [dict get $design rows $idx site] \ [dict get $design rows $idx start] \ [dict get $design rows $idx height] \ - [dict get $design rows $idx orientation] \ - ] + [dict get $design rows $idx orientation]] out [concat \ " DO [dict get $design rows $idx num_sites] BY 1 STEP " \ - "[dict get $design rows $idx site_width] 0 ;" \ - ] + "[dict get $design rows $idx site_width] 0 ;"] } } @@ -799,8 +801,7 @@ proc write { design } { dict for {pin_name pin} [dict get $design pins] { out -nonewline [concat \ "- $pin_name + NET [dict get $pin net_name]" \ - "+ DIRECTION [dict get $pin direction] " \ - ] + "+ DIRECTION [dict get $pin direction] "] if { [dict exists $pin use] } { out -nonewline "+ USE [dict get $pin use] " } @@ -898,10 +899,9 @@ proc write { design } { set mask "" } if { [llength $point] == 2 } { - out -nonewline [concat \ + out -nonewline [concat \ " + $type [dict get $route layer] " \ - "[get_line_width [dict get $route layer] [list $first_point $point]] " \ - ] + "[get_line_width [dict get $route layer] [list $first_point $point]] "] out -nonewline $shape out -nonewline $points out -nonewline $mask @@ -935,18 +935,16 @@ proc write { design } { out -nonewline [concat \ " + ROUTED [dict get $route layer] " \ "[expr round([dict get $route width])] " \ - "+ SHAPE [dict get $route shape] " \ - ] + "+ SHAPE [dict get $route shape] "] foreach point [dict get $route points] { out -nonewline " $point" } out "" foreach route [lrange [dict get $net routes] 1 end] { - out [concat \ + out [concat \ " NEW [dict get $route layer] [expr round([dict get $route width])]" \ - "+ SHAPE [dict get $route shape] " \ - ] + "+ SHAPE [dict get $route shape] "] foreach point [dict get $route points] { out -nonewline " $point" } diff --git a/flow/util/cell-veneer/wrap_stdcells.tcl b/flow/util/cell-veneer/wrap_stdcells.tcl index 0cd86e23e3..f6ad587cc6 100644 --- a/flow/util/cell-veneer/wrap_stdcells.tcl +++ b/flow/util/cell-veneer/wrap_stdcells.tcl @@ -102,8 +102,10 @@ proc clear_left { physical_pin blockages } { set track [dict get $physical_pin track] foreach blockage $blockages { - if { [dict get $blockage track] == $track && \ - [dict get $blockage to] < [dict get $physical_pin from] } { + if { + [dict get $blockage track] == $track && + [dict get $blockage to] < [dict get $physical_pin from] + } { return 0 } } @@ -114,8 +116,10 @@ proc clear_right { physical_pin blockages } { set track [dict get $physical_pin track] foreach blockage $blockages { - if { [dict get $blockage track] == $track && \ - [dict get $blockage from] > [dict get $physical_pin to] } { + if { + [dict get $blockage track] == $track && + [dict get $blockage from] > [dict get $physical_pin to] + } { return 0 } } @@ -184,7 +188,7 @@ proc move_m2_pins_to_edge { cell_name cell_data } { set new_pin_layer_width [expr round( \ [dict get $wrapper_cfg layer $new_pin_layer_name width] * \ $def_units \ - )] + )] set cell_width [lindex [dict get [lef get_cell $cell_name] die_area] 2] set design [wrapper::create_def_wrapper $cell_name ${cell_name}_mod] set lower_y [expr 2 * 128] @@ -290,9 +294,7 @@ proc move_m2_pins_to_edge { cell_name cell_data } { [expr round($x2 - ($new_pin_layer_width / 2))] \ $lower_y \ [expr round($x2 + ($new_pin_layer_width / 2))] \ - $upper_y \ - ] \ - ] + $upper_y]] if { [dict exists $port layers "M1" shapes] } { set shapes [dict get $port layers "M1" shapes] } else { @@ -382,8 +384,7 @@ proc move_m2_pins_to_edge { cell_name cell_data } { 0 \ [concat \ [expr [lindex [dict get $design die_area] 2] + \ - (($pad_idx - ($left_padding + 1)) * $padding_cell_width)] \ - ] \ + (($pad_idx - ($left_padding + 1)) * $padding_cell_width)]] \ [lindex [dict get $design die_area] 3]] # Extend VDD, VSS, VPW, VNW pins to be the width of the wrapper @@ -452,10 +453,7 @@ proc get_pin_rect { port layer } { return [absolute_rectangle \ [dict get \ [lindex \ - [dict get $port layers $layer shapes] 0 \ - ] rect \ - ] $offset \ - ] + [dict get $port layers $layer shapes] 0] rect] $offset] } proc wrap_macro { cell_name } { @@ -523,8 +521,7 @@ proc wrap_macro { cell_name } { dict set net_info [dict get $grid_pins $pin_pos] h_offset \ [expr \ [dict get $net_info [dict get $grid_pins $prev_pos] h_offset] \ - + 3 \ - ] + + 3] } set prev_pos $pin_pos } @@ -580,13 +577,10 @@ proc wrap_macro { cell_name } { dict set new_port fixed [list 0 $y_position] dict set new_port layers "C4" shapes [list \ [list rect [concat \ - [list 0 \ - [expr 0 - [dict get $tech layer C4 width] / 2] \ - [dict get $tech layer C4 depth] \ - [expr 0 + [dict get $tech layer C4 width] / 2] \ - ] \ - ]] \ - ] + [list 0 \ + [expr 0 - [dict get $tech layer C4 width] / 2] \ + [dict get $tech layer C4 depth] \ + [expr 0 + [dict get $tech layer C4 width] / 2]]]]] # debug "Replacing pin $net_name with $new_port" dict set wrapper pins $net_name ports [list $new_port] @@ -595,8 +589,7 @@ proc wrap_macro { cell_name } { # First segment from RAM to jog location, to the y grid of the pin set target_grid_point [expr \ ($wrapper_depth - [dict get $net h_offset]) * \ - [dict get $tech pitch vertical_track] \ - ] + [dict get $tech pitch vertical_track]] set width [dict get $tech layer [dict get $net pin_layer] width] lappend segments [list \ layer [dict get $net pin_layer] \ @@ -641,7 +634,7 @@ proc test_harness { wrappers } { def new_design "test_harness" [dict get $wrapper_cfg def_units] \ [concat [list 0 0] \ [list [expr round($grid_x_size * $num_grids)] \ - [expr round($grid_y_size * $num_grids)]]] + [expr round($grid_y_size * $num_grids)]]] foreach cell [dict keys $wrappers] { set x [expr round(($idx % $num_grids) * $grid_x_size)] @@ -687,7 +680,7 @@ proc convert_tech_to_def_units { tech } { dict set tech layer $layer_name $property \ [expr round( \ [dict get $layer $property] * $def_units \ - )] + )] } } } diff --git a/flow/util/write_net_rc.tcl b/flow/util/write_net_rc.tcl index 35cb193a6a..9f6b5d2b49 100644 --- a/flow/util/write_net_rc.tcl +++ b/flow/util/write_net_rc.tcl @@ -71,7 +71,7 @@ proc write_rc_csv { filename } { lassign $rc_var1($net_name) wire_res1 wire_cap1 lassign $rc_var2($net_name) wire_res2 wire_cap2 lassign $rc_var3($net_name) wire_res3 wire_cap3 - set net_type [expr {[string equal $type "CLOCK"] ? "clock" : "signal"}] + set net_type [expr { [string equal $type "CLOCK"] ? "clock" : "signal" }] puts -nonewline $stream "[get_full_name $net],$net_type," puts -nonewline $stream [concat \ [format "%.3e" $wire_res1] "," [format "%.3e" $wire_cap1] "," \ @@ -225,14 +225,12 @@ proc compare_wire_rc1 { net var_name ref_var_name } { [format "%8s" [sta::format_capacitance $wire_cap 3]] " " \ [format "%8s" [sta::format_capacitance $wire_cap_ref 3]] " " \ [format "%4.0f" $cap_delta]% " " \ - [format "%4.0f" $total_delta]% \ - ] + [format "%4.0f" $total_delta]%] if { $res > 0.0 } { puts [concat \ [format "%8s" [sta::format_resistance $res 3]] " " \ [format "%8s" [sta::format_resistance $res_ref 3]] " " \ - [format "%4.0f" $res_delta]% \ - ] + [format "%4.0f" $res_delta]%] } else { puts "" } @@ -252,13 +250,11 @@ proc write_layer_rc_cmds { adjustment } { set cap_area [$layer getCapacitance] # Convert pF/um to F/um. set cap [expr \ - ($cap_edge * 2.0 + $wire_width * $cap_area) * 1e-12 / (1.0 + $adjustment / 100.0) \ - ] + ($cap_edge * 2.0 + $wire_width * $cap_area) * 1e-12 / (1.0 + $adjustment / 100.0)] puts [concat \ "set_layer_rc -layer [$layer getConstName] " \ "-resistance [format %.4e [sta::resistance_sta_ui $res]] " \ - "-capacitance [format %.4e [sta::capacitance_sta_ui $cap]]" \ - ] + "-capacitance [format %.4e [sta::capacitance_sta_ui $cap]]"] } } } From 990010acde15c93f0a078f99e27ef111aaa8c4fd Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Mon, 30 Jun 2025 19:25:23 +0000 Subject: [PATCH 123/198] revert read_macros - to avoid messing with regex spacing Signed-off-by: Jack Luar --- flow/util/cell-veneer/lefdef.tcl | 65 ++++++++------------------------ 1 file changed, 16 insertions(+), 49 deletions(-) diff --git a/flow/util/cell-veneer/lefdef.tcl b/flow/util/cell-veneer/lefdef.tcl index 8beaa06df1..27438a009c 100644 --- a/flow/util/cell-veneer/lefdef.tcl +++ b/flow/util/cell-veneer/lefdef.tcl @@ -72,6 +72,7 @@ proc get_height { cell } { return [expr [lindex [dict get $cell die_area] 3] - [lindex [dict get $cell die_area] 1]] } +# tclint-disable line-length proc read_macros { file_name } { variable cells variable def_units @@ -93,17 +94,11 @@ proc read_macros { file_name } { } elseif { [regexp {CLASS\s+([^\s]*)} $line - cell_class] } { dict set cells $cell_name cell_class $cell_class } elseif { [regexp {ORIGIN\s+([^\s]*)\s+([^\s]*)} $line - origin_x origin_y] } { - dict set cells $cell_name origin \ - [lmap x [list $origin_x $origin_y] { expr round($x * $def_units) }] + dict set cells $cell_name origin [lmap x [list $origin_x $origin_y] { expr round($x * $def_units) }] } elseif { [regexp {FOREIGN\s+([^\s]*)\s+([^\s]*)\s+([^\s]*)} $line - foreign x y] } { - dict set cells $cell_name foreign \ - [list ref $foreign \ - origin [lmap x [list $x $y] { expr round($x * $def_units) }]] + dict set cells $cell_name foreign [list ref $foreign origin [lmap x [list $x $y] { expr round($x * $def_units) }]] } elseif { [regexp {SIZE\s+([^\s]*)\s+BY\s+([^\s]*)} $line - width height] } { - dict set cells $cell_name die_area \ - [list 0 0 \ - [expr round($width * $def_units)] \ - [expr round($height * $def_units)]] + dict set cells $cell_name die_area [list 0 0 [expr round($width * $def_units)] [expr round($height * $def_units)]] } elseif { [regexp {SYMMETRY\s+(.*)\s;} $line - symmetry] } { dict set cells $cell_name symmetry $symmetry } elseif { [regexp {SITE\s+([^\s]*)} $line - site] } { @@ -123,10 +118,7 @@ proc read_macros { file_name } { dict set cells $cell_name pins $pin_name use $use } elseif { [regexp {ANTENNAMODEL\s+([^\s]*)} $line - antennamodel] } { continue - } elseif { - [regexp {ANTENNAGATEAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} \ - $line - gate_area layer] - } { + } elseif { [regexp {ANTENNAGATEAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - gate_area layer] } { if { [info vars antennamodel] == "" } { set antennamodel "default" } @@ -148,10 +140,7 @@ proc read_macros { file_name } { } lappend model [list gate_area $gate_area] dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model - } elseif { - [regexp {ANTENNADIFFAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} \ - $line - antennadiffarea layer] - } { + } elseif { [regexp {ANTENNADIFFAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - antennadiffarea layer] } { dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea dict set cells $cell_name pins $pin_name antennadiffarea layer $antennadiffarea } elseif { [regexp {ANTENNADIFFAREA\s+([^\s]*)\s} $line - antennadiffarea] } { @@ -167,10 +156,7 @@ proc read_macros { file_name } { continue } elseif { [regexp {LAYER\s+([^\s]*)} $line - layer] } { continue - } elseif { - [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\ - \s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] - } { + } elseif { [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] } { if { [dict exists $port layers $layer shapes] } { set layer_shapes [dict get $port layers $layer shapes] } else { @@ -183,16 +169,11 @@ proc read_macros { file_name } { dict set port fixed $offset } set new_shape [list \ - rect [relative_rectangle \ - [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] \ - $offset] \ + rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] $offset] \ mask $mask] lappend layer_shapes $new_shape dict set port layers $layer shapes $layer_shapes - } elseif { - [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\ - \s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] - } { + } elseif { [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] } { if { [dict exists $port layers $layer shapes] } { set layer_shapes [dict get $port layers $layer shapes] } else { @@ -205,9 +186,7 @@ proc read_macros { file_name } { dict set port fixed $offset } set new_shape [list \ - rect [relative_rectangle \ - [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] \ - $offset]] + rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] $offset]] lappend layer_shapes $new_shape dict set port layers $layer shapes $layer_shapes } elseif { [regexp {END} $line] } { @@ -234,39 +213,26 @@ proc read_macros { file_name } { set line [gets $ch] if { [regexp {^\s*$} $line] } { continue - } elseif { - [regexp {LAYER\s+([^\s]*)(\s+DESIGNRULEWIDTH\s+([0-9.]+))?} \ - $line - layer - drw] - } { + } elseif { [regexp {LAYER\s+([^\s]*)(\s+DESIGNRULEWIDTH\s+([0-9.]+))?} $line - layer - drw] } { if { $drw != "" } { dict set cells $cell_name layers $layer drw $drw } continue - } elseif { - [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\ - \s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] - } { + } elseif { [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] } { if { [dict exists $cells $cell_name obstructions $layer] } { set obstructions [dict get $cells $cell_name obstructions $layer] } else { set obstructions {} } - lappend obstructions [concat \ - [list rect [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }]] \ - [list mask $mask]] + lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] mask $mask] dict set cells $cell_name obstructions $layer $obstructions - } elseif { - [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\ - \s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] - } { + } elseif { [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] } { if { [dict exists $cells $cell_name obstructions $layer] } { set obstructions [dict get $cells $cell_name obstructions $layer] } else { set obstructions {} } - lappend obstructions [concat \ - [list rect \ - [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }]]] + lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }]] dict set cells $cell_name obstructions $layer $obstructions } elseif { [regexp {END} $line] } { break @@ -285,6 +251,7 @@ proc read_macros { file_name } { ::close $ch } +# tclint-enable line-length proc get_blockage_layers { design } { if { [dict exists $design blockage_layers] } { From 5f98ed403da95556173444a292bbcd4ec0249c6d Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Mon, 30 Jun 2025 15:54:52 -0700 Subject: [PATCH 124/198] Added EARLY_SIZING_CAP_RATIO setting in resize.tcl Signed-off-by: Jeff Ng --- docs/user/FlowVariables.md | 4 ++++ flow/scripts/resize.tcl | 4 ++++ flow/scripts/variables.yaml | 10 ++++++++++ 3 files changed, 18 insertions(+) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 023a105555..0478d053c3 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -128,6 +128,7 @@ configuration file. | DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| | | DONT_USE_LIBS| Set liberty files as `dont_use`.| | | DPO_MAX_DISPLACEMENT| Specifies how far an instance can be moved when optimizing.| 5 1| +| EARLY_SIZING_CAP_RATIO| Ratio between the input pin capacitance and the output pin load during initial gate sizing.| | | ENABLE_DPO| Enable detail placement with improve_placement feature.| 1| | EQUIVALENCE_CHECK| Enable running equivalence checks to verify logical correctness of repair_timing.| 0| | FASTROUTE_TCL| Specifies a Tcl script with commands to run before FastRoute.| | @@ -234,6 +235,7 @@ configuration file. | TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| | | TIEHI_CELL_AND_PORT| Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist.| | | TIELO_CELL_AND_PORT| Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.| | +| TIE_SEPARATION| Distance separating tie high/low instances from the load.| | | TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100| | USE_FILL| Whether to perform metal density filling.| 0| | VERILOG_DEFINES| Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`| | @@ -327,6 +329,7 @@ configuration file. - [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT) - [CELL_PAD_IN_SITES_GLOBAL_PLACEMENT](#CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) +- [EARLY_SIZING_CAP_RATIO](#EARLY_SIZING_CAP_RATIO) - [FLOORPLAN_DEF](#FLOORPLAN_DEF) - [GPL_ROUTABILITY_DRIVEN](#GPL_ROUTABILITY_DRIVEN) - [GPL_TIMING_DRIVEN](#GPL_TIMING_DRIVEN) @@ -343,6 +346,7 @@ configuration file. - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT) - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT) +- [TIE_SEPARATION](#TIE_SEPARATION) ## cts variables diff --git a/flow/scripts/resize.tcl b/flow/scripts/resize.tcl index 1982f9b9aa..9e81848921 100644 --- a/flow/scripts/resize.tcl +++ b/flow/scripts/resize.tcl @@ -10,6 +10,10 @@ set pin_count_before [sta::network_leaf_pin_count] set_dont_use $::env(DONT_USE_CELLS) +if { [env_var_exists_and_non_empty EARLY_SIZING_CAP_RATIO] } { + log_cmd set_opt_config -set_early_sizing_cap_ratio $env(EARLY_SIZING_CAP_RATIO) +} + repair_design_helper if { [env_var_exists_and_non_empty TIE_SEPARATION] } { diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index a4f5758ad0..3ac5a8bbe5 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -222,6 +222,16 @@ TIELO_CELL_AND_PORT: stages: - synth - place +TIE_SEPARATION: + description: | + Distance separating tie high/low instances from the load. + stages: + - place +EARLY_SIZING_CAP_RATIO: + description: | + Ratio between the input pin capacitance and the output pin load during initial gate sizing. + stages: + - place MIN_BUF_CELL_AND_PORTS: description: | Used to insert a buffer cell to pass through wires. Used in synthesis. From 5e7f715b21deaaef23238133485721fe336c8d2c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 2 Jul 2025 14:13:35 +0200 Subject: [PATCH 125/198] Update OR submodule MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index c79c8317e0..a090ebaa03 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit c79c8317e05ecbf45eba5096a74cb421ab97b7ae +Subproject commit a090ebaa03b3171cc7282e49d651c8280d9372b2 From 301d5d05b557c592a0eff0b42966b569efd09d53 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 2 Jul 2025 15:23:36 +0200 Subject: [PATCH 126/198] Work around issues after OR update MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- flow/designs/nangate45/bp_fe_top/config.mk | 2 ++ flow/scripts/load.tcl | 10 ++++++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/flow/designs/nangate45/bp_fe_top/config.mk b/flow/designs/nangate45/bp_fe_top/config.mk index 5e972adb6a..249771d43d 100644 --- a/flow/designs/nangate45/bp_fe_top/config.mk +++ b/flow/designs/nangate45/bp_fe_top/config.mk @@ -29,3 +29,5 @@ export PLACE_DENSITY_MAX_POST_HOLD = 0.13 export TNS_END_PERCENT = 100 export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl + +export GPL_KEEP_OVERFLOW = 0 diff --git a/flow/scripts/load.tcl b/flow/scripts/load.tcl index 2134f61dda..78c678081d 100644 --- a/flow/scripts/load.tcl +++ b/flow/scripts/load.tcl @@ -108,8 +108,14 @@ proc write_eqy_script { } { # See issue OpenROAD#6545 "Equivalence check failure due to non-unique resizer nets" puts $outfile "gate-nomatch net*" - # Necessary to avoid false positive after Yosys 0.49 - puts $outfile "gate-nomatch clone*\n\n" + # Forbid matching on buffer instances or cloned instances to make it less + # likely EQY will fail to prove equivalence because of its assuming structural + # similarity between gold and gate netlists. This doesn't remove coverage. + puts $outfile "gate-nomatch clone*" + puts $outfile "gate-nomatch place*" + puts $outfile "gate-nomatch rebuffer*" + puts $outfile "gate-nomatch wire*" + puts $outfile "gate-nomatch place*\n\n" # Equivalence check recipe 1 puts $outfile "\[strategy basic]\nuse sat\ndepth 10\n\n" From 04cf9bc96661764377220cb58aae240563bbad6c Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Wed, 2 Jul 2025 16:03:59 +0000 Subject: [PATCH 127/198] lint flow/designs Signed-off-by: Jack Luar --- flow/designs/asap7/cva6/constraint.sdc | 24 +- .../asap7/mock-array/macro-placement.tcl | 5 +- flow/designs/asap7/mock-array/power.tcl | 3 +- flow/designs/asap7/mock-cpu/constraint.sdc | 6 +- flow/designs/asap7/mock-cpu/io.tcl | 3 +- flow/designs/gf12/ariane/io.tcl | 3 +- flow/designs/gf12/ariane133/io.tcl | 3 +- flow/designs/gf12/bp_single/fastroute.tcl | 3 +- flow/designs/gf12/ca53/io.tcl | 3 +- flow/designs/gf12/coyote/constraint.sdc | 2409 +++++++++++------ flow/designs/gf12/coyote/constraint_hier.sdc | 2409 +++++++++++------ flow/designs/gf12/coyote/io.tcl | 3 +- flow/designs/gf12/swerv_wrapper/io.tcl | 3 +- .../uart-blocks/BLOCKS_grid_strategy.tcl | 6 +- .../designs/gf180/uart-blocks/uart_rx/pdn.tcl | 6 +- .../i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl | 12 +- .../i2c-gpio-expander/constraint.sdc | 42 +- .../ihp-sg13g2/i2c-gpio-expander/pad.tcl | 73 +- .../ihp-sg13g2/i2c-gpio-expander/pdn.tcl | 16 +- flow/designs/nangate45/ariane133/io.tcl | 3 +- flow/designs/nangate45/ariane136/io.tcl | 7 +- flow/designs/nangate45/black_parrot/io.tcl | 3 +- flow/designs/nangate45/bp_quad/io.tcl | 3 +- .../nangate45/mempool_group/mempool_group.sdc | 32 +- flow/designs/nangate45/swerv_wrapper/io.tcl | 3 +- .../designs/sky130hd/microwatt/constraint.sdc | 12 +- flow/designs/src/mock-array/util.tcl | 2 +- tclint.toml | 3 +- 28 files changed, 3396 insertions(+), 1704 deletions(-) diff --git a/flow/designs/asap7/cva6/constraint.sdc b/flow/designs/asap7/cva6/constraint.sdc index d0f4fbb0d9..724d7f20ea 100644 --- a/flow/designs/asap7/cva6/constraint.sdc +++ b/flow/designs/asap7/cva6/constraint.sdc @@ -14,15 +14,23 @@ create_clock [get_ports $clk_port] -name $clk_name -period $clk_period # set_dont_touch i_cache_subsystem/i_cva6_icache/gen_sram[*].data_sram # set_dont_touch i_cache_subsystem/i_cva6_icache/gen_sram[*].tag_sram # #constraint the timing to and from the sram black boxes -# set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] -# set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] -# set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] -# set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] +# set_input_delay -clock main_clk -max $input_delay \ +# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] +# set_input_delay -clock main_clk -max $input_delay \ +# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] +# set_input_delay -clock main_clk -max $input_delay \ +# i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] +# set_input_delay -clock main_clk -max $input_delay \ +# i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] -# set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] -# set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] -# set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] -# set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] +# set_output_delay $output_delay -max -clock main_clk \ +# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] +# set_output_delay $output_delay -max -clock main_clk \ +# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] +# set_output_delay $output_delay -max -clock main_clk \ +# i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] +# set_output_delay $output_delay -max -clock main_clk \ +# i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] set_false_path -to [get_ports {rvfi_probes_o}] diff --git a/flow/designs/asap7/mock-array/macro-placement.tcl b/flow/designs/asap7/mock-array/macro-placement.tcl index 9b1bc3fb70..6eed9be902 100644 --- a/flow/designs/asap7/mock-array/macro-placement.tcl +++ b/flow/designs/asap7/mock-array/macro-placement.tcl @@ -20,6 +20,9 @@ for { set i 0 } { $i < 8 } { incr i } { set macro_name [format "ces_%d_%d" $i $j] set x_location [expr { $j * $x_pitch + $x_offset }] set y_location [expr { $i * $y_pitch + $y_offset }] - place_macro -macro_name $macro_name -location [list [expr [ord::dbu_to_microns 1] * $x_location] [expr [ord::dbu_to_microns 1] * $y_location]] -orientation R0 + place_macro -macro_name $macro_name -location \ + [list [expr [ord::dbu_to_microns 1] * $x_location] \ + [expr [ord::dbu_to_microns 1] * $y_location]] \ + -orientation R0 } } diff --git a/flow/designs/asap7/mock-array/power.tcl b/flow/designs/asap7/mock-array/power.tcl index 5f7f136cf9..b132101bd8 100644 --- a/flow/designs/asap7/mock-array/power.tcl +++ b/flow/designs/asap7/mock-array/power.tcl @@ -114,7 +114,8 @@ if { $total_power_vcd == $total_power_user_activity } { } if { abs($total_power_vcd - $total_power_user_activity) > 1e-3 } { - puts "Error: Total power mismatch between VCD and user activity: $total_power_vcd vs $total_power_user_activity" + puts "Error: Total power mismatch between VCD and user activity: \ + $total_power_vcd vs $total_power_user_activity" exit 1 } diff --git a/flow/designs/asap7/mock-cpu/constraint.sdc b/flow/designs/asap7/mock-cpu/constraint.sdc index 8f5b42e89f..4648916e35 100644 --- a/flow/designs/asap7/mock-cpu/constraint.sdc +++ b/flow/designs/asap7/mock-cpu/constraint.sdc @@ -10,11 +10,13 @@ set clk_period 333 set clk2_period 1000 set clk1_name clk -create_clock -name $clk1_name -period $clk_period -waveform [list 0 [expr $clk_period/2]] [get_ports $clk1_name] +create_clock -name $clk1_name -period $clk_period -waveform \ + [list 0 [expr $clk_period/2]] [get_ports $clk1_name] set_clock_uncertainty 10 [get_clocks $clk1_name] set clk2_name clk_uncore -create_clock -name $clk2_name -period $clk2_period -waveform [list 0 [expr $clk_period/2]] [get_ports $clk2_name] +create_clock -name $clk2_name -period $clk2_period -waveform \ + [list 0 [expr $clk_period/2]] [get_ports $clk2_name] set_clock_uncertainty 10 [get_clocks $clk2_name] set_clock_groups -group $clk1_name -group $clk2_name -asynchronous -allow_paths diff --git a/flow/designs/asap7/mock-cpu/io.tcl b/flow/designs/asap7/mock-cpu/io.tcl index 322f85c1f4..ea8b842fc3 100644 --- a/flow/designs/asap7/mock-cpu/io.tcl +++ b/flow/designs/asap7/mock-cpu/io.tcl @@ -6,4 +6,5 @@ foreach prefix {"" flow/} { } } -set_io_pin_constraint -order -group -region bottom:* -pin_names [concat [match_pins .*] [match_pins clk input 1]] +set_io_pin_constraint -order -group -region bottom:* \ + -pin_names [concat [match_pins .*] [match_pins clk input 1]] diff --git a/flow/designs/gf12/ariane/io.tcl b/flow/designs/gf12/ariane/io.tcl index 9a9b44e885..b49abf4c20 100644 --- a/flow/designs/gf12/ariane/io.tcl +++ b/flow/designs/gf12/ariane/io.tcl @@ -1 +1,2 @@ -exclude_io_pin_region -region left:0-150 -region left:450-600 -region right:* -region top:* -region bottom:* +exclude_io_pin_region -region left:0-150 -region left:450-600 -region right:* \ + -region top:* -region bottom:* diff --git a/flow/designs/gf12/ariane133/io.tcl b/flow/designs/gf12/ariane133/io.tcl index 9dbb9bc470..6ac9789e72 100644 --- a/flow/designs/gf12/ariane133/io.tcl +++ b/flow/designs/gf12/ariane133/io.tcl @@ -1 +1,2 @@ -exclude_io_pin_region -region left:0-200 -region left:500-700 -region right:* -region top:* -region bottom:* +exclude_io_pin_region -region left:0-200 -region left:500-700 -region right:* \ + -region top:* -region bottom:* diff --git a/flow/designs/gf12/bp_single/fastroute.tcl b/flow/designs/gf12/bp_single/fastroute.tcl index e05f213a65..69e55f9f90 100644 --- a/flow/designs/gf12/bp_single/fastroute.tcl +++ b/flow/designs/gf12/bp_single/fastroute.tcl @@ -3,4 +3,5 @@ set_global_routing_layer_adjustment M3 0.6 set_global_routing_layer_adjustment C4-C5 0.5 set_global_routing_layer_adjustment K1-K4 0.45 -set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) -clock K1-$::env(MAX_ROUTING_LAYER) +set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) \ + -clock K1-$::env(MAX_ROUTING_LAYER) diff --git a/flow/designs/gf12/ca53/io.tcl b/flow/designs/gf12/ca53/io.tcl index 77f5111afc..89e27e2ff6 100644 --- a/flow/designs/gf12/ca53/io.tcl +++ b/flow/designs/gf12/ca53/io.tcl @@ -1 +1,2 @@ -exclude_io_pin_region -region left:0-600 -region left:1350-1400 -region right:* -region top:* -region bottom:* +exclude_io_pin_region -region left:0-600 -region left:1350-1400 -region right:* \ + -region top:* -region bottom:* diff --git a/flow/designs/gf12/coyote/constraint.sdc b/flow/designs/gf12/coyote/constraint.sdc index d80a6cd806..b110ae09d5 100644 --- a/flow/designs/gf12/coyote/constraint.sdc +++ b/flow/designs/gf12/coyote/constraint.sdc @@ -11,809 +11,1612 @@ set_clock_transition 59.0000 [get_clocks {core_clk}] set_clock_uncertainty -setup 200.0000 core_clk set_clock_uncertainty -hold 20.0000 core_clk set_clock_latency -source 0.0000 [get_clocks {core_clk}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {en_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[0]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[10]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[11]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[12]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[13]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[14]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[15]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[16]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[17]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[18]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[19]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[1]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[20]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[21]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[22]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[23]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[24]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[25]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[26]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[27]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[28]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[29]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[2]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[30]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[31]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[32]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[33]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[34]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[35]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[36]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[37]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[38]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[39]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[3]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[40]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[41]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[42]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[43]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[44]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[45]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[46]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[47]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[48]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[49]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[4]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[50]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[51]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[52]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[53]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[54]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[55]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[56]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[57]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[58]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[59]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[5]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[60]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[61]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[62]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[63]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[64]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[65]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[66]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[67]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[68]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[69]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[6]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[70]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[71]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[72]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[73]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[74]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[75]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[76]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[77]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[78]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[79]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[7]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[8]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[9]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_yumi_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {reset_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_ready_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_busy_}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_interrupt_}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[0]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[100]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[101]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[102]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[103]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[104]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[105]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[106]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[107]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[108]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[109]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[10]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[110]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[111]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[112]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[113]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[114]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[115]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[116]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[117]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[118]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[119]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[11]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[120]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[121]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[122]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[12]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[13]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[14]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[15]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[16]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[17]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[18]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[19]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[1]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[20]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[21]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[22]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[23]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[24]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[25]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[26]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[27]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[28]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[29]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[2]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[30]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[31]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[32]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[33]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[34]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[35]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[36]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[37]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[38]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[39]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[3]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[40]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[41]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[42]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[43]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[44]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[45]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[46]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[47]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[48]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[49]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[4]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[50]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[51]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[52]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[53]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[54]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[55]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[56]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[57]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[58]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[59]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[5]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[60]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[61]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[62]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[63]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[64]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[65]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[66]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[67]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[68]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[69]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[6]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[70]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[71]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[72]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[73]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[74]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[75]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[76]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[77]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[78]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[79]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[7]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[80]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[81]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[82]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[83]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[84]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[85]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[86]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[87]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[88]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[89]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[8]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[90]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[91]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[92]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[93]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[94]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[95]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[96]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[97]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[98]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[99]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[9]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_v_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[0]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[10]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[11]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[12]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[13]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[14]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[15]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[16]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[17]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[18]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[19]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[1]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[20]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[21]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[22]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[23]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[24]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[25]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[26]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[27]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[28]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[29]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[2]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[30]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[31]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[32]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[33]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[34]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[35]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[36]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[37]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[38]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[39]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[3]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[40]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[41]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[42]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[43]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[44]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[45]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[46]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[47]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[48]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[49]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[4]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[50]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[51]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[52]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[53]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[54]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[55]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[56]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[57]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[58]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[59]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[5]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[60]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[61]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[62]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[63]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[64]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[65]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[66]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[67]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[68]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[6]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[7]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[8]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[9]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_v_i}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[0]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[10]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[11]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[12]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[13]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[14]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[15]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[16]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[17]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[18]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[19]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[1]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[20]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[21]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[22]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[23]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[24]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[25]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[26]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[27]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[28]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[29]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[2]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[30]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[31]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[32]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[33]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[34]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[35]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[36]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[37]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[38]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[39]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[3]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[40]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[41]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[42]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[43]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[44]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[45]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[46]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[47]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[48]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[49]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[4]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[50]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[51]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[52]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[53]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[54]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[55]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[56]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[57]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[58]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[59]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[5]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[60]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[61]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[62]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[63]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[64]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[65]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[66]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[67]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[68]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[69]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[6]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[70]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[71]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[72]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[73]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[74]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[75]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[76]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[77]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[78]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[79]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[7]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[8]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[9]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_ready_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[0]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[100]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[101]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[102]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[103]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[104]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[105]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[106]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[107]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[108]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[109]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[10]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[110]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[111]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[112]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[113]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[114]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[115]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[116]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[117]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[118]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[119]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[11]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[120]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[121]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[122]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[123]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[124]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[125]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[126]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[127]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[128]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[129]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[12]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[130]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[131]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[132]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[133]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[134]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[135]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[136]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[137]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[138]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[139]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[13]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[140]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[141]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[142]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[143]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[144]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[145]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[146]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[147]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[148]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[149]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[14]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[150]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[151]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[152]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[153]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[154]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[155]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[156]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[157]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[158]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[159]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[15]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[16]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[17]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[18]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[19]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[1]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[20]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[21]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[22]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[23]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[24]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[25]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[26]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[27]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[28]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[29]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[2]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[30]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[31]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[32]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[33]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[34]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[35]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[36]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[37]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[38]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[39]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[3]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[40]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[41]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[42]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[43]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[44]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[45]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[46]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[47]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[48]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[49]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[4]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[50]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[51]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[52]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[53]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[54]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[55]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[56]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[57]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[58]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[59]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[5]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[60]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[61]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[62]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[63]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[64]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[65]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[66]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[67]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[68]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[69]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[6]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[70]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[71]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[72]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[73]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[74]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[75]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[76]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[77]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[78]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[79]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[7]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[80]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[81]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[82]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[83]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[84]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[85]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[86]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[87]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[88]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[89]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[8]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[90]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[91]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[92]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[93]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[94]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[95]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[96]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[97]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[98]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[99]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[9]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_v_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_exception_}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_host_id_}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_s_}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_ready_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[0]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[100]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[101]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[102]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[103]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[104]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[105]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[106]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[107]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[108]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[109]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[10]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[110]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[111]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[112]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[113]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[114]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[115]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[116]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[117]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[118]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[119]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[11]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[120]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[121]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[122]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[123]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[124]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[125]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[126]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[127]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[128]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[129]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[12]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[130]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[131]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[132]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[133]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[134]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[135]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[136]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[137]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[138]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[139]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[13]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[140]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[141]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[142]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[143]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[144]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[145]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[146]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[147]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[148]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[149]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[14]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[150]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[151]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[152]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[153]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[154]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[155]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[156]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[157]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[158]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[159]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[15]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[160]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[161]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[162]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[163]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[164]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[165]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[166]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[167]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[168]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[169]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[16]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[170]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[171]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[172]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[173]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[174]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[175]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[176]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[177]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[178]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[179]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[17]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[180]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[181]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[182]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[183]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[184]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[185]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[186]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[187]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[188]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[189]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[18]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[190]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[191]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[192]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[193]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[194]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[195]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[196]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[197]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[198]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[199]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[19]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[1]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[200]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[201]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[202]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[203]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[204]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[205]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[206]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[207]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[208]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[209]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[20]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[210]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[211]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[212]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[213]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[214]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[215]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[216]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[217]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[218]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[219]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[21]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[220]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[221]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[222]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[223]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[224]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[225]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[226]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[227]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[228]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[229]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[22]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[230]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[231]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[232]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[233]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[234]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[235]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[236]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[237]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[238]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[239]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[23]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[240]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[241]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[242]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[243]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[244]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[245]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[246]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[247]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[248]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[249]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[24]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[250]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[251]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[252]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[25]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[26]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[27]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[28]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[29]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[2]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[30]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[31]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[32]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[33]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[34]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[35]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[36]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[37]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[38]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[39]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[3]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[40]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[41]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[42]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[43]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[44]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[45]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[46]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[47]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[48]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[49]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[4]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[50]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[51]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[52]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[53]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[54]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[55]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[56]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[57]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[58]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[59]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[5]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[60]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[61]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[62]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[63]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[64]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[65]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[66]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[67]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[68]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[69]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[6]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[70]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[71]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[72]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[73]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[74]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[75]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[76]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[77]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[78]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[79]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[7]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[80]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[81]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[82]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[83]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[84]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[85]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[86]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[87]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[88]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[89]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[8]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[90]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[91]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[92]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[93]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[94]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[95]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[96]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[97]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[98]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[99]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[9]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_v_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_ready_o}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem1.macro_mem0}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {en_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[0]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[10]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[11]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[12]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[13]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[14]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[15]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[16]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[17]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[18]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[19]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[1]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[20]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[21]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[22]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[23]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[24]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[25]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[26]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[27]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[28]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[29]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[2]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[30]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[31]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[32]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[33]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[34]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[35]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[36]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[37]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[38]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[39]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[3]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[40]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[41]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[42]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[43]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[44]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[45]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[46]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[47]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[48]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[49]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[4]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[50]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[51]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[52]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[53]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[54]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[55]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[56]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[57]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[58]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[59]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[5]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[60]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[61]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[62]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[63]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[64]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[65]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[66]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[67]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[68]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[69]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[6]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[70]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[71]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[72]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[73]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[74]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[75]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[76]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[77]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[78]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[79]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[7]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[8]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[9]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_yumi_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {reset_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_ready_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_busy_}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_interrupt_}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[0]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[100]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[101]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[102]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[103]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[104]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[105]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[106]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[107]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[108]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[109]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[10]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[110]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[111]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[112]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[113]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[114]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[115]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[116]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[117]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[118]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[119]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[11]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[120]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[121]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[122]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[12]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[13]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[14]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[15]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[16]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[17]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[18]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[19]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[1]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[20]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[21]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[22]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[23]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[24]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[25]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[26]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[27]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[28]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[29]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[2]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[30]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[31]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[32]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[33]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[34]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[35]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[36]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[37]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[38]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[39]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[3]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[40]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[41]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[42]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[43]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[44]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[45]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[46]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[47]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[48]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[49]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[4]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[50]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[51]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[52]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[53]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[54]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[55]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[56]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[57]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[58]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[59]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[5]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[60]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[61]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[62]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[63]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[64]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[65]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[66]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[67]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[68]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[69]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[6]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[70]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[71]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[72]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[73]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[74]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[75]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[76]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[77]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[78]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[79]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[7]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[80]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[81]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[82]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[83]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[84]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[85]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[86]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[87]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[88]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[89]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[8]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[90]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[91]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[92]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[93]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[94]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[95]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[96]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[97]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[98]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[99]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[9]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_v_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[0]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[10]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[11]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[12]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[13]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[14]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[15]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[16]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[17]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[18]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[19]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[1]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[20]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[21]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[22]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[23]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[24]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[25]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[26]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[27]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[28]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[29]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[2]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[30]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[31]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[32]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[33]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[34]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[35]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[36]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[37]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[38]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[39]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[3]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[40]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[41]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[42]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[43]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[44]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[45]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[46]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[47]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[48]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[49]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[4]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[50]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[51]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[52]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[53]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[54]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[55]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[56]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[57]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[58]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[59]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[5]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[60]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[61]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[62]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[63]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[64]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[65]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[66]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[67]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[68]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[6]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[7]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[8]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[9]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_v_i}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[0]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[10]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[11]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[12]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[13]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[14]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[15]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[16]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[17]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[18]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[19]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[1]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[20]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[21]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[22]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[23]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[24]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[25]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[26]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[27]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[28]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[29]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[2]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[30]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[31]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[32]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[33]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[34]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[35]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[36]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[37]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[38]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[39]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[3]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[40]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[41]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[42]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[43]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[44]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[45]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[46]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[47]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[48]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[49]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[4]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[50]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[51]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[52]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[53]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[54]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[55]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[56]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[57]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[58]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[59]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[5]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[60]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[61]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[62]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[63]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[64]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[65]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[66]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[67]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[68]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[69]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[6]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[70]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[71]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[72]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[73]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[74]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[75]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[76]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[77]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[78]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[79]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[7]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[8]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[9]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_ready_o}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_o}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[0]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[100]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[101]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[102]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[103]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[104]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[105]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[106]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[107]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[108]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[109]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[10]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[110]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[111]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[112]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[113]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[114]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[115]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[116]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[117]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[118]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[119]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[11]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[120]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[121]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[122]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[123]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[124]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[125]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[126]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[127]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[128]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[129]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[12]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[130]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[131]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[132]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[133]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[134]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[135]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[136]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[137]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[138]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[139]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[13]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[140]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[141]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[142]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[143]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[144]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[145]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[146]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[147]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[148]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[149]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[14]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[150]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[151]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[152]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[153]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[154]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[155]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[156]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[157]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[158]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[159]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[15]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[16]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[17]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[18]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[19]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[1]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[20]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[21]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[22]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[23]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[24]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[25]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[26]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[27]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[28]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[29]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[2]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[30]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[31]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[32]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[33]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[34]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[35]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[36]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[37]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[38]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[39]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[3]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[40]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[41]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[42]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[43]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[44]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[45]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[46]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[47]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[48]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[49]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[4]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[50]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[51]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[52]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[53]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[54]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[55]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[56]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[57]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[58]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[59]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[5]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[60]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[61]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[62]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[63]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[64]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[65]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[66]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[67]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[68]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[69]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[6]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[70]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[71]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[72]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[73]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[74]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[75]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[76]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[77]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[78]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[79]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[7]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[80]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[81]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[82]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[83]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[84]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[85]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[86]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[87]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[88]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[89]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[8]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[90]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[91]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[92]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[93]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[94]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[95]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[96]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[97]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[98]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[99]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[9]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_v_o}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_exception_}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_host_id_}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_s_}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_ready_o}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[0]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[100]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[101]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[102]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[103]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[104]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[105]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[106]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[107]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[108]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[109]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[10]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[110]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[111]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[112]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[113]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[114]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[115]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[116]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[117]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[118]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[119]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[11]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[120]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[121]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[122]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[123]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[124]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[125]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[126]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[127]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[128]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[129]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[12]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[130]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[131]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[132]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[133]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[134]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[135]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[136]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[137]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[138]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[139]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[13]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[140]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[141]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[142]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[143]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[144]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[145]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[146]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[147]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[148]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[149]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[14]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[150]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[151]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[152]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[153]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[154]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[155]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[156]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[157]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[158]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[159]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[15]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[160]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[161]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[162]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[163]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[164]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[165]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[166]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[167]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[168]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[169]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[16]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[170]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[171]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[172]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[173]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[174]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[175]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[176]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[177]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[178]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[179]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[17]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[180]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[181]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[182]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[183]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[184]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[185]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[186]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[187]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[188]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[189]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[18]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[190]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[191]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[192]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[193]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[194]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[195]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[196]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[197]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[198]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[199]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[19]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[1]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[200]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[201]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[202]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[203]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[204]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[205]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[206]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[207]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[208]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[209]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[20]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[210]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[211]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[212]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[213]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[214]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[215]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[216]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[217]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[218]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[219]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[21]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[220]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[221]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[222]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[223]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[224]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[225]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[226]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[227]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[228]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[229]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[22]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[230]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[231]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[232]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[233]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[234]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[235]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[236]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[237]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[238]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[239]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[23]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[240]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[241]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[242]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[243]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[244]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[245]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[246]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[247]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[248]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[249]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[24]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[250]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[251]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[252]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[25]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[26]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[27]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[28]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[29]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[2]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[30]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[31]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[32]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[33]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[34]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[35]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[36]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[37]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[38]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[39]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[3]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[40]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[41]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[42]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[43]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[44]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[45]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[46]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[47]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[48]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[49]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[4]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[50]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[51]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[52]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[53]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[54]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[55]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[56]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[57]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[58]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[59]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[5]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[60]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[61]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[62]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[63]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[64]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[65]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[66]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[67]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[68]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[69]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[6]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[70]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[71]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[72]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[73]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[74]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[75]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[76]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[77]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[78]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[79]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[7]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[80]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[81]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[82]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[83]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[84]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[85]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[86]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[87]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[88]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[89]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[8]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[90]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[91]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[92]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[93]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[94]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[95]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[96]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[97]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[98]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[99]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[9]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_v_o}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_ready_o}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem1.macro_mem0}] set_false_path \ -to [list [get_ports {rocc_ctrl_o_exception_}] \ [get_ports {rocc_ctrl_o_host_id_}] \ diff --git a/flow/designs/gf12/coyote/constraint_hier.sdc b/flow/designs/gf12/coyote/constraint_hier.sdc index d8a085a067..3ca86c77ea 100644 --- a/flow/designs/gf12/coyote/constraint_hier.sdc +++ b/flow/designs/gf12/coyote/constraint_hier.sdc @@ -11,809 +11,1612 @@ set_clock_transition 59.0000 [get_clocks {core_clk}] set_clock_uncertainty -setup 200.0000 core_clk set_clock_uncertainty -hold 20.0000 core_clk set_clock_latency -source 0.0000 [get_clocks {core_clk}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {en_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[0]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[10]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[11]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[12]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[13]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[14]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[15]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[16]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[17]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[18]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[19]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[1]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[20]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[21]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[22]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[23]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[24]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[25]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[26]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[27]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[28]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[29]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[2]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[30]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[31]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[32]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[33]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[34]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[35]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[36]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[37]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[38]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[39]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[3]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[40]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[41]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[42]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[43]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[44]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[45]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[46]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[47]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[48]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[49]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[4]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[50]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[51]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[52]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[53]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[54]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[55]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[56]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[57]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[58]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[59]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[5]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[60]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[61]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[62]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[63]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[64]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[65]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[66]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[67]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[68]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[69]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[6]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[70]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[71]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[72]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[73]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[74]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[75]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[76]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[77]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[78]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[79]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[7]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[8]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[9]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_yumi_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {reset_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_ready_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_busy_}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_interrupt_}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[0]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[100]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[101]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[102]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[103]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[104]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[105]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[106]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[107]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[108]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[109]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[10]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[110]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[111]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[112]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[113]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[114]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[115]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[116]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[117]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[118]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[119]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[11]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[120]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[121]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[122]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[12]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[13]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[14]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[15]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[16]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[17]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[18]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[19]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[1]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[20]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[21]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[22]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[23]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[24]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[25]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[26]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[27]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[28]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[29]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[2]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[30]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[31]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[32]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[33]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[34]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[35]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[36]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[37]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[38]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[39]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[3]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[40]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[41]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[42]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[43]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[44]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[45]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[46]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[47]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[48]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[49]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[4]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[50]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[51]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[52]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[53]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[54]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[55]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[56]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[57]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[58]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[59]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[5]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[60]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[61]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[62]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[63]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[64]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[65]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[66]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[67]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[68]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[69]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[6]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[70]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[71]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[72]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[73]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[74]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[75]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[76]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[77]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[78]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[79]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[7]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[80]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[81]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[82]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[83]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[84]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[85]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[86]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[87]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[88]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[89]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[8]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[90]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[91]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[92]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[93]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[94]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[95]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[96]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[97]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[98]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[99]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[9]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_v_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[0]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[10]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[11]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[12]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[13]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[14]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[15]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[16]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[17]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[18]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[19]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[1]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[20]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[21]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[22]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[23]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[24]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[25]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[26]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[27]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[28]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[29]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[2]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[30]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[31]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[32]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[33]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[34]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[35]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[36]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[37]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[38]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[39]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[3]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[40]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[41]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[42]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[43]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[44]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[45]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[46]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[47]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[48]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[49]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[4]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[50]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[51]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[52]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[53]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[54]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[55]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[56]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[57]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[58]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[59]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[5]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[60]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[61]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[62]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[63]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[64]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[65]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[66]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[67]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[68]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[6]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[7]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[8]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[9]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_v_i}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[0]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[10]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[11]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[12]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[13]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[14]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[15]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[16]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[17]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[18]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[19]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[1]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[20]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[21]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[22]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[23]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[24]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[25]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[26]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[27]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[28]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[29]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[2]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[30]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[31]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[32]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[33]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[34]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[35]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[36]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[37]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[38]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[39]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[3]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[40]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[41]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[42]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[43]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[44]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[45]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[46]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[47]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[48]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[49]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[4]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[50]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[51]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[52]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[53]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[54]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[55]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[56]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[57]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[58]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[59]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[5]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[60]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[61]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[62]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[63]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[64]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[65]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[66]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[67]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[68]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[69]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[6]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[70]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[71]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[72]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[73]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[74]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[75]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[76]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[77]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[78]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[79]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[7]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[8]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[9]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_ready_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[0]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[100]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[101]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[102]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[103]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[104]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[105]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[106]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[107]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[108]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[109]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[10]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[110]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[111]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[112]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[113]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[114]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[115]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[116]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[117]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[118]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[119]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[11]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[120]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[121]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[122]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[123]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[124]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[125]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[126]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[127]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[128]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[129]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[12]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[130]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[131]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[132]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[133]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[134]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[135]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[136]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[137]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[138]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[139]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[13]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[140]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[141]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[142]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[143]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[144]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[145]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[146]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[147]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[148]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[149]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[14]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[150]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[151]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[152]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[153]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[154]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[155]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[156]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[157]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[158]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[159]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[15]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[16]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[17]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[18]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[19]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[1]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[20]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[21]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[22]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[23]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[24]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[25]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[26]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[27]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[28]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[29]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[2]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[30]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[31]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[32]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[33]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[34]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[35]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[36]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[37]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[38]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[39]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[3]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[40]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[41]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[42]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[43]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[44]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[45]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[46]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[47]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[48]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[49]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[4]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[50]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[51]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[52]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[53]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[54]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[55]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[56]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[57]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[58]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[59]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[5]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[60]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[61]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[62]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[63]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[64]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[65]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[66]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[67]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[68]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[69]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[6]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[70]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[71]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[72]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[73]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[74]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[75]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[76]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[77]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[78]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[79]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[7]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[80]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[81]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[82]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[83]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[84]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[85]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[86]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[87]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[88]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[89]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[8]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[90]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[91]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[92]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[93]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[94]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[95]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[96]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[97]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[98]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[99]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[9]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_v_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_exception_}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_host_id_}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_s_}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_ready_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[0]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[100]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[101]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[102]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[103]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[104]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[105]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[106]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[107]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[108]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[109]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[10]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[110]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[111]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[112]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[113]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[114]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[115]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[116]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[117]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[118]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[119]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[11]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[120]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[121]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[122]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[123]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[124]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[125]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[126]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[127]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[128]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[129]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[12]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[130]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[131]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[132]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[133]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[134]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[135]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[136]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[137]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[138]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[139]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[13]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[140]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[141]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[142]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[143]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[144]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[145]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[146]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[147]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[148]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[149]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[14]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[150]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[151]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[152]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[153]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[154]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[155]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[156]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[157]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[158]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[159]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[15]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[160]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[161]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[162]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[163]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[164]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[165]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[166]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[167]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[168]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[169]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[16]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[170]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[171]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[172]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[173]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[174]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[175]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[176]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[177]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[178]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[179]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[17]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[180]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[181]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[182]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[183]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[184]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[185]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[186]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[187]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[188]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[189]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[18]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[190]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[191]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[192]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[193]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[194]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[195]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[196]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[197]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[198]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[199]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[19]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[1]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[200]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[201]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[202]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[203]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[204]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[205]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[206]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[207]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[208]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[209]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[20]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[210]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[211]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[212]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[213]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[214]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[215]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[216]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[217]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[218]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[219]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[21]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[220]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[221]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[222]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[223]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[224]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[225]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[226]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[227]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[228]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[229]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[22]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[230]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[231]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[232]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[233]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[234]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[235]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[236]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[237]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[238]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[239]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[23]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[240]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[241]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[242]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[243]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[244]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[245]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[246]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[247]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[248]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[249]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[24]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[250]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[251]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[252]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[25]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[26]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[27]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[28]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[29]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[2]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[30]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[31]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[32]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[33]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[34]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[35]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[36]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[37]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[38]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[39]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[3]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[40]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[41]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[42]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[43]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[44]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[45]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[46]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[47]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[48]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[49]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[4]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[50]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[51]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[52]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[53]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[54]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[55]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[56]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[57]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[58]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[59]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[5]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[60]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[61]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[62]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[63]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[64]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[65]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[66]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[67]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[68]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[69]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[6]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[70]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[71]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[72]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[73]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[74]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[75]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[76]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[77]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[78]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[79]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[7]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[80]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[81]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[82]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[83]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[84]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[85]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[86]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[87]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[88]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[89]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[8]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[90]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[91]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[92]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[93]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[94]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[95]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[96]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[97]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[98]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[99]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[9]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_v_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_ready_o}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {en_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[0]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[10]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[11]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[12]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[13]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[14]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[15]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[16]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[17]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[18]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[19]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[1]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[20]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[21]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[22]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[23]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[24]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[25]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[26]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[27]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[28]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[29]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[2]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[30]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[31]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[32]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[33]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[34]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[35]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[36]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[37]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[38]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[39]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[3]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[40]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[41]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[42]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[43]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[44]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[45]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[46]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[47]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[48]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[49]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[4]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[50]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[51]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[52]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[53]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[54]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[55]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[56]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[57]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[58]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[59]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[5]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[60]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[61]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[62]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[63]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[64]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[65]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[66]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[67]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[68]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[69]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[6]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[70]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[71]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[72]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[73]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[74]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[75]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[76]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[77]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[78]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[79]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[7]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[8]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[9]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_yumi_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {reset_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_ready_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_busy_}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_interrupt_}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[0]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[100]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[101]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[102]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[103]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[104]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[105]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[106]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[107]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[108]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[109]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[10]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[110]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[111]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[112]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[113]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[114]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[115]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[116]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[117]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[118]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[119]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[11]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[120]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[121]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[122]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[12]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[13]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[14]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[15]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[16]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[17]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[18]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[19]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[1]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[20]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[21]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[22]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[23]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[24]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[25]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[26]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[27]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[28]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[29]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[2]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[30]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[31]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[32]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[33]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[34]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[35]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[36]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[37]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[38]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[39]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[3]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[40]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[41]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[42]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[43]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[44]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[45]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[46]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[47]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[48]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[49]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[4]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[50]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[51]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[52]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[53]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[54]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[55]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[56]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[57]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[58]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[59]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[5]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[60]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[61]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[62]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[63]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[64]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[65]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[66]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[67]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[68]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[69]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[6]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[70]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[71]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[72]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[73]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[74]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[75]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[76]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[77]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[78]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[79]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[7]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[80]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[81]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[82]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[83]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[84]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[85]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[86]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[87]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[88]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[89]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[8]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[90]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[91]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[92]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[93]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[94]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[95]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[96]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[97]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[98]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[99]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[9]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_v_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[0]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[10]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[11]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[12]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[13]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[14]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[15]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[16]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[17]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[18]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[19]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[1]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[20]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[21]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[22]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[23]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[24]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[25]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[26]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[27]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[28]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[29]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[2]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[30]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[31]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[32]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[33]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[34]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[35]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[36]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[37]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[38]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[39]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[3]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[40]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[41]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[42]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[43]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[44]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[45]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[46]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[47]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[48]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[49]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[4]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[50]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[51]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[52]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[53]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[54]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[55]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[56]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[57]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[58]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[59]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[5]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[60]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[61]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[62]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[63]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[64]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[65]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[66]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[67]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[68]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[6]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[7]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[8]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[9]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_v_i}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[0]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[10]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[11]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[12]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[13]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[14]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[15]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[16]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[17]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[18]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[19]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[1]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[20]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[21]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[22]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[23]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[24]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[25]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[26]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[27]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[28]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[29]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[2]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[30]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[31]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[32]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[33]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[34]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[35]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[36]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[37]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[38]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[39]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[3]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[40]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[41]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[42]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[43]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[44]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[45]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[46]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[47]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[48]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[49]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[4]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[50]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[51]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[52]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[53]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[54]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[55]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[56]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[57]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[58]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[59]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[5]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[60]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[61]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[62]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[63]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[64]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[65]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[66]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[67]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[68]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[69]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[6]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[70]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[71]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[72]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[73]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[74]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[75]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[76]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[77]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[78]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[79]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[7]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[8]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[9]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_ready_o}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_o}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[0]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[100]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[101]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[102]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[103]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[104]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[105]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[106]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[107]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[108]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[109]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[10]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[110]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[111]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[112]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[113]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[114]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[115]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[116]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[117]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[118]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[119]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[11]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[120]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[121]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[122]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[123]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[124]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[125]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[126]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[127]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[128]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[129]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[12]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[130]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[131]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[132]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[133]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[134]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[135]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[136]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[137]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[138]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[139]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[13]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[140]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[141]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[142]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[143]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[144]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[145]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[146]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[147]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[148]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[149]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[14]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[150]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[151]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[152]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[153]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[154]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[155]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[156]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[157]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[158]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[159]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[15]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[16]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[17]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[18]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[19]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[1]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[20]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[21]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[22]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[23]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[24]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[25]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[26]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[27]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[28]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[29]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[2]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[30]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[31]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[32]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[33]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[34]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[35]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[36]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[37]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[38]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[39]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[3]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[40]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[41]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[42]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[43]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[44]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[45]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[46]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[47]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[48]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[49]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[4]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[50]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[51]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[52]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[53]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[54]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[55]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[56]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[57]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[58]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[59]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[5]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[60]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[61]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[62]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[63]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[64]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[65]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[66]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[67]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[68]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[69]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[6]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[70]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[71]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[72]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[73]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[74]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[75]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[76]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[77]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[78]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[79]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[7]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[80]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[81]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[82]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[83]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[84]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[85]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[86]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[87]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[88]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[89]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[8]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[90]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[91]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[92]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[93]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[94]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[95]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[96]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[97]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[98]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[99]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[9]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_v_o}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_exception_}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_host_id_}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_s_}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_ready_o}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[0]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[100]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[101]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[102]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[103]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[104]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[105]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[106]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[107]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[108]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[109]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[10]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[110]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[111]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[112]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[113]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[114]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[115]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[116]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[117]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[118]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[119]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[11]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[120]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[121]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[122]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[123]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[124]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[125]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[126]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[127]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[128]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[129]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[12]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[130]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[131]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[132]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[133]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[134]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[135]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[136]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[137]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[138]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[139]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[13]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[140]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[141]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[142]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[143]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[144]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[145]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[146]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[147]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[148]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[149]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[14]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[150]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[151]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[152]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[153]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[154]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[155]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[156]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[157]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[158]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[159]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[15]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[160]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[161]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[162]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[163]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[164]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[165]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[166]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[167]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[168]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[169]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[16]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[170]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[171]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[172]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[173]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[174]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[175]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[176]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[177]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[178]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[179]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[17]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[180]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[181]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[182]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[183]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[184]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[185]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[186]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[187]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[188]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[189]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[18]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[190]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[191]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[192]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[193]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[194]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[195]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[196]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[197]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[198]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[199]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[19]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[1]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[200]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[201]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[202]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[203]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[204]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[205]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[206]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[207]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[208]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[209]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[20]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[210]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[211]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[212]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[213]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[214]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[215]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[216]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[217]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[218]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[219]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[21]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[220]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[221]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[222]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[223]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[224]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[225]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[226]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[227]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[228]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[229]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[22]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[230]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[231]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[232]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[233]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[234]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[235]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[236]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[237]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[238]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[239]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[23]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[240]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[241]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[242]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[243]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[244]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[245]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[246]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[247]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[248]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[249]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[24]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[250]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[251]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[252]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[25]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[26]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[27]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[28]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[29]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[2]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[30]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[31]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[32]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[33]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[34]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[35]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[36]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[37]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[38]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[39]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[3]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[40]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[41]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[42]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[43]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[44]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[45]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[46]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[47]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[48]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[49]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[4]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[50]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[51]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[52]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[53]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[54]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[55]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[56]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[57]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[58]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[59]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[5]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[60]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[61]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[62]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[63]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[64]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[65]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[66]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[67]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[68]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[69]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[6]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[70]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[71]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[72]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[73]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[74]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[75]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[76]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[77]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[78]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[79]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[7]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[80]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[81]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[82]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[83]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[84]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[85]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[86]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[87]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[88]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[89]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[8]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[90]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[91]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[92]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[93]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[94]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[95]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[96]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[97]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[98]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[99]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[9]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_v_o}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_ready_o}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}] set_false_path \ -to [list [get_ports {rocc_ctrl_o_exception_}] \ [get_ports {rocc_ctrl_o_host_id_}] \ diff --git a/flow/designs/gf12/coyote/io.tcl b/flow/designs/gf12/coyote/io.tcl index eddd0b8d59..0154d2704c 100644 --- a/flow/designs/gf12/coyote/io.tcl +++ b/flow/designs/gf12/coyote/io.tcl @@ -1 +1,2 @@ -exclude_io_pin_region -region left:* -region right:* -region top:* -region bottom:0-20 -region bottom:450-750 +exclude_io_pin_region -region left:* -region right:* -region top:* \ + -region bottom:0-20 -region bottom:450-750 diff --git a/flow/designs/gf12/swerv_wrapper/io.tcl b/flow/designs/gf12/swerv_wrapper/io.tcl index fc3731672b..0545c0cca8 100644 --- a/flow/designs/gf12/swerv_wrapper/io.tcl +++ b/flow/designs/gf12/swerv_wrapper/io.tcl @@ -1 +1,2 @@ -exclude_io_pin_region -region left:* -region right:* -region top:* -region bottom:0-10 -region bottom:400-700 +exclude_io_pin_region -region left:* -region right:* -region top:* \ + -region bottom:0-10 -region bottom:400-700 diff --git a/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl b/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl index 15070643eb..c431fbff0f 100644 --- a/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl +++ b/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl @@ -20,12 +20,14 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} #################################### define_pdn_grid -name {block} -voltage_domains {CORE} add_pdn_stripe -grid {block} -layer {Metal1} -width {0.900} -pitch {5.040} -offset {0} -followpins -add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} -offset {22.4} +add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} \ + -offset {22.4} add_pdn_stripe -grid {block} -layer {Metal5} -width {4.480} -pitch {89.6} -offset {44.8} add_pdn_connect -grid {block} -layers {Metal1 Metal4} add_pdn_connect -grid {block} -layers {Metal4 Metal5} #################################### # Block grids #################################### -define_pdn_grid -macro -cells uart_rx -halo "2.0 2.0 2.0 2.0" -voltage_domains {CORE} -name BlocksGrid +define_pdn_grid -macro -cells uart_rx -halo "2.0 2.0 2.0 2.0" -voltage_domains {CORE} \ + -name BlocksGrid add_pdn_connect -grid {BlocksGrid} -layers {Metal4 Metal5} diff --git a/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl b/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl index fce426a382..ac80ec7d83 100644 --- a/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl +++ b/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl @@ -19,6 +19,8 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} # standard cell grid #################################### define_pdn_grid -name {block} -voltage_domains {CORE} -add_pdn_stripe -grid {block} -layer {Metal1} -width {0.900} -pitch {5.040} -offset {0} -followpins -add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} -offset {22.4} +add_pdn_stripe -grid {block} -layer {Metal1} -width {0.900} -pitch {5.040} -offset {0} \ + -followpins +add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} \ + -offset {22.4} add_pdn_connect -grid {block} -layers {Metal1 Metal4} diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl index fd105772b5..aa6f2f142a 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl @@ -26,9 +26,13 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} # stdcell grid define_pdn_grid -name {grid} -voltage_domains {CORE} -add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins -extend_to_core_ring -add_pdn_ring -grid {grid} -layers {Metal3 Metal4} -widths {3.0} -spacings {2.0} -core_offsets {4.5} -connect_to_pads -add_pdn_stripe -grid {grid} -layer {Metal3} -width {1.840} -pitch {75.6} -offset {37.8} -extend_to_core_ring -add_pdn_stripe -grid {grid} -layer {Metal4} -width {1.840} -pitch {75.6} -offset {37.8} -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} \ + -followpins -extend_to_core_ring +add_pdn_ring -grid {grid} -layers {Metal3 Metal4} -widths {3.0} -spacings {2.0} \ + -core_offsets {4.5} -connect_to_pads +add_pdn_stripe -grid {grid} -layer {Metal3} -width {1.840} -pitch {75.6} -offset {37.8} \ + -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {Metal4} -width {1.840} -pitch {75.6} -offset {37.8} \ + -extend_to_core_ring add_pdn_connect -grid {grid} -layers {Metal1 Metal3} add_pdn_connect -grid {grid} -layers {Metal3 Metal4} diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc b/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc index 7f9b71f07d..b66bcf5e1c 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc @@ -10,44 +10,44 @@ create_clock [get_pins sg13g2_IOPad_io_clock/p2c] -name clk_core -period 20.0 -w set_clock_uncertainty 0.15 [get_clocks clk_core] set_clock_transition 0.25 [get_clocks clk_core] -set clock_ports [get_ports { - io_clock_PAD +set clock_ports [get_ports { + io_clock_PAD }] set_driving_cell -lib_cell sg13g2_IOPadIn -pin pad $clock_ports -set clk_core_inout_16mA_ports [get_ports { - io_gpio_0_PAD - io_gpio_1_PAD - io_gpio_2_PAD - io_gpio_3_PAD - io_gpio_4_PAD - io_gpio_5_PAD - io_gpio_6_PAD - io_gpio_7_PAD +set clk_core_inout_16mA_ports [get_ports { + io_gpio_0_PAD + io_gpio_1_PAD + io_gpio_2_PAD + io_gpio_3_PAD + io_gpio_4_PAD + io_gpio_5_PAD + io_gpio_6_PAD + io_gpio_7_PAD }] set_driving_cell -lib_cell sg13g2_IOPadInOut16mA -pin pad $clk_core_inout_16mA_ports set_input_delay 8 -clock clk_core $clk_core_inout_16mA_ports set_output_delay 8 -clock clk_core $clk_core_inout_16mA_ports -set clk_core_inout_4mA_ports [get_ports { - io_i2c_scl_PAD - io_i2c_sda_PAD +set clk_core_inout_4mA_ports [get_ports { + io_i2c_scl_PAD + io_i2c_sda_PAD }] set_driving_cell -lib_cell sg13g2_IOPadInOut4mA -pin pad $clk_core_inout_4mA_ports set_input_delay 8 -clock clk_core $clk_core_inout_4mA_ports set_output_delay 8 -clock clk_core $clk_core_inout_4mA_ports -set clk_core_input_ports [get_ports { - io_reset_PAD - io_address_0_PAD - io_address_1_PAD - io_address_2_PAD +set clk_core_input_ports [get_ports { + io_reset_PAD + io_address_0_PAD + io_address_1_PAD + io_address_2_PAD }] set_driving_cell -lib_cell sg13g2_IOPadIn -pin pad $clk_core_input_ports set_input_delay 8 -clock clk_core $clk_core_input_ports -set clk_core_output_4mA_ports [get_ports { - io_i2c_interrupt_PAD +set clk_core_output_4mA_ports [get_ports { + io_i2c_interrupt_PAD }] set_driving_cell -lib_cell sg13g2_IOPadOut4mA -pin pad $clk_core_output_4mA_ports set_output_delay 8 -clock clk_core $clk_core_output_4mA_ports diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl index 2e2773ec98..1e7d27baa8 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl @@ -15,7 +15,10 @@ proc calc_horizontal_pad_location { index total } { set PAD_AREA_WIDTH [expr { $DIE_WIDTH - ($PAD_OFFSET * 2) }] set HORIZONTAL_PAD_DISTANCE [expr { ($PAD_AREA_WIDTH / $total) - $IO_WIDTH }] - return [expr { $PAD_OFFSET + (($IO_WIDTH + $HORIZONTAL_PAD_DISTANCE) * $index) + ($HORIZONTAL_PAD_DISTANCE / 2) }] + return [expr { + $PAD_OFFSET + (($IO_WIDTH + $HORIZONTAL_PAD_DISTANCE) * $index) + + ($HORIZONTAL_PAD_DISTANCE / 2) + }] } proc calc_vertical_pad_location { index total } { @@ -29,7 +32,10 @@ proc calc_vertical_pad_location { index total } { set PAD_AREA_HEIGHT [expr { $DIE_HEIGHT - ($PAD_OFFSET * 2) }] set VERTICAL_PAD_DISTANCE [expr { ($PAD_AREA_HEIGHT / $total) - $IO_WIDTH }] - return [expr { $PAD_OFFSET + (($IO_WIDTH + $VERTICAL_PAD_DISTANCE) * $index) + ($VERTICAL_PAD_DISTANCE / 2) }] + return [expr { + $PAD_OFFSET + (($IO_WIDTH + $VERTICAL_PAD_DISTANCE) * $index) + + ($VERTICAL_PAD_DISTANCE / 2) + }] } make_fake_io_site -name IOLibSite -width 1 -height $IO_LENGTH @@ -43,42 +49,63 @@ make_io_sites \ -corner_site IOLibCSite \ -offset $IO_OFFSET -# Place Pads\n# IO pin io_clock -place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 0 5] {sg13g2_IOPad_io_clock} -master sg13g2_IOPadIn +# Place Pads +# IO pin io_clock +place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 0 5] \ + {sg13g2_IOPad_io_clock} -master sg13g2_IOPadIn # IO pin io_reset -place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 1 5] {sg13g2_IOPad_io_reset} -master sg13g2_IOPadIn +place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 1 5] \ + {sg13g2_IOPad_io_reset} -master sg13g2_IOPadIn # IO pin io_i2c_scl -place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 2 5] {sg13g2_IOPad_io_i2c_scl} -master sg13g2_IOPadInOut4mA +place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 2 5] \ + {sg13g2_IOPad_io_i2c_scl} -master sg13g2_IOPadInOut4mA # IO pin io_i2c_sda -place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 3 5] {sg13g2_IOPad_io_i2c_sda} -master sg13g2_IOPadInOut4mA +place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 3 5] \ + {sg13g2_IOPad_io_i2c_sda} -master sg13g2_IOPadInOut4mA # IO pin io_i2c_interrupt -place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 4 5] {sg13g2_IOPad_io_i2c_interrupt} -master sg13g2_IOPadOut4mA -place_pad -row IO_EAST -location [calc_vertical_pad_location 0 5] {sg13g2_IOPadVdd_east_0} -master sg13g2_IOPadVdd -place_pad -row IO_EAST -location [calc_vertical_pad_location 1 5] {sg13g2_IOPadVss_east_1} -master sg13g2_IOPadVss +place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 4 5] \ + {sg13g2_IOPad_io_i2c_interrupt} -master sg13g2_IOPadOut4mA +place_pad -row IO_EAST -location [calc_vertical_pad_location 0 5] \ + {sg13g2_IOPadVdd_east_0} -master sg13g2_IOPadVdd +place_pad -row IO_EAST -location [calc_vertical_pad_location 1 5] \ + {sg13g2_IOPadVss_east_1} -master sg13g2_IOPadVss # IO pin io_address_0 -place_pad -row IO_EAST -location [calc_vertical_pad_location 2 5] {sg13g2_IOPad_io_address_0} -master sg13g2_IOPadIn +place_pad -row IO_EAST -location [calc_vertical_pad_location 2 5] \ + {sg13g2_IOPad_io_address_0} -master sg13g2_IOPadIn # IO pin io_address_1 -place_pad -row IO_EAST -location [calc_vertical_pad_location 3 5] {sg13g2_IOPad_io_address_1} -master sg13g2_IOPadIn +place_pad -row IO_EAST -location [calc_vertical_pad_location 3 5] \ + {sg13g2_IOPad_io_address_1} -master sg13g2_IOPadIn # IO pin io_address_2 -place_pad -row IO_EAST -location [calc_vertical_pad_location 4 5] {sg13g2_IOPad_io_address_2} -master sg13g2_IOPadIn +place_pad -row IO_EAST -location [calc_vertical_pad_location 4 5] \ + {sg13g2_IOPad_io_address_2} -master sg13g2_IOPadIn # IO pin io_gpio_0 -place_pad -row IO_NORTH -location [calc_horizontal_pad_location 0 5] {sg13g2_IOPad_io_gpio_0} -master sg13g2_IOPadInOut16mA +place_pad -row IO_NORTH -location [calc_horizontal_pad_location 0 5] \ + {sg13g2_IOPad_io_gpio_0} -master sg13g2_IOPadInOut16mA # IO pin io_gpio_1 -place_pad -row IO_NORTH -location [calc_horizontal_pad_location 1 5] {sg13g2_IOPad_io_gpio_1} -master sg13g2_IOPadInOut16mA +place_pad -row IO_NORTH -location [calc_horizontal_pad_location 1 5] \ + {sg13g2_IOPad_io_gpio_1} -master sg13g2_IOPadInOut16mA # IO pin io_gpio_2 -place_pad -row IO_NORTH -location [calc_horizontal_pad_location 2 5] {sg13g2_IOPad_io_gpio_2} -master sg13g2_IOPadInOut16mA +place_pad -row IO_NORTH -location [calc_horizontal_pad_location 2 5] \ + {sg13g2_IOPad_io_gpio_2} -master sg13g2_IOPadInOut16mA # IO pin io_gpio_3 -place_pad -row IO_NORTH -location [calc_horizontal_pad_location 3 5] {sg13g2_IOPad_io_gpio_3} -master sg13g2_IOPadInOut16mA +place_pad -row IO_NORTH -location [calc_horizontal_pad_location 3 5] \ + {sg13g2_IOPad_io_gpio_3} -master sg13g2_IOPadInOut16mA # IO pin io_gpio_4 -place_pad -row IO_NORTH -location [calc_horizontal_pad_location 4 5] {sg13g2_IOPad_io_gpio_4} -master sg13g2_IOPadInOut16mA +place_pad -row IO_NORTH -location [calc_horizontal_pad_location 4 5] \ + {sg13g2_IOPad_io_gpio_4} -master sg13g2_IOPadInOut16mA # IO pin io_gpio_5 -place_pad -row IO_WEST -location [calc_vertical_pad_location 0 5] {sg13g2_IOPad_io_gpio_5} -master sg13g2_IOPadInOut16mA +place_pad -row IO_WEST -location [calc_vertical_pad_location 0 5] \ + {sg13g2_IOPad_io_gpio_5} -master sg13g2_IOPadInOut16mA # IO pin io_gpio_6 -place_pad -row IO_WEST -location [calc_vertical_pad_location 1 5] {sg13g2_IOPad_io_gpio_6} -master sg13g2_IOPadInOut16mA +place_pad -row IO_WEST -location [calc_vertical_pad_location 1 5] \ + {sg13g2_IOPad_io_gpio_6} -master sg13g2_IOPadInOut16mA # IO pin io_gpio_7 -place_pad -row IO_WEST -location [calc_vertical_pad_location 2 5] {sg13g2_IOPad_io_gpio_7} -master sg13g2_IOPadInOut16mA -place_pad -row IO_WEST -location [calc_vertical_pad_location 3 5] {sg13g2_IOPadIOVss_west_3} -master sg13g2_IOPadIOVss -place_pad -row IO_WEST -location [calc_vertical_pad_location 4 5] {sg13g2_IOPadIOVdd_west_4} -master sg13g2_IOPadIOVdd +place_pad -row IO_WEST -location [calc_vertical_pad_location 2 5] \ + {sg13g2_IOPad_io_gpio_7} -master sg13g2_IOPadInOut16mA +place_pad -row IO_WEST -location [calc_vertical_pad_location 3 5] \ + {sg13g2_IOPadIOVss_west_3} -master sg13g2_IOPadIOVss +place_pad -row IO_WEST -location [calc_vertical_pad_location 4 5] \ + {sg13g2_IOPadIOVdd_west_4} -master sg13g2_IOPadIOVdd # Place Corner Cells and Filler place_corners sg13g2_Corner diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl index 8e205d1c13..6e80d2f55e 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl @@ -26,15 +26,21 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} # stdcell grid define_pdn_grid -name {grid} -voltage_domains {CORE} -add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins -extend_to_core_ring -add_pdn_ring -grid {grid} -layers {Metal5 TopMetal1} -widths {8.0} -spacings {5.0} -core_offsets {4.5} -connect_to_pads -add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {37.8} -extend_to_core_ring -add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {2.200} -pitch {75.6} -offset {37.8} -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} \ + -followpins -extend_to_core_ring +add_pdn_ring -grid {grid} -layers {Metal5 TopMetal1} -widths {8.0} -spacings {5.0} \ + -core_offsets {4.5} -connect_to_pads +add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {37.8} \ + -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {2.200} -pitch {75.6} -offset {37.8} \ + -extend_to_core_ring add_pdn_connect -grid {grid} -layers {Metal1 Metal5} add_pdn_connect -grid {grid} -layers {Metal5 TopMetal1} add_pdn_connect -grid {grid} -layers {Metal5 TopMetal2} add_pdn_connect -grid {grid} -layers {TopMetal1 TopMetal2} -define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -cells {I2cDeviceCtrl} -grid_over_boundary +define_pdn_grid \ + -name {CORE_macro_grid_1} -voltage_domains {CORE} \ + -macro -cells {I2cDeviceCtrl} -grid_over_boundary add_pdn_connect -grid {CORE_macro_grid_1} -layers {Metal3 TopMetal1} add_pdn_connect -grid {CORE_macro_grid_1} -layers {Metal4 TopMetal1} diff --git a/flow/designs/nangate45/ariane133/io.tcl b/flow/designs/nangate45/ariane133/io.tcl index 11444dfcea..cf94350a6c 100644 --- a/flow/designs/nangate45/ariane133/io.tcl +++ b/flow/designs/nangate45/ariane133/io.tcl @@ -1 +1,2 @@ -exclude_io_pin_region -region left:0-500 -region left:1000-1500: -region right:* -region top:* -region bottom:* +exclude_io_pin_region -region left:0-500 -region left:1000-1500: -region right:* \ + -region top:* -region bottom:* diff --git a/flow/designs/nangate45/ariane136/io.tcl b/flow/designs/nangate45/ariane136/io.tcl index 11444dfcea..4de8dc3e2a 100644 --- a/flow/designs/nangate45/ariane136/io.tcl +++ b/flow/designs/nangate45/ariane136/io.tcl @@ -1 +1,6 @@ -exclude_io_pin_region -region left:0-500 -region left:1000-1500: -region right:* -region top:* -region bottom:* +exclude_io_pin_region \ + -region left:0-500 \ + -region left:1000-1500: \ + -region right:* \ + -region top:* \ + -region bottom:* diff --git a/flow/designs/nangate45/black_parrot/io.tcl b/flow/designs/nangate45/black_parrot/io.tcl index 0204afcc11..9df7874f57 100644 --- a/flow/designs/nangate45/black_parrot/io.tcl +++ b/flow/designs/nangate45/black_parrot/io.tcl @@ -1 +1,2 @@ -exclude_io_pin_region -region left:* -region right:* -region top:* -region bottom:0-100 -region bottom:1200-1350 +exclude_io_pin_region -region left:* -region right:* -region top:* \ + -region bottom:0-100 -region bottom:1200-1350 diff --git a/flow/designs/nangate45/bp_quad/io.tcl b/flow/designs/nangate45/bp_quad/io.tcl index c9e50c4b0a..41bce8db56 100644 --- a/flow/designs/nangate45/bp_quad/io.tcl +++ b/flow/designs/nangate45/bp_quad/io.tcl @@ -1 +1,2 @@ -exclude_io_pin_region -region left:* -region right:* -region top:* -region bottom:0-1000 -region bottom:2400-3600 +exclude_io_pin_region -region left:* -region right:* -region top:* \ + -region bottom:0-1000 -region bottom:2400-3600 diff --git a/flow/designs/nangate45/mempool_group/mempool_group.sdc b/flow/designs/nangate45/mempool_group/mempool_group.sdc index 3d6bf172ca..a6efdf815b 100755 --- a/flow/designs/nangate45/mempool_group/mempool_group.sdc +++ b/flow/designs/nangate45/mempool_group/mempool_group.sdc @@ -11,8 +11,10 @@ set clock_port_mempool_tile clk_i create_clock -name clk_i -period $clock_cycle [get_ports $clock_port_mempool_tile] set_clock_uncertainty $uncertainty [all_clocks] -set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==in && is_on_clock_network==false"] -set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==out && is_on_clock_network==false"] +set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay \ + [get_ports * -filter "direction==in && is_on_clock_network==false"] +set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay \ + [get_ports * -filter "direction==out && is_on_clock_network==false"] set_max_transition $maxTransition -clock_path [get_clocks clk_i] set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i] #set_propagated_clock [get_clocks clk_i] @@ -33,21 +35,29 @@ set_max_fanout $maxFanout [current_design] #set_false_path -from tile_id_i # TCDM Master -set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter { name =~ tcdm_master_.*req_.*_i}] -set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter { name =~ tcdm_master_*req_*_o}] +set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i \ + [get_ports -filter { name =~ tcdm_master_.*req_.*_i}] +set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i \ + [get_ports -filter { name =~ tcdm_master_*req_*_o}] -set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_master_*resp_*_i}] -set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_master_*resp_*_o}] +set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i \ + [get_ports -filter {name =~ tcdm_master_*resp_*_i}] +set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i \ + [get_ports -filter {name =~ tcdm_master_*resp_*_o}] # TCDM Slave -#set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*req_*_i}] -set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*req_*_o}] +#set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i \ +# [get_ports -filter {name =~ tcdm_slave_*req_*_i}] +set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i \ + [get_ports -filter {name =~ tcdm_slave_*req_*_o}] -set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*resp_*_i}] -set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*resp_*_o}] +set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i \ + [get_ports -filter {name =~ tcdm_slave_*resp_*_i}] +set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i \ + [get_ports -filter {name =~ tcdm_slave_*resp_*_o}] # Refill port -#set_input_delay [expr 0.50*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ refill_*_i}] +#set_input_delay [expr 0.50*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ refill_*_i}] #set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ refill_*_o}] # Reset diff --git a/flow/designs/nangate45/swerv_wrapper/io.tcl b/flow/designs/nangate45/swerv_wrapper/io.tcl index 5a3c212330..74f327933a 100644 --- a/flow/designs/nangate45/swerv_wrapper/io.tcl +++ b/flow/designs/nangate45/swerv_wrapper/io.tcl @@ -1 +1,2 @@ -exclude_io_pin_region -region left:* -region right:* -region top:* -region bottom:0-200 -region bottom:1000-1100 +exclude_io_pin_region -region left:* -region right:* -region top:* \ + -region bottom:0-200 -region bottom:1000-1100 diff --git a/flow/designs/sky130hd/microwatt/constraint.sdc b/flow/designs/sky130hd/microwatt/constraint.sdc index 30f2da4808..55170d5f75 100644 --- a/flow/designs/sky130hd/microwatt/constraint.sdc +++ b/flow/designs/sky130hd/microwatt/constraint.sdc @@ -52,10 +52,14 @@ set_clock_groups -name group1 -logically_exclusive \ -group [get_clocks $jtag_clk_name] \ -group [get_clocks $clk_name] -set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] -clock $jtag_clk_name [get_ports jtag_tdi] -set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] -clock $jtag_clk_name [get_ports jtag_tms] -set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] -clock $jtag_clk_name [get_ports jtag_trst] -set_output_delay [expr $jtag_clk_period * $jtag_clk_io_pct] -clock $jtag_clk_name [get_ports jtag_tdo] +set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] \ + -clock $jtag_clk_name [get_ports jtag_tdi] +set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] \ + -clock $jtag_clk_name [get_ports jtag_tms] +set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] \ + -clock $jtag_clk_name [get_ports jtag_trst] +set_output_delay [expr $jtag_clk_period * $jtag_clk_io_pct] \ + -clock $jtag_clk_name [get_ports jtag_tdo] set_max_fanout 10 [current_design] diff --git a/flow/designs/src/mock-array/util.tcl b/flow/designs/src/mock-array/util.tcl index 6f3e9624c8..a219929c6d 100644 --- a/flow/designs/src/mock-array/util.tcl +++ b/flow/designs/src/mock-array/util.tcl @@ -47,7 +47,7 @@ proc match_pins { regex { direction .* } { is_clock 0 } } { if { ![regexp $direction [get_property $pin direction]] } { continue } - if { [expr $is_clock != [sta::is_clock_src [sta::get_port_pin $pin]]] } { + if { $is_clock != [sta::is_clock_src [sta::get_port_pin $pin]] } { continue } lappend pins [get_property $pin name] diff --git a/tclint.toml b/tclint.toml index 8545a28fad..caecb46445 100644 --- a/tclint.toml +++ b/tclint.toml @@ -3,7 +3,8 @@ exclude = [ "flow/results", "flow/logs", - "flow/designs", + "flow/designs/asap7/cva6/constraint.sdc", + "flow/designs/nangate45/bp_quad/bsg_chip.sdc", "flow/platforms", "flow/scripts/*.tcl", "tools/OpenROAD", From 6dd1075d0158ce5f8d4a5ec3a10f84006d3e47d1 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Wed, 2 Jul 2025 17:38:15 +0000 Subject: [PATCH 128/198] Fix cell-veener whitespace bug concat has the weird side-effect of removing trailing whitespace. Signed-off-by: Matt Liberty --- flow/util/cell-veneer/lefdef.tcl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/flow/util/cell-veneer/lefdef.tcl b/flow/util/cell-veneer/lefdef.tcl index 27438a009c..d95a108166 100644 --- a/flow/util/cell-veneer/lefdef.tcl +++ b/flow/util/cell-veneer/lefdef.tcl @@ -768,12 +768,12 @@ proc write { design } { dict for {pin_name pin} [dict get $design pins] { out -nonewline [concat \ "- $pin_name + NET [dict get $pin net_name]" \ - "+ DIRECTION [dict get $pin direction] "] + "+ DIRECTION [dict get $pin direction]"] if { [dict exists $pin use] } { - out -nonewline "+ USE [dict get $pin use] " + out -nonewline " + USE [dict get $pin use]" } if { [dict exists $pin special] } { - out -nonewline "+ SPECIAL " + out -nonewline " + SPECIAL" } out "" if { [dict exists $pin ports] } { From 044a3ef216eb1239f573347ca8da93bf339fa8b9 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" Date: Wed, 2 Jul 2025 19:04:49 +0000 Subject: [PATCH 129/198] flow: update rules Signed-off-by: github-actions[bot] --- flow/designs/ihp-sg13g2/aes/rules-base.json | 2 +- flow/designs/ihp-sg13g2/jpeg/rules-base.json | 2 +- flow/designs/nangate45/bp_fe_top/rules-base.json | 2 +- flow/designs/sky130hd/gcd/rules-base.json | 4 ++-- flow/designs/sky130hd/riscv32i/rules-base.json | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/flow/designs/ihp-sg13g2/aes/rules-base.json b/flow/designs/ihp-sg13g2/aes/rules-base.json index c0dbd17b30..39d01ef6cf 100644 --- a/flow/designs/ihp-sg13g2/aes/rules-base.json +++ b/flow/designs/ihp-sg13g2/aes/rules-base.json @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 5, + "value": 12, "compare": "<=" }, "finish__timing__setup__ws": { diff --git a/flow/designs/ihp-sg13g2/jpeg/rules-base.json b/flow/designs/ihp-sg13g2/jpeg/rules-base.json index 913c3fa3c8..115f3ccc12 100644 --- a/flow/designs/ihp-sg13g2/jpeg/rules-base.json +++ b/flow/designs/ihp-sg13g2/jpeg/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 4, + "value": 12, "compare": "<=" }, "detailedroute__route__wirelength": { diff --git a/flow/designs/nangate45/bp_fe_top/rules-base.json b/flow/designs/nangate45/bp_fe_top/rules-base.json index c5bec52251..8ae464c9af 100644 --- a/flow/designs/nangate45/bp_fe_top/rules-base.json +++ b/flow/designs/nangate45/bp_fe_top/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.12, + "value": -0.21, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/sky130hd/gcd/rules-base.json b/flow/designs/sky130hd/gcd/rules-base.json index eda2d1a286..68014abc69 100644 --- a/flow/designs/sky130hd/gcd/rules-base.json +++ b/flow/designs/sky130hd/gcd/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 9752, + "value": 11675, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 81, + "value": 86, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/sky130hd/riscv32i/rules-base.json b/flow/designs/sky130hd/riscv32i/rules-base.json index c1df764f6c..ac2c4c89f9 100644 --- a/flow/designs/sky130hd/riscv32i/rules-base.json +++ b/flow/designs/sky130hd/riscv32i/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 10, + "value": 20, "compare": "<=" }, "detailedroute__route__wirelength": { From 47750e19809addd3e97e7e178f9bb2dd51979a0f Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Wed, 2 Jul 2025 20:53:51 +0000 Subject: [PATCH 130/198] Fix cell-veneer again - just remove the problematic concats Signed-off-by: Matt Liberty --- flow/util/cell-veneer/lefdef.tcl | 56 +++++++++++++++----------------- 1 file changed, 26 insertions(+), 30 deletions(-) diff --git a/flow/util/cell-veneer/lefdef.tcl b/flow/util/cell-veneer/lefdef.tcl index d95a108166..901fd13706 100644 --- a/flow/util/cell-veneer/lefdef.tcl +++ b/flow/util/cell-veneer/lefdef.tcl @@ -312,9 +312,8 @@ proc write { design } { out " ORIGIN 0.0 0.0 ;" } out " FOREIGN [dict get $design foreign ref] [dict get $design foreign origin] ;" - out [concat \ - " SIZE [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units]" \ - " BY [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units] ;"] + out " SIZE [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units]\ + BY [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units] ;" out " SYMMETRY [dict get $design symmetry] ;" if { [dict exists $design site] } { out " SITE [dict get $design site] ;" @@ -344,10 +343,10 @@ proc write { design } { set rect [absolute_rectangle [dict get $shape rect] $offset] if { [dict exists $shape mask] } { - out [concat \ - " RECT MASK [dict get $shape mask]" \ - " [lmap x $rect { expr { 1.0 * $x / $def_units } }]" \ - " ;"] + out \ + " RECT MASK [dict get $shape mask]\ + [lmap x $rect { expr { 1.0 * $x / $def_units } }] \ + ;" } else { out " RECT [lmap x $rect { expr 1.0 * $x / $def_units }] ;" } @@ -383,10 +382,9 @@ proc write { design } { out " LAYER $layer_name ;" foreach obs $obstructions { if { [dict exists $obs mask] } { - out [concat \ - " RECT MASK [dict get $obs mask]" \ - " [lmap x [dict get $obs rect] { expr { 1.0 * $x / $def_units } }]" \ - " ;"] + out " RECT MASK [dict get $obs mask]\ + [lmap x [dict get $obs rect] { expr { 1.0 * $x / $def_units } }] + ;" } else { out " RECT [lmap x [dict get $obs rect] { expr 1.0 * $x / $def_units }] ;" } @@ -740,9 +738,8 @@ proc write { design } { } out "" - out [concat \ - "DIEAREA ( [lrange [dict get $design die_area] 0 1] )" \ - " ( [lrange [dict get $design die_area] 2 3] ) ;"] + out "DIEAREA ( [lrange [dict get $design die_area] 0 1] )\ + ( [lrange [dict get $design die_area] 2 3] ) ;" if { [dict exists $design tracks] } { @@ -756,9 +753,8 @@ proc write { design } { [dict get $design rows $idx start] \ [dict get $design rows $idx height] \ [dict get $design rows $idx orientation]] - out [concat \ - " DO [dict get $design rows $idx num_sites] BY 1 STEP " \ - "[dict get $design rows $idx site_width] 0 ;"] + out " DO [dict get $design rows $idx num_sites] BY 1 STEP\ + [dict get $design rows $idx site_width] 0 ;" } } @@ -766,9 +762,9 @@ proc write { design } { out "" out "PINS [dict size [dict get $design pins]] ;" dict for {pin_name pin} [dict get $design pins] { - out -nonewline [concat \ - "- $pin_name + NET [dict get $pin net_name]" \ - "+ DIRECTION [dict get $pin direction]"] + out -nonewline \ + "- $pin_name + NET [dict get $pin net_name]\ + + DIRECTION [dict get $pin direction]" if { [dict exists $pin use] } { out -nonewline " + USE [dict get $pin use]" } @@ -866,9 +862,9 @@ proc write { design } { set mask "" } if { [llength $point] == 2 } { - out -nonewline [concat \ - " + $type [dict get $route layer] " \ - "[get_line_width [dict get $route layer] [list $first_point $point]] "] + out -nonewline \ + " + $type [dict get $route layer]\ + [get_line_width [dict get $route layer] [list $first_point $point]] " out -nonewline $shape out -nonewline $points out -nonewline $mask @@ -899,19 +895,19 @@ proc write { design } { } if { [dict exists $net routes] } { set route [lindex [dict get $net routes] 0] - out -nonewline [concat \ - " + ROUTED [dict get $route layer] " \ - "[expr round([dict get $route width])] " \ - "+ SHAPE [dict get $route shape] "] + out -nonewline \ + " + ROUTED [dict get $route layer]\ + [expr round([dict get $route width])]\ + + SHAPE [dict get $route shape] " foreach point [dict get $route points] { out -nonewline " $point" } out "" foreach route [lrange [dict get $net routes] 1 end] { - out [concat \ - " NEW [dict get $route layer] [expr round([dict get $route width])]" \ - "+ SHAPE [dict get $route shape] "] + out \ + " NEW [dict get $route layer] [expr round([dict get $route width])]\ + + SHAPE [dict get $route shape] " foreach point [dict get $route points] { out -nonewline " $point" } From 60540dc3288c494c190193546886d51d12b1c0ef Mon Sep 17 00:00:00 2001 From: Sombrio Date: Wed, 2 Jul 2025 18:04:30 -0300 Subject: [PATCH 131/198] feat(workflows): use venv for python dependencies Isolates Python dependencies within a virtual environment for all GitHub Actions workflows. This prevents conflicts with system-wide packages and ensures a consistent, reproducible environment for CI/CD processes. - Replaces all 'pip install' commands with a 'venv' setup. - Simplifies 'pip' commands by removing unnecessary flags. - Adds 'venv/' to '.gitignore' to exclude virtual environment directories from source control. Signed-off-by: Sombrio --- .github/workflows/github-actions-lint-tcl.yml | 4 +++- .github/workflows/github-actions-manual-update-rules.yml | 2 ++ .github/workflows/github-actions-update-rules.yml | 2 ++ .github/workflows/github-actions-yaml-test.yml | 2 ++ .gitignore | 4 +++- 5 files changed, 12 insertions(+), 2 deletions(-) diff --git a/.github/workflows/github-actions-lint-tcl.yml b/.github/workflows/github-actions-lint-tcl.yml index 5e52158e62..3ac7fc446d 100644 --- a/.github/workflows/github-actions-lint-tcl.yml +++ b/.github/workflows/github-actions-lint-tcl.yml @@ -17,7 +17,9 @@ jobs: - name: Install Dependencies run: | - python3 -m pip install -U --user tclint==0.4.2 + python3 -m venv ./venv + source ./venv/bin/activate + pip install tclint==0.4.2 - name: Lint run: | diff --git a/.github/workflows/github-actions-manual-update-rules.yml b/.github/workflows/github-actions-manual-update-rules.yml index 2bc2e02d22..3394dd2b0f 100644 --- a/.github/workflows/github-actions-manual-update-rules.yml +++ b/.github/workflows/github-actions-manual-update-rules.yml @@ -22,6 +22,8 @@ jobs: python-version: "3.10" - name: Install Python Packages run: | + python3 -m venv ./venv + source ./venv/bin/activate pip install firebase-admin - name: Execute Python Script Update env: diff --git a/.github/workflows/github-actions-update-rules.yml b/.github/workflows/github-actions-update-rules.yml index 83e4b4208b..b7594ce8a6 100644 --- a/.github/workflows/github-actions-update-rules.yml +++ b/.github/workflows/github-actions-update-rules.yml @@ -24,6 +24,8 @@ jobs: python-version: "3.10" - name: Install Python Packages run: | + python3 -m venv ./venv + source ./venv/bin/activate pip install firebase-admin - name: Execute Python Script Update env: diff --git a/.github/workflows/github-actions-yaml-test.yml b/.github/workflows/github-actions-yaml-test.yml index 51cec64329..e69039c7d3 100644 --- a/.github/workflows/github-actions-yaml-test.yml +++ b/.github/workflows/github-actions-yaml-test.yml @@ -25,6 +25,8 @@ jobs: git diff --exit-code docs/user/FlowVariables.md - name: Run yamlfix check run: | + python3 -m venv ./venv + source ./venv/bin/activate pip install --quiet yamlfix==1.17.0 yamlfix --version set -x diff --git a/.gitignore b/.gitignore index 06388121d6..37ebf3fa79 100644 --- a/.gitignore +++ b/.gitignore @@ -29,7 +29,6 @@ flow/rc_model.bin flow/*.tif.gz flow/*.def.v - # RePlAce deps *PORT9.dat *POST9.dat @@ -103,3 +102,6 @@ bazel-bin bazel-out bazel-OpenROAD-flow-scripts bazel-testlogs + +# python venv +venv/ From af2504295047956779036593ad844dbac9f5d026 Mon Sep 17 00:00:00 2001 From: Sombrio Date: Wed, 2 Jul 2025 18:45:55 -0300 Subject: [PATCH 132/198] fixed venv sourcing Signed-off-by: Sombrio --- .github/workflows/github-actions-lint-tcl.yml | 6 +++--- .github/workflows/github-actions-manual-update-rules.yml | 6 +++--- .github/workflows/github-actions-update-rules.yml | 6 +++--- .github/workflows/github-actions-yaml-test.yml | 8 +++++--- 4 files changed, 14 insertions(+), 12 deletions(-) diff --git a/.github/workflows/github-actions-lint-tcl.yml b/.github/workflows/github-actions-lint-tcl.yml index 3ac7fc446d..0399b50831 100644 --- a/.github/workflows/github-actions-lint-tcl.yml +++ b/.github/workflows/github-actions-lint-tcl.yml @@ -17,12 +17,12 @@ jobs: - name: Install Dependencies run: | - python3 -m venv ./venv - source ./venv/bin/activate - pip install tclint==0.4.2 + python3 -m venv venv + venv/bin/pip install tclint==0.4.2 - name: Lint run: | + source venv/bin/activate tclfmt --version tclfmt --in-place . git diff --exit-code diff --git a/.github/workflows/github-actions-manual-update-rules.yml b/.github/workflows/github-actions-manual-update-rules.yml index 3394dd2b0f..cdcf2744e2 100644 --- a/.github/workflows/github-actions-manual-update-rules.yml +++ b/.github/workflows/github-actions-manual-update-rules.yml @@ -22,14 +22,14 @@ jobs: python-version: "3.10" - name: Install Python Packages run: | - python3 -m venv ./venv - source ./venv/bin/activate - pip install firebase-admin + python3 -m venv venv + venv/bin/pip install firebase-admin - name: Execute Python Script Update env: CREDS_FILE: ${{ secrets.CREDS_FILE }} API_BASE_URL: ${{ secrets.API_BASE_URL }} run: | + source venv/bin/activate if [[ "${{ github.event.inputs.type }}" == "overwrite" ]]; then python flow/util/updateRules.py --keyFile "${CREDS_FILE}" --apiURL ${API_BASE_URL} --commitSHA $(git rev-parse HEAD) --overwrite else diff --git a/.github/workflows/github-actions-update-rules.yml b/.github/workflows/github-actions-update-rules.yml index b7594ce8a6..3355612ba5 100644 --- a/.github/workflows/github-actions-update-rules.yml +++ b/.github/workflows/github-actions-update-rules.yml @@ -24,14 +24,14 @@ jobs: python-version: "3.10" - name: Install Python Packages run: | - python3 -m venv ./venv - source ./venv/bin/activate - pip install firebase-admin + python3 -m venv venv + venv/bin/pip install firebase-admin - name: Execute Python Script Update env: CREDS_FILE: ${{ secrets.CREDS_FILE }} API_BASE_URL: ${{ secrets.API_BASE_URL }} run: | + source ./venv/bin/activate echo ${{ github.event_name }} echo ${{ github.event.client_payload.type }} if [[ "${{ github.event_name }}" == "repository_dispatch" && "${{ github.event.client_payload.type }}" == "overwrite" ]]; then diff --git a/.github/workflows/github-actions-yaml-test.yml b/.github/workflows/github-actions-yaml-test.yml index e69039c7d3..704f34ab78 100644 --- a/.github/workflows/github-actions-yaml-test.yml +++ b/.github/workflows/github-actions-yaml-test.yml @@ -23,11 +23,13 @@ jobs: - name: Check if FlowVariables.md is up to date run: | git diff --exit-code docs/user/FlowVariables.md + - name: Install dependencies + run: | + python3 -m venv venv + venv/bin/pip install --quiet yamlfix==1.17.0 - name: Run yamlfix check run: | - python3 -m venv ./venv - source ./venv/bin/activate - pip install --quiet yamlfix==1.17.0 + source venv/bin/activate yamlfix --version set -x yamlfix -c yamlfix.toml flow/scripts/variables.yaml From 9ae833013550a17feb511f88a686692f8b3bb4db Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Wed, 2 Jul 2025 23:31:11 +0000 Subject: [PATCH 133/198] Update nangate45/ariane136 metrics | Metric | Old | New | Type | | ------ | --- | --- | ---- | | finish__timing__drv__hold_violation_count | 106 | 292 | Failing | Signed-off-by: Matt Liberty --- flow/designs/nangate45/ariane136/rules-base.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/flow/designs/nangate45/ariane136/rules-base.json b/flow/designs/nangate45/ariane136/rules-base.json index 8f69cae835..d692880787 100644 --- a/flow/designs/nangate45/ariane136/rules-base.json +++ b/flow/designs/nangate45/ariane136/rules-base.json @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 106, + "value": 292, "compare": "<=" }, "finish__timing__wns_percent_delay": { From f99cbd6384c63e4817cbfc66ff815b98034c1fe4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 4 Jul 2025 09:13:47 +0200 Subject: [PATCH 134/198] sdc: simplify MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/designs/asap7/aes-block/constraint.sdc | 2 +- flow/designs/asap7/aes-mbff/constraint.sdc | 2 +- flow/designs/asap7/aes/constraint.sdc | 2 +- flow/designs/asap7/aes_lvt/constraint.sdc | 2 +- flow/designs/asap7/ethmac/constraint.sdc | 2 +- flow/designs/asap7/ethmac_lvt/constraint.sdc | 2 +- flow/designs/asap7/gcd/constraint.sdc | 2 +- flow/designs/asap7/ibex/constraint.sdc | 2 +- flow/designs/asap7/ibex/constraint_pos_slack.sdc | 2 +- flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc | 2 +- flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc | 2 +- flow/designs/asap7/mock-alu/constraints.sdc | 2 +- flow/designs/asap7/riscv32i/constraint.sdc | 2 +- flow/designs/asap7/swerv_wrapper/constraint.sdc | 2 +- flow/designs/asap7/uart/constraint.sdc | 2 +- flow/designs/gf12/aes/constraint.sdc | 2 +- flow/designs/gf12/gcd/constraint.sdc | 2 +- flow/designs/gf12/ibex/constraint.sdc | 2 +- flow/designs/gf12/jpeg/constraint.sdc | 2 +- flow/designs/gf12/tinyRocket/constraint.sdc | 2 +- flow/designs/gf180/aes/constraint.sdc | 2 +- flow/designs/gf180/ibex/constraint.sdc | 2 +- flow/designs/gf180/jpeg/constraint.sdc | 2 +- flow/designs/gf180/riscv32i/constraint.sdc | 2 +- flow/designs/gf180/uart-blocks/constraint.sdc | 2 +- flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc | 2 +- flow/designs/ihp-sg13g2/aes/constraint.sdc | 2 +- flow/designs/ihp-sg13g2/gcd/constraint.sdc | 2 +- flow/designs/ihp-sg13g2/ibex/constraint.sdc | 2 +- flow/designs/ihp-sg13g2/jpeg/constraint.sdc | 2 +- flow/designs/ihp-sg13g2/spi/constraint.sdc | 2 +- flow/designs/nangate45/aes/constraint.sdc | 2 +- flow/designs/nangate45/gcd/constraint.sdc | 2 +- flow/designs/nangate45/ibex/constraint.sdc | 2 +- flow/designs/nangate45/jpeg/constraint.sdc | 2 +- flow/designs/nangate45/swerv/constraint.sdc | 2 +- flow/designs/nangate45/swerv_wrapper/constraint.sdc | 2 +- flow/designs/sky130hd/aes/constraint.sdc | 2 +- flow/designs/sky130hd/chameleon/constraint.sdc | 2 +- flow/designs/sky130hd/gcd/constraint.sdc | 2 +- flow/designs/sky130hd/ibex/constraint.sdc | 2 +- flow/designs/sky130hd/jpeg/constraint.sdc | 2 +- flow/designs/sky130hs/aes/constraint.sdc | 2 +- flow/designs/sky130hs/gcd/constraint.sdc | 2 +- flow/designs/sky130hs/ibex/constraint.sdc | 2 +- flow/designs/sky130hs/jpeg/constraint.sdc | 2 +- flow/platforms/asap7/constraints.sdc | 2 +- 47 files changed, 47 insertions(+), 47 deletions(-) diff --git a/flow/designs/asap7/aes-block/constraint.sdc b/flow/designs/asap7/aes-block/constraint.sdc index 8256fd752b..8d7d7c5987 100644 --- a/flow/designs/asap7/aes-block/constraint.sdc +++ b/flow/designs/asap7/aes-block/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/aes-mbff/constraint.sdc b/flow/designs/asap7/aes-mbff/constraint.sdc index f5bce962e5..a9b5a65d9c 100644 --- a/flow/designs/asap7/aes-mbff/constraint.sdc +++ b/flow/designs/asap7/aes-mbff/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/aes/constraint.sdc b/flow/designs/asap7/aes/constraint.sdc index f5bce962e5..a9b5a65d9c 100644 --- a/flow/designs/asap7/aes/constraint.sdc +++ b/flow/designs/asap7/aes/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/aes_lvt/constraint.sdc b/flow/designs/asap7/aes_lvt/constraint.sdc index f5bce962e5..a9b5a65d9c 100644 --- a/flow/designs/asap7/aes_lvt/constraint.sdc +++ b/flow/designs/asap7/aes_lvt/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/ethmac/constraint.sdc b/flow/designs/asap7/ethmac/constraint.sdc index 43759e0718..1dd0000a50 100644 --- a/flow/designs/asap7/ethmac/constraint.sdc +++ b/flow/designs/asap7/ethmac/constraint.sdc @@ -3,7 +3,7 @@ set clk_period 1000 set clk_io_pct 0.2 set clk_port [get_ports $top_clk_name] create_clock -name $top_clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs] diff --git a/flow/designs/asap7/ethmac_lvt/constraint.sdc b/flow/designs/asap7/ethmac_lvt/constraint.sdc index 6d59823cb6..465d603d0c 100644 --- a/flow/designs/asap7/ethmac_lvt/constraint.sdc +++ b/flow/designs/asap7/ethmac_lvt/constraint.sdc @@ -3,7 +3,7 @@ set clk_period 1000 set clk_io_pct 0.2 set clk_port [get_ports $top_clk_name] create_clock -name $top_clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs] diff --git a/flow/designs/asap7/gcd/constraint.sdc b/flow/designs/asap7/gcd/constraint.sdc index dc5d070adf..27de11250b 100644 --- a/flow/designs/asap7/gcd/constraint.sdc +++ b/flow/designs/asap7/gcd/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/ibex/constraint.sdc b/flow/designs/asap7/ibex/constraint.sdc index 956a60e40e..30bb0a2292 100644 --- a/flow/designs/asap7/ibex/constraint.sdc +++ b/flow/designs/asap7/ibex/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/ibex/constraint_pos_slack.sdc b/flow/designs/asap7/ibex/constraint_pos_slack.sdc index 0627af5b19..d605a5aa8e 100644 --- a/flow/designs/asap7/ibex/constraint_pos_slack.sdc +++ b/flow/designs/asap7/ibex/constraint_pos_slack.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc index 3800daaf8b..bd163e05ff 100644 --- a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc +++ b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc index 2e77403245..d1aa7a70f9 100644 --- a/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc +++ b/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/mock-alu/constraints.sdc b/flow/designs/asap7/mock-alu/constraints.sdc index 66d1e5725e..dd93e54e87 100644 --- a/flow/designs/asap7/mock-alu/constraints.sdc +++ b/flow/designs/asap7/mock-alu/constraints.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * 0.7] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/riscv32i/constraint.sdc b/flow/designs/asap7/riscv32i/constraint.sdc index 3cea613851..9868986799 100644 --- a/flow/designs/asap7/riscv32i/constraint.sdc +++ b/flow/designs/asap7/riscv32i/constraint.sdc @@ -9,6 +9,6 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/swerv_wrapper/constraint.sdc b/flow/designs/asap7/swerv_wrapper/constraint.sdc index 955b0805d5..2cae11c882 100644 --- a/flow/designs/asap7/swerv_wrapper/constraint.sdc +++ b/flow/designs/asap7/swerv_wrapper/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/uart/constraint.sdc b/flow/designs/asap7/uart/constraint.sdc index 0d7aa226f0..b58ae3408f 100644 --- a/flow/designs/asap7/uart/constraint.sdc +++ b/flow/designs/asap7/uart/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf12/aes/constraint.sdc b/flow/designs/gf12/aes/constraint.sdc index ae1bc48d58..a820710ab4 100644 --- a/flow/designs/gf12/aes/constraint.sdc +++ b/flow/designs/gf12/aes/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf12/gcd/constraint.sdc b/flow/designs/gf12/gcd/constraint.sdc index 18fe09d581..d7ee23ad0a 100644 --- a/flow/designs/gf12/gcd/constraint.sdc +++ b/flow/designs/gf12/gcd/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf12/ibex/constraint.sdc b/flow/designs/gf12/ibex/constraint.sdc index 3d19120721..85d691d76e 100644 --- a/flow/designs/gf12/ibex/constraint.sdc +++ b/flow/designs/gf12/ibex/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf12/jpeg/constraint.sdc b/flow/designs/gf12/jpeg/constraint.sdc index d196f8f423..9e32a57bf1 100644 --- a/flow/designs/gf12/jpeg/constraint.sdc +++ b/flow/designs/gf12/jpeg/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf12/tinyRocket/constraint.sdc b/flow/designs/gf12/tinyRocket/constraint.sdc index 02e8f6f066..79e26f0bee 100644 --- a/flow/designs/gf12/tinyRocket/constraint.sdc +++ b/flow/designs/gf12/tinyRocket/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/aes/constraint.sdc b/flow/designs/gf180/aes/constraint.sdc index da8e0a8244..9efd6867db 100644 --- a/flow/designs/gf180/aes/constraint.sdc +++ b/flow/designs/gf180/aes/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/ibex/constraint.sdc b/flow/designs/gf180/ibex/constraint.sdc index d91411c4dc..24711119f1 100644 --- a/flow/designs/gf180/ibex/constraint.sdc +++ b/flow/designs/gf180/ibex/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/jpeg/constraint.sdc b/flow/designs/gf180/jpeg/constraint.sdc index 5862d8ce02..42d6b4abf9 100644 --- a/flow/designs/gf180/jpeg/constraint.sdc +++ b/flow/designs/gf180/jpeg/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/riscv32i/constraint.sdc b/flow/designs/gf180/riscv32i/constraint.sdc index e38107b41f..3b2184da75 100644 --- a/flow/designs/gf180/riscv32i/constraint.sdc +++ b/flow/designs/gf180/riscv32i/constraint.sdc @@ -7,6 +7,6 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/uart-blocks/constraint.sdc b/flow/designs/gf180/uart-blocks/constraint.sdc index 5c231242df..e4bcee59d1 100644 --- a/flow/designs/gf180/uart-blocks/constraint.sdc +++ b/flow/designs/gf180/uart-blocks/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc b/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc index 5c231242df..e4bcee59d1 100644 --- a/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc +++ b/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/aes/constraint.sdc b/flow/designs/ihp-sg13g2/aes/constraint.sdc index f32c9be836..f0b3b99355 100644 --- a/flow/designs/ihp-sg13g2/aes/constraint.sdc +++ b/flow/designs/ihp-sg13g2/aes/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/gcd/constraint.sdc b/flow/designs/ihp-sg13g2/gcd/constraint.sdc index 20c0c7a73e..0c1e6d1d5b 100644 --- a/flow/designs/ihp-sg13g2/gcd/constraint.sdc +++ b/flow/designs/ihp-sg13g2/gcd/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/ibex/constraint.sdc b/flow/designs/ihp-sg13g2/ibex/constraint.sdc index 979e0b0b28..fed426995f 100644 --- a/flow/designs/ihp-sg13g2/ibex/constraint.sdc +++ b/flow/designs/ihp-sg13g2/ibex/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/jpeg/constraint.sdc b/flow/designs/ihp-sg13g2/jpeg/constraint.sdc index 923cf1199f..0ca3cc5b3d 100644 --- a/flow/designs/ihp-sg13g2/jpeg/constraint.sdc +++ b/flow/designs/ihp-sg13g2/jpeg/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/spi/constraint.sdc b/flow/designs/ihp-sg13g2/spi/constraint.sdc index 225f73938c..956369e4b8 100644 --- a/flow/designs/ihp-sg13g2/spi/constraint.sdc +++ b/flow/designs/ihp-sg13g2/spi/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/aes/constraint.sdc b/flow/designs/nangate45/aes/constraint.sdc index d7b8414c8e..95f709e341 100644 --- a/flow/designs/nangate45/aes/constraint.sdc +++ b/flow/designs/nangate45/aes/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/gcd/constraint.sdc b/flow/designs/nangate45/gcd/constraint.sdc index 852fef6395..c6d4b902be 100644 --- a/flow/designs/nangate45/gcd/constraint.sdc +++ b/flow/designs/nangate45/gcd/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/ibex/constraint.sdc b/flow/designs/nangate45/ibex/constraint.sdc index 210d591716..38667319ac 100644 --- a/flow/designs/nangate45/ibex/constraint.sdc +++ b/flow/designs/nangate45/ibex/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/jpeg/constraint.sdc b/flow/designs/nangate45/jpeg/constraint.sdc index 4548cad10c..7c97d6490a 100644 --- a/flow/designs/nangate45/jpeg/constraint.sdc +++ b/flow/designs/nangate45/jpeg/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/swerv/constraint.sdc b/flow/designs/nangate45/swerv/constraint.sdc index be7426a1a2..ccaab11ddf 100644 --- a/flow/designs/nangate45/swerv/constraint.sdc +++ b/flow/designs/nangate45/swerv/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/swerv_wrapper/constraint.sdc b/flow/designs/nangate45/swerv_wrapper/constraint.sdc index 4ccc054acb..f7c9f08b64 100644 --- a/flow/designs/nangate45/swerv_wrapper/constraint.sdc +++ b/flow/designs/nangate45/swerv_wrapper/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/aes/constraint.sdc b/flow/designs/sky130hd/aes/constraint.sdc index f32c9be836..f0b3b99355 100644 --- a/flow/designs/sky130hd/aes/constraint.sdc +++ b/flow/designs/sky130hd/aes/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/chameleon/constraint.sdc b/flow/designs/sky130hd/chameleon/constraint.sdc index da65f16f66..d3a0d6df47 100644 --- a/flow/designs/sky130hd/chameleon/constraint.sdc +++ b/flow/designs/sky130hd/chameleon/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/gcd/constraint.sdc b/flow/designs/sky130hd/gcd/constraint.sdc index d3fcca89a9..fadfedd028 100644 --- a/flow/designs/sky130hd/gcd/constraint.sdc +++ b/flow/designs/sky130hd/gcd/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/ibex/constraint.sdc b/flow/designs/sky130hd/ibex/constraint.sdc index 979e0b0b28..fed426995f 100644 --- a/flow/designs/sky130hd/ibex/constraint.sdc +++ b/flow/designs/sky130hd/ibex/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/jpeg/constraint.sdc b/flow/designs/sky130hd/jpeg/constraint.sdc index 5ac34a1acf..5d9b007f0e 100644 --- a/flow/designs/sky130hd/jpeg/constraint.sdc +++ b/flow/designs/sky130hd/jpeg/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/aes/constraint.sdc b/flow/designs/sky130hs/aes/constraint.sdc index f99ac98b46..5878fa7782 100644 --- a/flow/designs/sky130hs/aes/constraint.sdc +++ b/flow/designs/sky130hs/aes/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/gcd/constraint.sdc b/flow/designs/sky130hs/gcd/constraint.sdc index 71ddb64d28..ed93d8a1eb 100644 --- a/flow/designs/sky130hs/gcd/constraint.sdc +++ b/flow/designs/sky130hs/gcd/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/ibex/constraint.sdc b/flow/designs/sky130hs/ibex/constraint.sdc index a844a0dba6..9927412616 100644 --- a/flow/designs/sky130hs/ibex/constraint.sdc +++ b/flow/designs/sky130hs/ibex/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/jpeg/constraint.sdc b/flow/designs/sky130hs/jpeg/constraint.sdc index d150e21e15..4c40fe5a3f 100644 --- a/flow/designs/sky130hs/jpeg/constraint.sdc +++ b/flow/designs/sky130hs/jpeg/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/platforms/asap7/constraints.sdc b/flow/platforms/asap7/constraints.sdc index b08b9fa596..db9965aba7 100644 --- a/flow/platforms/asap7/constraints.sdc +++ b/flow/platforms/asap7/constraints.sdc @@ -69,7 +69,7 @@ set sdc_version 2.0 set clk_port [get_ports $clk_port_name] create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port -set non_clk_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clk_inputs [all_inputs -no_clocks] set all_register_outputs [get_pins -of_objects [all_registers] -filter {direction == output}] # Optimization targets: overconstrain by default and From 8b5ee4bbc13f0b525631ab50a59b8a28711b617e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 4 Jul 2025 09:18:17 +0200 Subject: [PATCH 135/198] sdc: fix invalid start point for path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/platforms/asap7/constraints.sdc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/flow/platforms/asap7/constraints.sdc b/flow/platforms/asap7/constraints.sdc index db9965aba7..f222d12ce3 100644 --- a/flow/platforms/asap7/constraints.sdc +++ b/flow/platforms/asap7/constraints.sdc @@ -70,7 +70,6 @@ set clk_port [get_ports $clk_port_name] create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port set non_clk_inputs [all_inputs -no_clocks] -set all_register_outputs [get_pins -of_objects [all_registers] -filter {direction == output}] # Optimization targets: overconstrain by default and # leave refinements to a more design specific constraints.sdc file. @@ -78,7 +77,7 @@ set all_register_outputs [get_pins -of_objects [all_registers] -filter {directio # Minimum time for io-io, io-reg, reg-io paths in macro is on # the order of 80ps for a small macro on ASAP7. set_max_delay [expr { [info exists in2reg_max] ? $in2reg_max : 80 }] -from $non_clk_inputs -to [all_registers] -set_max_delay [expr { [info exists reg2out_max] ? $reg2out_max : 80 }] -from $all_register_outputs -to [all_outputs] +set_max_delay [expr { [info exists reg2out_max] ? $reg2out_max : 80 }] -from [all_registers] -to [all_outputs] set_max_delay [expr { [info exists in2out_max] ? $in2out_max : 80 }] -from $non_clk_inputs -to [all_outputs] # This allows us to view the different groups From 2688092b3ac2ba6e602603a2630b9429eb1f030b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 4 Jul 2025 16:55:29 +0200 Subject: [PATCH 136/198] sdc: update mock-array rules-base.json MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/designs/asap7/mock-array/rules-base.json | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/flow/designs/asap7/mock-array/rules-base.json b/flow/designs/asap7/mock-array/rules-base.json index f11664d7bf..6073606041 100644 --- a/flow/designs/asap7/mock-array/rules-base.json +++ b/flow/designs/asap7/mock-array/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": 0.0, + "value": -440.47, "compare": ">=" }, "finish__design__instance__area": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 536, + "value": 605, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -10.0, + "value": -111.1, "compare": ">=" } } \ No newline at end of file From ce7b2804dffb9fe7d78f6ee59fe5c7b0e8b34e90 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 16 Jun 2025 17:11:33 +0200 Subject: [PATCH 137/198] Bump yosys-slang MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- tools/yosys-slang | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/yosys-slang b/tools/yosys-slang index 25540d82e3..9d9ce7b767 160000 --- a/tools/yosys-slang +++ b/tools/yosys-slang @@ -1 +1 @@ -Subproject commit 25540d82e35d1478b453670b752001cb1f5b1ef6 +Subproject commit 9d9ce7b767d2ea776e2dee0ef636a84512e6b229 From 40693351477969a340f0dc86817c08214fd155ca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 4 Jul 2025 22:40:46 +0200 Subject: [PATCH 138/198] make: print-ISSUE_VARIABLES now works MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/scripts/variables.mk | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/flow/scripts/variables.mk b/flow/scripts/variables.mk index 3f0ea97c3f..e7bc8ded86 100644 --- a/flow/scripts/variables.mk +++ b/flow/scripts/variables.mk @@ -214,4 +214,8 @@ vars: .PHONY: print-% # Print any variable, for instance: make print-DIE_AREA -print-% : ; @echo "$* = $($*)" +print-%: + $(file >$(OBJECTS_DIR)/print_tmp_$$,$($*)) + @echo -n "$* = " + @cat $(OBJECTS_DIR)/print_tmp_$$ + @rm $(OBJECTS_DIR)/print_tmp_$$ From 591fc4884baed0aa1fa3a8f4a486343d226cf089 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 4 Jul 2025 22:41:59 +0200 Subject: [PATCH 139/198] make: make vars/issue fix MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The name of the variable is what comes before the first, not the last '=' char Fixes make DESIGN_CONFIG=designs/asap7/mock-array/config.mk vars, for instance, because MAKEFLAGS is not excluded from vars.sh generated. Signed-off-by: Øyvind Harboe --- flow/util/generate-vars.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/flow/util/generate-vars.sh b/flow/util/generate-vars.sh index 0c5a04b5d5..a80c0d1312 100755 --- a/flow/util/generate-vars.sh +++ b/flow/util/generate-vars.sh @@ -22,7 +22,7 @@ while read -r VAR; do # they are invalid in shell continue fi - name="${VAR%=*}" + name="${VAR%%=*}" value="${VAR#*=}" if [[ "${name}" =~ ^[[:digit:]] ]] ; then # skip if the name starts with a number From 73148f3c8dabbbf9d068191dbcc6ed3541ccb1b2 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" Date: Sat, 5 Jul 2025 15:05:26 +0000 Subject: [PATCH 140/198] flow: update rules Signed-off-by: github-actions[bot] --- flow/designs/gf180/ibex/rules-base.json | 2 +- flow/designs/ihp-sg13g2/ibex/rules-base.json | 2 +- flow/designs/sky130hd/ibex/rules-base.json | 2 +- flow/designs/sky130hs/ibex/rules-base.json | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/flow/designs/gf180/ibex/rules-base.json b/flow/designs/gf180/ibex/rules-base.json index 9f50f9890d..87f7efb191 100644 --- a/flow/designs/gf180/ibex/rules-base.json +++ b/flow/designs/gf180/ibex/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 0, + "value": 2, "compare": "<=" }, "detailedroute__route__wirelength": { diff --git a/flow/designs/ihp-sg13g2/ibex/rules-base.json b/flow/designs/ihp-sg13g2/ibex/rules-base.json index 36f121e565..5b12a715ff 100644 --- a/flow/designs/ihp-sg13g2/ibex/rules-base.json +++ b/flow/designs/ihp-sg13g2/ibex/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 3, + "value": 21, "compare": "<=" }, "detailedroute__route__wirelength": { diff --git a/flow/designs/sky130hd/ibex/rules-base.json b/flow/designs/sky130hd/ibex/rules-base.json index 9176116e5a..c90e9cb8fd 100644 --- a/flow/designs/sky130hd/ibex/rules-base.json +++ b/flow/designs/sky130hd/ibex/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 62, + "value": 128, "compare": "<=" }, "detailedroute__route__wirelength": { diff --git a/flow/designs/sky130hs/ibex/rules-base.json b/flow/designs/sky130hs/ibex/rules-base.json index ab9f01be3f..87b458d33b 100644 --- a/flow/designs/sky130hs/ibex/rules-base.json +++ b/flow/designs/sky130hs/ibex/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 45, + "value": 130, "compare": "<=" }, "detailedroute__route__wirelength": { From a90676a72571950f032f085c46564910b1e26969 Mon Sep 17 00:00:00 2001 From: Augusto Berndt Date: Mon, 7 Jul 2025 09:13:24 +0000 Subject: [PATCH 141/198] adjust microwatt density Signed-off-by: Augusto Berndt --- flow/designs/sky130hd/microwatt/config.mk | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/flow/designs/sky130hd/microwatt/config.mk b/flow/designs/sky130hd/microwatt/config.mk index fcaca885fc..4995d64a26 100644 --- a/flow/designs/sky130hd/microwatt/config.mk +++ b/flow/designs/sky130hd/microwatt/config.mk @@ -11,8 +11,6 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint. export DIE_AREA = 0 0 3020 3610 export CORE_AREA = 10 10 3010 3600 -export PLACE_DENSITY ?= 0.2 - export microwatt_DIR = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME) export ADDITIONAL_GDS = $(wildcard $(microwatt_DIR)/gds/*.gds.gz) @@ -33,7 +31,7 @@ export MACRO_BLOCKAGE_HALO = 151 # There's less space due to the adapted blockage halos, so GPL requires a # higher density in order to run. -export PLACE_DENSITY = 0.19 +export PLACE_DENSITY = 0.2 # CTS tuning export CTS_BUF_DISTANCE = 600 From d8554c3c68b1b4ab92530143bb6694ccaefb5e52 Mon Sep 17 00:00:00 2001 From: Augusto Berndt Date: Mon, 7 Jul 2025 09:13:29 +0000 Subject: [PATCH 142/198] update OR Signed-off-by: Augusto Berndt --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index a090ebaa03..a9225047f8 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit a090ebaa03b3171cc7282e49d651c8280d9372b2 +Subproject commit a9225047f836574f62009f3e345c76806e5b4b23 From b63b64d9f1141b6441f1ca241eb60a41569bf2cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 7 Jul 2025 13:40:19 +0200 Subject: [PATCH 143/198] logging: log hash alongside elapsed to help find divergent results MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/test/test_genElapsedTime.py | 6 +++--- flow/util/genElapsedTime.py | 28 ++++++++++++++++++++++++---- 2 files changed, 27 insertions(+), 7 deletions(-) diff --git a/flow/test/test_genElapsedTime.py b/flow/test/test_genElapsedTime.py index e6108cb093..36da00209e 100755 --- a/flow/test/test_genElapsedTime.py +++ b/flow/test/test_genElapsedTime.py @@ -30,7 +30,7 @@ def test_elapsed_time(self, mock_stdout): genElapsedTime.scan_logs(["--logDir", str(self.tmp_dir.name), "--noHeader"]) # check if output is correct expected_output = ( - self.tmp_dir.name + "\n1_test 5400 9440\nTotal 5400 9440\n" + self.tmp_dir.name + "\n1_test 5400 9440 N/A\nTotal 5400 9440\n" ).split() actual_output = mock_stdout.getvalue().split() self.assertEqual(actual_output, expected_output) @@ -44,7 +44,7 @@ def test_zero_time(self, mock_stdout): # call the script with the test log file genElapsedTime.scan_logs(["--logDir", str(self.tmp_dir.name), "--noHeader"]) expected_output = ( - self.tmp_dir.name + "\n1_test 74 9440\nTotal 74 9440\n" + self.tmp_dir.name + "\n1_test 74 9440 N/A\nTotal 74 9440\n" ).split() actual_output = mock_stdout.getvalue().split() self.assertEqual(actual_output, expected_output) @@ -61,7 +61,7 @@ def test_elapsed_time_longer_duration(self, mock_stdout): genElapsedTime.scan_logs(["--logDir", str(self.tmp_dir.name), "--noHeader"]) # check if output is correct expected_output = ( - self.tmp_dir.name + "\n1_test 744 9440 Total 744 9440" + self.tmp_dir.name + "\n1_test 744 9440 N/A Total 744 9440" ).split() actual_output = mock_stdout.getvalue().split() self.assertEqual(actual_output, expected_output) diff --git a/flow/util/genElapsedTime.py b/flow/util/genElapsedTime.py index 4a1159d105..3c9d0c7cf9 100755 --- a/flow/util/genElapsedTime.py +++ b/flow/util/genElapsedTime.py @@ -4,9 +4,10 @@ # in the flow and prints it in a table # --------------------------------------------------------------------------- +import argparse +import hashlib import pathlib import os -import argparse # argument parsing import sys # Parse and validate arguments @@ -61,15 +62,33 @@ def print_log_dir_times(logdir, args): int(line.split("Peak memory: ")[1].split("KB")[0]) / 1024 ) + # content hash for .odb file alongside .log file is useful to + # debug divergent results under what should be identical + # builds(such as local and CI builds) + odb_file = pathlib.Path( + str(f).replace("logs/", "results/").replace(".log", ".odb") + ) + if odb_file.exists(): + hasher = hashlib.sha1() + with open(odb_file, "rb") as odb_f: + while chunk := odb_f.read(16 * 1024 * 1024): + hasher.update(chunk) + odb_hash = hasher.hexdigest() + else: + odb_hash = "N/A" + if not found: print("No elapsed time found in", str(f), file=sys.stderr) continue # Print the name of the step and the corresponding elapsed time - format_str = "%-25s %20s %14s" + format_str = "%-25s %10s %14s %20s" if elapsedTime is not None and peak_memory is not None: if first and not args.noHeader: - print(format_str % ("Log", "Elapsed seconds", "Peak Memory/MB")) + print( + format_str + % ("Log", "Elapsed/s", "Peak Memory/MB", "sha1sum .odb [0:20)") + ) first = False print( format_str @@ -77,13 +96,14 @@ def print_log_dir_times(logdir, args): os.path.splitext(os.path.basename(str(f)))[0], elapsedTime, peak_memory, + odb_hash[0:20], ) ) totalElapsed += elapsedTime total_max_memory = max(total_max_memory, int(peak_memory)) if totalElapsed != 0: - print(format_str % ("Total", totalElapsed, total_max_memory)) + print(format_str % ("Total", totalElapsed, total_max_memory, "")) def scan_logs(args): From cf1ac3106f0a2c8883d149004d5e582be2c5fa10 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Mon, 7 Jul 2025 11:40:06 -0300 Subject: [PATCH 144/198] use latest master Signed-off-by: Eder Monteiro --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index a090ebaa03..9756c46833 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit a090ebaa03b3171cc7282e49d651c8280d9372b2 +Subproject commit 9756c4683354d5662255df084d52f79a12309b00 From 775b76262e95e963f33e2e05910fd88d3cc3a9a5 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Mon, 7 Jul 2025 11:40:28 -0300 Subject: [PATCH 145/198] use Yosys 0.55 Signed-off-by: Eder Monteiro --- tools/yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/yosys b/tools/yosys index db72ec3bde..60f126cd00 160000 --- a/tools/yosys +++ b/tools/yosys @@ -1 +1 @@ -Subproject commit db72ec3bde296a9512b2d1e6fabf81cfb07c2c1b +Subproject commit 60f126cd00c94892782470192d6c9f7abebe7c05 From 40c2371feca27a59eceb122329ba47522d2972a0 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" Date: Mon, 7 Jul 2025 16:14:41 +0000 Subject: [PATCH 146/198] flow: update rules Signed-off-by: github-actions[bot] --- flow/designs/asap7/aes-block/rules-base.json | 2 +- flow/designs/asap7/aes_lvt/rules-base.json | 2 +- flow/designs/asap7/mock-array/rules-base.json | 2 +- flow/designs/ihp-sg13g2/aes/rules-base.json | 2 +- flow/designs/sky130hd/gcd/rules-base.json | 2 +- flow/designs/sky130hs/jpeg/rules-base.json | 2 +- flow/designs/sky130hs/riscv32i/rules-base.json | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json index 69341b0032..25ee5654b9 100644 --- a/flow/designs/asap7/aes-block/rules-base.json +++ b/flow/designs/asap7/aes-block/rules-base.json @@ -24,7 +24,7 @@ "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1078, + "value": 1331, "compare": "<=" }, "globalroute__antenna_diodes_count": { diff --git a/flow/designs/asap7/aes_lvt/rules-base.json b/flow/designs/asap7/aes_lvt/rules-base.json index 2b534e1efd..d531c2e47a 100644 --- a/flow/designs/asap7/aes_lvt/rules-base.json +++ b/flow/designs/asap7/aes_lvt/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -16.32, + "value": -45.99, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/asap7/mock-array/rules-base.json b/flow/designs/asap7/mock-array/rules-base.json index 6073606041..ca0dbc34d6 100644 --- a/flow/designs/asap7/mock-array/rules-base.json +++ b/flow/designs/asap7/mock-array/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -440.47, + "value": -457.76, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/ihp-sg13g2/aes/rules-base.json b/flow/designs/ihp-sg13g2/aes/rules-base.json index 39d01ef6cf..263fe9108d 100644 --- a/flow/designs/ihp-sg13g2/aes/rules-base.json +++ b/flow/designs/ihp-sg13g2/aes/rules-base.json @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 12, + "value": 21, "compare": "<=" }, "finish__timing__setup__ws": { diff --git a/flow/designs/sky130hd/gcd/rules-base.json b/flow/designs/sky130hd/gcd/rules-base.json index 68014abc69..a574f06862 100644 --- a/flow/designs/sky130hd/gcd/rules-base.json +++ b/flow/designs/sky130hd/gcd/rules-base.json @@ -20,7 +20,7 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 50, + "value": 62, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { diff --git a/flow/designs/sky130hs/jpeg/rules-base.json b/flow/designs/sky130hs/jpeg/rules-base.json index 181da8a088..87385afc6a 100644 --- a/flow/designs/sky130hs/jpeg/rules-base.json +++ b/flow/designs/sky130hs/jpeg/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 60, + "value": 122, "compare": "<=" }, "detailedroute__route__wirelength": { diff --git a/flow/designs/sky130hs/riscv32i/rules-base.json b/flow/designs/sky130hs/riscv32i/rules-base.json index 0b81614fcc..d7914f948c 100644 --- a/flow/designs/sky130hs/riscv32i/rules-base.json +++ b/flow/designs/sky130hs/riscv32i/rules-base.json @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 5, + "value": 9, "compare": "<=" }, "finish__timing__setup__ws": { From 16f6b018dd8ffc28e384629af8639937b22f5ce4 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Mon, 7 Jul 2025 14:13:16 -0300 Subject: [PATCH 147/198] update public metrics Signed-off-by: Eder Monteiro --- flow/designs/asap7/aes-block/rules-base.json | 4 ++-- flow/designs/asap7/gcd/rules-base.json | 4 ++-- flow/designs/gf180/ibex/rules-base.json | 14 +++++++------- flow/designs/gf180/riscv32i/rules-base.json | 6 +++--- flow/designs/sky130hs/riscv32i/rules-base.json | 4 ++-- 5 files changed, 16 insertions(+), 16 deletions(-) diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json index 69341b0032..d818e632b4 100644 --- a/flow/designs/asap7/aes-block/rules-base.json +++ b/flow/designs/asap7/aes-block/rules-base.json @@ -24,7 +24,7 @@ "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1078, + "value": 1744, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -18.47, + "value": -33.09, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/gcd/rules-base.json b/flow/designs/asap7/gcd/rules-base.json index 186b37c73d..b770bcc571 100644 --- a/flow/designs/asap7/gcd/rules-base.json +++ b/flow/designs/asap7/gcd/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1286, + "value": 1271, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 24, + "value": 27, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/gf180/ibex/rules-base.json b/flow/designs/gf180/ibex/rules-base.json index 87f7efb191..1614e8fcee 100644 --- a/flow/designs/gf180/ibex/rules-base.json +++ b/flow/designs/gf180/ibex/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 17103, + "value": 16937, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,15 +20,15 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1487, + "value": 1473, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1487, + "value": 1473, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 2, + "value": 38, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.31, + "value": -0.77, "compare": ">=" }, "finish__design__instance__area": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 744, + "value": 736, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -18.32, + "value": -14.05, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf180/riscv32i/rules-base.json b/flow/designs/gf180/riscv32i/rules-base.json index 50900a70fd..77b831cf4d 100644 --- a/flow/designs/gf180/riscv32i/rules-base.json +++ b/flow/designs/gf180/riscv32i/rules-base.json @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 0, + "value": 2, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 754102, + "value": 739817, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -52,7 +52,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 475666, + "value": 475387, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { diff --git a/flow/designs/sky130hs/riscv32i/rules-base.json b/flow/designs/sky130hs/riscv32i/rules-base.json index 0b81614fcc..60fe976e7d 100644 --- a/flow/designs/sky130hs/riscv32i/rules-base.json +++ b/flow/designs/sky130hs/riscv32i/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 116710, + "value": 116701, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 5, + "value": 16, "compare": "<=" }, "finish__timing__setup__ws": { From 614ecd8f4ec0b34b04da0114ddab73a161a89cee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 7 Jul 2025 19:46:54 +0200 Subject: [PATCH 148/198] synthesis: more consistent naming of logs and results MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/Makefile | 12 ++++++------ flow/scripts/synth.tcl | 4 ++-- flow/scripts/synth_canonicalize.tcl | 2 +- flow/scripts/synth_metrics.tcl | 2 +- flow/scripts/synth_preamble.tcl | 4 ++-- flow/util/genMetrics.py | 2 +- 6 files changed, 13 insertions(+), 13 deletions(-) diff --git a/flow/Makefile b/flow/Makefile index c96bf8f3c6..329df67452 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -258,7 +258,7 @@ synth-report: synth .PHONY: do-synth-report do-synth-report: - ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/synth_metrics.tcl) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys_metrics.log) + ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/synth_metrics.tcl) 2>&1 | tee $(abspath $(LOG_DIR)/1_2_yosys_metrics.log) .PHONY: memory memory: @@ -282,24 +282,24 @@ yosys-dependencies: $(YOSYS_DEPENDENCIES) .PHONY: do-yosys do-yosys: $(DONT_USE_SC_LIB) - $(SCRIPTS_DIR)/synth.sh $(SYNTH_SCRIPT) $(LOG_DIR)/1_1_yosys.log + $(SCRIPTS_DIR)/synth.sh $(SYNTH_SCRIPT) $(LOG_DIR)/1_2_yosys.log .PHONY: do-yosys-canonicalize do-yosys-canonicalize: yosys-dependencies $(DONT_USE_SC_LIB) $(SCRIPTS_DIR)/synth.sh $(SCRIPTS_DIR)/synth_canonicalize.tcl $(LOG_DIR)/1_1_yosys_canonicalize.log -$(RESULTS_DIR)/1_synth.rtlil: $(YOSYS_DEPENDENCIES) +$(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil: $(YOSYS_DEPENDENCIES) $(UNSET_AND_MAKE) do-yosys-canonicalize -$(RESULTS_DIR)/1_1_yosys.v: $(RESULTS_DIR)/1_synth.rtlil +$(RESULTS_DIR)/1_2_yosys.v: $(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil $(UNSET_AND_MAKE) do-yosys .PHONY: do-synth do-synth: mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) - cp $(RESULTS_DIR)/1_1_yosys.v $(RESULTS_DIR)/1_synth.v + cp $(RESULTS_DIR)/1_2_yosys.v $(RESULTS_DIR)/1_synth.v -$(RESULTS_DIR)/1_synth.v: $(RESULTS_DIR)/1_1_yosys.v +$(RESULTS_DIR)/1_synth.v: $(RESULTS_DIR)/1_2_yosys.v $(UNSET_AND_MAKE) do-synth .PHONY: clean_synth diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl index 9a6b75d0be..a6c9807af5 100644 --- a/flow/scripts/synth.tcl +++ b/flow/scripts/synth.tcl @@ -1,5 +1,5 @@ source $::env(SCRIPTS_DIR)/synth_preamble.tcl -read_checkpoint $::env(RESULTS_DIR)/1_synth.rtlil +read_checkpoint $::env(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil hierarchy -check -top $::env(DESIGN_NAME) @@ -145,7 +145,7 @@ if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } { } # Write synthesized design -write_verilog -nohex -nodec $::env(RESULTS_DIR)/1_1_yosys.v +write_verilog -nohex -nodec $::env(RESULTS_DIR)/1_2_yosys.v # One day a more sophisticated synthesis will write out a modified # .sdc file after synthesis. For now, just copy the input .sdc file, # making synthesis more consistent with other stages. diff --git a/flow/scripts/synth_canonicalize.tcl b/flow/scripts/synth_canonicalize.tcl index f53ca13219..3c167d7797 100644 --- a/flow/scripts/synth_canonicalize.tcl +++ b/flow/scripts/synth_canonicalize.tcl @@ -10,4 +10,4 @@ hierarchy -check -top $::env(DESIGN_NAME) # Get rid of unused modules opt_clean -purge # The hash of this file will not change if files not part of synthesis do not change -write_rtlil $::env(RESULTS_DIR)/1_synth.rtlil +write_rtlil $::env(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil diff --git a/flow/scripts/synth_metrics.tcl b/flow/scripts/synth_metrics.tcl index f24a05e80e..d2fe0ab500 100644 --- a/flow/scripts/synth_metrics.tcl +++ b/flow/scripts/synth_metrics.tcl @@ -1,5 +1,5 @@ utl::set_metrics_stage "synth__{}" source $::env(SCRIPTS_DIR)/load.tcl -load_design 1_1_yosys.v 1_synth.sdc +load_design 1_2_yosys.v 1_synth.sdc report_metrics 1 "Post synthesis" false false diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl index a148fd9460..22dcb2aefb 100644 --- a/flow/scripts/synth_preamble.tcl +++ b/flow/scripts/synth_preamble.tcl @@ -8,11 +8,11 @@ erase_non_stage_variables synth # floorplan step to be re-executed. if { [env_var_exists_and_non_empty SYNTH_NETLIST_FILES] } { if { [llength $::env(SYNTH_NETLIST_FILES)] == 1 } { - log_cmd exec cp -p $::env(SYNTH_NETLIST_FILES) $::env(RESULTS_DIR)/1_1_yosys.v + log_cmd exec cp -p $::env(SYNTH_NETLIST_FILES) $::env(RESULTS_DIR)/1_2_yosys.v } else { # The date should be the most recent date of the files, but to # keep things simple we just use the creation date - log_cmd exec cat {*}$::env(SYNTH_NETLIST_FILES) > $::env(RESULTS_DIR)/1_1_yosys.v + log_cmd exec cat {*}$::env(SYNTH_NETLIST_FILES) > $::env(RESULTS_DIR)/1_2_yosys.v } log_cmd exec cp -p $::env(SDC_FILE) $::env(RESULTS_DIR)/1_synth.sdc if { [env_var_exists_and_non_empty CACHED_REPORTS] } { diff --git a/flow/util/genMetrics.py b/flow/util/genMetrics.py index 0b5ebee993..33261a7f8c 100755 --- a/flow/util/genMetrics.py +++ b/flow/util/genMetrics.py @@ -288,7 +288,7 @@ def extract_metrics( # Accumulate time # ========================================================================= - extractGnuTime("synth", metrics_dict, logPath + "/1_1_yosys.log") + extractGnuTime("synth", metrics_dict, logPath + "/1_2_yosys.log") extractGnuTime("floorplan", metrics_dict, logPath + "/2_1_floorplan.log") extractGnuTime("floorplan_io", metrics_dict, logPath + "/2_2_floorplan_io.log") extractGnuTime( From 22bfa724a05f4b3f1c71034761a844187e6f3993 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 7 Jul 2025 17:20:27 +0200 Subject: [PATCH 149/198] make: elapsed now looks for .v after .odb for a stage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/util/genElapsedTime.py | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/flow/util/genElapsedTime.py b/flow/util/genElapsedTime.py index 3c9d0c7cf9..83e992c70e 100755 --- a/flow/util/genElapsedTime.py +++ b/flow/util/genElapsedTime.py @@ -62,20 +62,22 @@ def print_log_dir_times(logdir, args): int(line.split("Peak memory: ")[1].split("KB")[0]) / 1024 ) - # content hash for .odb file alongside .log file is useful to + # content hash for the result file alongside .log file is useful to # debug divergent results under what should be identical # builds(such as local and CI builds) - odb_file = pathlib.Path( - str(f).replace("logs/", "results/").replace(".log", ".odb") - ) - if odb_file.exists(): - hasher = hashlib.sha1() - with open(odb_file, "rb") as odb_f: - while chunk := odb_f.read(16 * 1024 * 1024): - hasher.update(chunk) - odb_hash = hasher.hexdigest() - else: - odb_hash = "N/A" + for ext in [".odb", ".rtlil", ".v"]: + result_file = pathlib.Path( + str(f).replace("logs/", "results/").replace(".log", ext) + ) + if result_file.exists(): + hasher = hashlib.sha1() + with open(result_file, "rb") as odb_f: + while chunk := odb_f.read(16 * 1024 * 1024): + hasher.update(chunk) + odb_hash = hasher.hexdigest() + break + else: + odb_hash = "N/A" if not found: print("No elapsed time found in", str(f), file=sys.stderr) From 8f6734a4ee425a080423426ca0bc1beb4c8fbf9e Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Mon, 7 Jul 2025 20:09:05 +0000 Subject: [PATCH 150/198] update OR Signed-off-by: Matt Liberty --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index a9225047f8..9d528d9b5c 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit a9225047f836574f62009f3e345c76806e5b4b23 +Subproject commit 9d528d9b5c8b2b4d4ded684186edad986740f6ad From 433dd5b678e4b9c69f6fbd7525f59a3b288bb8f4 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Mon, 7 Jul 2025 17:17:58 -0300 Subject: [PATCH 151/198] bump or Signed-off-by: Eder Monteiro --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index 9756c46833..9d528d9b5c 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 9756c4683354d5662255df084d52f79a12309b00 +Subproject commit 9d528d9b5c8b2b4d4ded684186edad986740f6ad From c537a7e91e304ba60f6e98683badd7acf241e999 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 7 Jul 2025 22:55:56 +0200 Subject: [PATCH 152/198] logs: log hashes to ORFS log files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In the bazel-orfs use-case, the .odb files are not all present in the finish step, so log as we go along in addition to the finish step. A little bit more verbose than I could have wished for, but it does the job. Refine later, possibly. Signed-off-by: Øyvind Harboe --- flow/scripts/flow.sh | 3 +++ flow/util/genElapsedTime.py | 14 +++++++++++--- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/flow/scripts/flow.sh b/flow/scripts/flow.sh index 2d2e037927..96ef5615e0 100755 --- a/flow/scripts/flow.sh +++ b/flow/scripts/flow.sh @@ -6,3 +6,6 @@ echo Running $2.tcl, stage $1 $OPENROAD_EXE $OPENROAD_ARGS -exit $SCRIPTS_DIR/noop.tcl 2>&1 >$LOG_DIR/$1.tmp.log; \ eval "$TIME_CMD $OPENROAD_CMD -no_splash $SCRIPTS_DIR/$2.tcl -metrics $LOG_DIR/$1.json" 2>&1 | \ tee -a $(realpath $LOG_DIR/$1.tmp.log)) +# Log the hash for this step. The summary "make elapsed" in "make finish", +# will not have all the .odb files for the bazel-orfs use-case. +$PYTHON_EXE $UTILS_DIR/genElapsedTime.py --match $1 -d $LOG_DIR | tee -a $(realpath $LOG_DIR/$1.log) diff --git a/flow/util/genElapsedTime.py b/flow/util/genElapsedTime.py index 83e992c70e..93a762afc7 100755 --- a/flow/util/genElapsedTime.py +++ b/flow/util/genElapsedTime.py @@ -18,13 +18,17 @@ def print_log_dir_times(logdir, args): first = True totalElapsed = 0 total_max_memory = 0 - print(logdir) + if not args.match: + print(logdir) # Loop on all log files in the directory for f in sorted(pathlib.Path(logdir).glob("**/*.log")): if "eqy_output" in str(f): continue # Extract Elapsed Time line from log file + stem = os.path.splitext(os.path.basename(str(f)))[0] + if args.match and args.match != stem: + continue with open(str(f)) as logfile: found = False for line in logfile: @@ -95,7 +99,7 @@ def print_log_dir_times(logdir, args): print( format_str % ( - os.path.splitext(os.path.basename(str(f)))[0], + stem, elapsedTime, peak_memory, odb_hash[0:20], @@ -104,7 +108,7 @@ def print_log_dir_times(logdir, args): totalElapsed += elapsedTime total_max_memory = max(total_max_memory, int(peak_memory)) - if totalElapsed != 0: + if totalElapsed != 0 and not args.match: print(format_str % ("Total", totalElapsed, total_max_memory, "")) @@ -112,6 +116,10 @@ def scan_logs(args): parser = argparse.ArgumentParser( description="Print elapsed time for every step in the flow" ) + parser.add_argument( + "--match", + help="Match this string in the log file names", + ) parser.add_argument( "--logDir", "-d", required=True, nargs="+", help="Log files directories" ) From 157c3a1a650c77c864440da2e40fd9970aa9b474 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Mon, 7 Jul 2025 22:30:10 +0000 Subject: [PATCH 153/198] Minor update of gf180/jpeg (a few diodes) | Metric | Old | New | Type | | ------ | --- | --- | ---- | | placeopt__design__instance__area | 2366631 | 2362986 | Tighten | | placeopt__design__instance__count__stdcell | 53829 | 53818 | Tighten | | cts__design__instance__count__setup_buffer | 4681 | 4680 | Tighten | | cts__design__instance__count__hold_buffer | 4681 | 4680 | Tighten | | detailedroute__route__wirelength | 2985307 | 2973166 | Tighten | | detailedroute__antenna_diodes_count | 6 | 10 | Failing | Signed-off-by: Matt Liberty --- flow/designs/gf180/jpeg/rules-base.json | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/flow/designs/gf180/jpeg/rules-base.json b/flow/designs/gf180/jpeg/rules-base.json index 87365b1740..f3d7b6a752 100644 --- a/flow/designs/gf180/jpeg/rules-base.json +++ b/flow/designs/gf180/jpeg/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2366631, + "value": 2362986, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 53829, + "value": 53818, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 4681, + "value": 4680, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 4681, + "value": 4680, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 2985307, + "value": 2973166, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 6, + "value": 10, "compare": "<=" }, "finish__timing__setup__ws": { From e99ca18beeff03346a6551156df651a289be8bef Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" Date: Tue, 8 Jul 2025 04:24:51 +0000 Subject: [PATCH 154/198] flow: update rules Signed-off-by: github-actions[bot] --- flow/designs/asap7/aes-block/rules-base.json | 2 +- flow/designs/asap7/aes/rules-base.json | 2 +- flow/designs/gf180/riscv32i/rules-base.json | 2 +- flow/designs/sky130hd/microwatt/rules-base.json | 2 +- flow/designs/sky130hs/riscv32i/rules-base.json | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json index 25ee5654b9..b862022943 100644 --- a/flow/designs/asap7/aes-block/rules-base.json +++ b/flow/designs/asap7/aes-block/rules-base.json @@ -24,7 +24,7 @@ "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1331, + "value": 1561, "compare": "<=" }, "globalroute__antenna_diodes_count": { diff --git a/flow/designs/asap7/aes/rules-base.json b/flow/designs/asap7/aes/rules-base.json index 6038bda668..5dfa3fd7a7 100644 --- a/flow/designs/asap7/aes/rules-base.json +++ b/flow/designs/asap7/aes/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -34.79, + "value": -73.23, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/gf180/riscv32i/rules-base.json b/flow/designs/gf180/riscv32i/rules-base.json index 77b831cf4d..02bc390fc2 100644 --- a/flow/designs/gf180/riscv32i/rules-base.json +++ b/flow/designs/gf180/riscv32i/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.45, + "value": -1.04, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/sky130hd/microwatt/rules-base.json b/flow/designs/sky130hd/microwatt/rules-base.json index 3d00501a44..4b1d9fe871 100644 --- a/flow/designs/sky130hd/microwatt/rules-base.json +++ b/flow/designs/sky130hd/microwatt/rules-base.json @@ -40,7 +40,7 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 1, + "value": 3, "compare": "<=" }, "detailedroute__antenna_diodes_count": { diff --git a/flow/designs/sky130hs/riscv32i/rules-base.json b/flow/designs/sky130hs/riscv32i/rules-base.json index d7914f948c..60e391e6ae 100644 --- a/flow/designs/sky130hs/riscv32i/rules-base.json +++ b/flow/designs/sky130hs/riscv32i/rules-base.json @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 9, + "value": 16, "compare": "<=" }, "finish__timing__setup__ws": { From af135778ba1533da6681f43aba958f5f094b584d Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Tue, 8 Jul 2025 10:12:47 -0300 Subject: [PATCH 155/198] bump or Signed-off-by: Eder Monteiro --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index 9d528d9b5c..9c4e436fd2 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 9d528d9b5c8b2b4d4ded684186edad986740f6ad +Subproject commit 9c4e436fd25b85c33476dddbfb60deb4ae18fd0d From 99121a1808bac4a85abea6ddb16de4120aa740ed Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Tue, 8 Jul 2025 10:13:18 -0300 Subject: [PATCH 156/198] update sky130hs metrics Signed-off-by: Eder Monteiro --- flow/designs/sky130hs/jpeg/rules-base.json | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/flow/designs/sky130hs/jpeg/rules-base.json b/flow/designs/sky130hs/jpeg/rules-base.json index 87385afc6a..a69feb23d7 100644 --- a/flow/designs/sky130hs/jpeg/rules-base.json +++ b/flow/designs/sky130hs/jpeg/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 122, + "value": 201, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 164, + "value": 102, "compare": "<=" }, "finish__timing__setup__ws": { From b9d4358349e304a92db09986fe0b7b0b194df896 Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Tue, 8 Jul 2025 15:37:08 +0000 Subject: [PATCH 157/198] lint flow/platforms Signed-off-by: Jack Luar --- flow/platforms/asap7/constraints.sdc | 27 ++++++++++--------- flow/platforms/asap7/liberty_suppressions.tcl | 3 ++- .../openRoad/pdn/BLOCKS_grid_strategy.tcl | 13 ++++++--- .../openRoad/pdn/BLOCK_grid_strategy.tcl | 3 ++- .../pdn/grid_strategy-M1-M2-M5-M6.tcl | 6 +++-- .../asap7/openlane/asap7sc7p5t/config.tcl | 2 ++ flow/platforms/asap7/openlane/config.tcl | 2 ++ flow/platforms/ihp-sg13g2/pdn.tcl | 12 ++++++--- flow/platforms/nangate45/fakeram.tcl | 6 +++-- .../nangate45/grid_strategy-M1-M4-M7.tcl | 6 +++-- flow/platforms/sky130hd/pdn.tcl | 6 +++-- flow/platforms/sky130hs/pdn.tcl | 6 +++-- tclint.toml | 1 - 13 files changed, 60 insertions(+), 33 deletions(-) diff --git a/flow/platforms/asap7/constraints.sdc b/flow/platforms/asap7/constraints.sdc index f222d12ce3..103986bbbc 100644 --- a/flow/platforms/asap7/constraints.sdc +++ b/flow/platforms/asap7/constraints.sdc @@ -1,6 +1,6 @@ # A minimal generic constraints.sdc for architectural exploration of macros # ------------------------------------------------------------------------- -# +# # Used in designs/asap7/mock-array, for example. # # From the following observations, all else follows: the only thing @@ -8,7 +8,7 @@ # other constraints give the flow an optimization target. Failure # to meet the timing constraint of an optimization target constraint # is not a timing closure failure. -# +# # Note that ORFS regression checks do not have the ability to distinguish # between timing closure failures(register to register paths) and # optimization constraints violations. @@ -17,26 +17,26 @@ # in mock-array Element, such as maximum transit time for a combinational path # through mock-array Element, may or may not cause timing # violations later on higher up in mock-array on register to register paths. -# +# # For the Element, the only register to register path # are within the Element and no lower level macros are # involved. Register to register paths within Element have to be checked # at the Element level as they are invisible higher up in mock-array. -# +# # As for the remaining optimization constraints for Element, they # should be for combinational through paths(io-io) and # from input pins to register(io-reg) and from register to output pins(reg-io): -# +# # This constraints.sdc file is designed such that the clock latency & tree # can be ignored as far constraints go; # it is not part of the optimization constraints. The clock tree latency # is accounted for in register to register paths and not visible outside # of the macro that use this constraints.sdc. -# +# # All non reg-reg paths in Element are part of reg-reg paths in mock-array # and timing closure in which those take part are checked at the mock-array # level. -# +# # With this in mind, the constraints.sdc file for the Element becomes # quite general and simple. set_max_delay is used exclusively for # optimization constraints and the clock period is used to check timing @@ -51,13 +51,13 @@ # the time at the clock pin for the macro, which makes it impossible to articulate # the number that is passed in to set_input/output_delay without taking # clock network insertion latency into account. -# +# # Since set_input_delay is not used and set_max_delay is used instead, then # no hold cells are inserted, which is what is desired here. # # Details such as clock uncertainty, max transition time, load, etc. # is beyond the scope of this generic constraints.sdc file. -# +# # Beware of [path segmentation](https://docs.xilinx.com/r/2020.2-English/ug906-vivado-design-analysis/TIMING-13-Timing-Paths-Ignored-Due-to-Path-Segmentation), which # can occur with OpenSTA. @@ -76,9 +76,12 @@ set non_clk_inputs [all_inputs -no_clocks] # # Minimum time for io-io, io-reg, reg-io paths in macro is on # the order of 80ps for a small macro on ASAP7. -set_max_delay [expr { [info exists in2reg_max] ? $in2reg_max : 80 }] -from $non_clk_inputs -to [all_registers] -set_max_delay [expr { [info exists reg2out_max] ? $reg2out_max : 80 }] -from [all_registers] -to [all_outputs] -set_max_delay [expr { [info exists in2out_max] ? $in2out_max : 80 }] -from $non_clk_inputs -to [all_outputs] +set_max_delay [expr { [info exists in2reg_max] ? $in2reg_max : 80 }] -from $non_clk_inputs \ + -to [all_registers] +set_max_delay [expr { [info exists reg2out_max] ? $reg2out_max : 80 }] -from [all_registers] \ + -to [all_outputs] +set_max_delay [expr { [info exists in2out_max] ? $in2out_max : 80 }] -from $non_clk_inputs \ + -to [all_outputs] # This allows us to view the different groups # in the histogram in the GUI and also includes these diff --git a/flow/platforms/asap7/liberty_suppressions.tcl b/flow/platforms/asap7/liberty_suppressions.tcl index f8de273475..2600a0abf4 100644 --- a/flow/platforms/asap7/liberty_suppressions.tcl +++ b/flow/platforms/asap7/liberty_suppressions.tcl @@ -1,4 +1,5 @@ # To remove [WARNING STA-1212] from the logs for ASAP7. -# /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz line 13178, timing group from output port. +# /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz +# line 13178, timing group from output port. # Added following suppress_message log_cmd suppress_message STA 1212 diff --git a/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl b/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl index 02d76cdcec..d26c62c64b 100644 --- a/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl +++ b/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl @@ -18,10 +18,13 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} define_pdn_grid -name {top} -voltage_domains {CORE} add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins -add_pdn_ring -grid {top} -layers {M5 M6} -widths {0.504 0.544} -spacings {0.096} -core_offset {0.504} +add_pdn_ring -grid {top} -layers {M5 M6} -widths {0.504 0.544} -spacings {0.096} \ + -core_offset {0.504} -add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.16} -offset {1.50} -extend_to_core_ring -add_pdn_stripe -grid {top} -layer {M6} -width {0.288} -spacing {0.096} -pitch {4.32} -offset {1.504} -extend_to_core_ring +add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.16} \ + -offset {1.50} -extend_to_core_ring +add_pdn_stripe -grid {top} -layer {M6} -width {0.288} -spacing {0.096} -pitch {4.32} \ + -offset {1.504} -extend_to_core_ring add_pdn_connect -grid {top} -layers {M1 M2} add_pdn_connect -grid {top} -layers {M2 M5} @@ -40,8 +43,10 @@ foreach macro [find_macros] { } set macro_names [dict keys $macro_names] +set halo_x $::env(MACRO_ROWS_HALO_X) +set halo_y $::env(MACRO_ROWS_HALO_Y) define_pdn_grid -macro -cells $macro_names \ - -halo "$::env(MACRO_ROWS_HALO_X) $::env(MACRO_ROWS_HALO_Y) $::env(MACRO_ROWS_HALO_X) $::env(MACRO_ROWS_HALO_Y)" \ + -halo "$halo_x $halo_y $halo_x $halo_y" \ -voltage_domains {CORE} -name ElementGrid add_pdn_connect -grid {ElementGrid} -layers {M5 M6} diff --git a/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl b/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl index b8d6c4d392..a5cb2dd041 100644 --- a/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl +++ b/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl @@ -25,7 +25,8 @@ add_pdn_ring -grid {top} -layers {M5 M4} -widths {0.12 0.12} -spacings {0.072} - add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins -add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.976} -offset {1.5} -extend_to_core_ring +add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.976} -offset {1.5} \ + -extend_to_core_ring add_pdn_connect -grid {top} -layers {M1 M2} add_pdn_connect -grid {top} -layers {M2 M5} diff --git a/flow/platforms/asap7/openRoad/pdn/grid_strategy-M1-M2-M5-M6.tcl b/flow/platforms/asap7/openRoad/pdn/grid_strategy-M1-M2-M5-M6.tcl index 0b19e5d69a..d3bcfa8a67 100644 --- a/flow/platforms/asap7/openRoad/pdn/grid_strategy-M1-M2-M5-M6.tcl +++ b/flow/platforms/asap7/openRoad/pdn/grid_strategy-M1-M2-M5-M6.tcl @@ -28,10 +28,12 @@ add_pdn_connect -grid {top} -layers {M5 M6} #################################### # grid for: CORE_macro_grid_1 #################################### -define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -cells {.*} +define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro \ + -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -cells {.*} add_pdn_connect -grid {CORE_macro_grid_1} -layers {M4 M5} #################################### # grid for: CORE_macro_grid_2 #################################### -define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -cells {.*} +define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro \ + -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -cells {.*} add_pdn_connect -grid {CORE_macro_grid_2} -layers {M4 M5} diff --git a/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl b/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl index 9e23b6d0bd..4751010d48 100644 --- a/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl +++ b/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl @@ -1,3 +1,5 @@ +# tclint-disable line-length + set current_folder [file dirname [file normalize [info script]]] # Technology lib diff --git a/flow/platforms/asap7/openlane/config.tcl b/flow/platforms/asap7/openlane/config.tcl index ac404b4e2f..8724cdef98 100755 --- a/flow/platforms/asap7/openlane/config.tcl +++ b/flow/platforms/asap7/openlane/config.tcl @@ -1,3 +1,5 @@ +# tclint-disable line-length + # Process node set ::env(PROCESS) 7 set ::env(DEF_UNITS_PER_MICRON) 1000 diff --git a/flow/platforms/ihp-sg13g2/pdn.tcl b/flow/platforms/ihp-sg13g2/pdn.tcl index 27c506046a..812bcab616 100644 --- a/flow/platforms/ihp-sg13g2/pdn.tcl +++ b/flow/platforms/ihp-sg13g2/pdn.tcl @@ -19,10 +19,14 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} # standard cell grid #################################### define_pdn_grid -name {grid} -voltage_domains {CORE} -add_pdn_ring -grid {grid} -layers {Metal5 TopMetal1} -widths {5.0} -spacings {2.0} -core_offsets {4.5} -connect_to_pads -add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins -extend_to_core_ring -add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {13.600} -extend_to_core_ring -add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {1.800} -pitch {75.6} -offset {13.570} -extend_to_core_ring +add_pdn_ring -grid {grid} -layers {Metal5 TopMetal1} -widths {5.0} -spacings {2.0} \ + -core_offsets {4.5} -connect_to_pads +add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins \ + -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {13.600} \ + -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {1.800} -pitch {75.6} -offset {13.570} \ + -extend_to_core_ring add_pdn_connect -grid {grid} -layers {Metal1 Metal5} add_pdn_connect -grid {grid} -layers {Metal5 TopMetal1} # I/O pads diff --git a/flow/platforms/nangate45/fakeram.tcl b/flow/platforms/nangate45/fakeram.tcl index d4706cbe1a..68d548e689 100644 --- a/flow/platforms/nangate45/fakeram.tcl +++ b/flow/platforms/nangate45/fakeram.tcl @@ -31,8 +31,10 @@ proc copy_fakeram_results { } { foreach {design sizes} $design_rams { foreach size $sizes { - file copy -force $results_dir/fakeram45_$size/fakeram45_$size.lib $flow_dir/lib/fakeram45_$size.lib - file copy -force $results_dir/fakeram45_$size/fakeram45_$size.lef $flow_dir/lef/fakeram45_$size.lef + file copy -force \ + $results_dir/fakeram45_$size/fakeram45_$size.lib $flow_dir/lib/fakeram45_$size.lib + file copy -force \ + $results_dir/fakeram45_$size/fakeram45_$size.lef $flow_dir/lef/fakeram45_$size.lef } } } diff --git a/flow/platforms/nangate45/grid_strategy-M1-M4-M7.tcl b/flow/platforms/nangate45/grid_strategy-M1-M4-M7.tcl index a124d25802..02af27999c 100644 --- a/flow/platforms/nangate45/grid_strategy-M1-M4-M7.tcl +++ b/flow/platforms/nangate45/grid_strategy-M1-M4-M7.tcl @@ -26,7 +26,8 @@ add_pdn_connect -grid {grid} -layers {metal4 metal7} #################################### # grid for: CORE_macro_grid_1 #################################### -define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -cells {.*} +define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro \ + -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -cells {.*} add_pdn_stripe -grid {CORE_macro_grid_1} -layer {metal5} -width {0.93} -pitch {10.0} -offset {2} add_pdn_stripe -grid {CORE_macro_grid_1} -layer {metal6} -width {0.93} -pitch {10.0} -offset {2} add_pdn_connect -grid {CORE_macro_grid_1} -layers {metal4 metal5} @@ -35,7 +36,8 @@ add_pdn_connect -grid {CORE_macro_grid_1} -layers {metal6 metal7} #################################### # grid for: CORE_macro_grid_2 #################################### -define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -cells {.*} +define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro \ + -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -cells {.*} add_pdn_stripe -grid {CORE_macro_grid_2} -layer {metal6} -width {0.93} -pitch {40.0} -offset {2} add_pdn_connect -grid {CORE_macro_grid_2} -layers {metal4 metal6} add_pdn_connect -grid {CORE_macro_grid_2} -layers {metal6 metal7} diff --git a/flow/platforms/sky130hd/pdn.tcl b/flow/platforms/sky130hd/pdn.tcl index 1901913015..cb158996c8 100644 --- a/flow/platforms/sky130hd/pdn.tcl +++ b/flow/platforms/sky130hd/pdn.tcl @@ -30,10 +30,12 @@ add_pdn_connect -grid {grid} -layers {met4 met5} #################################### # grid for: CORE_macro_grid_1 #################################### -define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary +define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro \ + -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary add_pdn_connect -grid {CORE_macro_grid_1} -layers {met4 met5} #################################### # grid for: CORE_macro_grid_2 #################################### -define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary +define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro \ + -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary add_pdn_connect -grid {CORE_macro_grid_2} -layers {met4 met5} diff --git a/flow/platforms/sky130hs/pdn.tcl b/flow/platforms/sky130hs/pdn.tcl index 546a9a084f..8597d2a4bb 100644 --- a/flow/platforms/sky130hs/pdn.tcl +++ b/flow/platforms/sky130hs/pdn.tcl @@ -30,10 +30,12 @@ add_pdn_connect -grid {grid} -layers {met4 met5} #################################### # grid for: CORE_macro_grid_1 #################################### -define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary +define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro \ + -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary add_pdn_connect -grid {CORE_macro_grid_1} -layers {met4 met5} #################################### # grid for: CORE_macro_grid_2 #################################### -define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary +define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro \ + -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary add_pdn_connect -grid {CORE_macro_grid_2} -layers {met4 met5} diff --git a/tclint.toml b/tclint.toml index caecb46445..6a5d3c0c2d 100644 --- a/tclint.toml +++ b/tclint.toml @@ -5,7 +5,6 @@ exclude = [ "flow/logs", "flow/designs/asap7/cva6/constraint.sdc", "flow/designs/nangate45/bp_quad/bsg_chip.sdc", - "flow/platforms", "flow/scripts/*.tcl", "tools/OpenROAD", "tools/yosys", From 574871992f28a29ba045e6cab4f6669df04e3900 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Tue, 8 Jul 2025 13:20:13 -0300 Subject: [PATCH 158/198] update density for failing design Signed-off-by: Eder Monteiro --- flow/designs/ihp-sg13g2/jpeg/config.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/flow/designs/ihp-sg13g2/jpeg/config.mk b/flow/designs/ihp-sg13g2/jpeg/config.mk index a1cfef88a4..24bb3852d5 100644 --- a/flow/designs/ihp-sg13g2/jpeg/config.mk +++ b/flow/designs/ihp-sg13g2/jpeg/config.mk @@ -6,8 +6,8 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/* export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc -export CORE_UTILIZATION = 55 -export PLACE_DENSITY_LB_ADDON = 0.20 +export CORE_UTILIZATION = 50 +export PLACE_DENSITY_LB_ADDON = 0.15 export TNS_END_PERCENT = 100 export REMOVE_ABC_BUFFERS = 1 From 5810f536e33bef9a0d16a384e670a5bdda4b65e9 Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Tue, 8 Jul 2025 17:05:32 +0000 Subject: [PATCH 159/198] add flow/scripts Signed-off-by: Jack Luar --- flow/scripts/floorplan.tcl | 6 ++++-- flow/scripts/generate_abstract.tcl | 6 +++++- flow/scripts/global_route.tcl | 11 +++++++---- flow/scripts/load.tcl | 13 ++++++++----- flow/scripts/open.tcl | 5 +++-- flow/scripts/report_metrics.tcl | 27 ++++++++++++++++++--------- flow/scripts/resize.tcl | 2 +- flow/scripts/synth.tcl | 6 ++++-- flow/scripts/synth_preamble.tcl | 2 +- flow/scripts/util.tcl | 26 +++++++++++++++++--------- tclint.toml | 1 - 11 files changed, 68 insertions(+), 37 deletions(-) diff --git a/flow/scripts/floorplan.tcl b/flow/scripts/floorplan.tcl index a46f7365ca..2f4892dcf1 100644 --- a/flow/scripts/floorplan.tcl +++ b/flow/scripts/floorplan.tcl @@ -45,10 +45,12 @@ append_env_var additional_args ADDITIONAL_SITES -additional_sites 1 set use_floorplan_def [env_var_exists_and_non_empty FLOORPLAN_DEF] set use_footprint [env_var_exists_and_non_empty FOOTPRINT] -set use_die_and_core_area [expr { [env_var_exists_and_non_empty DIE_AREA] && [env_var_exists_and_non_empty CORE_AREA] }] +set use_die_and_core_area \ + [expr { [env_var_exists_and_non_empty DIE_AREA] && [env_var_exists_and_non_empty CORE_AREA] }] set use_core_utilization [env_var_exists_and_non_empty CORE_UTILIZATION] -set methods_defined [expr { $use_floorplan_def + $use_footprint + $use_die_and_core_area + $use_core_utilization }] +set methods_defined \ + [expr { $use_floorplan_def + $use_footprint + $use_die_and_core_area + $use_core_utilization }] if { $methods_defined > 1 } { puts "Error: Floorplan initialization methods are mutually exclusive, pick one." exit 1 diff --git a/flow/scripts/generate_abstract.tcl b/flow/scripts/generate_abstract.tcl index 6fc76b693a..9940ad3660 100644 --- a/flow/scripts/generate_abstract.tcl +++ b/flow/scripts/generate_abstract.tcl @@ -1,7 +1,11 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables generate_abstract -set stem [expr { [env_var_exists_and_non_empty ABSTRACT_SOURCE] ? $::env(ABSTRACT_SOURCE) : "6_final" }] +set stem [expr { + [env_var_exists_and_non_empty ABSTRACT_SOURCE] ? + $::env(ABSTRACT_SOURCE) : + "6_final" +}] set result [find_sdc_file $stem.odb] set design_stage [lindex $result 0] diff --git a/flow/scripts/global_route.tcl b/flow/scripts/global_route.tcl index 360a0067cc..3b29fe18d9 100644 --- a/flow/scripts/global_route.tcl +++ b/flow/scripts/global_route.tcl @@ -25,7 +25,7 @@ proc global_route_helper { } { if { $result != 0 } { if { - [expr !$::env(GENERATE_ARTIFACTS_ON_FAILURE) || \ + [!$::env(GENERATE_ARTIFACTS_ON_FAILURE) || \ ![file exists $::global_route_congestion_report] || \ [file size $::global_route_congestion_report] == 0] } { @@ -64,7 +64,8 @@ proc global_route_helper { } { log_cmd global_route -start_incremental log_cmd detailed_placement # Route only the modified net by DPL - log_cmd global_route -end_incremental -congestion_report_file $::env(REPORTS_DIR)/congestion_post_repair_design.rpt + log_cmd global_route -end_incremental \ + -congestion_report_file $::env(REPORTS_DIR)/congestion_post_repair_design.rpt # Repair timing using global route parasitics puts "Repair setup and hold violations..." @@ -81,14 +82,16 @@ proc global_route_helper { } { log_cmd global_route -start_incremental log_cmd detailed_placement # Route only the modified net by DPL - log_cmd global_route -end_incremental -congestion_report_file $::env(REPORTS_DIR)/congestion_post_repair_timing.rpt + log_cmd global_route -end_incremental \ + -congestion_report_file $::env(REPORTS_DIR)/congestion_post_repair_timing.rpt } log_cmd global_route -start_incremental recover_power_helper # Route the modified nets by rsz journal restore - log_cmd global_route -end_incremental -congestion_report_file $::env(REPORTS_DIR)/congestion_post_recover_power.rpt + log_cmd global_route -end_incremental \ + -congestion_report_file $::env(REPORTS_DIR)/congestion_post_recover_power.rpt if { ![env_var_equals SKIP_ANTENNA_REPAIR 1] } { puts "Repair antennas..." diff --git a/flow/scripts/load.tcl b/flow/scripts/load.tcl index 78c678081d..fd7664d2e4 100644 --- a/flow/scripts/load.tcl +++ b/flow/scripts/load.tcl @@ -33,7 +33,7 @@ proc load_design { design_file sdc_file } { # Read SDC file read_sdc $::env(RESULTS_DIR)/$sdc_file - if [file exists $::env(PLATFORM_DIR)/derate.tcl] { + if { [file exists $::env(PLATFORM_DIR)/derate.tcl] } { log_cmd source $::env(PLATFORM_DIR)/derate.tcl } @@ -46,7 +46,7 @@ proc load_design { design_file sdc_file } { } #=========================================================================================== -# Routines to run equivalence tests when they are enabled. +# Routines to run equivalence tests when they are enabled. proc get_verilog_cells_for_design { } { set dir "$::env(PLATFORM_DIR)/work_around_yosys/" @@ -74,7 +74,8 @@ proc write_eqy_script_for_sky130hd { } { #[script] #prep -top aes_cipher_top -flatten - ## Using `rename -hide` is a better performing choice than nomatch if the signal names have no meaning at all + ## Using `rename -hide` is a better performing choice than nomatch + ## if the signal names have no meaning at all #rename -hide */_*_.* ## This removes unused signals before partitioning so no partitions are created for them @@ -98,7 +99,7 @@ proc write_eqy_script { } { # Gold netlist puts $outfile "\[gold]\nread_verilog -sv $::env(RESULTS_DIR)/4_before_rsz.v $cell_files\n" puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n" - # Modified netlist + # Modified netlist puts $outfile "\[gate]\nread_verilog -sv $::env(RESULTS_DIR)/4_after_rsz.v $cell_files\n" puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n" @@ -129,12 +130,14 @@ proc run_equivalence_test { } { write_eqy_verilog 4_after_rsz.v write_eqy_script + # tclint-disable-next-line command-args eval exec eqy -d $::env(LOG_DIR)/4_eqy_output \ --force \ --jobs $::env(NUM_CORES) \ $::env(OBJECTS_DIR)/4_eqy_test.eqy \ > $::env(LOG_DIR)/4_equivalence_check.log - set count [exec grep -c "Successfully proved designs equivalent" $::env(LOG_DIR)/4_equivalence_check.log] + set count \ + [exec grep -c "Successfully proved designs equivalent" $::env(LOG_DIR)/4_equivalence_check.log] if { $count == 0 } { error "Repair timing output failed equivalence test" } else { diff --git a/flow/scripts/open.tcl b/flow/scripts/open.tcl index 36659892e0..a0cc92ce14 100644 --- a/flow/scripts/open.tcl +++ b/flow/scripts/open.tcl @@ -28,7 +28,7 @@ proc read_timing { input_file } { set sdc_file $::env(SDC_FILE) } log_cmd read_sdc $sdc_file - if [file exists $::env(PLATFORM_DIR)/derate.tcl] { + if { [file exists $::env(PLATFORM_DIR)/derate.tcl] } { source $::env(PLATFORM_DIR)/derate.tcl } @@ -57,7 +57,8 @@ proc read_timing { input_file } { if { [ord::openroad_gui_compiled] } { set db_basename [file rootname [file tail $input_file]] - gui::set_title "OpenROAD - $::env(PLATFORM)/$::env(DESIGN_NICKNAME)/$::env(FLOW_VARIANT) - ${db_basename}" + gui::set_title \ + "OpenROAD - $::env(PLATFORM)/$::env(DESIGN_NICKNAME)/$::env(FLOW_VARIANT) - ${db_basename}" } if { [env_var_equals GUI_TIMING 1] } { diff --git a/flow/scripts/report_metrics.tcl b/flow/scripts/report_metrics.tcl index a1c31864f6..b03cef6d63 100644 --- a/flow/scripts/report_metrics.tcl +++ b/flow/scripts/report_metrics.tcl @@ -45,17 +45,20 @@ proc report_metrics { stage when { include_erc true } { include_clock_skew true report_puts "\n==========================================================================" report_puts "$when report_checks -path_delay min" report_puts "--------------------------------------------------------------------------" - report_checks -path_delay min -fields {slew cap input net fanout} -format full_clock_expanded >> $filename + report_checks -path_delay min -fields {slew cap input net fanout} \ + -format full_clock_expanded >> $filename report_puts "\n==========================================================================" report_puts "$when report_checks -path_delay max" report_puts "--------------------------------------------------------------------------" - report_checks -path_delay max -fields {slew cap input net fanout} -format full_clock_expanded >> $filename + report_checks -path_delay max -fields {slew cap input net fanout} \ + -format full_clock_expanded >> $filename report_puts "\n==========================================================================" report_puts "$when report_checks -unconstrained" report_puts "--------------------------------------------------------------------------" - report_checks -unconstrained -fields {slew cap input net fanout} -format full_clock_expanded >> $filename + report_checks -unconstrained -fields {slew cap input net fanout} \ + -format full_clock_expanded >> $filename if { $include_erc } { report_puts "\n==========================================================================" @@ -154,23 +157,29 @@ proc report_metrics { stage when { include_erc true } { include_clock_skew true report_puts "\n==========================================================================" report_puts "$when report_checks -path_delay max reg to reg" report_puts "--------------------------------------------------------------------------" - report_checks -path_delay max -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename + report_checks -path_delay max -from [all_registers] -to [all_registers] \ + -format full_clock_expanded >> $filename report_puts "\n==========================================================================" report_puts "$when report_checks -path_delay min reg to reg" report_puts "--------------------------------------------------------------------------" - report_checks -path_delay min -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename + report_checks -path_delay min -from [all_registers] -to [all_registers] \ + -format full_clock_expanded >> $filename - set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay max -from [all_inputs] -to [all_registers]] 0] + set inp_to_reg_critical_path \ + [lindex [find_timing_paths -path_delay max -from [all_inputs] -to [all_registers]] 0] if { $inp_to_reg_critical_path != "" } { - set target_clock_latency_max [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4] + set target_clock_latency_max \ + [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4] } else { set target_clock_latency_max 0 } - set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay min -from [all_inputs] -to [all_registers]] 0] + set inp_to_reg_critical_path [lindex \ + [find_timing_paths -path_delay min -from [all_inputs] -to [all_registers]] 0] if { $inp_to_reg_critical_path != "" } { - set target_clock_latency_min [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4] + set target_clock_latency_min \ + [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4] set source_clock_latency [sta::format_time [$inp_to_reg_critical_path source_clk_latency] 4] } else { set target_clock_latency_min 0 diff --git a/flow/scripts/resize.tcl b/flow/scripts/resize.tcl index cb27fea936..d810d65de0 100644 --- a/flow/scripts/resize.tcl +++ b/flow/scripts/resize.tcl @@ -11,7 +11,7 @@ set pin_count_before [sta::network_leaf_pin_count] set_dont_use $::env(DONT_USE_CELLS) if { [env_var_exists_and_non_empty EARLY_SIZING_CAP_RATIO] } { - log_cmd set_opt_config -set_early_sizing_cap_ratio $env(EARLY_SIZING_CAP_RATIO) + log_cmd set_opt_config -set_early_sizing_cap_ratio $env(EARLY_SIZING_CAP_RATIO) } repair_design_helper diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl index a6c9807af5..6e8a82f7d4 100644 --- a/flow/scripts/synth.tcl +++ b/flow/scripts/synth.tcl @@ -25,7 +25,8 @@ set synth_full_args [env_var_or_empty SYNTH_ARGS] if { [env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS] } { set synth_full_args [concat $synth_full_args $::env(SYNTH_OPERATIONS_ARGS)] } else { - set synth_full_args [concat $synth_full_args "-extra-map $::env(FLOW_HOME)/platforms/common/lcu_kogge_stone.v"] + set synth_full_args [concat $synth_full_args \ + "-extra-map $::env(FLOW_HOME)/platforms/common/lcu_kogge_stone.v"] } if { ![env_var_equals SYNTH_HIERARCHICAL 1] } { @@ -52,7 +53,8 @@ if { ![env_var_equals SYNTH_HIERARCHICAL 1] } { json -o $::env(RESULTS_DIR)/mem.json # Run report and check here so as to fail early if this synthesis run is doomed -exec -- $::env(PYTHON_EXE) $::env(SCRIPTS_DIR)/mem_dump.py --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json +exec -- $::env(PYTHON_EXE) $::env(SCRIPTS_DIR)/mem_dump.py \ + --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } { synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_full_args diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl index 22dcb2aefb..5419d28b8a 100644 --- a/flow/scripts/synth_preamble.tcl +++ b/flow/scripts/synth_preamble.tcl @@ -141,7 +141,7 @@ proc convert_liberty_areas { } { continue } set area [rtlil::get_attr -string -mod $cell area] - if { $found_cell == "" || [expr $area < $found_cell_area] } { + if { $found_cell == "" || [$area < $found_cell_area] } { set found_cell $cell set found_cell_area $area } diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl index c7739f529f..eb7e849025 100644 --- a/flow/scripts/util.tcl +++ b/flow/scripts/util.tcl @@ -1,6 +1,6 @@ proc log_cmd { cmd args } { # log the command, escape arguments with spaces - set log_cmd "$cmd[join [lmap arg $args { format " %s" [expr { [string match {* *} $arg] ? "\"$arg\"" : "$arg" }] }] ""]" + set log_cmd "$cmd[join [lmap arg $args { format " %s" [expr { [string match {* *} $arg] ? "\"$arg\"" : "$arg" }] }] ""]" ;# tclint-disable-line line-length puts $log_cmd set start [clock seconds] set result [uplevel 1 [list $cmd {*}$args]] @@ -13,7 +13,7 @@ proc log_cmd { cmd args } { return $result } -proc repair_tie_fanout_helper {} { +proc repair_tie_fanout_helper { } { if { [env_var_exists_and_non_empty TIE_SEPARATION] } { set tie_separation $env(TIE_SEPARATION) } else { @@ -39,7 +39,9 @@ proc fast_route { } { if { [env_var_exists_and_non_empty FASTROUTE_TCL] } { log_cmd source $::env(FASTROUTE_TCL) } else { - log_cmd set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) $::env(ROUTING_LAYER_ADJUSTMENT) + log_cmd \ + set_global_routing_layer_adjustment \ + $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) $::env(ROUTING_LAYER_ADJUSTMENT) log_cmd set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) } } @@ -115,7 +117,8 @@ proc find_sdc_file { input_file } { set sdc_file "" set exact_sdc [string map {.odb .sdc} $input_file] - set sdc_files [glob -nocomplain -directory $::env(RESULTS_DIR) -types f "\[1-9+\]_\[1-9_A-Za-z\]*\.sdc"] + set sdc_files \ + [glob -nocomplain -directory $::env(RESULTS_DIR) -types f "\[1-9+\]_\[1-9_A-Za-z\]*\.sdc"] set sdc_files [lsort -decreasing -dictionary $sdc_files] set sdc_files [lmap file $sdc_files { file normalize $file }] foreach name $sdc_files { @@ -175,9 +178,9 @@ proc find_macros { } { proc erase_non_stage_variables { stage_name } { # "$::env(SCRIPTS_DIR)/stage_variables.py stage_name" returns list of # variables to erase. - # + # # Tcl yaml package can't be imported in the sta/openroad environment: - # + # # https://github.com/The-OpenROAD-Project/OpenROAD/issues/5875 set variables [exec $::env(SCRIPTS_DIR)/non_stage_variables.py $stage_name] foreach var $variables { @@ -195,11 +198,16 @@ proc place_density_with_lb_addon { } { set place_density_lb [gpl::get_global_placement_uniform_density \ -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)] - set place_density [expr $place_density_lb + ((1.0 - $place_density_lb) * $::env(PLACE_DENSITY_LB_ADDON)) + 0.01] + set place_density \ + [expr $place_density_lb + ((1.0 - $place_density_lb) * $::env(PLACE_DENSITY_LB_ADDON)) + 0.01] if { $place_density > 1.0 } { - utl::error FLW 24 "Place density exceeds 1.0 (current PLACE_DENSITY_LB_ADDON = $::env(PLACE_DENSITY_LB_ADDON)). Please check if the value of PLACE_DENSITY_LB_ADDON is between 0 and 0.99." + utl::error FLW 24 \ + "Place density exceeds 1.0 (current PLACE_DENSITY_LB_ADDON = \ + $::env(PLACE_DENSITY_LB_ADDON)). Please check if the value of \ + PLACE_DENSITY_LB_ADDON is between 0 and 0.99." } - puts "Placement density is $place_density, computed from PLACE_DENSITY_LB_ADDON $::env(PLACE_DENSITY_LB_ADDON) and lower bound $place_density_lb" + puts "Placement density is $place_density, computed from PLACE_DENSITY_LB_ADDON \ + $::env(PLACE_DENSITY_LB_ADDON) and lower bound $place_density_lb" } else { set place_density $::env(PLACE_DENSITY) } diff --git a/tclint.toml b/tclint.toml index 6a5d3c0c2d..cffc1af827 100644 --- a/tclint.toml +++ b/tclint.toml @@ -5,7 +5,6 @@ exclude = [ "flow/logs", "flow/designs/asap7/cva6/constraint.sdc", "flow/designs/nangate45/bp_quad/bsg_chip.sdc", - "flow/scripts/*.tcl", "tools/OpenROAD", "tools/yosys", "tools/yosys-slang", From 1f47df8d368168587e162d327ff2fff5c88f1d9d Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Tue, 8 Jul 2025 17:17:21 +0000 Subject: [PATCH 160/198] replace disable-next-line with disable-line Signed-off-by: Jack Luar --- flow/designs/nangate45/bp_quad/bsg_chip.sdc | 3 +-- flow/scripts/synth_wrap_operators.tcl | 2 +- tclint.toml | 1 - 3 files changed, 2 insertions(+), 4 deletions(-) diff --git a/flow/designs/nangate45/bp_quad/bsg_chip.sdc b/flow/designs/nangate45/bp_quad/bsg_chip.sdc index ea9a593ed0..d89a844195 100644 --- a/flow/designs/nangate45/bp_quad/bsg_chip.sdc +++ b/flow/designs/nangate45/bp_quad/bsg_chip.sdc @@ -144,5 +144,4 @@ set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_8_i] set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_8_i] set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_8_i] set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_8_i] -set_timing_derate -early -cell_delay 0.97 [get_cells \ - {bp_processor/cc/y_0__x_0__tile_node/tile/core/fe/mem/icache/tag_mem/macro_bmem/db1_wb_0__bank/macro_mem}] +set_timing_derate -early -cell_delay 0.97 [get_cells {bp_processor/cc/y_0__x_0__tile_node/tile/core/fe/mem/icache/tag_mem/macro_bmem/db1_wb_0__bank/macro_mem}] ;# tclint-disable-line line-length diff --git a/flow/scripts/synth_wrap_operators.tcl b/flow/scripts/synth_wrap_operators.tcl index a003aa2e32..a4e2897704 100644 --- a/flow/scripts/synth_wrap_operators.tcl +++ b/flow/scripts/synth_wrap_operators.tcl @@ -37,7 +37,7 @@ foreach info $deferred_cells { t:$type r:A_WIDTH>=10 r:Y_WIDTH>=14 %i %i # make per-architecture copies of the unmapped module - foreach modname [tee -q -s result.string select -list-mod A:arithmetic_operator A:copy_pending %i] { + foreach modname [tee -q -s result.string select -list-mod A:arithmetic_operator A:copy_pending %i] { # tclint-disable-line line-length setattr -mod -unset copy_pending $modname # iterate over non-default architectures diff --git a/tclint.toml b/tclint.toml index cffc1af827..4a98b01c7c 100644 --- a/tclint.toml +++ b/tclint.toml @@ -4,7 +4,6 @@ exclude = [ "flow/results", "flow/logs", "flow/designs/asap7/cva6/constraint.sdc", - "flow/designs/nangate45/bp_quad/bsg_chip.sdc", "tools/OpenROAD", "tools/yosys", "tools/yosys-slang", From d31ff1b09821b618521150879cf6328a8e0d8b11 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Wed, 9 Jul 2025 05:05:24 +0000 Subject: [PATCH 161/198] Add log_cmd to read_liberty.tcl Signed-off-by: Matt Liberty --- flow/scripts/read_liberty.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/flow/scripts/read_liberty.tcl b/flow/scripts/read_liberty.tcl index 89ff2df733..14f8f06e7a 100644 --- a/flow/scripts/read_liberty.tcl +++ b/flow/scripts/read_liberty.tcl @@ -5,7 +5,7 @@ if { [env_var_exists_and_non_empty CORNERS] } { foreach corner $::env(CORNERS) { set LIBKEY "[string toupper $corner]_LIB_FILES" foreach libFile $::env($LIBKEY) { - read_liberty -corner $corner $libFile + log_cmd read_liberty -corner $corner $libFile } unset LIBKEY } @@ -13,6 +13,6 @@ if { [env_var_exists_and_non_empty CORNERS] } { } else { ## no corner foreach libFile $::env(LIB_FILES) { - read_liberty $libFile + log_cmd read_liberty $libFile } } From 7754bff1553b9b6ba05e895355ed4b91c1b74e13 Mon Sep 17 00:00:00 2001 From: Augusto Berndt Date: Wed, 9 Jul 2025 13:59:55 +0000 Subject: [PATCH 162/198] update OR Signed-off-by: Augusto Berndt --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index 9c4e436fd2..e9a886276c 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 9c4e436fd25b85c33476dddbfb60deb4ae18fd0d +Subproject commit e9a886276c7f89da3b6246a7c8e4c8982a0addfd From 854f4023dcaecfc2b2010f9c979bb70c2ec1c445 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Wed, 9 Jul 2025 15:54:32 +0000 Subject: [PATCH 163/198] Check for None in computing totalElapsed and total_max_memory Fixes #3303 Signed-off-by: Matt Liberty --- flow/util/genElapsedTime.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/flow/util/genElapsedTime.py b/flow/util/genElapsedTime.py index 93a762afc7..e1bca5d0f8 100755 --- a/flow/util/genElapsedTime.py +++ b/flow/util/genElapsedTime.py @@ -105,8 +105,10 @@ def print_log_dir_times(logdir, args): odb_hash[0:20], ) ) - totalElapsed += elapsedTime - total_max_memory = max(total_max_memory, int(peak_memory)) + if elapsedTime is not None: + totalElapsed += elapsedTime + if peak_memory is not None: + total_max_memory = max(total_max_memory, int(peak_memory)) if totalElapsed != 0 and not args.match: print(format_str % ("Total", totalElapsed, total_max_memory, "")) From bb58022614f4c8ab954636e5e9b4f2bbc1770097 Mon Sep 17 00:00:00 2001 From: Augusto Berndt Date: Mon, 28 Apr 2025 20:33:32 +0200 Subject: [PATCH 164/198] include "-all" parameter to dependency installer description If I run DependencyInstaller without any input flag it throws an error, so I believe this is the right description Signed-off-by: Augusto Berndt --- etc/DependencyInstaller.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/etc/DependencyInstaller.sh b/etc/DependencyInstaller.sh index 769758230b..abbbadd0d9 100755 --- a/etc/DependencyInstaller.sh +++ b/etc/DependencyInstaller.sh @@ -235,7 +235,7 @@ _help() { cat < Date: Wed, 9 Jul 2025 10:24:00 -0300 Subject: [PATCH 165/198] Update etc/DependencyInstaller.sh Signed-off-by: Vitor Bandeira --- etc/DependencyInstaller.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/etc/DependencyInstaller.sh b/etc/DependencyInstaller.sh index abbbadd0d9..a1892490c6 100755 --- a/etc/DependencyInstaller.sh +++ b/etc/DependencyInstaller.sh @@ -235,7 +235,7 @@ _help() { cat <] # Installs all of OpenROAD's dependencies no # need to run -base or -common. Requires # privileged access. From 462013e8974c5ee81dfafbb86146337fa3727d8d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=A3o=20Mai?= Date: Wed, 9 Jul 2025 17:19:06 -0300 Subject: [PATCH 166/198] flow: update rules MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: João Mai --- flow/designs/asap7/aes-block/rules-base.json | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json index b862022943..e9fbea3933 100644 --- a/flow/designs/asap7/aes-block/rules-base.json +++ b/flow/designs/asap7/aes-block/rules-base.json @@ -24,7 +24,7 @@ "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1561, + "value": 1866, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -152.45, + "value": -243.45, "compare": ">=" }, "finish__design__instance__area": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -18.47, + "value": -43.48, "compare": ">=" } } \ No newline at end of file From 606fcf0d9152532efe6482981937567935db5c52 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=A3o=20Mai?= Date: Wed, 9 Jul 2025 17:19:49 -0300 Subject: [PATCH 167/198] flow: update mock-array MPL params MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: João Mai --- flow/designs/asap7/mock-array/config.mk | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/flow/designs/asap7/mock-array/config.mk b/flow/designs/asap7/mock-array/config.mk index 599dc6bed4..6b694315ff 100644 --- a/flow/designs/asap7/mock-array/config.mk +++ b/flow/designs/asap7/mock-array/config.mk @@ -26,6 +26,10 @@ export DIE_AREA = $(shell \ export MACRO_PLACE_HALO = 0 2.16 export RTLMP_BOUNDARY_WT = 0 export RTLMP_FLOW ?= 1 +export RTLMP_MAX_INST = 250 +export RTLMP_MIN_INST = 50 +export RTLMP_MAX_MACRO = 64 +export RTLMP_MIN_MACRO = 8 export BLOCKS ?= Element From f22634158e2fb52a738969af7ba4b3f282b73e70 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Wed, 9 Jul 2025 20:29:00 +0000 Subject: [PATCH 168/198] genElapsedTime.py: handle lines after the elapsed time line Previously the additional lines reset the elapsedTime & peak_memory. We only expect one such line so stop when it is found. Signed-off-by: Matt Liberty --- flow/util/genElapsedTime.py | 1 + 1 file changed, 1 insertion(+) diff --git a/flow/util/genElapsedTime.py b/flow/util/genElapsedTime.py index 93a762afc7..e22f42af1e 100755 --- a/flow/util/genElapsedTime.py +++ b/flow/util/genElapsedTime.py @@ -65,6 +65,7 @@ def print_log_dir_times(logdir, args): peak_memory = int( int(line.split("Peak memory: ")[1].split("KB")[0]) / 1024 ) + break # content hash for the result file alongside .log file is useful to # debug divergent results under what should be identical From 351845ad13f60fb8cc14f3397bebb524dc391828 Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Wed, 9 Jul 2025 14:17:13 -0700 Subject: [PATCH 169/198] Moved ODB hashing into its own method and made it compatible with pre-Python 3.8 Signed-off-by: Jeff Ng --- flow/util/genElapsedTime.py | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/flow/util/genElapsedTime.py b/flow/util/genElapsedTime.py index e1bca5d0f8..ad3e2c4f59 100755 --- a/flow/util/genElapsedTime.py +++ b/flow/util/genElapsedTime.py @@ -14,6 +14,26 @@ # ============================================================================== +def get_hash(f): + # content hash for the result file alongside .log file is useful to + # debug divergent results under what should be identical + # builds(such as local and CI builds) + for ext in [".odb", ".rtlil", ".v"]: + result_file = pathlib.Path( + str(f).replace("logs/", "results/").replace(".log", ext) + ) + if result_file.exists(): + hasher = hashlib.sha1() + with open(result_file, "rb") as odb_f: + while True: + chunk = odb_f.read(16 * 1024 * 1024) + if not chunk: + break + hasher.update(chunk) + return hasher.hexdigest() + return "N/A" + + def print_log_dir_times(logdir, args): first = True totalElapsed = 0 @@ -66,22 +86,7 @@ def print_log_dir_times(logdir, args): int(line.split("Peak memory: ")[1].split("KB")[0]) / 1024 ) - # content hash for the result file alongside .log file is useful to - # debug divergent results under what should be identical - # builds(such as local and CI builds) - for ext in [".odb", ".rtlil", ".v"]: - result_file = pathlib.Path( - str(f).replace("logs/", "results/").replace(".log", ext) - ) - if result_file.exists(): - hasher = hashlib.sha1() - with open(result_file, "rb") as odb_f: - while chunk := odb_f.read(16 * 1024 * 1024): - hasher.update(chunk) - odb_hash = hasher.hexdigest() - break - else: - odb_hash = "N/A" + odb_hash = get_hash(f) if not found: print("No elapsed time found in", str(f), file=sys.stderr) From 711ca2077f40a90882d4ed580f90880b241756bb Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Thu, 10 Jul 2025 00:07:38 +0000 Subject: [PATCH 170/198] added design configs for rapidus2hp platform incorporated review feedback Signed-off-by: Jeff Ng --- flow/designs/rapidus2hp/README.md | 14 ++ flow/designs/rapidus2hp/cva6/autotuner.json | 43 ++++++ flow/designs/rapidus2hp/cva6/config.mk | 122 +++++++++++++++ flow/designs/rapidus2hp/cva6/constraint.sdc | 11 ++ flow/designs/rapidus2hp/ethmac/config.mk | 12 ++ flow/designs/rapidus2hp/ethmac/constraint.sdc | 31 ++++ flow/designs/rapidus2hp/gcd/autotuner.json | 35 +++++ flow/designs/rapidus2hp/gcd/config.mk | 10 ++ flow/designs/rapidus2hp/gcd/constraint.sdc | 15 ++ .../rapidus2hp/hercules_is_int/config.mk | 139 ++++++++++++++++++ .../rapidus2hp/hercules_is_int/prects.sdc | 14 ++ flow/designs/rapidus2hp/ibex/config.mk | 29 ++++ flow/designs/rapidus2hp/ibex/constraint.sdc | 13 ++ .../rapidus2hp/ibex/constraint_pos_slack.sdc | 13 ++ flow/designs/rapidus2hp/jpeg/config.mk | 16 ++ .../rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc | 15 ++ 16 files changed, 532 insertions(+) create mode 100644 flow/designs/rapidus2hp/README.md create mode 100644 flow/designs/rapidus2hp/cva6/autotuner.json create mode 100644 flow/designs/rapidus2hp/cva6/config.mk create mode 100644 flow/designs/rapidus2hp/cva6/constraint.sdc create mode 100644 flow/designs/rapidus2hp/ethmac/config.mk create mode 100644 flow/designs/rapidus2hp/ethmac/constraint.sdc create mode 100644 flow/designs/rapidus2hp/gcd/autotuner.json create mode 100644 flow/designs/rapidus2hp/gcd/config.mk create mode 100644 flow/designs/rapidus2hp/gcd/constraint.sdc create mode 100644 flow/designs/rapidus2hp/hercules_is_int/config.mk create mode 100644 flow/designs/rapidus2hp/hercules_is_int/prects.sdc create mode 100644 flow/designs/rapidus2hp/ibex/config.mk create mode 100644 flow/designs/rapidus2hp/ibex/constraint.sdc create mode 100644 flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc create mode 100644 flow/designs/rapidus2hp/jpeg/config.mk create mode 100644 flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc diff --git a/flow/designs/rapidus2hp/README.md b/flow/designs/rapidus2hp/README.md new file mode 100644 index 0000000000..b95ec56e72 --- /dev/null +++ b/flow/designs/rapidus2hp/README.md @@ -0,0 +1,14 @@ +# Rapidus Environment Setup + +## Clone Rapidus Repo from Private GH + +The ORFS-specific files for the Rapidus platform are stored separately in the private rapidus repo. Clone out the repo into a separate directory and then set PLATFORM_HOME to point to it: + +``` +cd rapidus_platform_dir_goes_here +git clone http://github.com/The-OpenROAD-Project-private/rapidus +export PLATFORM_HOME=`pwd`/rapidus_platform_dir_goes_here +``` + +For more information, check out (http://github.com/The-OpenROAD-Project-private/rapidus) + diff --git a/flow/designs/rapidus2hp/cva6/autotuner.json b/flow/designs/rapidus2hp/cva6/autotuner.json new file mode 100644 index 0000000000..cc58f5fda7 --- /dev/null +++ b/flow/designs/rapidus2hp/cva6/autotuner.json @@ -0,0 +1,43 @@ +{ + "_SDC_FILE_PATH": "constraint.sdc", + "_SDC_CLK_PERIOD": { + "type": "float", + "minmax": [ + 990, + 1015 + ], + "step": 0 + }, + "CORE_UTILIZATION": { + "type": "int", + "minmax": [ + 25, + 45 + ], + "step": 1 + }, + "CTS_CLUSTER_SIZE": { + "type": "int", + "minmax": [ + 30, + 60 + ], + "step": 1 + }, + "CTS_CLUSTER_DIAMETER": { + "type": "int", + "minmax": [ + 15, + 25 + ], + "step": 1 + }, + "CORE_MARGIN": { + "type": "float", + "minmax": [ + 1.8, + 2.1 + ], + "step": 0 + } +} diff --git a/flow/designs/rapidus2hp/cva6/config.mk b/flow/designs/rapidus2hp/cva6/config.mk new file mode 100644 index 0000000000..c36324e323 --- /dev/null +++ b/flow/designs/rapidus2hp/cva6/config.mk @@ -0,0 +1,122 @@ +export PLATFORM = rapidus2hp + +export DESIGN_NAME = cva6 + +# Some files are listed specifically vs. sorted wilcard to control the order (makes Verific happy) +export SRC_HOME = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME) +export VERILOG_FILES = $(sort $(wildcard $(SRC_HOME)/common/local/util/*.sv)) \ + $(SRC_HOME)/core/include/config_pkg.sv \ + $(SRC_HOME)/core/include/cv32a65x_config_pkg.sv \ + $(SRC_HOME)/core/include/riscv_pkg.sv \ + $(SRC_HOME)/core/include/ariane_pkg.sv \ + $(SRC_HOME)/core/include/build_config_pkg.sv \ + $(SRC_HOME)/core/include/std_cache_pkg.sv \ + $(SRC_HOME)/core/include/wt_cache_pkg.sv \ + $(sort $(wildcard $(SRC_HOME)/vendor/pulp-platform/common_cells/src/*.sv)) \ + $(SRC_HOME)/core/cvfpu/src/fpnew_pkg.sv \ + $(sort $(wildcard $(SRC_HOME)/vendor/pulp-platform/axi/src/*.sv)) \ + $(SRC_HOME)/core/cvfpu/src/fpnew_cast_multi.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_classifier.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_divsqrt_multi.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_fma.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_fma_multi.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_noncomp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_block.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_fmt_slice.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_rounding.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_top.sv \ + $(sort $(wildcard $(SRC_HOME)/core/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/pmp/src/*.sv)) \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_pkg.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_amo.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_cmo.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_core_arbiter.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl_pe.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_memctrl.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_miss_handler.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_mshr.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_rtab.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_uncached.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_plru.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_random.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_pkg.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_arb.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/common/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/utils/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cva6_mmu/*.sv)) \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv \ + $(SRC_HOME)/core/cvxif_example/include/cvxif_instr_pkg.sv \ + $(sort $(wildcard $(SRC_HOME)/core/frontend/*.sv)) \ + $(SRC_HOME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \ + $(PLATFORM_DIR)/ram/verilog/fakeram7_64x256_shim.sv \ + $(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p64x256m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv \ + $(PLATFORM_DIR)/ram/verilog/fakeram7_128x64_shim.sv \ + $(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p128x64m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv \ + $(PLATFORM_DIR)/ram/verilog/fakeram7_64x28_shim.sv \ + $(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p64x28m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv \ + $(PLATFORM_DIR)/ram/verilog/fakeram7_64x25_shim.sv \ + $(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p64x25m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv + +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/common_cells/include \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/include + +export VERILOG_DEFINES += -D HPDCACHE_ASSERT_OFF + +export ADDITIONAL_LEFS = $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x256m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \ + $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p128x64m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \ + $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x28m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \ + $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x25m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef + +export ADDITIONAL_LIBS += $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x256m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \ + $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p128x64m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \ + $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x28m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \ + $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x25m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc + +# Must be defined before the ifeq's +export SYNTH_HDL_FRONTEND = slang +export SYNTH_HIERARCHICAL ?= 0 + +ifeq ($(SYNTH_HDL_FRONTEND),verific) + # Reduce utilization for verific since it runs into issues with DPL not being + # able to place instances or with one-site gap/overlap issues + export CORE_UTILIZATION = 35 +else + ifeq ($(SYNTH_HIERARCHICAL),1) + # Reduce the amount of resizing done between GPL and DPL + export EARLY_SIZING_CAP_RATIO = 6 + endif + export CORE_UTILIZATION = 45 +endif + +export CORE_MARGIN = 2 +export MACRO_PLACE_HALO = 2 2 + +export PLACE_DENSITY = 0.65 + +export ENABLE_DPO = 0 + +# a smoketest for this option, there are a +# few last gasp iterations +export SKIP_LAST_GASP ?= 1 + +# For use with SYNTH_HIERARCHICAL +export SYNTH_MINIMUM_KEEP_SIZE ?= 40000 diff --git a/flow/designs/rapidus2hp/cva6/constraint.sdc b/flow/designs/rapidus2hp/cva6/constraint.sdc new file mode 100644 index 0000000000..92605441dc --- /dev/null +++ b/flow/designs/rapidus2hp/cva6/constraint.sdc @@ -0,0 +1,11 @@ +# Derived from cva6_synth.tcl and Makefiles + +set clk_name main_clk +set clk_port clk_i +set clk_ports_list [list $clk_port] +set clk_period 1000 +set input_delay 0.46 +set output_delay 0.11 +create_clock [get_ports $clk_port] -name $clk_name -period $clk_period + +set_false_path -to [get_ports {rvfi_probes_o}] diff --git a/flow/designs/rapidus2hp/ethmac/config.mk b/flow/designs/rapidus2hp/ethmac/config.mk new file mode 100644 index 0000000000..b3507b64a9 --- /dev/null +++ b/flow/designs/rapidus2hp/ethmac/config.mk @@ -0,0 +1,12 @@ +export PLATFORM = rapidus2hp + +export DESIGN_NAME = ethmac + +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export ABC_AREA = 1 + +export CORE_UTILIZATION = 45 +export CORE_ASPECT_RATIO = 1 +export CORE_MARGIN = 0.75 +export PLACE_DENSITY = 0.70 diff --git a/flow/designs/rapidus2hp/ethmac/constraint.sdc b/flow/designs/rapidus2hp/ethmac/constraint.sdc new file mode 100644 index 0000000000..a4037db532 --- /dev/null +++ b/flow/designs/rapidus2hp/ethmac/constraint.sdc @@ -0,0 +1,31 @@ +set top_clk_name wb_clk_i +set clk_period 875 +set clk_io_pct 0.2 +set clk_port [get_ports $top_clk_name] +create_clock -name $top_clk_name -period $clk_period $clk_port +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs] + +set tx_clk_name mtx_clk_pad_i +set tx_clk_port [get_ports $tx_clk_name] +set tx_clk_period 300 +create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port +set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port] +set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs +set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs] + +set rx_clk_name mrx_clk_pad_i +set rx_clk_port [get_ports $rx_clk_name] +set rx_clk_period 300 +create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port +set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port] +set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs +set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs] + +set_clock_groups -name core_clock -logically_exclusive \ + -group [get_clocks $top_clk_name] \ + -group [get_clocks $tx_clk_name] \ + -group [get_clocks $rx_clk_name] + +set_max_fanout 10 [current_design] diff --git a/flow/designs/rapidus2hp/gcd/autotuner.json b/flow/designs/rapidus2hp/gcd/autotuner.json new file mode 100644 index 0000000000..e622bbf82d --- /dev/null +++ b/flow/designs/rapidus2hp/gcd/autotuner.json @@ -0,0 +1,35 @@ +{ + "_SDC_FILE_PATH": "constraint.sdc", + "_SDC_CLK_PERIOD": { + "type": "float", + "minmax": [ + 180, + 300 + ], + "step": 0 + }, + "CORE_UTILIZATION": { + "type": "float", + "minmax": [ + 21, + 60 + ], + "step": 0 + }, + "CTS_CLUSTER_SIZE": { + "type": "int", + "minmax": [ + 10, + 200 + ], + "step": 1 + }, + "CTS_CLUSTER_DIAMETER": { + "type": "int", + "minmax": [ + 20, + 400 + ], + "step": 1 + } +} diff --git a/flow/designs/rapidus2hp/gcd/config.mk b/flow/designs/rapidus2hp/gcd/config.mk new file mode 100644 index 0000000000..0dae84d592 --- /dev/null +++ b/flow/designs/rapidus2hp/gcd/config.mk @@ -0,0 +1,10 @@ +export DESIGN_NICKNAME = gcd +export DESIGN_NAME = gcd +export PLATFORM = rapidus2hp + +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc + +export CORE_UTILIZATION = 30 +export CORE_MARGIN = .75 +export PLACE_DENSITY = 0.42 diff --git a/flow/designs/rapidus2hp/gcd/constraint.sdc b/flow/designs/rapidus2hp/gcd/constraint.sdc new file mode 100644 index 0000000000..fd5cb2c47b --- /dev/null +++ b/flow/designs/rapidus2hp/gcd/constraint.sdc @@ -0,0 +1,15 @@ +current_design gcd + +set clk_name core_clock +set clk_port_name clk +set clk_period 185 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/rapidus2hp/hercules_is_int/config.mk b/flow/designs/rapidus2hp/hercules_is_int/config.mk new file mode 100644 index 0000000000..6ccb921da5 --- /dev/null +++ b/flow/designs/rapidus2hp/hercules_is_int/config.mk @@ -0,0 +1,139 @@ +export PLATFORM = rapidus2hp + +export DESIGN_NAME = hercules_is_int + +export SRC_HOME = /platforms/Rapidus/designs/hercules_is_int +export VERILOG_FILES = $(SRC_HOME)/hercules_issue/verilog/hercules_is_defines.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_flush_compare.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_gcbfwd.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_gclfwd.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_gcxfwd.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_gfwd.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_grbt_bnk.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_grbt.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_grf_bnk_rd.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_grf_bnk.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_grf_bnk_wr.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_grf.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_int_comm.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_int_ela.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_int_fwd.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_int_pipe.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_int.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq2_age.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq2_entry.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq2_ncentry.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq2.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq_age.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq_dep.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq_entry.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq_free_list.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq_ncentry.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq_top_dep.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_ls_uop_ctl_dec.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_mx0_entry.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_mx0.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_mx1_entry.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_mx1.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_mxq_age.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_mxq_dep.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_mxq_free_list.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_mxq_ncentry.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_mxq_slow_age.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_mxq_slow_dep.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_mxq_top_dep.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_params.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_pcrf_bnk.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_pcrf.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_resc_cnt1s_4b.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_resc_ix.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_resc_ls.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_resc_tag.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_stid_compare.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_sxq_age.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_sxq_dep.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_sxq_entry.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_sxq_free_list.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_sxq_ncentry.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_sxq_slow_age.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_sxq_slow_dep.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_sxq.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_sxq_top_dep.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_vec_comm.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_vec_ela.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_vec_pipe.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_vec_res_ctl.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_vec.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_vrbt_rmux.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_vrbt.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_vrbt_wmux.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_vrf_port_arb.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_vxq_age.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_vxq_entry.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_vxq_free_list.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_vxq_pipe.sv \ + $(SRC_HOME)/hercules_issue/verilog/hercules_is_vxq.sv \ + $(SRC_HOME)/shared/verilog/hercules_ccpass.sv \ + $(SRC_HOME)/shared/verilog/hercules_core_defines.sv \ + $(SRC_HOME)/shared/verilog/hercules_dffr_rstval.sv \ + $(SRC_HOME)/shared/verilog/hercules_dffr.sv \ + $(SRC_HOME)/shared/verilog/hercules_dff.sv \ + $(SRC_HOME)/shared/verilog/hercules_ecc_chk.sv \ + $(SRC_HOME)/shared/verilog/hercules_ecc_correct.sv \ + $(SRC_HOME)/shared/verilog/hercules_ecc_gen.sv \ + $(SRC_HOME)/shared/verilog/hercules_ecc_matrix.sv \ + $(SRC_HOME)/shared/verilog/hercules_ecc_syndrome_correct.sv \ + $(SRC_HOME)/shared/verilog/hercules_ela_defines.sv \ + $(SRC_HOME)/shared/verilog/hercules_fcvt64.sv \ + $(SRC_HOME)/shared/verilog/hercules_flush_compare.sv \ + $(SRC_HOME)/shared/verilog/hercules_flush_type_defines.sv \ + $(SRC_HOME)/shared/verilog/hercules_header.sv \ + $(SRC_HOME)/shared/verilog/hercules_ifid_lsm_regcnt_armthm.sv \ + $(SRC_HOME)/shared/verilog/hercules_ifid_lsm_regcnt_neon.sv \ + $(SRC_HOME)/shared/verilog/hercules_ifid_lsm_regcnt.sv \ + $(SRC_HOME)/shared/verilog/hercules_ifid_mop_t16_iqual.sv \ + $(SRC_HOME)/shared/verilog/hercules_ifid_mop_t32p_iqual.sv \ + $(SRC_HOME)/shared/verilog/hercules_ifid_mq_props.sv \ + $(SRC_HOME)/shared/verilog/hercules_invmask64.sv \ + $(SRC_HOME)/shared/verilog/hercules_lsl2_defines.sv \ + $(SRC_HOME)/shared/verilog/hercules_params.sv \ + $(SRC_HOME)/shared/verilog/hercules_pdp_period.sv \ + $(SRC_HOME)/shared/verilog/hercules_pdp_tracker_ls.sv \ + $(SRC_HOME)/shared/verilog/hercules_pdp_tracker.sv \ + $(SRC_HOME)/shared/verilog/hercules_plru_arb.sv \ + $(SRC_HOME)/shared/verilog/hercules_plru_order.sv \ + $(SRC_HOME)/shared/verilog/hercules_pmu_defines.sv \ + $(SRC_HOME)/shared/verilog/hercules_shared_params.sv \ + $(SRC_HOME)/models/cells/generic/hercules_ck_gate.sv \ + $(SRC_HOME)/models/cells/generic/hercules_nand_gate.sv \ + $(SRC_HOME)/models/cells/generic/hercules_nor_gate.sv + +export VERILOG_INCLUDE_DIRS = $(SRC_HOME)/hercules_issue/verilog \ + $(SRC_HOME)/shared/verilog \ + $(SRC_HOME)/models/cells/generic + +export VERILOG_DEFINES += + +export ADDITIONAL_LEFS = +export ADDITIONAL_LIBS += + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/prects.sdc + +# Must be defined before the ifeq's +export SYNTH_HDL_FRONTEND = slang +export SYNTH_HIERARCHICAL ?= 0 + +export CORE_UTILIZATION = 25 + +export CORE_MARGIN = 2 +export MACRO_PLACE_HALO = 4 4 + +export PLACE_DENSITY = 0.58 + +# a smoketest for this option, there are a +# few last gasp iterations +export SKIP_LAST_GASP ?= 1 + +# For use with SYNTH_HIERARCHICAL +export SYNTH_MINIMUM_KEEP_SIZE ?= 40000 diff --git a/flow/designs/rapidus2hp/hercules_is_int/prects.sdc b/flow/designs/rapidus2hp/hercules_is_int/prects.sdc new file mode 100644 index 0000000000..0444b6a48e --- /dev/null +++ b/flow/designs/rapidus2hp/hercules_is_int/prects.sdc @@ -0,0 +1,14 @@ +#set sdc_version 2.1 +set sdc_version 1.4 +current_design hercules_is_int + +set clk_period 250 + +set_max_fanout 32 [current_design] +set_load 10 [all_outputs] +set_max_capacitance 10 [all_inputs] + +create_clock -name "clk" -add -period $clk_period -waveform [list 0.0 [expr 0.5*$clk_period]] [get_ports clk] + + + diff --git a/flow/designs/rapidus2hp/ibex/config.mk b/flow/designs/rapidus2hp/ibex/config.mk new file mode 100644 index 0000000000..f29c39a686 --- /dev/null +++ b/flow/designs/rapidus2hp/ibex/config.mk @@ -0,0 +1,29 @@ +export PLATFORM = rapidus2hp + +export DESIGN_NICKNAME = ibex +export DESIGN_NAME = ibex_core + +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \ + $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v + +export VERILOG_INCLUDE_DIRS = \ + $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/ + +export SYNTH_HDL_FRONTEND = slang + +# if FLOW_VARIANT == pos_slack, use an SDC file that has a larger clock +# resulting in positive slack +ifeq ($(FLOW_VARIANT),pos_slack) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_pos_slack.sdc +else +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +endif + +export CORE_UTILIZATION = 45 +export CORE_ASPECT_RATIO = 1 +export CORE_MARGIN = 0.75 +export PLACE_DENSITY_LB_ADDON = 0.20 + +export ENABLE_DPO = 0 + +export TNS_END_PERCENT = 100 diff --git a/flow/designs/rapidus2hp/ibex/constraint.sdc b/flow/designs/rapidus2hp/ibex/constraint.sdc new file mode 100644 index 0000000000..4ce87915ab --- /dev/null +++ b/flow/designs/rapidus2hp/ibex/constraint.sdc @@ -0,0 +1,13 @@ +set clk_name core_clock +set clk_port_name clk_i +set clk_period 790 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc b/flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc new file mode 100644 index 0000000000..7d9d39b7c1 --- /dev/null +++ b/flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc @@ -0,0 +1,13 @@ +set clk_name core_clock +set clk_port_name clk_i +set clk_period 1468 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/rapidus2hp/jpeg/config.mk b/flow/designs/rapidus2hp/jpeg/config.mk new file mode 100644 index 0000000000..6996f9da0e --- /dev/null +++ b/flow/designs/rapidus2hp/jpeg/config.mk @@ -0,0 +1,16 @@ +export PLATFORM = rapidus2hp + +export DESIGN_NAME = jpeg_encoder +export DESIGN_NICKNAME = jpeg + +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc +export ABC_AREA = 1 + +export CORE_UTILIZATION = 35 +export CORE_ASPECT_RATIO = 1 +export CORE_MARGIN = 0.75 +export PLACE_DENSITY = 0.62 + +export TNS_END_PERCENT = 100 diff --git a/flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc b/flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc new file mode 100644 index 0000000000..6b6ad12acf --- /dev/null +++ b/flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc @@ -0,0 +1,15 @@ +current_design jpeg_encoder + +set clk_name clk +set clk_port_name clk +set clk_period 425 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] From a64153d2879de4527a20a741b14498e4e5f062e8 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Thu, 10 Jul 2025 20:13:01 +0000 Subject: [PATCH 171/198] designs/gf12/bp_single/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | finish__timing__setup__ws | -144.83 | -97.15 | Tighten | | finish__timing__drv__hold_violation_count | 479 | 740 | Failing | | finish__timing__wns_percent_delay | -12.6 | -10.0 | Tighten | Signed-off-by: Matt Liberty --- flow/designs/gf12/bp_single/rules-base.json | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/flow/designs/gf12/bp_single/rules-base.json b/flow/designs/gf12/bp_single/rules-base.json index be33224b80..561e77cdbd 100644 --- a/flow/designs/gf12/bp_single/rules-base.json +++ b/flow/designs/gf12/bp_single/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -144.83, + "value": -97.15, "compare": ">=" }, "finish__design__instance__area": { @@ -60,11 +60,11 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 479, + "value": 740, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -12.6, + "value": -10.0, "compare": ">=" } } \ No newline at end of file From 58e0fb315d72b060bcaa15ae23cf948022a808b6 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Fri, 11 Jul 2025 02:54:38 +0000 Subject: [PATCH 172/198] update OR Signed-off-by: Matt Liberty --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index e9a886276c..153afd9c34 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit e9a886276c7f89da3b6246a7c8e4c8982a0addfd +Subproject commit 153afd9c34c2d552586cff4d3060380d99f694a9 From 1cd6a0ca7de9045713af16de6e7a07517a6d94db Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Fri, 11 Jul 2025 03:25:24 +0000 Subject: [PATCH 173/198] tclfmt/lint the Rapidus design .sdc files Signed-off-by: Matt Liberty --- flow/designs/rapidus2hp/ethmac/constraint.sdc | 30 ++++++++++++------- flow/designs/rapidus2hp/gcd/constraint.sdc | 10 ++++--- .../rapidus2hp/hercules_is_int/prects.sdc | 6 ++-- flow/designs/rapidus2hp/ibex/constraint.sdc | 8 +++-- .../rapidus2hp/ibex/constraint_pos_slack.sdc | 8 +++-- .../rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc | 8 +++-- 6 files changed, 42 insertions(+), 28 deletions(-) diff --git a/flow/designs/rapidus2hp/ethmac/constraint.sdc b/flow/designs/rapidus2hp/ethmac/constraint.sdc index a4037db532..50e470ebba 100644 --- a/flow/designs/rapidus2hp/ethmac/constraint.sdc +++ b/flow/designs/rapidus2hp/ethmac/constraint.sdc @@ -4,28 +4,36 @@ set clk_io_pct 0.2 set clk_port [get_ports $top_clk_name] create_clock -name $top_clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs] +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $top_clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $top_clk_name \ + [all_outputs] set tx_clk_name mtx_clk_pad_i set tx_clk_port [get_ports $tx_clk_name] set tx_clk_period 300 create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port -set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port] -set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs -set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs] +set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] \ + $tx_clk_port] +set_input_delay [expr { $tx_clk_period * $clk_io_pct }] -clock $tx_clk_name \ + $mtx_non_clock_inputs +set_output_delay [expr { $tx_clk_period * $clk_io_pct }] -clock $tx_clk_name \ + [all_outputs] set rx_clk_name mrx_clk_pad_i set rx_clk_port [get_ports $rx_clk_name] set rx_clk_period 300 create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port -set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port] -set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs -set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs] +set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] \ + $rx_clk_port] +set_input_delay [expr { $rx_clk_period * $clk_io_pct }] -clock $rx_clk_name \ + $mrx_non_clock_inputs +set_output_delay [expr { $rx_clk_period * $clk_io_pct }] -clock $rx_clk_name \ + [all_outputs] set_clock_groups -name core_clock -logically_exclusive \ - -group [get_clocks $top_clk_name] \ - -group [get_clocks $tx_clk_name] \ - -group [get_clocks $rx_clk_name] + -group [get_clocks $top_clk_name] \ + -group [get_clocks $tx_clk_name] \ + -group [get_clocks $rx_clk_name] set_max_fanout 10 [current_design] diff --git a/flow/designs/rapidus2hp/gcd/constraint.sdc b/flow/designs/rapidus2hp/gcd/constraint.sdc index fd5cb2c47b..3eb0db2391 100644 --- a/flow/designs/rapidus2hp/gcd/constraint.sdc +++ b/flow/designs/rapidus2hp/gcd/constraint.sdc @@ -1,15 +1,17 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk set clk_period 185 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + [all_outputs] diff --git a/flow/designs/rapidus2hp/hercules_is_int/prects.sdc b/flow/designs/rapidus2hp/hercules_is_int/prects.sdc index 0444b6a48e..934de6be54 100644 --- a/flow/designs/rapidus2hp/hercules_is_int/prects.sdc +++ b/flow/designs/rapidus2hp/hercules_is_int/prects.sdc @@ -8,7 +8,5 @@ set_max_fanout 32 [current_design] set_load 10 [all_outputs] set_max_capacitance 10 [all_inputs] -create_clock -name "clk" -add -period $clk_period -waveform [list 0.0 [expr 0.5*$clk_period]] [get_ports clk] - - - +create_clock -name "clk" -add -period $clk_period \ + -waveform [list 0.0 [expr { 0.5 * $clk_period }]] [get_ports clk] diff --git a/flow/designs/rapidus2hp/ibex/constraint.sdc b/flow/designs/rapidus2hp/ibex/constraint.sdc index 4ce87915ab..1465ae6069 100644 --- a/flow/designs/rapidus2hp/ibex/constraint.sdc +++ b/flow/designs/rapidus2hp/ibex/constraint.sdc @@ -1,4 +1,4 @@ -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 790 set clk_io_pct 0.2 @@ -9,5 +9,7 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + [all_outputs] diff --git a/flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc b/flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc index 7d9d39b7c1..d714d428ae 100644 --- a/flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc +++ b/flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc @@ -1,4 +1,4 @@ -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 1468 set clk_io_pct 0.2 @@ -9,5 +9,7 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + [all_outputs] diff --git a/flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc b/flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc index 6b6ad12acf..9f0d6c6a9b 100644 --- a/flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc +++ b/flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc @@ -1,6 +1,6 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 425 set clk_io_pct 0.2 @@ -11,5 +11,7 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + [all_outputs] From e7486aeab8216961a135e6b9a5ea59f73d621bcc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 11 Jul 2025 13:30:57 +0200 Subject: [PATCH 174/198] make: silently suppress warnings in read_liberty.tcl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes and `make gui_open` and also `make floorplan` Reduce log spam: don't log command that suppresses warning Signed-off-by: Øyvind Harboe --- flow/platforms/asap7/liberty_suppressions.tcl | 2 +- flow/scripts/load.tcl | 6 ------ flow/scripts/read_liberty.tcl | 6 ++++++ 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/flow/platforms/asap7/liberty_suppressions.tcl b/flow/platforms/asap7/liberty_suppressions.tcl index f8de273475..3278afd965 100644 --- a/flow/platforms/asap7/liberty_suppressions.tcl +++ b/flow/platforms/asap7/liberty_suppressions.tcl @@ -1,4 +1,4 @@ # To remove [WARNING STA-1212] from the logs for ASAP7. # /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz line 13178, timing group from output port. # Added following suppress_message -log_cmd suppress_message STA 1212 +suppress_message STA 1212 diff --git a/flow/scripts/load.tcl b/flow/scripts/load.tcl index 78c678081d..437e45bf63 100644 --- a/flow/scripts/load.tcl +++ b/flow/scripts/load.tcl @@ -3,12 +3,6 @@ source $::env(SCRIPTS_DIR)/util.tcl source $::env(SCRIPTS_DIR)/report_metrics.tcl proc load_design { design_file sdc_file } { - # Source platform-related Tcl command (initially for suppressing Liberty - # warnings - if { [env_var_exists_and_non_empty PLATFORM_TCL] } { - log_cmd source $::env(PLATFORM_TCL) - } - # Read liberty files source $::env(SCRIPTS_DIR)/read_liberty.tcl diff --git a/flow/scripts/read_liberty.tcl b/flow/scripts/read_liberty.tcl index 89ff2df733..f13178bace 100644 --- a/flow/scripts/read_liberty.tcl +++ b/flow/scripts/read_liberty.tcl @@ -1,3 +1,9 @@ +# Source platform-related Tcl command (initially for suppressing Liberty +# warnings +if { [env_var_exists_and_non_empty PLATFORM_TCL] } { + source $::env(PLATFORM_TCL) +} + #Read Liberty if { [env_var_exists_and_non_empty CORNERS] } { # corners From 232e59ede37eaf2f4518b4d41a50e3a3fe856b09 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 11 Jul 2025 13:30:57 +0200 Subject: [PATCH 175/198] make: silently suppress warnings in read_liberty.tcl, review feedback MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/scripts/load.tcl | 3 ++- flow/scripts/open.tcl | 6 +++--- flow/scripts/read_liberty.tcl | 6 ------ flow/scripts/util.tcl | 6 ++++++ 4 files changed, 11 insertions(+), 10 deletions(-) diff --git a/flow/scripts/load.tcl b/flow/scripts/load.tcl index 437e45bf63..7b1f322308 100644 --- a/flow/scripts/load.tcl +++ b/flow/scripts/load.tcl @@ -3,7 +3,8 @@ source $::env(SCRIPTS_DIR)/util.tcl source $::env(SCRIPTS_DIR)/report_metrics.tcl proc load_design { design_file sdc_file } { - # Read liberty files + source_env_var_if_exists PLATFORM_TCL + source $::env(SCRIPTS_DIR)/read_liberty.tcl # Read design files diff --git a/flow/scripts/open.tcl b/flow/scripts/open.tcl index 36659892e0..4d8b306326 100644 --- a/flow/scripts/open.tcl +++ b/flow/scripts/open.tcl @@ -1,10 +1,10 @@ source $::env(SCRIPTS_DIR)/util.tcl -# Read liberty files + +source_env_var_if_exists PLATFORM_TCL + source $::env(SCRIPTS_DIR)/read_liberty.tcl -# Read def if { [env_var_exists_and_non_empty DEF_FILE] } { - # Read lef log_cmd read_lef $::env(TECH_LEF) log_cmd read_lef $::env(SC_LEF) if { [env_var_exists_and_non_empty ADDITIONAL_LEFS] } { diff --git a/flow/scripts/read_liberty.tcl b/flow/scripts/read_liberty.tcl index f13178bace..89ff2df733 100644 --- a/flow/scripts/read_liberty.tcl +++ b/flow/scripts/read_liberty.tcl @@ -1,9 +1,3 @@ -# Source platform-related Tcl command (initially for suppressing Liberty -# warnings -if { [env_var_exists_and_non_empty PLATFORM_TCL] } { - source $::env(PLATFORM_TCL) -} - #Read Liberty if { [env_var_exists_and_non_empty CORNERS] } { # corners diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl index c7739f529f..86ede2499c 100644 --- a/flow/scripts/util.tcl +++ b/flow/scripts/util.tcl @@ -205,3 +205,9 @@ proc place_density_with_lb_addon { } { } return $place_density } + +proc source_env_var_if_exists { env_var } { + if { [env_var_exists_and_non_empty $env_var] } { + source $::env($env_var) + } +} From 9e6d096956db5f804fbb03fdae9217212d90e17a Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Fri, 11 Jul 2025 17:03:55 +0000 Subject: [PATCH 176/198] Update metrics designs/ihp-sg13g2/aes/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | placeopt__design__instance__count__stdcell | 18996 | 18986 | Tighten | | globalroute__antenna_diodes_count | 166 | 6 | Tighten | | detailedroute__antenna_diodes_count | 21 | 39 | Failing | designs/sky130hd/aes/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | globalroute__antenna_diodes_count | 442 | 148 | Tighten | | detailedroute__route__wirelength | 677310 | 783010 | Failing | | detailedroute__antenna_diodes_count | 40 | 16 | Tighten | | finish__timing__setup__ws | -0.61 | -0.1 | Tighten | designs/sky130hs/jpeg/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | globalroute__antenna_diodes_count | 201 | 166 | Tighten | | detailedroute__antenna__violating__nets | 0 | 1 | Failing | designs/ihp-sg13g2/riscv32i/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | placeopt__design__instance__area | 171401 | 170435 | Tighten | | globalroute__antenna_diodes_count | 4 | 0 | Tighten | | detailedroute__route__wirelength | 534072 | 511850 | Tighten | | detailedroute__antenna_diodes_count | 5 | 12 | Failing | Signed-off-by: Matt Liberty --- flow/designs/ihp-sg13g2/aes/rules-base.json | 6 +++--- flow/designs/ihp-sg13g2/riscv32i/rules-base.json | 8 ++++---- flow/designs/sky130hd/aes/rules-base.json | 8 ++++---- flow/designs/sky130hs/jpeg/rules-base.json | 4 ++-- tools/OpenROAD | 2 +- 5 files changed, 14 insertions(+), 14 deletions(-) diff --git a/flow/designs/ihp-sg13g2/aes/rules-base.json b/flow/designs/ihp-sg13g2/aes/rules-base.json index 263fe9108d..8d1832de8c 100644 --- a/flow/designs/ihp-sg13g2/aes/rules-base.json +++ b/flow/designs/ihp-sg13g2/aes/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 18996, + "value": 18986, "compare": "<=" }, "detailedplace__design__violations": { @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 166, + "value": 6, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 21, + "value": 39, "compare": "<=" }, "finish__timing__setup__ws": { diff --git a/flow/designs/ihp-sg13g2/riscv32i/rules-base.json b/flow/designs/ihp-sg13g2/riscv32i/rules-base.json index 4a5905cd8e..1559d3db81 100644 --- a/flow/designs/ihp-sg13g2/riscv32i/rules-base.json +++ b/flow/designs/ihp-sg13g2/riscv32i/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 171401, + "value": 170435, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 4, + "value": 0, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 534072, + "value": 511850, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 5, + "value": 12, "compare": "<=" }, "finish__timing__setup__ws": { diff --git a/flow/designs/sky130hd/aes/rules-base.json b/flow/designs/sky130hd/aes/rules-base.json index 8427199c0d..32771e8a71 100644 --- a/flow/designs/sky130hd/aes/rules-base.json +++ b/flow/designs/sky130hd/aes/rules-base.json @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 442, + "value": 148, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 677310, + "value": 783010, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,11 +44,11 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 40, + "value": 16, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.61, + "value": -0.1, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/sky130hs/jpeg/rules-base.json b/flow/designs/sky130hs/jpeg/rules-base.json index a69feb23d7..6bbaa98dba 100644 --- a/flow/designs/sky130hs/jpeg/rules-base.json +++ b/flow/designs/sky130hs/jpeg/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 201, + "value": 166, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -40,7 +40,7 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 0, + "value": 1, "compare": "<=" }, "detailedroute__antenna_diodes_count": { diff --git a/tools/OpenROAD b/tools/OpenROAD index 153afd9c34..3ed3271270 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 153afd9c34c2d552586cff4d3060380d99f694a9 +Subproject commit 3ed3271270f98a349fb6005755e91155fa3a755c From 62cd9726aeb41f5ec368a05ba966e9ab942b0457 Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Thu, 10 Jul 2025 22:24:50 +0000 Subject: [PATCH 177/198] make hierarchical synth the default for rapidus2hp cva6 Signed-off-by: Jeff Ng --- flow/designs/rapidus2hp/cva6/config.mk | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/flow/designs/rapidus2hp/cva6/config.mk b/flow/designs/rapidus2hp/cva6/config.mk index c36324e323..de97cfcd7a 100644 --- a/flow/designs/rapidus2hp/cva6/config.mk +++ b/flow/designs/rapidus2hp/cva6/config.mk @@ -93,17 +93,15 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constr # Must be defined before the ifeq's export SYNTH_HDL_FRONTEND = slang -export SYNTH_HIERARCHICAL ?= 0 +export SYNTH_HIERARCHICAL = 1 ifeq ($(SYNTH_HDL_FRONTEND),verific) # Reduce utilization for verific since it runs into issues with DPL not being # able to place instances or with one-site gap/overlap issues export CORE_UTILIZATION = 35 else - ifeq ($(SYNTH_HIERARCHICAL),1) - # Reduce the amount of resizing done between GPL and DPL - export EARLY_SIZING_CAP_RATIO = 6 - endif + # Reduce the amount of resizing done between GPL and DPL + export EARLY_SIZING_CAP_RATIO = 6 export CORE_UTILIZATION = 45 endif From 62490a947186c70d8aeee4e4f1aaf76a8947e891 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 11 Jul 2025 19:07:07 +0200 Subject: [PATCH 178/198] scripts: use source_env_var_if_exists utility fn consistently MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/scripts/cts.tcl | 4 +--- flow/scripts/detail_route.tcl | 4 +--- flow/scripts/global_route.tcl | 4 +--- flow/scripts/pdn.tcl | 4 +--- 4 files changed, 4 insertions(+), 12 deletions(-) diff --git a/flow/scripts/cts.tcl b/flow/scripts/cts.tcl index 5865a19485..0fe80f63ad 100644 --- a/flow/scripts/cts.tcl +++ b/flow/scripts/cts.tcl @@ -75,9 +75,7 @@ if { ![env_var_equals SKIP_CTS_REPAIR_TIMING 1] } { report_metrics 4 "cts final" -if { [env_var_exists_and_non_empty POST_CTS_TCL] } { - source $::env(POST_CTS_TCL) -} +source_env_var_if_exists POST_CTS_TCL write_db $::env(RESULTS_DIR)/4_1_cts.odb write_sdc -no_timestamp $::env(RESULTS_DIR)/4_cts.sdc diff --git a/flow/scripts/detail_route.tcl b/flow/scripts/detail_route.tcl index 0ec28b2135..28eccba75c 100644 --- a/flow/scripts/detail_route.tcl +++ b/flow/scripts/detail_route.tcl @@ -62,9 +62,7 @@ if { ![env_var_equals SKIP_ANTENNA_REPAIR_POST_DRT 1] } { utl::metric_int "antenna_diodes_count" -1 } -if { [env_var_exists_and_non_empty POST_DETAIL_ROUTE_TCL] } { - source $::env(POST_DETAIL_ROUTE_TCL) -} +source_env_var_if_exists POST_DETAIL_ROUTE_TCL check_antennas -report_file $env(REPORTS_DIR)/drt_antennas.log diff --git a/flow/scripts/global_route.tcl b/flow/scripts/global_route.tcl index 360a0067cc..51fab8d4ca 100644 --- a/flow/scripts/global_route.tcl +++ b/flow/scripts/global_route.tcl @@ -6,9 +6,7 @@ load_design 4_cts.odb 4_cts.sdc # This proc is here to allow us to use 'return' to return early from this # file which is sourced proc global_route_helper { } { - if { [env_var_exists_and_non_empty PRE_GLOBAL_ROUTE] } { - source $::env(PRE_GLOBAL_ROUTE) - } + source_env_var_if_exists PRE_GLOBAL_ROUTE proc do_global_route { } { set all_args [concat [list \ diff --git a/flow/scripts/pdn.tcl b/flow/scripts/pdn.tcl index 628c4727c5..72d2c55c14 100644 --- a/flow/scripts/pdn.tcl +++ b/flow/scripts/pdn.tcl @@ -5,9 +5,7 @@ load_design 2_3_floorplan_tapcell.odb 2_1_floorplan.sdc source $::env(PDN_TCL) pdngen -if { [env_var_exists_and_non_empty POST_PDN_TCL] } { - source $::env(POST_PDN_TCL) -} +source_env_var_if_exists POST_PDN_TCL # Check all supply nets set block [ord::get_db_block] From 7c03d50902a5c9f4f96b0efe2f1e5eb7f845c9b3 Mon Sep 17 00:00:00 2001 From: Jack Luar Date: Sat, 12 Jul 2025 18:12:58 +0000 Subject: [PATCH 179/198] fix synth_preamble syntax Signed-off-by: Jack Luar --- flow/scripts/synth_preamble.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl index 5419d28b8a..339ebf621e 100644 --- a/flow/scripts/synth_preamble.tcl +++ b/flow/scripts/synth_preamble.tcl @@ -141,7 +141,7 @@ proc convert_liberty_areas { } { continue } set area [rtlil::get_attr -string -mod $cell area] - if { $found_cell == "" || [$area < $found_cell_area] } { + if { $found_cell == "" || $area < $found_cell_area } { set found_cell $cell set found_cell_area $area } From a006cf4e44eddd6baff29e5febbe61e1fc5e7edd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 14 Jul 2025 21:25:19 +0200 Subject: [PATCH 180/198] synth: Adjust verific port naming to match slang MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Before module cva6 input [0:0] clk_i input [0:0] rst_ni input [0:0] ipi_i input [0:0] time_irq_i input [0:0] debug_req_i output [0:0] rvfi_probes_o.csr.dcsr_q.ebreakvs output [0:0] rvfi_probes_o.csr.dcsr_q.ebreakvu output [0:0] rvfi_probes_o.csr.dcsr_q.ebreakm output [0:0] rvfi_probes_o.csr.dcsr_q.zero1 output [0:0] rvfi_probes_o.csr.dcsr_q.ebreaks output [0:0] rvfi_probes_o.csr.dcsr_q.ebreaku output [0:0] rvfi_probes_o.csr.dcsr_q.stepie output [0:0] rvfi_probes_o.csr.dcsr_q.stopcount output [0:0] rvfi_probes_o.csr.dcsr_q.stoptime output [0:0] rvfi_probes_o.csr.dcsr_q.v output [0:0] rvfi_probes_o.csr.dcsr_q.mprven output [0:0] rvfi_probes_o.csr.dcsr_q.nmip output [0:0] rvfi_probes_o.csr.dcsr_q.step output [0:0] rvfi_probes_o.csr.fiom_q output [0:0] rvfi_probes_o.csr.pmpcfg_q[63].locked output [0:0] rvfi_probes_o.csr.pmpcfg_q[63].access_type.x output [0:0] rvfi_probes_o.csr.pmpcfg_q[63].access_type.w output [0:0] rvfi_probes_o.csr.pmpcfg_q[63].access_type.r output [0:0] rvfi_probes_o.csr.pmpcfg_q[62].locked output [0:0] rvfi_probes_o.csr.pmpcfg_q[62].access_type.x output [0:0] rvfi_probes_o.csr.pmpcfg_q[62].access_type.w output [0:0] rvfi_probes_o.csr.pmpcfg_q[62].access_type.r output [0:0] rvfi_probes_o.csr.pmpcfg_q[61].locked ... and more After module cva6 input [0:0] clk_i input [0:0] rst_ni input [31:0] boot_addr_i input [31:0] hart_id_i input [1:0] irq_i input [0:0] ipi_i input [0:0] time_irq_i input [0:0] debug_req_i output [4294:0] rvfi_probes_o output [256:0] cvxif_req_o input [113:0] cvxif_resp_i output [373:0] noc_req_o input [145:0] noc_resp_i Signed-off-by: Martin Povišer --- flow/scripts/synth_preamble.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl index 339ebf621e..21cf176be5 100644 --- a/flow/scripts/synth_preamble.tcl +++ b/flow/scripts/synth_preamble.tcl @@ -59,6 +59,7 @@ proc read_design_sources { } { verific -vlog-define {*}$::env(VERILOG_DEFINES) } verific -sv2012 {*}$::env(VERILOG_FILES) + verific -import -no-split-complex-ports $::env(DESIGN_NAME) } elseif { ![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND] } { verilog_defaults -push if { [env_var_exists_and_non_empty VERILOG_DEFINES] } { From 3e49dbc34818077c58a1999ac9129732d1f33b51 Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Mon, 14 Jul 2025 17:25:00 +0000 Subject: [PATCH 181/198] Updated hercules_is_int for slang; Added initial I/O constraints for cva6 fixed tcllint complaints fixed one more space issue long line and unneeded expr Signed-off-by: Jeff Ng --- .../rapidus2hp/cva6/io_constraints.tcl | 46 +++++++++++++++++++ .../rapidus2hp/hercules_is_int/config.mk | 4 +- 2 files changed, 48 insertions(+), 2 deletions(-) create mode 100644 flow/designs/rapidus2hp/cva6/io_constraints.tcl diff --git a/flow/designs/rapidus2hp/cva6/io_constraints.tcl b/flow/designs/rapidus2hp/cva6/io_constraints.tcl new file mode 100644 index 0000000000..e220b161d1 --- /dev/null +++ b/flow/designs/rapidus2hp/cva6/io_constraints.tcl @@ -0,0 +1,46 @@ +# left (bottom to top) +# cvxif_req_o +# axi_req_o - noc_req_o in ours +# scan_output - doesn't exist in ours +set_io_pin_constraint -group -order -region left:20-38.7 -pin_names {cvxif_req_o*} +set_io_pin_constraint -group -order -region left:38.8-90.2 -pin_names {noc_req_o*} + +# right (bottom to top) +# scan_input - doesn't exist in ours +# test_mode - doesn't exist in ours +# scan_enable - doesn't exist in ours +# axi_resp_i - noc_resp_i in ours +# cvxif_resp_i +# debug_req_i +# time_irq_i +# ipi_i +# irq_i +# hart_id_i +# boot_addr_i +# rst_ni +# clk_i +set_io_pin_constraint -group -order -region right:5-31.4 -pin_names {noc_resp_i*} +set_io_pin_constraint -group -order -region right:31.5-73.1 -pin_names {cvxif_resp_i*} +set_io_pin_constraint -group -order -region right:73.3-73.7 -pin_names {debug_req_i \ + time_irq_i ipi_i} +set_io_pin_constraint -group -order -region right:74-74.3 -pin_names {irq_i*} +set_io_pin_constraint -group -order -region right:74.5-82 -pin_names {hart_id_i*} +set_io_pin_constraint -group -order -region right:82.2-89.8 -pin_names {boot_addr_i*} +set_io_pin_constraint -group -order -region right:89.9-90.3 -pin_names {rst_n_i clk_i} + +# don't exist in reference design implementation - does it make us I/O bound? +# put a third of them on the top, a third on the bottom, and let the placer +# decide where to put the remaining third +set num_rvfi_probes_ports 4295 +set third_rvfi_probes_ports [expr $num_rvfi_probes_ports / 3] +set top_group {} +for { set i 0 } { $i < $third_rvfi_probes_ports } { incr i } { + lappend top_group "rvfi_probes_o\[$i\]" +} +set bottom_group {} +for { } { $i < $third_rvfi_probes_ports * 2 } { incr i } { + lappend bottom_group "rvfi_probes_o\[$i\]" +} + +set_io_pin_constraint -group -order -region bottom:* -pin_names $top_group +set_io_pin_constraint -group -order -region top:* -pin_names $bottom_group diff --git a/flow/designs/rapidus2hp/hercules_is_int/config.mk b/flow/designs/rapidus2hp/hercules_is_int/config.mk index 6ccb921da5..f41a96abf1 100644 --- a/flow/designs/rapidus2hp/hercules_is_int/config.mk +++ b/flow/designs/rapidus2hp/hercules_is_int/config.mk @@ -124,10 +124,10 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/prects export SYNTH_HDL_FRONTEND = slang export SYNTH_HIERARCHICAL ?= 0 -export CORE_UTILIZATION = 25 +export CORE_UTILIZATION = 35 export CORE_MARGIN = 2 -export MACRO_PLACE_HALO = 4 4 +export MACRO_PLACE_HALO = 2 2 export PLACE_DENSITY = 0.58 From a0568eabf53399949d9818803aa285e8bdebadf5 Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Mon, 14 Jul 2025 23:55:34 +0000 Subject: [PATCH 182/198] transitioned Verilog list to wildcards Signed-off-by: Jeff Ng --- .../rapidus2hp/hercules_is_int/config.mk | 112 +----------------- 1 file changed, 5 insertions(+), 107 deletions(-) diff --git a/flow/designs/rapidus2hp/hercules_is_int/config.mk b/flow/designs/rapidus2hp/hercules_is_int/config.mk index 6ccb921da5..a9486b6323 100644 --- a/flow/designs/rapidus2hp/hercules_is_int/config.mk +++ b/flow/designs/rapidus2hp/hercules_is_int/config.mk @@ -3,111 +3,9 @@ export PLATFORM = rapidus2hp export DESIGN_NAME = hercules_is_int export SRC_HOME = /platforms/Rapidus/designs/hercules_is_int -export VERILOG_FILES = $(SRC_HOME)/hercules_issue/verilog/hercules_is_defines.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_flush_compare.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_gcbfwd.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_gclfwd.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_gcxfwd.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_gfwd.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_grbt_bnk.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_grbt.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_grf_bnk_rd.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_grf_bnk.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_grf_bnk_wr.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_grf.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_int_comm.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_int_ela.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_int_fwd.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_int_pipe.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_int.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq2_age.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq2_entry.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq2_ncentry.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq2.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq_age.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq_dep.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq_entry.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq_free_list.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq_ncentry.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_lsq_top_dep.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_ls_uop_ctl_dec.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_mx0_entry.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_mx0.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_mx1_entry.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_mx1.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_mxq_age.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_mxq_dep.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_mxq_free_list.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_mxq_ncentry.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_mxq_slow_age.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_mxq_slow_dep.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_mxq_top_dep.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_params.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_pcrf_bnk.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_pcrf.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_resc_cnt1s_4b.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_resc_ix.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_resc_ls.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_resc_tag.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_stid_compare.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_sxq_age.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_sxq_dep.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_sxq_entry.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_sxq_free_list.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_sxq_ncentry.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_sxq_slow_age.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_sxq_slow_dep.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_sxq.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_sxq_top_dep.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_vec_comm.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_vec_ela.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_vec_pipe.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_vec_res_ctl.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_vec.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_vrbt_rmux.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_vrbt.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_vrbt_wmux.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_vrf_port_arb.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_vxq_age.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_vxq_entry.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_vxq_free_list.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_vxq_pipe.sv \ - $(SRC_HOME)/hercules_issue/verilog/hercules_is_vxq.sv \ - $(SRC_HOME)/shared/verilog/hercules_ccpass.sv \ - $(SRC_HOME)/shared/verilog/hercules_core_defines.sv \ - $(SRC_HOME)/shared/verilog/hercules_dffr_rstval.sv \ - $(SRC_HOME)/shared/verilog/hercules_dffr.sv \ - $(SRC_HOME)/shared/verilog/hercules_dff.sv \ - $(SRC_HOME)/shared/verilog/hercules_ecc_chk.sv \ - $(SRC_HOME)/shared/verilog/hercules_ecc_correct.sv \ - $(SRC_HOME)/shared/verilog/hercules_ecc_gen.sv \ - $(SRC_HOME)/shared/verilog/hercules_ecc_matrix.sv \ - $(SRC_HOME)/shared/verilog/hercules_ecc_syndrome_correct.sv \ - $(SRC_HOME)/shared/verilog/hercules_ela_defines.sv \ - $(SRC_HOME)/shared/verilog/hercules_fcvt64.sv \ - $(SRC_HOME)/shared/verilog/hercules_flush_compare.sv \ - $(SRC_HOME)/shared/verilog/hercules_flush_type_defines.sv \ - $(SRC_HOME)/shared/verilog/hercules_header.sv \ - $(SRC_HOME)/shared/verilog/hercules_ifid_lsm_regcnt_armthm.sv \ - $(SRC_HOME)/shared/verilog/hercules_ifid_lsm_regcnt_neon.sv \ - $(SRC_HOME)/shared/verilog/hercules_ifid_lsm_regcnt.sv \ - $(SRC_HOME)/shared/verilog/hercules_ifid_mop_t16_iqual.sv \ - $(SRC_HOME)/shared/verilog/hercules_ifid_mop_t32p_iqual.sv \ - $(SRC_HOME)/shared/verilog/hercules_ifid_mq_props.sv \ - $(SRC_HOME)/shared/verilog/hercules_invmask64.sv \ - $(SRC_HOME)/shared/verilog/hercules_lsl2_defines.sv \ - $(SRC_HOME)/shared/verilog/hercules_params.sv \ - $(SRC_HOME)/shared/verilog/hercules_pdp_period.sv \ - $(SRC_HOME)/shared/verilog/hercules_pdp_tracker_ls.sv \ - $(SRC_HOME)/shared/verilog/hercules_pdp_tracker.sv \ - $(SRC_HOME)/shared/verilog/hercules_plru_arb.sv \ - $(SRC_HOME)/shared/verilog/hercules_plru_order.sv \ - $(SRC_HOME)/shared/verilog/hercules_pmu_defines.sv \ - $(SRC_HOME)/shared/verilog/hercules_shared_params.sv \ - $(SRC_HOME)/models/cells/generic/hercules_ck_gate.sv \ - $(SRC_HOME)/models/cells/generic/hercules_nand_gate.sv \ - $(SRC_HOME)/models/cells/generic/hercules_nor_gate.sv +export VERILOG_FILES = $(sort $(wildcard $(SRC_HOME)/hercules_issue/verilog/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/shared/verilog/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/models/cells/generic/*.sv)) export VERILOG_INCLUDE_DIRS = $(SRC_HOME)/hercules_issue/verilog \ $(SRC_HOME)/shared/verilog \ @@ -124,10 +22,10 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/prects export SYNTH_HDL_FRONTEND = slang export SYNTH_HIERARCHICAL ?= 0 -export CORE_UTILIZATION = 25 +export CORE_UTILIZATION = 35 export CORE_MARGIN = 2 -export MACRO_PLACE_HALO = 4 4 +export MACRO_PLACE_HALO = 2 2 export PLACE_DENSITY = 0.58 From 259efe8d06b839e83b813aa1422894e121fcbc22 Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Wed, 16 Jul 2025 18:13:36 +0000 Subject: [PATCH 183/198] Increased rapidus cva6 util to 45 for Verific tcllint fixes removed comments Signed-off-by: Jeff Ng --- flow/designs/rapidus2hp/cva6/config.mk | 6 ++- .../rapidus2hp/cva6/io_constraints.tcl | 42 +++++++------------ 2 files changed, 19 insertions(+), 29 deletions(-) diff --git a/flow/designs/rapidus2hp/cva6/config.mk b/flow/designs/rapidus2hp/cva6/config.mk index de97cfcd7a..a18f881f83 100644 --- a/flow/designs/rapidus2hp/cva6/config.mk +++ b/flow/designs/rapidus2hp/cva6/config.mk @@ -98,11 +98,11 @@ export SYNTH_HIERARCHICAL = 1 ifeq ($(SYNTH_HDL_FRONTEND),verific) # Reduce utilization for verific since it runs into issues with DPL not being # able to place instances or with one-site gap/overlap issues - export CORE_UTILIZATION = 35 + export CORE_UTILIZATION = 45 else # Reduce the amount of resizing done between GPL and DPL export EARLY_SIZING_CAP_RATIO = 6 - export CORE_UTILIZATION = 45 + export CORE_UTILIZATION = 50 endif export CORE_MARGIN = 2 @@ -118,3 +118,5 @@ export SKIP_LAST_GASP ?= 1 # For use with SYNTH_HIERARCHICAL export SYNTH_MINIMUM_KEEP_SIZE ?= 40000 + +#export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io_constraints.tcl diff --git a/flow/designs/rapidus2hp/cva6/io_constraints.tcl b/flow/designs/rapidus2hp/cva6/io_constraints.tcl index e220b161d1..44c48e5927 100644 --- a/flow/designs/rapidus2hp/cva6/io_constraints.tcl +++ b/flow/designs/rapidus2hp/cva6/io_constraints.tcl @@ -1,34 +1,21 @@ # left (bottom to top) -# cvxif_req_o -# axi_req_o - noc_req_o in ours -# scan_output - doesn't exist in ours -set_io_pin_constraint -group -order -region left:20-38.7 -pin_names {cvxif_req_o*} -set_io_pin_constraint -group -order -region left:38.8-90.2 -pin_names {noc_req_o*} +set_io_pin_constraint -group -order -region left:4.09-40.70 -pin_names {cvxif_req_o[*]} +set_io_pin_constraint -group -order -region left:40.85-90.13 -pin_names {noc_req_o[*]} # right (bottom to top) -# scan_input - doesn't exist in ours -# test_mode - doesn't exist in ours -# scan_enable - doesn't exist in ours -# axi_resp_i - noc_resp_i in ours -# cvxif_resp_i -# debug_req_i -# time_irq_i -# ipi_i -# irq_i -# hart_id_i -# boot_addr_i -# rst_ni -# clk_i -set_io_pin_constraint -group -order -region right:5-31.4 -pin_names {noc_resp_i*} -set_io_pin_constraint -group -order -region right:31.5-73.1 -pin_names {cvxif_resp_i*} -set_io_pin_constraint -group -order -region right:73.3-73.7 -pin_names {debug_req_i \ - time_irq_i ipi_i} -set_io_pin_constraint -group -order -region right:74-74.3 -pin_names {irq_i*} -set_io_pin_constraint -group -order -region right:74.5-82 -pin_names {hart_id_i*} -set_io_pin_constraint -group -order -region right:82.2-89.8 -pin_names {boot_addr_i*} -set_io_pin_constraint -group -order -region right:89.9-90.3 -pin_names {rst_n_i clk_i} +# The intervals have been expanded based on pin placer feedback +set_io_pin_constraint -group -order -region right:5.25-45.34 -pin_names {noc_resp_i[*]} +set_io_pin_constraint -group -order -region right:45.62-93.07 -pin_names {cvxif_resp_i[*]} +set_io_pin_constraint -group -order -region right:93.32-93.73 \ + -pin_names { + debug_req_i time_irq_i ipi_i + } +set_io_pin_constraint -group -order -region right:94.01-94.28 -pin_names {irq_i[*]} +set_io_pin_constraint -group -order -region right:94.51-102.01 -pin_names {hart_id_i[*]} +set_io_pin_constraint -group -order -region right:102.25-109.74 -pin_names {boot_addr_i[*]} +set_io_pin_constraint -group -order -region right:109.99-110.25 -pin_names {rst_ni clk_i} -# don't exist in reference design implementation - does it make us I/O bound? +# The rvfi_probes_o pins don't exist in reference design implementation # put a third of them on the top, a third on the bottom, and let the placer # decide where to put the remaining third set num_rvfi_probes_ports 4295 @@ -42,5 +29,6 @@ for { } { $i < $third_rvfi_probes_ports * 2 } { incr i } { lappend bottom_group "rvfi_probes_o\[$i\]" } + set_io_pin_constraint -group -order -region bottom:* -pin_names $top_group set_io_pin_constraint -group -order -region top:* -pin_names $bottom_group From cba7c8e069a0ebb0d8ce3e1727889acbd4ac9c3c Mon Sep 17 00:00:00 2001 From: Faholan <62927863+Faholan@users.noreply.github.com> Date: Wed, 16 Jul 2025 15:32:01 -0700 Subject: [PATCH 184/198] Support zsh as shell Signed-off-by: Faholan <62927863+Faholan@users.noreply.github.com> --- dev_env.sh | 2 +- env.sh | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/dev_env.sh b/dev_env.sh index 61a77e6929..917747caf5 100755 --- a/dev_env.sh +++ b/dev_env.sh @@ -3,7 +3,7 @@ # Set developer paths and environment variables here, # user settings go in ./env.sh function __setpaths() { - local DIR=$(readlink -f "$(dirname "${BASH_SOURCE[0]}")") + local DIR=$(readlink -f "$(dirname "${BASH_SOURCE[0]:-${(%):-%x}}")") [ "$(find $DIR/dependencies -type f -user root)" ] && echo "WARNING! Files set up by sudo found in $DIR" export PATH="$DIR/dependencies/bin:$PATH" export CMAKE_INSTALL_RPATH=$DIR/dependencies/lib:$DIR/dependencies/lib64 diff --git a/env.sh b/env.sh index 88021867cb..563c003a81 100755 --- a/env.sh +++ b/env.sh @@ -1,9 +1,9 @@ #!/usr/bin/env bash function __setpaths() { if [[ "$OSTYPE" == "darwin"* ]]; then - DIR="$(dirname $(perl -e 'use Cwd "abs_path";print abs_path(shift)' "${BASH_SOURCE[0]}"))" + DIR="$(dirname $(perl -e 'use Cwd "abs_path";print abs_path(shift)' "${BASH_SOURCE[0]:-${(%):-%x}}"))" else - DIR="$(dirname $(readlink -f "${BASH_SOURCE[0]}"))" + DIR="$(dirname $(readlink -f "${BASH_SOURCE[0]:-${(%):-%x}}"))" fi export OPENROAD=${DIR}/tools/OpenROAD From e3d366b2da321faeedd02107bccc00f958a7b99a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Thu, 17 Jul 2025 07:53:20 +0200 Subject: [PATCH 185/198] make: print-FOO fixes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/scripts/variables.mk | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/flow/scripts/variables.mk b/flow/scripts/variables.mk index e7bc8ded86..6cfd19517d 100644 --- a/flow/scripts/variables.mk +++ b/flow/scripts/variables.mk @@ -215,7 +215,15 @@ vars: .PHONY: print-% # Print any variable, for instance: make print-DIE_AREA print-%: - $(file >$(OBJECTS_DIR)/print_tmp_$$,$($*)) + # HERE BE DRAGONS! + # + # We have to use /tmp. $(OBJECTS_DIR) may not exist + # at $(file) expansion time, which is before commands are run + # here, so we can't mkdir -p $(OBJECTS_DIR) either + # + # We have to use $(file ...) because we want to be able + # to print variables that contain newlines. + $(file >/tmp/print_tmp$$,$($*)) @echo -n "$* = " - @cat $(OBJECTS_DIR)/print_tmp_$$ - @rm $(OBJECTS_DIR)/print_tmp_$$ + @cat /tmp/print_tmp$$ + @rm /tmp/print_tmp$$ From 36881266148998c7129d170b8b5591fa17ef03bb Mon Sep 17 00:00:00 2001 From: Cho Moon Date: Fri, 18 Jul 2025 01:06:39 +0000 Subject: [PATCH 186/198] made it easier to enable wrapped operator synthesis and operator mapping Signed-off-by: Cho Moon --- flow/scripts/floorplan.tcl | 5 +++++ flow/scripts/load.tcl | 14 ++++++++++++-- flow/scripts/resize.tcl | 4 ++++ flow/scripts/synth.tcl | 7 ++++--- flow/scripts/synth_wrap_operators.tcl | 2 +- flow/scripts/variables.yaml | 7 +++++++ 6 files changed, 33 insertions(+), 6 deletions(-) diff --git a/flow/scripts/floorplan.tcl b/flow/scripts/floorplan.tcl index 2f4892dcf1..94696efbaf 100644 --- a/flow/scripts/floorplan.tcl +++ b/flow/scripts/floorplan.tcl @@ -101,6 +101,11 @@ if { [env_var_exists_and_non_empty FOOTPRINT_TCL] } { # tie driving multiple buffers that drive multiple outputs. repair_tie_fanout_helper +if { [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] } { + estimate_parasitics -placement + replace_arith_modules +} + if { [env_var_equals REMOVE_ABC_BUFFERS 1] } { # remove buffers inserted by yosys/abc remove_buffers diff --git a/flow/scripts/load.tcl b/flow/scripts/load.tcl index dc3febd404..3f5e04d1ac 100644 --- a/flow/scripts/load.tcl +++ b/flow/scripts/load.tcl @@ -18,9 +18,19 @@ proc load_design { design_file sdc_file } { } } read_verilog $::env(RESULTS_DIR)/$design_file - link_design $::env(DESIGN_NAME) + if { [env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] || + [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] } { + link_design -hier $::env(DESIGN_NAME) + } else { + link_design $::env(DESIGN_NAME) + } } elseif { $ext == ".odb" } { - read_db $::env(RESULTS_DIR)/$design_file + if { [env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] || + [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] } { + read_db -hier $::env(RESULTS_DIR)/$design_file + } else { + read_db $::env(RESULTS_DIR)/$design_file + } } else { error "Unrecognized input file $design_file" } diff --git a/flow/scripts/resize.tcl b/flow/scripts/resize.tcl index d810d65de0..50276a85ec 100644 --- a/flow/scripts/resize.tcl +++ b/flow/scripts/resize.tcl @@ -14,6 +14,10 @@ if { [env_var_exists_and_non_empty EARLY_SIZING_CAP_RATIO] } { log_cmd set_opt_config -set_early_sizing_cap_ratio $env(EARLY_SIZING_CAP_RATIO) } +if { [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] } { + replace_arith_modules +} + repair_design_helper # hold violations are not repaired until after CTS diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl index 6e8a82f7d4..0a29db7661 100644 --- a/flow/scripts/synth.tcl +++ b/flow/scripts/synth.tcl @@ -56,10 +56,11 @@ json -o $::env(RESULTS_DIR)/mem.json exec -- $::env(PYTHON_EXE) $::env(SCRIPTS_DIR)/mem_dump.py \ --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json -if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } { - synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_full_args -} else { +if { [env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] || + [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] } { source $::env(SCRIPTS_DIR)/synth_wrap_operators.tcl +} else { + synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_full_args } # Get rid of indigestibles diff --git a/flow/scripts/synth_wrap_operators.tcl b/flow/scripts/synth_wrap_operators.tcl index a4e2897704..a47dc60452 100644 --- a/flow/scripts/synth_wrap_operators.tcl +++ b/flow/scripts/synth_wrap_operators.tcl @@ -10,8 +10,8 @@ set deferred_cells { { \$macc MACC_{CONFIG}_{Y_WIDTH}{%unused} - {BASE -map +/choices/han-carlson.v} {BOOTH -max_iter 1 -map ../flow/scripts/synth_wrap_operators-booth.v} + {BASE -map +/choices/han-carlson.v} } } diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 8a459fc326..7508eefd05 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -269,6 +269,13 @@ SYNTH_WRAPPED_OPERATORS: the flow. stages: - synth +SWAP_ARITH_OPERATORS: + description: > + Improve timing QoR by swapping ALU and MULT arithmetic operators. + stages: + - synth + - floorplan + - place FLOORPLAN_DEF: description: | Use the DEF file to initialize floorplan. From 86ece71e062b07adcbf556226bc81b67cececa03 Mon Sep 17 00:00:00 2001 From: Cho Moon Date: Fri, 18 Jul 2025 04:00:35 +0000 Subject: [PATCH 187/198] updated FlowVariables.md Signed-off-by: Cho Moon --- docs/user/FlowVariables.md | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 2fa305783c..6400146387 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -219,6 +219,7 @@ configuration file. | SKIP_PIN_SWAP| Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).| | | SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| | | SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| | +| SWAP_ARITH_OPERATORS| Improve timing QoR by swapping ALU and MULT arithmetic operators.| | | SYNTH_ARGS| Optional synthesis variables for yosys.| | | SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| | | SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | From ad681d7273aa1e9412592633f5a212ac378199c1 Mon Sep 17 00:00:00 2001 From: Cho Moon Date: Fri, 18 Jul 2025 04:15:35 +0000 Subject: [PATCH 188/198] updated synthesis/floorplan/place section in FlowVariables.md Signed-off-by: Cho Moon --- docs/user/FlowVariables.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 6400146387..0e4d29bf18 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -256,6 +256,7 @@ configuration file. - [MIN_BUF_CELL_AND_PORTS](#MIN_BUF_CELL_AND_PORTS) - [SDC_FILE](#SDC_FILE) - [SDC_GUT](#SDC_GUT) +- [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS) - [SYNTH_BLACKBOXES](#SYNTH_BLACKBOXES) - [SYNTH_GUT](#SYNTH_GUT) - [SYNTH_HDL_FRONTEND](#SYNTH_HDL_FRONTEND) @@ -323,6 +324,7 @@ configuration file. - [SKIP_LAST_GASP](#SKIP_LAST_GASP) - [SKIP_PIN_SWAP](#SKIP_PIN_SWAP) - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) +- [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS) - [TAPCELL_TCL](#TAPCELL_TCL) - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT) - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT) @@ -347,6 +349,7 @@ configuration file. - [PLACE_PINS_ARGS](#PLACE_PINS_ARGS) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) +- [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS) - [TIE_SEPARATION](#TIE_SEPARATION) ## cts variables From 29d9cf402efb058492752b577ec9239866ba2474 Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Fri, 18 Jul 2025 14:17:16 +0000 Subject: [PATCH 189/198] added ability to inject Tcl commands in synth canonicalize step tclfmt fixes Signed-off-by: Jeff Ng --- docs/user/FlowVariables.md | 2 ++ flow/designs/rapidus2hp/cva6/canonicalize.tcl | 4 ++++ flow/designs/rapidus2hp/cva6/config.mk | 5 ++++- flow/scripts/synth_canonicalize.tcl | 5 +++++ flow/scripts/variables.yaml | 6 ++++++ 5 files changed, 21 insertions(+), 1 deletion(-) create mode 100644 flow/designs/rapidus2hp/cva6/canonicalize.tcl diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 2fa305783c..74d2c614b8 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -221,6 +221,7 @@ configuration file. | SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| | | SYNTH_ARGS| Optional synthesis variables for yosys.| | | SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| | +| SYNTH_CANONICALIZE_TCL| Specifies a Tcl script with commands to run as part of the synth canonicalize step.| | | SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | | SYNTH_HDL_FRONTEND| Select an alternative language frontend to ingest the design. Available option is "slang". If the variable is empty, design is read with the Yosys read_verilog command.| | | SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| @@ -256,6 +257,7 @@ configuration file. - [SDC_FILE](#SDC_FILE) - [SDC_GUT](#SDC_GUT) - [SYNTH_BLACKBOXES](#SYNTH_BLACKBOXES) +- [SYNTH_CANONICALIZE_TCL](#SYNTH_CANONICALIZE_TCL) - [SYNTH_GUT](#SYNTH_GUT) - [SYNTH_HDL_FRONTEND](#SYNTH_HDL_FRONTEND) - [SYNTH_HIERARCHICAL](#SYNTH_HIERARCHICAL) diff --git a/flow/designs/rapidus2hp/cva6/canonicalize.tcl b/flow/designs/rapidus2hp/cva6/canonicalize.tcl new file mode 100644 index 0000000000..d9f81be71f --- /dev/null +++ b/flow/designs/rapidus2hp/cva6/canonicalize.tcl @@ -0,0 +1,4 @@ +# Remove rvfi_probes_o interface since it's not in the baseline and contributes +# 4k ports and connections (many of which are buffers tied to tie cells) + +delete cva6/o:rvfi_probes_o* diff --git a/flow/designs/rapidus2hp/cva6/config.mk b/flow/designs/rapidus2hp/cva6/config.mk index a18f881f83..ce52828b2c 100644 --- a/flow/designs/rapidus2hp/cva6/config.mk +++ b/flow/designs/rapidus2hp/cva6/config.mk @@ -102,7 +102,7 @@ ifeq ($(SYNTH_HDL_FRONTEND),verific) else # Reduce the amount of resizing done between GPL and DPL export EARLY_SIZING_CAP_RATIO = 6 - export CORE_UTILIZATION = 50 + export CORE_UTILIZATION = 55 endif export CORE_MARGIN = 2 @@ -120,3 +120,6 @@ export SKIP_LAST_GASP ?= 1 export SYNTH_MINIMUM_KEEP_SIZE ?= 40000 #export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io_constraints.tcl + +# Remove rvfi_probes_o interface +export SYNTH_CANONICALIZE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/canonicalize.tcl diff --git a/flow/scripts/synth_canonicalize.tcl b/flow/scripts/synth_canonicalize.tcl index 3c167d7797..60f64c096b 100644 --- a/flow/scripts/synth_canonicalize.tcl +++ b/flow/scripts/synth_canonicalize.tcl @@ -7,6 +7,11 @@ dict for {key value} [env_var_or_empty VERILOG_TOP_PARAMS] { } hierarchy -check -top $::env(DESIGN_NAME) + +if { [env_var_exists_and_non_empty SYNTH_CANONICALIZE_TCL] } { + log_cmd source $::env(SYNTH_CANONICALIZE_TCL) +} + # Get rid of unused modules opt_clean -purge # The hash of this file will not change if files not part of synthesis do not change diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 8a459fc326..a060bbf3d4 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -194,6 +194,12 @@ SYNTH_NETLIST_FILES: subsequent modules are silently ignored and only the first module is used. stages: - synth +SYNTH_CANONICALIZE_TCL: + description: > + Specifies a Tcl script with commands to run as part of the synth + canonicalize step. + stages: + - synth LATCH_MAP_FILE: description: | List of latches treated as a black box by Yosys. From 21e02cb6b82a5aa53a4f370fbf0ca56afab55f6b Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Fri, 18 Jul 2025 16:28:37 -0700 Subject: [PATCH 190/198] Make CTS_BUF_DISTANCE tunable Signed-off-by: Jeff Ng --- flow/scripts/variables.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 4e9c73c5f6..4c1ab371b4 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -769,11 +769,15 @@ CTS_BUF_DISTANCE: Distance (in microns) between buffers. stages: - cts + tunable: 1 + type: float CTS_BUF_LIST: description: | List of cells used to construct the clock tree. Overrides buffer inference. stages: - cts + tunable: 1 + type: float CTS_CLUSTER_DIAMETER: description: > Maximum diameter (in microns) of sink cluster. From c9701fa1a4aa7b233e7e1b930d5a82e201eb59fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Sat, 19 Jul 2025 09:04:39 +0200 Subject: [PATCH 191/198] variables: PRE_GLOBAL_ROUTE_TCL now has consistent naming MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- docs/user/FlowVariables.md | 2 ++ flow/Makefile | 2 +- flow/scripts/global_route.tcl | 2 +- flow/scripts/variables.yaml | 5 +++++ flow/util/makeIssue.sh | 2 +- 5 files changed, 10 insertions(+), 3 deletions(-) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index fa65a59ea0..854bceb8d2 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -174,6 +174,7 @@ configuration file. | PLATFORM| Specifies process design kit or technology node to be used.| | | PLATFORM_TCL| Specifies a Tcl script with commands to run before loading design.| | | POST_CTS_TCL| Specifies a Tcl script with commands to run after CTS is completed.| | +| PRE_GLOBAL_ROUTE_TCL| Specifies a Tcl script with commands to run before global route.| | | PROCESS| Technology node or process in use.| | | PWR_NETS_VOLTAGES| Used for IR Drop calculation.| | | RCX_RULES| RC Extraction rules file path.| | @@ -388,6 +389,7 @@ configuration file. - [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN) - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) +- [PRE_GLOBAL_ROUTE_TCL](#PRE_GLOBAL_ROUTE_TCL) - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) - [SETUP_REPAIR_SEQUENCE](#SETUP_REPAIR_SEQUENCE) diff --git a/flow/Makefile b/flow/Makefile index 329df67452..530ff511c4 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -550,7 +550,7 @@ grt: $(RESULTS_DIR)/5_1_grt.odb # STEP 1: Run global route #------------------------------------------------------------------------------- -$(eval $(call do-step,5_1_grt,$(RESULTS_DIR)/4_cts.odb $(FASTROUTE_TCL) $(PRE_GLOBAL_ROUTE),global_route)) +$(eval $(call do-step,5_1_grt,$(RESULTS_DIR)/4_cts.odb $(FASTROUTE_TCL) $(PRE_GLOBAL_ROUTE_TCL),global_route)) # STEP 2: Run detailed route #------------------------------------------------------------------------------- diff --git a/flow/scripts/global_route.tcl b/flow/scripts/global_route.tcl index 6eab49df96..d0edcc993c 100644 --- a/flow/scripts/global_route.tcl +++ b/flow/scripts/global_route.tcl @@ -6,7 +6,7 @@ load_design 4_cts.odb 4_cts.sdc # This proc is here to allow us to use 'return' to return early from this # file which is sourced proc global_route_helper { } { - source_env_var_if_exists PRE_GLOBAL_ROUTE + source_env_var_if_exists PRE_GLOBAL_ROUTE_TCL proc do_global_route { } { set all_args [concat [list \ diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 4c1ab371b4..d2ca6cb1d4 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -824,6 +824,11 @@ ABSTRACT_SOURCE: Which .odb file to use to create abstract stages: - generate_abstract +PRE_GLOBAL_ROUTE_TCL: + description: | + Specifies a Tcl script with commands to run before global route. + stages: + - grt GLOBAL_ROUTE_ARGS: description: > Replaces default arguments for global route. diff --git a/flow/util/makeIssue.sh b/flow/util/makeIssue.sh index b06b789567..9152294daa 100755 --- a/flow/util/makeIssue.sh +++ b/flow/util/makeIssue.sh @@ -32,7 +32,7 @@ ISSUE_CP_PLATFORM_FILE_VARS="LIB_FILES \ PDN_TCL \ POST_PDN_TCL \ POST_CTS_TCL \ - PRE_GLOBAL_ROUTE \ + PRE_GLOBAL_ROUTE_TCL \ FASTROUTE_TCL \ POST_DETAIL_ROUTE_TCL \ RCX_RULES \ From 4e62b4533984ebb7a055e71800a83f08e1dda28c Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Sat, 19 Jul 2025 16:50:33 +0000 Subject: [PATCH 192/198] Aligned clock period with July 2025 demo tclfmt fix + added opt constraint SDC Signed-off-by: Jeff Ng --- flow/designs/rapidus2hp/cva6/autotuner.json | 12 ++++++++++-- flow/designs/rapidus2hp/cva6/constraint.sdc | 4 +--- flow/designs/rapidus2hp/cva6/opt_constraint.sdc | 9 +++++++++ 3 files changed, 20 insertions(+), 5 deletions(-) create mode 100644 flow/designs/rapidus2hp/cva6/opt_constraint.sdc diff --git a/flow/designs/rapidus2hp/cva6/autotuner.json b/flow/designs/rapidus2hp/cva6/autotuner.json index cc58f5fda7..734b7d6808 100644 --- a/flow/designs/rapidus2hp/cva6/autotuner.json +++ b/flow/designs/rapidus2hp/cva6/autotuner.json @@ -4,15 +4,23 @@ "type": "float", "minmax": [ 990, - 1015 + 1250 ], "step": 0 }, "CORE_UTILIZATION": { + "type": "int", + "minmax": [ + 40, + 60 + ], + "step": 1 + }, + "CTS_BUF_DISTANCE": { "type": "int", "minmax": [ 25, - 45 + 50 ], "step": 1 }, diff --git a/flow/designs/rapidus2hp/cva6/constraint.sdc b/flow/designs/rapidus2hp/cva6/constraint.sdc index 92605441dc..f263502816 100644 --- a/flow/designs/rapidus2hp/cva6/constraint.sdc +++ b/flow/designs/rapidus2hp/cva6/constraint.sdc @@ -3,9 +3,7 @@ set clk_name main_clk set clk_port clk_i set clk_ports_list [list $clk_port] -set clk_period 1000 +set clk_period 1380 set input_delay 0.46 set output_delay 0.11 create_clock [get_ports $clk_port] -name $clk_name -period $clk_period - -set_false_path -to [get_ports {rvfi_probes_o}] diff --git a/flow/designs/rapidus2hp/cva6/opt_constraint.sdc b/flow/designs/rapidus2hp/cva6/opt_constraint.sdc new file mode 100644 index 0000000000..b0692f6387 --- /dev/null +++ b/flow/designs/rapidus2hp/cva6/opt_constraint.sdc @@ -0,0 +1,9 @@ +# Derived from cva6_synth.tcl and Makefiles + +set clk_name main_clk +set clk_port clk_i +set clk_ports_list [list $clk_port] +set clk_period 1013.87619516354 +set input_delay 0.46 +set output_delay 0.11 +create_clock [get_ports $clk_port] -name $clk_name -period $clk_period From 6cb96d495ab16de5f6aacf3a732913f70bb8ba64 Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Fri, 18 Jul 2025 14:08:33 -0700 Subject: [PATCH 193/198] Switched to use source_env_var_if_exists fixed tcl issue with i2c-gpio-expander pad.tcl tclfmt fixes Signed-off-by: Jeff Ng --- .../ihp-sg13g2/i2c-gpio-expander/pad.tcl | 174 ++++++++++++------ flow/scripts/floorplan.tcl | 14 +- flow/scripts/synth_canonicalize.tcl | 4 +- flow/scripts/util.tcl | 2 +- 4 files changed, 127 insertions(+), 67 deletions(-) diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl index 1e7d27baa8..049987ebe2 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl @@ -4,12 +4,7 @@ set BONDPAD_SIZE 70 set SEALRING_OFFSET 70 set IO_OFFSET [expr { $BONDPAD_SIZE + $SEALRING_OFFSET }] -proc calc_horizontal_pad_location { index total } { - global IO_LENGTH - global IO_WIDTH - global BONDPAD_SIZE - global SEALRING_OFFSET - +proc calc_horizontal_pad_location { index total IO_LENGTH IO_WIDTH BONDPAD_SIZE SEALRING_OFFSET } { set DIE_WIDTH [expr { [lindex $::env(DIE_AREA) 2] - [lindex $::env(DIE_AREA) 0] }] set PAD_OFFSET [expr { $IO_LENGTH + $BONDPAD_SIZE + $SEALRING_OFFSET }] set PAD_AREA_WIDTH [expr { $DIE_WIDTH - ($PAD_OFFSET * 2) }] @@ -21,12 +16,7 @@ proc calc_horizontal_pad_location { index total } { }] } -proc calc_vertical_pad_location { index total } { - global IO_LENGTH - global IO_WIDTH - global BONDPAD_SIZE - global SEALRING_OFFSET - +proc calc_vertical_pad_location { index total IO_LENGTH IO_WIDTH BONDPAD_SIZE SEALRING_OFFSET } { set DIE_HEIGHT [expr { [lindex $::env(DIE_AREA) 3] - [lindex $::env(DIE_AREA) 1] }] set PAD_OFFSET [expr { $IO_LENGTH + $BONDPAD_SIZE + $SEALRING_OFFSET }] set PAD_AREA_HEIGHT [expr { $DIE_HEIGHT - ($PAD_OFFSET * 2) }] @@ -51,61 +41,141 @@ make_io_sites \ # Place Pads # IO pin io_clock -place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 0 5] \ - {sg13g2_IOPad_io_clock} -master sg13g2_IOPadIn +place_pad \ + -row IO_SOUTH \ + -location [calc_horizontal_pad_location \ + 0 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_clock} \ + -master sg13g2_IOPadIn # IO pin io_reset -place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 1 5] \ - {sg13g2_IOPad_io_reset} -master sg13g2_IOPadIn +place_pad \ + -row IO_SOUTH \ + -location [calc_horizontal_pad_location \ + 1 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_reset} \ + -master sg13g2_IOPadIn # IO pin io_i2c_scl -place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 2 5] \ - {sg13g2_IOPad_io_i2c_scl} -master sg13g2_IOPadInOut4mA +place_pad \ + -row IO_SOUTH \ + -location [calc_horizontal_pad_location \ + 2 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_i2c_scl} \ + -master sg13g2_IOPadInOut4mA # IO pin io_i2c_sda -place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 3 5] \ - {sg13g2_IOPad_io_i2c_sda} -master sg13g2_IOPadInOut4mA +place_pad \ + -row IO_SOUTH \ + -location [calc_horizontal_pad_location \ + 3 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_i2c_sda} \ + -master sg13g2_IOPadInOut4mA # IO pin io_i2c_interrupt -place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 4 5] \ - {sg13g2_IOPad_io_i2c_interrupt} -master sg13g2_IOPadOut4mA -place_pad -row IO_EAST -location [calc_vertical_pad_location 0 5] \ - {sg13g2_IOPadVdd_east_0} -master sg13g2_IOPadVdd -place_pad -row IO_EAST -location [calc_vertical_pad_location 1 5] \ - {sg13g2_IOPadVss_east_1} -master sg13g2_IOPadVss +place_pad \ + -row IO_SOUTH \ + -location [calc_horizontal_pad_location \ + 4 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_i2c_interrupt} \ + -master sg13g2_IOPadOut4mA +place_pad \ + -row IO_EAST \ + -location [calc_vertical_pad_location \ + 0 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPadVdd_east_0} \ + -master sg13g2_IOPadVdd +place_pad \ + -row IO_EAST \ + -location [calc_vertical_pad_location \ + 1 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPadVss_east_1} \ + -master sg13g2_IOPadVss # IO pin io_address_0 -place_pad -row IO_EAST -location [calc_vertical_pad_location 2 5] \ - {sg13g2_IOPad_io_address_0} -master sg13g2_IOPadIn +place_pad \ + -row IO_EAST \ + -location [calc_vertical_pad_location \ + 2 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_address_0} \ + -master sg13g2_IOPadIn # IO pin io_address_1 -place_pad -row IO_EAST -location [calc_vertical_pad_location 3 5] \ - {sg13g2_IOPad_io_address_1} -master sg13g2_IOPadIn +place_pad \ + -row IO_EAST \ + -location [calc_vertical_pad_location \ + 3 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_address_1} \ + -master sg13g2_IOPadIn # IO pin io_address_2 -place_pad -row IO_EAST -location [calc_vertical_pad_location 4 5] \ - {sg13g2_IOPad_io_address_2} -master sg13g2_IOPadIn +place_pad \ + -row IO_EAST \ + -location [calc_vertical_pad_location \ + 4 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_address_2} \ + -master sg13g2_IOPadIn # IO pin io_gpio_0 -place_pad -row IO_NORTH -location [calc_horizontal_pad_location 0 5] \ - {sg13g2_IOPad_io_gpio_0} -master sg13g2_IOPadInOut16mA +place_pad \ + -row IO_NORTH \ + -location [calc_horizontal_pad_location \ + 0 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_0} \ + -master sg13g2_IOPadInOut16mA # IO pin io_gpio_1 -place_pad -row IO_NORTH -location [calc_horizontal_pad_location 1 5] \ - {sg13g2_IOPad_io_gpio_1} -master sg13g2_IOPadInOut16mA +place_pad \ + -row IO_NORTH \ + -location [calc_horizontal_pad_location \ + 1 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_1} \ + -master sg13g2_IOPadInOut16mA # IO pin io_gpio_2 -place_pad -row IO_NORTH -location [calc_horizontal_pad_location 2 5] \ - {sg13g2_IOPad_io_gpio_2} -master sg13g2_IOPadInOut16mA +place_pad \ + -row IO_NORTH \ + -location [calc_horizontal_pad_location \ + 2 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_2} \ + -master sg13g2_IOPadInOut16mA # IO pin io_gpio_3 -place_pad -row IO_NORTH -location [calc_horizontal_pad_location 3 5] \ - {sg13g2_IOPad_io_gpio_3} -master sg13g2_IOPadInOut16mA +place_pad \ + -row IO_NORTH \ + -location [calc_horizontal_pad_location \ + 3 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_3} \ + -master sg13g2_IOPadInOut16mA # IO pin io_gpio_4 -place_pad -row IO_NORTH -location [calc_horizontal_pad_location 4 5] \ - {sg13g2_IOPad_io_gpio_4} -master sg13g2_IOPadInOut16mA +place_pad \ + -row IO_NORTH \ + -location [calc_horizontal_pad_location \ + 4 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_4} \ + -master sg13g2_IOPadInOut16mA # IO pin io_gpio_5 -place_pad -row IO_WEST -location [calc_vertical_pad_location 0 5] \ - {sg13g2_IOPad_io_gpio_5} -master sg13g2_IOPadInOut16mA +place_pad \ + -row IO_WEST \ + -location [calc_vertical_pad_location \ + 0 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_5} \ + -master sg13g2_IOPadInOut16mA # IO pin io_gpio_6 -place_pad -row IO_WEST -location [calc_vertical_pad_location 1 5] \ - {sg13g2_IOPad_io_gpio_6} -master sg13g2_IOPadInOut16mA +place_pad \ + -row IO_WEST \ + -location [calc_vertical_pad_location \ + 1 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_6} \ + -master sg13g2_IOPadInOut16mA # IO pin io_gpio_7 -place_pad -row IO_WEST -location [calc_vertical_pad_location 2 5] \ - {sg13g2_IOPad_io_gpio_7} -master sg13g2_IOPadInOut16mA -place_pad -row IO_WEST -location [calc_vertical_pad_location 3 5] \ - {sg13g2_IOPadIOVss_west_3} -master sg13g2_IOPadIOVss -place_pad -row IO_WEST -location [calc_vertical_pad_location 4 5] \ - {sg13g2_IOPadIOVdd_west_4} -master sg13g2_IOPadIOVdd +place_pad \ + -row IO_WEST \ + -location [calc_vertical_pad_location \ + 2 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_7} \ + -master sg13g2_IOPadInOut16mA +place_pad \ + -row IO_WEST \ + -location [calc_vertical_pad_location \ + 3 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPadIOVss_west_3} \ + -master sg13g2_IOPadIOVss +place_pad \ + -row IO_WEST \ + -location [calc_vertical_pad_location \ + 4 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPadIOVdd_west_4} \ + -master sg13g2_IOPadIOVdd # Place Corner Cells and Filler place_corners sg13g2_Corner diff --git a/flow/scripts/floorplan.tcl b/flow/scripts/floorplan.tcl index 94696efbaf..5adda7dd99 100644 --- a/flow/scripts/floorplan.tcl +++ b/flow/scripts/floorplan.tcl @@ -93,9 +93,7 @@ if { [env_var_exists_and_non_empty MAKE_TRACKS] } { make_tracks } -if { [env_var_exists_and_non_empty FOOTPRINT_TCL] } { - log_cmd source $::env(FOOTPRINT_TCL) -} +source_env_var_if_exists FOOTPRINT_TCL # This needs to come before any call to remove_buffers. You could have one # tie driving multiple buffers that drive multiple outputs. @@ -121,14 +119,8 @@ report_units report_units_metric report_metrics 2 "floorplan final" false false -if { [env_var_exists_and_non_empty POST_FLOORPLAN_TCL] } { - log_cmd source $::env(POST_FLOORPLAN_TCL) -} - - -if { [env_var_exists_and_non_empty IO_CONSTRAINTS] } { - log_cmd source $::env(IO_CONSTRAINTS) -} +source_env_var_if_exists POST_FLOORPLAN_TCL +source_env_var_if_exists IO_CONSTRAINTS write_db $::env(RESULTS_DIR)/2_1_floorplan.odb write_sdc -no_timestamp $::env(RESULTS_DIR)/2_1_floorplan.sdc diff --git a/flow/scripts/synth_canonicalize.tcl b/flow/scripts/synth_canonicalize.tcl index 60f64c096b..f7d4c44657 100644 --- a/flow/scripts/synth_canonicalize.tcl +++ b/flow/scripts/synth_canonicalize.tcl @@ -8,9 +8,7 @@ dict for {key value} [env_var_or_empty VERILOG_TOP_PARAMS] { hierarchy -check -top $::env(DESIGN_NAME) -if { [env_var_exists_and_non_empty SYNTH_CANONICALIZE_TCL] } { - log_cmd source $::env(SYNTH_CANONICALIZE_TCL) -} +source_env_var_if_exists SYNTH_CANONICALIZE_TCL # Get rid of unused modules opt_clean -purge diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl index 851d80d620..8c9689ddd0 100644 --- a/flow/scripts/util.tcl +++ b/flow/scripts/util.tcl @@ -216,6 +216,6 @@ proc place_density_with_lb_addon { } { proc source_env_var_if_exists { env_var } { if { [env_var_exists_and_non_empty $env_var] } { - source $::env($env_var) + log_cmd source $::env($env_var) } } From 50213124eb7eb4960bc8c7ccf8102c40f72cb0ce Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Mon, 21 Jul 2025 05:07:02 +0000 Subject: [PATCH 194/198] update designs/gf12/ariane/rules-base.json: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | placeopt__design__instance__area | 226890 | 226083 | Tighten | | detailedroute__route__wirelength | 3723168 | 3662425 | Tighten | | detailedroute__route__drc_errors | 0 | 1 | Failing | | finish__timing__setup__ws | -402.07 | -212.42 | Tighten | | finish__design__instance__area | 228909 | 228519 | Tighten | | finish__timing__wns_percent_delay | -27.26 | -14.79 | Tighten | Signed-off-by: Matt Liberty --- flow/designs/gf12/ariane/rules-base.json | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/flow/designs/gf12/ariane/rules-base.json b/flow/designs/gf12/ariane/rules-base.json index 747bfd0115..3c43ec8b2d 100644 --- a/flow/designs/gf12/ariane/rules-base.json +++ b/flow/designs/gf12/ariane/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 226890, + "value": 226083, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,11 +32,11 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 3723168, + "value": 3662425, "compare": "<=" }, "detailedroute__route__drc_errors": { - "value": 0, + "value": 1, "compare": "<=" }, "detailedroute__antenna__violating__nets": { @@ -48,11 +48,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -402.07, + "value": -212.42, "compare": ">=" }, "finish__design__instance__area": { - "value": 228909, + "value": 228519, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -27.26, + "value": -14.79, "compare": ">=" } } \ No newline at end of file From 86f4763ae04e22c2328521d041e7a8132747dbb3 Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Mon, 21 Jul 2025 07:15:38 -0700 Subject: [PATCH 195/198] Removed tunable attribute from CTS_BUF_LIST Signed-off-by: Jeff Ng --- flow/scripts/variables.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 4c1ab371b4..a183e0d674 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -776,8 +776,6 @@ CTS_BUF_LIST: List of cells used to construct the clock tree. Overrides buffer inference. stages: - cts - tunable: 1 - type: float CTS_CLUSTER_DIAMETER: description: > Maximum diameter (in microns) of sink cluster. From e448a2abcb03e82f2d6d0af546f6690e6536c435 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Fri, 18 Jul 2025 19:27:21 +0000 Subject: [PATCH 196/198] Change configs and metrics for MPL fixes 1. Update metrics for ihp-sg13g2/i2c-gpio-expander | Metric | Old | New | Type | | ------ | --- | --- | ---- | | placeopt__design__instance__count__stdcell | 983 | 965 | Tighten | | cts__design__instance__count__setup_buffer | 86 | 84 | Tighten | | cts__design__instance__count__hold_buffer | 86 | 84 | Tighten | | globalroute__antenna_diodes_count | 156 | 18 | Tighten | | detailedroute__route__wirelength | 42588 | 39121 | Tighten | | detailedroute__antenna_diodes_count | 5 | 22 | Failing | | finish__design__instance__area | 136013 | 135868 | Tighten | | finish__timing__drv__setup_violation_count | 43 | 42 | Tighten | 2. Decrease asap7/aes-block density to make registers closer to each other and avoid CTS high skew; 3. Decrease minimum aspect ratio for sky130hd/uW std cell clusters in MPL. Signed-off-by: Arthur Koucher --- flow/designs/asap7/aes-block/config.mk | 2 +- .../ihp-sg13g2/i2c-gpio-expander/rules-base.json | 16 ++++++++-------- flow/designs/sky130hd/microwatt/config.mk | 3 +++ 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/flow/designs/asap7/aes-block/config.mk b/flow/designs/asap7/aes-block/config.mk index edd4c96a07..08e2b12595 100644 --- a/flow/designs/asap7/aes-block/config.mk +++ b/flow/designs/asap7/aes-block/config.mk @@ -11,7 +11,7 @@ export ABC_AREA = 1 export CORE_UTILIZATION = 20 export CORE_ASPECT_RATIO = 1 export CORE_MARGIN = 2 -export PLACE_DENSITY = 0.60 +export PLACE_DENSITY = 0.53 export BLOCKS ?= aes_rcon aes_sbox export SYNTH_HIERARCHICAL = 1 diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json index 0d62bb9a3a..e848ab6240 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 983, + "value": 965, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 86, + "value": 84, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 86, + "value": 84, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 156, + "value": 18, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 42588, + "value": 39121, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 5, + "value": 22, "compare": "<=" }, "finish__timing__setup__ws": { @@ -52,11 +52,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 136013, + "value": 135868, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 43, + "value": 42, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/sky130hd/microwatt/config.mk b/flow/designs/sky130hd/microwatt/config.mk index 4995d64a26..589df7a899 100644 --- a/flow/designs/sky130hd/microwatt/config.mk +++ b/flow/designs/sky130hd/microwatt/config.mk @@ -33,6 +33,9 @@ export MACRO_BLOCKAGE_HALO = 151 # higher density in order to run. export PLACE_DENSITY = 0.2 +# Extra effort to ease routing: avoid very tall std cell clusters in MPL. +export RTLMP_MIN_AR = 0.40 + # CTS tuning export CTS_BUF_DISTANCE = 600 export SKIP_GATE_CLONING = 1 From cc4407f760058aa203d5b2ab29dc336278859c33 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Mon, 21 Jul 2025 17:29:43 +0000 Subject: [PATCH 197/198] Update metrics for MPL changes gf12/swerv_wrapper | Metric | Old | New | Type | | ------ | --- | --- | ---- | | cts__design__instance__count__hold_buffer | 13650 | 11303 | Tighten | | detailedroute__route__wirelength | 2668710 | 2311628 | Tighten | | finish__timing__drv__hold_violation_count | 521 | 755 | Failing | Signed-off-by: Arthur Koucher --- flow/designs/gf12/swerv_wrapper/rules-base.json | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/flow/designs/gf12/swerv_wrapper/rules-base.json b/flow/designs/gf12/swerv_wrapper/rules-base.json index 41042fe3ee..eccdad7d0f 100644 --- a/flow/designs/gf12/swerv_wrapper/rules-base.json +++ b/flow/designs/gf12/swerv_wrapper/rules-base.json @@ -24,7 +24,7 @@ "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 13650, + "value": 11303, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 2668710, + "value": 2311628, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 521, + "value": 755, "compare": "<=" }, "finish__timing__wns_percent_delay": { From 9a1141567e2e9bcb1ee27e2db0d4eb1a620fce81 Mon Sep 17 00:00:00 2001 From: jeffng-or <177239724+jeffng-or@users.noreply.github.com> Date: Mon, 21 Jul 2025 23:50:00 +0000 Subject: [PATCH 198/198] [BOT] Update yosys submodule Signed-off-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com> --- tools/yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/yosys b/tools/yosys index 60f126cd00..9ed031ddd5 160000 --- a/tools/yosys +++ b/tools/yosys @@ -1 +1 @@ -Subproject commit 60f126cd00c94892782470192d6c9f7abebe7c05 +Subproject commit 9ed031ddd588442f22be13ce608547a5809b62f0